All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Matthew Auld <matthew.auld@intel.com>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 7/8] drm/i915: fixup the initial fb base on DG1
Date: Mon, 7 Mar 2022 20:41:15 +0200	[thread overview]
Message-ID: <YiZRy78PW2n2I/HB@intel.com> (raw)
In-Reply-To: <476964f2-772f-b734-1a17-8e65c74b309c@intel.com>

On Mon, Mar 07, 2022 at 06:26:32PM +0000, Matthew Auld wrote:
> On 07/03/2022 17:06, Ville Syrjälä wrote:
> > On Mon, Mar 07, 2022 at 10:32:36AM +0000, Matthew Auld wrote:
> >> On 04/03/2022 19:33, Ville Syrjälä wrote:
> >>> On Fri, Mar 04, 2022 at 05:23:32PM +0000, Matthew Auld wrote:
> >>>> The offset we get looks to be the exact start of DSM, but the
> >>>> inital_plane_vma expects the address to be relative.
> >>>>
> >>>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> >>>> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> >>>> ---
> >>>>    .../drm/i915/display/intel_plane_initial.c    | 22 +++++++++++++++----
> >>>>    1 file changed, 18 insertions(+), 4 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> >>>> index f797fcef18fc..b39d3a8dfe45 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> >>>> @@ -56,10 +56,24 @@ initial_plane_vma(struct drm_i915_private *i915,
> >>>>    	if (!mem || plane_config->size == 0)
> >>>>    		return NULL;
> >>>>    
> >>>> -	base = round_down(plane_config->base,
> >>>> -			  I915_GTT_MIN_ALIGNMENT);
> >>>> -	size = round_up(plane_config->base + plane_config->size,
> >>>> -			mem->min_page_size);
> >>>> +	base = plane_config->base;
> >>>> +	if (IS_DGFX(i915)) {
> >>>> +		/*
> >>>> +		 * On discrete the base address should be somewhere in LMEM, but
> >>>> +		 * depending on the size of LMEM the base address might
> >>>> +		 * intersect with the start of DSM, like on DG1, in which case
> >>>> +		 * we need the relative address. In such cases we might also
> >>>> +		 * need to choose between inital fb vs fbc, if space is limited.
> >>>> +		 *
> >>>> +		 * On future discrete HW, like DG2, we should be able to just
> >>>> +		 * allocate directly from LMEM, due to larger LMEM size.
> >>>> +		 */
> >>>> +		if (base >= i915->dsm.start)
> >>>> +			base -= i915->dsm.start;
> >>>
> >>> Subsequent code expects the object to actually be inside stolen.
> >>> If that is not the case we should just give up.
> >>
> >> Thanks for taking a look at this. Is that subsequent code outside
> >> initial_plane_vma()? In the next patch this is now using LMEM directly
> >> for dg2. Would that blow up somewhere else?
> > 
> > It uses i915_gem_object_create_stolen_for_preallocated() which assumes
> > the stuff is inside stolen.
> 
> At the start of the series that gets ripped out and replaced with 
> i915_gem_object_create_region_at(), where we can now just pass in the 
> intel_memory_region, and the backend hopefully takes care of the rest.

Why? Is the BIOS no longer allocating its fbs from stolen?

> 
> > 
> >>> The fact that we fail to confirm any of that on integrated
> >>> parts has always bugged me, but not enough to actually do
> >>> anything about it. Such a check would be somewhat more involved
> >>> since we'd have to look at the PTEs. But on discrete sounds like
> >>> we can get away with a trivial check.
> >>
> >> Which PTEs?
> > 
> > The PTEs the plane is actually using. We have no idea where they
> > actually point to and just assume they represent a 1:1 mapping of
> > stolen.
> > 
> > I suppose with lmem we'll just start assuming a 1:1 mapping of
> > the whole lmem rather than just stolen.
> 
> So IIUC the base that we read is actually some GGTT address(I guess it 
> comes pre-programmed or something?), and that hopefully 1:1 maps to 
> stolen. Ok, so as you say, I guess we only want to subtract the 
> dsm.start for the physical allocation, and not the GGTT address, when 
> dealing with stolen lmem.
> 
> > 

-- 
Ville Syrjälä
Intel

WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Matthew Auld <matthew.auld@intel.com>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 7/8] drm/i915: fixup the initial fb base on DG1
Date: Mon, 7 Mar 2022 20:41:15 +0200	[thread overview]
Message-ID: <YiZRy78PW2n2I/HB@intel.com> (raw)
In-Reply-To: <476964f2-772f-b734-1a17-8e65c74b309c@intel.com>

On Mon, Mar 07, 2022 at 06:26:32PM +0000, Matthew Auld wrote:
> On 07/03/2022 17:06, Ville Syrjälä wrote:
> > On Mon, Mar 07, 2022 at 10:32:36AM +0000, Matthew Auld wrote:
> >> On 04/03/2022 19:33, Ville Syrjälä wrote:
> >>> On Fri, Mar 04, 2022 at 05:23:32PM +0000, Matthew Auld wrote:
> >>>> The offset we get looks to be the exact start of DSM, but the
> >>>> inital_plane_vma expects the address to be relative.
> >>>>
> >>>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> >>>> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> >>>> ---
> >>>>    .../drm/i915/display/intel_plane_initial.c    | 22 +++++++++++++++----
> >>>>    1 file changed, 18 insertions(+), 4 deletions(-)
> >>>>
> >>>> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> >>>> index f797fcef18fc..b39d3a8dfe45 100644
> >>>> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> >>>> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> >>>> @@ -56,10 +56,24 @@ initial_plane_vma(struct drm_i915_private *i915,
> >>>>    	if (!mem || plane_config->size == 0)
> >>>>    		return NULL;
> >>>>    
> >>>> -	base = round_down(plane_config->base,
> >>>> -			  I915_GTT_MIN_ALIGNMENT);
> >>>> -	size = round_up(plane_config->base + plane_config->size,
> >>>> -			mem->min_page_size);
> >>>> +	base = plane_config->base;
> >>>> +	if (IS_DGFX(i915)) {
> >>>> +		/*
> >>>> +		 * On discrete the base address should be somewhere in LMEM, but
> >>>> +		 * depending on the size of LMEM the base address might
> >>>> +		 * intersect with the start of DSM, like on DG1, in which case
> >>>> +		 * we need the relative address. In such cases we might also
> >>>> +		 * need to choose between inital fb vs fbc, if space is limited.
> >>>> +		 *
> >>>> +		 * On future discrete HW, like DG2, we should be able to just
> >>>> +		 * allocate directly from LMEM, due to larger LMEM size.
> >>>> +		 */
> >>>> +		if (base >= i915->dsm.start)
> >>>> +			base -= i915->dsm.start;
> >>>
> >>> Subsequent code expects the object to actually be inside stolen.
> >>> If that is not the case we should just give up.
> >>
> >> Thanks for taking a look at this. Is that subsequent code outside
> >> initial_plane_vma()? In the next patch this is now using LMEM directly
> >> for dg2. Would that blow up somewhere else?
> > 
> > It uses i915_gem_object_create_stolen_for_preallocated() which assumes
> > the stuff is inside stolen.
> 
> At the start of the series that gets ripped out and replaced with 
> i915_gem_object_create_region_at(), where we can now just pass in the 
> intel_memory_region, and the backend hopefully takes care of the rest.

Why? Is the BIOS no longer allocating its fbs from stolen?

> 
> > 
> >>> The fact that we fail to confirm any of that on integrated
> >>> parts has always bugged me, but not enough to actually do
> >>> anything about it. Such a check would be somewhat more involved
> >>> since we'd have to look at the PTEs. But on discrete sounds like
> >>> we can get away with a trivial check.
> >>
> >> Which PTEs?
> > 
> > The PTEs the plane is actually using. We have no idea where they
> > actually point to and just assume they represent a 1:1 mapping of
> > stolen.
> > 
> > I suppose with lmem we'll just start assuming a 1:1 mapping of
> > the whole lmem rather than just stolen.
> 
> So IIUC the base that we read is actually some GGTT address(I guess it 
> comes pre-programmed or something?), and that hopefully 1:1 maps to 
> stolen. Ok, so as you say, I guess we only want to subtract the 
> dsm.start for the physical allocation, and not the GGTT address, when 
> dealing with stolen lmem.
> 
> > 

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2022-03-07 18:41 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-04 17:23 [PATCH 0/8] Some more bits for small BAR enabling Matthew Auld
2022-03-04 17:23 ` [Intel-gfx] " Matthew Auld
2022-03-04 17:23 ` [PATCH 1/8] drm/i915/lmem: don't treat small BAR as an error Matthew Auld
2022-03-04 17:23   ` [Intel-gfx] " Matthew Auld
2022-03-04 17:23 ` [PATCH 2/8] drm/i915/stolen: " Matthew Auld
2022-03-04 17:23   ` [Intel-gfx] " Matthew Auld
2022-03-04 17:23 ` [PATCH 3/8] drm/i915: add i915_gem_object_create_region_at() Matthew Auld
2022-03-04 17:23   ` [Intel-gfx] " Matthew Auld
2022-03-04 17:23 ` [PATCH 4/8] drm/i915/buddy: tweak CONTIGUOUS rounding Matthew Auld
2022-03-04 17:23   ` [Intel-gfx] " Matthew Auld
2022-03-04 17:23 ` [PATCH 5/8] drm/i915/ttm: wire up the object offset Matthew Auld
2022-03-04 17:23   ` [Intel-gfx] " Matthew Auld
2022-03-04 17:23 ` [PATCH 6/8] drm/i915/display: Check mappable aperture when pinning preallocated vma Matthew Auld
2022-03-04 17:23   ` [Intel-gfx] " Matthew Auld
2022-03-04 17:23 ` [PATCH 7/8] drm/i915: fixup the initial fb base on DG1 Matthew Auld
2022-03-04 17:23   ` [Intel-gfx] " Matthew Auld
2022-03-04 19:33   ` Ville Syrjälä
2022-03-04 19:33     ` [Intel-gfx] " Ville Syrjälä
2022-03-07 10:32     ` Matthew Auld
2022-03-07 10:32       ` [Intel-gfx] " Matthew Auld
2022-03-07 17:06       ` Ville Syrjälä
2022-03-07 17:06         ` [Intel-gfx] " Ville Syrjälä
2022-03-07 18:26         ` Matthew Auld
2022-03-07 18:26           ` [Intel-gfx] " Matthew Auld
2022-03-07 18:41           ` Ville Syrjälä [this message]
2022-03-07 18:41             ` Ville Syrjälä
2022-03-07 19:19             ` Matthew Auld
2022-03-04 17:23 ` [PATCH 8/8] drm/i915: fixup the initial fb on DG2 Matthew Auld
2022-03-04 17:23   ` [Intel-gfx] " Matthew Auld
2022-03-04 19:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Some more bits for small BAR enabling Patchwork
2022-03-04 19:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-04 19:56 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=YiZRy78PW2n2I/HB@intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=matthew.auld@intel.com \
    --cc=thomas.hellstrom@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.