[PATCH v4 0/9] serial: 8250: dw: RZN1 DMA support

[PATCH v4 0/9] serial: 8250: dw: RZN1 DMA support

[Miquel Raynal]

Hello,

Support for the RZN1 DMA engine allows us adapt a little bit the 8250 DW
UART driver with to bring DMA support for this SoC.

This short series applies on top of the series bringing RZN1 DMA
support, currently on its v5, see [1]. Technically speaking, only the DT
patch needs to be applied after [1]. The other patches can come in at
any moment, because if no "dmas" property is provided in the DT, DMA
support will simply be ignored.

[1] https://lore.kernel.org/dmaengine/20220315191255.221473-1-miquel.raynal@bootlin.com/T/#m0ef3323abce3eec961e142bf2fb35e95b9045fc5

Thanks,
Miquèl

Changes in v4:
* Squashed the patch changing the quirks type with the patch introducing
  the pdata structure. This way I don't need to go through the uintptr_t
  step. 
* Added a pdata stub to the DW compatible. This way "if (pdata)" checks
  are no longer needed and we can avoid ternary operators disliked by
  Greg.
* Saved the pdata structure pointer inside the per-device structure to
  avoid calling the same device property heplper over and over again. 
* Changed the style a bit to fit Andy's requirements.

Changes in v3:
* Added Geert's Reviewed-by's.
* Used forward declaration in dwlib.h when relevant.
* Reordered the headers when necessary.
* Added a patch changing the quirks type from unsigned long to unsigned
  int as advised by Andy.
* s/up->port.dev/p->dev/ when relevant.
* Added a debug message in dwlib when no CPR is available.
* Dropped the CPR_DMA_EXTRA bit addition: we assume DMA is there.
* Changed the prefix of certain definitions.

Changes in v2:
* Rebased on top of Emil's patches. Added platform data structures
  instead of raw quirk integers in order to provide a CPR value.
* Added includes in dwlib.h even though it's not particularly useful, it
  may help preventing a build error later on if we ever decide to include
  this file from another location.
* Dropped the call to ->tx_dma and instead implemented a callback that
  can be called from serial8250_tx/rx_dma.
* Used the device API instead of the of API.
* Changed the logic about DMA capabilities to avoid breaking existing
  designs.
* Introduced a new quirk related to the flow-control feature of the
  RZ/N1 version of the UART controller when used with DMA.
* Re-arranged the entire series as advised by Andy and Geert.
* Added several preparation patches to ease the review of various
  functional changes.

Miquel Raynal (6):
  serial: 8250: dw: Use the device API
  serial: 8250: dw: Create a more generic platform data structure
  serial: 8250: dw: Allow to use a fallback CPR value if not synthesized
  serial: 8250: dma: Allow driver operations before starting DMA
    transfers
  serial: 8250: dw: Introduce an rx_timeout variable in the IRQ path
  ARM: dts: r9a06g032: Fill the UART DMA properties

Phil Edworthy (3):
  serial: 8250: dw: Move definitions to the shared header
  serial: 8250: dw: Add support for DMA flow controlling devices
  serial: 8250: dw: Improve RZN1 support

 arch/arm/boot/dts/r9a06g032.dtsi     |  15 ++++
 drivers/tty/serial/8250/8250.h       |  18 ++++
 drivers/tty/serial/8250/8250_dma.c   |   4 +
 drivers/tty/serial/8250/8250_dw.c    | 123 ++++++++++++++++++++-------
 drivers/tty/serial/8250/8250_dwlib.c |  12 ++-
 drivers/tty/serial/8250/8250_dwlib.h |  32 +++++++
 6 files changed, 172 insertions(+), 32 deletions(-)

-- 
2.27.0

[PATCH v4 1/9] serial: 8250: dw: Move definitions to the shared header

[Miquel Raynal]

From: Phil Edworthy <phil.edworthy@renesas.com>

Move the per-device structure and a helper out of the main .c file, into
a shared header as they will both be reused from another .c file.

There is no functional change.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
[miquel.raynal@bootlin.com: Extracted from a bigger change]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/tty/serial/8250/8250_dw.c    | 21 ---------------------
 drivers/tty/serial/8250/8250_dwlib.h | 26 ++++++++++++++++++++++++++
 2 files changed, 26 insertions(+), 21 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 96a62e95726b..1666041513a5 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -42,27 +42,6 @@
 #define DW_UART_QUIRK_ARMADA_38X	BIT(1)
 #define DW_UART_QUIRK_SKIP_SET_RATE	BIT(2)
 
-struct dw8250_data {
-	struct dw8250_port_data	data;
-
-	u8			usr_reg;
-	int			msr_mask_on;
-	int			msr_mask_off;
-	struct clk		*clk;
-	struct clk		*pclk;
-	struct notifier_block	clk_notifier;
-	struct work_struct	clk_work;
-	struct reset_control	*rst;
-
-	unsigned int		skip_autocfg:1;
-	unsigned int		uart_16550_compatible:1;
-};
-
-static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
-{
-	return container_of(data, struct dw8250_data, data);
-}
-
 static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
 {
 	return container_of(nb, struct dw8250_data, clk_notifier);
diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
index 83d528e5cc21..72e7dbcccad0 100644
--- a/drivers/tty/serial/8250/8250_dwlib.h
+++ b/drivers/tty/serial/8250/8250_dwlib.h
@@ -1,10 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /* Synopsys DesignWare 8250 library header file. */
 
+#include <linux/notifier.h>
 #include <linux/types.h>
+#include <linux/workqueue.h>
 
 #include "8250.h"
 
+struct clk;
+struct reset_control;
+
 struct dw8250_port_data {
 	/* Port properties */
 	int			line;
@@ -16,5 +21,26 @@ struct dw8250_port_data {
 	u8			dlf_size;
 };
 
+struct dw8250_data {
+	struct dw8250_port_data	data;
+
+	u8			usr_reg;
+	int			msr_mask_on;
+	int			msr_mask_off;
+	struct clk		*clk;
+	struct clk		*pclk;
+	struct notifier_block	clk_notifier;
+	struct work_struct	clk_work;
+	struct reset_control	*rst;
+
+	unsigned int		skip_autocfg:1;
+	unsigned int		uart_16550_compatible:1;
+};
+
 void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old);
 void dw8250_setup_port(struct uart_port *p);
+
+static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
+{
+	return container_of(data, struct dw8250_data, data);
+}
-- 
2.27.0

[PATCH v4 2/9] serial: 8250: dw: Use the device API

[Miquel Raynal]

Use the device API instead of the of_* API.
While at it move this operation outside of the if block to reduce the
indentation level.

Cc: Emil Renner Berthing <kernel@esmil.dk>
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/tty/serial/8250/8250_dw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 1666041513a5..b6238b9bf0b2 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -371,9 +371,9 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 {
 	struct device_node *np = p->dev->of_node;
+	unsigned long quirks = (unsigned long)device_get_match_data(p->dev);
 
 	if (np) {
-		unsigned long quirks = (unsigned long)of_device_get_match_data(p->dev);
 		int id;
 
 		/* get index of serial line, if found in DT aliases */
-- 
2.27.0

[PATCH v4 3/9] serial: 8250: dw: Create a more generic platform data structure

[Miquel Raynal]

Before adding more platform data information, let's turn the quirks
information as being a member of a wider structure. More fields will be
added later.

At the same time, change the quirks type to unsigned int, as its size
won't change between setups and we don't really need this variable to be
more than a few bits wide anyway.

Provide a stub to the compatibles without quirks to simplify handling.
Keep two different empty structure for the base DW compatible and the
Renesas one because the latter will soon be fulfilled anyway.

Cc: Emil Renner Berthing <kernel@esmil.dk>
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 drivers/tty/serial/8250/8250_dw.c    | 32 ++++++++++++++++++++++------
 drivers/tty/serial/8250/8250_dwlib.h |  5 +++++
 2 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index b6238b9bf0b2..70a843e31ffd 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -19,6 +19,7 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/platform_device.h>
+#include <linux/property.h>
 #include <linux/workqueue.h>
 #include <linux/notifier.h>
 #include <linux/slab.h>
@@ -371,7 +372,7 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 {
 	struct device_node *np = p->dev->of_node;
-	unsigned long quirks = (unsigned long)device_get_match_data(p->dev);
+	unsigned int quirks = data->pdata->quirks;
 
 	if (np) {
 		int id;
@@ -462,6 +463,7 @@ static int dw8250_probe(struct platform_device *pdev)
 
 	data->data.dma.fn = dw8250_fallback_dma_filter;
 	data->usr_reg = DW_UART_USR;
+	data->pdata = device_get_match_data(p->dev);
 	p->private_data = &data->data;
 
 	data->uart_16550_compatible = device_property_read_bool(dev,
@@ -678,13 +680,29 @@ static const struct dev_pm_ops dw8250_pm_ops = {
 	SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
 };
 
+static const struct dw8250_platform_data dw8250_dw_apb = {};
+
+static const struct dw8250_platform_data dw8250_octeon_3860_data = {
+	.quirks = DW_UART_QUIRK_OCTEON,
+};
+
+static const struct dw8250_platform_data dw8250_armada_38x_data = {
+	.quirks = DW_UART_QUIRK_ARMADA_38X,
+};
+
+static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {};
+
+static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
+	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
+};
+
 static const struct of_device_id dw8250_of_match[] = {
-	{ .compatible = "snps,dw-apb-uart" },
-	{ .compatible = "cavium,octeon-3860-uart", .data = (void *)DW_UART_QUIRK_OCTEON },
-	{ .compatible = "marvell,armada-38x-uart", .data = (void *)DW_UART_QUIRK_ARMADA_38X },
-	{ .compatible = "renesas,rzn1-uart" },
-	{ .compatible = "starfive,jh7100-hsuart",  .data = (void *)DW_UART_QUIRK_SKIP_SET_RATE },
-	{ .compatible = "starfive,jh7100-uart",    .data = (void *)DW_UART_QUIRK_SKIP_SET_RATE },
+	{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
+	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
+	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
+	{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
+	{ .compatible = "starfive,jh7100-hsuart", .data = &dw8250_starfive_jh7100_data },
+	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
 	{ /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, dw8250_of_match);
diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
index 72e7dbcccad0..68bb81bee660 100644
--- a/drivers/tty/serial/8250/8250_dwlib.h
+++ b/drivers/tty/serial/8250/8250_dwlib.h
@@ -21,8 +21,13 @@ struct dw8250_port_data {
 	u8			dlf_size;
 };
 
+struct dw8250_platform_data {
+	unsigned int quirks;
+};
+
 struct dw8250_data {
 	struct dw8250_port_data	data;
+	const struct dw8250_platform_data *pdata;
 
 	u8			usr_reg;
 	int			msr_mask_on;
-- 
2.27.0

[PATCH v4 4/9] serial: 8250: dw: Allow to use a fallback CPR value if not synthesized

[Miquel Raynal]

DW UART controllers can be synthesized without the CPR register.
In this case, allow to the platform information to provide a CPR value.

Co-developed-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/tty/serial/8250/8250_dwlib.c | 12 +++++++++---
 drivers/tty/serial/8250/8250_dwlib.h |  1 +
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c
index 622d3b0d89e7..6ec59b64f8bc 100644
--- a/drivers/tty/serial/8250/8250_dwlib.c
+++ b/drivers/tty/serial/8250/8250_dwlib.c
@@ -5,6 +5,7 @@
 #include <linux/device.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/property.h>
 #include <linux/serial_8250.h>
 #include <linux/serial_core.h>
 
@@ -89,6 +90,8 @@ EXPORT_SYMBOL_GPL(dw8250_do_set_termios);
 
 void dw8250_setup_port(struct uart_port *p)
 {
+	struct dw8250_port_data *pd = p->private_data;
+	struct dw8250_data *data = to_dw8250_data(pd);
 	struct uart_8250_port *up = up_to_u8250p(p);
 	u32 reg;
 
@@ -108,14 +111,17 @@ void dw8250_setup_port(struct uart_port *p)
 	dw8250_writel_ext(p, DW_UART_DLF, 0);
 
 	if (reg) {
-		struct dw8250_port_data *d = p->private_data;
-
-		d->dlf_size = fls(reg);
+		pd->dlf_size = fls(reg);
 		p->get_divisor = dw8250_get_divisor;
 		p->set_divisor = dw8250_set_divisor;
 	}
 
 	reg = dw8250_readl_ext(p, DW_UART_CPR);
+	if (!reg) {
+		reg = data->pdata->cpr;
+		dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg);
+	}
+
 	if (!reg)
 		return;
 
diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
index 68bb81bee660..5bd534825414 100644
--- a/drivers/tty/serial/8250/8250_dwlib.h
+++ b/drivers/tty/serial/8250/8250_dwlib.h
@@ -23,6 +23,7 @@ struct dw8250_port_data {
 
 struct dw8250_platform_data {
 	unsigned int quirks;
+	u32 cpr;
 };
 
 struct dw8250_data {
-- 
2.27.0

[PATCH v4 5/9] serial: 8250: dma: Allow driver operations before starting DMA transfers

[Miquel Raynal]

One situation where this could be used is when configuring the UART
controller to be the DMA flow controller. This is a typical case where
the driver might need to program a few more registers before starting a
DMA transfer. Provide the necessary infrastructure to support this
case.

Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/tty/serial/8250/8250.h     | 18 ++++++++++++++++++
 drivers/tty/serial/8250/8250_dma.c |  4 ++++
 2 files changed, 22 insertions(+)

diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h
index db784ace25d8..d19f24e4d13e 100644
--- a/drivers/tty/serial/8250/8250.h
+++ b/drivers/tty/serial/8250/8250.h
@@ -17,6 +17,8 @@
 struct uart_8250_dma {
 	int (*tx_dma)(struct uart_8250_port *p);
 	int (*rx_dma)(struct uart_8250_port *p);
+	void (*prepare_tx_dma)(struct uart_8250_port *p);
+	void (*prepare_rx_dma)(struct uart_8250_port *p);
 
 	/* Filter function */
 	dma_filter_fn		fn;
@@ -301,6 +303,22 @@ extern int serial8250_rx_dma(struct uart_8250_port *);
 extern void serial8250_rx_dma_flush(struct uart_8250_port *);
 extern int serial8250_request_dma(struct uart_8250_port *);
 extern void serial8250_release_dma(struct uart_8250_port *);
+
+static inline void serial8250_do_prepare_tx_dma(struct uart_8250_port *p)
+{
+	struct uart_8250_dma *dma = p->dma;
+
+	if (dma->prepare_tx_dma)
+		dma->prepare_tx_dma(p);
+}
+
+static inline void serial8250_do_prepare_rx_dma(struct uart_8250_port *p)
+{
+	struct uart_8250_dma *dma = p->dma;
+
+	if (dma->prepare_rx_dma)
+		dma->prepare_rx_dma(p);
+}
 #else
 static inline int serial8250_tx_dma(struct uart_8250_port *p)
 {
diff --git a/drivers/tty/serial/8250/8250_dma.c b/drivers/tty/serial/8250/8250_dma.c
index 890fa7ddaa7f..558d3a2ac65b 100644
--- a/drivers/tty/serial/8250/8250_dma.c
+++ b/drivers/tty/serial/8250/8250_dma.c
@@ -77,6 +77,8 @@ int serial8250_tx_dma(struct uart_8250_port *p)
 
 	dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 
+	serial8250_do_prepare_tx_dma(p);
+
 	desc = dmaengine_prep_slave_single(dma->txchan,
 					   dma->tx_addr + xmit->tail,
 					   dma->tx_size, DMA_MEM_TO_DEV,
@@ -114,6 +116,8 @@ int serial8250_rx_dma(struct uart_8250_port *p)
 	if (dma->rx_running)
 		return 0;
 
+	serial8250_do_prepare_rx_dma(p);
+
 	desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
 					   dma->rx_size, DMA_DEV_TO_MEM,
 					   DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
-- 
2.27.0

[PATCH v4 6/9] serial: 8250: dw: Introduce an rx_timeout variable in the IRQ path

[Miquel Raynal]

In a next change we are going to need the same Rx timeout condition as
we already have in the IRQ handling code. Let's just create a boolean to
clarify what this operation does before reusing it.

There is no functional change.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/tty/serial/8250/8250_dw.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 70a843e31ffd..a156c6d2f866 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -223,6 +223,7 @@ static int dw8250_handle_irq(struct uart_port *p)
 	struct uart_8250_port *up = up_to_u8250p(p);
 	struct dw8250_data *d = to_dw8250_data(p->private_data);
 	unsigned int iir = p->serial_in(p, UART_IIR);
+	bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
 	unsigned int status;
 	unsigned long flags;
 
@@ -236,7 +237,7 @@ static int dw8250_handle_irq(struct uart_port *p)
 	 * This problem has only been observed so far when not in DMA mode
 	 * so we limit the workaround only to non-DMA mode.
 	 */
-	if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
+	if (!up->dma && rx_timeout) {
 		spin_lock_irqsave(&p->lock, flags);
 		status = p->serial_in(p, UART_LSR);
 
-- 
2.27.0

[PATCH v4 7/9] serial: 8250: dw: Add support for DMA flow controlling devices

[Miquel Raynal]

From: Phil Edworthy <phil.edworthy@renesas.com>

DW based controllers like the one on Renesas RZ/N1 must be programmed as
flow controllers when using DMA.

* Table 11.45 of the system manual, "Flow Control Combinations", states
  that using UART with DMA requires setting the DMA in the peripheral
  flow controller mode regardless of the direction.

* Chapter 11.6.1.3 of the system manual, "Basic Interface Definitions",
  explains that the burst size in the above case must be configured in
  the peripheral's register DEST/SRC_BURST_SIZE.

Experiments shown that upon Rx timeout, the DMA transaction needed to be
manually cleared as well.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Co-developed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/tty/serial/8250/8250_dw.c | 64 +++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index a156c6d2f866..977a473535e8 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -34,14 +34,26 @@
 
 /* Offsets for the DesignWare specific registers */
 #define DW_UART_USR	0x1f /* UART Status Register */
+#define DW_UART_DMASA	0xa8 /* DMA Software Ack */
+
+#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
+#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
 
 /* DesignWare specific register fields */
 #define DW_UART_MCR_SIRE		BIT(6)
 
+/* Renesas specific register fields */
+#define RZN1_UART_xDMACR_DMA_EN		BIT(0)
+#define RZN1_UART_xDMACR_1_WORD_BURST	(0 << 1)
+#define RZN1_UART_xDMACR_4_WORD_BURST	(1 << 1)
+#define RZN1_UART_xDMACR_8_WORD_BURST	(3 << 1)
+#define RZN1_UART_xDMACR_BLK_SZ(x)	((x) << 3)
+
 /* Quirks */
 #define DW_UART_QUIRK_OCTEON		BIT(0)
 #define DW_UART_QUIRK_ARMADA_38X	BIT(1)
 #define DW_UART_QUIRK_SKIP_SET_RATE	BIT(2)
+#define DW_UART_QUIRK_IS_DMA_FC		BIT(3)
 
 static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
 {
@@ -224,6 +236,7 @@ static int dw8250_handle_irq(struct uart_port *p)
 	struct dw8250_data *d = to_dw8250_data(p->private_data);
 	unsigned int iir = p->serial_in(p, UART_IIR);
 	bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
+	unsigned int quirks = d->pdata->quirks;
 	unsigned int status;
 	unsigned long flags;
 
@@ -247,6 +260,15 @@ static int dw8250_handle_irq(struct uart_port *p)
 		spin_unlock_irqrestore(&p->lock, flags);
 	}
 
+	/* Manually stop the Rx DMA transfer when acting as flow controller */
+	if (up->dma && up->dma->rx_running && rx_timeout && quirks & DW_UART_QUIRK_IS_DMA_FC) {
+		status = p->serial_in(p, UART_LSR);
+		if (status & (UART_LSR_DR | UART_LSR_BI)) {
+			writel(0, p->membase + RZN1_UART_RDMACR);
+			writel(1, p->membase + DW_UART_DMASA);
+		}
+	}
+
 	if (serial8250_handle_irq(p, iir))
 		return 1;
 
@@ -370,6 +392,42 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
 	return param == chan->device->dev;
 }
 
+static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
+{
+	if (max_burst >= 8)
+		return RZN1_UART_xDMACR_8_WORD_BURST;
+	else if (max_burst >= 4)
+		return RZN1_UART_xDMACR_4_WORD_BURST;
+	else
+		return RZN1_UART_xDMACR_1_WORD_BURST;
+}
+
+static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
+{
+	struct uart_port *up = &p->port;
+	struct uart_8250_dma *dma = p->dma;
+	u32 val;
+
+	writel(0, up->membase + RZN1_UART_TDMACR);
+	val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
+	      RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
+	      RZN1_UART_xDMACR_DMA_EN;
+	writel(val, up->membase + RZN1_UART_TDMACR);
+}
+
+static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
+{
+	struct uart_port *up = &p->port;
+	struct uart_8250_dma *dma = p->dma;
+	u32 val;
+
+	writel(0, up->membase + RZN1_UART_RDMACR);
+	val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
+	      RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
+	      RZN1_UART_xDMACR_DMA_EN;
+	writel(val, up->membase + RZN1_UART_RDMACR);
+}
+
 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 {
 	struct device_node *np = p->dev->of_node;
@@ -403,6 +461,12 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
 			p->serial_out = dw8250_serial_out38x;
 		if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
 			p->set_termios = dw8250_do_set_termios;
+		if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
+			data->data.dma.txconf.device_fc = 1;
+			data->data.dma.rxconf.device_fc = 1;
+			data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
+			data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
+		}
 
 	} else if (acpi_dev_present("APMC0D08", NULL, -1)) {
 		p->iotype = UPIO_MEM32;
-- 
2.27.0

[PATCH v4 8/9] serial: 8250: dw: Improve RZN1 support

[Miquel Raynal]

From: Phil Edworthy <phil.edworthy@renesas.com>

Renesas RZ/N1 SoC features a slightly modified DW UART.

On this SoC, the CPR register value is known but not synthetized in
hardware. We hence need to provide a CPR value in the platform
data. This version of the controller also relies on acting as flow
controller when using DMA, so we need to provide the
"is dma flow controller" quirk.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Co-developed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 drivers/tty/serial/8250/8250_dw.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
index 977a473535e8..195aa4516b2b 100644
--- a/drivers/tty/serial/8250/8250_dw.c
+++ b/drivers/tty/serial/8250/8250_dw.c
@@ -755,7 +755,10 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = {
 	.quirks = DW_UART_QUIRK_ARMADA_38X,
 };
 
-static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {};
+static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
+	.quirks = DW_UART_QUIRK_IS_DMA_FC,
+	.cpr = 0x00012f32,
+};
 
 static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
 	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
-- 
2.27.0

[PATCH v4 9/9] ARM: dts: r9a06g032: Fill the UART DMA properties

[Miquel Raynal]

UART 0 to 2 do not have DMA support, while UART 3 to 7 do.

Fill the "dmas" and "dma-names" properties for each of these nodes.

Please mind that these nodes go through the dmamux node which will
redirect the requests to the right DMA controller. The first 4 cells of
the "dmas" properties will be transferred as-is to the DMA
controllers. The last 2 cells are consumed by the dmamux. Which means
cell 0 and 4 are almost redundant, one giving the controller request ID
and the other the dmamux channel which is a 1:1 translation of the
request IDs, shifted by 16 when pointing to the second DMA controller.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 arch/arm/boot/dts/r9a06g032.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
index 804f2d6f416f..aa447e2622e0 100644
--- a/arch/arm/boot/dts/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -128,6 +128,9 @@ uart3: serial@50000000 {
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
 			clock-names = "baudclk", "apb_pclk";
+			dmas =  <&dmamux 0 0 0 0 0 1>,
+				<&dmamux 1 0 0 0 1 1>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
@@ -139,6 +142,9 @@ uart4: serial@50001000 {
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
 			clock-names = "baudclk", "apb_pclk";
+			dmas =  <&dmamux 2 0 0 0 2 1>,
+				<&dmamux 3 0 0 0 3 1>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
@@ -150,6 +156,9 @@ uart5: serial@50002000 {
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
 			clock-names = "baudclk", "apb_pclk";
+			dmas =  <&dmamux 4 0 0 0 4 1>,
+				<&dmamux 5 0 0 0 5 1>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
@@ -161,6 +170,9 @@ uart6: serial@50003000 {
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
 			clock-names = "baudclk", "apb_pclk";
+			dmas =  <&dmamux 6 0 0 0 6 1>,
+				<&dmamux 7 0 0 0 7 1>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
@@ -172,6 +184,9 @@ uart7: serial@50004000 {
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
 			clock-names = "baudclk", "apb_pclk";
+			dmas =  <&dmamux 4 0 0 0 20 1>,
+				<&dmamux 5 0 0 0 21 1>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 		};
 
-- 
2.27.0

Re: [PATCH v4 2/9] serial: 8250: dw: Use the device API

[Andy Shevchenko]

On Wed, Mar 30, 2022 at 03:20:31PM +0200, Miquel Raynal wrote:
> Use the device API instead of the of_* API.
> While at it move this operation outside of the if block to reduce the
> indentation level.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

> Cc: Emil Renner Berthing <kernel@esmil.dk>
> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/tty/serial/8250/8250_dw.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 1666041513a5..b6238b9bf0b2 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -371,9 +371,9 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
>  static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
>  {
>  	struct device_node *np = p->dev->of_node;
> +	unsigned long quirks = (unsigned long)device_get_match_data(p->dev);
>  
>  	if (np) {
> -		unsigned long quirks = (unsigned long)of_device_get_match_data(p->dev);
>  		int id;
>  
>  		/* get index of serial line, if found in DT aliases */
> -- 
> 2.27.0
> 

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 3/9] serial: 8250: dw: Create a more generic platform data structure

[Andy Shevchenko]

On Wed, Mar 30, 2022 at 03:20:32PM +0200, Miquel Raynal wrote:
> Before adding more platform data information, let's turn the quirks
> information as being a member of a wider structure. More fields will be
> added later.
> 
> At the same time, change the quirks type to unsigned int, as its size
> won't change between setups and we don't really need this variable to be
> more than a few bits wide anyway.
> 
> Provide a stub to the compatibles without quirks to simplify handling.
> Keep two different empty structure for the base DW compatible and the
> Renesas one because the latter will soon be fulfilled anyway.

I'm almost fine with it,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

Please, see below remarks.

> Cc: Emil Renner Berthing <kernel@esmil.dk>
> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  drivers/tty/serial/8250/8250_dw.c    | 32 ++++++++++++++++++++++------
>  drivers/tty/serial/8250/8250_dwlib.h |  5 +++++
>  2 files changed, 30 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index b6238b9bf0b2..70a843e31ffd 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -19,6 +19,7 @@
>  #include <linux/of_irq.h>
>  #include <linux/of_platform.h>
>  #include <linux/platform_device.h>
> +#include <linux/property.h>
>  #include <linux/workqueue.h>
>  #include <linux/notifier.h>
>  #include <linux/slab.h>
> @@ -371,7 +372,7 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
>  static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
>  {
>  	struct device_node *np = p->dev->of_node;
> -	unsigned long quirks = (unsigned long)device_get_match_data(p->dev);
> +	unsigned int quirks = data->pdata->quirks;
>  
>  	if (np) {
>  		int id;
> @@ -462,6 +463,7 @@ static int dw8250_probe(struct platform_device *pdev)
>  
>  	data->data.dma.fn = dw8250_fallback_dma_filter;
>  	data->usr_reg = DW_UART_USR;

(1)

> +	data->pdata = device_get_match_data(p->dev);
>  	p->private_data = &data->data;
>  
>  	data->uart_16550_compatible = device_property_read_bool(dev,
> @@ -678,13 +680,29 @@ static const struct dev_pm_ops dw8250_pm_ops = {
>  	SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
>  };
>  
> +static const struct dw8250_platform_data dw8250_dw_apb = {};

(2)


' = {}' part is actually redundant in (2), but can we move (1) to pdata
(perhaps as a separate patch)?

In such case I would change (2) to

  static const struct dw8250_platform_data dw8250_dw_apb = {
  };

> +static const struct dw8250_platform_data dw8250_octeon_3860_data = {
> +	.quirks = DW_UART_QUIRK_OCTEON,
> +};
> +
> +static const struct dw8250_platform_data dw8250_armada_38x_data = {
> +	.quirks = DW_UART_QUIRK_ARMADA_38X,
> +};
> +
> +static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {};
> +
> +static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
> +	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
> +};
> +
>  static const struct of_device_id dw8250_of_match[] = {
> -	{ .compatible = "snps,dw-apb-uart" },
> -	{ .compatible = "cavium,octeon-3860-uart", .data = (void *)DW_UART_QUIRK_OCTEON },
> -	{ .compatible = "marvell,armada-38x-uart", .data = (void *)DW_UART_QUIRK_ARMADA_38X },
> -	{ .compatible = "renesas,rzn1-uart" },
> -	{ .compatible = "starfive,jh7100-hsuart",  .data = (void *)DW_UART_QUIRK_SKIP_SET_RATE },
> -	{ .compatible = "starfive,jh7100-uart",    .data = (void *)DW_UART_QUIRK_SKIP_SET_RATE },
> +	{ .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
> +	{ .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
> +	{ .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
> +	{ .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
> +	{ .compatible = "starfive,jh7100-hsuart", .data = &dw8250_starfive_jh7100_data },
> +	{ .compatible = "starfive,jh7100-uart", .data = &dw8250_starfive_jh7100_data },
>  	{ /* Sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, dw8250_of_match);
> diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
> index 72e7dbcccad0..68bb81bee660 100644
> --- a/drivers/tty/serial/8250/8250_dwlib.h
> +++ b/drivers/tty/serial/8250/8250_dwlib.h
> @@ -21,8 +21,13 @@ struct dw8250_port_data {
>  	u8			dlf_size;
>  };
>  
> +struct dw8250_platform_data {
> +	unsigned int quirks;
> +};
> +
>  struct dw8250_data {
>  	struct dw8250_port_data	data;
> +	const struct dw8250_platform_data *pdata;
>  
>  	u8			usr_reg;
>  	int			msr_mask_on;
> -- 
> 2.27.0
> 

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 3/9] serial: 8250: dw: Create a more generic platform data structure

[Andy Shevchenko]

On Wed, Mar 30, 2022 at 05:02:47PM +0300, Andy Shevchenko wrote:
> On Wed, Mar 30, 2022 at 03:20:32PM +0200, Miquel Raynal wrote:

...

> In such case I would change (2) to
> 
>   static const struct dw8250_platform_data dw8250_dw_apb = {
>   };

...

> > +static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {};

Btw, it makes sense to apply the above suggestion here as well

  static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
  };

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 5/9] serial: 8250: dma: Allow driver operations before starting DMA transfers

[Andy Shevchenko]

On Wed, Mar 30, 2022 at 03:20:34PM +0200, Miquel Raynal wrote:
> One situation where this could be used is when configuring the UART
> controller to be the DMA flow controller. This is a typical case where
> the driver might need to program a few more registers before starting a
> DMA transfer. Provide the necessary infrastructure to support this
> case.

OK!
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
>  drivers/tty/serial/8250/8250.h     | 18 ++++++++++++++++++
>  drivers/tty/serial/8250/8250_dma.c |  4 ++++
>  2 files changed, 22 insertions(+)
> 
> diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h
> index db784ace25d8..d19f24e4d13e 100644
> --- a/drivers/tty/serial/8250/8250.h
> +++ b/drivers/tty/serial/8250/8250.h
> @@ -17,6 +17,8 @@
>  struct uart_8250_dma {
>  	int (*tx_dma)(struct uart_8250_port *p);
>  	int (*rx_dma)(struct uart_8250_port *p);
> +	void (*prepare_tx_dma)(struct uart_8250_port *p);
> +	void (*prepare_rx_dma)(struct uart_8250_port *p);
>  
>  	/* Filter function */
>  	dma_filter_fn		fn;
> @@ -301,6 +303,22 @@ extern int serial8250_rx_dma(struct uart_8250_port *);
>  extern void serial8250_rx_dma_flush(struct uart_8250_port *);
>  extern int serial8250_request_dma(struct uart_8250_port *);
>  extern void serial8250_release_dma(struct uart_8250_port *);
> +
> +static inline void serial8250_do_prepare_tx_dma(struct uart_8250_port *p)
> +{
> +	struct uart_8250_dma *dma = p->dma;
> +
> +	if (dma->prepare_tx_dma)
> +		dma->prepare_tx_dma(p);
> +}
> +
> +static inline void serial8250_do_prepare_rx_dma(struct uart_8250_port *p)
> +{
> +	struct uart_8250_dma *dma = p->dma;
> +
> +	if (dma->prepare_rx_dma)
> +		dma->prepare_rx_dma(p);
> +}
>  #else
>  static inline int serial8250_tx_dma(struct uart_8250_port *p)
>  {
> diff --git a/drivers/tty/serial/8250/8250_dma.c b/drivers/tty/serial/8250/8250_dma.c
> index 890fa7ddaa7f..558d3a2ac65b 100644
> --- a/drivers/tty/serial/8250/8250_dma.c
> +++ b/drivers/tty/serial/8250/8250_dma.c
> @@ -77,6 +77,8 @@ int serial8250_tx_dma(struct uart_8250_port *p)
>  
>  	dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
>  
> +	serial8250_do_prepare_tx_dma(p);
> +
>  	desc = dmaengine_prep_slave_single(dma->txchan,
>  					   dma->tx_addr + xmit->tail,
>  					   dma->tx_size, DMA_MEM_TO_DEV,
> @@ -114,6 +116,8 @@ int serial8250_rx_dma(struct uart_8250_port *p)
>  	if (dma->rx_running)
>  		return 0;
>  
> +	serial8250_do_prepare_rx_dma(p);
> +
>  	desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
>  					   dma->rx_size, DMA_DEV_TO_MEM,
>  					   DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
> -- 
> 2.27.0
> 

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 1/9] serial: 8250: dw: Move definitions to the shared header

[Andy Shevchenko]

On Wed, Mar 30, 2022 at 03:20:30PM +0200, Miquel Raynal wrote:
> From: Phil Edworthy <phil.edworthy@renesas.com>
> 
> Move the per-device structure and a helper out of the main .c file, into
> a shared header as they will both be reused from another .c file.
> 
> There is no functional change.

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> [miquel.raynal@bootlin.com: Extracted from a bigger change]
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
>  drivers/tty/serial/8250/8250_dw.c    | 21 ---------------------
>  drivers/tty/serial/8250/8250_dwlib.h | 26 ++++++++++++++++++++++++++
>  2 files changed, 26 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 96a62e95726b..1666041513a5 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -42,27 +42,6 @@
>  #define DW_UART_QUIRK_ARMADA_38X	BIT(1)
>  #define DW_UART_QUIRK_SKIP_SET_RATE	BIT(2)
>  
> -struct dw8250_data {
> -	struct dw8250_port_data	data;
> -
> -	u8			usr_reg;
> -	int			msr_mask_on;
> -	int			msr_mask_off;
> -	struct clk		*clk;
> -	struct clk		*pclk;
> -	struct notifier_block	clk_notifier;
> -	struct work_struct	clk_work;
> -	struct reset_control	*rst;
> -
> -	unsigned int		skip_autocfg:1;
> -	unsigned int		uart_16550_compatible:1;
> -};
> -
> -static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
> -{
> -	return container_of(data, struct dw8250_data, data);
> -}
> -
>  static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
>  {
>  	return container_of(nb, struct dw8250_data, clk_notifier);
> diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h
> index 83d528e5cc21..72e7dbcccad0 100644
> --- a/drivers/tty/serial/8250/8250_dwlib.h
> +++ b/drivers/tty/serial/8250/8250_dwlib.h
> @@ -1,10 +1,15 @@
>  /* SPDX-License-Identifier: GPL-2.0+ */
>  /* Synopsys DesignWare 8250 library header file. */
>  
> +#include <linux/notifier.h>
>  #include <linux/types.h>
> +#include <linux/workqueue.h>
>  
>  #include "8250.h"
>  
> +struct clk;
> +struct reset_control;
> +
>  struct dw8250_port_data {
>  	/* Port properties */
>  	int			line;
> @@ -16,5 +21,26 @@ struct dw8250_port_data {
>  	u8			dlf_size;
>  };
>  
> +struct dw8250_data {
> +	struct dw8250_port_data	data;
> +
> +	u8			usr_reg;
> +	int			msr_mask_on;
> +	int			msr_mask_off;
> +	struct clk		*clk;
> +	struct clk		*pclk;
> +	struct notifier_block	clk_notifier;
> +	struct work_struct	clk_work;
> +	struct reset_control	*rst;
> +
> +	unsigned int		skip_autocfg:1;
> +	unsigned int		uart_16550_compatible:1;
> +};
> +
>  void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, struct ktermios *old);
>  void dw8250_setup_port(struct uart_port *p);
> +
> +static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
> +{
> +	return container_of(data, struct dw8250_data, data);
> +}
> -- 
> 2.27.0
> 

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 4/9] serial: 8250: dw: Allow to use a fallback CPR value if not synthesized

[Andy Shevchenko]

On Wed, Mar 30, 2022 at 03:20:33PM +0200, Miquel Raynal wrote:
> DW UART controllers can be synthesized without the CPR register.
> In this case, allow to the platform information to provide a CPR value.

...

> +#include <linux/property.h>

Doesn't belong to this patch.

...

>  	reg = dw8250_readl_ext(p, DW_UART_CPR);
> +	if (!reg) {
> +		reg = data->pdata->cpr;
> +		dev_dbg(p->dev, "CPR is not available, using 0x%08x instead\n", reg);
> +	}

> +

Redundant blank line.

>  	if (!reg)
>  		return;

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 0/9] serial: 8250: dw: RZN1 DMA support

[Andy Shevchenko]

On Wed, Mar 30, 2022 at 03:20:29PM +0200, Miquel Raynal wrote:
> Hello,
> 
> Support for the RZN1 DMA engine allows us adapt a little bit the 8250 DW
> UART driver with to bring DMA support for this SoC.
> 
> This short series applies on top of the series bringing RZN1 DMA
> support, currently on its v5, see [1]. Technically speaking, only the DT
> patch needs to be applied after [1]. The other patches can come in at
> any moment, because if no "dmas" property is provided in the DT, DMA
> support will simply be ignored.
> 
> [1] https://lore.kernel.org/dmaengine/20220315191255.221473-1-miquel.raynal@bootlin.com/T/#m0ef3323abce3eec961e142bf2fb35e95b9045fc5

Couple of versions ago I have asked you to Cc the series to Ilpo (Cc'ed).
I hope you will not forget it in v5.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 6/9] serial: 8250: dw: Introduce an rx_timeout variable in the IRQ path

[Andy Shevchenko]

On Wed, Mar 30, 2022 at 03:20:35PM +0200, Miquel Raynal wrote:
> In a next change we are going to need the same Rx timeout condition as
> we already have in the IRQ handling code. Let's just create a boolean to
> clarify what this operation does before reusing it.
> 
> There is no functional change.

OK!

Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
>  drivers/tty/serial/8250/8250_dw.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 70a843e31ffd..a156c6d2f866 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -223,6 +223,7 @@ static int dw8250_handle_irq(struct uart_port *p)
>  	struct uart_8250_port *up = up_to_u8250p(p);
>  	struct dw8250_data *d = to_dw8250_data(p->private_data);
>  	unsigned int iir = p->serial_in(p, UART_IIR);
> +	bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
>  	unsigned int status;
>  	unsigned long flags;
>  
> @@ -236,7 +237,7 @@ static int dw8250_handle_irq(struct uart_port *p)
>  	 * This problem has only been observed so far when not in DMA mode
>  	 * so we limit the workaround only to non-DMA mode.
>  	 */
> -	if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
> +	if (!up->dma && rx_timeout) {
>  		spin_lock_irqsave(&p->lock, flags);
>  		status = p->serial_in(p, UART_LSR);
>  
> -- 
> 2.27.0
> 

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 7/9] serial: 8250: dw: Add support for DMA flow controlling devices

[Andy Shevchenko]

On Wed, Mar 30, 2022 at 03:20:36PM +0200, Miquel Raynal wrote:
> From: Phil Edworthy <phil.edworthy@renesas.com>
> 
> DW based controllers like the one on Renesas RZ/N1 must be programmed as
> flow controllers when using DMA.
> 
> * Table 11.45 of the system manual, "Flow Control Combinations", states
>   that using UART with DMA requires setting the DMA in the peripheral
>   flow controller mode regardless of the direction.
> 
> * Chapter 11.6.1.3 of the system manual, "Basic Interface Definitions",
>   explains that the burst size in the above case must be configured in
>   the peripheral's register DEST/SRC_BURST_SIZE.
> 
> Experiments shown that upon Rx timeout, the DMA transaction needed to be
> manually cleared as well.

One comment below, after addressing,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Co-developed-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
>  drivers/tty/serial/8250/8250_dw.c | 64 +++++++++++++++++++++++++++++++
>  1 file changed, 64 insertions(+)
> 
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index a156c6d2f866..977a473535e8 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -34,14 +34,26 @@
>  
>  /* Offsets for the DesignWare specific registers */
>  #define DW_UART_USR	0x1f /* UART Status Register */
> +#define DW_UART_DMASA	0xa8 /* DMA Software Ack */
> +
> +#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
> +#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
>  
>  /* DesignWare specific register fields */
>  #define DW_UART_MCR_SIRE		BIT(6)
>  
> +/* Renesas specific register fields */
> +#define RZN1_UART_xDMACR_DMA_EN		BIT(0)
> +#define RZN1_UART_xDMACR_1_WORD_BURST	(0 << 1)
> +#define RZN1_UART_xDMACR_4_WORD_BURST	(1 << 1)
> +#define RZN1_UART_xDMACR_8_WORD_BURST	(3 << 1)
> +#define RZN1_UART_xDMACR_BLK_SZ(x)	((x) << 3)
> +
>  /* Quirks */
>  #define DW_UART_QUIRK_OCTEON		BIT(0)
>  #define DW_UART_QUIRK_ARMADA_38X	BIT(1)
>  #define DW_UART_QUIRK_SKIP_SET_RATE	BIT(2)
> +#define DW_UART_QUIRK_IS_DMA_FC		BIT(3)
>  
>  static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
>  {
> @@ -224,6 +236,7 @@ static int dw8250_handle_irq(struct uart_port *p)
>  	struct dw8250_data *d = to_dw8250_data(p->private_data);
>  	unsigned int iir = p->serial_in(p, UART_IIR);
>  	bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
> +	unsigned int quirks = d->pdata->quirks;
>  	unsigned int status;
>  	unsigned long flags;
>  
> @@ -247,6 +260,15 @@ static int dw8250_handle_irq(struct uart_port *p)
>  		spin_unlock_irqrestore(&p->lock, flags);
>  	}
>  
> +	/* Manually stop the Rx DMA transfer when acting as flow controller */
> +	if (up->dma && up->dma->rx_running && rx_timeout && quirks & DW_UART_QUIRK_IS_DMA_FC) {
> +		status = p->serial_in(p, UART_LSR);
> +		if (status & (UART_LSR_DR | UART_LSR_BI)) {
> +			writel(0, p->membase + RZN1_UART_RDMACR);
> +			writel(1, p->membase + DW_UART_DMASA);
> +		}
> +	}
> +
>  	if (serial8250_handle_irq(p, iir))
>  		return 1;
>  
> @@ -370,6 +392,42 @@ static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
>  	return param == chan->device->dev;
>  }
>  
> +static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
> +{
> +	if (max_burst >= 8)
> +		return RZN1_UART_xDMACR_8_WORD_BURST;
> +	else if (max_burst >= 4)
> +		return RZN1_UART_xDMACR_4_WORD_BURST;
> +	else
> +		return RZN1_UART_xDMACR_1_WORD_BURST;
> +}
> +
> +static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
> +{
> +	struct uart_port *up = &p->port;
> +	struct uart_8250_dma *dma = p->dma;
> +	u32 val;
> +
> +	writel(0, up->membase + RZN1_UART_TDMACR);
> +	val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
> +	      RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
> +	      RZN1_UART_xDMACR_DMA_EN;
> +	writel(val, up->membase + RZN1_UART_TDMACR);
> +}
> +
> +static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
> +{
> +	struct uart_port *up = &p->port;
> +	struct uart_8250_dma *dma = p->dma;
> +	u32 val;
> +
> +	writel(0, up->membase + RZN1_UART_RDMACR);
> +	val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
> +	      RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
> +	      RZN1_UART_xDMACR_DMA_EN;
> +	writel(val, up->membase + RZN1_UART_RDMACR);
> +}
> +
>  static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
>  {
>  	struct device_node *np = p->dev->of_node;
> @@ -403,6 +461,12 @@ static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
>  			p->serial_out = dw8250_serial_out38x;
>  		if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
>  			p->set_termios = dw8250_do_set_termios;
> +		if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
> +			data->data.dma.txconf.device_fc = 1;
> +			data->data.dma.rxconf.device_fc = 1;
> +			data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
> +			data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
> +		}
>  
>  	} else if (acpi_dev_present("APMC0D08", NULL, -1)) {
>  		p->iotype = UPIO_MEM32;
> -- 
> 2.27.0
> 

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 7/9] serial: 8250: dw: Add support for DMA flow controlling devices

[Andy Shevchenko]

On Wed, Mar 30, 2022 at 05:16:42PM +0300, Andy Shevchenko wrote:
> On Wed, Mar 30, 2022 at 03:20:36PM +0200, Miquel Raynal wrote:
> > From: Phil Edworthy <phil.edworthy@renesas.com>

> One comment below, after addressing,

Missed comment:

> > +	/* Manually stop the Rx DMA transfer when acting as flow controller */

> > +	if (up->dma && up->dma->rx_running && rx_timeout && quirks & DW_UART_QUIRK_IS_DMA_FC) {

This is an interrupt context and I think it's better that we quit as earlier as
possible, meaning the quirk check should be first (i.o.w. from particular to
general when && is in use).

> > +		status = p->serial_in(p, UART_LSR);
> > +		if (status & (UART_LSR_DR | UART_LSR_BI)) {
> > +			writel(0, p->membase + RZN1_UART_RDMACR);
> > +			writel(1, p->membase + DW_UART_DMASA);
> > +		}
> > +	}

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 8/9] serial: 8250: dw: Improve RZN1 support

[Andy Shevchenko]

On Wed, Mar 30, 2022 at 03:20:37PM +0200, Miquel Raynal wrote:
> From: Phil Edworthy <phil.edworthy@renesas.com>
> 
> Renesas RZ/N1 SoC features a slightly modified DW UART.
> 
> On this SoC, the CPR register value is known but not synthetized in
> hardware. We hence need to provide a CPR value in the platform
> data. This version of the controller also relies on acting as flow
> controller when using DMA, so we need to provide the
> "is dma flow controller" quirk.

After modifying one of previous patches...

> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Co-developed-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
>  drivers/tty/serial/8250/8250_dw.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 977a473535e8..195aa4516b2b 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -755,7 +755,10 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = {
>  	.quirks = DW_UART_QUIRK_ARMADA_38X,
>  };
>  
> -static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {};
> +static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {

...this change...

> +	.quirks = DW_UART_QUIRK_IS_DMA_FC,
> +	.cpr = 0x00012f32,

> +};

...and this will disappear from this patch.

With it rebased,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>

>  static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {
>  	.quirks = DW_UART_QUIRK_SKIP_SET_RATE,
> -- 
> 2.27.0
> 

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 7/9] serial: 8250: dw: Add support for DMA flow controlling devices

[Ilpo Järvinen]

On Wed, 30 Mar 2022, Miquel Raynal wrote:

> From: Phil Edworthy <phil.edworthy@renesas.com>
> 
> DW based controllers like the one on Renesas RZ/N1 must be programmed as
> flow controllers when using DMA.
> 
> * Table 11.45 of the system manual, "Flow Control Combinations", states
>   that using UART with DMA requires setting the DMA in the peripheral
>   flow controller mode regardless of the direction.
> 
> * Chapter 11.6.1.3 of the system manual, "Basic Interface Definitions",
>   explains that the burst size in the above case must be configured in
>   the peripheral's register DEST/SRC_BURST_SIZE.
> 
> Experiments shown that upon Rx timeout, the DMA transaction needed to be
> manually cleared as well.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Co-developed-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
>  drivers/tty/serial/8250/8250_dw.c | 64 +++++++++++++++++++++++++++++++
>  1 file changed, 64 insertions(+)
> 
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index a156c6d2f866..977a473535e8 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -34,14 +34,26 @@
>  
>  /* Offsets for the DesignWare specific registers */
>  #define DW_UART_USR	0x1f /* UART Status Register */
> +#define DW_UART_DMASA	0xa8 /* DMA Software Ack */
> +
> +#define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
> +#define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
>  
>  /* DesignWare specific register fields */
>  #define DW_UART_MCR_SIRE		BIT(6)
>  
> +/* Renesas specific register fields */
> +#define RZN1_UART_xDMACR_DMA_EN		BIT(0)
> +#define RZN1_UART_xDMACR_1_WORD_BURST	(0 << 1)
> +#define RZN1_UART_xDMACR_4_WORD_BURST	(1 << 1)
> +#define RZN1_UART_xDMACR_8_WORD_BURST	(3 << 1)
> +#define RZN1_UART_xDMACR_BLK_SZ(x)	((x) << 3)
> +
>  /* Quirks */
>  #define DW_UART_QUIRK_OCTEON		BIT(0)
>  #define DW_UART_QUIRK_ARMADA_38X	BIT(1)
>  #define DW_UART_QUIRK_SKIP_SET_RATE	BIT(2)
> +#define DW_UART_QUIRK_IS_DMA_FC		BIT(3)
>  
>  static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
>  {
> @@ -224,6 +236,7 @@ static int dw8250_handle_irq(struct uart_port *p)
>  	struct dw8250_data *d = to_dw8250_data(p->private_data);
>  	unsigned int iir = p->serial_in(p, UART_IIR);
>  	bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
> +	unsigned int quirks = d->pdata->quirks;
>  	unsigned int status;
>  	unsigned long flags;
>  
> @@ -247,6 +260,15 @@ static int dw8250_handle_irq(struct uart_port *p)
>  		spin_unlock_irqrestore(&p->lock, flags);
>  	}
>  
> +	/* Manually stop the Rx DMA transfer when acting as flow controller */
> +	if (up->dma && up->dma->rx_running && rx_timeout && quirks & DW_UART_QUIRK_IS_DMA_FC) {
> +		status = p->serial_in(p, UART_LSR);
> +		if (status & (UART_LSR_DR | UART_LSR_BI)) {
> +			writel(0, p->membase + RZN1_UART_RDMACR);
> +			writel(1, p->membase + DW_UART_DMASA);

Currently there is serial_out(), dw8250_writel_ext(), and a few writel()s 
too for writing to registers. It would be nice to move towards more 
homogeneous approach rather than adding more writel()s.

I suggest dw8250_writel_ext() is moved to dwlib.h. Then it could be used 
here (and dw8250_readl_ext() too should be moved but IIRC there wasn't 
any reads added by this series).

-- 
 i.

Re: [PATCH v4 7/9] serial: 8250: dw: Add support for DMA flow controlling devices

[Andy Shevchenko]

On Fri, Apr 01, 2022 at 01:56:49PM +0300, Ilpo Järvinen wrote:
> On Wed, 30 Mar 2022, Miquel Raynal wrote:

...

> > +			writel(0, p->membase + RZN1_UART_RDMACR);
> > +			writel(1, p->membase + DW_UART_DMASA);
> 
> Currently there is serial_out(), dw8250_writel_ext(), and a few writel()s 
> too for writing to registers. It would be nice to move towards more 
> homogeneous approach rather than adding more writel()s.

Actually a good catch!

> I suggest dw8250_writel_ext() is moved to dwlib.h. Then it could be used 
> here (and dw8250_readl_ext() too should be moved but IIRC there wasn't 
> any reads added by this series).

I agree that for the sake of symmetry it's good to move both.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v4 0/9] serial: 8250: dw: RZN1 DMA support

[Miquel Raynal]

Hello,

andriy.shevchenko@linux.intel.com wrote on Wed, 30 Mar 2022 17:13:16
+0300:

> On Wed, Mar 30, 2022 at 03:20:29PM +0200, Miquel Raynal wrote:
> > Hello,
> > 
> > Support for the RZN1 DMA engine allows us adapt a little bit the 8250 DW
> > UART driver with to bring DMA support for this SoC.
> > 
> > This short series applies on top of the series bringing RZN1 DMA
> > support, currently on its v5, see [1]. Technically speaking, only the DT
> > patch needs to be applied after [1]. The other patches can come in at
> > any moment, because if no "dmas" property is provided in the DT, DMA
> > support will simply be ignored.
> > 
> > [1] https://lore.kernel.org/dmaengine/20220315191255.221473-1-miquel.raynal@bootlin.com/T/#m0ef3323abce3eec961e142bf2fb35e95b9045fc5  
> 
> Couple of versions ago I have asked you to Cc the series to Ilpo (Cc'ed).
> I hope you will not forget it in v5.

Sorry I forgot to re-add manually Ilpo in the recipients.

Anyway, if Ilpo really needs to be Cc'ed, then there is something to do
on MAINTAINER's side.

Thanks,
Miquèl

Re: [PATCH v4 0/9] serial: 8250: dw: RZN1 DMA support

[Ilpo Järvinen]

On Mon, 4 Apr 2022, Miquel Raynal wrote:

> Hello,
> 
> andriy.shevchenko@linux.intel.com wrote on Wed, 30 Mar 2022 17:13:16
> +0300:
> 
> > On Wed, Mar 30, 2022 at 03:20:29PM +0200, Miquel Raynal wrote:
> > > Hello,
> > > 
> > > Support for the RZN1 DMA engine allows us adapt a little bit the 8250 DW
> > > UART driver with to bring DMA support for this SoC.
> > > 
> > > This short series applies on top of the series bringing RZN1 DMA
> > > support, currently on its v5, see [1]. Technically speaking, only the DT
> > > patch needs to be applied after [1]. The other patches can come in at
> > > any moment, because if no "dmas" property is provided in the DT, DMA
> > > support will simply be ignored.
> > > 
> > > [1] https://lore.kernel.org/dmaengine/20220315191255.221473-1-miquel.raynal@bootlin.com/T/#m0ef3323abce3eec961e142bf2fb35e95b9045fc5  
> > 
> > Couple of versions ago I have asked you to Cc the series to Ilpo (Cc'ed).
> > I hope you will not forget it in v5.
> 
> Sorry I forgot to re-add manually Ilpo in the recipients.
> 
> Anyway, if Ilpo really needs to be Cc'ed, then there is something to do
> on MAINTAINER's side.

While I'm considering doing like you suggest, I don't think it can be in 
general said that people who you're specificially told to Cc would be ok 
to get dropped unless they're among the listed maintainers.


-- 
 i.

Re: [PATCH v4 7/9] serial: 8250: dw: Add support for DMA flow controlling devices

[Miquel Raynal]

Hi Andy, Ilpo,

andriy.shevchenko@linux.intel.com wrote on Fri, 1 Apr 2022 20:38:24
+0300:

> On Fri, Apr 01, 2022 at 01:56:49PM +0300, Ilpo Järvinen wrote:
> > On Wed, 30 Mar 2022, Miquel Raynal wrote:  
> 
> ...
> 
> > > +			writel(0, p->membase + RZN1_UART_RDMACR);
> > > +			writel(1, p->membase + DW_UART_DMASA);  
> > 
> > Currently there is serial_out(), dw8250_writel_ext(), and a few writel()s 
> > too for writing to registers. It would be nice to move towards more 
> > homogeneous approach rather than adding more writel()s.  
> 
> Actually a good catch!
> 
> > I suggest dw8250_writel_ext() is moved to dwlib.h. Then it could be used 
> > here (and dw8250_readl_ext() too should be moved but IIRC there wasn't 
> > any reads added by this series).  
> 
> I agree that for the sake of symmetry it's good to move both.

I moved them both to dwlib.h as suggested.

I had a look at the current uses of readb/l and writeb/l in dw.c but
converting all these function calls is not as straightforward as I
initially thought so I decided to limit myself to moving these helpers
and using them in my additions, I hope this is fine.

Thanks,
Miquèl

Re: [PATCH v4 7/9] serial: 8250: dw: Add support for DMA flow controlling devices

[Ilpo Järvinen]

[-- Attachment #1: Type: text/plain, Size: 1293 bytes --]

On Mon, 4 Apr 2022, Miquel Raynal wrote:

> Hi Andy, Ilpo,
> 
> andriy.shevchenko@linux.intel.com wrote on Fri, 1 Apr 2022 20:38:24
> +0300:
> 
> > On Fri, Apr 01, 2022 at 01:56:49PM +0300, Ilpo Järvinen wrote:
> > > On Wed, 30 Mar 2022, Miquel Raynal wrote:  
> > 
> > ...
> > 
> > > > +			writel(0, p->membase + RZN1_UART_RDMACR);
> > > > +			writel(1, p->membase + DW_UART_DMASA);  
> > > 
> > > Currently there is serial_out(), dw8250_writel_ext(), and a few writel()s 
> > > too for writing to registers. It would be nice to move towards more 
> > > homogeneous approach rather than adding more writel()s.  
> > 
> > Actually a good catch!
> > 
> > > I suggest dw8250_writel_ext() is moved to dwlib.h. Then it could be used 
> > > here (and dw8250_readl_ext() too should be moved but IIRC there wasn't 
> > > any reads added by this series).  
> > 
> > I agree that for the sake of symmetry it's good to move both.
> 
> I moved them both to dwlib.h as suggested.
> 
> I had a look at the current uses of readb/l and writeb/l in dw.c but
> converting all these function calls is not as straightforward as I
> initially thought so I decided to limit myself to moving these helpers
> and using them in my additions, I hope this is fine.

Yes, I think it's enough for this series.


-- 
 i.