Re: [PATCH] arm64/sme: Add hwcap for Scalable Matrix Extension

From: Mark Brown <broonie@kernel.org>
To: Tianjia Zhang <tianjia.zhang@linux.alibaba.com>
Cc: Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Jonathan Corbet <corbet@lwn.net>, Marc Zyngier <maz@kernel.org>,
	Joey Gouly <joey.gouly@arm.com>,
	Vincenzo Frascino <Vincenzo.Frascino@arm.com>,
	Arnd Bergmann <arnd@arndb.de>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	Fuad Tabba <tabba@google.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Vladimir Murzin <vladimir.murzin@arm.com>,
	James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64/sme: Add hwcap for Scalable Matrix Extension
Date: Tue, 19 Apr 2022 14:58:17 +0100	[thread overview]
Message-ID: <Yl6/+baDhElVxwyC@sirena.org.uk> (raw)
In-Reply-To: <e7a0d0d4-b6ca-6fec-df33-929961f0d43e@linux.alibaba.com>

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On Fri, Apr 15, 2022 at 10:25:33AM +0800, Tianjia Zhang wrote:
> On 4/14/22 8:02 PM, Mark Brown wrote:
> > On Thu, Apr 14, 2022 at 07:55:44PM +0800, Tianjia Zhang wrote:

> > Why add something independently, especially given that there is no way
> > for userspace to do anything constructive with the feature without the
> > rest of the kernel support?  Any attempt to use SME instructions without
> > kernel support will trap and generate a SIGILL even if the feature is
> > present in hardware.

> Great job, I encountered the issue of invalid REVD (requires FEAT_SME)
> instruction when developing SVE2 programs, so I plan to gradually
> support SME in the kernel, thanks for your contribution, you can ignore
> my patch.

I see.  Unfortunately all the new registers mean that we really need to
define all the ABI as soon as we enable anything and the only thing we
can really skip out on when doing initial enablement is KVM (which I
have in fact skipped for the time being, I'll look at that at some point
after the initial support is landed).

> In addition, I would like to ask a question, whether there is an
> alternative SVE2 instruction for the REVD instruction that can complete
> this operation, if the machine does not support SME.

I'm not aware of anything, but I am mostly focused on the OS support
rather than any of the actual mathematical operations that are more the
point of these architecture features so I might be missing something.

> > Do you have a system with SME that you're trying to use?  Review/testing
> > on the current series would be appreciated.

> Unfortunately, the value currently read by my machine ID_AA64PFR1_EL1
> register is 0x121. It seems that the hardware does not support SME. Is
> there any other help I can provide?

Other than verifying that the series doesn't cause trouble for systems
without SME 

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