* [PATCH 0/3] arm64: dts: qcom: sm8450: add thermal zones and cooling maps
@ 2022-04-10 23:44 Dmitry Baryshkov
2022-04-10 23:44 ` [PATCH 1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers Dmitry Baryshkov
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Dmitry Baryshkov @ 2022-04-10 23:44 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, Vladimir Zapolskiy
Add thermal related definitions for the SM8450 platform:
- Add two tsens thermal sensors nodes
- Add corresponding thermal zones
- Link thermal zones to cooling devices provided by CPU clusters.
Dmitry Baryshkov (1):
arm64: dts: qcom: sm8450: add cooling-maps to CPU trip points
Vladimir Zapolskiy (2):
arm64: dts: qcom: sm8450: Add thermal sensor controllers
arm64: dts: qcom: sm8450: Add thermal zones
arch/arm64/boot/dts/qcom/sm8450.dtsi | 1056 ++++++++++++++++++++++++++
1 file changed, 1056 insertions(+)
--
2.35.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers 2022-04-10 23:44 [PATCH 0/3] arm64: dts: qcom: sm8450: add thermal zones and cooling maps Dmitry Baryshkov @ 2022-04-10 23:44 ` Dmitry Baryshkov 2022-04-12 19:39 ` Dmitry Baryshkov ` (2 more replies) 2022-04-10 23:44 ` [PATCH 2/3] arm64: dts: qcom: sm8450: Add thermal zones Dmitry Baryshkov 2022-04-10 23:44 ` [PATCH 3/3] arm64: dts: qcom: sm8450: add cooling-maps to CPU trip points Dmitry Baryshkov 2 siblings, 3 replies; 9+ messages in thread From: Dmitry Baryshkov @ 2022-04-10 23:44 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, Vladimir Zapolskiy From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> The change adds description of two thermal sensor controllers found on SM8450. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 934e29b9e153..b695ce824722 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1021,6 +1021,28 @@ pdc: interrupt-controller@b220000 { interrupt-controller; }; + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1000>, /* TM */ + <0 0x0c222000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1000>, /* TM */ + <0 0x0c223000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; -- 2.35.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers 2022-04-10 23:44 ` [PATCH 1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers Dmitry Baryshkov @ 2022-04-12 19:39 ` Dmitry Baryshkov 2022-04-19 17:34 ` Bjorn Andersson 2022-04-21 14:26 ` (subset) " Bjorn Andersson 2 siblings, 0 replies; 9+ messages in thread From: Dmitry Baryshkov @ 2022-04-12 19:39 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, Vladimir Zapolskiy On 11/04/2022 02:44, Dmitry Baryshkov wrote: > From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > > The change adds description of two thermal sensor controllers found > on SM8450. > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Of course: Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 934e29b9e153..b695ce824722 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -1021,6 +1021,28 @@ pdc: interrupt-controller@b220000 { > interrupt-controller; > }; > > + tsens0: thermal-sensor@c263000 { > + compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; > + reg = <0 0x0c263000 0 0x1000>, /* TM */ > + <0 0x0c222000 0 0x1000>; /* SROT */ > + #qcom,sensors = <16>; > + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow", "critical"; > + #thermal-sensor-cells = <1>; > + }; > + > + tsens1: thermal-sensor@c265000 { > + compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; > + reg = <0 0x0c265000 0 0x1000>, /* TM */ > + <0 0x0c223000 0 0x1000>; /* SROT */ > + #qcom,sensors = <16>; > + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow", "critical"; > + #thermal-sensor-cells = <1>; > + }; > + > aoss_qmp: power-controller@c300000 { > compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; > reg = <0 0x0c300000 0 0x400>; -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers 2022-04-10 23:44 ` [PATCH 1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers Dmitry Baryshkov 2022-04-12 19:39 ` Dmitry Baryshkov @ 2022-04-19 17:34 ` Bjorn Andersson 2022-04-21 14:26 ` (subset) " Bjorn Andersson 2 siblings, 0 replies; 9+ messages in thread From: Bjorn Andersson @ 2022-04-19 17:34 UTC (permalink / raw) To: Dmitry Baryshkov Cc: Andy Gross, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, Vladimir Zapolskiy On Sun 10 Apr 18:44 CDT 2022, Dmitry Baryshkov wrote: > From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > > The change adds description of two thermal sensor controllers found > on SM8450. > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 934e29b9e153..b695ce824722 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -1021,6 +1021,28 @@ pdc: interrupt-controller@b220000 { > interrupt-controller; > }; > > + tsens0: thermal-sensor@c263000 { > + compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; Please don't forget to add qcom,sm8450-tsens to the DT binding documentation. Thanks, Bjorn > + reg = <0 0x0c263000 0 0x1000>, /* TM */ > + <0 0x0c222000 0 0x1000>; /* SROT */ > + #qcom,sensors = <16>; > + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow", "critical"; > + #thermal-sensor-cells = <1>; > + }; > + > + tsens1: thermal-sensor@c265000 { > + compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; > + reg = <0 0x0c265000 0 0x1000>, /* TM */ > + <0 0x0c223000 0 0x1000>; /* SROT */ > + #qcom,sensors = <16>; > + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow", "critical"; > + #thermal-sensor-cells = <1>; > + }; > + > aoss_qmp: power-controller@c300000 { > compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; > reg = <0 0x0c300000 0 0x400>; > -- > 2.35.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: (subset) [PATCH 1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers 2022-04-10 23:44 ` [PATCH 1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers Dmitry Baryshkov 2022-04-12 19:39 ` Dmitry Baryshkov 2022-04-19 17:34 ` Bjorn Andersson @ 2022-04-21 14:26 ` Bjorn Andersson 2 siblings, 0 replies; 9+ messages in thread From: Bjorn Andersson @ 2022-04-21 14:26 UTC (permalink / raw) To: Rob Herring, Dmitry Baryshkov, Andy Gross, Krzysztof Kozlowski Cc: devicetree, linux-arm-msm, Vladimir Zapolskiy On Mon, 11 Apr 2022 02:44:56 +0300, Dmitry Baryshkov wrote: > From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > > The change adds description of two thermal sensor controllers found > on SM8450. > > Applied, thanks! [1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers commit: 48995e863307bf08a51362a0aafb10e70bdafb4e Best regards, -- Bjorn Andersson <bjorn.andersson@linaro.org> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 2/3] arm64: dts: qcom: sm8450: Add thermal zones 2022-04-10 23:44 [PATCH 0/3] arm64: dts: qcom: sm8450: add thermal zones and cooling maps Dmitry Baryshkov 2022-04-10 23:44 ` [PATCH 1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers Dmitry Baryshkov @ 2022-04-10 23:44 ` Dmitry Baryshkov 2022-04-21 14:26 ` (subset) " Bjorn Andersson 2022-04-10 23:44 ` [PATCH 3/3] arm64: dts: qcom: sm8450: add cooling-maps to CPU trip points Dmitry Baryshkov 2 siblings, 1 reply; 9+ messages in thread From: Dmitry Baryshkov @ 2022-04-10 23:44 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, Vladimir Zapolskiy From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Add thermal zones handled by tsens sensors. The definitions and the trip points were taken from the downstream dts. For the CPU core thermal sensors, the trip points were changed to follow the example of other Qualcomm platforms. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 843 +++++++++++++++++++++++++++ 1 file changed, 843 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b695ce824722..4f3c7e7d2855 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/interconnect/qcom,sm8450.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -47,6 +48,7 @@ CPU0: cpu@0 { power-domains = <&CPU_PD0>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -65,6 +67,7 @@ CPU1: cpu@100 { power-domains = <&CPU_PD1>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -80,6 +83,7 @@ CPU2: cpu@200 { power-domains = <&CPU_PD2>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -95,6 +99,7 @@ CPU3: cpu@300 { power-domains = <&CPU_PD3>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -110,6 +115,7 @@ CPU4: cpu@400 { power-domains = <&CPU_PD4>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -125,6 +131,7 @@ CPU5: cpu@500 { power-domains = <&CPU_PD5>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -141,6 +148,7 @@ CPU6: cpu@600 { power-domains = <&CPU_PD6>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -156,6 +164,7 @@ CPU7: cpu@700 { power-domains = <&CPU_PD7>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; + #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -1517,6 +1526,840 @@ lpass_ag_noc: interconnect@3c40000 { }; }; + thermal-zones { + aoss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + cpu4_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + cpu4_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + cpu5_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + cpu5_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + cpu6_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + cpu7_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-middle-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + cpu7_middle_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + + trips { + cpu7_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-top-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu0_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpu-bottom-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu1_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cdsp0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp_0_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp_1_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp2-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp_2_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + ddr_config0: ddr0-config { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss0_config0: mdmss0-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss0_config1: mdmss0-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss1_config0: mdmss1-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss1_config1: mdmss1-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss2_config0: mdmss2-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss2_config1: mdmss2-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss3_config0: mdmss3-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss3_config1: mdmss3-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 14>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 15>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, -- 2.35.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: (subset) [PATCH 2/3] arm64: dts: qcom: sm8450: Add thermal zones 2022-04-10 23:44 ` [PATCH 2/3] arm64: dts: qcom: sm8450: Add thermal zones Dmitry Baryshkov @ 2022-04-21 14:26 ` Bjorn Andersson 0 siblings, 0 replies; 9+ messages in thread From: Bjorn Andersson @ 2022-04-21 14:26 UTC (permalink / raw) To: Rob Herring, Dmitry Baryshkov, Andy Gross, Krzysztof Kozlowski Cc: Vladimir Zapolskiy, linux-arm-msm, devicetree On Mon, 11 Apr 2022 02:44:57 +0300, Dmitry Baryshkov wrote: > From: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> > > Add thermal zones handled by tsens sensors. The definitions and the trip > points were taken from the downstream dts. For the CPU core thermal > sensors, the trip points were changed to follow the example of other > Qualcomm platforms. > > [...] Applied, thanks! [2/3] arm64: dts: qcom: sm8450: Add thermal zones commit: fccf8e31ac3d7c3f874ae5d78de495edaf1ead58 Best regards, -- Bjorn Andersson <bjorn.andersson@linaro.org> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: sm8450: add cooling-maps to CPU trip points 2022-04-10 23:44 [PATCH 0/3] arm64: dts: qcom: sm8450: add thermal zones and cooling maps Dmitry Baryshkov 2022-04-10 23:44 ` [PATCH 1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers Dmitry Baryshkov 2022-04-10 23:44 ` [PATCH 2/3] arm64: dts: qcom: sm8450: Add thermal zones Dmitry Baryshkov @ 2022-04-10 23:44 ` Dmitry Baryshkov 2022-04-19 17:16 ` Bjorn Andersson 2 siblings, 1 reply; 9+ messages in thread From: Dmitry Baryshkov @ 2022-04-10 23:44 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, Vladimir Zapolskiy Follow the lead of other Qualcomm platforms and add cooling maps for CPU trip points. Handle three clusters separately, cooling cores 0-3 for cpu0-3 trip points, cores 4-6 for cpu4-6 trip points and only cpu7 for cpu7 trip points. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 191 +++++++++++++++++++++++++++ 1 file changed, 191 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 4f3c7e7d2855..dd8ef4438fd0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1651,6 +1651,21 @@ cpu4_top_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu4_top_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu4_top_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu4-bottom-thermal { @@ -1677,6 +1692,21 @@ cpu4_bottom_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu4_bottom_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu4_bottom_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu5-top-thermal { @@ -1703,6 +1733,21 @@ cpu5_top_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu5_top_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu5_top_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu5-bottom-thermal { @@ -1729,6 +1774,21 @@ cpu5_bottom_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu5_bottom_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu5_bottom_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu6-top-thermal { @@ -1755,6 +1815,21 @@ cpu6_top_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu6_top_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu6_top_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu6-bottom-thermal { @@ -1781,6 +1856,21 @@ cpu6_bottom_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu6_bottom_alert0>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu6_bottom_alert1>; + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu7-top-thermal { @@ -1807,6 +1897,17 @@ cpu7_top_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu7_top_alert0>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu7_top_alert1>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu7-middle-thermal { @@ -1833,6 +1934,17 @@ cpu7_middle_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu7_middle_alert0>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu7_middle_alert1>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu7-bottom-thermal { @@ -1859,6 +1971,17 @@ cpu7_bottom_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu7_bottom_alert0>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu7_bottom_alert1>; + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpu-top-thermal { @@ -1969,6 +2092,23 @@ cpu0_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu0_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu0_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -1995,6 +2135,23 @@ cpu1_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu1_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu1_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -2021,6 +2178,23 @@ cpu2_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu2_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu2_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -2047,6 +2221,23 @@ cpu3_crit: cpu_crit { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu3_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu3_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cdsp0-thermal { -- 2.35.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: sm8450: add cooling-maps to CPU trip points 2022-04-10 23:44 ` [PATCH 3/3] arm64: dts: qcom: sm8450: add cooling-maps to CPU trip points Dmitry Baryshkov @ 2022-04-19 17:16 ` Bjorn Andersson 0 siblings, 0 replies; 9+ messages in thread From: Bjorn Andersson @ 2022-04-19 17:16 UTC (permalink / raw) To: Dmitry Baryshkov Cc: Andy Gross, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, Vladimir Zapolskiy On Sun 10 Apr 18:44 CDT 2022, Dmitry Baryshkov wrote: > Follow the lead of other Qualcomm platforms and add cooling maps for CPU > trip points. Handle three clusters separately, cooling cores 0-3 for > cpu0-3 trip points, cores 4-6 for cpu4-6 trip points and only cpu7 for > cpu7 trip points. > In line with 52e3b2ca6f9d ("arm64: dts: qcom: sdm845: Remove cpufreq cooling devices for CPU thermal zones") I don't think we should have cooling-maps for platforms where LMh is already thermal throttling the CPU clusters. Picking the other two patches. Regards, Bjorn > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 191 +++++++++++++++++++++++++++ > 1 file changed, 191 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 4f3c7e7d2855..dd8ef4438fd0 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -1651,6 +1651,21 @@ cpu4_top_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu4_top_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu4_top_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cpu4-bottom-thermal { > @@ -1677,6 +1692,21 @@ cpu4_bottom_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu4_bottom_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu4_bottom_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cpu5-top-thermal { > @@ -1703,6 +1733,21 @@ cpu5_top_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu5_top_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu5_top_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cpu5-bottom-thermal { > @@ -1729,6 +1774,21 @@ cpu5_bottom_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu5_bottom_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu5_bottom_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cpu6-top-thermal { > @@ -1755,6 +1815,21 @@ cpu6_top_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu6_top_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu6_top_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cpu6-bottom-thermal { > @@ -1781,6 +1856,21 @@ cpu6_bottom_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu6_bottom_alert0>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu6_bottom_alert1>; > + cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cpu7-top-thermal { > @@ -1807,6 +1897,17 @@ cpu7_top_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu7_top_alert0>; > + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu7_top_alert1>; > + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cpu7-middle-thermal { > @@ -1833,6 +1934,17 @@ cpu7_middle_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu7_middle_alert0>; > + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu7_middle_alert1>; > + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cpu7-bottom-thermal { > @@ -1859,6 +1971,17 @@ cpu7_bottom_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu7_bottom_alert0>; > + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu7_bottom_alert1>; > + cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > gpu-top-thermal { > @@ -1969,6 +2092,23 @@ cpu0_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu0_alert0>; > + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu0_alert1>; > + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cpu1-thermal { > @@ -1995,6 +2135,23 @@ cpu1_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu1_alert0>; > + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu1_alert1>; > + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cpu2-thermal { > @@ -2021,6 +2178,23 @@ cpu2_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu2_alert0>; > + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu2_alert1>; > + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cpu3-thermal { > @@ -2047,6 +2221,23 @@ cpu3_crit: cpu_crit { > type = "critical"; > }; > }; > + > + cooling-maps { > + map0 { > + trip = <&cpu3_alert0>; > + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + map1 { > + trip = <&cpu3_alert1>; > + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > + }; > + }; > }; > > cdsp0-thermal { > -- > 2.35.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-04-21 14:27 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-10 23:44 [PATCH 0/3] arm64: dts: qcom: sm8450: add thermal zones and cooling maps Dmitry Baryshkov 2022-04-10 23:44 ` [PATCH 1/3] arm64: dts: qcom: sm8450: Add thermal sensor controllers Dmitry Baryshkov 2022-04-12 19:39 ` Dmitry Baryshkov 2022-04-19 17:34 ` Bjorn Andersson 2022-04-21 14:26 ` (subset) " Bjorn Andersson 2022-04-10 23:44 ` [PATCH 2/3] arm64: dts: qcom: sm8450: Add thermal zones Dmitry Baryshkov 2022-04-21 14:26 ` (subset) " Bjorn Andersson 2022-04-10 23:44 ` [PATCH 3/3] arm64: dts: qcom: sm8450: add cooling-maps to CPU trip points Dmitry Baryshkov 2022-04-19 17:16 ` Bjorn Andersson
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