* [PATCH 0/3] RISC-V: Add Bitmanip/Scalar Crypto HWCAP @ 2022-04-30 13:48 ` Hongren (Zenithal) Zheng 0 siblings, 0 replies; 12+ messages in thread From: Hongren (Zenithal) Zheng @ 2022-04-30 13:48 UTC (permalink / raw) To: Palmer Dabbelt, Paul Walmsley, Albert Ou Cc: Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-riscv, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He This patchset proposes a currently viable and forward compatible way to expose the bitmanip/scalar crypto capability of the platform to the userspace. Currently viable refers to the property that hardware platforms can easily modify the riscv,isa field in DT to tell the kernel it has the capability. Note that QEMU has already done so in its device tree. Forward compatible refers to the property that userspace can still detect the capability of the environment by using HWCAP regardless of how the mechanism changes below kernel in the future. I do know that it has not been settled how to discover a capability, but I think kernel has to offer some API after all, and HWCAP is the preferred way among other mechanisms for now. More discussion on userspace discovering can be found on my PR to openssl https://github.com/openssl/openssl/pull/18197 Hongren (Zenithal) Zheng (3): RISC-V: add Bitmanip/Scalar Crypto parsing from DT RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto RISC-V: HWCAP: parse Bitmanip/Scalar Crypto HWCAP from DT arch/riscv/include/asm/elf.h | 2 + arch/riscv/include/asm/hwcap.h | 16 ++++++ arch/riscv/include/uapi/asm/hwcap.h | 22 ++++++++ arch/riscv/kernel/cpu.c | 14 +++++ arch/riscv/kernel/cpufeature.c | 79 +++++++++++++++++++++++++---- 5 files changed, 123 insertions(+), 10 deletions(-) -- 2.35.1 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 0/3] RISC-V: Add Bitmanip/Scalar Crypto HWCAP @ 2022-04-30 13:48 ` Hongren (Zenithal) Zheng 0 siblings, 0 replies; 12+ messages in thread From: Hongren (Zenithal) Zheng @ 2022-04-30 13:48 UTC (permalink / raw) To: Palmer Dabbelt, Paul Walmsley, Albert Ou Cc: Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-riscv, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He This patchset proposes a currently viable and forward compatible way to expose the bitmanip/scalar crypto capability of the platform to the userspace. Currently viable refers to the property that hardware platforms can easily modify the riscv,isa field in DT to tell the kernel it has the capability. Note that QEMU has already done so in its device tree. Forward compatible refers to the property that userspace can still detect the capability of the environment by using HWCAP regardless of how the mechanism changes below kernel in the future. I do know that it has not been settled how to discover a capability, but I think kernel has to offer some API after all, and HWCAP is the preferred way among other mechanisms for now. More discussion on userspace discovering can be found on my PR to openssl https://github.com/openssl/openssl/pull/18197 Hongren (Zenithal) Zheng (3): RISC-V: add Bitmanip/Scalar Crypto parsing from DT RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto RISC-V: HWCAP: parse Bitmanip/Scalar Crypto HWCAP from DT arch/riscv/include/asm/elf.h | 2 + arch/riscv/include/asm/hwcap.h | 16 ++++++ arch/riscv/include/uapi/asm/hwcap.h | 22 ++++++++ arch/riscv/kernel/cpu.c | 14 +++++ arch/riscv/kernel/cpufeature.c | 79 +++++++++++++++++++++++++---- 5 files changed, 123 insertions(+), 10 deletions(-) -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT 2022-04-30 13:48 ` Hongren (Zenithal) Zheng @ 2022-04-30 13:50 ` Hongren (Zenithal) Zheng -1 siblings, 0 replies; 12+ messages in thread From: Hongren (Zenithal) Zheng @ 2022-04-30 13:50 UTC (permalink / raw) To: Palmer Dabbelt, Paul Walmsley, Albert Ou Cc: Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-riscv, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He This commit parses Zb/Zk related string from DT and output them in cpuinfo One thing worth noting is that if DT provides zk, all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled. Note that zk is a valid extension name and the current DT binding spec allows this. There currently lacks a mechanism to merge them when producing cpuinfo. Namely if you provide a riscv,isa "rv64imafdc_zk_zks", the cpuinfo output would be "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed _zksh_zkt" Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> --- arch/riscv/include/asm/hwcap.h | 14 ++++++++++++++ arch/riscv/kernel/cpu.c | 14 ++++++++++++++ arch/riscv/kernel/cpufeature.c | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 0734e42f74f2..199eda39e0b8 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -52,6 +52,20 @@ extern unsigned long elf_hwcap; */ enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, + RISCV_ISA_EXT_ZBA, + RISCV_ISA_EXT_ZBB, + RISCV_ISA_EXT_ZBC, + RISCV_ISA_EXT_ZBS, + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZBKX, + RISCV_ISA_EXT_ZKNE, + RISCV_ISA_EXT_ZKND, + RISCV_ISA_EXT_ZKNH, + RISCV_ISA_EXT_ZKSED, + RISCV_ISA_EXT_ZKSH, + RISCV_ISA_EXT_ZKR, + RISCV_ISA_EXT_ZKT, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ccb617791e56..7251336969c1 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -87,6 +87,20 @@ int riscv_of_parent_hartid(struct device_node *node) * extensions by an underscore. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b2d42d7f589..10f9daf3734e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -192,6 +192,39 @@ void __init riscv_fill_hwcap(void) set_bit(*ext - 'a', this_isa); } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); + SET_ISA_EXT_MAP("zba" , RISCV_ISA_EXT_ZBA ); + SET_ISA_EXT_MAP("zbb" , RISCV_ISA_EXT_ZBB ); + SET_ISA_EXT_MAP("zbc" , RISCV_ISA_EXT_ZBC ); + SET_ISA_EXT_MAP("zbs" , RISCV_ISA_EXT_ZBS ); + SET_ISA_EXT_MAP("zbkb" , RISCV_ISA_EXT_ZBKB ); + SET_ISA_EXT_MAP("zbkc" , RISCV_ISA_EXT_ZBKC ); + SET_ISA_EXT_MAP("zbks" , RISCV_ISA_EXT_ZBKX ); + SET_ISA_EXT_MAP("zknd" , RISCV_ISA_EXT_ZKND ); + SET_ISA_EXT_MAP("zkne" , RISCV_ISA_EXT_ZKNE ); + SET_ISA_EXT_MAP("zknh" , RISCV_ISA_EXT_ZKNH ); + SET_ISA_EXT_MAP("zksed" , RISCV_ISA_EXT_ZKSED ); + SET_ISA_EXT_MAP("zksh" , RISCV_ISA_EXT_ZKSH ); + SET_ISA_EXT_MAP("zkr" , RISCV_ISA_EXT_ZKR ); + SET_ISA_EXT_MAP("zkt" , RISCV_ISA_EXT_ZKT ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKB ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKC ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKX ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKND ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNE ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNH ); + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKB ); + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKC ); + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKX ); + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSED ); + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSH ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKB ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKC ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKX ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKND ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNE ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNH ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKR ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKT ); } #undef SET_ISA_EXT_MAP } -- 2.35.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT @ 2022-04-30 13:50 ` Hongren (Zenithal) Zheng 0 siblings, 0 replies; 12+ messages in thread From: Hongren (Zenithal) Zheng @ 2022-04-30 13:50 UTC (permalink / raw) To: Palmer Dabbelt, Paul Walmsley, Albert Ou Cc: Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-riscv, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He This commit parses Zb/Zk related string from DT and output them in cpuinfo One thing worth noting is that if DT provides zk, all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled. Note that zk is a valid extension name and the current DT binding spec allows this. There currently lacks a mechanism to merge them when producing cpuinfo. Namely if you provide a riscv,isa "rv64imafdc_zk_zks", the cpuinfo output would be "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed _zksh_zkt" Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> --- arch/riscv/include/asm/hwcap.h | 14 ++++++++++++++ arch/riscv/kernel/cpu.c | 14 ++++++++++++++ arch/riscv/kernel/cpufeature.c | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 0734e42f74f2..199eda39e0b8 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -52,6 +52,20 @@ extern unsigned long elf_hwcap; */ enum riscv_isa_ext_id { RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, + RISCV_ISA_EXT_ZBA, + RISCV_ISA_EXT_ZBB, + RISCV_ISA_EXT_ZBC, + RISCV_ISA_EXT_ZBS, + RISCV_ISA_EXT_ZBKB, + RISCV_ISA_EXT_ZBKC, + RISCV_ISA_EXT_ZBKX, + RISCV_ISA_EXT_ZKNE, + RISCV_ISA_EXT_ZKND, + RISCV_ISA_EXT_ZKNH, + RISCV_ISA_EXT_ZKSED, + RISCV_ISA_EXT_ZKSH, + RISCV_ISA_EXT_ZKR, + RISCV_ISA_EXT_ZKT, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index ccb617791e56..7251336969c1 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -87,6 +87,20 @@ int riscv_of_parent_hartid(struct device_node *node) * extensions by an underscore. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1b2d42d7f589..10f9daf3734e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -192,6 +192,39 @@ void __init riscv_fill_hwcap(void) set_bit(*ext - 'a', this_isa); } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); + SET_ISA_EXT_MAP("zba" , RISCV_ISA_EXT_ZBA ); + SET_ISA_EXT_MAP("zbb" , RISCV_ISA_EXT_ZBB ); + SET_ISA_EXT_MAP("zbc" , RISCV_ISA_EXT_ZBC ); + SET_ISA_EXT_MAP("zbs" , RISCV_ISA_EXT_ZBS ); + SET_ISA_EXT_MAP("zbkb" , RISCV_ISA_EXT_ZBKB ); + SET_ISA_EXT_MAP("zbkc" , RISCV_ISA_EXT_ZBKC ); + SET_ISA_EXT_MAP("zbks" , RISCV_ISA_EXT_ZBKX ); + SET_ISA_EXT_MAP("zknd" , RISCV_ISA_EXT_ZKND ); + SET_ISA_EXT_MAP("zkne" , RISCV_ISA_EXT_ZKNE ); + SET_ISA_EXT_MAP("zknh" , RISCV_ISA_EXT_ZKNH ); + SET_ISA_EXT_MAP("zksed" , RISCV_ISA_EXT_ZKSED ); + SET_ISA_EXT_MAP("zksh" , RISCV_ISA_EXT_ZKSH ); + SET_ISA_EXT_MAP("zkr" , RISCV_ISA_EXT_ZKR ); + SET_ISA_EXT_MAP("zkt" , RISCV_ISA_EXT_ZKT ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKB ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKC ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKX ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKND ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNE ); + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNH ); + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKB ); + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKC ); + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKX ); + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSED ); + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSH ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKB ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKC ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKX ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKND ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNE ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNH ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKR ); + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKT ); } #undef SET_ISA_EXT_MAP } -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT 2022-04-30 13:50 ` Hongren (Zenithal) Zheng @ 2022-05-03 23:21 ` Heiko Stuebner -1 siblings, 0 replies; 12+ messages in thread From: Heiko Stuebner @ 2022-05-03 23:21 UTC (permalink / raw) To: Palmer Dabbelt, Paul Walmsley, Albert Ou, linux-riscv Cc: Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-riscv, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He, Hongren (Zenithal) Zheng Am Samstag, 30. April 2022, 15:50:22 CEST schrieb Hongren (Zenithal) Zheng: > This commit parses Zb/Zk related string from DT and > output them in cpuinfo > > One thing worth noting is that if DT provides zk, > all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled. > > Note that zk is a valid extension name and the current > DT binding spec allows this. > > There currently lacks a mechanism to merge them when > producing cpuinfo. Namely if you provide a riscv,isa > "rv64imafdc_zk_zks", the cpuinfo output would be > "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed > _zksh_zkt" > > Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> > Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> > --- > arch/riscv/include/asm/hwcap.h | 14 ++++++++++++++ > arch/riscv/kernel/cpu.c | 14 ++++++++++++++ > arch/riscv/kernel/cpufeature.c | 33 +++++++++++++++++++++++++++++++++ > 3 files changed, 61 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 0734e42f74f2..199eda39e0b8 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -52,6 +52,20 @@ extern unsigned long elf_hwcap; > */ > enum riscv_isa_ext_id { > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > + RISCV_ISA_EXT_ZBA, > + RISCV_ISA_EXT_ZBB, > + RISCV_ISA_EXT_ZBC, > + RISCV_ISA_EXT_ZBS, > + RISCV_ISA_EXT_ZBKB, > + RISCV_ISA_EXT_ZBKC, > + RISCV_ISA_EXT_ZBKX, > + RISCV_ISA_EXT_ZKNE, > + RISCV_ISA_EXT_ZKND, > + RISCV_ISA_EXT_ZKNH, > + RISCV_ISA_EXT_ZKSED, > + RISCV_ISA_EXT_ZKSH, > + RISCV_ISA_EXT_ZKR, > + RISCV_ISA_EXT_ZKT, > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index ccb617791e56..7251336969c1 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -87,6 +87,20 @@ int riscv_of_parent_hartid(struct device_node *node) > * extensions by an underscore. > */ > static struct riscv_isa_ext_data isa_ext_arr[] = { > + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), > + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), > + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), > + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), > + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), > + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), > + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), > + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), > + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), > + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), > + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), > + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), > + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), I guess a bit of sorting rule might be helpful, here it's the additions above sscofpmf while in the enum it's the other way around. As the list will get a long longer over time, I guess consistency might improve readability. > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), > }; > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1b2d42d7f589..10f9daf3734e 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -192,6 +192,39 @@ void __init riscv_fill_hwcap(void) > set_bit(*ext - 'a', this_isa); > } else { > SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); > + SET_ISA_EXT_MAP("zba" , RISCV_ISA_EXT_ZBA ); not sure if the additional whitespaces are really necessary? [especially the ones at the end] What did checkpatch have to say about them? > + SET_ISA_EXT_MAP("zbb" , RISCV_ISA_EXT_ZBB ); > + SET_ISA_EXT_MAP("zbc" , RISCV_ISA_EXT_ZBC ); > + SET_ISA_EXT_MAP("zbs" , RISCV_ISA_EXT_ZBS ); > + SET_ISA_EXT_MAP("zbkb" , RISCV_ISA_EXT_ZBKB ); > + SET_ISA_EXT_MAP("zbkc" , RISCV_ISA_EXT_ZBKC ); > + SET_ISA_EXT_MAP("zbks" , RISCV_ISA_EXT_ZBKX ); > + SET_ISA_EXT_MAP("zknd" , RISCV_ISA_EXT_ZKND ); > + SET_ISA_EXT_MAP("zkne" , RISCV_ISA_EXT_ZKNE ); > + SET_ISA_EXT_MAP("zknh" , RISCV_ISA_EXT_ZKNH ); > + SET_ISA_EXT_MAP("zksed" , RISCV_ISA_EXT_ZKSED ); > + SET_ISA_EXT_MAP("zksh" , RISCV_ISA_EXT_ZKSH ); > + SET_ISA_EXT_MAP("zkr" , RISCV_ISA_EXT_ZKR ); > + SET_ISA_EXT_MAP("zkt" , RISCV_ISA_EXT_ZKT ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKB ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKC ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKX ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKND ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNE ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNH ); > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKB ); > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKC ); > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKX ); > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSED ); > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSH ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKB ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKC ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKX ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKND ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNE ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNH ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKR ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKT ); > } > #undef SET_ISA_EXT_MAP > } > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT @ 2022-05-03 23:21 ` Heiko Stuebner 0 siblings, 0 replies; 12+ messages in thread From: Heiko Stuebner @ 2022-05-03 23:21 UTC (permalink / raw) To: Palmer Dabbelt, Paul Walmsley, Albert Ou, linux-riscv Cc: Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-riscv, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He, Hongren (Zenithal) Zheng Am Samstag, 30. April 2022, 15:50:22 CEST schrieb Hongren (Zenithal) Zheng: > This commit parses Zb/Zk related string from DT and > output them in cpuinfo > > One thing worth noting is that if DT provides zk, > all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled. > > Note that zk is a valid extension name and the current > DT binding spec allows this. > > There currently lacks a mechanism to merge them when > producing cpuinfo. Namely if you provide a riscv,isa > "rv64imafdc_zk_zks", the cpuinfo output would be > "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed > _zksh_zkt" > > Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> > Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> > --- > arch/riscv/include/asm/hwcap.h | 14 ++++++++++++++ > arch/riscv/kernel/cpu.c | 14 ++++++++++++++ > arch/riscv/kernel/cpufeature.c | 33 +++++++++++++++++++++++++++++++++ > 3 files changed, 61 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 0734e42f74f2..199eda39e0b8 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -52,6 +52,20 @@ extern unsigned long elf_hwcap; > */ > enum riscv_isa_ext_id { > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > + RISCV_ISA_EXT_ZBA, > + RISCV_ISA_EXT_ZBB, > + RISCV_ISA_EXT_ZBC, > + RISCV_ISA_EXT_ZBS, > + RISCV_ISA_EXT_ZBKB, > + RISCV_ISA_EXT_ZBKC, > + RISCV_ISA_EXT_ZBKX, > + RISCV_ISA_EXT_ZKNE, > + RISCV_ISA_EXT_ZKND, > + RISCV_ISA_EXT_ZKNH, > + RISCV_ISA_EXT_ZKSED, > + RISCV_ISA_EXT_ZKSH, > + RISCV_ISA_EXT_ZKR, > + RISCV_ISA_EXT_ZKT, > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index ccb617791e56..7251336969c1 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -87,6 +87,20 @@ int riscv_of_parent_hartid(struct device_node *node) > * extensions by an underscore. > */ > static struct riscv_isa_ext_data isa_ext_arr[] = { > + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), > + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), > + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), > + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), > + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), > + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), > + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), > + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), > + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), > + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), > + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), > + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), > + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), I guess a bit of sorting rule might be helpful, here it's the additions above sscofpmf while in the enum it's the other way around. As the list will get a long longer over time, I guess consistency might improve readability. > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), > }; > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1b2d42d7f589..10f9daf3734e 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -192,6 +192,39 @@ void __init riscv_fill_hwcap(void) > set_bit(*ext - 'a', this_isa); > } else { > SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); > + SET_ISA_EXT_MAP("zba" , RISCV_ISA_EXT_ZBA ); not sure if the additional whitespaces are really necessary? [especially the ones at the end] What did checkpatch have to say about them? > + SET_ISA_EXT_MAP("zbb" , RISCV_ISA_EXT_ZBB ); > + SET_ISA_EXT_MAP("zbc" , RISCV_ISA_EXT_ZBC ); > + SET_ISA_EXT_MAP("zbs" , RISCV_ISA_EXT_ZBS ); > + SET_ISA_EXT_MAP("zbkb" , RISCV_ISA_EXT_ZBKB ); > + SET_ISA_EXT_MAP("zbkc" , RISCV_ISA_EXT_ZBKC ); > + SET_ISA_EXT_MAP("zbks" , RISCV_ISA_EXT_ZBKX ); > + SET_ISA_EXT_MAP("zknd" , RISCV_ISA_EXT_ZKND ); > + SET_ISA_EXT_MAP("zkne" , RISCV_ISA_EXT_ZKNE ); > + SET_ISA_EXT_MAP("zknh" , RISCV_ISA_EXT_ZKNH ); > + SET_ISA_EXT_MAP("zksed" , RISCV_ISA_EXT_ZKSED ); > + SET_ISA_EXT_MAP("zksh" , RISCV_ISA_EXT_ZKSH ); > + SET_ISA_EXT_MAP("zkr" , RISCV_ISA_EXT_ZKR ); > + SET_ISA_EXT_MAP("zkt" , RISCV_ISA_EXT_ZKT ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKB ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKC ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKX ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKND ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNE ); > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNH ); > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKB ); > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKC ); > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKX ); > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSED ); > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSH ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKB ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKC ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKX ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKND ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNE ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNH ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKR ); > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKT ); > } > #undef SET_ISA_EXT_MAP > } > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT 2022-05-03 23:21 ` Heiko Stuebner @ 2022-05-04 2:39 ` Hongren (Zenithal) Zheng -1 siblings, 0 replies; 12+ messages in thread From: Hongren (Zenithal) Zheng @ 2022-05-04 2:39 UTC (permalink / raw) To: Heiko Stuebner Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, linux-riscv, Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He On Wed, May 04, 2022 at 01:21:23AM +0200, Heiko Stuebner wrote: > Am Samstag, 30. April 2022, 15:50:22 CEST schrieb Hongren (Zenithal) Zheng: > > This commit parses Zb/Zk related string from DT and > > output them in cpuinfo > > > > One thing worth noting is that if DT provides zk, > > all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled. > > > > Note that zk is a valid extension name and the current > > DT binding spec allows this. > > > > There currently lacks a mechanism to merge them when > > producing cpuinfo. Namely if you provide a riscv,isa > > "rv64imafdc_zk_zks", the cpuinfo output would be > > "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed > > _zksh_zkt" > > > > Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> > > Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> > > --- > > arch/riscv/include/asm/hwcap.h | 14 ++++++++++++++ > > arch/riscv/kernel/cpu.c | 14 ++++++++++++++ > > arch/riscv/kernel/cpufeature.c | 33 +++++++++++++++++++++++++++++++++ > > 3 files changed, 61 insertions(+) > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index 0734e42f74f2..199eda39e0b8 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -52,6 +52,20 @@ extern unsigned long elf_hwcap; > > */ > > enum riscv_isa_ext_id { > > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > > + RISCV_ISA_EXT_ZBA, > > + RISCV_ISA_EXT_ZBB, > > + RISCV_ISA_EXT_ZBC, > > + RISCV_ISA_EXT_ZBS, > > + RISCV_ISA_EXT_ZBKB, > > + RISCV_ISA_EXT_ZBKC, > > + RISCV_ISA_EXT_ZBKX, > > + RISCV_ISA_EXT_ZKNE, > > + RISCV_ISA_EXT_ZKND, > > + RISCV_ISA_EXT_ZKNH, > > + RISCV_ISA_EXT_ZKSED, > > + RISCV_ISA_EXT_ZKSH, > > + RISCV_ISA_EXT_ZKR, > > + RISCV_ISA_EXT_ZKT, > > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > > }; > > > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > index ccb617791e56..7251336969c1 100644 > > --- a/arch/riscv/kernel/cpu.c > > +++ b/arch/riscv/kernel/cpu.c > > @@ -87,6 +87,20 @@ int riscv_of_parent_hartid(struct device_node *node) > > * extensions by an underscore. > > */ > > static struct riscv_isa_ext_data isa_ext_arr[] = { > > + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), > > + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > > + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), > > + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), > > + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), > > + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), > > + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), > > + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), > > + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), > > + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), > > + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), > > + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), > > + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), > > + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), > > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > > I guess a bit of sorting rule might be helpful, here it's the additions > above sscofpmf while in the enum it's the other way around. Here the order is defined by the rule that "Standard supervisor-level extensions (starts with 'S') should be listed after standard unprivileged extensions." You can see the comment above this snippet. You can also see the for loop in print_isa_ext. Although I do not know should I place 'Zbs' before 'Zbk*' or after them as 'Zbk*' belong to scalar crypto but they are prefixed with "b". It seems it is undecided now. In the enum it is sorted according to the logical id. As "This enum represent the logical ID" in arch/riscv/include/asm/hwcap.h said. > As the list will get a long longer over time, I guess consistency > might improve readability. Agreed. I think changing the internal logical id is acceptable for me and it brings no API change. I need feedback on whether I could change the logical id of the existing sscofpmf extension. > > > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), > > }; > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 1b2d42d7f589..10f9daf3734e 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -192,6 +192,39 @@ void __init riscv_fill_hwcap(void) > > set_bit(*ext - 'a', this_isa); > > } else { > > SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); > > + SET_ISA_EXT_MAP("zba" , RISCV_ISA_EXT_ZBA ); > > not sure if the additional whitespaces are really necessary? [especially the ones at the end] > What did checkpatch have to say about them? checkpatch did complain about them. Also checkpatch complaint about the style issue for PATCH 3/3. It's my fault not to check style before sending. Will fix the style issue in the next version. I think I'll send the next version after getting more feedbacks. > > > + SET_ISA_EXT_MAP("zbb" , RISCV_ISA_EXT_ZBB ); > > + SET_ISA_EXT_MAP("zbc" , RISCV_ISA_EXT_ZBC ); > > + SET_ISA_EXT_MAP("zbs" , RISCV_ISA_EXT_ZBS ); > > + SET_ISA_EXT_MAP("zbkb" , RISCV_ISA_EXT_ZBKB ); > > + SET_ISA_EXT_MAP("zbkc" , RISCV_ISA_EXT_ZBKC ); > > + SET_ISA_EXT_MAP("zbks" , RISCV_ISA_EXT_ZBKX ); > > + SET_ISA_EXT_MAP("zknd" , RISCV_ISA_EXT_ZKND ); > > + SET_ISA_EXT_MAP("zkne" , RISCV_ISA_EXT_ZKNE ); > > + SET_ISA_EXT_MAP("zknh" , RISCV_ISA_EXT_ZKNH ); > > + SET_ISA_EXT_MAP("zksed" , RISCV_ISA_EXT_ZKSED ); > > + SET_ISA_EXT_MAP("zksh" , RISCV_ISA_EXT_ZKSH ); > > + SET_ISA_EXT_MAP("zkr" , RISCV_ISA_EXT_ZKR ); > > + SET_ISA_EXT_MAP("zkt" , RISCV_ISA_EXT_ZKT ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKB ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKC ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKX ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKND ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNE ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNH ); > > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKB ); > > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKC ); > > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKX ); > > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSED ); > > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSH ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKB ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKC ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKX ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKND ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNE ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNH ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKR ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKT ); > > } > > #undef SET_ISA_EXT_MAP > > } > > > > > > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT @ 2022-05-04 2:39 ` Hongren (Zenithal) Zheng 0 siblings, 0 replies; 12+ messages in thread From: Hongren (Zenithal) Zheng @ 2022-05-04 2:39 UTC (permalink / raw) To: Heiko Stuebner Cc: Palmer Dabbelt, Paul Walmsley, Albert Ou, linux-riscv, Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He On Wed, May 04, 2022 at 01:21:23AM +0200, Heiko Stuebner wrote: > Am Samstag, 30. April 2022, 15:50:22 CEST schrieb Hongren (Zenithal) Zheng: > > This commit parses Zb/Zk related string from DT and > > output them in cpuinfo > > > > One thing worth noting is that if DT provides zk, > > all zbkb, zbkc, zbkx and zkn, zkr, zkt would be enabled. > > > > Note that zk is a valid extension name and the current > > DT binding spec allows this. > > > > There currently lacks a mechanism to merge them when > > producing cpuinfo. Namely if you provide a riscv,isa > > "rv64imafdc_zk_zks", the cpuinfo output would be > > "rv64imafdc_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zksed > > _zksh_zkt" > > > > Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> > > Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> > > --- > > arch/riscv/include/asm/hwcap.h | 14 ++++++++++++++ > > arch/riscv/kernel/cpu.c | 14 ++++++++++++++ > > arch/riscv/kernel/cpufeature.c | 33 +++++++++++++++++++++++++++++++++ > > 3 files changed, 61 insertions(+) > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index 0734e42f74f2..199eda39e0b8 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -52,6 +52,20 @@ extern unsigned long elf_hwcap; > > */ > > enum riscv_isa_ext_id { > > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, > > + RISCV_ISA_EXT_ZBA, > > + RISCV_ISA_EXT_ZBB, > > + RISCV_ISA_EXT_ZBC, > > + RISCV_ISA_EXT_ZBS, > > + RISCV_ISA_EXT_ZBKB, > > + RISCV_ISA_EXT_ZBKC, > > + RISCV_ISA_EXT_ZBKX, > > + RISCV_ISA_EXT_ZKNE, > > + RISCV_ISA_EXT_ZKND, > > + RISCV_ISA_EXT_ZKNH, > > + RISCV_ISA_EXT_ZKSED, > > + RISCV_ISA_EXT_ZKSH, > > + RISCV_ISA_EXT_ZKR, > > + RISCV_ISA_EXT_ZKT, > > RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, > > }; > > > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > index ccb617791e56..7251336969c1 100644 > > --- a/arch/riscv/kernel/cpu.c > > +++ b/arch/riscv/kernel/cpu.c > > @@ -87,6 +87,20 @@ int riscv_of_parent_hartid(struct device_node *node) > > * extensions by an underscore. > > */ > > static struct riscv_isa_ext_data isa_ext_arr[] = { > > + __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), > > + __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > > + __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), > > + __RISCV_ISA_EXT_DATA(zbkb, RISCV_ISA_EXT_ZBKB), > > + __RISCV_ISA_EXT_DATA(zbkc, RISCV_ISA_EXT_ZBKC), > > + __RISCV_ISA_EXT_DATA(zbkx, RISCV_ISA_EXT_ZBKX), > > + __RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS), > > + __RISCV_ISA_EXT_DATA(zknd, RISCV_ISA_EXT_ZKND), > > + __RISCV_ISA_EXT_DATA(zkne, RISCV_ISA_EXT_ZKNE), > > + __RISCV_ISA_EXT_DATA(zknh, RISCV_ISA_EXT_ZKNH), > > + __RISCV_ISA_EXT_DATA(zkr, RISCV_ISA_EXT_ZKR), > > + __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), > > + __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), > > + __RISCV_ISA_EXT_DATA(zkt, RISCV_ISA_EXT_ZKT), > > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > > I guess a bit of sorting rule might be helpful, here it's the additions > above sscofpmf while in the enum it's the other way around. Here the order is defined by the rule that "Standard supervisor-level extensions (starts with 'S') should be listed after standard unprivileged extensions." You can see the comment above this snippet. You can also see the for loop in print_isa_ext. Although I do not know should I place 'Zbs' before 'Zbk*' or after them as 'Zbk*' belong to scalar crypto but they are prefixed with "b". It seems it is undecided now. In the enum it is sorted according to the logical id. As "This enum represent the logical ID" in arch/riscv/include/asm/hwcap.h said. > As the list will get a long longer over time, I guess consistency > might improve readability. Agreed. I think changing the internal logical id is acceptable for me and it brings no API change. I need feedback on whether I could change the logical id of the existing sscofpmf extension. > > > __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), > > }; > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 1b2d42d7f589..10f9daf3734e 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -192,6 +192,39 @@ void __init riscv_fill_hwcap(void) > > set_bit(*ext - 'a', this_isa); > > } else { > > SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); > > + SET_ISA_EXT_MAP("zba" , RISCV_ISA_EXT_ZBA ); > > not sure if the additional whitespaces are really necessary? [especially the ones at the end] > What did checkpatch have to say about them? checkpatch did complain about them. Also checkpatch complaint about the style issue for PATCH 3/3. It's my fault not to check style before sending. Will fix the style issue in the next version. I think I'll send the next version after getting more feedbacks. > > > + SET_ISA_EXT_MAP("zbb" , RISCV_ISA_EXT_ZBB ); > > + SET_ISA_EXT_MAP("zbc" , RISCV_ISA_EXT_ZBC ); > > + SET_ISA_EXT_MAP("zbs" , RISCV_ISA_EXT_ZBS ); > > + SET_ISA_EXT_MAP("zbkb" , RISCV_ISA_EXT_ZBKB ); > > + SET_ISA_EXT_MAP("zbkc" , RISCV_ISA_EXT_ZBKC ); > > + SET_ISA_EXT_MAP("zbks" , RISCV_ISA_EXT_ZBKX ); > > + SET_ISA_EXT_MAP("zknd" , RISCV_ISA_EXT_ZKND ); > > + SET_ISA_EXT_MAP("zkne" , RISCV_ISA_EXT_ZKNE ); > > + SET_ISA_EXT_MAP("zknh" , RISCV_ISA_EXT_ZKNH ); > > + SET_ISA_EXT_MAP("zksed" , RISCV_ISA_EXT_ZKSED ); > > + SET_ISA_EXT_MAP("zksh" , RISCV_ISA_EXT_ZKSH ); > > + SET_ISA_EXT_MAP("zkr" , RISCV_ISA_EXT_ZKR ); > > + SET_ISA_EXT_MAP("zkt" , RISCV_ISA_EXT_ZKT ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKB ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKC ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZBKX ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKND ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNE ); > > + SET_ISA_EXT_MAP("zkn" , RISCV_ISA_EXT_ZKNH ); > > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKB ); > > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKC ); > > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZBKX ); > > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSED ); > > + SET_ISA_EXT_MAP("zks" , RISCV_ISA_EXT_ZKSH ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKB ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKC ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZBKX ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKND ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNE ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKNH ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKR ); > > + SET_ISA_EXT_MAP("zk" , RISCV_ISA_EXT_ZKT ); > > } > > #undef SET_ISA_EXT_MAP > > } > > > > > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 2/3] RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto 2022-04-30 13:48 ` Hongren (Zenithal) Zheng @ 2022-04-30 13:51 ` Hongren (Zenithal) Zheng -1 siblings, 0 replies; 12+ messages in thread From: Hongren (Zenithal) Zheng @ 2022-04-30 13:51 UTC (permalink / raw) To: Palmer Dabbelt, Paul Walmsley, Albert Ou Cc: Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-riscv, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He userspace currently lacks a way to detect whether the platform has Bitmanip/Scalar Crypto capability, this commit provides a way such that the userspace can detect it. RISC-V currently still has no mature mechanism, but no matter how things in the spec changes, (no matter how "M" mode things change), the kernel still needs to offer some API to the userspace. More discussion can be found at https://github.com/openssl/openssl/pull/18197 Userspace currently has to use env var to detect them. This commit along does not assume any specific mechanism below kernel. Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> --- arch/riscv/include/uapi/asm/hwcap.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h index 46dc3f5ee99f..bfed3e5c338c 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -22,4 +22,26 @@ #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +/* + * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2 + * + * As only 32 bits of elf_hwcap (in kernel) could be used + * and RISC-V has reserved 26 bits of it, other caps like + * bitmanip and crypto can not be placed in AT_HWCAP + */ +#define COMPAT_HWCAP2_ISA_ZBA (1 << 0) +#define COMPAT_HWCAP2_ISA_ZBB (1 << 1) +#define COMPAT_HWCAP2_ISA_ZBC (1 << 2) +#define COMPAT_HWCAP2_ISA_ZBS (1 << 3) +#define COMPAT_HWCAP2_ISA_ZBKB (1 << 4) +#define COMPAT_HWCAP2_ISA_ZBKC (1 << 5) +#define COMPAT_HWCAP2_ISA_ZBKX (1 << 6) +#define COMPAT_HWCAP2_ISA_ZKND (1 << 7) +#define COMPAT_HWCAP2_ISA_ZKNE (1 << 8) +#define COMPAT_HWCAP2_ISA_ZKNH (1 << 9) +#define COMPAT_HWCAP2_ISA_ZKSED (1 << 10) +#define COMPAT_HWCAP2_ISA_ZKSH (1 << 11) +#define COMPAT_HWCAP2_ISA_ZKR (1 << 12) +#define COMPAT_HWCAP2_ISA_ZKT (1 << 13) + #endif /* _UAPI_ASM_RISCV_HWCAP_H */ -- 2.35.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/3] RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto @ 2022-04-30 13:51 ` Hongren (Zenithal) Zheng 0 siblings, 0 replies; 12+ messages in thread From: Hongren (Zenithal) Zheng @ 2022-04-30 13:51 UTC (permalink / raw) To: Palmer Dabbelt, Paul Walmsley, Albert Ou Cc: Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-riscv, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He userspace currently lacks a way to detect whether the platform has Bitmanip/Scalar Crypto capability, this commit provides a way such that the userspace can detect it. RISC-V currently still has no mature mechanism, but no matter how things in the spec changes, (no matter how "M" mode things change), the kernel still needs to offer some API to the userspace. More discussion can be found at https://github.com/openssl/openssl/pull/18197 Userspace currently has to use env var to detect them. This commit along does not assume any specific mechanism below kernel. Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> --- arch/riscv/include/uapi/asm/hwcap.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h index 46dc3f5ee99f..bfed3e5c338c 100644 --- a/arch/riscv/include/uapi/asm/hwcap.h +++ b/arch/riscv/include/uapi/asm/hwcap.h @@ -22,4 +22,26 @@ #define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) #define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +/* + * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2 + * + * As only 32 bits of elf_hwcap (in kernel) could be used + * and RISC-V has reserved 26 bits of it, other caps like + * bitmanip and crypto can not be placed in AT_HWCAP + */ +#define COMPAT_HWCAP2_ISA_ZBA (1 << 0) +#define COMPAT_HWCAP2_ISA_ZBB (1 << 1) +#define COMPAT_HWCAP2_ISA_ZBC (1 << 2) +#define COMPAT_HWCAP2_ISA_ZBS (1 << 3) +#define COMPAT_HWCAP2_ISA_ZBKB (1 << 4) +#define COMPAT_HWCAP2_ISA_ZBKC (1 << 5) +#define COMPAT_HWCAP2_ISA_ZBKX (1 << 6) +#define COMPAT_HWCAP2_ISA_ZKND (1 << 7) +#define COMPAT_HWCAP2_ISA_ZKNE (1 << 8) +#define COMPAT_HWCAP2_ISA_ZKNH (1 << 9) +#define COMPAT_HWCAP2_ISA_ZKSED (1 << 10) +#define COMPAT_HWCAP2_ISA_ZKSH (1 << 11) +#define COMPAT_HWCAP2_ISA_ZKR (1 << 12) +#define COMPAT_HWCAP2_ISA_ZKT (1 << 13) + #endif /* _UAPI_ASM_RISCV_HWCAP_H */ -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/3] RISC-V: HWCAP: parse Bitmanip/Scalar Crypto HWCAP from DT 2022-04-30 13:48 ` Hongren (Zenithal) Zheng @ 2022-04-30 13:51 ` Hongren (Zenithal) Zheng -1 siblings, 0 replies; 12+ messages in thread From: Hongren (Zenithal) Zheng @ 2022-04-30 13:51 UTC (permalink / raw) To: Palmer Dabbelt, Paul Walmsley, Albert Ou Cc: Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-riscv, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He One viable way to detect Zb/Zk HWCAP is from the DT binding. No matter how the "M" mode things change, this way can always be an auxiliary way to detect it. Note that QEMU currently has "zba/zbb/zbc/zbs" in their device tree riscv,isa This also fixes the isa2hwcap way as using unsigned char for long extension is not viable. Note that the tolower function ensures functionality. For other no-hwcap extension (e.g. h, s, u), or ("|") with 0 has no effect on hwcap. Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> --- arch/riscv/include/asm/elf.h | 2 ++ arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 46 ++++++++++++++++++++++++++-------- 3 files changed, 40 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index f53c40026c7a..c6a4d8d2a241 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -51,7 +51,9 @@ * but it's not easy, and we've already done it here. */ #define ELF_HWCAP (elf_hwcap) +#define ELF_HWCAP2 (elf_hwcap2) extern unsigned long elf_hwcap; +extern unsigned long elf_hwcap2; /* * This yields a string that ld.so will use to load implementation diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 199eda39e0b8..357b0481f1d0 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -17,12 +17,14 @@ * instruction set this cpu supports. */ #define ELF_HWCAP (elf_hwcap) +#define ELF_HWCAP2 (elf_hwcap2) enum { CAP_HWCAP = 1, }; extern unsigned long elf_hwcap; +extern unsigned long elf_hwcap2; #define RISCV_ISA_EXT_a ('a' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 10f9daf3734e..f3a033bb51f5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -17,6 +17,7 @@ #define NUM_ALPHA_EXTS ('z' - 'a' + 1) unsigned long elf_hwcap __read_mostly; +unsigned long elf_hwcap2 __read_mostly; /* Host ISA bitmap */ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; @@ -68,21 +69,39 @@ void __init riscv_fill_hwcap(void) const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; int i, j; - static unsigned long isa2hwcap[256] = {0}; + static unsigned long isa2hwcap[RISCV_ISA_EXT_MAX] = {0}; - isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; - isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M; - isa2hwcap['a'] = isa2hwcap['A'] = COMPAT_HWCAP_ISA_A; - isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F; - isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D; - isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C; + /* HWCAP */ + isa2hwcap[RISCV_ISA_EXT_i] = COMPAT_HWCAP_ISA_I; + isa2hwcap[RISCV_ISA_EXT_m] = COMPAT_HWCAP_ISA_M; + isa2hwcap[RISCV_ISA_EXT_a] = COMPAT_HWCAP_ISA_A; + isa2hwcap[RISCV_ISA_EXT_f] = COMPAT_HWCAP_ISA_F; + isa2hwcap[RISCV_ISA_EXT_d] = COMPAT_HWCAP_ISA_D; + isa2hwcap[RISCV_ISA_EXT_c] = COMPAT_HWCAP_ISA_C; + /* HWCAP2 */ + isa2hwcap[RISCV_ISA_EXT_ZBA ] = COMPAT_HWCAP2_ISA_ZBA; + isa2hwcap[RISCV_ISA_EXT_ZBB ] = COMPAT_HWCAP2_ISA_ZBB; + isa2hwcap[RISCV_ISA_EXT_ZBC ] = COMPAT_HWCAP2_ISA_ZBC; + isa2hwcap[RISCV_ISA_EXT_ZBS ] = COMPAT_HWCAP2_ISA_ZBS; + isa2hwcap[RISCV_ISA_EXT_ZBKB ] = COMPAT_HWCAP2_ISA_ZBKB; + isa2hwcap[RISCV_ISA_EXT_ZBKC ] = COMPAT_HWCAP2_ISA_ZBKC; + isa2hwcap[RISCV_ISA_EXT_ZBKX ] = COMPAT_HWCAP2_ISA_ZBKX; + isa2hwcap[RISCV_ISA_EXT_ZKNE ] = COMPAT_HWCAP2_ISA_ZKND; + isa2hwcap[RISCV_ISA_EXT_ZKND ] = COMPAT_HWCAP2_ISA_ZKNE; + isa2hwcap[RISCV_ISA_EXT_ZKNH ] = COMPAT_HWCAP2_ISA_ZKNH; + isa2hwcap[RISCV_ISA_EXT_ZKSED] = COMPAT_HWCAP2_ISA_ZKSED; + isa2hwcap[RISCV_ISA_EXT_ZKSH ] = COMPAT_HWCAP2_ISA_ZKSH; + isa2hwcap[RISCV_ISA_EXT_ZKR ] = COMPAT_HWCAP2_ISA_ZKR; + isa2hwcap[RISCV_ISA_EXT_ZKT ] = COMPAT_HWCAP2_ISA_ZKT; elf_hwcap = 0; + elf_hwcap2 = 0; bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; + unsigned long this_hwcap2 = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; @@ -181,15 +200,17 @@ void __init riscv_fill_hwcap(void) #define SET_ISA_EXT_MAP(name, bit) \ do { \ if ((ext_end - ext == sizeof(name) - 1) && \ - !memcmp(ext, name, sizeof(name) - 1)) \ + !memcmp(ext, name, sizeof(name) - 1)) { \ + this_hwcap2 |= isa2hwcap[bit]; \ set_bit(bit, this_isa); \ + } \ } while (false) \ if (unlikely(ext_err)) continue; if (!ext_long) { - this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; - set_bit(*ext - 'a', this_isa); + this_hwcap |= isa2hwcap[tolower(*ext) - 'a']; + set_bit(tolower(*ext) - 'a', this_isa); } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("zba" , RISCV_ISA_EXT_ZBA ); @@ -239,6 +260,11 @@ void __init riscv_fill_hwcap(void) else elf_hwcap = this_hwcap; + if (elf_hwcap2) + elf_hwcap2 &= this_hwcap2; + else + elf_hwcap2 = this_hwcap2; + if (bitmap_weight(riscv_isa, RISCV_ISA_EXT_MAX)) bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); else -- 2.35.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/3] RISC-V: HWCAP: parse Bitmanip/Scalar Crypto HWCAP from DT @ 2022-04-30 13:51 ` Hongren (Zenithal) Zheng 0 siblings, 0 replies; 12+ messages in thread From: Hongren (Zenithal) Zheng @ 2022-04-30 13:51 UTC (permalink / raw) To: Palmer Dabbelt, Paul Walmsley, Albert Ou Cc: Atish Patra, Anup Patel, Eric Biederman, Kees Cook, linux-mm, linux-riscv, linux-kernel, linux-api, Michael Kerrisk, linux-man, Jiatai He One viable way to detect Zb/Zk HWCAP is from the DT binding. No matter how the "M" mode things change, this way can always be an auxiliary way to detect it. Note that QEMU currently has "zba/zbb/zbc/zbs" in their device tree riscv,isa This also fixes the isa2hwcap way as using unsigned char for long extension is not viable. Note that the tolower function ensures functionality. For other no-hwcap extension (e.g. h, s, u), or ("|") with 0 has no effect on hwcap. Tested-by: Jiatai He <jiatai2021@iscas.ac.cn> Signed-off-by: Hongren (Zenithal) Zheng <i@zenithal.me> --- arch/riscv/include/asm/elf.h | 2 ++ arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 46 ++++++++++++++++++++++++++-------- 3 files changed, 40 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/elf.h b/arch/riscv/include/asm/elf.h index f53c40026c7a..c6a4d8d2a241 100644 --- a/arch/riscv/include/asm/elf.h +++ b/arch/riscv/include/asm/elf.h @@ -51,7 +51,9 @@ * but it's not easy, and we've already done it here. */ #define ELF_HWCAP (elf_hwcap) +#define ELF_HWCAP2 (elf_hwcap2) extern unsigned long elf_hwcap; +extern unsigned long elf_hwcap2; /* * This yields a string that ld.so will use to load implementation diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 199eda39e0b8..357b0481f1d0 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -17,12 +17,14 @@ * instruction set this cpu supports. */ #define ELF_HWCAP (elf_hwcap) +#define ELF_HWCAP2 (elf_hwcap2) enum { CAP_HWCAP = 1, }; extern unsigned long elf_hwcap; +extern unsigned long elf_hwcap2; #define RISCV_ISA_EXT_a ('a' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 10f9daf3734e..f3a033bb51f5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -17,6 +17,7 @@ #define NUM_ALPHA_EXTS ('z' - 'a' + 1) unsigned long elf_hwcap __read_mostly; +unsigned long elf_hwcap2 __read_mostly; /* Host ISA bitmap */ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; @@ -68,21 +69,39 @@ void __init riscv_fill_hwcap(void) const char *isa; char print_str[NUM_ALPHA_EXTS + 1]; int i, j; - static unsigned long isa2hwcap[256] = {0}; + static unsigned long isa2hwcap[RISCV_ISA_EXT_MAX] = {0}; - isa2hwcap['i'] = isa2hwcap['I'] = COMPAT_HWCAP_ISA_I; - isa2hwcap['m'] = isa2hwcap['M'] = COMPAT_HWCAP_ISA_M; - isa2hwcap['a'] = isa2hwcap['A'] = COMPAT_HWCAP_ISA_A; - isa2hwcap['f'] = isa2hwcap['F'] = COMPAT_HWCAP_ISA_F; - isa2hwcap['d'] = isa2hwcap['D'] = COMPAT_HWCAP_ISA_D; - isa2hwcap['c'] = isa2hwcap['C'] = COMPAT_HWCAP_ISA_C; + /* HWCAP */ + isa2hwcap[RISCV_ISA_EXT_i] = COMPAT_HWCAP_ISA_I; + isa2hwcap[RISCV_ISA_EXT_m] = COMPAT_HWCAP_ISA_M; + isa2hwcap[RISCV_ISA_EXT_a] = COMPAT_HWCAP_ISA_A; + isa2hwcap[RISCV_ISA_EXT_f] = COMPAT_HWCAP_ISA_F; + isa2hwcap[RISCV_ISA_EXT_d] = COMPAT_HWCAP_ISA_D; + isa2hwcap[RISCV_ISA_EXT_c] = COMPAT_HWCAP_ISA_C; + /* HWCAP2 */ + isa2hwcap[RISCV_ISA_EXT_ZBA ] = COMPAT_HWCAP2_ISA_ZBA; + isa2hwcap[RISCV_ISA_EXT_ZBB ] = COMPAT_HWCAP2_ISA_ZBB; + isa2hwcap[RISCV_ISA_EXT_ZBC ] = COMPAT_HWCAP2_ISA_ZBC; + isa2hwcap[RISCV_ISA_EXT_ZBS ] = COMPAT_HWCAP2_ISA_ZBS; + isa2hwcap[RISCV_ISA_EXT_ZBKB ] = COMPAT_HWCAP2_ISA_ZBKB; + isa2hwcap[RISCV_ISA_EXT_ZBKC ] = COMPAT_HWCAP2_ISA_ZBKC; + isa2hwcap[RISCV_ISA_EXT_ZBKX ] = COMPAT_HWCAP2_ISA_ZBKX; + isa2hwcap[RISCV_ISA_EXT_ZKNE ] = COMPAT_HWCAP2_ISA_ZKND; + isa2hwcap[RISCV_ISA_EXT_ZKND ] = COMPAT_HWCAP2_ISA_ZKNE; + isa2hwcap[RISCV_ISA_EXT_ZKNH ] = COMPAT_HWCAP2_ISA_ZKNH; + isa2hwcap[RISCV_ISA_EXT_ZKSED] = COMPAT_HWCAP2_ISA_ZKSED; + isa2hwcap[RISCV_ISA_EXT_ZKSH ] = COMPAT_HWCAP2_ISA_ZKSH; + isa2hwcap[RISCV_ISA_EXT_ZKR ] = COMPAT_HWCAP2_ISA_ZKR; + isa2hwcap[RISCV_ISA_EXT_ZKT ] = COMPAT_HWCAP2_ISA_ZKT; elf_hwcap = 0; + elf_hwcap2 = 0; bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; + unsigned long this_hwcap2 = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; @@ -181,15 +200,17 @@ void __init riscv_fill_hwcap(void) #define SET_ISA_EXT_MAP(name, bit) \ do { \ if ((ext_end - ext == sizeof(name) - 1) && \ - !memcmp(ext, name, sizeof(name) - 1)) \ + !memcmp(ext, name, sizeof(name) - 1)) { \ + this_hwcap2 |= isa2hwcap[bit]; \ set_bit(bit, this_isa); \ + } \ } while (false) \ if (unlikely(ext_err)) continue; if (!ext_long) { - this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; - set_bit(*ext - 'a', this_isa); + this_hwcap |= isa2hwcap[tolower(*ext) - 'a']; + set_bit(tolower(*ext) - 'a', this_isa); } else { SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("zba" , RISCV_ISA_EXT_ZBA ); @@ -239,6 +260,11 @@ void __init riscv_fill_hwcap(void) else elf_hwcap = this_hwcap; + if (elf_hwcap2) + elf_hwcap2 &= this_hwcap2; + else + elf_hwcap2 = this_hwcap2; + if (bitmap_weight(riscv_isa, RISCV_ISA_EXT_MAX)) bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); else -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-05-04 2:40 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-30 13:48 [PATCH 0/3] RISC-V: Add Bitmanip/Scalar Crypto HWCAP Hongren (Zenithal) Zheng 2022-04-30 13:48 ` Hongren (Zenithal) Zheng 2022-04-30 13:50 ` [PATCH 1/3] RISC-V: add Bitmanip/Scalar Crypto parsing from DT Hongren (Zenithal) Zheng 2022-04-30 13:50 ` Hongren (Zenithal) Zheng 2022-05-03 23:21 ` Heiko Stuebner 2022-05-03 23:21 ` Heiko Stuebner 2022-05-04 2:39 ` Hongren (Zenithal) Zheng 2022-05-04 2:39 ` Hongren (Zenithal) Zheng 2022-04-30 13:51 ` [PATCH 2/3] RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto Hongren (Zenithal) Zheng 2022-04-30 13:51 ` Hongren (Zenithal) Zheng 2022-04-30 13:51 ` [PATCH 3/3] RISC-V: HWCAP: parse Bitmanip/Scalar Crypto HWCAP from DT Hongren (Zenithal) Zheng 2022-04-30 13:51 ` Hongren (Zenithal) Zheng
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