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From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 6/8] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1
Date: Thu, 21 Apr 2022 10:58:12 +0100	[thread overview]
Message-ID: <YmEqtGIdTnP0wiGj@FVFF77S0Q05N> (raw)
In-Reply-To: <20220419104329.188489-7-broonie@kernel.org>

On Tue, Apr 19, 2022 at 11:43:27AM +0100, Mark Brown wrote:
> Remove the manual definitions for ID_AA64ISAR0_EL1 in favour of automatic
> generation. There should be no functional change. Other notable changes:
> 
>  - 27:24 TME is defined rather than RES0 reflecting DDI0487H.a.

Nice!

>  - 23:20 Atomic is named "atomics" reflecting existing usage.

Can we fix the "Atomic" field to match the architectural name with a
preparatory patch? That'd be a nice cleanup regardless of the scripting, since
the matching name will make it easier to search for in the ARM ARM, and it
looks like that's simple enough that we could get that through now (ahead of
even adding the _EL1 part to the name).

With that additional fix:

Acked-by: Mark Rutland <mark.rutland@arm.com>

Thanks,
Mark.

> 
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
>  arch/arm64/include/asm/sysreg.h | 20 ----------
>  arch/arm64/tools/sysreg         | 67 +++++++++++++++++++++++++++++++++
>  2 files changed, 67 insertions(+), 20 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 11bf3636c741..2b5cc67b3bc3 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -196,7 +196,6 @@
>  #define SYS_ID_AA64AFR0_EL1		sys_reg(3, 0, 0, 5, 4)
>  #define SYS_ID_AA64AFR1_EL1		sys_reg(3, 0, 0, 5, 5)
>  
> -#define SYS_ID_AA64ISAR0_EL1		sys_reg(3, 0, 0, 6, 0)
>  #define SYS_ID_AA64ISAR1_EL1		sys_reg(3, 0, 0, 6, 1)
>  #define SYS_ID_AA64ISAR2_EL1		sys_reg(3, 0, 0, 6, 2)
>  
> @@ -736,25 +735,6 @@
>  /* Position the attr at the correct index */
>  #define MAIR_ATTRIDX(attr, idx)		((attr) << ((idx) * 8))
>  
> -/* id_aa64isar0 */
> -#define ID_AA64ISAR0_EL1_RNDR_SHIFT		60
> -#define ID_AA64ISAR0_EL1_TLB_SHIFT		56
> -#define ID_AA64ISAR0_EL1_TS_SHIFT		52
> -#define ID_AA64ISAR0_EL1_FHM_SHIFT		48
> -#define ID_AA64ISAR0_EL1_DP_SHIFT		44
> -#define ID_AA64ISAR0_EL1_SM4_SHIFT		40
> -#define ID_AA64ISAR0_EL1_SM3_SHIFT		36
> -#define ID_AA64ISAR0_EL1_SHA3_SHIFT		32
> -#define ID_AA64ISAR0_EL1_RDM_SHIFT		28
> -#define ID_AA64ISAR0_EL1_ATOMICS_SHIFT		20
> -#define ID_AA64ISAR0_EL1_CRC32_SHIFT		16
> -#define ID_AA64ISAR0_EL1_SHA2_SHIFT		12
> -#define ID_AA64ISAR0_EL1_SHA1_SHIFT		8
> -#define ID_AA64ISAR0_EL1_AES_SHIFT		4
> -
> -#define ID_AA64ISAR0_EL1_TLB_RANGE_NI		0x0
> -#define ID_AA64ISAR0_EL1_TLB_RANGE		0x2
> -
>  /* id_aa64isar1 */
>  #define ID_AA64ISAR1_I8MM_SHIFT		52
>  #define ID_AA64ISAR1_DGH_SHIFT		48
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 3595c68b9a0b..040745387528 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -32,3 +32,70 @@
>  # feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration
>  # item ACCDATA) though it may be more taseful to do something else.
>  
> +Sysreg	ID_AA64ISAR0_EL1	3	0	0	6	0
> +Enum	63:60	RNDR
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	59:56	TLB
> +	0b0000	NI
> +	0b0001	OS
> +	0b0010	RANGE
> +EndEnum
> +Enum	55:52	TS
> +	0b0000	NI
> +	0b0001	FLAGM
> +	0b0010	FLAGM2
> +EndEnum
> +Enum	51:48	FHM
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	47:44	DP
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	43:40	SM4
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	39:36	SM3
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	35:32	SHA3
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	31:28	RDM
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	27:24	TME
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	23:20	ATOMICS
> +	0b0000	NI
> +	0b0010	IMP
> +EndEnum
> +Enum	19:16	CRC32
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	15:12	SHA2
> +	0b0000	NI
> +	0b0001	SHA256
> +	0b0010	SHA512
> +EndEnum
> +Enum	11:8	SHA1
> +	0b0000	NI
> +	0b0001	IMP
> +EndEnum
> +Enum	7:4	AES
> +	0b0000	NI
> +	0b0001	AES
> +	0b0010	PMULL
> +EndEnum
> +Res0	3:0
> +EndSysreg
> -- 
> 2.30.2
> 

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  reply	other threads:[~2022-04-21  9:59 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-19 10:43 [PATCH v4 0/8] arm64: Automatic system register definition generation Mark Brown
2022-04-19 10:43 ` [PATCH v4 1/8] arm64/mte: Move shift from definition of TCF0 enumeration values Mark Brown
2022-04-21  9:33   ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 2/8] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Mark Brown
2022-04-21  9:35   ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 3/8] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI Mark Brown
2022-04-21  9:36   ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 4/8] arm64: Add sysreg header generation scripting Mark Brown
2022-04-21  9:47   ` Mark Rutland
2022-04-21 13:00     ` Mark Brown
2022-04-21 14:16       ` Mark Rutland
2022-04-21 14:50         ` Mark Brown
2022-04-21 15:35           ` Mark Rutland
2022-04-21 15:46             ` Mark Brown
2022-04-19 10:43 ` [PATCH v4 5/8] arm64/sysreg: Enable automatic generation of system register definitions Mark Brown
2022-04-21  9:52   ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 6/8] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Mark Brown
2022-04-21  9:58   ` Mark Rutland [this message]
2022-04-19 10:43 ` [PATCH v4 7/8] arm64/sysreg: Generate definitions for TTBRn_EL1 Mark Brown
2022-04-21  9:59   ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 8/8] arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Brown
2022-04-21 10:05   ` Mark Rutland
2022-04-22 12:14     ` Mark Brown
2022-04-22 13:42       ` Mark Rutland
2022-04-22 13:50         ` Mark Brown
2022-04-21 10:15 ` [PATCH v4 0/8] arm64: Automatic system register definition generation Mark Rutland
2022-04-21 15:14   ` Mark Brown

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