From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 8/8] arm64/sysreg: Generate definitions for SCTLR_EL1
Date: Thu, 21 Apr 2022 11:05:27 +0100 [thread overview]
Message-ID: <YmEsZ/Ec1KubN045@FVFF77S0Q05N> (raw)
In-Reply-To: <20220419104329.188489-9-broonie@kernel.org>
On Tue, Apr 19, 2022 at 11:43:29AM +0100, Mark Brown wrote:
> Automatically generate register definitions for SCTLR_EL1. No functional
> change.
>
> Several fields which are defined in the current revision of DDI0487 but
> which are not yet used by the kernel are left as RES1 in order to ensure
> that the SCTLR_EL1_RES1 mask used for early initialisation of SCTLR_EL1 is
> not changed. These are LSMAOE, nTLSMD, EIS, TSCXT and EOS.
I think that going forward we'll hit similar issues when adding new fields, so
we probably want to distinguish "architecturally RESx" and "The kernel wants to
treat these as RESx".
I suspect we should add those fields to the scripting, but (manually) add a
definition to a header with both the architectural RES1 bits and the bits we're
treating as RES1 even though they're now been allocated a purpose.
I'm not sure how to name that clearly, though.
Otherwise, this looks good to me.
Thanks,
Mark.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 29 --------------
> arch/arm64/tools/sysreg | 70 +++++++++++++++++++++++++++++++++
> 2 files changed, 70 insertions(+), 29 deletions(-)
>
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index b9023797a5b9..63b545260e62 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -203,7 +203,6 @@
> #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
> #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
>
> -#define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
> #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
> #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
> #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
> @@ -679,34 +678,6 @@
> (SCTLR_EL2_RES1 | ENDIAN_SET_EL2)
>
> /* SCTLR_EL1 specific flags. */
> -#define SCTLR_EL1_EPAN (BIT(57))
> -#define SCTLR_EL1_ATA0 (BIT(42))
> -
> -#define SCTLR_EL1_TCF0_SHIFT 38
> -#define SCTLR_EL1_TCF0_NONE UL(0x0)
> -#define SCTLR_EL1_TCF0_SYNC UL(0x1)
> -#define SCTLR_EL1_TCF0_ASYNC UL(0x2)
> -#define SCTLR_EL1_TCF0_ASYMM UL(0x3)
> -#define SCTLR_EL1_TCF0_MASK (UL(0x3) << SCTLR_EL1_TCF0_SHIFT)
> -
> -#define SCTLR_EL1_BT1 (BIT(36))
> -#define SCTLR_EL1_BT0 (BIT(35))
> -#define SCTLR_EL1_UCI (BIT(26))
> -#define SCTLR_EL1_E0E (BIT(24))
> -#define SCTLR_EL1_SPAN (BIT(23))
> -#define SCTLR_EL1_nTWE (BIT(18))
> -#define SCTLR_EL1_nTWI (BIT(16))
> -#define SCTLR_EL1_UCT (BIT(15))
> -#define SCTLR_EL1_DZE (BIT(14))
> -#define SCTLR_EL1_UMA (BIT(9))
> -#define SCTLR_EL1_SED (BIT(8))
> -#define SCTLR_EL1_ITD (BIT(7))
> -#define SCTLR_EL1_CP15BEN (BIT(5))
> -#define SCTLR_EL1_SA0 (BIT(4))
> -
> -#define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \
> - (BIT(29)))
> -
> #ifdef CONFIG_CPU_BIG_ENDIAN
> #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
> #else
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index f6195ccbf9b8..6248cfbf5288 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -100,6 +100,76 @@ EndEnum
> Res0 3:0
> EndSysreg
>
> +Sysreg SCTLR_EL1 3 0 1 9 9
> +Field 63 TIDCP
> +Field 62 SPINMASK
> +Field 61 NMI
> +Field 60 EnTP2
> +Res0 59:58
> +Field 57 EPAN
> +Field 56 EnALS
> +Field 55 EnAS0
> +Field 54 EnASR
> +Field 53 TME
> +Field 52 TME0
> +Field 51 TMT
> +Field 50 TMT0
> +Field 49:46 TWEDEL
> +Field 45 TWEDEn
> +Field 44 DSSBS
> +Field 43 ATA
> +Field 42 ATA0
> +Enum 41:40 TCF
> + 0b00 NONE
> + 0b01 SYNC
> + 0b10 ASYNC
> + 0b11 ASYMM
> +EndEnum
> +Enum 39:38 TCF0
> + 0b00 NONE
> + 0b01 SYNC
> + 0b10 ASYNC
> + 0b11 ASYMM
> +EndEnum
> +Field 37 ITFSB
> +Field 36 BT1
> +Field 35 BT0
> +Res0 34
> +Field 33 MSCEn
> +Field 32 CMOW
> +Field 31 EnIA
> +Field 30 EnIB
> +Res1 29:28
> +Field 27 EnDA
> +Field 26 UCI
> +Field 25 EE
> +Field 24 E0E
> +Field 23 SPAN
> +Res1 22
> +Field 21 IESB
> +Res1 20
> +Field 19 WXN
> +Field 18 nTWE
> +Res0 17
> +Field 16 nTWI
> +Field 15 UCT
> +Field 14 DZE
> +Field 13 EnDB
> +Field 12 I
> +Res1 11
> +Field 10 EnRCTX
> +Field 9 UMA
> +Field 8 SED
> +Field 7 ITD
> +Field 6 nAA
> +Field 5 CP15BEN
> +Field 4 SA0
> +Field 3 SA
> +Field 2 C
> +Field 1 A
> +Field 0 M
> +EndSysreg
> +
> Sysreg TTBR0_EL1 3 0 2 0 0
> Field 63:48 ASID
> Field 47:1 BADDR
> --
> 2.30.2
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-04-21 10:06 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-19 10:43 [PATCH v4 0/8] arm64: Automatic system register definition generation Mark Brown
2022-04-19 10:43 ` [PATCH v4 1/8] arm64/mte: Move shift from definition of TCF0 enumeration values Mark Brown
2022-04-21 9:33 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 2/8] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Mark Brown
2022-04-21 9:35 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 3/8] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI Mark Brown
2022-04-21 9:36 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 4/8] arm64: Add sysreg header generation scripting Mark Brown
2022-04-21 9:47 ` Mark Rutland
2022-04-21 13:00 ` Mark Brown
2022-04-21 14:16 ` Mark Rutland
2022-04-21 14:50 ` Mark Brown
2022-04-21 15:35 ` Mark Rutland
2022-04-21 15:46 ` Mark Brown
2022-04-19 10:43 ` [PATCH v4 5/8] arm64/sysreg: Enable automatic generation of system register definitions Mark Brown
2022-04-21 9:52 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 6/8] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Mark Brown
2022-04-21 9:58 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 7/8] arm64/sysreg: Generate definitions for TTBRn_EL1 Mark Brown
2022-04-21 9:59 ` Mark Rutland
2022-04-19 10:43 ` [PATCH v4 8/8] arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Brown
2022-04-21 10:05 ` Mark Rutland [this message]
2022-04-22 12:14 ` Mark Brown
2022-04-22 13:42 ` Mark Rutland
2022-04-22 13:50 ` Mark Brown
2022-04-21 10:15 ` [PATCH v4 0/8] arm64: Automatic system register definition generation Mark Rutland
2022-04-21 15:14 ` Mark Brown
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YmEsZ/Ec1KubN045@FVFF77S0Q05N \
--to=mark.rutland@arm.com \
--cc=broonie@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=maz@kernel.org \
--cc=suzuki.poulose@arm.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.