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* [igt-dev] [PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines
@ 2022-04-04 17:18 Zbigniew Kempczyński
  2022-04-04 18:12 ` [igt-dev] ✗ GitLab.Pipeline: warning for " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 9+ messages in thread
From: Zbigniew Kempczyński @ 2022-04-04 17:18 UTC (permalink / raw)
  To: igt-dev; +Cc: Thomas Hellström

Test verifies does eviction works when all engines try to use same
offset for different handles. It replaces allocator-evict-all-engines
test because it simpler version of it.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
 tests/i915/gem_softpin.c | 85 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 83 insertions(+), 2 deletions(-)

diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
index 34fc9983ff..5945317ed1 100644
--- a/tests/i915/gem_softpin.c
+++ b/tests/i915/gem_softpin.c
@@ -1072,6 +1072,87 @@ static void test_allocator_evict(int fd, const intel_ctx_t *ctx,
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
+static void single_offset_submit(int fd, struct drm_i915_gem_execbuffer2 *eb,
+				 struct batch *batches, unsigned int count)
+{
+	struct drm_i915_gem_exec_object2 obj;
+	uint64_t address = max_t(uint64_t, gem_detect_safe_start_offset(fd), 0x200000);
+
+	memset(&obj, 0, sizeof(obj));
+	obj.flags = EXEC_OBJECT_PINNED;
+
+	for (unsigned int i = 0; i < count; i++) {
+		obj.handle = batches[i].handle;
+		obj.offset = address;
+		eb->buffers_ptr = to_user_pointer(&obj);
+		gem_execbuf(fd, eb);
+	}
+}
+
+static void evict_single_offset(int fd, const intel_ctx_t *ctx, int timeout)
+{
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct intel_execution_engine2 *e;
+	unsigned int engines[I915_EXEC_RING_MASK + 1];
+	struct batch *batches;
+	unsigned int nengine;
+	unsigned int count;
+	uint64_t size;
+
+	nengine = 0;
+	for_each_ctx_engine(fd, ctx, e) {
+		engines[nengine++] = e->flags;
+	}
+	igt_require(nengine);
+
+	size = gem_aperture_size(fd);
+	if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
+		size = 1ull << 32;
+	igt_require(size < (1ull<<32) * BATCH_SIZE);
+
+	count = size / BATCH_SIZE + 1;
+	igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
+		  count, (long long)size, nengine);
+
+	intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
+	intel_detect_and_clear_missed_interrupts(fd);
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffer_count = 1;
+	execbuf.rsvd1 = ctx->id;
+
+	batches = calloc(count, sizeof(*batches));
+	igt_assert(batches);
+	for (unsigned int i = 0; i < count; i++) {
+		uint32_t *p;
+
+		batches[i].handle = gem_create(fd, BATCH_SIZE);
+		batches[i].ptr =
+			gem_mmap__device_coherent(fd, batches[i].handle,
+						  0, BATCH_SIZE, PROT_WRITE);
+		p = batches[i].ptr + BATCH_SIZE - 8;
+		*p = MI_BATCH_BUFFER_END;
+	}
+
+	/* Flush all memory before we start the timer */
+	single_offset_submit(fd, &execbuf, batches, count);
+
+	igt_fork(child, nengine) {
+		execbuf.flags |= engines[child];
+		igt_until_timeout(timeout)
+			single_offset_submit(fd, &execbuf, batches, count);
+	}
+	igt_waitchildren();
+
+	for (unsigned int i = 0; i < count; i++) {
+		munmap(batches[i].ptr, BATCH_SIZE);
+		gem_close(fd, batches[i].handle);
+	}
+	free(batches);
+
+	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+}
+
 static void make_batch(int i915, uint32_t handle, uint64_t size)
 {
 	uint32_t *bb = gem_mmap__device_coherent(i915, handle, 0, size, PROT_WRITE);
@@ -1212,8 +1293,8 @@ igt_main
 		test_each_engine("allocator-evict", fd, ctx, e)
 			test_allocator_evict(fd, ctx, e->flags, 20);
 
-		igt_subtest("allocator-evict-all-engines")
-			test_allocator_evict(fd, ctx, ALL_ENGINES, 20);
+		igt_subtest("evict-single-offset")
+			evict_single_offset(fd, ctx, 20);
 	}
 
 	igt_describe("Check start offset and alignment detection");
-- 
2.32.0

^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [igt-dev] ✗ GitLab.Pipeline: warning for tests/i915/gem_softpin: Exercise single offset eviction on all engines
  2022-04-04 17:18 [igt-dev] [PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines Zbigniew Kempczyński
@ 2022-04-04 18:12 ` Patchwork
  2022-04-04 18:32 ` [igt-dev] ✗ Fi.CI.BAT: failure " Patchwork
  2022-04-05 18:28 ` [igt-dev] [PATCH i-g-t] " Kamil Konieczny
  2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-04-04 18:12 UTC (permalink / raw)
  To: Zbigniew Kempczyński; +Cc: igt-dev

== Series Details ==

Series: tests/i915/gem_softpin: Exercise single offset eviction on all engines
URL   : https://patchwork.freedesktop.org/series/102154/
State : warning

== Summary ==

Pipeline status: FAILED.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/550136 for the overview.

test:ninja-test-armhf has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/20691529):
  Ok:                   22
  Expected Fail:         3
  Fail:                287
  Unexpected Pass:       0
  Skipped:               0
  Timeout:               0
  
  Full log written to /builds/gfx-ci/igt-ci-tags/build/meson-logs/testlog.txt
  section_end:1649095790:step_script
  section_start:1649095790:upload_artifacts_on_failure
  Uploading artifacts for failed job
  Uploading artifacts...
  build: found 1713 matching files and directories   
  Uploading artifacts as "archive" to coordinator... 201 Created  id=20691529 responseStatus=201 Created token=sEh_QVUR
  section_end:1649095803:upload_artifacts_on_failure
  section_start:1649095803:cleanup_file_variables
  Cleaning up project directory and file based variables
  section_end:1649095806:cleanup_file_variables
  ERROR: Job failed: exit code 1

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/550136

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [igt-dev] ✗ Fi.CI.BAT: failure for tests/i915/gem_softpin: Exercise single offset eviction on all engines
  2022-04-04 17:18 [igt-dev] [PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines Zbigniew Kempczyński
  2022-04-04 18:12 ` [igt-dev] ✗ GitLab.Pipeline: warning for " Patchwork
@ 2022-04-04 18:32 ` Patchwork
  2022-04-05 18:28 ` [igt-dev] [PATCH i-g-t] " Kamil Konieczny
  2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-04-04 18:32 UTC (permalink / raw)
  To: Zbigniew Kempczyński; +Cc: igt-dev

[-- Attachment #1: Type: text/plain, Size: 9503 bytes --]

== Series Details ==

Series: tests/i915/gem_softpin: Exercise single offset eviction on all engines
URL   : https://patchwork.freedesktop.org/series/102154/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11449 -> IGTPW_6871
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_6871 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_6871, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/index.html

Participating hosts (49 -> 46)
------------------------------

  Additional (1): fi-icl-u2 
  Missing    (4): fi-bsw-cyan shard-rkl shard-tglu fi-bdw-samus 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6871:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@slpc:
    - bat-dg1-5:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/bat-dg1-5/igt@i915_selftest@live@slpc.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/bat-dg1-5/igt@i915_selftest@live@slpc.html
    - bat-dg1-6:          NOTRUN -> [INCOMPLETE][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/bat-dg1-6/igt@i915_selftest@live@slpc.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_lmem_swapping@basic:
    - {fi-jsl-1}:         [SKIP][4] ([i915#4613]) -> [SKIP][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/fi-jsl-1/igt@gem_lmem_swapping@basic.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-jsl-1/igt@gem_lmem_swapping@basic.html

  
Known issues
------------

  Here are the changes found in IGTPW_6871 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
    - fi-icl-u2:          NOTRUN -> [SKIP][6] ([fdo#109315]) +17 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
    - fi-bsw-n3050:       NOTRUN -> [SKIP][7] ([fdo#109271]) +17 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-bsw-n3050/igt@amdgpu/amd_cs_nop@fork-gfx0.html

  * igt@gem_huc_copy@huc-copy:
    - fi-icl-u2:          NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-icl-u2/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-icl-u2:          NOTRUN -> [SKIP][9] ([i915#4613]) +3 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-4770:        [PASS][10] -> [INCOMPLETE][11] ([i915#4785])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          NOTRUN -> [SKIP][12] ([fdo#111827]) +8 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-icl-u2:          NOTRUN -> [SKIP][13] ([fdo#109278]) +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
    - fi-tgl-u2:          [PASS][14] -> [DMESG-WARN][15] ([i915#402])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-icl-u2:          NOTRUN -> [SKIP][16] ([fdo#109285])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-icl-u2:          NOTRUN -> [SKIP][17] ([i915#3555])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-userptr:
    - fi-icl-u2:          NOTRUN -> [SKIP][18] ([i915#3301])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-icl-u2/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-hsw-4770:        NOTRUN -> [FAIL][19] ([fdo#109271] / [i915#1436] / [i915#2722] / [i915#4312])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-hsw-4770/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@active:
    - fi-bsw-n3050:       [DMESG-FAIL][20] ([i915#2927]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/fi-bsw-n3050/igt@i915_selftest@live@active.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-bsw-n3050/igt@i915_selftest@live@active.html

  * igt@i915_selftest@live@gt_engines:
    - bat-dg1-6:          [INCOMPLETE][22] ([i915#4418]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/bat-dg1-6/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@hangcheck:
    - bat-dg1-5:          [DMESG-FAIL][24] ([i915#4494] / [i915#4957]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/bat-dg1-5/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@migrate:
    - fi-bsw-n3050:       [DMESG-WARN][26] -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/fi-bsw-n3050/igt@i915_selftest@live@migrate.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-bsw-n3050/igt@i915_selftest@live@migrate.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
    - fi-tgl-u2:          [DMESG-WARN][28] ([i915#402]) -> [PASS][29]
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/fi-tgl-u2/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/fi-tgl-u2/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
    - {bat-adlp-6}:       [DMESG-WARN][30] ([i915#3576]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6409 -> IGTPW_6871

  CI-20190529: 20190529
  CI_DRM_11449: 7f954433d09e65d55ca3ba81e1eb5eced93d4203 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6871: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/index.html
  IGT_6409: 13700f4a3ffaac3a825fe59b014c7c6c48a0a5f1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@gem_softpin@evict-single-offset
-igt@gem_softpin@allocator-evict-all-engines

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6871/index.html

[-- Attachment #2: Type: text/html, Size: 10455 bytes --]

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [igt-dev] [PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines
  2022-04-04 17:18 [igt-dev] [PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines Zbigniew Kempczyński
  2022-04-04 18:12 ` [igt-dev] ✗ GitLab.Pipeline: warning for " Patchwork
  2022-04-04 18:32 ` [igt-dev] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-04-05 18:28 ` Kamil Konieczny
  2022-04-27  6:03   ` Zbigniew Kempczyński
  2 siblings, 1 reply; 9+ messages in thread
From: Kamil Konieczny @ 2022-04-05 18:28 UTC (permalink / raw)
  To: igt-dev; +Cc: Thomas Hellström

Hi Zbigniew,

Dnia 2022-04-04 at 19:18:07 +0200, Zbigniew Kempczyński napisał(a):
> Test verifies does eviction works when all engines try to use same

s/Test verifies does/Verify that/

> offset for different handles. It replaces allocator-evict-all-engines
> test because it simpler version of it.

s/test/subtest/
s/because it simpler version of it./because it is simpler./

> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
>  tests/i915/gem_softpin.c | 85 +++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 83 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
> index 34fc9983ff..5945317ed1 100644
> --- a/tests/i915/gem_softpin.c
> +++ b/tests/i915/gem_softpin.c
> @@ -1072,6 +1072,87 @@ static void test_allocator_evict(int fd, const intel_ctx_t *ctx,
>  	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
>  }
>  
> +static void single_offset_submit(int fd, struct drm_i915_gem_execbuffer2 *eb,
> +				 struct batch *batches, unsigned int count)
> +{
> +	struct drm_i915_gem_exec_object2 obj;
> +	uint64_t address = max_t(uint64_t, gem_detect_safe_start_offset(fd), 0x200000);
---------------------------------------------------------------------------- ^
Shouldn't this be gem_detect_safe_alignment() ? Or #define and
describe it with comment or add comment here.
Another idea whould be to calculate it in evict_single_offset
before fork and pass it as parameter.

> +
> +	memset(&obj, 0, sizeof(obj));
> +	obj.flags = EXEC_OBJECT_PINNED;
> +
> +	for (unsigned int i = 0; i < count; i++) {
> +		obj.handle = batches[i].handle;
> +		obj.offset = address;
> +		eb->buffers_ptr = to_user_pointer(&obj);
> +		gem_execbuf(fd, eb);
> +	}
> +}
> +
> +static void evict_single_offset(int fd, const intel_ctx_t *ctx, int timeout)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	struct intel_execution_engine2 *e;
> +	unsigned int engines[I915_EXEC_RING_MASK + 1];
> +	struct batch *batches;
> +	unsigned int nengine;
> +	unsigned int count;
> +	uint64_t size;
> +
> +	nengine = 0;
> +	for_each_ctx_engine(fd, ctx, e) {
> +		engines[nengine++] = e->flags;
> +	}
> +	igt_require(nengine);
> +
> +	size = gem_aperture_size(fd);
> +	if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
> +		size = 1ull << 32;
> +	igt_require(size < (1ull<<32) * BATCH_SIZE);
> +
> +	count = size / BATCH_SIZE + 1;
> +	igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
> +		  count, (long long)size, nengine);
> +
> +	intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
> +	intel_detect_and_clear_missed_interrupts(fd);
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffer_count = 1;
> +	execbuf.rsvd1 = ctx->id;
> +
> +	batches = calloc(count, sizeof(*batches));
> +	igt_assert(batches);
> +	for (unsigned int i = 0; i < count; i++) {
> +		uint32_t *p;
> +
> +		batches[i].handle = gem_create(fd, BATCH_SIZE);
> +		batches[i].ptr =
> +			gem_mmap__device_coherent(fd, batches[i].handle,
> +						  0, BATCH_SIZE, PROT_WRITE);
> +		p = batches[i].ptr + BATCH_SIZE - 8;
> +		*p = MI_BATCH_BUFFER_END;
> +	}
> +
> +	/* Flush all memory before we start the timer */
> +	single_offset_submit(fd, &execbuf, batches, count);
> +
> +	igt_fork(child, nengine) {
> +		execbuf.flags |= engines[child];
> +		igt_until_timeout(timeout)
> +			single_offset_submit(fd, &execbuf, batches, count);
> +	}
> +	igt_waitchildren();
> +
> +	for (unsigned int i = 0; i < count; i++) {
> +		munmap(batches[i].ptr, BATCH_SIZE);
> +		gem_close(fd, batches[i].handle);
> +	}
> +	free(batches);
> +
> +	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> +}
> +
>  static void make_batch(int i915, uint32_t handle, uint64_t size)
>  {
>  	uint32_t *bb = gem_mmap__device_coherent(i915, handle, 0, size, PROT_WRITE);
> @@ -1212,8 +1293,8 @@ igt_main
>  		test_each_engine("allocator-evict", fd, ctx, e)
>  			test_allocator_evict(fd, ctx, e->flags, 20);
>  
> -		igt_subtest("allocator-evict-all-engines")
> -			test_allocator_evict(fd, ctx, ALL_ENGINES, 20);
> +		igt_subtest("evict-single-offset")
> +			evict_single_offset(fd, ctx, 20);

While you change it please add description before subtest.

Regards,
Kamil
>  	}
>  
>  	igt_describe("Check start offset and alignment detection");
> -- 
> 2.32.0
> 

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [igt-dev] [PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines
  2022-04-05 18:28 ` [igt-dev] [PATCH i-g-t] " Kamil Konieczny
@ 2022-04-27  6:03   ` Zbigniew Kempczyński
  0 siblings, 0 replies; 9+ messages in thread
From: Zbigniew Kempczyński @ 2022-04-27  6:03 UTC (permalink / raw)
  To: Kamil Konieczny, igt-dev, Thomas Hellström

On Tue, Apr 05, 2022 at 08:28:30PM +0200, Kamil Konieczny wrote:
> Hi Zbigniew,
> 
> Dnia 2022-04-04 at 19:18:07 +0200, Zbigniew Kempczyński napisał(a):
> > Test verifies does eviction works when all engines try to use same
> 
> s/Test verifies does/Verify that/
> 
> > offset for different handles. It replaces allocator-evict-all-engines
> > test because it simpler version of it.
> 
> s/test/subtest/
> s/because it simpler version of it./because it is simpler./
> 
> > 
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> > Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> > ---
> >  tests/i915/gem_softpin.c | 85 +++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 83 insertions(+), 2 deletions(-)
> > 
> > diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
> > index 34fc9983ff..5945317ed1 100644
> > --- a/tests/i915/gem_softpin.c
> > +++ b/tests/i915/gem_softpin.c
> > @@ -1072,6 +1072,87 @@ static void test_allocator_evict(int fd, const intel_ctx_t *ctx,
> >  	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> >  }
> >  
> > +static void single_offset_submit(int fd, struct drm_i915_gem_execbuffer2 *eb,
> > +				 struct batch *batches, unsigned int count)
> > +{
> > +	struct drm_i915_gem_exec_object2 obj;
> > +	uint64_t address = max_t(uint64_t, gem_detect_safe_start_offset(fd), 0x200000);
> ---------------------------------------------------------------------------- ^
> Shouldn't this be gem_detect_safe_alignment() ? Or #define and
> describe it with comment or add comment here.

No, in this subtest I want to reuse same offset. But I agree,
adding #define will make this constant more descriptive.

> Another idea whould be to calculate it in evict_single_offset
> before fork and pass it as parameter.

But this is "calculated" (probed) in gem_detect_safe_start_offset().
I don't want to be 0x0 as start offset so max_t() choose 2M offset
if minimal start offset is lesser than I want. 

> 
> > +
> > +	memset(&obj, 0, sizeof(obj));
> > +	obj.flags = EXEC_OBJECT_PINNED;
> > +
> > +	for (unsigned int i = 0; i < count; i++) {
> > +		obj.handle = batches[i].handle;
> > +		obj.offset = address;
> > +		eb->buffers_ptr = to_user_pointer(&obj);
> > +		gem_execbuf(fd, eb);
> > +	}
> > +}
> > +
> > +static void evict_single_offset(int fd, const intel_ctx_t *ctx, int timeout)
> > +{
> > +	struct drm_i915_gem_execbuffer2 execbuf;
> > +	struct intel_execution_engine2 *e;
> > +	unsigned int engines[I915_EXEC_RING_MASK + 1];
> > +	struct batch *batches;
> > +	unsigned int nengine;
> > +	unsigned int count;
> > +	uint64_t size;
> > +
> > +	nengine = 0;
> > +	for_each_ctx_engine(fd, ctx, e) {
> > +		engines[nengine++] = e->flags;
> > +	}
> > +	igt_require(nengine);
> > +
> > +	size = gem_aperture_size(fd);
> > +	if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
> > +		size = 1ull << 32;
> > +	igt_require(size < (1ull<<32) * BATCH_SIZE);
> > +
> > +	count = size / BATCH_SIZE + 1;
> > +	igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
> > +		  count, (long long)size, nengine);
> > +
> > +	intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
> > +	intel_detect_and_clear_missed_interrupts(fd);
> > +
> > +	memset(&execbuf, 0, sizeof(execbuf));
> > +	execbuf.buffer_count = 1;
> > +	execbuf.rsvd1 = ctx->id;
> > +
> > +	batches = calloc(count, sizeof(*batches));
> > +	igt_assert(batches);
> > +	for (unsigned int i = 0; i < count; i++) {
> > +		uint32_t *p;
> > +
> > +		batches[i].handle = gem_create(fd, BATCH_SIZE);
> > +		batches[i].ptr =
> > +			gem_mmap__device_coherent(fd, batches[i].handle,
> > +						  0, BATCH_SIZE, PROT_WRITE);
> > +		p = batches[i].ptr + BATCH_SIZE - 8;
> > +		*p = MI_BATCH_BUFFER_END;
> > +	}
> > +
> > +	/* Flush all memory before we start the timer */
> > +	single_offset_submit(fd, &execbuf, batches, count);
> > +
> > +	igt_fork(child, nengine) {
> > +		execbuf.flags |= engines[child];
> > +		igt_until_timeout(timeout)
> > +			single_offset_submit(fd, &execbuf, batches, count);
> > +	}
> > +	igt_waitchildren();
> > +
> > +	for (unsigned int i = 0; i < count; i++) {
> > +		munmap(batches[i].ptr, BATCH_SIZE);
> > +		gem_close(fd, batches[i].handle);
> > +	}
> > +	free(batches);
> > +
> > +	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> > +}
> > +
> >  static void make_batch(int i915, uint32_t handle, uint64_t size)
> >  {
> >  	uint32_t *bb = gem_mmap__device_coherent(i915, handle, 0, size, PROT_WRITE);
> > @@ -1212,8 +1293,8 @@ igt_main
> >  		test_each_engine("allocator-evict", fd, ctx, e)
> >  			test_allocator_evict(fd, ctx, e->flags, 20);
> >  
> > -		igt_subtest("allocator-evict-all-engines")
> > -			test_allocator_evict(fd, ctx, ALL_ENGINES, 20);
> > +		igt_subtest("evict-single-offset")
> > +			evict_single_offset(fd, ctx, 20);
> 
> While you change it please add description before subtest.

Ok, will be in v2.

--
Zbigniew

> 
> Regards,
> Kamil
> >  	}
> >  
> >  	igt_describe("Check start offset and alignment detection");
> > -- 
> > 2.32.0
> > 

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [igt-dev] [PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines
  2022-04-28 16:07 ` Kamil Konieczny
@ 2022-04-29  4:51   ` Zbigniew Kempczyński
  0 siblings, 0 replies; 9+ messages in thread
From: Zbigniew Kempczyński @ 2022-04-29  4:51 UTC (permalink / raw)
  To: Kamil Konieczny, igt-dev, Thomas Hellström

On Thu, Apr 28, 2022 at 06:07:50PM +0200, Kamil Konieczny wrote:
> Hi Zbigniew,
> 
> On 2022-04-27 at 20:42:04 +0200, Zbigniew Kempczyński wrote:
> > Verify that eviction works when all engines try to use same offset for
> > different handles. It replaces allocator-evict-all-engines test because
> > it is simpler.
> > 
> > v2: addressing review comments (Kamil)
> > v3: simplifying subtest (Chris)
> > 
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> > Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> > ---
> >  tests/i915/gem_softpin.c | 76 ++++++++++++++++++++++++++++++++++++++--
> >  1 file changed, 74 insertions(+), 2 deletions(-)
> > 
> > diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
> > index 448b4c4b9e..7dae2a6c44 100644
> > --- a/tests/i915/gem_softpin.c
> > +++ b/tests/i915/gem_softpin.c
> > @@ -1073,6 +1073,77 @@ static void test_allocator_evict(int fd, const intel_ctx_t *ctx,
> >  	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> >  }
> >  
> > +#define MINIMAL_OFFSET 0x200000
> > +static void single_offset_submit(int fd, struct drm_i915_gem_execbuffer2 *eb,
> > +				 struct batch *batches, unsigned int count)
> > +{
> > +	struct drm_i915_gem_exec_object2 obj = {
> > +		.offset = max_t(uint64_t, gem_detect_safe_start_offset(fd), MINIMAL_OFFSET),
> 
> imho this should be a parameter to this function, so it will be
> calculated once but you can leave it here, your choice.

Safe start offset is cached during first run so following calls returns
it from the cache, without further probing.

> 
> > +		.flags = EXEC_OBJECT_PINNED,
> > +	};
> > +
> > +	eb->buffers_ptr = to_user_pointer(&obj);
> > +
> > +	for (unsigned int i = 0; i < count; i++) {
> > +		obj.handle = batches[i].handle;
> > +		gem_execbuf(fd, eb);
> > +	}
> > +}
> > +
> > +static void evict_single_offset(int fd, const intel_ctx_t *ctx, int timeout)
> > +{
> > +	struct drm_i915_gem_execbuffer2 execbuf;
> > +	struct intel_execution_engine2 *e;
> > +	unsigned int engines[I915_EXEC_RING_MASK + 1];
> > +	struct batch *batches;
> > +	unsigned int nengine;
> > +	unsigned int count;
> > +	uint64_t size, batch_size = BATCH_SIZE;
> > +
> > +	nengine = 0;
> > +	for_each_ctx_engine(fd, ctx, e) {
> > +		engines[nengine++] = e->flags;
> > +	}
> > +	igt_require(nengine);
> > +
> > +	size = gem_aperture_size(fd);
> > +	if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
> > +		size = 1ull << 32;
> > +	igt_require(size < (1ull<<32) * BATCH_SIZE);
> > +
> > +	count = size / BATCH_SIZE + 1;
> > +	igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
> > +		  count, (long long)size, nengine);
> 
> Please add here print for timeout used and also change printing
> size to MB.

I understand you want to see this with --debug option? Ok, will add this
before merging.

> 
> > +
> > +	intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
> > +	intel_detect_and_clear_missed_interrupts(fd);
> > +
> > +	memset(&execbuf, 0, sizeof(execbuf));
> > +	execbuf.buffer_count = 1;
> > +	execbuf.rsvd1 = ctx->id;
> > +
> > +	batches = calloc(count, sizeof(*batches));
> > +	igt_assert(batches);
> > +	for (unsigned int i = 0; i < count; i++)
> > +		batches[i].handle = batch_create(fd, &batch_size);
> > +
> > +	/* Flush all memory before we start the timer */
> > +	single_offset_submit(fd, &execbuf, batches, count);
> > +
> > +	igt_fork(child, nengine) {
> > +		execbuf.flags |= engines[child];
> > +		igt_until_timeout(timeout)
> > +			single_offset_submit(fd, &execbuf, batches, count);
> > +	}
> > +	igt_waitchildren();
> > +
> > +	for (unsigned int i = 0; i < count; i++)
> > +		gem_close(fd, batches[i].handle);
> > +	free(batches);
> > +
> > +	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> > +}
> > +
> >  static void make_batch(int i915, uint32_t handle, uint64_t size)
> >  {
> >  	uint32_t *bb = gem_mmap__device_coherent(i915, handle, 0, size, PROT_WRITE);
> > @@ -1213,8 +1284,9 @@ igt_main
> >  		test_each_engine("allocator-evict", fd, ctx, e)
> >  			test_allocator_evict(fd, ctx, e->flags, 20);
> >  
> > -		igt_subtest("allocator-evict-all-engines")
> > -			test_allocator_evict(fd, ctx, ALL_ENGINES, 20);
> > +		igt_describe("Use same offset for all engines and for different handles");
> > +		igt_subtest("evict-single-offset")
> > +			evict_single_offset(fd, ctx, 20);
> 
> You are not using allocator here, so maybe move this down after
> evict-hog sibtest ?

Test need to be placed within 'gem_uses_full_ppgtt' group. We may argue
for the location, but I cannot move it outside it.

With above changes I'm going to take your r-b and merge.
--
Zbigniew

> 
> With that small changes you can add my r-b tag.
> 
> Regards,
> Kamil
> >  	}
> >  
> >  	igt_describe("Check start offset and alignment detection");
> > -- 
> > 2.32.0
> > 

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [igt-dev] [PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines
  2022-04-27 18:42 Zbigniew Kempczyński
@ 2022-04-28 16:07 ` Kamil Konieczny
  2022-04-29  4:51   ` Zbigniew Kempczyński
  0 siblings, 1 reply; 9+ messages in thread
From: Kamil Konieczny @ 2022-04-28 16:07 UTC (permalink / raw)
  To: igt-dev; +Cc: Thomas Hellström

Hi Zbigniew,

On 2022-04-27 at 20:42:04 +0200, Zbigniew Kempczyński wrote:
> Verify that eviction works when all engines try to use same offset for
> different handles. It replaces allocator-evict-all-engines test because
> it is simpler.
> 
> v2: addressing review comments (Kamil)
> v3: simplifying subtest (Chris)
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
>  tests/i915/gem_softpin.c | 76 ++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 74 insertions(+), 2 deletions(-)
> 
> diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
> index 448b4c4b9e..7dae2a6c44 100644
> --- a/tests/i915/gem_softpin.c
> +++ b/tests/i915/gem_softpin.c
> @@ -1073,6 +1073,77 @@ static void test_allocator_evict(int fd, const intel_ctx_t *ctx,
>  	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
>  }
>  
> +#define MINIMAL_OFFSET 0x200000
> +static void single_offset_submit(int fd, struct drm_i915_gem_execbuffer2 *eb,
> +				 struct batch *batches, unsigned int count)
> +{
> +	struct drm_i915_gem_exec_object2 obj = {
> +		.offset = max_t(uint64_t, gem_detect_safe_start_offset(fd), MINIMAL_OFFSET),

imho this should be a parameter to this function, so it will be
calculated once but you can leave it here, your choice.

> +		.flags = EXEC_OBJECT_PINNED,
> +	};
> +
> +	eb->buffers_ptr = to_user_pointer(&obj);
> +
> +	for (unsigned int i = 0; i < count; i++) {
> +		obj.handle = batches[i].handle;
> +		gem_execbuf(fd, eb);
> +	}
> +}
> +
> +static void evict_single_offset(int fd, const intel_ctx_t *ctx, int timeout)
> +{
> +	struct drm_i915_gem_execbuffer2 execbuf;
> +	struct intel_execution_engine2 *e;
> +	unsigned int engines[I915_EXEC_RING_MASK + 1];
> +	struct batch *batches;
> +	unsigned int nengine;
> +	unsigned int count;
> +	uint64_t size, batch_size = BATCH_SIZE;
> +
> +	nengine = 0;
> +	for_each_ctx_engine(fd, ctx, e) {
> +		engines[nengine++] = e->flags;
> +	}
> +	igt_require(nengine);
> +
> +	size = gem_aperture_size(fd);
> +	if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
> +		size = 1ull << 32;
> +	igt_require(size < (1ull<<32) * BATCH_SIZE);
> +
> +	count = size / BATCH_SIZE + 1;
> +	igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
> +		  count, (long long)size, nengine);

Please add here print for timeout used and also change printing
size to MB.

> +
> +	intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
> +	intel_detect_and_clear_missed_interrupts(fd);
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.buffer_count = 1;
> +	execbuf.rsvd1 = ctx->id;
> +
> +	batches = calloc(count, sizeof(*batches));
> +	igt_assert(batches);
> +	for (unsigned int i = 0; i < count; i++)
> +		batches[i].handle = batch_create(fd, &batch_size);
> +
> +	/* Flush all memory before we start the timer */
> +	single_offset_submit(fd, &execbuf, batches, count);
> +
> +	igt_fork(child, nengine) {
> +		execbuf.flags |= engines[child];
> +		igt_until_timeout(timeout)
> +			single_offset_submit(fd, &execbuf, batches, count);
> +	}
> +	igt_waitchildren();
> +
> +	for (unsigned int i = 0; i < count; i++)
> +		gem_close(fd, batches[i].handle);
> +	free(batches);
> +
> +	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
> +}
> +
>  static void make_batch(int i915, uint32_t handle, uint64_t size)
>  {
>  	uint32_t *bb = gem_mmap__device_coherent(i915, handle, 0, size, PROT_WRITE);
> @@ -1213,8 +1284,9 @@ igt_main
>  		test_each_engine("allocator-evict", fd, ctx, e)
>  			test_allocator_evict(fd, ctx, e->flags, 20);
>  
> -		igt_subtest("allocator-evict-all-engines")
> -			test_allocator_evict(fd, ctx, ALL_ENGINES, 20);
> +		igt_describe("Use same offset for all engines and for different handles");
> +		igt_subtest("evict-single-offset")
> +			evict_single_offset(fd, ctx, 20);

You are not using allocator here, so maybe move this down after
evict-hog sibtest ?

With that small changes you can add my r-b tag.

Regards,
Kamil
>  	}
>  
>  	igt_describe("Check start offset and alignment detection");
> -- 
> 2.32.0
> 

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [igt-dev] [PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines
@ 2022-04-27 18:42 Zbigniew Kempczyński
  2022-04-28 16:07 ` Kamil Konieczny
  0 siblings, 1 reply; 9+ messages in thread
From: Zbigniew Kempczyński @ 2022-04-27 18:42 UTC (permalink / raw)
  To: igt-dev; +Cc: Thomas Hellström

Verify that eviction works when all engines try to use same offset for
different handles. It replaces allocator-evict-all-engines test because
it is simpler.

v2: addressing review comments (Kamil)
v3: simplifying subtest (Chris)

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
 tests/i915/gem_softpin.c | 76 ++++++++++++++++++++++++++++++++++++++--
 1 file changed, 74 insertions(+), 2 deletions(-)

diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
index 448b4c4b9e..7dae2a6c44 100644
--- a/tests/i915/gem_softpin.c
+++ b/tests/i915/gem_softpin.c
@@ -1073,6 +1073,77 @@ static void test_allocator_evict(int fd, const intel_ctx_t *ctx,
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
+#define MINIMAL_OFFSET 0x200000
+static void single_offset_submit(int fd, struct drm_i915_gem_execbuffer2 *eb,
+				 struct batch *batches, unsigned int count)
+{
+	struct drm_i915_gem_exec_object2 obj = {
+		.offset = max_t(uint64_t, gem_detect_safe_start_offset(fd), MINIMAL_OFFSET),
+		.flags = EXEC_OBJECT_PINNED,
+	};
+
+	eb->buffers_ptr = to_user_pointer(&obj);
+
+	for (unsigned int i = 0; i < count; i++) {
+		obj.handle = batches[i].handle;
+		gem_execbuf(fd, eb);
+	}
+}
+
+static void evict_single_offset(int fd, const intel_ctx_t *ctx, int timeout)
+{
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct intel_execution_engine2 *e;
+	unsigned int engines[I915_EXEC_RING_MASK + 1];
+	struct batch *batches;
+	unsigned int nengine;
+	unsigned int count;
+	uint64_t size, batch_size = BATCH_SIZE;
+
+	nengine = 0;
+	for_each_ctx_engine(fd, ctx, e) {
+		engines[nengine++] = e->flags;
+	}
+	igt_require(nengine);
+
+	size = gem_aperture_size(fd);
+	if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
+		size = 1ull << 32;
+	igt_require(size < (1ull<<32) * BATCH_SIZE);
+
+	count = size / BATCH_SIZE + 1;
+	igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
+		  count, (long long)size, nengine);
+
+	intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
+	intel_detect_and_clear_missed_interrupts(fd);
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffer_count = 1;
+	execbuf.rsvd1 = ctx->id;
+
+	batches = calloc(count, sizeof(*batches));
+	igt_assert(batches);
+	for (unsigned int i = 0; i < count; i++)
+		batches[i].handle = batch_create(fd, &batch_size);
+
+	/* Flush all memory before we start the timer */
+	single_offset_submit(fd, &execbuf, batches, count);
+
+	igt_fork(child, nengine) {
+		execbuf.flags |= engines[child];
+		igt_until_timeout(timeout)
+			single_offset_submit(fd, &execbuf, batches, count);
+	}
+	igt_waitchildren();
+
+	for (unsigned int i = 0; i < count; i++)
+		gem_close(fd, batches[i].handle);
+	free(batches);
+
+	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+}
+
 static void make_batch(int i915, uint32_t handle, uint64_t size)
 {
 	uint32_t *bb = gem_mmap__device_coherent(i915, handle, 0, size, PROT_WRITE);
@@ -1213,8 +1284,9 @@ igt_main
 		test_each_engine("allocator-evict", fd, ctx, e)
 			test_allocator_evict(fd, ctx, e->flags, 20);
 
-		igt_subtest("allocator-evict-all-engines")
-			test_allocator_evict(fd, ctx, ALL_ENGINES, 20);
+		igt_describe("Use same offset for all engines and for different handles");
+		igt_subtest("evict-single-offset")
+			evict_single_offset(fd, ctx, 20);
 	}
 
 	igt_describe("Check start offset and alignment detection");
-- 
2.32.0

^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [igt-dev] [PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines
@ 2022-04-27  6:10 Zbigniew Kempczyński
  0 siblings, 0 replies; 9+ messages in thread
From: Zbigniew Kempczyński @ 2022-04-27  6:10 UTC (permalink / raw)
  To: igt-dev; +Cc: Thomas Hellström

Verify that eviction works when all engines try to use same offset for
different handles. It replaces allocator-evict-all-engines test because
it is simpler.

v2: addressing review comments (Kamil)

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Kamil Konieczny <kamil.konieczny@linux.intel.com>
Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
 tests/i915/gem_softpin.c | 88 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 86 insertions(+), 2 deletions(-)

diff --git a/tests/i915/gem_softpin.c b/tests/i915/gem_softpin.c
index 448b4c4b9e..84fed0720c 100644
--- a/tests/i915/gem_softpin.c
+++ b/tests/i915/gem_softpin.c
@@ -1073,6 +1073,89 @@ static void test_allocator_evict(int fd, const intel_ctx_t *ctx,
 	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
 }
 
+#define MINIMAL_OFFSET 0x200000
+static void single_offset_submit(int fd, struct drm_i915_gem_execbuffer2 *eb,
+				 struct batch *batches, unsigned int count)
+{
+	struct drm_i915_gem_exec_object2 obj;
+	uint64_t address = max_t(uint64_t, gem_detect_safe_start_offset(fd),
+				 MINIMAL_OFFSET);
+
+	memset(&obj, 0, sizeof(obj));
+	obj.flags = EXEC_OBJECT_PINNED;
+
+	for (unsigned int i = 0; i < count; i++) {
+		obj.handle = batches[i].handle;
+		obj.offset = address;
+		eb->buffers_ptr = to_user_pointer(&obj);
+		gem_execbuf(fd, eb);
+	}
+}
+
+static void evict_single_offset(int fd, const intel_ctx_t *ctx, int timeout)
+{
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct intel_execution_engine2 *e;
+	unsigned int engines[I915_EXEC_RING_MASK + 1];
+	struct batch *batches;
+	unsigned int nengine;
+	unsigned int count;
+	uint64_t size;
+
+	nengine = 0;
+	for_each_ctx_engine(fd, ctx, e) {
+		engines[nengine++] = e->flags;
+	}
+	igt_require(nengine);
+
+	size = gem_aperture_size(fd);
+	if (size > 1ull<<32) /* Limit to 4GiB as we do not use allow-48b */
+		size = 1ull << 32;
+	igt_require(size < (1ull<<32) * BATCH_SIZE);
+
+	count = size / BATCH_SIZE + 1;
+	igt_debug("Using %'d batches to fill %'llu aperture on %d engines\n",
+		  count, (long long)size, nengine);
+
+	intel_require_memory(count, BATCH_SIZE, CHECK_RAM);
+	intel_detect_and_clear_missed_interrupts(fd);
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffer_count = 1;
+	execbuf.rsvd1 = ctx->id;
+
+	batches = calloc(count, sizeof(*batches));
+	igt_assert(batches);
+	for (unsigned int i = 0; i < count; i++) {
+		uint32_t *p;
+
+		batches[i].handle = gem_create(fd, BATCH_SIZE);
+		batches[i].ptr =
+			gem_mmap__device_coherent(fd, batches[i].handle,
+						  0, BATCH_SIZE, PROT_WRITE);
+		p = batches[i].ptr + BATCH_SIZE - 8;
+		*p = MI_BATCH_BUFFER_END;
+	}
+
+	/* Flush all memory before we start the timer */
+	single_offset_submit(fd, &execbuf, batches, count);
+
+	igt_fork(child, nengine) {
+		execbuf.flags |= engines[child];
+		igt_until_timeout(timeout)
+			single_offset_submit(fd, &execbuf, batches, count);
+	}
+	igt_waitchildren();
+
+	for (unsigned int i = 0; i < count; i++) {
+		munmap(batches[i].ptr, BATCH_SIZE);
+		gem_close(fd, batches[i].handle);
+	}
+	free(batches);
+
+	igt_assert_eq(intel_detect_and_clear_missed_interrupts(fd), 0);
+}
+
 static void make_batch(int i915, uint32_t handle, uint64_t size)
 {
 	uint32_t *bb = gem_mmap__device_coherent(i915, handle, 0, size, PROT_WRITE);
@@ -1213,8 +1296,9 @@ igt_main
 		test_each_engine("allocator-evict", fd, ctx, e)
 			test_allocator_evict(fd, ctx, e->flags, 20);
 
-		igt_subtest("allocator-evict-all-engines")
-			test_allocator_evict(fd, ctx, ALL_ENGINES, 20);
+		igt_describe("Use same offset for all engines and for different handles");
+		igt_subtest("evict-single-offset")
+			evict_single_offset(fd, ctx, 20);
 	}
 
 	igt_describe("Check start offset and alignment detection");
-- 
2.32.0

^ permalink raw reply related	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2022-04-29  4:51 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-04 17:18 [igt-dev] [PATCH i-g-t] tests/i915/gem_softpin: Exercise single offset eviction on all engines Zbigniew Kempczyński
2022-04-04 18:12 ` [igt-dev] ✗ GitLab.Pipeline: warning for " Patchwork
2022-04-04 18:32 ` [igt-dev] ✗ Fi.CI.BAT: failure " Patchwork
2022-04-05 18:28 ` [igt-dev] [PATCH i-g-t] " Kamil Konieczny
2022-04-27  6:03   ` Zbigniew Kempczyński
2022-04-27  6:10 Zbigniew Kempczyński
2022-04-27 18:42 Zbigniew Kempczyński
2022-04-28 16:07 ` Kamil Konieczny
2022-04-29  4:51   ` Zbigniew Kempczyński

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