* [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map @ 2022-04-04 9:31 Mullati Siva 2022-04-04 9:31 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva ` (5 more replies) 0 siblings, 6 replies; 16+ messages in thread From: Mullati Siva @ 2022-04-04 9:31 UTC (permalink / raw) To: intel-gfx, siva.mullati; +Cc: lucas.demarchi From: Siva Mullati <siva.mullati@intel.com> ver2: remove newly added iosys map api from ver1 ver3: address review comments This is continuation to the below patch series to use iosys map APIs, to use CT commands and descriptors. https://patchwork.freedesktop.org/series/99711/ Siva Mullati (1): drm/i915/guc: Convert ct buffer to iosys_map drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- 2 files changed, 127 insertions(+), 82 deletions(-) -- 2.33.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-04-04 9:31 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva @ 2022-04-04 9:31 ` Mullati Siva 2022-04-14 12:11 ` Balasubramani Vivekanandan 2022-04-18 9:08 ` Balasubramani Vivekanandan 2022-04-04 10:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev3) Patchwork ` (4 subsequent siblings) 5 siblings, 2 replies; 16+ messages in thread From: Mullati Siva @ 2022-04-04 9:31 UTC (permalink / raw) To: intel-gfx, siva.mullati; +Cc: lucas.demarchi From: Siva Mullati <siva.mullati@intel.com> Convert CT commands and descriptors to use iosys_map rather than plain pointer and save it in the intel_guc_ct_buffer struct. This will help with ct_write and ct_read for cmd send and receive after the initialization by abstracting the IO vs system memory. Signed-off-by: Siva Mullati <siva.mullati@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- 2 files changed, 127 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index f01325cd1b62..64568dc90b05 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) #define CT_PROBE_ERROR(_ct, _fmt, ...) \ i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) +#define ct_desc_read(desc_map_, field_) \ + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) +#define ct_desc_write(desc_map_, field_, val_) \ + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) + /** * DOC: CTB Blob * @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) +#define CTB_SEND_DESC_OFFSET 0u +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) + struct ct_request { struct list_head link; u32 fence; @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) init_waitqueue_head(&ct->wq); } -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) +static void guc_ct_buffer_desc_init(struct iosys_map *desc) { - memset(desc, 0, sizeof(*desc)); + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); } static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; atomic_set(&ctb->space, space); - guc_ct_buffer_desc_init(ctb->desc); + guc_ct_buffer_desc_init(&ctb->desc_map); } static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, - struct guc_ct_buffer_desc *desc, - u32 *cmds, u32 size_in_bytes, u32 resv_space) + struct iosys_map *desc, + struct iosys_map *cmds, + u32 size_in_bytes, u32 resv_space) { GEM_BUG_ON(size_in_bytes % 4); - ctb->desc = desc; - ctb->cmds = cmds; + ctb->desc_map = *desc; + ctb->cmds_map = *cmds; ctb->size = size_in_bytes / 4; ctb->resv_space = resv_space / 4; @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, int intel_guc_ct_init(struct intel_guc_ct *ct) { struct intel_guc *guc = ct_to_guc(ct); - struct guc_ct_buffer_desc *desc; + struct iosys_map blob_map; + struct iosys_map desc_map; + struct iosys_map cmds_map; u32 blob_size; u32 cmds_size; u32 resv_space; void *blob; - u32 *cmds; int err; err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); - /* store pointers to desc and cmds for send ctb */ - desc = blob; - cmds = blob + 2 * CTB_DESC_SIZE; + if (i915_gem_object_is_lmem(ct->vma->obj)) + iosys_map_set_vaddr_iomem(&blob_map, + (void __iomem *)blob); + else + iosys_map_set_vaddr(&blob_map, blob); + + /* store sysmap to desc_map and cmds_map for send ctb */ + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); cmds_size = CTB_H2G_BUFFER_SIZE; resv_space = 0; - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, - resv_space); + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, + cmds_size, resv_space); - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); + guc_ct_buffer_init(&ct->ctbs.send, + &desc_map, &cmds_map, cmds_size, resv_space); - /* store pointers to desc and cmds for recv ctb */ - desc = blob + CTB_DESC_SIZE; - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; + /* store sysmap to desc_map and cmds_map for recv ctb */ + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); cmds_size = CTB_G2H_BUFFER_SIZE; resv_space = G2H_ROOM_BUFFER_SIZE; - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, - resv_space); + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, + cmds_size, resv_space); - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); + guc_ct_buffer_init(&ct->ctbs.recv, + &desc_map, &cmds_map, cmds_size, resv_space); return 0; } @@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) tasklet_kill(&ct->receive_tasklet); i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP); + iosys_map_clear(&ct->ctbs.send.desc_map); + iosys_map_clear(&ct->ctbs.send.cmds_map); + iosys_map_clear(&ct->ctbs.recv.desc_map); + iosys_map_clear(&ct->ctbs.recv.cmds_map); memset(ct, 0, sizeof(*ct)); } @@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) int intel_guc_ct_enable(struct intel_guc_ct *ct) { struct intel_guc *guc = ct_to_guc(ct); + struct iosys_map blob_map; u32 base, desc, cmds, size; - void *blob; int err; GEM_BUG_ON(ct->enabled); @@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); base = intel_guc_ggtt_offset(guc, ct->vma); + if (i915_gem_object_is_lmem(ct->vma->obj)) + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) + __px_vaddr(ct->vma->obj)); + else + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); + /* blob should start with send descriptor */ - blob = __px_vaddr(ct->vma->obj); - GEM_BUG_ON(blob != ct->ctbs.send.desc); + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); /* (re)initialize descriptors */ guc_ct_buffer_reset(&ct->ctbs.send); @@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) * Register both CT buffers starting with RECV buffer. * Descriptors are in first half of the blob. */ - desc = base + ptrdiff(ct->ctbs.recv.desc, blob); - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); + desc = base + CTB_RECV_DESC_OFFSET; + cmds = base + CTB_RECV_CMDS_OFFSET; size = ct->ctbs.recv.size * 4; err = ct_register_buffer(ct, false, desc, cmds, size); if (unlikely(err)) goto err_out; - desc = base + ptrdiff(ct->ctbs.send.desc, blob); - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); + desc = base + CTB_SEND_DESC_OFFSET; + cmds = base + CTB_SEND_CMDS_OFFSET; size = ct->ctbs.send.size * 4; err = ct_register_buffer(ct, true, desc, cmds, size); if (unlikely(err)) @@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct, u32 fence, u32 flags) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 tail = ctb->tail; u32 size = ctb->size; u32 header; u32 hxg; u32 type; - u32 *cmds = ctb->cmds; + u32 status = ct_desc_read(&ctb->desc_map, status); unsigned int i; - if (unlikely(desc->status)) + if (unlikely(status)) goto corrupted; GEM_BUG_ON(tail > size); #ifdef CONFIG_DRM_I915_DEBUG_GUC - if (unlikely(tail != READ_ONCE(desc->tail))) { + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { CT_ERROR(ct, "Tail was modified %u != %u\n", - desc->tail, tail); - desc->status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_read(&ctb->desc_map, tail), tail); + status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } - if (unlikely(READ_ONCE(desc->head) >= size)) { + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) { CT_ERROR(ct, "Invalid head offset %u >= %u)\n", - desc->head, size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_read(&ctb->desc_map, head), size); + status = ct_desc_read(&ctb->desc_map, status) | + GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } #endif @@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct, CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); - cmds[tail] = header; + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, header); tail = (tail + 1) % size; - cmds[tail] = hxg; + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, hxg); tail = (tail + 1) % size; for (i = 1; i < len; i++) { - cmds[tail] = action[i]; + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, action[i]); tail = (tail + 1) % size; } GEM_BUG_ON(tail > size); @@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct, atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); /* now update descriptor */ - WRITE_ONCE(desc->tail, tail); + ct_desc_write(&ctb->desc_map, tail, tail); return 0; corrupted: CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", - desc->head, desc->tail, desc->status); + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail), + ct_desc_read(&ctb->desc_map, status)); ctb->broken = true; return -EPIPE; } @@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; if (unlikely(ret)) { - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; - CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", ktime_ms_delta(ktime_get(), ct->stall_time), - send->status, recv->status); + ct_desc_read(&ct->ctbs.send.desc_map, status), + ct_desc_read(&ct->ctbs.recv.desc_map, status)); CT_ERROR(ct, "H2G Space: %u (Bytes)\n", atomic_read(&ct->ctbs.send.space) * 4); - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); + CT_ERROR(ct, "Head: %u (Dwords)\n", + ct_desc_read(&ct->ctbs.send.desc_map, head)); + CT_ERROR(ct, "Tail: %u (Dwords)\n", + ct_desc_read(&ct->ctbs.send.desc_map, tail)); CT_ERROR(ct, "G2H Space: %u (Bytes)\n", atomic_read(&ct->ctbs.recv.space) * 4); - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); + CT_ERROR(ct, "Head: %u\n (Dwords)", + ct_desc_read(&ct->ctbs.recv.desc_map, head)); + CT_ERROR(ct, "Tail: %u\n (Dwords)", + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); ct->ctbs.send.broken = true; } @@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 head; u32 space; + u32 status = ct_desc_read(&ctb->desc_map, status); if (atomic_read(&ctb->space) >= len_dw) return true; - head = READ_ONCE(desc->head); + head = ct_desc_read(&ctb->desc_map, head); if (unlikely(head > ctb->size)) { CT_ERROR(ct, "Invalid head offset %u >= %u)\n", head, ctb->size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); ctb->broken = true; return false; } @@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg) static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 head = ctb->head; - u32 tail = READ_ONCE(desc->tail); + u32 tail = ct_desc_read(&ctb->desc_map, tail); u32 size = ctb->size; - u32 *cmds = ctb->cmds; + u32 status = ct_desc_read(&ctb->desc_map, status); s32 available; unsigned int len; unsigned int i; @@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (unlikely(ctb->broken)) return -EPIPE; - if (unlikely(desc->status)) + if (unlikely(status)) goto corrupted; GEM_BUG_ON(head > size); #ifdef CONFIG_DRM_I915_DEBUG_GUC - if (unlikely(head != READ_ONCE(desc->head))) { + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) { CT_ERROR(ct, "Head was modified %u != %u\n", - desc->head, head); - desc->status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_read(&ctb->desc_map, head), head); + status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } #endif if (unlikely(tail >= size)) { CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", tail, size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + status = ct_desc_read(&ctb->desc_map, status) | + GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } @@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); GEM_BUG_ON(available < 0); - header = cmds[head]; + header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32); head = (head + 1) % size; /* message len with header */ @@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (unlikely(len > (u32)available)) { CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", 4, &header, + 4 * (head + available - 1 > size ? size - head : + available - 1), ((__px_vaddr(ct->vma->obj) + + CTB_RECV_CMDS_OFFSET) + (4 * head)), 4 * (head + available - 1 > size ? - size - head : available - 1), &cmds[head], - 4 * (head + available - 1 > size ? - available - 1 - size + head : 0), &cmds[0]); - desc->status |= GUC_CTB_STATUS_UNDERFLOW; + available - 1 - size + head : 0), + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); + status = ct_desc_read(&ctb->desc_map, status) | + GUC_CTB_STATUS_UNDERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } @@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (!*msg) { CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", 4, &header, + 4 * (head + available - 1 > size ? size - head : + available - 1), (ctb->cmds_map.vaddr + (4 * head)), 4 * (head + available - 1 > size ? - size - head : available - 1), &cmds[head], - 4 * (head + available - 1 > size ? - available - 1 - size + head : 0), &cmds[0]); + available - 1 - size + head : 0), ctb->cmds_map.vaddr); return available; } (*msg)->msg[0] = header; for (i = 1; i < len; i++) { - (*msg)->msg[i] = cmds[head]; + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, + (4 * head), u32); head = (head + 1) % size; } CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); @@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) ctb->head = head; /* now update descriptor */ - WRITE_ONCE(desc->head, head); + ct_desc_write(&ctb->desc_map, head, head); return available - len; corrupted: CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", - desc->head, desc->tail, desc->status); + ct_desc_read(&ctb->desc_map, head), + ct_desc_read(&ctb->desc_map, tail), + ct_desc_read(&ctb->desc_map, status)); ctb->broken = true; return -EPIPE; } @@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, drm_printf(p, "H2G Space: %u\n", atomic_read(&ct->ctbs.send.space) * 4); drm_printf(p, "Head: %u\n", - ct->ctbs.send.desc->head); + ct_desc_read(&ct->ctbs.send.desc_map, head)); drm_printf(p, "Tail: %u\n", - ct->ctbs.send.desc->tail); + ct_desc_read(&ct->ctbs.send.desc_map, tail)); drm_printf(p, "G2H Space: %u\n", atomic_read(&ct->ctbs.recv.space) * 4); drm_printf(p, "Head: %u\n", - ct->ctbs.recv.desc->head); + ct_desc_read(&ct->ctbs.recv.desc_map, head)); drm_printf(p, "Tail: %u\n", - ct->ctbs.recv.desc->tail); + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h index f709a19c7e21..867fe13fb47d 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h @@ -7,6 +7,7 @@ #define _INTEL_GUC_CT_H_ #include <linux/interrupt.h> +#include <linux/iosys-map.h> #include <linux/spinlock.h> #include <linux/workqueue.h> #include <linux/ktime.h> @@ -32,8 +33,8 @@ struct drm_printer; * holds the commands. * * @lock: protects access to the commands buffer and buffer descriptor - * @desc: pointer to the buffer descriptor - * @cmds: pointer to the commands buffer + * @desc: iosys map to the buffer descriptor + * @cmds: iosys map to the commands buffer * @size: size of the commands buffer in dwords * @resv_space: reserved space in buffer in dwords * @head: local shadow copy of head in dwords @@ -43,8 +44,8 @@ struct drm_printer; */ struct intel_guc_ct_buffer { spinlock_t lock; - struct guc_ct_buffer_desc *desc; - u32 *cmds; + struct iosys_map desc_map; + struct iosys_map cmds_map; u32 size; u32 resv_space; u32 tail; -- 2.33.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-04-04 9:31 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva @ 2022-04-14 12:11 ` Balasubramani Vivekanandan 2022-04-28 14:13 ` Siva Mullati 2022-04-18 9:08 ` Balasubramani Vivekanandan 1 sibling, 1 reply; 16+ messages in thread From: Balasubramani Vivekanandan @ 2022-04-14 12:11 UTC (permalink / raw) To: Mullati Siva, intel-gfx; +Cc: lucas.demarchi On 04.04.2022 15:01, Mullati Siva wrote: > From: Siva Mullati <siva.mullati@intel.com> > > Convert CT commands and descriptors to use iosys_map rather > than plain pointer and save it in the intel_guc_ct_buffer struct. > This will help with ct_write and ct_read for cmd send and receive > after the initialization by abstracting the IO vs system memory. > > Signed-off-by: Siva Mullati <siva.mullati@intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++--------- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- > 2 files changed, 127 insertions(+), 82 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > index f01325cd1b62..64568dc90b05 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > #define CT_PROBE_ERROR(_ct, _fmt, ...) \ > i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) > > +#define ct_desc_read(desc_map_, field_) \ > + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) > +#define ct_desc_write(desc_map_, field_, val_) \ > + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) > + Did you try to make the change Lucas mentioned in his comment on rev0, to pass `struct guc_ct_buffer_desc *` as first argument to the above macros? Was it not feasible? > /** > * DOC: CTB Blob > * > @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) > #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) > > +#define CTB_SEND_DESC_OFFSET 0u > +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) > +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) > +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) > + > struct ct_request { > struct list_head link; > u32 fence; > @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) > init_waitqueue_head(&ct->wq); > } > > -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) > +static void guc_ct_buffer_desc_init(struct iosys_map *desc) > { > - memset(desc, 0, sizeof(*desc)); > + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); > } > > static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) > @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) > space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; > atomic_set(&ctb->space, space); > > - guc_ct_buffer_desc_init(ctb->desc); > + guc_ct_buffer_desc_init(&ctb->desc_map); > } > > static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, > - struct guc_ct_buffer_desc *desc, > - u32 *cmds, u32 size_in_bytes, u32 resv_space) > + struct iosys_map *desc, > + struct iosys_map *cmds, > + u32 size_in_bytes, u32 resv_space) > { > GEM_BUG_ON(size_in_bytes % 4); > > - ctb->desc = desc; > - ctb->cmds = cmds; > + ctb->desc_map = *desc; > + ctb->cmds_map = *cmds; > ctb->size = size_in_bytes / 4; > ctb->resv_space = resv_space / 4; > > @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, > int intel_guc_ct_init(struct intel_guc_ct *ct) > { > struct intel_guc *guc = ct_to_guc(ct); > - struct guc_ct_buffer_desc *desc; > + struct iosys_map blob_map; > + struct iosys_map desc_map; > + struct iosys_map cmds_map; > u32 blob_size; > u32 cmds_size; > u32 resv_space; > void *blob; > - u32 *cmds; > int err; > > err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); > @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) > > CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); > > - /* store pointers to desc and cmds for send ctb */ > - desc = blob; > - cmds = blob + 2 * CTB_DESC_SIZE; > + if (i915_gem_object_is_lmem(ct->vma->obj)) > + iosys_map_set_vaddr_iomem(&blob_map, > + (void __iomem *)blob); > + else > + iosys_map_set_vaddr(&blob_map, blob); > + > + /* store sysmap to desc_map and cmds_map for send ctb */ > + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); > + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); > cmds_size = CTB_H2G_BUFFER_SIZE; > resv_space = 0; > - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", > - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, > - resv_space); > + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", > + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, > + cmds_size, resv_space); > > - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); > + guc_ct_buffer_init(&ct->ctbs.send, > + &desc_map, &cmds_map, cmds_size, resv_space); > > - /* store pointers to desc and cmds for recv ctb */ > - desc = blob + CTB_DESC_SIZE; > - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; > + /* store sysmap to desc_map and cmds_map for recv ctb */ > + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); > + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); > cmds_size = CTB_G2H_BUFFER_SIZE; > resv_space = G2H_ROOM_BUFFER_SIZE; > - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", > - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, > - resv_space); > + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", > + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, > + cmds_size, resv_space); > > - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); > + guc_ct_buffer_init(&ct->ctbs.recv, > + &desc_map, &cmds_map, cmds_size, resv_space); > > return 0; > } > @@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) > > tasklet_kill(&ct->receive_tasklet); > i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP); > + iosys_map_clear(&ct->ctbs.send.desc_map); > + iosys_map_clear(&ct->ctbs.send.cmds_map); > + iosys_map_clear(&ct->ctbs.recv.desc_map); > + iosys_map_clear(&ct->ctbs.recv.cmds_map); I think there is no need of clearing the iosys_map when were are zeroing the complete structure area below. > memset(ct, 0, sizeof(*ct)); > } > > @@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) > int intel_guc_ct_enable(struct intel_guc_ct *ct) > { > struct intel_guc *guc = ct_to_guc(ct); > + struct iosys_map blob_map; > u32 base, desc, cmds, size; > - void *blob; > int err; > > GEM_BUG_ON(ct->enabled); > @@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); > base = intel_guc_ggtt_offset(guc, ct->vma); > > + if (i915_gem_object_is_lmem(ct->vma->obj)) > + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) > + __px_vaddr(ct->vma->obj)); > + else > + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); > + > /* blob should start with send descriptor */ > - blob = __px_vaddr(ct->vma->obj); > - GEM_BUG_ON(blob != ct->ctbs.send.desc); > + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); > > /* (re)initialize descriptors */ > guc_ct_buffer_reset(&ct->ctbs.send); > @@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > * Register both CT buffers starting with RECV buffer. > * Descriptors are in first half of the blob. > */ > - desc = base + ptrdiff(ct->ctbs.recv.desc, blob); > - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); > + desc = base + CTB_RECV_DESC_OFFSET; > + cmds = base + CTB_RECV_CMDS_OFFSET; > size = ct->ctbs.recv.size * 4; > err = ct_register_buffer(ct, false, desc, cmds, size); > if (unlikely(err)) > goto err_out; > > - desc = base + ptrdiff(ct->ctbs.send.desc, blob); > - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); > + desc = base + CTB_SEND_DESC_OFFSET; > + cmds = base + CTB_SEND_CMDS_OFFSET; > size = ct->ctbs.send.size * 4; > err = ct_register_buffer(ct, true, desc, cmds, size); > if (unlikely(err)) > @@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct, > u32 fence, u32 flags) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; > - struct guc_ct_buffer_desc *desc = ctb->desc; > u32 tail = ctb->tail; > u32 size = ctb->size; > u32 header; > u32 hxg; > u32 type; > - u32 *cmds = ctb->cmds; > + u32 status = ct_desc_read(&ctb->desc_map, status); > unsigned int i; > > - if (unlikely(desc->status)) > + if (unlikely(status)) > goto corrupted; > > GEM_BUG_ON(tail > size); > > #ifdef CONFIG_DRM_I915_DEBUG_GUC > - if (unlikely(tail != READ_ONCE(desc->tail))) { > + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { > CT_ERROR(ct, "Tail was modified %u != %u\n", > - desc->tail, tail); > - desc->status |= GUC_CTB_STATUS_MISMATCH; > + ct_desc_read(&ctb->desc_map, tail), tail); > + status |= GUC_CTB_STATUS_MISMATCH; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > - if (unlikely(READ_ONCE(desc->head) >= size)) { > + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) { > CT_ERROR(ct, "Invalid head offset %u >= %u)\n", > - desc->head, size); > - desc->status |= GUC_CTB_STATUS_OVERFLOW; > + ct_desc_read(&ctb->desc_map, head), size); Can we avoid reading the head from ctb->desc_map twice? Since each iosys_map read translates to memcpy, it is better to avoid repeating if we can cache from the earlier read. > + status = ct_desc_read(&ctb->desc_map, status) | > + GUC_CTB_STATUS_OVERFLOW; Same here, can we avoid reading status since we already have it read. We can do the same like how it is done for the GUC_CTB_STATUS_MISMATCH case. > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > #endif > @@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct, > CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", > tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); > > - cmds[tail] = header; > + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, header); I prefer not to use the MAGIC number. My suggestion is to use sizeof(tail) since we need the offset in bytes. > tail = (tail + 1) % size; > > - cmds[tail] = hxg; > + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, hxg); MAGIC number again. There are numerous places in the patch, where numbers are used. I prefer to remove it. > tail = (tail + 1) % size; > > for (i = 1; i < len; i++) { > - cmds[tail] = action[i]; > + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, action[i]); > tail = (tail + 1) % size; > } > GEM_BUG_ON(tail > size); > @@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct, > atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); > > /* now update descriptor */ > - WRITE_ONCE(desc->tail, tail); > + ct_desc_write(&ctb->desc_map, tail, tail); > > return 0; > > corrupted: > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", > - desc->head, desc->tail, desc->status); > + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail), > + ct_desc_read(&ctb->desc_map, status)); > ctb->broken = true; > return -EPIPE; > } > @@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) > bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; > > if (unlikely(ret)) { > - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; > - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; > - > CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", > ktime_ms_delta(ktime_get(), ct->stall_time), > - send->status, recv->status); > + ct_desc_read(&ct->ctbs.send.desc_map, status), > + ct_desc_read(&ct->ctbs.recv.desc_map, status)); > CT_ERROR(ct, "H2G Space: %u (Bytes)\n", > atomic_read(&ct->ctbs.send.space) * 4); > - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); > - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); > + CT_ERROR(ct, "Head: %u (Dwords)\n", > + ct_desc_read(&ct->ctbs.send.desc_map, head)); > + CT_ERROR(ct, "Tail: %u (Dwords)\n", > + ct_desc_read(&ct->ctbs.send.desc_map, tail)); > CT_ERROR(ct, "G2H Space: %u (Bytes)\n", > atomic_read(&ct->ctbs.recv.space) * 4); > - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); > - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); > + CT_ERROR(ct, "Head: %u\n (Dwords)", > + ct_desc_read(&ct->ctbs.recv.desc_map, head)); > + CT_ERROR(ct, "Tail: %u\n (Dwords)", > + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > > ct->ctbs.send.broken = true; > } > @@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) > static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; > - struct guc_ct_buffer_desc *desc = ctb->desc; > u32 head; > u32 space; > + u32 status = ct_desc_read(&ctb->desc_map, status); > > if (atomic_read(&ctb->space) >= len_dw) > return true; > > - head = READ_ONCE(desc->head); > + head = ct_desc_read(&ctb->desc_map, head); > if (unlikely(head > ctb->size)) { > CT_ERROR(ct, "Invalid head offset %u >= %u)\n", > head, ctb->size); > - desc->status |= GUC_CTB_STATUS_OVERFLOW; > + status |= GUC_CTB_STATUS_OVERFLOW; > + ct_desc_write(&ctb->desc_map, status, status); > ctb->broken = true; > return false; > } > @@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg) > static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; > - struct guc_ct_buffer_desc *desc = ctb->desc; > u32 head = ctb->head; > - u32 tail = READ_ONCE(desc->tail); > + u32 tail = ct_desc_read(&ctb->desc_map, tail); > u32 size = ctb->size; > - u32 *cmds = ctb->cmds; > + u32 status = ct_desc_read(&ctb->desc_map, status); > s32 available; > unsigned int len; > unsigned int i; > @@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (unlikely(ctb->broken)) > return -EPIPE; > > - if (unlikely(desc->status)) > + if (unlikely(status)) > goto corrupted; > > GEM_BUG_ON(head > size); > > #ifdef CONFIG_DRM_I915_DEBUG_GUC > - if (unlikely(head != READ_ONCE(desc->head))) { > + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) { > CT_ERROR(ct, "Head was modified %u != %u\n", > - desc->head, head); > - desc->status |= GUC_CTB_STATUS_MISMATCH; > + ct_desc_read(&ctb->desc_map, head), head); head read twice here as well. > + status |= GUC_CTB_STATUS_MISMATCH; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > #endif > if (unlikely(tail >= size)) { > CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", > tail, size); > - desc->status |= GUC_CTB_STATUS_OVERFLOW; > + status = ct_desc_read(&ctb->desc_map, status) | > + GUC_CTB_STATUS_OVERFLOW; No need to read the status again as we already have it cached. > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > > @@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); > GEM_BUG_ON(available < 0); > > - header = cmds[head]; > + header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32); MAGIC numbers > head = (head + 1) % size; > > /* message len with header */ > @@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (unlikely(len > (u32)available)) { > CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", > 4, &header, > + 4 * (head + available - 1 > size ? size - head : > + available - 1), ((__px_vaddr(ct->vma->obj) + > + CTB_RECV_CMDS_OFFSET) + (4 * head)), > 4 * (head + available - 1 > size ? > - size - head : available - 1), &cmds[head], > - 4 * (head + available - 1 > size ? > - available - 1 - size + head : 0), &cmds[0]); > - desc->status |= GUC_CTB_STATUS_UNDERFLOW; > + available - 1 - size + head : 0), > + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); > + status = ct_desc_read(&ctb->desc_map, status) | > + GUC_CTB_STATUS_UNDERFLOW; No need to read status again Regards, Bala > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > > @@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (!*msg) { > CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", > 4, &header, > + 4 * (head + available - 1 > size ? size - head : > + available - 1), (ctb->cmds_map.vaddr + (4 * head)), > 4 * (head + available - 1 > size ? > - size - head : available - 1), &cmds[head], > - 4 * (head + available - 1 > size ? > - available - 1 - size + head : 0), &cmds[0]); > + available - 1 - size + head : 0), ctb->cmds_map.vaddr); > return available; > } > > (*msg)->msg[0] = header; > > for (i = 1; i < len; i++) { > - (*msg)->msg[i] = cmds[head]; > + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, > + (4 * head), u32); > head = (head + 1) % size; > } > CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); > @@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > ctb->head = head; > > /* now update descriptor */ > - WRITE_ONCE(desc->head, head); > + ct_desc_write(&ctb->desc_map, head, head); > > return available - len; > > corrupted: > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", > - desc->head, desc->tail, desc->status); > + ct_desc_read(&ctb->desc_map, head), > + ct_desc_read(&ctb->desc_map, tail), > + ct_desc_read(&ctb->desc_map, status)); > ctb->broken = true; > return -EPIPE; > } > @@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, > drm_printf(p, "H2G Space: %u\n", > atomic_read(&ct->ctbs.send.space) * 4); > drm_printf(p, "Head: %u\n", > - ct->ctbs.send.desc->head); > + ct_desc_read(&ct->ctbs.send.desc_map, head)); > drm_printf(p, "Tail: %u\n", > - ct->ctbs.send.desc->tail); > + ct_desc_read(&ct->ctbs.send.desc_map, tail)); > drm_printf(p, "G2H Space: %u\n", > atomic_read(&ct->ctbs.recv.space) * 4); > drm_printf(p, "Head: %u\n", > - ct->ctbs.recv.desc->head); > + ct_desc_read(&ct->ctbs.recv.desc_map, head)); > drm_printf(p, "Tail: %u\n", > - ct->ctbs.recv.desc->tail); > + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > } > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > index f709a19c7e21..867fe13fb47d 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > @@ -7,6 +7,7 @@ > #define _INTEL_GUC_CT_H_ > > #include <linux/interrupt.h> > +#include <linux/iosys-map.h> > #include <linux/spinlock.h> > #include <linux/workqueue.h> > #include <linux/ktime.h> > @@ -32,8 +33,8 @@ struct drm_printer; > * holds the commands. > * > * @lock: protects access to the commands buffer and buffer descriptor > - * @desc: pointer to the buffer descriptor > - * @cmds: pointer to the commands buffer > + * @desc: iosys map to the buffer descriptor > + * @cmds: iosys map to the commands buffer > * @size: size of the commands buffer in dwords > * @resv_space: reserved space in buffer in dwords > * @head: local shadow copy of head in dwords > @@ -43,8 +44,8 @@ struct drm_printer; > */ > struct intel_guc_ct_buffer { > spinlock_t lock; > - struct guc_ct_buffer_desc *desc; > - u32 *cmds; > + struct iosys_map desc_map; > + struct iosys_map cmds_map; > u32 size; > u32 resv_space; > u32 tail; > -- > 2.33.0 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-04-14 12:11 ` Balasubramani Vivekanandan @ 2022-04-28 14:13 ` Siva Mullati 2022-04-29 9:07 ` Balasubramani Vivekanandan 0 siblings, 1 reply; 16+ messages in thread From: Siva Mullati @ 2022-04-28 14:13 UTC (permalink / raw) To: Balasubramani Vivekanandan, intel-gfx; +Cc: lucas.demarchi On 14/04/22 17:41, Balasubramani Vivekanandan wrote: > On 04.04.2022 15:01, Mullati Siva wrote: >> From: Siva Mullati <siva.mullati@intel.com> >> >> Convert CT commands and descriptors to use iosys_map rather >> than plain pointer and save it in the intel_guc_ct_buffer struct. >> This will help with ct_write and ct_read for cmd send and receive >> after the initialization by abstracting the IO vs system memory. >> >> Signed-off-by: Siva Mullati <siva.mullati@intel.com> >> --- >> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++--------- >> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- >> 2 files changed, 127 insertions(+), 82 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >> index f01325cd1b62..64568dc90b05 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >> @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) >> #define CT_PROBE_ERROR(_ct, _fmt, ...) \ >> i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) >> >> +#define ct_desc_read(desc_map_, field_) \ >> + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) >> +#define ct_desc_write(desc_map_, field_, val_) \ >> + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) >> + > Did you try to make the change Lucas mentioned in his comment on rev0, > to pass `struct guc_ct_buffer_desc *` as first argument to the above > macros? Was it not feasible? It is not feasible. >> /** >> * DOC: CTB Blob >> * >> @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) >> #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) >> #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) >> >> +#define CTB_SEND_DESC_OFFSET 0u >> +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) >> +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) >> +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) >> + >> struct ct_request { >> struct list_head link; >> u32 fence; >> @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) >> init_waitqueue_head(&ct->wq); >> } >> >> -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) >> +static void guc_ct_buffer_desc_init(struct iosys_map *desc) >> { >> - memset(desc, 0, sizeof(*desc)); >> + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); >> } >> >> static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) >> @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) >> space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; >> atomic_set(&ctb->space, space); >> >> - guc_ct_buffer_desc_init(ctb->desc); >> + guc_ct_buffer_desc_init(&ctb->desc_map); >> } >> >> static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, >> - struct guc_ct_buffer_desc *desc, >> - u32 *cmds, u32 size_in_bytes, u32 resv_space) >> + struct iosys_map *desc, >> + struct iosys_map *cmds, >> + u32 size_in_bytes, u32 resv_space) >> { >> GEM_BUG_ON(size_in_bytes % 4); >> >> - ctb->desc = desc; >> - ctb->cmds = cmds; >> + ctb->desc_map = *desc; >> + ctb->cmds_map = *cmds; >> ctb->size = size_in_bytes / 4; >> ctb->resv_space = resv_space / 4; >> >> @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, >> int intel_guc_ct_init(struct intel_guc_ct *ct) >> { >> struct intel_guc *guc = ct_to_guc(ct); >> - struct guc_ct_buffer_desc *desc; >> + struct iosys_map blob_map; >> + struct iosys_map desc_map; >> + struct iosys_map cmds_map; >> u32 blob_size; >> u32 cmds_size; >> u32 resv_space; >> void *blob; >> - u32 *cmds; >> int err; >> >> err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); >> @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) >> >> CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); >> >> - /* store pointers to desc and cmds for send ctb */ >> - desc = blob; >> - cmds = blob + 2 * CTB_DESC_SIZE; >> + if (i915_gem_object_is_lmem(ct->vma->obj)) >> + iosys_map_set_vaddr_iomem(&blob_map, >> + (void __iomem *)blob); >> + else >> + iosys_map_set_vaddr(&blob_map, blob); >> + >> + /* store sysmap to desc_map and cmds_map for send ctb */ >> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); >> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); >> cmds_size = CTB_H2G_BUFFER_SIZE; >> resv_space = 0; >> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", >> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, >> - resv_space); >> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", >> + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, >> + cmds_size, resv_space); >> >> - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); >> + guc_ct_buffer_init(&ct->ctbs.send, >> + &desc_map, &cmds_map, cmds_size, resv_space); >> >> - /* store pointers to desc and cmds for recv ctb */ >> - desc = blob + CTB_DESC_SIZE; >> - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; >> + /* store sysmap to desc_map and cmds_map for recv ctb */ >> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); >> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); >> cmds_size = CTB_G2H_BUFFER_SIZE; >> resv_space = G2H_ROOM_BUFFER_SIZE; >> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", >> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, >> - resv_space); >> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", >> + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, >> + cmds_size, resv_space); >> >> - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); >> + guc_ct_buffer_init(&ct->ctbs.recv, >> + &desc_map, &cmds_map, cmds_size, resv_space); >> >> return 0; >> } >> @@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) >> >> tasklet_kill(&ct->receive_tasklet); >> i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP); >> + iosys_map_clear(&ct->ctbs.send.desc_map); >> + iosys_map_clear(&ct->ctbs.send.cmds_map); >> + iosys_map_clear(&ct->ctbs.recv.desc_map); >> + iosys_map_clear(&ct->ctbs.recv.cmds_map); > I think there is no need of clearing the iosys_map when were are zeroing > the complete structure area below. Yes, I have updated this in latest revision. >> memset(ct, 0, sizeof(*ct)); >> } >> >> @@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) >> int intel_guc_ct_enable(struct intel_guc_ct *ct) >> { >> struct intel_guc *guc = ct_to_guc(ct); >> + struct iosys_map blob_map; >> u32 base, desc, cmds, size; >> - void *blob; >> int err; >> >> GEM_BUG_ON(ct->enabled); >> @@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) >> GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); >> base = intel_guc_ggtt_offset(guc, ct->vma); >> >> + if (i915_gem_object_is_lmem(ct->vma->obj)) >> + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) >> + __px_vaddr(ct->vma->obj)); >> + else >> + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); >> + >> /* blob should start with send descriptor */ >> - blob = __px_vaddr(ct->vma->obj); >> - GEM_BUG_ON(blob != ct->ctbs.send.desc); >> + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); >> >> /* (re)initialize descriptors */ >> guc_ct_buffer_reset(&ct->ctbs.send); >> @@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) >> * Register both CT buffers starting with RECV buffer. >> * Descriptors are in first half of the blob. >> */ >> - desc = base + ptrdiff(ct->ctbs.recv.desc, blob); >> - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); >> + desc = base + CTB_RECV_DESC_OFFSET; >> + cmds = base + CTB_RECV_CMDS_OFFSET; >> size = ct->ctbs.recv.size * 4; >> err = ct_register_buffer(ct, false, desc, cmds, size); >> if (unlikely(err)) >> goto err_out; >> >> - desc = base + ptrdiff(ct->ctbs.send.desc, blob); >> - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); >> + desc = base + CTB_SEND_DESC_OFFSET; >> + cmds = base + CTB_SEND_CMDS_OFFSET; >> size = ct->ctbs.send.size * 4; >> err = ct_register_buffer(ct, true, desc, cmds, size); >> if (unlikely(err)) >> @@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct, >> u32 fence, u32 flags) >> { >> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; >> - struct guc_ct_buffer_desc *desc = ctb->desc; >> u32 tail = ctb->tail; >> u32 size = ctb->size; >> u32 header; >> u32 hxg; >> u32 type; >> - u32 *cmds = ctb->cmds; >> + u32 status = ct_desc_read(&ctb->desc_map, status); >> unsigned int i; >> >> - if (unlikely(desc->status)) >> + if (unlikely(status)) >> goto corrupted; >> >> GEM_BUG_ON(tail > size); >> >> #ifdef CONFIG_DRM_I915_DEBUG_GUC >> - if (unlikely(tail != READ_ONCE(desc->tail))) { >> + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { >> CT_ERROR(ct, "Tail was modified %u != %u\n", >> - desc->tail, tail); >> - desc->status |= GUC_CTB_STATUS_MISMATCH; >> + ct_desc_read(&ctb->desc_map, tail), tail); >> + status |= GUC_CTB_STATUS_MISMATCH; >> + ct_desc_write(&ctb->desc_map, status, status); >> goto corrupted; >> } >> - if (unlikely(READ_ONCE(desc->head) >= size)) { >> + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) { >> CT_ERROR(ct, "Invalid head offset %u >= %u)\n", >> - desc->head, size); >> - desc->status |= GUC_CTB_STATUS_OVERFLOW; >> + ct_desc_read(&ctb->desc_map, head), size); > Can we avoid reading the head from ctb->desc_map twice? Since each > iosys_map read translates to memcpy, it is better to avoid repeating if > we can cache from the earlier read. Do you see real need of having a variable to cache value locally, considering the path is very unlikely to hit. >> + status = ct_desc_read(&ctb->desc_map, status) | >> + GUC_CTB_STATUS_OVERFLOW; > Same here, can we avoid reading status since we already have it read. We > can do the same like how it is done for the GUC_CTB_STATUS_MISMATCH case. Addressed in latest patch >> + ct_desc_write(&ctb->desc_map, status, status); >> goto corrupted; >> } >> #endif >> @@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct, >> CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", >> tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); >> >> - cmds[tail] = header; >> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, header); > I prefer not to use the MAGIC number. My suggestion is to use > sizeof(tail) since we need the offset in bytes. I tried avoiding it, can't use sizeof(tail). Here tail is just an index which might be a misleading if we use it in this case, cmds would have been the right one but this has been changed to iosys map. Currently updated with sizeof(u32). >> tail = (tail + 1) % size; >> >> - cmds[tail] = hxg; >> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, hxg); > MAGIC number again. There are numerous places in the patch, where > numbers are used. I prefer to remove it. >> tail = (tail + 1) % size; >> >> for (i = 1; i < len; i++) { >> - cmds[tail] = action[i]; >> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, action[i]); >> tail = (tail + 1) % size; >> } >> GEM_BUG_ON(tail > size); >> @@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct, >> atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); >> >> /* now update descriptor */ >> - WRITE_ONCE(desc->tail, tail); >> + ct_desc_write(&ctb->desc_map, tail, tail); >> >> return 0; >> >> corrupted: >> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", >> - desc->head, desc->tail, desc->status); >> + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail), >> + ct_desc_read(&ctb->desc_map, status)); >> ctb->broken = true; >> return -EPIPE; >> } >> @@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) >> bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; >> >> if (unlikely(ret)) { >> - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; >> - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; >> - >> CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", >> ktime_ms_delta(ktime_get(), ct->stall_time), >> - send->status, recv->status); >> + ct_desc_read(&ct->ctbs.send.desc_map, status), >> + ct_desc_read(&ct->ctbs.recv.desc_map, status)); >> CT_ERROR(ct, "H2G Space: %u (Bytes)\n", >> atomic_read(&ct->ctbs.send.space) * 4); >> - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); >> - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); >> + CT_ERROR(ct, "Head: %u (Dwords)\n", >> + ct_desc_read(&ct->ctbs.send.desc_map, head)); >> + CT_ERROR(ct, "Tail: %u (Dwords)\n", >> + ct_desc_read(&ct->ctbs.send.desc_map, tail)); >> CT_ERROR(ct, "G2H Space: %u (Bytes)\n", >> atomic_read(&ct->ctbs.recv.space) * 4); >> - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); >> - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); >> + CT_ERROR(ct, "Head: %u\n (Dwords)", >> + ct_desc_read(&ct->ctbs.recv.desc_map, head)); >> + CT_ERROR(ct, "Tail: %u\n (Dwords)", >> + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); >> >> ct->ctbs.send.broken = true; >> } >> @@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) >> static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) >> { >> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; >> - struct guc_ct_buffer_desc *desc = ctb->desc; >> u32 head; >> u32 space; >> + u32 status = ct_desc_read(&ctb->desc_map, status); >> >> if (atomic_read(&ctb->space) >= len_dw) >> return true; >> >> - head = READ_ONCE(desc->head); >> + head = ct_desc_read(&ctb->desc_map, head); >> if (unlikely(head > ctb->size)) { >> CT_ERROR(ct, "Invalid head offset %u >= %u)\n", >> head, ctb->size); >> - desc->status |= GUC_CTB_STATUS_OVERFLOW; >> + status |= GUC_CTB_STATUS_OVERFLOW; >> + ct_desc_write(&ctb->desc_map, status, status); >> ctb->broken = true; >> return false; >> } >> @@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg) >> static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) >> { >> struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; >> - struct guc_ct_buffer_desc *desc = ctb->desc; >> u32 head = ctb->head; >> - u32 tail = READ_ONCE(desc->tail); >> + u32 tail = ct_desc_read(&ctb->desc_map, tail); >> u32 size = ctb->size; >> - u32 *cmds = ctb->cmds; >> + u32 status = ct_desc_read(&ctb->desc_map, status); >> s32 available; >> unsigned int len; >> unsigned int i; >> @@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) >> if (unlikely(ctb->broken)) >> return -EPIPE; >> >> - if (unlikely(desc->status)) >> + if (unlikely(status)) >> goto corrupted; >> >> GEM_BUG_ON(head > size); >> >> #ifdef CONFIG_DRM_I915_DEBUG_GUC >> - if (unlikely(head != READ_ONCE(desc->head))) { >> + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) { >> CT_ERROR(ct, "Head was modified %u != %u\n", >> - desc->head, head); >> - desc->status |= GUC_CTB_STATUS_MISMATCH; >> + ct_desc_read(&ctb->desc_map, head), head); > head read twice here as well. Same answer. >> + status |= GUC_CTB_STATUS_MISMATCH; >> + ct_desc_write(&ctb->desc_map, status, status); >> goto corrupted; >> } >> #endif >> if (unlikely(tail >= size)) { >> CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", >> tail, size); >> - desc->status |= GUC_CTB_STATUS_OVERFLOW; >> + status = ct_desc_read(&ctb->desc_map, status) | >> + GUC_CTB_STATUS_OVERFLOW; > No need to read the status again as we already have it cached. addressed. >> + ct_desc_write(&ctb->desc_map, status, status); >> goto corrupted; >> } >> >> @@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) >> CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); >> GEM_BUG_ON(available < 0); >> >> - header = cmds[head]; >> + header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32); > MAGIC numbers >> head = (head + 1) % size; >> >> /* message len with header */ >> @@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) >> if (unlikely(len > (u32)available)) { >> CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", >> 4, &header, >> + 4 * (head + available - 1 > size ? size - head : >> + available - 1), ((__px_vaddr(ct->vma->obj) + >> + CTB_RECV_CMDS_OFFSET) + (4 * head)), >> 4 * (head + available - 1 > size ? >> - size - head : available - 1), &cmds[head], >> - 4 * (head + available - 1 > size ? >> - available - 1 - size + head : 0), &cmds[0]); >> - desc->status |= GUC_CTB_STATUS_UNDERFLOW; >> + available - 1 - size + head : 0), >> + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); >> + status = ct_desc_read(&ctb->desc_map, status) | >> + GUC_CTB_STATUS_UNDERFLOW; > No need to read status again > > Regards, > Bala >> + ct_desc_write(&ctb->desc_map, status, status); >> goto corrupted; >> } >> >> @@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) >> if (!*msg) { >> CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", >> 4, &header, >> + 4 * (head + available - 1 > size ? size - head : >> + available - 1), (ctb->cmds_map.vaddr + (4 * head)), >> 4 * (head + available - 1 > size ? >> - size - head : available - 1), &cmds[head], >> - 4 * (head + available - 1 > size ? >> - available - 1 - size + head : 0), &cmds[0]); >> + available - 1 - size + head : 0), ctb->cmds_map.vaddr); >> return available; >> } >> >> (*msg)->msg[0] = header; >> >> for (i = 1; i < len; i++) { >> - (*msg)->msg[i] = cmds[head]; >> + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, >> + (4 * head), u32); >> head = (head + 1) % size; >> } >> CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); >> @@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) >> ctb->head = head; >> >> /* now update descriptor */ >> - WRITE_ONCE(desc->head, head); >> + ct_desc_write(&ctb->desc_map, head, head); >> >> return available - len; >> >> corrupted: >> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", >> - desc->head, desc->tail, desc->status); >> + ct_desc_read(&ctb->desc_map, head), >> + ct_desc_read(&ctb->desc_map, tail), >> + ct_desc_read(&ctb->desc_map, status)); >> ctb->broken = true; >> return -EPIPE; >> } >> @@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, >> drm_printf(p, "H2G Space: %u\n", >> atomic_read(&ct->ctbs.send.space) * 4); >> drm_printf(p, "Head: %u\n", >> - ct->ctbs.send.desc->head); >> + ct_desc_read(&ct->ctbs.send.desc_map, head)); >> drm_printf(p, "Tail: %u\n", >> - ct->ctbs.send.desc->tail); >> + ct_desc_read(&ct->ctbs.send.desc_map, tail)); >> drm_printf(p, "G2H Space: %u\n", >> atomic_read(&ct->ctbs.recv.space) * 4); >> drm_printf(p, "Head: %u\n", >> - ct->ctbs.recv.desc->head); >> + ct_desc_read(&ct->ctbs.recv.desc_map, head)); >> drm_printf(p, "Tail: %u\n", >> - ct->ctbs.recv.desc->tail); >> + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); >> } >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h >> index f709a19c7e21..867fe13fb47d 100644 >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h >> @@ -7,6 +7,7 @@ >> #define _INTEL_GUC_CT_H_ >> >> #include <linux/interrupt.h> >> +#include <linux/iosys-map.h> >> #include <linux/spinlock.h> >> #include <linux/workqueue.h> >> #include <linux/ktime.h> >> @@ -32,8 +33,8 @@ struct drm_printer; >> * holds the commands. >> * >> * @lock: protects access to the commands buffer and buffer descriptor >> - * @desc: pointer to the buffer descriptor >> - * @cmds: pointer to the commands buffer >> + * @desc: iosys map to the buffer descriptor >> + * @cmds: iosys map to the commands buffer >> * @size: size of the commands buffer in dwords >> * @resv_space: reserved space in buffer in dwords >> * @head: local shadow copy of head in dwords >> @@ -43,8 +44,8 @@ struct drm_printer; >> */ >> struct intel_guc_ct_buffer { >> spinlock_t lock; >> - struct guc_ct_buffer_desc *desc; >> - u32 *cmds; >> + struct iosys_map desc_map; >> + struct iosys_map cmds_map; >> u32 size; >> u32 resv_space; >> u32 tail; >> -- >> 2.33.0 >> ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-04-28 14:13 ` Siva Mullati @ 2022-04-29 9:07 ` Balasubramani Vivekanandan 0 siblings, 0 replies; 16+ messages in thread From: Balasubramani Vivekanandan @ 2022-04-29 9:07 UTC (permalink / raw) To: Siva Mullati, intel-gfx; +Cc: lucas.demarchi On 28.04.2022 19:43, Siva Mullati wrote: > > On 14/04/22 17:41, Balasubramani Vivekanandan wrote: > > On 04.04.2022 15:01, Mullati Siva wrote: > >> From: Siva Mullati <siva.mullati@intel.com> > >> > >> Convert CT commands and descriptors to use iosys_map rather > >> than plain pointer and save it in the intel_guc_ct_buffer struct. > >> This will help with ct_write and ct_read for cmd send and receive > >> after the initialization by abstracting the IO vs system memory. > >> > >> Signed-off-by: Siva Mullati <siva.mullati@intel.com> > >> --- > >> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++--------- > >> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- > >> 2 files changed, 127 insertions(+), 82 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > >> index f01325cd1b62..64568dc90b05 100644 > >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > >> @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > >> #define CT_PROBE_ERROR(_ct, _fmt, ...) \ > >> i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) > >> > >> +#define ct_desc_read(desc_map_, field_) \ > >> + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) > >> +#define ct_desc_write(desc_map_, field_, val_) \ > >> + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) > >> + > > Did you try to make the change Lucas mentioned in his comment on rev0, > > to pass `struct guc_ct_buffer_desc *` as first argument to the above > > macros? Was it not feasible? > It is not feasible. > >> /** > >> * DOC: CTB Blob > >> * > >> @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > >> #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) > >> #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) > >> > >> +#define CTB_SEND_DESC_OFFSET 0u > >> +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) > >> +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) > >> +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) > >> + > >> struct ct_request { > >> struct list_head link; > >> u32 fence; > >> @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) > >> init_waitqueue_head(&ct->wq); > >> } > >> > >> -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) > >> +static void guc_ct_buffer_desc_init(struct iosys_map *desc) > >> { > >> - memset(desc, 0, sizeof(*desc)); > >> + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); > >> } > >> > >> static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) > >> @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) > >> space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; > >> atomic_set(&ctb->space, space); > >> > >> - guc_ct_buffer_desc_init(ctb->desc); > >> + guc_ct_buffer_desc_init(&ctb->desc_map); > >> } > >> > >> static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, > >> - struct guc_ct_buffer_desc *desc, > >> - u32 *cmds, u32 size_in_bytes, u32 resv_space) > >> + struct iosys_map *desc, > >> + struct iosys_map *cmds, > >> + u32 size_in_bytes, u32 resv_space) > >> { > >> GEM_BUG_ON(size_in_bytes % 4); > >> > >> - ctb->desc = desc; > >> - ctb->cmds = cmds; > >> + ctb->desc_map = *desc; > >> + ctb->cmds_map = *cmds; > >> ctb->size = size_in_bytes / 4; > >> ctb->resv_space = resv_space / 4; > >> > >> @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, > >> int intel_guc_ct_init(struct intel_guc_ct *ct) > >> { > >> struct intel_guc *guc = ct_to_guc(ct); > >> - struct guc_ct_buffer_desc *desc; > >> + struct iosys_map blob_map; > >> + struct iosys_map desc_map; > >> + struct iosys_map cmds_map; > >> u32 blob_size; > >> u32 cmds_size; > >> u32 resv_space; > >> void *blob; > >> - u32 *cmds; > >> int err; > >> > >> err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); > >> @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) > >> > >> CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); > >> > >> - /* store pointers to desc and cmds for send ctb */ > >> - desc = blob; > >> - cmds = blob + 2 * CTB_DESC_SIZE; > >> + if (i915_gem_object_is_lmem(ct->vma->obj)) > >> + iosys_map_set_vaddr_iomem(&blob_map, > >> + (void __iomem *)blob); > >> + else > >> + iosys_map_set_vaddr(&blob_map, blob); > >> + > >> + /* store sysmap to desc_map and cmds_map for send ctb */ > >> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); > >> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); > >> cmds_size = CTB_H2G_BUFFER_SIZE; > >> resv_space = 0; > >> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", > >> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, > >> - resv_space); > >> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", > >> + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, > >> + cmds_size, resv_space); > >> > >> - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); > >> + guc_ct_buffer_init(&ct->ctbs.send, > >> + &desc_map, &cmds_map, cmds_size, resv_space); > >> > >> - /* store pointers to desc and cmds for recv ctb */ > >> - desc = blob + CTB_DESC_SIZE; > >> - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; > >> + /* store sysmap to desc_map and cmds_map for recv ctb */ > >> + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); > >> + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); > >> cmds_size = CTB_G2H_BUFFER_SIZE; > >> resv_space = G2H_ROOM_BUFFER_SIZE; > >> - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", > >> - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, > >> - resv_space); > >> + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", > >> + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, > >> + cmds_size, resv_space); > >> > >> - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); > >> + guc_ct_buffer_init(&ct->ctbs.recv, > >> + &desc_map, &cmds_map, cmds_size, resv_space); > >> > >> return 0; > >> } > >> @@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) > >> > >> tasklet_kill(&ct->receive_tasklet); > >> i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP); > >> + iosys_map_clear(&ct->ctbs.send.desc_map); > >> + iosys_map_clear(&ct->ctbs.send.cmds_map); > >> + iosys_map_clear(&ct->ctbs.recv.desc_map); > >> + iosys_map_clear(&ct->ctbs.recv.cmds_map); > > I think there is no need of clearing the iosys_map when were are zeroing > > the complete structure area below. > Yes, I have updated this in latest revision. > >> memset(ct, 0, sizeof(*ct)); > >> } > >> > >> @@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) > >> int intel_guc_ct_enable(struct intel_guc_ct *ct) > >> { > >> struct intel_guc *guc = ct_to_guc(ct); > >> + struct iosys_map blob_map; > >> u32 base, desc, cmds, size; > >> - void *blob; > >> int err; > >> > >> GEM_BUG_ON(ct->enabled); > >> @@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > >> GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); > >> base = intel_guc_ggtt_offset(guc, ct->vma); > >> > >> + if (i915_gem_object_is_lmem(ct->vma->obj)) > >> + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) > >> + __px_vaddr(ct->vma->obj)); > >> + else > >> + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); > >> + > >> /* blob should start with send descriptor */ > >> - blob = __px_vaddr(ct->vma->obj); > >> - GEM_BUG_ON(blob != ct->ctbs.send.desc); > >> + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); > >> > >> /* (re)initialize descriptors */ > >> guc_ct_buffer_reset(&ct->ctbs.send); > >> @@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > >> * Register both CT buffers starting with RECV buffer. > >> * Descriptors are in first half of the blob. > >> */ > >> - desc = base + ptrdiff(ct->ctbs.recv.desc, blob); > >> - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); > >> + desc = base + CTB_RECV_DESC_OFFSET; > >> + cmds = base + CTB_RECV_CMDS_OFFSET; > >> size = ct->ctbs.recv.size * 4; > >> err = ct_register_buffer(ct, false, desc, cmds, size); > >> if (unlikely(err)) > >> goto err_out; > >> > >> - desc = base + ptrdiff(ct->ctbs.send.desc, blob); > >> - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); > >> + desc = base + CTB_SEND_DESC_OFFSET; > >> + cmds = base + CTB_SEND_CMDS_OFFSET; > >> size = ct->ctbs.send.size * 4; > >> err = ct_register_buffer(ct, true, desc, cmds, size); > >> if (unlikely(err)) > >> @@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct, > >> u32 fence, u32 flags) > >> { > >> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; > >> - struct guc_ct_buffer_desc *desc = ctb->desc; > >> u32 tail = ctb->tail; > >> u32 size = ctb->size; > >> u32 header; > >> u32 hxg; > >> u32 type; > >> - u32 *cmds = ctb->cmds; > >> + u32 status = ct_desc_read(&ctb->desc_map, status); > >> unsigned int i; > >> > >> - if (unlikely(desc->status)) > >> + if (unlikely(status)) > >> goto corrupted; > >> > >> GEM_BUG_ON(tail > size); > >> > >> #ifdef CONFIG_DRM_I915_DEBUG_GUC > >> - if (unlikely(tail != READ_ONCE(desc->tail))) { > >> + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { > >> CT_ERROR(ct, "Tail was modified %u != %u\n", > >> - desc->tail, tail); > >> - desc->status |= GUC_CTB_STATUS_MISMATCH; > >> + ct_desc_read(&ctb->desc_map, tail), tail); > >> + status |= GUC_CTB_STATUS_MISMATCH; > >> + ct_desc_write(&ctb->desc_map, status, status); > >> goto corrupted; > >> } > >> - if (unlikely(READ_ONCE(desc->head) >= size)) { > >> + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) { > >> CT_ERROR(ct, "Invalid head offset %u >= %u)\n", > >> - desc->head, size); > >> - desc->status |= GUC_CTB_STATUS_OVERFLOW; > >> + ct_desc_read(&ctb->desc_map, head), size); > > Can we avoid reading the head from ctb->desc_map twice? Since each > > iosys_map read translates to memcpy, it is better to avoid repeating if > > we can cache from the earlier read. > Do you see real need of having a variable to cache value locally, considering the path is very unlikely to hit. At first I thought reading the head twice just affects performance, but after our discussion, I realized it can potentially mislead debugging. As it is possible that head can be updated concurrently, we might print a different value than what was really used in the if condition. Printing a different value can mislead debugging. So we should print the same value used in the condition. Even in the original code, READ_ONCE is used only in the condition not while printing. > >> + status = ct_desc_read(&ctb->desc_map, status) | > >> + GUC_CTB_STATUS_OVERFLOW; > > Same here, can we avoid reading status since we already have it read. We > > can do the same like how it is done for the GUC_CTB_STATUS_MISMATCH case. > Addressed in latest patch > >> + ct_desc_write(&ctb->desc_map, status, status); > >> goto corrupted; > >> } > >> #endif > >> @@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct, > >> CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", > >> tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); > >> > >> - cmds[tail] = header; > >> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, header); > > I prefer not to use the MAGIC number. My suggestion is to use > > sizeof(tail) since we need the offset in bytes. > I tried avoiding it, can't use sizeof(tail). Here tail is just an index which might be a misleading if we use it in this case, cmds would have been the right one but this has been changed to iosys map. Currently updated with sizeof(u32). > >> tail = (tail + 1) % size; > >> > >> - cmds[tail] = hxg; > >> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, hxg); > > MAGIC number again. There are numerous places in the patch, where > > numbers are used. I prefer to remove it. > >> tail = (tail + 1) % size; > >> > >> for (i = 1; i < len; i++) { > >> - cmds[tail] = action[i]; > >> + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, action[i]); > >> tail = (tail + 1) % size; > >> } > >> GEM_BUG_ON(tail > size); > >> @@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct, > >> atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); > >> > >> /* now update descriptor */ > >> - WRITE_ONCE(desc->tail, tail); > >> + ct_desc_write(&ctb->desc_map, tail, tail); > >> > >> return 0; > >> > >> corrupted: > >> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", > >> - desc->head, desc->tail, desc->status); > >> + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail), > >> + ct_desc_read(&ctb->desc_map, status)); > >> ctb->broken = true; > >> return -EPIPE; > >> } > >> @@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) > >> bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; > >> > >> if (unlikely(ret)) { > >> - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; > >> - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; > >> - > >> CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", > >> ktime_ms_delta(ktime_get(), ct->stall_time), > >> - send->status, recv->status); > >> + ct_desc_read(&ct->ctbs.send.desc_map, status), > >> + ct_desc_read(&ct->ctbs.recv.desc_map, status)); > >> CT_ERROR(ct, "H2G Space: %u (Bytes)\n", > >> atomic_read(&ct->ctbs.send.space) * 4); > >> - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); > >> - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); > >> + CT_ERROR(ct, "Head: %u (Dwords)\n", > >> + ct_desc_read(&ct->ctbs.send.desc_map, head)); > >> + CT_ERROR(ct, "Tail: %u (Dwords)\n", > >> + ct_desc_read(&ct->ctbs.send.desc_map, tail)); > >> CT_ERROR(ct, "G2H Space: %u (Bytes)\n", > >> atomic_read(&ct->ctbs.recv.space) * 4); > >> - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); > >> - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); > >> + CT_ERROR(ct, "Head: %u\n (Dwords)", > >> + ct_desc_read(&ct->ctbs.recv.desc_map, head)); > >> + CT_ERROR(ct, "Tail: %u\n (Dwords)", > >> + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > >> > >> ct->ctbs.send.broken = true; > >> } > >> @@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) > >> static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) > >> { > >> struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; > >> - struct guc_ct_buffer_desc *desc = ctb->desc; > >> u32 head; > >> u32 space; > >> + u32 status = ct_desc_read(&ctb->desc_map, status); > >> > >> if (atomic_read(&ctb->space) >= len_dw) > >> return true; > >> > >> - head = READ_ONCE(desc->head); > >> + head = ct_desc_read(&ctb->desc_map, head); > >> if (unlikely(head > ctb->size)) { > >> CT_ERROR(ct, "Invalid head offset %u >= %u)\n", > >> head, ctb->size); > >> - desc->status |= GUC_CTB_STATUS_OVERFLOW; > >> + status |= GUC_CTB_STATUS_OVERFLOW; > >> + ct_desc_write(&ctb->desc_map, status, status); > >> ctb->broken = true; > >> return false; > >> } > >> @@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg) > >> static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > >> { > >> struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; > >> - struct guc_ct_buffer_desc *desc = ctb->desc; > >> u32 head = ctb->head; > >> - u32 tail = READ_ONCE(desc->tail); > >> + u32 tail = ct_desc_read(&ctb->desc_map, tail); > >> u32 size = ctb->size; > >> - u32 *cmds = ctb->cmds; > >> + u32 status = ct_desc_read(&ctb->desc_map, status); > >> s32 available; > >> unsigned int len; > >> unsigned int i; > >> @@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > >> if (unlikely(ctb->broken)) > >> return -EPIPE; > >> > >> - if (unlikely(desc->status)) > >> + if (unlikely(status)) > >> goto corrupted; > >> > >> GEM_BUG_ON(head > size); > >> > >> #ifdef CONFIG_DRM_I915_DEBUG_GUC > >> - if (unlikely(head != READ_ONCE(desc->head))) { > >> + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) { > >> CT_ERROR(ct, "Head was modified %u != %u\n", > >> - desc->head, head); > >> - desc->status |= GUC_CTB_STATUS_MISMATCH; > >> + ct_desc_read(&ctb->desc_map, head), head); > > head read twice here as well. > Same answer. > >> + status |= GUC_CTB_STATUS_MISMATCH; > >> + ct_desc_write(&ctb->desc_map, status, status); > >> goto corrupted; > >> } > >> #endif > >> if (unlikely(tail >= size)) { > >> CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", > >> tail, size); > >> - desc->status |= GUC_CTB_STATUS_OVERFLOW; > >> + status = ct_desc_read(&ctb->desc_map, status) | > >> + GUC_CTB_STATUS_OVERFLOW; > > No need to read the status again as we already have it cached. > addressed. > >> + ct_desc_write(&ctb->desc_map, status, status); > >> goto corrupted; > >> } > >> > >> @@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > >> CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); > >> GEM_BUG_ON(available < 0); > >> > >> - header = cmds[head]; > >> + header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32); > > MAGIC numbers > >> head = (head + 1) % size; > >> > >> /* message len with header */ > >> @@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > >> if (unlikely(len > (u32)available)) { > >> CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", > >> 4, &header, > >> + 4 * (head + available - 1 > size ? size - head : > >> + available - 1), ((__px_vaddr(ct->vma->obj) + > >> + CTB_RECV_CMDS_OFFSET) + (4 * head)), > >> 4 * (head + available - 1 > size ? > >> - size - head : available - 1), &cmds[head], > >> - 4 * (head + available - 1 > size ? > >> - available - 1 - size + head : 0), &cmds[0]); > >> - desc->status |= GUC_CTB_STATUS_UNDERFLOW; > >> + available - 1 - size + head : 0), > >> + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); > >> + status = ct_desc_read(&ctb->desc_map, status) | > >> + GUC_CTB_STATUS_UNDERFLOW; > > No need to read status again > > > > Regards, > > Bala > >> + ct_desc_write(&ctb->desc_map, status, status); > >> goto corrupted; > >> } > >> > >> @@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > >> if (!*msg) { > >> CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", > >> 4, &header, > >> + 4 * (head + available - 1 > size ? size - head : > >> + available - 1), (ctb->cmds_map.vaddr + (4 * head)), > >> 4 * (head + available - 1 > size ? > >> - size - head : available - 1), &cmds[head], > >> - 4 * (head + available - 1 > size ? > >> - available - 1 - size + head : 0), &cmds[0]); > >> + available - 1 - size + head : 0), ctb->cmds_map.vaddr); > >> return available; > >> } > >> > >> (*msg)->msg[0] = header; > >> > >> for (i = 1; i < len; i++) { > >> - (*msg)->msg[i] = cmds[head]; > >> + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, > >> + (4 * head), u32); > >> head = (head + 1) % size; > >> } > >> CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); > >> @@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > >> ctb->head = head; > >> > >> /* now update descriptor */ > >> - WRITE_ONCE(desc->head, head); > >> + ct_desc_write(&ctb->desc_map, head, head); > >> > >> return available - len; > >> > >> corrupted: > >> CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", > >> - desc->head, desc->tail, desc->status); > >> + ct_desc_read(&ctb->desc_map, head), > >> + ct_desc_read(&ctb->desc_map, tail), > >> + ct_desc_read(&ctb->desc_map, status)); > >> ctb->broken = true; > >> return -EPIPE; > >> } > >> @@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, > >> drm_printf(p, "H2G Space: %u\n", > >> atomic_read(&ct->ctbs.send.space) * 4); > >> drm_printf(p, "Head: %u\n", > >> - ct->ctbs.send.desc->head); > >> + ct_desc_read(&ct->ctbs.send.desc_map, head)); > >> drm_printf(p, "Tail: %u\n", > >> - ct->ctbs.send.desc->tail); > >> + ct_desc_read(&ct->ctbs.send.desc_map, tail)); > >> drm_printf(p, "G2H Space: %u\n", > >> atomic_read(&ct->ctbs.recv.space) * 4); > >> drm_printf(p, "Head: %u\n", > >> - ct->ctbs.recv.desc->head); > >> + ct_desc_read(&ct->ctbs.recv.desc_map, head)); > >> drm_printf(p, "Tail: %u\n", > >> - ct->ctbs.recv.desc->tail); > >> + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > >> } > >> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > >> index f709a19c7e21..867fe13fb47d 100644 > >> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > >> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > >> @@ -7,6 +7,7 @@ > >> #define _INTEL_GUC_CT_H_ > >> > >> #include <linux/interrupt.h> > >> +#include <linux/iosys-map.h> > >> #include <linux/spinlock.h> > >> #include <linux/workqueue.h> > >> #include <linux/ktime.h> > >> @@ -32,8 +33,8 @@ struct drm_printer; > >> * holds the commands. > >> * > >> * @lock: protects access to the commands buffer and buffer descriptor > >> - * @desc: pointer to the buffer descriptor > >> - * @cmds: pointer to the commands buffer > >> + * @desc: iosys map to the buffer descriptor > >> + * @cmds: iosys map to the commands buffer > >> * @size: size of the commands buffer in dwords > >> * @resv_space: reserved space in buffer in dwords > >> * @head: local shadow copy of head in dwords > >> @@ -43,8 +44,8 @@ struct drm_printer; > >> */ > >> struct intel_guc_ct_buffer { > >> spinlock_t lock; > >> - struct guc_ct_buffer_desc *desc; > >> - u32 *cmds; > >> + struct iosys_map desc_map; > >> + struct iosys_map cmds_map; > >> u32 size; > >> u32 resv_space; > >> u32 tail; > >> -- > >> 2.33.0 > >> ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-04-04 9:31 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva 2022-04-14 12:11 ` Balasubramani Vivekanandan @ 2022-04-18 9:08 ` Balasubramani Vivekanandan 1 sibling, 0 replies; 16+ messages in thread From: Balasubramani Vivekanandan @ 2022-04-18 9:08 UTC (permalink / raw) To: Mullati Siva, intel-gfx; +Cc: lucas.demarchi On 04.04.2022 15:01, Mullati Siva wrote: > From: Siva Mullati <siva.mullati@intel.com> > > Convert CT commands and descriptors to use iosys_map rather > than plain pointer and save it in the intel_guc_ct_buffer struct. > This will help with ct_write and ct_read for cmd send and receive > after the initialization by abstracting the IO vs system memory. > > Signed-off-by: Siva Mullati <siva.mullati@intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++--------- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- > 2 files changed, 127 insertions(+), 82 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > index f01325cd1b62..64568dc90b05 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > #define CT_PROBE_ERROR(_ct, _fmt, ...) \ > i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) > > +#define ct_desc_read(desc_map_, field_) \ > + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) > +#define ct_desc_write(desc_map_, field_, val_) \ > + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) > + > /** > * DOC: CTB Blob > * > @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) > #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) > > +#define CTB_SEND_DESC_OFFSET 0u > +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) > +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) > +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) > + > struct ct_request { > struct list_head link; > u32 fence; > @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) > init_waitqueue_head(&ct->wq); > } > > -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) > +static void guc_ct_buffer_desc_init(struct iosys_map *desc) > { > - memset(desc, 0, sizeof(*desc)); > + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); > } > > static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) > @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) > space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; > atomic_set(&ctb->space, space); > > - guc_ct_buffer_desc_init(ctb->desc); > + guc_ct_buffer_desc_init(&ctb->desc_map); > } > > static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, > - struct guc_ct_buffer_desc *desc, > - u32 *cmds, u32 size_in_bytes, u32 resv_space) > + struct iosys_map *desc, > + struct iosys_map *cmds, > + u32 size_in_bytes, u32 resv_space) > { > GEM_BUG_ON(size_in_bytes % 4); > > - ctb->desc = desc; > - ctb->cmds = cmds; > + ctb->desc_map = *desc; > + ctb->cmds_map = *cmds; > ctb->size = size_in_bytes / 4; > ctb->resv_space = resv_space / 4; > > @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, > int intel_guc_ct_init(struct intel_guc_ct *ct) > { > struct intel_guc *guc = ct_to_guc(ct); > - struct guc_ct_buffer_desc *desc; > + struct iosys_map blob_map; > + struct iosys_map desc_map; > + struct iosys_map cmds_map; > u32 blob_size; > u32 cmds_size; > u32 resv_space; > void *blob; > - u32 *cmds; > int err; > > err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); > @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) > > CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); > > - /* store pointers to desc and cmds for send ctb */ > - desc = blob; > - cmds = blob + 2 * CTB_DESC_SIZE; > + if (i915_gem_object_is_lmem(ct->vma->obj)) > + iosys_map_set_vaddr_iomem(&blob_map, > + (void __iomem *)blob); > + else > + iosys_map_set_vaddr(&blob_map, blob); > + > + /* store sysmap to desc_map and cmds_map for send ctb */ > + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); > + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); > cmds_size = CTB_H2G_BUFFER_SIZE; > resv_space = 0; > - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", > - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, > - resv_space); > + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", > + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, > + cmds_size, resv_space); > > - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); > + guc_ct_buffer_init(&ct->ctbs.send, > + &desc_map, &cmds_map, cmds_size, resv_space); > > - /* store pointers to desc and cmds for recv ctb */ > - desc = blob + CTB_DESC_SIZE; > - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; > + /* store sysmap to desc_map and cmds_map for recv ctb */ > + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); > + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); > cmds_size = CTB_G2H_BUFFER_SIZE; > resv_space = G2H_ROOM_BUFFER_SIZE; > - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", > - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, > - resv_space); > + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", > + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, > + cmds_size, resv_space); > > - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); > + guc_ct_buffer_init(&ct->ctbs.recv, > + &desc_map, &cmds_map, cmds_size, resv_space); > > return 0; > } > @@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) > > tasklet_kill(&ct->receive_tasklet); > i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP); > + iosys_map_clear(&ct->ctbs.send.desc_map); > + iosys_map_clear(&ct->ctbs.send.cmds_map); > + iosys_map_clear(&ct->ctbs.recv.desc_map); > + iosys_map_clear(&ct->ctbs.recv.cmds_map); > memset(ct, 0, sizeof(*ct)); > } > > @@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) > int intel_guc_ct_enable(struct intel_guc_ct *ct) > { > struct intel_guc *guc = ct_to_guc(ct); > + struct iosys_map blob_map; > u32 base, desc, cmds, size; > - void *blob; > int err; > > GEM_BUG_ON(ct->enabled); > @@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); > base = intel_guc_ggtt_offset(guc, ct->vma); > > + if (i915_gem_object_is_lmem(ct->vma->obj)) > + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) > + __px_vaddr(ct->vma->obj)); > + else > + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); > + > /* blob should start with send descriptor */ > - blob = __px_vaddr(ct->vma->obj); > - GEM_BUG_ON(blob != ct->ctbs.send.desc); > + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); > > /* (re)initialize descriptors */ > guc_ct_buffer_reset(&ct->ctbs.send); > @@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > * Register both CT buffers starting with RECV buffer. > * Descriptors are in first half of the blob. > */ > - desc = base + ptrdiff(ct->ctbs.recv.desc, blob); > - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); > + desc = base + CTB_RECV_DESC_OFFSET; > + cmds = base + CTB_RECV_CMDS_OFFSET; > size = ct->ctbs.recv.size * 4; > err = ct_register_buffer(ct, false, desc, cmds, size); > if (unlikely(err)) > goto err_out; > > - desc = base + ptrdiff(ct->ctbs.send.desc, blob); > - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); > + desc = base + CTB_SEND_DESC_OFFSET; > + cmds = base + CTB_SEND_CMDS_OFFSET; > size = ct->ctbs.send.size * 4; > err = ct_register_buffer(ct, true, desc, cmds, size); > if (unlikely(err)) > @@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct, > u32 fence, u32 flags) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; > - struct guc_ct_buffer_desc *desc = ctb->desc; > u32 tail = ctb->tail; > u32 size = ctb->size; > u32 header; > u32 hxg; > u32 type; > - u32 *cmds = ctb->cmds; > + u32 status = ct_desc_read(&ctb->desc_map, status); > unsigned int i; > > - if (unlikely(desc->status)) > + if (unlikely(status)) > goto corrupted; > > GEM_BUG_ON(tail > size); > > #ifdef CONFIG_DRM_I915_DEBUG_GUC > - if (unlikely(tail != READ_ONCE(desc->tail))) { > + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { > CT_ERROR(ct, "Tail was modified %u != %u\n", > - desc->tail, tail); > - desc->status |= GUC_CTB_STATUS_MISMATCH; > + ct_desc_read(&ctb->desc_map, tail), tail); > + status |= GUC_CTB_STATUS_MISMATCH; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > - if (unlikely(READ_ONCE(desc->head) >= size)) { > + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) { > CT_ERROR(ct, "Invalid head offset %u >= %u)\n", > - desc->head, size); > - desc->status |= GUC_CTB_STATUS_OVERFLOW; > + ct_desc_read(&ctb->desc_map, head), size); > + status = ct_desc_read(&ctb->desc_map, status) | > + GUC_CTB_STATUS_OVERFLOW; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > #endif > @@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct, > CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", > tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); > > - cmds[tail] = header; > + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, header); > tail = (tail + 1) % size; > > - cmds[tail] = hxg; > + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, hxg); > tail = (tail + 1) % size; > > for (i = 1; i < len; i++) { > - cmds[tail] = action[i]; > + iosys_map_wr(&ctb->cmds_map, 4 * tail, u32, action[i]); > tail = (tail + 1) % size; > } > GEM_BUG_ON(tail > size); > @@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct, > atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); > > /* now update descriptor */ > - WRITE_ONCE(desc->tail, tail); > + ct_desc_write(&ctb->desc_map, tail, tail); > > return 0; > > corrupted: > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", > - desc->head, desc->tail, desc->status); > + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail), > + ct_desc_read(&ctb->desc_map, status)); > ctb->broken = true; > return -EPIPE; > } > @@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) > bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; > > if (unlikely(ret)) { > - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; > - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; > - > CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", > ktime_ms_delta(ktime_get(), ct->stall_time), > - send->status, recv->status); > + ct_desc_read(&ct->ctbs.send.desc_map, status), > + ct_desc_read(&ct->ctbs.recv.desc_map, status)); > CT_ERROR(ct, "H2G Space: %u (Bytes)\n", > atomic_read(&ct->ctbs.send.space) * 4); > - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); > - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); > + CT_ERROR(ct, "Head: %u (Dwords)\n", > + ct_desc_read(&ct->ctbs.send.desc_map, head)); > + CT_ERROR(ct, "Tail: %u (Dwords)\n", > + ct_desc_read(&ct->ctbs.send.desc_map, tail)); > CT_ERROR(ct, "G2H Space: %u (Bytes)\n", > atomic_read(&ct->ctbs.recv.space) * 4); > - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); > - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); > + CT_ERROR(ct, "Head: %u\n (Dwords)", > + ct_desc_read(&ct->ctbs.recv.desc_map, head)); > + CT_ERROR(ct, "Tail: %u\n (Dwords)", > + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > > ct->ctbs.send.broken = true; > } > @@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) > static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; > - struct guc_ct_buffer_desc *desc = ctb->desc; > u32 head; > u32 space; > + u32 status = ct_desc_read(&ctb->desc_map, status); > > if (atomic_read(&ctb->space) >= len_dw) > return true; > > - head = READ_ONCE(desc->head); > + head = ct_desc_read(&ctb->desc_map, head); > if (unlikely(head > ctb->size)) { > CT_ERROR(ct, "Invalid head offset %u >= %u)\n", > head, ctb->size); > - desc->status |= GUC_CTB_STATUS_OVERFLOW; > + status |= GUC_CTB_STATUS_OVERFLOW; > + ct_desc_write(&ctb->desc_map, status, status); > ctb->broken = true; > return false; > } > @@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg) > static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; > - struct guc_ct_buffer_desc *desc = ctb->desc; > u32 head = ctb->head; > - u32 tail = READ_ONCE(desc->tail); > + u32 tail = ct_desc_read(&ctb->desc_map, tail); > u32 size = ctb->size; > - u32 *cmds = ctb->cmds; > + u32 status = ct_desc_read(&ctb->desc_map, status); > s32 available; > unsigned int len; > unsigned int i; > @@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (unlikely(ctb->broken)) > return -EPIPE; > > - if (unlikely(desc->status)) > + if (unlikely(status)) > goto corrupted; > > GEM_BUG_ON(head > size); > > #ifdef CONFIG_DRM_I915_DEBUG_GUC > - if (unlikely(head != READ_ONCE(desc->head))) { > + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) { > CT_ERROR(ct, "Head was modified %u != %u\n", > - desc->head, head); > - desc->status |= GUC_CTB_STATUS_MISMATCH; > + ct_desc_read(&ctb->desc_map, head), head); > + status |= GUC_CTB_STATUS_MISMATCH; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > #endif > if (unlikely(tail >= size)) { > CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", > tail, size); > - desc->status |= GUC_CTB_STATUS_OVERFLOW; > + status = ct_desc_read(&ctb->desc_map, status) | > + GUC_CTB_STATUS_OVERFLOW; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > > @@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); > GEM_BUG_ON(available < 0); > > - header = cmds[head]; > + header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32); > head = (head + 1) % size; > > /* message len with header */ > @@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (unlikely(len > (u32)available)) { > CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", > 4, &header, > + 4 * (head + available - 1 > size ? size - head : > + available - 1), ((__px_vaddr(ct->vma->obj) + > + CTB_RECV_CMDS_OFFSET) + (4 * head)), > 4 * (head + available - 1 > size ? > - size - head : available - 1), &cmds[head], > - 4 * (head + available - 1 > size ? > - available - 1 - size + head : 0), &cmds[0]); > - desc->status |= GUC_CTB_STATUS_UNDERFLOW; > + available - 1 - size + head : 0), > + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); > + status = ct_desc_read(&ctb->desc_map, status) | > + GUC_CTB_STATUS_UNDERFLOW; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > > @@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (!*msg) { > CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", > 4, &header, > + 4 * (head + available - 1 > size ? size - head : > + available - 1), (ctb->cmds_map.vaddr + (4 * head)), We cannot directly use the vaddr here as the cmds_map may contain system memory or io memory address. You need to check the address type and use the right member. > 4 * (head + available - 1 > size ? > - size - head : available - 1), &cmds[head], > - 4 * (head + available - 1 > size ? > - available - 1 - size + head : 0), &cmds[0]); > + available - 1 - size + head : 0), ctb->cmds_map.vaddr); Also here. > return available; > } > > (*msg)->msg[0] = header; > > for (i = 1; i < len; i++) { > - (*msg)->msg[i] = cmds[head]; > + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, > + (4 * head), u32); > head = (head + 1) % size; > } > CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); > @@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > ctb->head = head; > > /* now update descriptor */ > - WRITE_ONCE(desc->head, head); > + ct_desc_write(&ctb->desc_map, head, head); > > return available - len; > > corrupted: > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", > - desc->head, desc->tail, desc->status); > + ct_desc_read(&ctb->desc_map, head), > + ct_desc_read(&ctb->desc_map, tail), > + ct_desc_read(&ctb->desc_map, status)); > ctb->broken = true; > return -EPIPE; > } > @@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, > drm_printf(p, "H2G Space: %u\n", > atomic_read(&ct->ctbs.send.space) * 4); > drm_printf(p, "Head: %u\n", > - ct->ctbs.send.desc->head); > + ct_desc_read(&ct->ctbs.send.desc_map, head)); > drm_printf(p, "Tail: %u\n", > - ct->ctbs.send.desc->tail); > + ct_desc_read(&ct->ctbs.send.desc_map, tail)); > drm_printf(p, "G2H Space: %u\n", > atomic_read(&ct->ctbs.recv.space) * 4); > drm_printf(p, "Head: %u\n", > - ct->ctbs.recv.desc->head); > + ct_desc_read(&ct->ctbs.recv.desc_map, head)); > drm_printf(p, "Tail: %u\n", > - ct->ctbs.recv.desc->tail); > + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > } > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > index f709a19c7e21..867fe13fb47d 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > @@ -7,6 +7,7 @@ > #define _INTEL_GUC_CT_H_ > > #include <linux/interrupt.h> > +#include <linux/iosys-map.h> > #include <linux/spinlock.h> > #include <linux/workqueue.h> > #include <linux/ktime.h> > @@ -32,8 +33,8 @@ struct drm_printer; > * holds the commands. > * > * @lock: protects access to the commands buffer and buffer descriptor > - * @desc: pointer to the buffer descriptor > - * @cmds: pointer to the commands buffer > + * @desc: iosys map to the buffer descriptor > + * @cmds: iosys map to the commands buffer > * @size: size of the commands buffer in dwords > * @resv_space: reserved space in buffer in dwords > * @head: local shadow copy of head in dwords > @@ -43,8 +44,8 @@ struct drm_printer; > */ > struct intel_guc_ct_buffer { > spinlock_t lock; > - struct guc_ct_buffer_desc *desc; > - u32 *cmds; > + struct iosys_map desc_map; > + struct iosys_map cmds_map; > u32 size; > u32 resv_space; > u32 tail; > -- > 2.33.0 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev3) 2022-04-04 9:31 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva 2022-04-04 9:31 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva @ 2022-04-04 10:41 ` Patchwork 2022-04-04 11:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (3 subsequent siblings) 5 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-04-04 10:41 UTC (permalink / raw) To: Mullati Siva; +Cc: intel-gfx == Series Details == Series: drm/i915/guc: Refactor CT access to use iosys_map (rev3) URL : https://patchwork.freedesktop.org/series/101148/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Refactor CT access to use iosys_map (rev3) 2022-04-04 9:31 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva 2022-04-04 9:31 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva 2022-04-04 10:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev3) Patchwork @ 2022-04-04 11:14 ` Patchwork 2022-04-04 13:42 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork ` (2 subsequent siblings) 5 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-04-04 11:14 UTC (permalink / raw) To: Mullati Siva; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 8322 bytes --] == Series Details == Series: drm/i915/guc: Refactor CT access to use iosys_map (rev3) URL : https://patchwork.freedesktop.org/series/101148/ State : success == Summary == CI Bug Log - changes from CI_DRM_11446 -> Patchwork_22771 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/index.html Participating hosts (45 -> 43) ------------------------------ Additional (1): bat-rpls-2 Missing (3): fi-bsw-cyan fi-icl-u2 fi-bdw-samus Known issues ------------ Here are the changes found in Patchwork_22771 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_cs_nop@sync-gfx0: - fi-rkl-11600: NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@amdgpu/amd_cs_nop@sync-gfx0.html * igt@gem_huc_copy@huc-copy: - fi-rkl-11600: NOTRUN -> [SKIP][2] ([i915#2190]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@gem_lmem_swapping@basic.html * igt@gem_tiled_pread_basic: - fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#3282]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#3012]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html * igt@i915_selftest@live@gt_engines: - bat-dg1-6: [PASS][6] -> [INCOMPLETE][7] ([i915#4418]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/bat-dg1-6/igt@i915_selftest@live@gt_engines.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/bat-dg1-6/igt@i915_selftest@live@gt_engines.html * igt@kms_chamelium@dp-crc-fast: - fi-rkl-11600: NOTRUN -> [SKIP][8] ([fdo#111827]) +8 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@kms_chamelium@dp-crc-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-rkl-11600: NOTRUN -> [SKIP][9] ([i915#4070] / [i915#4103]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_flip@basic-flip-vs-modeset@a-edp1: - fi-tgl-u2: [PASS][10] -> [DMESG-WARN][11] ([i915#402]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/fi-tgl-u2/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-tgl-u2/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html * igt@kms_force_connector_basic@force-load-detect: - fi-rkl-11600: NOTRUN -> [SKIP][12] ([fdo#109285] / [i915#4098]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-rkl-11600: NOTRUN -> [SKIP][13] ([i915#4070] / [i915#533]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_mmap_gtt: - fi-rkl-11600: NOTRUN -> [SKIP][14] ([i915#1072]) +3 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@kms_psr@primary_mmap_gtt.html * igt@kms_setmode@basic-clone-single-crtc: - fi-rkl-11600: NOTRUN -> [SKIP][15] ([i915#3555] / [i915#4098]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-userptr: - fi-rkl-11600: NOTRUN -> [SKIP][16] ([i915#3301] / [i915#3708]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@prime_vgem@basic-userptr.html * igt@prime_vgem@basic-write: - fi-rkl-11600: NOTRUN -> [SKIP][17] ([i915#3291] / [i915#3708]) +2 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@prime_vgem@basic-write.html * igt@runner@aborted: - bat-dg1-6: NOTRUN -> [FAIL][18] ([i915#4312] / [i915#5257]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/bat-dg1-6/igt@runner@aborted.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s3@smem: - fi-rkl-11600: [INCOMPLETE][19] ([i915#5127]) -> [PASS][20] [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html * igt@kms_busy@basic@modeset: - {bat-adlp-6}: [DMESG-WARN][21] ([i915#3576]) -> [PASS][22] [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/bat-adlp-6/igt@kms_busy@basic@modeset.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/bat-adlp-6/igt@kms_busy@basic@modeset.html * igt@kms_flip@basic-plain-flip@a-edp1: - fi-tgl-u2: [DMESG-WARN][23] ([i915#402]) -> [PASS][24] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5535]: https://gitlab.freedesktop.org/drm/intel/issues/5535 Build changes ------------- * Linux: CI_DRM_11446 -> Patchwork_22771 CI-20190529: 20190529 CI_DRM_11446: 517ca0f267ede31213c57d17bcea56728cbe3b1d @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6408: 28e8b61068ee67efe9dc1c5467359a2b993f5b5d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22771: ea1dfe80f93577f3221e71650ea2edb82414fef0 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ea1dfe80f935 drm/i915/guc: Convert ct buffer to iosys_map == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/index.html [-- Attachment #2: Type: text/html, Size: 9334 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Refactor CT access to use iosys_map (rev3) 2022-04-04 9:31 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva ` (2 preceding siblings ...) 2022-04-04 11:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2022-04-04 13:42 ` Patchwork 2022-04-08 5:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev4) Patchwork 2022-04-08 5:42 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 5 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-04-04 13:42 UTC (permalink / raw) To: Mullati Siva; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30280 bytes --] == Series Details == Series: drm/i915/guc: Refactor CT access to use iosys_map (rev3) URL : https://patchwork.freedesktop.org/series/101148/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11446_full -> Patchwork_22771_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_22771_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22771_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_22771_full: ### IGT changes ### #### Possible regressions #### * igt@i915_selftest@live@ring_submission: - shard-skl: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-skl7/igt@i915_selftest@live@ring_submission.html Known issues ------------ Here are the changes found in Patchwork_22771_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ccs@block-copy-inplace: - shard-iclb: NOTRUN -> [SKIP][2] ([i915#5327]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@gem_ccs@block-copy-inplace.html * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][3] ([i915#4991]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl4/igt@gem_create@create-massive.html - shard-apl: NOTRUN -> [DMESG-WARN][4] ([i915#4991]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl4/igt@gem_create@create-massive.html * igt@gem_eio@in-flight-suspend: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-kbl7/igt@gem_eio@in-flight-suspend.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl1/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_balancer@parallel-contexts: - shard-kbl: NOTRUN -> [DMESG-WARN][7] ([i915#5076]) +1 similar issue [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl3/igt@gem_exec_balancer@parallel-contexts.html * igt@gem_exec_balancer@parallel-out-fence: - shard-iclb: NOTRUN -> [SKIP][8] ([i915#4525]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@gem_exec_balancer@parallel-out-fence.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb1/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_params@no-bsd: - shard-tglb: NOTRUN -> [SKIP][11] ([fdo#109283]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@gem_exec_params@no-bsd.html * igt@gem_exec_whisper@basic-fds-priority-all: - shard-iclb: [PASS][12] -> [INCOMPLETE][13] ([i915#1895]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-iclb2/igt@gem_exec_whisper@basic-fds-priority-all.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb4/igt@gem_exec_whisper@basic-fds-priority-all.html * igt@gem_lmem_swapping@parallel-multi: - shard-apl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl6/igt@gem_lmem_swapping@parallel-multi.html * igt@gem_lmem_swapping@verify-random: - shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl1/igt@gem_lmem_swapping@verify-random.html * igt@gem_pwrite@basic-exhaustion: - shard-glk: NOTRUN -> [WARN][16] ([i915#2658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-glk9/igt@gem_pwrite@basic-exhaustion.html * igt@gem_pxp@display-protected-crc: - shard-iclb: NOTRUN -> [SKIP][17] ([i915#4270]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb5/igt@gem_pxp@display-protected-crc.html * igt@gem_render_copy@y-tiled-to-vebox-linear: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#768]) +1 similar issue [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@gem_render_copy@y-tiled-to-vebox-linear.html * igt@gem_softpin@noreloc-s3: - shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-apl6/igt@gem_softpin@noreloc-s3.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl4/igt@gem_softpin@noreloc-s3.html * igt@gem_userptr_blits@coherency-sync: - shard-iclb: NOTRUN -> [SKIP][21] ([fdo#109290]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@gem_userptr_blits@coherency-sync.html * igt@gem_userptr_blits@dmabuf-unsync: - shard-iclb: NOTRUN -> [SKIP][22] ([i915#3297]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@gem_userptr_blits@dmabuf-unsync.html * igt@gem_userptr_blits@vma-merge: - shard-apl: NOTRUN -> [FAIL][23] ([i915#3318]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl8/igt@gem_userptr_blits@vma-merge.html - shard-kbl: NOTRUN -> [FAIL][24] ([i915#3318]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl6/igt@gem_userptr_blits@vma-merge.html * igt@gen7_exec_parse@basic-offset: - shard-apl: NOTRUN -> [SKIP][25] ([fdo#109271]) +169 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl7/igt@gen7_exec_parse@basic-offset.html * igt@gen9_exec_parse@allowed-single: - shard-skl: NOTRUN -> [DMESG-WARN][26] ([i915#1436] / [i915#716]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-skl6/igt@gen9_exec_parse@allowed-single.html * igt@gen9_exec_parse@unaligned-access: - shard-iclb: NOTRUN -> [SKIP][27] ([i915#2856]) +2 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb5/igt@gen9_exec_parse@unaligned-access.html * igt@i915_pm_rpm@dpms-mode-unset-non-lpsp: - shard-glk: [PASS][28] -> [DMESG-WARN][29] ([i915#118] / [i915#1888]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-glk2/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-glk6/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html * igt@i915_pm_rpm@modeset-pc8-residency-stress: - shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271]) +8 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-skl6/igt@i915_pm_rpm@modeset-pc8-residency-stress.html * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-tglb: NOTRUN -> [SKIP][31] ([i915#5286]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@x-tiled-32bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][32] ([fdo#110725] / [fdo#111614]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb5/igt@kms_big_fb@x-tiled-32bpp-rotate-90.html * igt@kms_big_fb@x-tiled-64bpp-rotate-270: - shard-tglb: NOTRUN -> [SKIP][33] ([fdo#111614]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip: - shard-kbl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3777]) +4 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][35] ([fdo#110723]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip: - shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3777]) +2 similar issues [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip.html * igt@kms_big_joiner@2x-modeset: - shard-tglb: NOTRUN -> [SKIP][37] ([i915#2705]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_big_joiner@2x-modeset.html * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109278] / [i915#3886]) +1 similar issue [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb5/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html - shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3886]) +8 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl7/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][40] ([fdo#111615] / [i915#3689]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs.html * igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc: - shard-kbl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3886]) +8 similar issues [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl1/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-d-crc-primary-rotation-180-y_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][42] ([i915#3689]) [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_ccs@pipe-d-crc-primary-rotation-180-y_tiled_ccs.html * igt@kms_chamelium@hdmi-edid-change-during-suspend: - shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-skl6/igt@kms_chamelium@hdmi-edid-change-during-suspend.html * igt@kms_chamelium@hdmi-hpd-storm: - shard-tglb: NOTRUN -> [SKIP][44] ([fdo#109284] / [fdo#111827]) +1 similar issue [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_chamelium@hdmi-hpd-storm.html * igt@kms_color@pipe-b-deep-color: - shard-tglb: NOTRUN -> [SKIP][45] ([i915#3555]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_color@pipe-b-deep-color.html * igt@kms_color@pipe-d-ctm-green-to-red: - shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109278] / [i915#1149]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_color@pipe-d-ctm-green-to-red.html * igt@kms_color_chamelium@pipe-c-ctm-0-5: - shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109284] / [fdo#111827]) +4 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_color_chamelium@pipe-c-ctm-0-5.html * igt@kms_color_chamelium@pipe-c-gamma: - shard-kbl: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +11 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl7/igt@kms_color_chamelium@pipe-c-gamma.html - shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +10 similar issues [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl7/igt@kms_color_chamelium@pipe-c-gamma.html * igt@kms_color_chamelium@pipe-d-ctm-red-to-blue: - shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109278] / [fdo#109284] / [fdo#111827]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb5/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html * igt@kms_content_protection@uevent: - shard-apl: NOTRUN -> [FAIL][51] ([i915#2105]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl8/igt@kms_content_protection@uevent.html - shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109300] / [fdo#111066]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_content_protection@uevent.html * igt@kms_cursor_crc@pipe-a-cursor-512x170-random: - shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109279] / [i915#3359]) +1 similar issue [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html * igt@kms_cursor_crc@pipe-b-cursor-512x512-offscreen: - shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109278] / [fdo#109279]) +1 similar issue [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_cursor_crc@pipe-b-cursor-512x512-offscreen.html * igt@kms_cursor_crc@pipe-c-cursor-max-size-random: - shard-tglb: NOTRUN -> [SKIP][55] ([i915#3359]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-max-size-random.html * igt@kms_cursor_legacy@cursora-vs-flipb-atomic: - shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109274] / [fdo#109278]) +1 similar issue [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-apl: [PASS][57] -> [FAIL][58] ([i915#2346] / [i915#533]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_cursor_legacy@pipe-d-single-move: - shard-iclb: NOTRUN -> [SKIP][59] ([fdo#109278]) +13 similar issues [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_cursor_legacy@pipe-d-single-move.html * igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled: - shard-iclb: NOTRUN -> [SKIP][60] ([i915#5287]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb5/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-4tiled.html * igt@kms_flip@2x-busy-flip: - shard-tglb: NOTRUN -> [SKIP][61] ([fdo#109274] / [fdo#111825]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_flip@2x-busy-flip.html * igt@kms_flip@2x-nonexisting-fb: - shard-iclb: NOTRUN -> [SKIP][62] ([fdo#109274]) +4 similar issues [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb5/igt@kms_flip@2x-nonexisting-fb.html * igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1: - shard-skl: [PASS][63] -> [FAIL][64] ([i915#2122]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling: - shard-iclb: NOTRUN -> [SKIP][65] ([i915#2587]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt: - shard-glk: NOTRUN -> [SKIP][66] ([fdo#109271]) +8 similar issues [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-glk9/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-cpu: - shard-iclb: NOTRUN -> [SKIP][67] ([fdo#109280]) +16 similar issues [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt: - shard-tglb: NOTRUN -> [SKIP][68] ([fdo#109280] / [fdo#111825]) +5 similar issues [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html * igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence: - shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#533]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl6/igt@kms_pipe_crc_basic@read-crc-pipe-d-frame-sequence.html * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - shard-apl: NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265]) +1 similar issue [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl8/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html - shard-kbl: NOTRUN -> [FAIL][71] ([fdo#108145] / [i915#265]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-kbl: NOTRUN -> [FAIL][72] ([i915#265]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb: - shard-apl: NOTRUN -> [FAIL][73] ([i915#265]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html * igt@kms_plane_lowres@pipe-b-tiling-4: - shard-iclb: NOTRUN -> [SKIP][74] ([i915#5288]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_plane_lowres@pipe-b-tiling-4.html * igt@kms_plane_lowres@pipe-b-tiling-x: - shard-iclb: NOTRUN -> [SKIP][75] ([i915#3536]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_plane_lowres@pipe-b-tiling-x.html * igt@kms_plane_multiple@atomic-pipe-a-tiling-4: - shard-tglb: NOTRUN -> [SKIP][76] ([i915#5288]) +1 similar issue [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_plane_multiple@atomic-pipe-a-tiling-4.html * igt@kms_plane_multiple@atomic-pipe-d-tiling-x: - shard-kbl: NOTRUN -> [SKIP][77] ([fdo#109271]) +157 similar issues [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl3/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html * igt@kms_plane_scaling@downscale-with-rotation-factor-0-75@pipe-c-edp-1-downscale-with-rotation: - shard-iclb: NOTRUN -> [SKIP][78] ([i915#5176]) +2 similar issues [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@kms_plane_scaling@downscale-with-rotation-factor-0-75@pipe-c-edp-1-downscale-with-rotation.html * igt@kms_psr2_su@frontbuffer-xrgb8888: - shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#658]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl6/igt@kms_psr2_su@frontbuffer-xrgb8888.html * igt@kms_psr2_su@page_flip-p010: - shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#658]) [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl7/igt@kms_psr2_su@page_flip-p010.html * igt@kms_psr@psr2_basic: - shard-iclb: [PASS][81] -> [SKIP][82] ([fdo#109441]) +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-iclb2/igt@kms_psr@psr2_basic.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb7/igt@kms_psr@psr2_basic.html * igt@kms_psr@psr2_no_drrs: - shard-iclb: NOTRUN -> [SKIP][83] ([fdo#109441]) +1 similar issue [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb5/igt@kms_psr@psr2_no_drrs.html * igt@kms_psr@psr2_primary_blt: - shard-tglb: NOTRUN -> [FAIL][84] ([i915#132] / [i915#3467]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@kms_psr@psr2_primary_blt.html * igt@kms_vblank@pipe-d-wait-idle: - shard-kbl: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#533]) [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl3/igt@kms_vblank@pipe-d-wait-idle.html * igt@kms_writeback@writeback-pixel-formats: - shard-kbl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#2437]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl1/igt@kms_writeback@writeback-pixel-formats.html * igt@nouveau_crc@pipe-d-source-outp-complete: - shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109278] / [i915#2530]) +1 similar issue [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@nouveau_crc@pipe-d-source-outp-complete.html * igt@perf@polling-parameterized: - shard-glk: [PASS][88] -> [FAIL][89] ([i915#1542]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-glk6/igt@perf@polling-parameterized.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-glk2/igt@perf@polling-parameterized.html * igt@perf@polling-small-buf: - shard-skl: [PASS][90] -> [FAIL][91] ([i915#1722]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-skl1/igt@perf@polling-small-buf.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-skl10/igt@perf@polling-small-buf.html * igt@prime_nv_pcopy@test3_2: - shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109291]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@prime_nv_pcopy@test3_2.html * igt@prime_vgem@coherency-gtt: - shard-iclb: NOTRUN -> [SKIP][93] ([fdo#109292]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@prime_vgem@coherency-gtt.html * igt@sysfs_clients@pidname: - shard-iclb: NOTRUN -> [SKIP][94] ([i915#2994]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@sysfs_clients@pidname.html * igt@sysfs_clients@sema-25: - shard-glk: NOTRUN -> [SKIP][95] ([fdo#109271] / [i915#2994]) [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-glk9/igt@sysfs_clients@sema-25.html * igt@sysfs_clients@split-10: - shard-tglb: NOTRUN -> [SKIP][96] ([i915#2994]) [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@sysfs_clients@split-10.html - shard-apl: NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#2994]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl6/igt@sysfs_clients@split-10.html #### Possible fixes #### * igt@feature_discovery@psr2: - shard-iclb: [SKIP][98] ([i915#658]) -> [PASS][99] [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-iclb7/igt@feature_discovery@psr2.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb2/igt@feature_discovery@psr2.html * igt@gem_ctx_isolation@preservation-s3@rcs0: - shard-tglb: [INCOMPLETE][100] ([i915#1373]) -> [PASS][101] [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-tglb2/igt@gem_ctx_isolation@preservation-s3@rcs0.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglb3/igt@gem_ctx_isolation@preservation-s3@rcs0.html * igt@gem_ctx_persistence@smoketest: - shard-glk: [INCOMPLETE][102] -> [PASS][103] [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-glk5/igt@gem_ctx_persistence@smoketest.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-glk9/igt@gem_ctx_persistence@smoketest.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [FAIL][104] ([i915#2842]) -> [PASS][105] [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-iclb: [FAIL][106] ([i915#2842]) -> [PASS][107] +1 similar issue [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb4/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_whisper@basic-queues-priority: - shard-iclb: [INCOMPLETE][108] ([i915#1895]) -> [PASS][109] [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-iclb7/igt@gem_exec_whisper@basic-queues-priority.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb5/igt@gem_exec_whisper@basic-queues-priority.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][110] ([i915#180]) -> [PASS][111] +5 similar issues [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-apl7/igt@gem_workarounds@suspend-resume-context.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-apl2/igt@gem_workarounds@suspend-resume-context.html * igt@i915_pm_backlight@fade_with_suspend: - shard-skl: [DMESG-WARN][112] ([i915#1982]) -> [PASS][113] [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-skl7/igt@i915_pm_backlight@fade_with_suspend.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-skl6/igt@i915_pm_backlight@fade_with_suspend.html * igt@i915_selftest@live@execlists: - shard-skl: [INCOMPLETE][114] ([i915#5514]) -> [PASS][115] [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-skl8/igt@i915_selftest@live@execlists.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-skl7/igt@i915_selftest@live@execlists.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117] +6 similar issues [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-kbl1/igt@i915_suspend@sysfs-reader.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-kbl4/igt@i915_suspend@sysfs-reader.html * igt@kms_big_fb@x-tiled-32bpp-rotate-180: - {shard-tglu}: [DMESG-WARN][118] ([i915#402]) -> [PASS][119] [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-tglu-2/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-tglu-5/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html * igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen: - shard-glk: [DMESG-WARN][120] ([i915#118]) -> [PASS][121] +2 similar issues [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-glk2/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-glk6/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy: - shard-glk: [FAIL][122] ([i915#72]) -> [PASS][123] [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions: - shard-glk: [FAIL][124] ([i915#2346]) -> [PASS][125] [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1: - shard-skl: [FAIL][126] ([i915#79]) -> [PASS][127] [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [SKIP][128] ([fdo#109441]) -> [PASS][129] +1 similar issue [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-iclb7/igt@kms_psr@psr2_cursor_blt.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html #### Warnings #### * igt@gem_exec_balancer@parallel-keep-in-fence: - shard-iclb: [DMESG-WARN][130] ([i915#5076]) -> [SKIP][131] ([i915#4525]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/shard-iclb3/igt@gem_exec_balancer@parallel-keep-in-fence.html * igt@gem_exec_balancer@parallel-keep-submit-fence: - shard-iclb: [SKIP][132] ([i915#4525]) -> [DMESG-WARN][133] ([i915#5076]) +2 similar issues [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11446/shard-iclb5/igt@gem_exec_balancer@parallel-keep-submit-fence.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_227 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22771/index.html [-- Attachment #2: Type: text/html, Size: 33752 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev4) 2022-04-04 9:31 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva ` (3 preceding siblings ...) 2022-04-04 13:42 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2022-04-08 5:07 ` Patchwork 2022-04-08 5:42 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 5 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-04-08 5:07 UTC (permalink / raw) To: Mullati Siva; +Cc: intel-gfx == Series Details == Series: drm/i915/guc: Refactor CT access to use iosys_map (rev4) URL : https://patchwork.freedesktop.org/series/101148/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/guc: Refactor CT access to use iosys_map (rev4) 2022-04-04 9:31 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva ` (4 preceding siblings ...) 2022-04-08 5:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev4) Patchwork @ 2022-04-08 5:42 ` Patchwork 5 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-04-08 5:42 UTC (permalink / raw) To: Mullati Siva; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 12283 bytes --] == Series Details == Series: drm/i915/guc: Refactor CT access to use iosys_map (rev4) URL : https://patchwork.freedesktop.org/series/101148/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11473 -> Patchwork_22823 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_22823 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22823, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/index.html Participating hosts (46 -> 47) ------------------------------ Additional (4): bat-rpls-1 bat-rpls-2 fi-tgl-u2 fi-pnv-d510 Missing (3): fi-bsw-cyan fi-bwr-2160 fi-bdw-samus Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_22823: ### CI changes ### #### Possible regressions #### * boot: - fi-pnv-d510: NOTRUN -> [FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-pnv-d510/boot.html ### IGT changes ### #### Possible regressions #### * igt@gem_lmem_swapping@basic: - fi-tgl-u2: NOTRUN -> [FAIL][2] [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-tgl-u2/igt@gem_lmem_swapping@basic.html * igt@i915_pm_rpm@basic-rte: - fi-tgl-u2: NOTRUN -> [SKIP][3] +1 similar issue [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-tgl-u2/igt@i915_pm_rpm@basic-rte.html #### Warnings #### * igt@gem_lmem_swapping@basic: - fi-rkl-guc: [FAIL][4] ([i915#5602]) -> [FAIL][5] [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-rkl-guc/igt@gem_lmem_swapping@basic.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-rkl-guc/igt@gem_lmem_swapping@basic.html - fi-hsw-4770: [SKIP][6] ([fdo#109271]) -> [FAIL][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-hsw-4770/igt@gem_lmem_swapping@basic.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-hsw-4770/igt@gem_lmem_swapping@basic.html - fi-glk-j4005: [FAIL][8] ([i915#5602]) -> [FAIL][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-glk-j4005/igt@gem_lmem_swapping@basic.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-glk-j4005/igt@gem_lmem_swapping@basic.html * igt@runner@aborted: - fi-cfl-8109u: [FAIL][10] ([i915#4312]) -> [FAIL][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-cfl-8109u/igt@runner@aborted.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-cfl-8109u/igt@runner@aborted.html - fi-kbl-soraka: [FAIL][12] ([i915#4312]) -> [FAIL][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-kbl-soraka/igt@runner@aborted.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-kbl-soraka/igt@runner@aborted.html - fi-bxt-dsi: [FAIL][14] ([i915#4312]) -> [FAIL][15] [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-bxt-dsi/igt@runner@aborted.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-bxt-dsi/igt@runner@aborted.html - fi-kbl-x1275: [FAIL][16] ([i915#4312]) -> [FAIL][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-kbl-x1275/igt@runner@aborted.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-kbl-x1275/igt@runner@aborted.html - fi-kbl-8809g: [FAIL][18] ([i915#2722]) -> [FAIL][19] [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-kbl-8809g/igt@runner@aborted.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-kbl-8809g/igt@runner@aborted.html - fi-hsw-g3258: [FAIL][20] ([i915#4312]) -> [FAIL][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-hsw-g3258/igt@runner@aborted.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-hsw-g3258/igt@runner@aborted.html - fi-snb-2600: [FAIL][22] ([i915#4312]) -> [FAIL][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-snb-2600/igt@runner@aborted.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-snb-2600/igt@runner@aborted.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@gem_exec_basic@basic: - {bat-rpls-1}: NOTRUN -> [SKIP][24] +145 similar issues [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/bat-rpls-1/igt@gem_exec_basic@basic.html * igt@gem_lmem_swapping@basic: - {fi-tgl-dsi}: NOTRUN -> [SKIP][25] +2 similar issues [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-tgl-dsi/igt@gem_lmem_swapping@basic.html * igt@kms_chamelium@vga-hpd-fast: - {bat-adls-5}: NOTRUN -> [SKIP][26] +78 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/bat-adls-5/igt@kms_chamelium@vga-hpd-fast.html * igt@runner@aborted: - {bat-jsl-2}: [FAIL][27] ([i915#4312]) -> [FAIL][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/bat-jsl-2/igt@runner@aborted.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/bat-jsl-2/igt@runner@aborted.html Known issues ------------ Here are the changes found in Patchwork_22823 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_basic@create-close: - fi-ivb-3770: NOTRUN -> [SKIP][29] ([fdo#109271]) +146 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-ivb-3770/igt@gem_basic@create-close.html * igt@gem_close_race@basic-process: - fi-tgl-u2: NOTRUN -> [SKIP][30] ([fdo#109315] / [i915#2575]) +66 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-tgl-u2/igt@gem_close_race@basic-process.html * igt@gem_lmem_swapping@basic: - fi-skl-6700k2: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#5602]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-skl-6700k2/igt@gem_lmem_swapping@basic.html * igt@kms_addfb_basic@addfb25-yf-tiled-legacy: - fi-tgl-u2: NOTRUN -> [SKIP][32] ([fdo#111615] / [i915#2575]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-tgl-u2/igt@kms_addfb_basic@addfb25-yf-tiled-legacy.html * igt@kms_chamelium@hdmi-crc-fast: - fi-skl-6700k2: NOTRUN -> [SKIP][33] ([fdo#109271]) +145 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-skl-6700k2/igt@kms_chamelium@hdmi-crc-fast.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: - fi-ivb-3770: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#5341]) [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-ivb-3770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html - fi-skl-6700k2: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#5341]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-skl-6700k2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html - fi-tgl-u2: NOTRUN -> [SKIP][36] ([i915#2575] / [i915#5341]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-tgl-u2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: - fi-tgl-u2: NOTRUN -> [SKIP][37] ([i915#2575]) +75 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-tgl-u2/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html * igt@runner@aborted: - fi-tgl-u2: NOTRUN -> [FAIL][38] ([i915#3690] / [i915#4312]) [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-tgl-u2/igt@runner@aborted.html #### Warnings #### * igt@gem_lmem_swapping@basic: - fi-apl-guc: [SKIP][39] ([fdo#109271] / [i915#5602]) -> [SKIP][40] ([fdo#109271]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-apl-guc/igt@gem_lmem_swapping@basic.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-apl-guc/igt@gem_lmem_swapping@basic.html - fi-kbl-7500u: [FAIL][41] -> [FAIL][42] ([i915#5602]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-kbl-7500u/igt@gem_lmem_swapping@basic.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-kbl-7500u/igt@gem_lmem_swapping@basic.html * igt@runner@aborted: - fi-kbl-7500u: [FAIL][43] ([i915#4312] / [i915#5257]) -> [FAIL][44] ([i915#4312]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-kbl-7500u/igt@runner@aborted.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-kbl-7500u/igt@runner@aborted.html - bat-adlp-4: [FAIL][45] ([i915#4312]) -> [FAIL][46] ([i915#5457]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/bat-adlp-4/igt@runner@aborted.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/bat-adlp-4/igt@runner@aborted.html - fi-ivb-3770: [FAIL][47] -> [FAIL][48] ([i915#4312]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-ivb-3770/igt@runner@aborted.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-ivb-3770/igt@runner@aborted.html - fi-tgl-1115g4: [FAIL][49] ([i915#3690] / [i915#4312]) -> [FAIL][50] ([i915#4312] / [i915#5257]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-tgl-1115g4/igt@runner@aborted.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-tgl-1115g4/igt@runner@aborted.html - fi-skl-6700k2: [FAIL][51] -> [FAIL][52] ([i915#4312]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-skl-6700k2/igt@runner@aborted.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-skl-6700k2/igt@runner@aborted.html - fi-bsw-n3050: [FAIL][53] ([i915#4312]) -> [FAIL][54] ([i915#3690] / [i915#4312]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-bsw-n3050/igt@runner@aborted.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-bsw-n3050/igt@runner@aborted.html - fi-bsw-nick: [FAIL][55] ([i915#4312]) -> [FAIL][56] ([i915#3690] / [i915#4312]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11473/fi-bsw-nick/igt@runner@aborted.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/fi-bsw-nick/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#3690]: https://gitlab.freedesktop.org/drm/intel/issues/3690 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341 [i915#5457]: https://gitlab.freedesktop.org/drm/intel/issues/5457 [i915#5602]: https://gitlab.freedesktop.org/drm/intel/issues/5602 Build changes ------------- * Linux: CI_DRM_11473 -> Patchwork_22823 CI-20190529: 20190529 CI_DRM_11473: c6aee66322a45f20c89a1a26e214a70149635f02 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6415: c3b690bd5f7fb1fb7ed786ab0f3b815930a6a55f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22823: 47f1f65c4144f804b6d7cafad57181c297af9f8f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 47f1f65c4144 drm/i915/guc: Convert ct buffer to iosys_map == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22823/index.html [-- Attachment #2: Type: text/html, Size: 16106 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map @ 2022-05-09 6:49 Mullati Siva 2022-05-09 6:49 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva 0 siblings, 1 reply; 16+ messages in thread From: Mullati Siva @ 2022-05-09 6:49 UTC (permalink / raw) To: intel-gfx, siva.mullati; +Cc: lucas.demarchi From: Siva Mullati <siva.mullati@intel.com> ver2: remove newly added iosys map api from ver1 ver3: address review comments ver4: remove accessing vaddr This is continuation to the below patch series to use iosys map APIs, to use CT commands and descriptors. https://patchwork.freedesktop.org/series/99711/ Siva Mullati (1): drm/i915/guc: Convert ct buffer to iosys_map drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 195 +++++++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- 2 files changed, 122 insertions(+), 82 deletions(-) -- 2.33.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-05-09 6:49 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva @ 2022-05-09 6:49 ` Mullati Siva 2022-05-11 15:15 ` Balasubramani Vivekanandan 0 siblings, 1 reply; 16+ messages in thread From: Mullati Siva @ 2022-05-09 6:49 UTC (permalink / raw) To: intel-gfx, siva.mullati; +Cc: lucas.demarchi From: Siva Mullati <siva.mullati@intel.com> Convert CT commands and descriptors to use iosys_map rather than plain pointer and save it in the intel_guc_ct_buffer struct. This will help with ct_write and ct_read for cmd send and receive after the initialization by abstracting the IO vs system memory. Signed-off-by: Siva Mullati <siva.mullati@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 195 +++++++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- 2 files changed, 122 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index f01325cd1b62..bd5b4312d968 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) #define CT_PROBE_ERROR(_ct, _fmt, ...) \ i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) +#define ct_desc_read(desc_map_, field_) \ + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) +#define ct_desc_write(desc_map_, field_, val_) \ + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) + /** * DOC: CTB Blob * @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) +#define CTB_SEND_DESC_OFFSET 0u +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) + struct ct_request { struct list_head link; u32 fence; @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) init_waitqueue_head(&ct->wq); } -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) +static void guc_ct_buffer_desc_init(struct iosys_map *desc) { - memset(desc, 0, sizeof(*desc)); + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); } static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; atomic_set(&ctb->space, space); - guc_ct_buffer_desc_init(ctb->desc); + guc_ct_buffer_desc_init(&ctb->desc_map); } static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, - struct guc_ct_buffer_desc *desc, - u32 *cmds, u32 size_in_bytes, u32 resv_space) + struct iosys_map *desc, + struct iosys_map *cmds, + u32 size_in_bytes, u32 resv_space) { GEM_BUG_ON(size_in_bytes % 4); - ctb->desc = desc; - ctb->cmds = cmds; + ctb->desc_map = *desc; + ctb->cmds_map = *cmds; ctb->size = size_in_bytes / 4; ctb->resv_space = resv_space / 4; @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, int intel_guc_ct_init(struct intel_guc_ct *ct) { struct intel_guc *guc = ct_to_guc(ct); - struct guc_ct_buffer_desc *desc; + struct iosys_map blob_map; + struct iosys_map desc_map; + struct iosys_map cmds_map; u32 blob_size; u32 cmds_size; u32 resv_space; void *blob; - u32 *cmds; int err; err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); - /* store pointers to desc and cmds for send ctb */ - desc = blob; - cmds = blob + 2 * CTB_DESC_SIZE; + if (i915_gem_object_is_lmem(ct->vma->obj)) + iosys_map_set_vaddr_iomem(&blob_map, + (void __iomem *)blob); + else + iosys_map_set_vaddr(&blob_map, blob); + + /* store sysmap to desc_map and cmds_map for send ctb */ + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); cmds_size = CTB_H2G_BUFFER_SIZE; resv_space = 0; - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, - resv_space); + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, + cmds_size, resv_space); - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); + guc_ct_buffer_init(&ct->ctbs.send, + &desc_map, &cmds_map, cmds_size, resv_space); - /* store pointers to desc and cmds for recv ctb */ - desc = blob + CTB_DESC_SIZE; - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; + /* store sysmap to desc_map and cmds_map for recv ctb */ + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); cmds_size = CTB_G2H_BUFFER_SIZE; resv_space = G2H_ROOM_BUFFER_SIZE; - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, - resv_space); + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, + cmds_size, resv_space); - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); + guc_ct_buffer_init(&ct->ctbs.recv, + &desc_map, &cmds_map, cmds_size, resv_space); return 0; } @@ -291,8 +311,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) int intel_guc_ct_enable(struct intel_guc_ct *ct) { struct intel_guc *guc = ct_to_guc(ct); + struct iosys_map blob_map; u32 base, desc, cmds, size; - void *blob; int err; GEM_BUG_ON(ct->enabled); @@ -302,9 +322,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); base = intel_guc_ggtt_offset(guc, ct->vma); + if (i915_gem_object_is_lmem(ct->vma->obj)) + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) + __px_vaddr(ct->vma->obj)); + else + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); + /* blob should start with send descriptor */ - blob = __px_vaddr(ct->vma->obj); - GEM_BUG_ON(blob != ct->ctbs.send.desc); + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); /* (re)initialize descriptors */ guc_ct_buffer_reset(&ct->ctbs.send); @@ -314,15 +339,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) * Register both CT buffers starting with RECV buffer. * Descriptors are in first half of the blob. */ - desc = base + ptrdiff(ct->ctbs.recv.desc, blob); - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); + desc = base + CTB_RECV_DESC_OFFSET; + cmds = base + CTB_RECV_CMDS_OFFSET; size = ct->ctbs.recv.size * 4; err = ct_register_buffer(ct, false, desc, cmds, size); if (unlikely(err)) goto err_out; - desc = base + ptrdiff(ct->ctbs.send.desc, blob); - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); + desc = base + CTB_SEND_DESC_OFFSET; + cmds = base + CTB_SEND_CMDS_OFFSET; size = ct->ctbs.send.size * 4; err = ct_register_buffer(ct, true, desc, cmds, size); if (unlikely(err)) @@ -371,31 +396,33 @@ static int ct_write(struct intel_guc_ct *ct, u32 fence, u32 flags) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 tail = ctb->tail; u32 size = ctb->size; u32 header; u32 hxg; u32 type; - u32 *cmds = ctb->cmds; + u32 status = ct_desc_read(&ctb->desc_map, status); + u32 desc_head = ct_desc_read(&ctb->desc_map, head); unsigned int i; - if (unlikely(desc->status)) + if (unlikely(status)) goto corrupted; GEM_BUG_ON(tail > size); #ifdef CONFIG_DRM_I915_DEBUG_GUC - if (unlikely(tail != READ_ONCE(desc->tail))) { + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { CT_ERROR(ct, "Tail was modified %u != %u\n", - desc->tail, tail); - desc->status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_read(&ctb->desc_map, tail), tail); + status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } - if (unlikely(READ_ONCE(desc->head) >= size)) { + if (unlikely(desc_head >= size)) { CT_ERROR(ct, "Invalid head offset %u >= %u)\n", - desc->head, size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + desc_head, size); + status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } #endif @@ -418,14 +445,15 @@ static int ct_write(struct intel_guc_ct *ct, CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); - cmds[tail] = header; + iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, header); tail = (tail + 1) % size; - cmds[tail] = hxg; + iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, hxg); tail = (tail + 1) % size; for (i = 1; i < len; i++) { - cmds[tail] = action[i]; + iosys_map_wr(&ctb->cmds_map, + sizeof(u32) * tail, u32, action[i]); tail = (tail + 1) % size; } GEM_BUG_ON(tail > size); @@ -442,13 +470,13 @@ static int ct_write(struct intel_guc_ct *ct, atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); /* now update descriptor */ - WRITE_ONCE(desc->tail, tail); + ct_desc_write(&ctb->desc_map, tail, tail); return 0; corrupted: CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", - desc->head, desc->tail, desc->status); + desc_head, ct_desc_read(&ctb->desc_map, tail), status); ctb->broken = true; return -EPIPE; } @@ -499,20 +527,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; if (unlikely(ret)) { - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; - CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", ktime_ms_delta(ktime_get(), ct->stall_time), - send->status, recv->status); + ct_desc_read(&ct->ctbs.send.desc_map, status), + ct_desc_read(&ct->ctbs.recv.desc_map, status)); CT_ERROR(ct, "H2G Space: %u (Bytes)\n", atomic_read(&ct->ctbs.send.space) * 4); - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); + CT_ERROR(ct, "Head: %u (Dwords)\n", + ct_desc_read(&ct->ctbs.send.desc_map, head)); + CT_ERROR(ct, "Tail: %u (Dwords)\n", + ct_desc_read(&ct->ctbs.send.desc_map, tail)); CT_ERROR(ct, "G2H Space: %u (Bytes)\n", atomic_read(&ct->ctbs.recv.space) * 4); - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); + CT_ERROR(ct, "Head: %u\n (Dwords)", + ct_desc_read(&ct->ctbs.recv.desc_map, head)); + CT_ERROR(ct, "Tail: %u\n (Dwords)", + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); ct->ctbs.send.broken = true; } @@ -549,18 +579,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 head; u32 space; + u32 status = ct_desc_read(&ctb->desc_map, status); if (atomic_read(&ctb->space) >= len_dw) return true; - head = READ_ONCE(desc->head); + head = ct_desc_read(&ctb->desc_map, head); if (unlikely(head > ctb->size)) { CT_ERROR(ct, "Invalid head offset %u >= %u)\n", head, ctb->size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); ctb->broken = true; return false; } @@ -803,11 +834,11 @@ static void ct_free_msg(struct ct_incoming_msg *msg) static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 head = ctb->head; - u32 tail = READ_ONCE(desc->tail); + u32 tail = ct_desc_read(&ctb->desc_map, tail); u32 size = ctb->size; - u32 *cmds = ctb->cmds; + u32 status = ct_desc_read(&ctb->desc_map, status); + u32 desc_head = ct_desc_read(&ctb->desc_map, head); s32 available; unsigned int len; unsigned int i; @@ -816,23 +847,25 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (unlikely(ctb->broken)) return -EPIPE; - if (unlikely(desc->status)) + if (unlikely(status)) goto corrupted; GEM_BUG_ON(head > size); #ifdef CONFIG_DRM_I915_DEBUG_GUC - if (unlikely(head != READ_ONCE(desc->head))) { + if (unlikely(head != desc_head)) { CT_ERROR(ct, "Head was modified %u != %u\n", - desc->head, head); - desc->status |= GUC_CTB_STATUS_MISMATCH; + desc_head, head); + status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } #endif if (unlikely(tail >= size)) { CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", tail, size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } @@ -849,7 +882,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); GEM_BUG_ON(available < 0); - header = cmds[head]; + header = iosys_map_rd(&ctb->cmds_map, sizeof(u32) * head, u32); head = (head + 1) % size; /* message len with header */ @@ -857,11 +890,14 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (unlikely(len > (u32)available)) { CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", 4, &header, + 4 * (head + available - 1 > size ? size - head : + available - 1), ((__px_vaddr(ct->vma->obj) + + CTB_RECV_CMDS_OFFSET) + (4 * head)), 4 * (head + available - 1 > size ? - size - head : available - 1), &cmds[head], - 4 * (head + available - 1 > size ? - available - 1 - size + head : 0), &cmds[0]); - desc->status |= GUC_CTB_STATUS_UNDERFLOW; + available - 1 - size + head : 0), + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); + status |= GUC_CTB_STATUS_UNDERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } @@ -869,17 +905,20 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (!*msg) { CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", 4, &header, + 4 * (head + available - 1 > size ? size - head : + available - 1), ((__px_vaddr(ct->vma->obj) + + CTB_RECV_CMDS_OFFSET) + (4 * head)), 4 * (head + available - 1 > size ? - size - head : available - 1), &cmds[head], - 4 * (head + available - 1 > size ? - available - 1 - size + head : 0), &cmds[0]); + available - 1 - size + head : 0), + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); return available; } (*msg)->msg[0] = header; for (i = 1; i < len; i++) { - (*msg)->msg[i] = cmds[head]; + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, + sizeof(u32) * head, u32); head = (head + 1) % size; } CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); @@ -888,13 +927,13 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) ctb->head = head; /* now update descriptor */ - WRITE_ONCE(desc->head, head); + ct_desc_write(&ctb->desc_map, head, head); return available - len; corrupted: CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", - desc->head, desc->tail, desc->status); + desc_head, ct_desc_read(&ctb->desc_map, tail), status); ctb->broken = true; return -EPIPE; } @@ -1211,13 +1250,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, drm_printf(p, "H2G Space: %u\n", atomic_read(&ct->ctbs.send.space) * 4); drm_printf(p, "Head: %u\n", - ct->ctbs.send.desc->head); + ct_desc_read(&ct->ctbs.send.desc_map, head)); drm_printf(p, "Tail: %u\n", - ct->ctbs.send.desc->tail); + ct_desc_read(&ct->ctbs.send.desc_map, tail)); drm_printf(p, "G2H Space: %u\n", atomic_read(&ct->ctbs.recv.space) * 4); drm_printf(p, "Head: %u\n", - ct->ctbs.recv.desc->head); + ct_desc_read(&ct->ctbs.recv.desc_map, head)); drm_printf(p, "Tail: %u\n", - ct->ctbs.recv.desc->tail); + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h index f709a19c7e21..867fe13fb47d 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h @@ -7,6 +7,7 @@ #define _INTEL_GUC_CT_H_ #include <linux/interrupt.h> +#include <linux/iosys-map.h> #include <linux/spinlock.h> #include <linux/workqueue.h> #include <linux/ktime.h> @@ -32,8 +33,8 @@ struct drm_printer; * holds the commands. * * @lock: protects access to the commands buffer and buffer descriptor - * @desc: pointer to the buffer descriptor - * @cmds: pointer to the commands buffer + * @desc: iosys map to the buffer descriptor + * @cmds: iosys map to the commands buffer * @size: size of the commands buffer in dwords * @resv_space: reserved space in buffer in dwords * @head: local shadow copy of head in dwords @@ -43,8 +44,8 @@ struct drm_printer; */ struct intel_guc_ct_buffer { spinlock_t lock; - struct guc_ct_buffer_desc *desc; - u32 *cmds; + struct iosys_map desc_map; + struct iosys_map cmds_map; u32 size; u32 resv_space; u32 tail; -- 2.33.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-05-09 6:49 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva @ 2022-05-11 15:15 ` Balasubramani Vivekanandan 0 siblings, 0 replies; 16+ messages in thread From: Balasubramani Vivekanandan @ 2022-05-11 15:15 UTC (permalink / raw) To: Mullati Siva, intel-gfx; +Cc: lucas.demarchi On 09.05.2022 12:19, Mullati Siva wrote: > From: Siva Mullati <siva.mullati@intel.com> > > Convert CT commands and descriptors to use iosys_map rather > than plain pointer and save it in the intel_guc_ct_buffer struct. > This will help with ct_write and ct_read for cmd send and receive > after the initialization by abstracting the IO vs system memory. > > Signed-off-by: Siva Mullati <siva.mullati@intel.com> Acked-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 195 +++++++++++++--------- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- > 2 files changed, 122 insertions(+), 82 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > index f01325cd1b62..bd5b4312d968 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c > @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > #define CT_PROBE_ERROR(_ct, _fmt, ...) \ > i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) > > +#define ct_desc_read(desc_map_, field_) \ > + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) > +#define ct_desc_write(desc_map_, field_, val_) \ > + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) > + > /** > * DOC: CTB Blob > * > @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) > #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) > > +#define CTB_SEND_DESC_OFFSET 0u > +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) > +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) > +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) > + > struct ct_request { > struct list_head link; > u32 fence; > @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) > init_waitqueue_head(&ct->wq); > } > > -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) > +static void guc_ct_buffer_desc_init(struct iosys_map *desc) > { > - memset(desc, 0, sizeof(*desc)); > + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); > } > > static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) > @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) > space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; > atomic_set(&ctb->space, space); > > - guc_ct_buffer_desc_init(ctb->desc); > + guc_ct_buffer_desc_init(&ctb->desc_map); > } > > static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, > - struct guc_ct_buffer_desc *desc, > - u32 *cmds, u32 size_in_bytes, u32 resv_space) > + struct iosys_map *desc, > + struct iosys_map *cmds, > + u32 size_in_bytes, u32 resv_space) > { > GEM_BUG_ON(size_in_bytes % 4); > > - ctb->desc = desc; > - ctb->cmds = cmds; > + ctb->desc_map = *desc; > + ctb->cmds_map = *cmds; > ctb->size = size_in_bytes / 4; > ctb->resv_space = resv_space / 4; > > @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, > int intel_guc_ct_init(struct intel_guc_ct *ct) > { > struct intel_guc *guc = ct_to_guc(ct); > - struct guc_ct_buffer_desc *desc; > + struct iosys_map blob_map; > + struct iosys_map desc_map; > + struct iosys_map cmds_map; > u32 blob_size; > u32 cmds_size; > u32 resv_space; > void *blob; > - u32 *cmds; > int err; > > err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); > @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) > > CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); > > - /* store pointers to desc and cmds for send ctb */ > - desc = blob; > - cmds = blob + 2 * CTB_DESC_SIZE; > + if (i915_gem_object_is_lmem(ct->vma->obj)) > + iosys_map_set_vaddr_iomem(&blob_map, > + (void __iomem *)blob); > + else > + iosys_map_set_vaddr(&blob_map, blob); > + > + /* store sysmap to desc_map and cmds_map for send ctb */ > + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); > + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); > cmds_size = CTB_H2G_BUFFER_SIZE; > resv_space = 0; > - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", > - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, > - resv_space); > + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", > + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, > + cmds_size, resv_space); > > - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); > + guc_ct_buffer_init(&ct->ctbs.send, > + &desc_map, &cmds_map, cmds_size, resv_space); > > - /* store pointers to desc and cmds for recv ctb */ > - desc = blob + CTB_DESC_SIZE; > - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; > + /* store sysmap to desc_map and cmds_map for recv ctb */ > + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); > + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); > cmds_size = CTB_G2H_BUFFER_SIZE; > resv_space = G2H_ROOM_BUFFER_SIZE; > - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", > - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, > - resv_space); > + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", > + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, > + cmds_size, resv_space); > > - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); > + guc_ct_buffer_init(&ct->ctbs.recv, > + &desc_map, &cmds_map, cmds_size, resv_space); > > return 0; > } > @@ -291,8 +311,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) > int intel_guc_ct_enable(struct intel_guc_ct *ct) > { > struct intel_guc *guc = ct_to_guc(ct); > + struct iosys_map blob_map; > u32 base, desc, cmds, size; > - void *blob; > int err; > > GEM_BUG_ON(ct->enabled); > @@ -302,9 +322,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); > base = intel_guc_ggtt_offset(guc, ct->vma); > > + if (i915_gem_object_is_lmem(ct->vma->obj)) > + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) > + __px_vaddr(ct->vma->obj)); > + else > + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); > + > /* blob should start with send descriptor */ > - blob = __px_vaddr(ct->vma->obj); > - GEM_BUG_ON(blob != ct->ctbs.send.desc); > + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); > > /* (re)initialize descriptors */ > guc_ct_buffer_reset(&ct->ctbs.send); > @@ -314,15 +339,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > * Register both CT buffers starting with RECV buffer. > * Descriptors are in first half of the blob. > */ > - desc = base + ptrdiff(ct->ctbs.recv.desc, blob); > - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); > + desc = base + CTB_RECV_DESC_OFFSET; > + cmds = base + CTB_RECV_CMDS_OFFSET; > size = ct->ctbs.recv.size * 4; > err = ct_register_buffer(ct, false, desc, cmds, size); > if (unlikely(err)) > goto err_out; > > - desc = base + ptrdiff(ct->ctbs.send.desc, blob); > - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); > + desc = base + CTB_SEND_DESC_OFFSET; > + cmds = base + CTB_SEND_CMDS_OFFSET; > size = ct->ctbs.send.size * 4; > err = ct_register_buffer(ct, true, desc, cmds, size); > if (unlikely(err)) > @@ -371,31 +396,33 @@ static int ct_write(struct intel_guc_ct *ct, > u32 fence, u32 flags) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; > - struct guc_ct_buffer_desc *desc = ctb->desc; > u32 tail = ctb->tail; > u32 size = ctb->size; > u32 header; > u32 hxg; > u32 type; > - u32 *cmds = ctb->cmds; > + u32 status = ct_desc_read(&ctb->desc_map, status); > + u32 desc_head = ct_desc_read(&ctb->desc_map, head); > unsigned int i; > > - if (unlikely(desc->status)) > + if (unlikely(status)) > goto corrupted; > > GEM_BUG_ON(tail > size); > > #ifdef CONFIG_DRM_I915_DEBUG_GUC > - if (unlikely(tail != READ_ONCE(desc->tail))) { > + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { > CT_ERROR(ct, "Tail was modified %u != %u\n", > - desc->tail, tail); > - desc->status |= GUC_CTB_STATUS_MISMATCH; > + ct_desc_read(&ctb->desc_map, tail), tail); > + status |= GUC_CTB_STATUS_MISMATCH; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > - if (unlikely(READ_ONCE(desc->head) >= size)) { > + if (unlikely(desc_head >= size)) { > CT_ERROR(ct, "Invalid head offset %u >= %u)\n", > - desc->head, size); > - desc->status |= GUC_CTB_STATUS_OVERFLOW; > + desc_head, size); > + status |= GUC_CTB_STATUS_OVERFLOW; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > #endif > @@ -418,14 +445,15 @@ static int ct_write(struct intel_guc_ct *ct, > CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", > tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); > > - cmds[tail] = header; > + iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, header); > tail = (tail + 1) % size; > > - cmds[tail] = hxg; > + iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, hxg); > tail = (tail + 1) % size; > > for (i = 1; i < len; i++) { > - cmds[tail] = action[i]; > + iosys_map_wr(&ctb->cmds_map, > + sizeof(u32) * tail, u32, action[i]); > tail = (tail + 1) % size; > } > GEM_BUG_ON(tail > size); > @@ -442,13 +470,13 @@ static int ct_write(struct intel_guc_ct *ct, > atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); > > /* now update descriptor */ > - WRITE_ONCE(desc->tail, tail); > + ct_desc_write(&ctb->desc_map, tail, tail); > > return 0; > > corrupted: > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", > - desc->head, desc->tail, desc->status); > + desc_head, ct_desc_read(&ctb->desc_map, tail), status); > ctb->broken = true; > return -EPIPE; > } > @@ -499,20 +527,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) > bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; > > if (unlikely(ret)) { > - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; > - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; > - > CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", > ktime_ms_delta(ktime_get(), ct->stall_time), > - send->status, recv->status); > + ct_desc_read(&ct->ctbs.send.desc_map, status), > + ct_desc_read(&ct->ctbs.recv.desc_map, status)); > CT_ERROR(ct, "H2G Space: %u (Bytes)\n", > atomic_read(&ct->ctbs.send.space) * 4); > - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); > - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); > + CT_ERROR(ct, "Head: %u (Dwords)\n", > + ct_desc_read(&ct->ctbs.send.desc_map, head)); > + CT_ERROR(ct, "Tail: %u (Dwords)\n", > + ct_desc_read(&ct->ctbs.send.desc_map, tail)); > CT_ERROR(ct, "G2H Space: %u (Bytes)\n", > atomic_read(&ct->ctbs.recv.space) * 4); > - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); > - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); > + CT_ERROR(ct, "Head: %u\n (Dwords)", > + ct_desc_read(&ct->ctbs.recv.desc_map, head)); > + CT_ERROR(ct, "Tail: %u\n (Dwords)", > + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > > ct->ctbs.send.broken = true; > } > @@ -549,18 +579,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) > static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; > - struct guc_ct_buffer_desc *desc = ctb->desc; > u32 head; > u32 space; > + u32 status = ct_desc_read(&ctb->desc_map, status); > > if (atomic_read(&ctb->space) >= len_dw) > return true; > > - head = READ_ONCE(desc->head); > + head = ct_desc_read(&ctb->desc_map, head); > if (unlikely(head > ctb->size)) { > CT_ERROR(ct, "Invalid head offset %u >= %u)\n", > head, ctb->size); > - desc->status |= GUC_CTB_STATUS_OVERFLOW; > + status |= GUC_CTB_STATUS_OVERFLOW; > + ct_desc_write(&ctb->desc_map, status, status); > ctb->broken = true; > return false; > } > @@ -803,11 +834,11 @@ static void ct_free_msg(struct ct_incoming_msg *msg) > static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; > - struct guc_ct_buffer_desc *desc = ctb->desc; > u32 head = ctb->head; > - u32 tail = READ_ONCE(desc->tail); > + u32 tail = ct_desc_read(&ctb->desc_map, tail); > u32 size = ctb->size; > - u32 *cmds = ctb->cmds; > + u32 status = ct_desc_read(&ctb->desc_map, status); > + u32 desc_head = ct_desc_read(&ctb->desc_map, head); > s32 available; > unsigned int len; > unsigned int i; > @@ -816,23 +847,25 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (unlikely(ctb->broken)) > return -EPIPE; > > - if (unlikely(desc->status)) > + if (unlikely(status)) > goto corrupted; > > GEM_BUG_ON(head > size); > > #ifdef CONFIG_DRM_I915_DEBUG_GUC > - if (unlikely(head != READ_ONCE(desc->head))) { > + if (unlikely(head != desc_head)) { > CT_ERROR(ct, "Head was modified %u != %u\n", > - desc->head, head); > - desc->status |= GUC_CTB_STATUS_MISMATCH; > + desc_head, head); > + status |= GUC_CTB_STATUS_MISMATCH; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > #endif > if (unlikely(tail >= size)) { > CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", > tail, size); > - desc->status |= GUC_CTB_STATUS_OVERFLOW; > + status |= GUC_CTB_STATUS_OVERFLOW; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > > @@ -849,7 +882,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); > GEM_BUG_ON(available < 0); > > - header = cmds[head]; > + header = iosys_map_rd(&ctb->cmds_map, sizeof(u32) * head, u32); > head = (head + 1) % size; > > /* message len with header */ > @@ -857,11 +890,14 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (unlikely(len > (u32)available)) { > CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", > 4, &header, > + 4 * (head + available - 1 > size ? size - head : > + available - 1), ((__px_vaddr(ct->vma->obj) + > + CTB_RECV_CMDS_OFFSET) + (4 * head)), > 4 * (head + available - 1 > size ? > - size - head : available - 1), &cmds[head], > - 4 * (head + available - 1 > size ? > - available - 1 - size + head : 0), &cmds[0]); > - desc->status |= GUC_CTB_STATUS_UNDERFLOW; > + available - 1 - size + head : 0), > + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); > + status |= GUC_CTB_STATUS_UNDERFLOW; > + ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > > @@ -869,17 +905,20 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (!*msg) { > CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", > 4, &header, > + 4 * (head + available - 1 > size ? size - head : > + available - 1), ((__px_vaddr(ct->vma->obj) + > + CTB_RECV_CMDS_OFFSET) + (4 * head)), > 4 * (head + available - 1 > size ? > - size - head : available - 1), &cmds[head], > - 4 * (head + available - 1 > size ? > - available - 1 - size + head : 0), &cmds[0]); > + available - 1 - size + head : 0), > + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); > return available; > } > > (*msg)->msg[0] = header; > > for (i = 1; i < len; i++) { > - (*msg)->msg[i] = cmds[head]; > + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, > + sizeof(u32) * head, u32); > head = (head + 1) % size; > } > CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); > @@ -888,13 +927,13 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > ctb->head = head; > > /* now update descriptor */ > - WRITE_ONCE(desc->head, head); > + ct_desc_write(&ctb->desc_map, head, head); > > return available - len; > > corrupted: > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", > - desc->head, desc->tail, desc->status); > + desc_head, ct_desc_read(&ctb->desc_map, tail), status); > ctb->broken = true; > return -EPIPE; > } > @@ -1211,13 +1250,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, > drm_printf(p, "H2G Space: %u\n", > atomic_read(&ct->ctbs.send.space) * 4); > drm_printf(p, "Head: %u\n", > - ct->ctbs.send.desc->head); > + ct_desc_read(&ct->ctbs.send.desc_map, head)); > drm_printf(p, "Tail: %u\n", > - ct->ctbs.send.desc->tail); > + ct_desc_read(&ct->ctbs.send.desc_map, tail)); > drm_printf(p, "G2H Space: %u\n", > atomic_read(&ct->ctbs.recv.space) * 4); > drm_printf(p, "Head: %u\n", > - ct->ctbs.recv.desc->head); > + ct_desc_read(&ct->ctbs.recv.desc_map, head)); > drm_printf(p, "Tail: %u\n", > - ct->ctbs.recv.desc->tail); > + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > } > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > index f709a19c7e21..867fe13fb47d 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h > @@ -7,6 +7,7 @@ > #define _INTEL_GUC_CT_H_ > > #include <linux/interrupt.h> > +#include <linux/iosys-map.h> > #include <linux/spinlock.h> > #include <linux/workqueue.h> > #include <linux/ktime.h> > @@ -32,8 +33,8 @@ struct drm_printer; > * holds the commands. > * > * @lock: protects access to the commands buffer and buffer descriptor > - * @desc: pointer to the buffer descriptor > - * @cmds: pointer to the commands buffer > + * @desc: iosys map to the buffer descriptor > + * @cmds: iosys map to the commands buffer > * @size: size of the commands buffer in dwords > * @resv_space: reserved space in buffer in dwords > * @head: local shadow copy of head in dwords > @@ -43,8 +44,8 @@ struct drm_printer; > */ > struct intel_guc_ct_buffer { > spinlock_t lock; > - struct guc_ct_buffer_desc *desc; > - u32 *cmds; > + struct iosys_map desc_map; > + struct iosys_map cmds_map; > u32 size; > u32 resv_space; > u32 tail; > -- > 2.33.0 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 0/1] Refactor CT access to use iosys_map @ 2022-04-21 17:26 Mullati Siva 2022-04-21 17:26 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva 0 siblings, 1 reply; 16+ messages in thread From: Mullati Siva @ 2022-04-21 17:26 UTC (permalink / raw) To: intel-gfx, siva.mullati; +Cc: lucas.demarchi From: Siva Mullati <siva.mullati@intel.com> ver2: remove newly added iosys map api from ver1 ver3: address review comments ver4: remove accessing vaddr This is continuation to the below patch series to use iosys map APIs, to use CT commands and descriptors. https://patchwork.freedesktop.org/series/99711/ Siva Mullati (1): drm/i915/guc: Convert ct buffer to iosys_map drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 197 +++++++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- 2 files changed, 124 insertions(+), 82 deletions(-) -- 2.33.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-04-21 17:26 [Intel-gfx] [PATCH 0/1] Refactor CT access to use iosys_map Mullati Siva @ 2022-04-21 17:26 ` Mullati Siva 0 siblings, 0 replies; 16+ messages in thread From: Mullati Siva @ 2022-04-21 17:26 UTC (permalink / raw) To: intel-gfx, siva.mullati; +Cc: lucas.demarchi From: Siva Mullati <siva.mullati@intel.com> Convert CT commands and descriptors to use iosys_map rather than plain pointer and save it in the intel_guc_ct_buffer struct. This will help with ct_write and ct_read for cmd send and receive after the initialization by abstracting the IO vs system memory. Signed-off-by: Siva Mullati <siva.mullati@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 197 +++++++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- 2 files changed, 124 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index f01325cd1b62..5bd03d3112f7 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) #define CT_PROBE_ERROR(_ct, _fmt, ...) \ i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) +#define ct_desc_read(desc_map_, field_) \ + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) +#define ct_desc_write(desc_map_, field_, val_) \ + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) + /** * DOC: CTB Blob * @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) +#define CTB_SEND_DESC_OFFSET 0u +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) + struct ct_request { struct list_head link; u32 fence; @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) init_waitqueue_head(&ct->wq); } -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) +static void guc_ct_buffer_desc_init(struct iosys_map *desc) { - memset(desc, 0, sizeof(*desc)); + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); } static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; atomic_set(&ctb->space, space); - guc_ct_buffer_desc_init(ctb->desc); + guc_ct_buffer_desc_init(&ctb->desc_map); } static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, - struct guc_ct_buffer_desc *desc, - u32 *cmds, u32 size_in_bytes, u32 resv_space) + struct iosys_map *desc, + struct iosys_map *cmds, + u32 size_in_bytes, u32 resv_space) { GEM_BUG_ON(size_in_bytes % 4); - ctb->desc = desc; - ctb->cmds = cmds; + ctb->desc_map = *desc; + ctb->cmds_map = *cmds; ctb->size = size_in_bytes / 4; ctb->resv_space = resv_space / 4; @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, int intel_guc_ct_init(struct intel_guc_ct *ct) { struct intel_guc *guc = ct_to_guc(ct); - struct guc_ct_buffer_desc *desc; + struct iosys_map blob_map; + struct iosys_map desc_map; + struct iosys_map cmds_map; u32 blob_size; u32 cmds_size; u32 resv_space; void *blob; - u32 *cmds; int err; err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); - /* store pointers to desc and cmds for send ctb */ - desc = blob; - cmds = blob + 2 * CTB_DESC_SIZE; + if (i915_gem_object_is_lmem(ct->vma->obj)) + iosys_map_set_vaddr_iomem(&blob_map, + (void __iomem *)blob); + else + iosys_map_set_vaddr(&blob_map, blob); + + /* store sysmap to desc_map and cmds_map for send ctb */ + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); cmds_size = CTB_H2G_BUFFER_SIZE; resv_space = 0; - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, - resv_space); + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", + CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, + cmds_size, resv_space); - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); + guc_ct_buffer_init(&ct->ctbs.send, + &desc_map, &cmds_map, cmds_size, resv_space); - /* store pointers to desc and cmds for recv ctb */ - desc = blob + CTB_DESC_SIZE; - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; + /* store sysmap to desc_map and cmds_map for recv ctb */ + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); cmds_size = CTB_G2H_BUFFER_SIZE; resv_space = G2H_ROOM_BUFFER_SIZE; - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, - resv_space); + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, + cmds_size, resv_space); - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); + guc_ct_buffer_init(&ct->ctbs.recv, + &desc_map, &cmds_map, cmds_size, resv_space); return 0; } @@ -291,8 +311,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) int intel_guc_ct_enable(struct intel_guc_ct *ct) { struct intel_guc *guc = ct_to_guc(ct); + struct iosys_map blob_map; u32 base, desc, cmds, size; - void *blob; int err; GEM_BUG_ON(ct->enabled); @@ -302,9 +322,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); base = intel_guc_ggtt_offset(guc, ct->vma); + if (i915_gem_object_is_lmem(ct->vma->obj)) + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) + __px_vaddr(ct->vma->obj)); + else + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); + /* blob should start with send descriptor */ - blob = __px_vaddr(ct->vma->obj); - GEM_BUG_ON(blob != ct->ctbs.send.desc); + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); /* (re)initialize descriptors */ guc_ct_buffer_reset(&ct->ctbs.send); @@ -314,15 +339,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) * Register both CT buffers starting with RECV buffer. * Descriptors are in first half of the blob. */ - desc = base + ptrdiff(ct->ctbs.recv.desc, blob); - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); + desc = base + CTB_RECV_DESC_OFFSET; + cmds = base + CTB_RECV_CMDS_OFFSET; size = ct->ctbs.recv.size * 4; err = ct_register_buffer(ct, false, desc, cmds, size); if (unlikely(err)) goto err_out; - desc = base + ptrdiff(ct->ctbs.send.desc, blob); - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); + desc = base + CTB_SEND_DESC_OFFSET; + cmds = base + CTB_SEND_CMDS_OFFSET; size = ct->ctbs.send.size * 4; err = ct_register_buffer(ct, true, desc, cmds, size); if (unlikely(err)) @@ -371,31 +396,32 @@ static int ct_write(struct intel_guc_ct *ct, u32 fence, u32 flags) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 tail = ctb->tail; u32 size = ctb->size; u32 header; u32 hxg; u32 type; - u32 *cmds = ctb->cmds; + u32 status = ct_desc_read(&ctb->desc_map, status); unsigned int i; - if (unlikely(desc->status)) + if (unlikely(status)) goto corrupted; GEM_BUG_ON(tail > size); #ifdef CONFIG_DRM_I915_DEBUG_GUC - if (unlikely(tail != READ_ONCE(desc->tail))) { + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { CT_ERROR(ct, "Tail was modified %u != %u\n", - desc->tail, tail); - desc->status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_read(&ctb->desc_map, tail), tail); + status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } - if (unlikely(READ_ONCE(desc->head) >= size)) { + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) { CT_ERROR(ct, "Invalid head offset %u >= %u)\n", - desc->head, size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_read(&ctb->desc_map, head), size); + status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } #endif @@ -418,14 +444,15 @@ static int ct_write(struct intel_guc_ct *ct, CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); - cmds[tail] = header; + iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, header); tail = (tail + 1) % size; - cmds[tail] = hxg; + iosys_map_wr(&ctb->cmds_map, sizeof(u32) * tail, u32, hxg); tail = (tail + 1) % size; for (i = 1; i < len; i++) { - cmds[tail] = action[i]; + iosys_map_wr(&ctb->cmds_map, + sizeof(u32) * tail, u32, action[i]); tail = (tail + 1) % size; } GEM_BUG_ON(tail > size); @@ -442,13 +469,14 @@ static int ct_write(struct intel_guc_ct *ct, atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); /* now update descriptor */ - WRITE_ONCE(desc->tail, tail); + ct_desc_write(&ctb->desc_map, tail, tail); return 0; corrupted: CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", - desc->head, desc->tail, desc->status); + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail), + ct_desc_read(&ctb->desc_map, status)); ctb->broken = true; return -EPIPE; } @@ -499,20 +527,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; if (unlikely(ret)) { - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; - CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", ktime_ms_delta(ktime_get(), ct->stall_time), - send->status, recv->status); + ct_desc_read(&ct->ctbs.send.desc_map, status), + ct_desc_read(&ct->ctbs.recv.desc_map, status)); CT_ERROR(ct, "H2G Space: %u (Bytes)\n", atomic_read(&ct->ctbs.send.space) * 4); - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); + CT_ERROR(ct, "Head: %u (Dwords)\n", + ct_desc_read(&ct->ctbs.send.desc_map, head)); + CT_ERROR(ct, "Tail: %u (Dwords)\n", + ct_desc_read(&ct->ctbs.send.desc_map, tail)); CT_ERROR(ct, "G2H Space: %u (Bytes)\n", atomic_read(&ct->ctbs.recv.space) * 4); - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); + CT_ERROR(ct, "Head: %u\n (Dwords)", + ct_desc_read(&ct->ctbs.recv.desc_map, head)); + CT_ERROR(ct, "Tail: %u\n (Dwords)", + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); ct->ctbs.send.broken = true; } @@ -549,18 +579,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 head; u32 space; + u32 status = ct_desc_read(&ctb->desc_map, status); if (atomic_read(&ctb->space) >= len_dw) return true; - head = READ_ONCE(desc->head); + head = ct_desc_read(&ctb->desc_map, head); if (unlikely(head > ctb->size)) { CT_ERROR(ct, "Invalid head offset %u >= %u)\n", head, ctb->size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); ctb->broken = true; return false; } @@ -803,11 +834,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg) static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 head = ctb->head; - u32 tail = READ_ONCE(desc->tail); + u32 tail = ct_desc_read(&ctb->desc_map, tail); u32 size = ctb->size; - u32 *cmds = ctb->cmds; + u32 status = ct_desc_read(&ctb->desc_map, status); s32 available; unsigned int len; unsigned int i; @@ -816,23 +846,25 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (unlikely(ctb->broken)) return -EPIPE; - if (unlikely(desc->status)) + if (unlikely(status)) goto corrupted; GEM_BUG_ON(head > size); #ifdef CONFIG_DRM_I915_DEBUG_GUC - if (unlikely(head != READ_ONCE(desc->head))) { + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) { CT_ERROR(ct, "Head was modified %u != %u\n", - desc->head, head); - desc->status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_read(&ctb->desc_map, head), head); + status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } #endif if (unlikely(tail >= size)) { CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", tail, size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } @@ -849,7 +881,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); GEM_BUG_ON(available < 0); - header = cmds[head]; + header = iosys_map_rd(&ctb->cmds_map, sizeof(u32) * head, u32); head = (head + 1) % size; /* message len with header */ @@ -857,11 +889,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (unlikely(len > (u32)available)) { CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", 4, &header, + 4 * (head + available - 1 > size ? size - head : + available - 1), ((__px_vaddr(ct->vma->obj) + + CTB_RECV_CMDS_OFFSET) + (4 * head)), 4 * (head + available - 1 > size ? - size - head : available - 1), &cmds[head], - 4 * (head + available - 1 > size ? - available - 1 - size + head : 0), &cmds[0]); - desc->status |= GUC_CTB_STATUS_UNDERFLOW; + available - 1 - size + head : 0), + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); + status = ct_desc_read(&ctb->desc_map, status) | + GUC_CTB_STATUS_UNDERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } @@ -869,17 +905,20 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (!*msg) { CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", 4, &header, + 4 * (head + available - 1 > size ? size - head : + available - 1), ((__px_vaddr(ct->vma->obj) + + CTB_RECV_CMDS_OFFSET) + (4 * head)), 4 * (head + available - 1 > size ? - size - head : available - 1), &cmds[head], - 4 * (head + available - 1 > size ? - available - 1 - size + head : 0), &cmds[0]); + available - 1 - size + head : 0), + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); return available; } (*msg)->msg[0] = header; for (i = 1; i < len; i++) { - (*msg)->msg[i] = cmds[head]; + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, + sizeof(u32) * head, u32); head = (head + 1) % size; } CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); @@ -888,13 +927,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) ctb->head = head; /* now update descriptor */ - WRITE_ONCE(desc->head, head); + ct_desc_write(&ctb->desc_map, head, head); return available - len; corrupted: CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", - desc->head, desc->tail, desc->status); + ct_desc_read(&ctb->desc_map, head), + ct_desc_read(&ctb->desc_map, tail), + ct_desc_read(&ctb->desc_map, status)); ctb->broken = true; return -EPIPE; } @@ -1211,13 +1252,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, drm_printf(p, "H2G Space: %u\n", atomic_read(&ct->ctbs.send.space) * 4); drm_printf(p, "Head: %u\n", - ct->ctbs.send.desc->head); + ct_desc_read(&ct->ctbs.send.desc_map, head)); drm_printf(p, "Tail: %u\n", - ct->ctbs.send.desc->tail); + ct_desc_read(&ct->ctbs.send.desc_map, tail)); drm_printf(p, "G2H Space: %u\n", atomic_read(&ct->ctbs.recv.space) * 4); drm_printf(p, "Head: %u\n", - ct->ctbs.recv.desc->head); + ct_desc_read(&ct->ctbs.recv.desc_map, head)); drm_printf(p, "Tail: %u\n", - ct->ctbs.recv.desc->tail); + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h index f709a19c7e21..867fe13fb47d 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h @@ -7,6 +7,7 @@ #define _INTEL_GUC_CT_H_ #include <linux/interrupt.h> +#include <linux/iosys-map.h> #include <linux/spinlock.h> #include <linux/workqueue.h> #include <linux/ktime.h> @@ -32,8 +33,8 @@ struct drm_printer; * holds the commands. * * @lock: protects access to the commands buffer and buffer descriptor - * @desc: pointer to the buffer descriptor - * @cmds: pointer to the commands buffer + * @desc: iosys map to the buffer descriptor + * @cmds: iosys map to the commands buffer * @size: size of the commands buffer in dwords * @resv_space: reserved space in buffer in dwords * @head: local shadow copy of head in dwords @@ -43,8 +44,8 @@ struct drm_printer; */ struct intel_guc_ct_buffer { spinlock_t lock; - struct guc_ct_buffer_desc *desc; - u32 *cmds; + struct iosys_map desc_map; + struct iosys_map cmds_map; u32 size; u32 resv_space; u32 tail; -- 2.33.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map @ 2022-03-22 8:44 Mullati Siva 2022-03-22 8:44 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva 0 siblings, 1 reply; 16+ messages in thread From: Mullati Siva @ 2022-03-22 8:44 UTC (permalink / raw) To: intel-gfx, siva.mullati; +Cc: lucas.demarchi From: Siva Mullati <siva.mullati@intel.com> This is continuation to the below patch series to use iosys map APIs, to use CT commands and descriptors. https://patchwork.freedesktop.org/series/99711/ Siva Mullati (1): drm/i915/guc: Convert ct buffer to iosys_map drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- 2 files changed, 127 insertions(+), 82 deletions(-) -- 2.33.0 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-03-22 8:44 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva @ 2022-03-22 8:44 ` Mullati Siva 2022-04-02 4:13 ` Lucas De Marchi 0 siblings, 1 reply; 16+ messages in thread From: Mullati Siva @ 2022-03-22 8:44 UTC (permalink / raw) To: intel-gfx, siva.mullati; +Cc: lucas.demarchi From: Siva Mullati <siva.mullati@intel.com> Convert CT commands and descriptors to use iosys_map rather than plain pointer and save it in the intel_guc_ct_buffer struct. This will help with ct_write and ct_read for cmd send and receive after the initialization by abstracting the IO vs system memory. Signed-off-by: Siva Mullati <siva.mullati@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++--------- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- 2 files changed, 127 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c index f01325cd1b62..1c21ced44106 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c @@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) #define CT_PROBE_ERROR(_ct, _fmt, ...) \ i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) +#define ct_desc_read(desc_map_, field_) \ + iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) +#define ct_desc_write(desc_map_, field_, val_) \ + iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) + /** * DOC: CTB Blob * @@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) +#define CTB_SEND_DESC_OFFSET (0X0000) +#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) +#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) +#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) + struct ct_request { struct list_head link; u32 fence; @@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) init_waitqueue_head(&ct->wq); } -static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) +static void guc_ct_buffer_desc_init(struct iosys_map *desc) { - memset(desc, 0, sizeof(*desc)); + iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); } static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) @@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; atomic_set(&ctb->space, space); - guc_ct_buffer_desc_init(ctb->desc); + guc_ct_buffer_desc_init(&ctb->desc_map); } static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, - struct guc_ct_buffer_desc *desc, - u32 *cmds, u32 size_in_bytes, u32 resv_space) + struct iosys_map *desc, + struct iosys_map *cmds, + u32 size_in_bytes, u32 resv_space) { GEM_BUG_ON(size_in_bytes % 4); - ctb->desc = desc; - ctb->cmds = cmds; + ctb->desc_map = *desc; + ctb->cmds_map = *cmds; ctb->size = size_in_bytes / 4; ctb->resv_space = resv_space / 4; @@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, int intel_guc_ct_init(struct intel_guc_ct *ct) { struct intel_guc *guc = ct_to_guc(ct); - struct guc_ct_buffer_desc *desc; + struct iosys_map blob_map; + struct iosys_map desc_map; + struct iosys_map cmds_map; u32 blob_size; u32 cmds_size; u32 resv_space; void *blob; - u32 *cmds; int err; err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); @@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); - /* store pointers to desc and cmds for send ctb */ - desc = blob; - cmds = blob + 2 * CTB_DESC_SIZE; + if (i915_gem_object_is_lmem(ct->vma->obj)) + iosys_map_set_vaddr_iomem(&blob_map, + (void __iomem *)blob); + else + iosys_map_set_vaddr(&blob_map, blob); + + /* store sysmap to desc_map and cmds_map for send ctb */ + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); cmds_size = CTB_H2G_BUFFER_SIZE; resv_space = 0; - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, - resv_space); + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", + (u32)CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, + cmds_size, resv_space); - guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); + guc_ct_buffer_init(&ct->ctbs.send, + &desc_map, &cmds_map, cmds_size, resv_space); - /* store pointers to desc and cmds for recv ctb */ - desc = blob + CTB_DESC_SIZE; - cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; + /* store sysmap to desc_map and cmds_map for recv ctb */ + desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); + cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); cmds_size = CTB_G2H_BUFFER_SIZE; resv_space = G2H_ROOM_BUFFER_SIZE; - CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", - ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, - resv_space); + CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", + (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, + cmds_size, resv_space); - guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); + guc_ct_buffer_init(&ct->ctbs.recv, + &desc_map, &cmds_map, cmds_size, resv_space); return 0; } @@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) tasklet_kill(&ct->receive_tasklet); i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP); + iosys_map_clear(&ct->ctbs.send.desc_map); + iosys_map_clear(&ct->ctbs.send.cmds_map); + iosys_map_clear(&ct->ctbs.recv.desc_map); + iosys_map_clear(&ct->ctbs.recv.cmds_map); memset(ct, 0, sizeof(*ct)); } @@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) int intel_guc_ct_enable(struct intel_guc_ct *ct) { struct intel_guc *guc = ct_to_guc(ct); + struct iosys_map blob_map; u32 base, desc, cmds, size; - void *blob; int err; GEM_BUG_ON(ct->enabled); @@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); base = intel_guc_ggtt_offset(guc, ct->vma); + if (i915_gem_object_is_lmem(ct->vma->obj)) + iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) + __px_vaddr(ct->vma->obj)); + else + iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); + /* blob should start with send descriptor */ - blob = __px_vaddr(ct->vma->obj); - GEM_BUG_ON(blob != ct->ctbs.send.desc); + GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); /* (re)initialize descriptors */ guc_ct_buffer_reset(&ct->ctbs.send); @@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) * Register both CT buffers starting with RECV buffer. * Descriptors are in first half of the blob. */ - desc = base + ptrdiff(ct->ctbs.recv.desc, blob); - cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); + desc = base + CTB_RECV_DESC_OFFSET; + cmds = base + CTB_RECV_CMDS_OFFSET; size = ct->ctbs.recv.size * 4; err = ct_register_buffer(ct, false, desc, cmds, size); if (unlikely(err)) goto err_out; - desc = base + ptrdiff(ct->ctbs.send.desc, blob); - cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); + desc = base + CTB_SEND_DESC_OFFSET; + cmds = base + CTB_SEND_CMDS_OFFSET; size = ct->ctbs.send.size * 4; err = ct_register_buffer(ct, true, desc, cmds, size); if (unlikely(err)) @@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct, u32 fence, u32 flags) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 tail = ctb->tail; u32 size = ctb->size; u32 header; u32 hxg; u32 type; - u32 *cmds = ctb->cmds; + u32 status = ct_desc_read(&ctb->desc_map, status); unsigned int i; - if (unlikely(desc->status)) + if (unlikely(status)) goto corrupted; GEM_BUG_ON(tail > size); #ifdef CONFIG_DRM_I915_DEBUG_GUC - if (unlikely(tail != READ_ONCE(desc->tail))) { + if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { CT_ERROR(ct, "Tail was modified %u != %u\n", - desc->tail, tail); - desc->status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_read(&ctb->desc_map, tail), tail); + status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } - if (unlikely(READ_ONCE(desc->head) >= size)) { + if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) { CT_ERROR(ct, "Invalid head offset %u >= %u)\n", - desc->head, size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_read(&ctb->desc_map, head), size); + status = ct_desc_read(&ctb->desc_map, status) | + GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } #endif @@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct, CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); - cmds[tail] = header; + iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, header); tail = (tail + 1) % size; - cmds[tail] = hxg; + iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, hxg); tail = (tail + 1) % size; for (i = 1; i < len; i++) { - cmds[tail] = action[i]; + iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, action[i]); tail = (tail + 1) % size; } GEM_BUG_ON(tail > size); @@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct, atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); /* now update descriptor */ - WRITE_ONCE(desc->tail, tail); + ct_desc_write(&ctb->desc_map, tail, tail); return 0; corrupted: CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", - desc->head, desc->tail, desc->status); + ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail), + ct_desc_read(&ctb->desc_map, status)); ctb->broken = true; return -EPIPE; } @@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; if (unlikely(ret)) { - struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; - struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; - CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", ktime_ms_delta(ktime_get(), ct->stall_time), - send->status, recv->status); + ct_desc_read(&ct->ctbs.send.desc_map, status), + ct_desc_read(&ct->ctbs.recv.desc_map, status)); CT_ERROR(ct, "H2G Space: %u (Bytes)\n", atomic_read(&ct->ctbs.send.space) * 4); - CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); - CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); + CT_ERROR(ct, "Head: %u (Dwords)\n", + ct_desc_read(&ct->ctbs.send.desc_map, head)); + CT_ERROR(ct, "Tail: %u (Dwords)\n", + ct_desc_read(&ct->ctbs.send.desc_map, tail)); CT_ERROR(ct, "G2H Space: %u (Bytes)\n", atomic_read(&ct->ctbs.recv.space) * 4); - CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); - CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); + CT_ERROR(ct, "Head: %u\n (Dwords)", + ct_desc_read(&ct->ctbs.recv.desc_map, head)); + CT_ERROR(ct, "Tail: %u\n (Dwords)", + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); ct->ctbs.send.broken = true; } @@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 head; u32 space; + u32 status = ct_desc_read(&ctb->desc_map, status); if (atomic_read(&ctb->space) >= len_dw) return true; - head = READ_ONCE(desc->head); + head = ct_desc_read(&ctb->desc_map, head); if (unlikely(head > ctb->size)) { CT_ERROR(ct, "Invalid head offset %u >= %u)\n", head, ctb->size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + status |= GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); ctb->broken = true; return false; } @@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg) static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) { struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; - struct guc_ct_buffer_desc *desc = ctb->desc; u32 head = ctb->head; - u32 tail = READ_ONCE(desc->tail); + u32 tail = ct_desc_read(&ctb->desc_map, tail); u32 size = ctb->size; - u32 *cmds = ctb->cmds; + u32 status = ct_desc_read(&ctb->desc_map, status); s32 available; unsigned int len; unsigned int i; @@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (unlikely(ctb->broken)) return -EPIPE; - if (unlikely(desc->status)) + if (unlikely(status)) goto corrupted; GEM_BUG_ON(head > size); #ifdef CONFIG_DRM_I915_DEBUG_GUC - if (unlikely(head != READ_ONCE(desc->head))) { + if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) { CT_ERROR(ct, "Head was modified %u != %u\n", - desc->head, head); - desc->status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_read(&ctb->desc_map, head), head); + status |= GUC_CTB_STATUS_MISMATCH; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } #endif if (unlikely(tail >= size)) { CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", tail, size); - desc->status |= GUC_CTB_STATUS_OVERFLOW; + status = ct_desc_read(&ctb->desc_map, status) | + GUC_CTB_STATUS_OVERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } @@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); GEM_BUG_ON(available < 0); - header = cmds[head]; + header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32); head = (head + 1) % size; /* message len with header */ @@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (unlikely(len > (u32)available)) { CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", 4, &header, + 4 * (head + available - 1 > size ? size - head : + available - 1), ((__px_vaddr(ct->vma->obj) + + CTB_RECV_CMDS_OFFSET) + (4 * head)), 4 * (head + available - 1 > size ? - size - head : available - 1), &cmds[head], - 4 * (head + available - 1 > size ? - available - 1 - size + head : 0), &cmds[0]); - desc->status |= GUC_CTB_STATUS_UNDERFLOW; + available - 1 - size + head : 0), + (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); + status = ct_desc_read(&ctb->desc_map, status) | + GUC_CTB_STATUS_UNDERFLOW; + ct_desc_write(&ctb->desc_map, status, status); goto corrupted; } @@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) if (!*msg) { CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", 4, &header, + 4 * (head + available - 1 > size ? size - head : + available - 1), (ctb->cmds_map.vaddr + (4 * head)), 4 * (head + available - 1 > size ? - size - head : available - 1), &cmds[head], - 4 * (head + available - 1 > size ? - available - 1 - size + head : 0), &cmds[0]); + available - 1 - size + head : 0), ctb->cmds_map.vaddr); return available; } (*msg)->msg[0] = header; for (i = 1; i < len; i++) { - (*msg)->msg[i] = cmds[head]; + (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, + (4 * head), u32); head = (head + 1) % size; } CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); @@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) ctb->head = head; /* now update descriptor */ - WRITE_ONCE(desc->head, head); + ct_desc_write(&ctb->desc_map, head, head); return available - len; corrupted: CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", - desc->head, desc->tail, desc->status); + ct_desc_read(&ctb->desc_map, head), + ct_desc_read(&ctb->desc_map, tail), + ct_desc_read(&ctb->desc_map, status)); ctb->broken = true; return -EPIPE; } @@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, drm_printf(p, "H2G Space: %u\n", atomic_read(&ct->ctbs.send.space) * 4); drm_printf(p, "Head: %u\n", - ct->ctbs.send.desc->head); + ct_desc_read(&ct->ctbs.send.desc_map, head)); drm_printf(p, "Tail: %u\n", - ct->ctbs.send.desc->tail); + ct_desc_read(&ct->ctbs.send.desc_map, tail)); drm_printf(p, "G2H Space: %u\n", atomic_read(&ct->ctbs.recv.space) * 4); drm_printf(p, "Head: %u\n", - ct->ctbs.recv.desc->head); + ct_desc_read(&ct->ctbs.recv.desc_map, head)); drm_printf(p, "Tail: %u\n", - ct->ctbs.recv.desc->tail); + ct_desc_read(&ct->ctbs.recv.desc_map, tail)); } diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h index f709a19c7e21..867fe13fb47d 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h @@ -7,6 +7,7 @@ #define _INTEL_GUC_CT_H_ #include <linux/interrupt.h> +#include <linux/iosys-map.h> #include <linux/spinlock.h> #include <linux/workqueue.h> #include <linux/ktime.h> @@ -32,8 +33,8 @@ struct drm_printer; * holds the commands. * * @lock: protects access to the commands buffer and buffer descriptor - * @desc: pointer to the buffer descriptor - * @cmds: pointer to the commands buffer + * @desc: iosys map to the buffer descriptor + * @cmds: iosys map to the commands buffer * @size: size of the commands buffer in dwords * @resv_space: reserved space in buffer in dwords * @head: local shadow copy of head in dwords @@ -43,8 +44,8 @@ struct drm_printer; */ struct intel_guc_ct_buffer { spinlock_t lock; - struct guc_ct_buffer_desc *desc; - u32 *cmds; + struct iosys_map desc_map; + struct iosys_map cmds_map; u32 size; u32 resv_space; u32 tail; -- 2.33.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map 2022-03-22 8:44 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva @ 2022-04-02 4:13 ` Lucas De Marchi 0 siblings, 0 replies; 16+ messages in thread From: Lucas De Marchi @ 2022-04-02 4:13 UTC (permalink / raw) To: Mullati Siva; +Cc: intel-gfx On Tue, Mar 22, 2022 at 02:14:37PM +0530, Mullati Siva wrote: >From: Siva Mullati <siva.mullati@intel.com> > >Convert CT commands and descriptors to use iosys_map rather >than plain pointer and save it in the intel_guc_ct_buffer struct. >This will help with ct_write and ct_read for cmd send and receive >after the initialization by abstracting the IO vs system memory. > >Signed-off-by: Siva Mullati <siva.mullati@intel.com> >--- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 200 +++++++++++++--------- > drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 9 +- > 2 files changed, 127 insertions(+), 82 deletions(-) > >diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >index f01325cd1b62..1c21ced44106 100644 >--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c >@@ -44,6 +44,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > #define CT_PROBE_ERROR(_ct, _fmt, ...) \ > i915_probe_error(ct_to_i915(ct), "CT: " _fmt, ##__VA_ARGS__) > >+#define ct_desc_read(desc_map_, field_) \ >+ iosys_map_rd_field(desc_map_, 0, struct guc_ct_buffer_desc, field_) >+#define ct_desc_write(desc_map_, field_, val_) \ >+ iosys_map_wr_field(desc_map_, 0, struct guc_ct_buffer_desc, field_, val_) >+ > /** > * DOC: CTB Blob > * >@@ -76,6 +81,11 @@ static inline struct drm_device *ct_to_drm(struct intel_guc_ct *ct) > #define CTB_G2H_BUFFER_SIZE (4 * CTB_H2G_BUFFER_SIZE) > #define G2H_ROOM_BUFFER_SIZE (CTB_G2H_BUFFER_SIZE / 4) > >+#define CTB_SEND_DESC_OFFSET (0X0000) 0, or even better... 0u, so you don't have to cast to unsigned in other places >+#define CTB_RECV_DESC_OFFSET (CTB_DESC_SIZE) >+#define CTB_SEND_CMDS_OFFSET (2 * CTB_DESC_SIZE) >+#define CTB_RECV_CMDS_OFFSET (2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE) >+ > struct ct_request { > struct list_head link; > u32 fence; >@@ -113,9 +123,9 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct) > init_waitqueue_head(&ct->wq); > } > >-static void guc_ct_buffer_desc_init(struct guc_ct_buffer_desc *desc) >+static void guc_ct_buffer_desc_init(struct iosys_map *desc) > { >- memset(desc, 0, sizeof(*desc)); >+ iosys_map_memset(desc, 0, 0, sizeof(struct guc_ct_buffer_desc)); > } > > static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) >@@ -128,17 +138,18 @@ static void guc_ct_buffer_reset(struct intel_guc_ct_buffer *ctb) > space = CIRC_SPACE(ctb->tail, ctb->head, ctb->size) - ctb->resv_space; > atomic_set(&ctb->space, space); > >- guc_ct_buffer_desc_init(ctb->desc); >+ guc_ct_buffer_desc_init(&ctb->desc_map); > } > > static void guc_ct_buffer_init(struct intel_guc_ct_buffer *ctb, >- struct guc_ct_buffer_desc *desc, >- u32 *cmds, u32 size_in_bytes, u32 resv_space) >+ struct iosys_map *desc, >+ struct iosys_map *cmds, >+ u32 size_in_bytes, u32 resv_space) > { > GEM_BUG_ON(size_in_bytes % 4); > >- ctb->desc = desc; >- ctb->cmds = cmds; >+ ctb->desc_map = *desc; >+ ctb->cmds_map = *cmds; > ctb->size = size_in_bytes / 4; > ctb->resv_space = resv_space / 4; > >@@ -218,12 +229,13 @@ static int ct_register_buffer(struct intel_guc_ct *ct, bool send, > int intel_guc_ct_init(struct intel_guc_ct *ct) > { > struct intel_guc *guc = ct_to_guc(ct); >- struct guc_ct_buffer_desc *desc; >+ struct iosys_map blob_map; >+ struct iosys_map desc_map; >+ struct iosys_map cmds_map; > u32 blob_size; > u32 cmds_size; > u32 resv_space; > void *blob; >- u32 *cmds; > int err; > > err = i915_inject_probe_error(guc_to_gt(guc)->i915, -ENXIO); >@@ -242,27 +254,35 @@ int intel_guc_ct_init(struct intel_guc_ct *ct) > > CT_DEBUG(ct, "base=%#x size=%u\n", intel_guc_ggtt_offset(guc, ct->vma), blob_size); > >- /* store pointers to desc and cmds for send ctb */ >- desc = blob; >- cmds = blob + 2 * CTB_DESC_SIZE; >+ if (i915_gem_object_is_lmem(ct->vma->obj)) >+ iosys_map_set_vaddr_iomem(&blob_map, >+ (void __iomem *)blob); >+ else >+ iosys_map_set_vaddr(&blob_map, blob); >+ >+ /* store sysmap to desc_map and cmds_map for send ctb */ >+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_DESC_OFFSET); >+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_SEND_CMDS_OFFSET); > cmds_size = CTB_H2G_BUFFER_SIZE; > resv_space = 0; >- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "send", >- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, >- resv_space); >+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "send", >+ (u32)CTB_SEND_DESC_OFFSET, (u32)CTB_SEND_CMDS_OFFSET, >+ cmds_size, resv_space); > >- guc_ct_buffer_init(&ct->ctbs.send, desc, cmds, cmds_size, resv_space); >+ guc_ct_buffer_init(&ct->ctbs.send, >+ &desc_map, &cmds_map, cmds_size, resv_space); > >- /* store pointers to desc and cmds for recv ctb */ >- desc = blob + CTB_DESC_SIZE; >- cmds = blob + 2 * CTB_DESC_SIZE + CTB_H2G_BUFFER_SIZE; >+ /* store sysmap to desc_map and cmds_map for recv ctb */ >+ desc_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_DESC_OFFSET); >+ cmds_map = IOSYS_MAP_INIT_OFFSET(&blob_map, CTB_RECV_CMDS_OFFSET); > cmds_size = CTB_G2H_BUFFER_SIZE; > resv_space = G2H_ROOM_BUFFER_SIZE; >- CT_DEBUG(ct, "%s desc %#tx cmds %#tx size %u/%u\n", "recv", >- ptrdiff(desc, blob), ptrdiff(cmds, blob), cmds_size, >- resv_space); >+ CT_DEBUG(ct, "%s desc %#x cmds %#x size %u/%u\n", "recv", >+ (u32)CTB_RECV_DESC_OFFSET, (u32)CTB_RECV_CMDS_OFFSET, >+ cmds_size, resv_space); > >- guc_ct_buffer_init(&ct->ctbs.recv, desc, cmds, cmds_size, resv_space); >+ guc_ct_buffer_init(&ct->ctbs.recv, >+ &desc_map, &cmds_map, cmds_size, resv_space); > > return 0; > } >@@ -279,6 +299,10 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) > > tasklet_kill(&ct->receive_tasklet); > i915_vma_unpin_and_release(&ct->vma, I915_VMA_RELEASE_MAP); >+ iosys_map_clear(&ct->ctbs.send.desc_map); >+ iosys_map_clear(&ct->ctbs.send.cmds_map); >+ iosys_map_clear(&ct->ctbs.recv.desc_map); >+ iosys_map_clear(&ct->ctbs.recv.cmds_map); > memset(ct, 0, sizeof(*ct)); > } > >@@ -291,8 +315,8 @@ void intel_guc_ct_fini(struct intel_guc_ct *ct) > int intel_guc_ct_enable(struct intel_guc_ct *ct) > { > struct intel_guc *guc = ct_to_guc(ct); >+ struct iosys_map blob_map; > u32 base, desc, cmds, size; >- void *blob; > int err; > > GEM_BUG_ON(ct->enabled); >@@ -302,9 +326,14 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > GEM_BUG_ON(!i915_gem_object_has_pinned_pages(ct->vma->obj)); > base = intel_guc_ggtt_offset(guc, ct->vma); > >+ if (i915_gem_object_is_lmem(ct->vma->obj)) >+ iosys_map_set_vaddr_iomem(&blob_map, (void __iomem *) >+ __px_vaddr(ct->vma->obj)); >+ else >+ iosys_map_set_vaddr(&blob_map, __px_vaddr(ct->vma->obj)); >+ > /* blob should start with send descriptor */ >- blob = __px_vaddr(ct->vma->obj); >- GEM_BUG_ON(blob != ct->ctbs.send.desc); >+ GEM_BUG_ON(!iosys_map_is_equal(&blob_map, &ct->ctbs.send.desc_map)); > > /* (re)initialize descriptors */ > guc_ct_buffer_reset(&ct->ctbs.send); >@@ -314,15 +343,15 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct) > * Register both CT buffers starting with RECV buffer. > * Descriptors are in first half of the blob. > */ >- desc = base + ptrdiff(ct->ctbs.recv.desc, blob); >- cmds = base + ptrdiff(ct->ctbs.recv.cmds, blob); >+ desc = base + CTB_RECV_DESC_OFFSET; >+ cmds = base + CTB_RECV_CMDS_OFFSET; > size = ct->ctbs.recv.size * 4; > err = ct_register_buffer(ct, false, desc, cmds, size); > if (unlikely(err)) > goto err_out; > >- desc = base + ptrdiff(ct->ctbs.send.desc, blob); >- cmds = base + ptrdiff(ct->ctbs.send.cmds, blob); >+ desc = base + CTB_SEND_DESC_OFFSET; >+ cmds = base + CTB_SEND_CMDS_OFFSET; > size = ct->ctbs.send.size * 4; > err = ct_register_buffer(ct, true, desc, cmds, size); > if (unlikely(err)) >@@ -371,31 +400,33 @@ static int ct_write(struct intel_guc_ct *ct, > u32 fence, u32 flags) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; >- struct guc_ct_buffer_desc *desc = ctb->desc; > u32 tail = ctb->tail; > u32 size = ctb->size; > u32 header; > u32 hxg; > u32 type; >- u32 *cmds = ctb->cmds; >+ u32 status = ct_desc_read(&ctb->desc_map, status); > unsigned int i; > >- if (unlikely(desc->status)) >+ if (unlikely(status)) > goto corrupted; > > GEM_BUG_ON(tail > size); > > #ifdef CONFIG_DRM_I915_DEBUG_GUC >- if (unlikely(tail != READ_ONCE(desc->tail))) { >+ if (unlikely(tail != ct_desc_read(&ctb->desc_map, tail))) { > CT_ERROR(ct, "Tail was modified %u != %u\n", >- desc->tail, tail); >- desc->status |= GUC_CTB_STATUS_MISMATCH; >+ ct_desc_read(&ctb->desc_map, tail), tail); >+ status |= GUC_CTB_STATUS_MISMATCH; >+ ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } >- if (unlikely(READ_ONCE(desc->head) >= size)) { >+ if (unlikely(ct_desc_read(&ctb->desc_map, head) >= size)) { > CT_ERROR(ct, "Invalid head offset %u >= %u)\n", >- desc->head, size); >- desc->status |= GUC_CTB_STATUS_OVERFLOW; >+ ct_desc_read(&ctb->desc_map, head), size); >+ status = ct_desc_read(&ctb->desc_map, status) | >+ GUC_CTB_STATUS_OVERFLOW; >+ ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > #endif >@@ -418,14 +449,14 @@ static int ct_write(struct intel_guc_ct *ct, > CT_DEBUG(ct, "writing (tail %u) %*ph %*ph %*ph\n", > tail, 4, &header, 4, &hxg, 4 * (len - 1), &action[1]); > >- cmds[tail] = header; >+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, header); excess parenthesis -------------^ > tail = (tail + 1) % size; > >- cmds[tail] = hxg; >+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, hxg); and in other places like here > tail = (tail + 1) % size; > > for (i = 1; i < len; i++) { >- cmds[tail] = action[i]; >+ iosys_map_wr(&ctb->cmds_map, (4 * tail), u32, action[i]); > tail = (tail + 1) % size; > } > GEM_BUG_ON(tail > size); >@@ -442,13 +473,14 @@ static int ct_write(struct intel_guc_ct *ct, > atomic_sub(len + GUC_CTB_HDR_LEN, &ctb->space); > > /* now update descriptor */ >- WRITE_ONCE(desc->tail, tail); >+ ct_desc_write(&ctb->desc_map, tail, tail); too bad we will lose the _ONCE annotations. Eventually we may want to remove the memcpy[_fromio()] function call, but then we will need to pay attention to these. Not something to do here though, just thinking out loud. ... lots of changes in a single patch, but apparently it's ok. with above changes Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> thanks Lucas De Marchi > > return 0; > > corrupted: > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", >- desc->head, desc->tail, desc->status); >+ ct_desc_read(&ctb->desc_map, head), ct_desc_read(&ctb->desc_map, tail), >+ ct_desc_read(&ctb->desc_map, status)); > ctb->broken = true; > return -EPIPE; > } >@@ -499,20 +531,22 @@ static inline bool ct_deadlocked(struct intel_guc_ct *ct) > bool ret = ktime_ms_delta(ktime_get(), ct->stall_time) > timeout; > > if (unlikely(ret)) { >- struct guc_ct_buffer_desc *send = ct->ctbs.send.desc; >- struct guc_ct_buffer_desc *recv = ct->ctbs.send.desc; >- > CT_ERROR(ct, "Communication stalled for %lld ms, desc status=%#x,%#x\n", > ktime_ms_delta(ktime_get(), ct->stall_time), >- send->status, recv->status); >+ ct_desc_read(&ct->ctbs.send.desc_map, status), >+ ct_desc_read(&ct->ctbs.recv.desc_map, status)); > CT_ERROR(ct, "H2G Space: %u (Bytes)\n", > atomic_read(&ct->ctbs.send.space) * 4); >- CT_ERROR(ct, "Head: %u (Dwords)\n", ct->ctbs.send.desc->head); >- CT_ERROR(ct, "Tail: %u (Dwords)\n", ct->ctbs.send.desc->tail); >+ CT_ERROR(ct, "Head: %u (Dwords)\n", >+ ct_desc_read(&ct->ctbs.send.desc_map, head)); >+ CT_ERROR(ct, "Tail: %u (Dwords)\n", >+ ct_desc_read(&ct->ctbs.send.desc_map, tail)); > CT_ERROR(ct, "G2H Space: %u (Bytes)\n", > atomic_read(&ct->ctbs.recv.space) * 4); >- CT_ERROR(ct, "Head: %u\n (Dwords)", ct->ctbs.recv.desc->head); >- CT_ERROR(ct, "Tail: %u\n (Dwords)", ct->ctbs.recv.desc->tail); >+ CT_ERROR(ct, "Head: %u\n (Dwords)", >+ ct_desc_read(&ct->ctbs.recv.desc_map, head)); >+ CT_ERROR(ct, "Tail: %u\n (Dwords)", >+ ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > > ct->ctbs.send.broken = true; > } >@@ -549,18 +583,19 @@ static inline void g2h_release_space(struct intel_guc_ct *ct, u32 g2h_len_dw) > static inline bool h2g_has_room(struct intel_guc_ct *ct, u32 len_dw) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.send; >- struct guc_ct_buffer_desc *desc = ctb->desc; > u32 head; > u32 space; >+ u32 status = ct_desc_read(&ctb->desc_map, status); > > if (atomic_read(&ctb->space) >= len_dw) > return true; > >- head = READ_ONCE(desc->head); >+ head = ct_desc_read(&ctb->desc_map, head); > if (unlikely(head > ctb->size)) { > CT_ERROR(ct, "Invalid head offset %u >= %u)\n", > head, ctb->size); >- desc->status |= GUC_CTB_STATUS_OVERFLOW; >+ status |= GUC_CTB_STATUS_OVERFLOW; >+ ct_desc_write(&ctb->desc_map, status, status); > ctb->broken = true; > return false; > } >@@ -803,11 +838,10 @@ static void ct_free_msg(struct ct_incoming_msg *msg) > static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > { > struct intel_guc_ct_buffer *ctb = &ct->ctbs.recv; >- struct guc_ct_buffer_desc *desc = ctb->desc; > u32 head = ctb->head; >- u32 tail = READ_ONCE(desc->tail); >+ u32 tail = ct_desc_read(&ctb->desc_map, tail); > u32 size = ctb->size; >- u32 *cmds = ctb->cmds; >+ u32 status = ct_desc_read(&ctb->desc_map, status); > s32 available; > unsigned int len; > unsigned int i; >@@ -816,23 +850,26 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (unlikely(ctb->broken)) > return -EPIPE; > >- if (unlikely(desc->status)) >+ if (unlikely(status)) > goto corrupted; > > GEM_BUG_ON(head > size); > > #ifdef CONFIG_DRM_I915_DEBUG_GUC >- if (unlikely(head != READ_ONCE(desc->head))) { >+ if (unlikely(head != ct_desc_read(&ctb->desc_map, head))) { > CT_ERROR(ct, "Head was modified %u != %u\n", >- desc->head, head); >- desc->status |= GUC_CTB_STATUS_MISMATCH; >+ ct_desc_read(&ctb->desc_map, head), head); >+ status |= GUC_CTB_STATUS_MISMATCH; >+ ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > #endif > if (unlikely(tail >= size)) { > CT_ERROR(ct, "Invalid tail offset %u >= %u)\n", > tail, size); >- desc->status |= GUC_CTB_STATUS_OVERFLOW; >+ status = ct_desc_read(&ctb->desc_map, status) | >+ GUC_CTB_STATUS_OVERFLOW; >+ ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > >@@ -849,7 +886,7 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > CT_DEBUG(ct, "available %d (%u:%u:%u)\n", available, head, tail, size); > GEM_BUG_ON(available < 0); > >- header = cmds[head]; >+ header = iosys_map_rd(&ctb->cmds_map, (4 * head), u32); > head = (head + 1) % size; > > /* message len with header */ >@@ -857,11 +894,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (unlikely(len > (u32)available)) { > CT_ERROR(ct, "Incomplete message %*ph %*ph %*ph\n", > 4, &header, >+ 4 * (head + available - 1 > size ? size - head : >+ available - 1), ((__px_vaddr(ct->vma->obj) + >+ CTB_RECV_CMDS_OFFSET) + (4 * head)), > 4 * (head + available - 1 > size ? >- size - head : available - 1), &cmds[head], >- 4 * (head + available - 1 > size ? >- available - 1 - size + head : 0), &cmds[0]); >- desc->status |= GUC_CTB_STATUS_UNDERFLOW; >+ available - 1 - size + head : 0), >+ (__px_vaddr(ct->vma->obj) + CTB_RECV_CMDS_OFFSET)); >+ status = ct_desc_read(&ctb->desc_map, status) | >+ GUC_CTB_STATUS_UNDERFLOW; >+ ct_desc_write(&ctb->desc_map, status, status); > goto corrupted; > } > >@@ -869,17 +910,18 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > if (!*msg) { > CT_ERROR(ct, "No memory for message %*ph %*ph %*ph\n", > 4, &header, >+ 4 * (head + available - 1 > size ? size - head : >+ available - 1), (ctb->cmds_map.vaddr + (4 * head)), > 4 * (head + available - 1 > size ? >- size - head : available - 1), &cmds[head], >- 4 * (head + available - 1 > size ? >- available - 1 - size + head : 0), &cmds[0]); >+ available - 1 - size + head : 0), ctb->cmds_map.vaddr); > return available; > } > > (*msg)->msg[0] = header; > > for (i = 1; i < len; i++) { >- (*msg)->msg[i] = cmds[head]; >+ (*msg)->msg[i] = iosys_map_rd(&ctb->cmds_map, >+ (4 * head), u32); > head = (head + 1) % size; > } > CT_DEBUG(ct, "received %*ph\n", 4 * len, (*msg)->msg); >@@ -888,13 +930,15 @@ static int ct_read(struct intel_guc_ct *ct, struct ct_incoming_msg **msg) > ctb->head = head; > > /* now update descriptor */ >- WRITE_ONCE(desc->head, head); >+ ct_desc_write(&ctb->desc_map, head, head); > > return available - len; > > corrupted: > CT_ERROR(ct, "Corrupted descriptor head=%u tail=%u status=%#x\n", >- desc->head, desc->tail, desc->status); >+ ct_desc_read(&ctb->desc_map, head), >+ ct_desc_read(&ctb->desc_map, tail), >+ ct_desc_read(&ctb->desc_map, status)); > ctb->broken = true; > return -EPIPE; > } >@@ -1211,13 +1255,13 @@ void intel_guc_ct_print_info(struct intel_guc_ct *ct, > drm_printf(p, "H2G Space: %u\n", > atomic_read(&ct->ctbs.send.space) * 4); > drm_printf(p, "Head: %u\n", >- ct->ctbs.send.desc->head); >+ ct_desc_read(&ct->ctbs.send.desc_map, head)); > drm_printf(p, "Tail: %u\n", >- ct->ctbs.send.desc->tail); >+ ct_desc_read(&ct->ctbs.send.desc_map, tail)); > drm_printf(p, "G2H Space: %u\n", > atomic_read(&ct->ctbs.recv.space) * 4); > drm_printf(p, "Head: %u\n", >- ct->ctbs.recv.desc->head); >+ ct_desc_read(&ct->ctbs.recv.desc_map, head)); > drm_printf(p, "Tail: %u\n", >- ct->ctbs.recv.desc->tail); >+ ct_desc_read(&ct->ctbs.recv.desc_map, tail)); > } >diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h >index f709a19c7e21..867fe13fb47d 100644 >--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h >+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h >@@ -7,6 +7,7 @@ > #define _INTEL_GUC_CT_H_ > > #include <linux/interrupt.h> >+#include <linux/iosys-map.h> > #include <linux/spinlock.h> > #include <linux/workqueue.h> > #include <linux/ktime.h> >@@ -32,8 +33,8 @@ struct drm_printer; > * holds the commands. > * > * @lock: protects access to the commands buffer and buffer descriptor >- * @desc: pointer to the buffer descriptor >- * @cmds: pointer to the commands buffer >+ * @desc: iosys map to the buffer descriptor >+ * @cmds: iosys map to the commands buffer > * @size: size of the commands buffer in dwords > * @resv_space: reserved space in buffer in dwords > * @head: local shadow copy of head in dwords >@@ -43,8 +44,8 @@ struct drm_printer; > */ > struct intel_guc_ct_buffer { > spinlock_t lock; >- struct guc_ct_buffer_desc *desc; >- u32 *cmds; >+ struct iosys_map desc_map; >+ struct iosys_map cmds_map; > u32 size; > u32 resv_space; > u32 tail; >-- >2.33.0 > ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-05-11 15:15 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-04 9:31 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva 2022-04-04 9:31 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva 2022-04-14 12:11 ` Balasubramani Vivekanandan 2022-04-28 14:13 ` Siva Mullati 2022-04-29 9:07 ` Balasubramani Vivekanandan 2022-04-18 9:08 ` Balasubramani Vivekanandan 2022-04-04 10:41 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev3) Patchwork 2022-04-04 11:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-04-04 13:42 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-04-08 5:07 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor CT access to use iosys_map (rev4) Patchwork 2022-04-08 5:42 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2022-05-09 6:49 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva 2022-05-09 6:49 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva 2022-05-11 15:15 ` Balasubramani Vivekanandan 2022-04-21 17:26 [Intel-gfx] [PATCH 0/1] Refactor CT access to use iosys_map Mullati Siva 2022-04-21 17:26 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva 2022-03-22 8:44 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor CT access to use iosys_map Mullati Siva 2022-03-22 8:44 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert ct buffer to iosys_map Mullati Siva 2022-04-02 4:13 ` Lucas De Marchi
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