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From: Rob Herring <robh@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Jingoo Han <jingoohan1@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	Vinod Koul <vkoul@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: Re: [PATCH v7 6/7] dt-bindings: PCI: qcom: Support additional MSI interrupts
Date: Thu, 5 May 2022 16:30:09 -0500	[thread overview]
Message-ID: <YnRB4UxBzFDmsls7@robh.at.kernel.org> (raw)
In-Reply-To: <20220505135407.1352382-7-dmitry.baryshkov@linaro.org>

On Thu, May 05, 2022 at 04:54:06PM +0300, Dmitry Baryshkov wrote:
> On Qualcomm platforms each group of 32 MSI vectors is routed to the
> separate GIC interrupt. Document mapping of additional interrupts.
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../devicetree/bindings/pci/qcom,pcie.yaml    | 45 ++++++++++++++++++-
>  1 file changed, 44 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index 0b69b12b849e..fd3290e0e220 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -43,11 +43,20 @@ properties:
>      maxItems: 5
>  
>    interrupts:
> -    maxItems: 1
> +    minItems: 1
> +    maxItems: 8
>  
>    interrupt-names:
> +    minItems: 1
>      items:
>        - const: msi
> +      - const: msi2

Is 2 from some documentation or you made up. If the latter, software 
folks start numbering at 0, not 1. :) I wouldn't care, but I think this 
may become common. 

> +      - const: msi3
> +      - const: msi4
> +      - const: msi5
> +      - const: msi6
> +      - const: msi7
> +      - const: msi8

  reply	other threads:[~2022-05-05 21:30 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-05 13:54 [PATCH v7 0/7] PCI: qcom: Fix higher MSI vectors handling Dmitry Baryshkov
2022-05-05 13:54 ` [PATCH v7 1/7] PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" Dmitry Baryshkov
2022-05-05 20:12   ` Rob Herring
2022-05-05 13:54 ` [PATCH v7 2/7] PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() Dmitry Baryshkov
2022-05-05 20:11   ` Rob Herring
2022-05-05 13:54 ` [PATCH v7 3/7] PCI: dwc: Add msi_host_deinit callback Dmitry Baryshkov
2022-05-05 13:54 ` [PATCH v7 4/7] PCI: dwc: Export several functions useful for MSI implentations Dmitry Baryshkov
2022-05-05 13:54 ` [PATCH v7 5/7] PCI: qcom: Handle MSIs routed to multiple GIC interrupts Dmitry Baryshkov
2022-05-05 21:26   ` Rob Herring
2022-05-06  7:40     ` Dmitry Baryshkov
2022-05-09 21:00       ` Rob Herring
2022-05-05 13:54 ` [PATCH v7 6/7] dt-bindings: PCI: qcom: Support additional MSI interrupts Dmitry Baryshkov
2022-05-05 21:30   ` Rob Herring [this message]
2022-05-11 14:50     ` Dmitry Baryshkov
2022-05-05 13:54 ` [PATCH v7 7/7] arm64: dts: qcom: sm8250: provide " Dmitry Baryshkov
2022-05-05 15:37 ` [PATCH v7 0/7] PCI: qcom: Fix higher MSI vectors handling Stanimir Varbanov

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