* [PATCH v7 0/7] Introduce multitile support
@ 2022-03-18 23:39 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Abdiel Janulgue, Andi Shyti, Tvrtko Ursulin, Lucas De Marchi,
Chris Wilson, Daniele Ceraolo Spurio, Matthew Auld, Andi Shyti,
Sujaritha Sundaresan, Dale B Stimson, Michal Wajdeczko
Hi,
This is the second series that prepares i915 to host multitile
platforms. It introduces the for_each_gt() macro that loops over
the tiles to perform per gt actions.
This patch is a combination of two patches developed originally
by Abdiel, who introduced some refactoring during probe, and then
Tvrtko has added the necessary tools to start using the various
tiles.
The second patch re-organises the sysfs interface to expose the
API for each of the GTs. I decided to prioritise this patch
over others to unblock Sujaritha for further development.
A third series will still follow this.
Thanks Michal and Andrzej for the reviews and support!
Thanks,
Andi
Patchwork: https://patchwork.freedesktop.org/series/98741/
Changelog
=========
v6 -> v7
- fixed a mock selftest error by initializing i915->gt[0]
(thanks Tvrtko!)
- removed spurious file added by mistake (thanks Matt!)
- improved commit log in patch 7 (thanks Suja!)
v5 -> v6
- address all Michal and Andrzej's reviews that consist mainly
in code refactoring.
v4 -> v5
- fixed Michal's reviews.
- the sysfs patches have been split in 3 parts to make reviews
easier.
- Sujaritha's patch on pm throttle has been queued.
- INTEL_REGION_LMEM has been renamed to INTEL_REGION_LMEM_0
- added the gt_is_root() helper
- the sysfs files will be called intel_gt_sysfs_* instead of
sysfs_gt_*
v3 -> v4
- fixed Tvrtko's review:
- remove the SYSFS_DEPRECATED_V2 mention from the commit log
- reworded the error message when accessing deprecated files
- errors in sysfs are printed as warnings as they are not
fatal
- the inline functions are moved to be out of line.
and some other minor refactoring.
v2 -> v3
- Added Matt and Sujaritha's r-b for patch 1 and 2.
- Reworded the commit of patch 2 to underline the fact that the
interface is useful also when used manually.
v1 -> v2
- fixed a couple of coding style issues in patch 2.
Andi Shyti (5):
drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
drm/i915/gt: add gt_is_root() helper
drm/i915/gt: create per-tile sysfs interface
drm/i915/gt: Create per-tile RC6 sysfs interface
drm/i915/gt: Create per-tile RPS sysfs interfaces
Sujaritha Sundaresan (1):
drm/i915/gt: Add sysfs throttle frequency interfaces
Tvrtko Ursulin (1):
drm/i915: Prepare for multiple GTs
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
.../drm/i915/display/intel_plane_initial.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_dmabuf.c | 6 +-
.../drm/i915/gem/selftests/i915_gem_migrate.c | 8 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 135 +++-
drivers/gpu/drm/i915/gt/intel_gt.h | 22 +-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 122 ++++
drivers/gpu/drm/i915/gt/intel_gt_sysfs.h | 34 +
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 601 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h | 15 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
drivers/gpu/drm/i915/gt/intel_rps.c | 18 +
drivers/gpu/drm/i915/gt/intel_rps.h | 4 +
drivers/gpu/drm/i915/i915_driver.c | 28 +-
drivers/gpu/drm/i915/i915_drv.h | 8 +
drivers/gpu/drm/i915/i915_reg.h | 11 +
drivers/gpu/drm/i915/i915_sysfs.c | 310 +--------
drivers/gpu/drm/i915/i915_sysfs.h | 3 +
drivers/gpu/drm/i915/intel_memory_region.c | 2 +-
drivers/gpu/drm/i915/intel_memory_region.h | 7 +-
drivers/gpu/drm/i915/intel_uncore.c | 11 +-
drivers/gpu/drm/i915/intel_uncore.h | 3 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 13 +-
27 files changed, 1023 insertions(+), 366 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
base-commit: 76874531ffae41683316380bd6d6227bbba12148
--
2.35.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH v7 0/7] Introduce multitile support
@ 2022-03-18 23:39 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Matthew Auld
Hi,
This is the second series that prepares i915 to host multitile
platforms. It introduces the for_each_gt() macro that loops over
the tiles to perform per gt actions.
This patch is a combination of two patches developed originally
by Abdiel, who introduced some refactoring during probe, and then
Tvrtko has added the necessary tools to start using the various
tiles.
The second patch re-organises the sysfs interface to expose the
API for each of the GTs. I decided to prioritise this patch
over others to unblock Sujaritha for further development.
A third series will still follow this.
Thanks Michal and Andrzej for the reviews and support!
Thanks,
Andi
Patchwork: https://patchwork.freedesktop.org/series/98741/
Changelog
=========
v6 -> v7
- fixed a mock selftest error by initializing i915->gt[0]
(thanks Tvrtko!)
- removed spurious file added by mistake (thanks Matt!)
- improved commit log in patch 7 (thanks Suja!)
v5 -> v6
- address all Michal and Andrzej's reviews that consist mainly
in code refactoring.
v4 -> v5
- fixed Michal's reviews.
- the sysfs patches have been split in 3 parts to make reviews
easier.
- Sujaritha's patch on pm throttle has been queued.
- INTEL_REGION_LMEM has been renamed to INTEL_REGION_LMEM_0
- added the gt_is_root() helper
- the sysfs files will be called intel_gt_sysfs_* instead of
sysfs_gt_*
v3 -> v4
- fixed Tvrtko's review:
- remove the SYSFS_DEPRECATED_V2 mention from the commit log
- reworded the error message when accessing deprecated files
- errors in sysfs are printed as warnings as they are not
fatal
- the inline functions are moved to be out of line.
and some other minor refactoring.
v2 -> v3
- Added Matt and Sujaritha's r-b for patch 1 and 2.
- Reworded the commit of patch 2 to underline the fact that the
interface is useful also when used manually.
v1 -> v2
- fixed a couple of coding style issues in patch 2.
Andi Shyti (5):
drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
drm/i915/gt: add gt_is_root() helper
drm/i915/gt: create per-tile sysfs interface
drm/i915/gt: Create per-tile RC6 sysfs interface
drm/i915/gt: Create per-tile RPS sysfs interfaces
Sujaritha Sundaresan (1):
drm/i915/gt: Add sysfs throttle frequency interfaces
Tvrtko Ursulin (1):
drm/i915: Prepare for multiple GTs
drivers/gpu/drm/i915/Makefile | 2 +
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
.../drm/i915/display/intel_plane_initial.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 4 +-
.../drm/i915/gem/selftests/i915_gem_dmabuf.c | 6 +-
.../drm/i915/gem/selftests/i915_gem_migrate.c | 8 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 135 +++-
drivers/gpu/drm/i915/gt/intel_gt.h | 22 +-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 122 ++++
drivers/gpu/drm/i915/gt/intel_gt_sysfs.h | 34 +
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 601 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h | 15 +
drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
drivers/gpu/drm/i915/gt/intel_rps.c | 18 +
drivers/gpu/drm/i915/gt/intel_rps.h | 4 +
drivers/gpu/drm/i915/i915_driver.c | 28 +-
drivers/gpu/drm/i915/i915_drv.h | 8 +
drivers/gpu/drm/i915/i915_reg.h | 11 +
drivers/gpu/drm/i915/i915_sysfs.c | 310 +--------
drivers/gpu/drm/i915/i915_sysfs.h | 3 +
drivers/gpu/drm/i915/intel_memory_region.c | 2 +-
drivers/gpu/drm/i915/intel_memory_region.h | 7 +-
drivers/gpu/drm/i915/intel_uncore.c | 11 +-
drivers/gpu/drm/i915/intel_uncore.h | 3 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 13 +-
27 files changed, 1023 insertions(+), 366 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
base-commit: 76874531ffae41683316380bd6d6227bbba12148
--
2.35.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v7 1/7] drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
@ 2022-03-18 23:39 ` Andi Shyti
-1 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Abdiel Janulgue, Andi Shyti, Tvrtko Ursulin, Lucas De Marchi,
Chris Wilson, Daniele Ceraolo Spurio, Matthew Auld, Andi Shyti,
Sujaritha Sundaresan, Dale B Stimson, Michal Wajdeczko
With the upcoming multitile support each tile will have its own
local memory. Mark the current LMEM with the suffix '0' to
emphasise that it belongs to the root tile.
Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 4 ++--
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 6 +++---
drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c | 8 ++++----
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/intel_memory_region.c | 2 +-
drivers/gpu/drm/i915/intel_memory_region.h | 4 ++--
9 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 94c57facbb463..e9ad142ac40fa 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -1994,7 +1994,7 @@ intel_user_framebuffer_create(struct drm_device *dev,
/* object is backed with LMEM for discrete */
i915 = to_i915(obj->base.dev);
- if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM)) {
+ if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM_0)) {
/* object is "remote", not in local memory */
i915_gem_object_put(obj);
return ERR_PTR(-EREMOTE);
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index a307b4993bcf3..bd6e7c98e751d 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -140,7 +140,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
if (!ret && phys_cursor)
ret = i915_gem_object_attach_phys(obj, alignment);
else if (!ret && HAS_LMEM(dev_priv))
- ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM);
+ ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0);
/* TODO: Do we need to sync when migration becomes async? */
if (!ret)
ret = i915_gem_object_pin_pages(obj);
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 7979929bb6323..d10f27d0b7b09 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -72,7 +72,7 @@ initial_plane_vma(struct drm_i915_private *i915,
}
phys_base = pte & I915_GTT_PAGE_MASK;
- mem = i915->mm.regions[INTEL_REGION_LMEM];
+ mem = i915->mm.regions[INTEL_REGION_LMEM_0];
/*
* We don't currently expect this to ever be placed in the
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index ede084f36ca93..b2aaf620741e3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -102,7 +102,7 @@ __i915_gem_object_create_lmem_with_ps(struct drm_i915_private *i915,
resource_size_t page_size,
unsigned int flags)
{
- return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM],
+ return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM_0],
size, page_size, flags);
}
@@ -137,6 +137,6 @@ i915_gem_object_create_lmem(struct drm_i915_private *i915,
resource_size_t size,
unsigned int flags)
{
- return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM],
+ return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM_0],
size, 0, flags);
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
index b071a58dd6daa..a342fd387d4ef 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
@@ -88,7 +88,7 @@ static int igt_dmabuf_import_self(void *arg)
static int igt_dmabuf_import_same_driver_lmem(void *arg)
{
struct drm_i915_private *i915 = arg;
- struct intel_memory_region *lmem = i915->mm.regions[INTEL_REGION_LMEM];
+ struct intel_memory_region *lmem = i915->mm.regions[INTEL_REGION_LMEM_0];
struct drm_i915_gem_object *obj;
struct drm_gem_object *import;
struct dma_buf *dmabuf;
@@ -252,10 +252,10 @@ static int igt_dmabuf_import_same_driver_lmem_smem(void *arg)
struct drm_i915_private *i915 = arg;
struct intel_memory_region *regions[2];
- if (!i915->mm.regions[INTEL_REGION_LMEM])
+ if (!i915->mm.regions[INTEL_REGION_LMEM_0])
return 0;
- regions[0] = i915->mm.regions[INTEL_REGION_LMEM];
+ regions[0] = i915->mm.regions[INTEL_REGION_LMEM_0];
regions[1] = i915->mm.regions[INTEL_REGION_SMEM];
return igt_dmabuf_import_same_driver(i915, regions, 2);
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
index d534141b2cf7c..2c63daf932de7 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
@@ -92,17 +92,17 @@ static int igt_create_migrate(struct intel_gt *gt, enum intel_region_id src,
static int igt_smem_create_migrate(void *arg)
{
- return igt_create_migrate(arg, INTEL_REGION_LMEM, INTEL_REGION_SMEM);
+ return igt_create_migrate(arg, INTEL_REGION_LMEM_0, INTEL_REGION_SMEM);
}
static int igt_lmem_create_migrate(void *arg)
{
- return igt_create_migrate(arg, INTEL_REGION_SMEM, INTEL_REGION_LMEM);
+ return igt_create_migrate(arg, INTEL_REGION_SMEM, INTEL_REGION_LMEM_0);
}
static int igt_same_create_migrate(void *arg)
{
- return igt_create_migrate(arg, INTEL_REGION_LMEM, INTEL_REGION_LMEM);
+ return igt_create_migrate(arg, INTEL_REGION_LMEM_0, INTEL_REGION_LMEM_0);
}
static int lmem_pages_migrate_one(struct i915_gem_ww_ctx *ww,
@@ -152,7 +152,7 @@ static int lmem_pages_migrate_one(struct i915_gem_ww_ctx *ww,
}
} else {
- err = i915_gem_object_migrate(obj, ww, INTEL_REGION_LMEM);
+ err = i915_gem_object_migrate(obj, ww, INTEL_REGION_LMEM_0);
if (err) {
pr_err("Object failed migration to lmem\n");
if (err)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 57ca1e6b6203d..ca875ba3e2a9d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -76,7 +76,7 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return err;
}
- id = INTEL_REGION_LMEM;
+ id = INTEL_REGION_LMEM_0;
mem->id = id;
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index ded78b83e0b55..e38d2db1c3e32 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -19,7 +19,7 @@ static const struct {
.class = INTEL_MEMORY_SYSTEM,
.instance = 0,
},
- [INTEL_REGION_LMEM] = {
+ [INTEL_REGION_LMEM_0] = {
.class = INTEL_MEMORY_LOCAL,
.instance = 0,
},
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index beded40c6d71c..cc7078bcbfbfc 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -29,14 +29,14 @@ enum intel_memory_type {
enum intel_region_id {
INTEL_REGION_SMEM = 0,
- INTEL_REGION_LMEM,
+ INTEL_REGION_LMEM_0,
INTEL_REGION_STOLEN_SMEM,
INTEL_REGION_STOLEN_LMEM,
INTEL_REGION_UNKNOWN, /* Should be last */
};
#define REGION_SMEM BIT(INTEL_REGION_SMEM)
-#define REGION_LMEM BIT(INTEL_REGION_LMEM)
+#define REGION_LMEM BIT(INTEL_REGION_LMEM_0)
#define REGION_STOLEN_SMEM BIT(INTEL_REGION_STOLEN_SMEM)
#define REGION_STOLEN_LMEM BIT(INTEL_REGION_STOLEN_LMEM)
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH v7 1/7] drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
@ 2022-03-18 23:39 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Matthew Auld
With the upcoming multitile support each tile will have its own
local memory. Mark the current LMEM with the suffix '0' to
emphasise that it belongs to the root tile.
Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/display/intel_fb.c | 2 +-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +-
drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 4 ++--
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 6 +++---
drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c | 8 ++++----
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/intel_memory_region.c | 2 +-
drivers/gpu/drm/i915/intel_memory_region.h | 4 ++--
9 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 94c57facbb463..e9ad142ac40fa 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -1994,7 +1994,7 @@ intel_user_framebuffer_create(struct drm_device *dev,
/* object is backed with LMEM for discrete */
i915 = to_i915(obj->base.dev);
- if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM)) {
+ if (HAS_LMEM(i915) && !i915_gem_object_can_migrate(obj, INTEL_REGION_LMEM_0)) {
/* object is "remote", not in local memory */
i915_gem_object_put(obj);
return ERR_PTR(-EREMOTE);
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index a307b4993bcf3..bd6e7c98e751d 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -140,7 +140,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
if (!ret && phys_cursor)
ret = i915_gem_object_attach_phys(obj, alignment);
else if (!ret && HAS_LMEM(dev_priv))
- ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM);
+ ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0);
/* TODO: Do we need to sync when migration becomes async? */
if (!ret)
ret = i915_gem_object_pin_pages(obj);
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 7979929bb6323..d10f27d0b7b09 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -72,7 +72,7 @@ initial_plane_vma(struct drm_i915_private *i915,
}
phys_base = pte & I915_GTT_PAGE_MASK;
- mem = i915->mm.regions[INTEL_REGION_LMEM];
+ mem = i915->mm.regions[INTEL_REGION_LMEM_0];
/*
* We don't currently expect this to ever be placed in the
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index ede084f36ca93..b2aaf620741e3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -102,7 +102,7 @@ __i915_gem_object_create_lmem_with_ps(struct drm_i915_private *i915,
resource_size_t page_size,
unsigned int flags)
{
- return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM],
+ return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM_0],
size, page_size, flags);
}
@@ -137,6 +137,6 @@ i915_gem_object_create_lmem(struct drm_i915_private *i915,
resource_size_t size,
unsigned int flags)
{
- return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM],
+ return i915_gem_object_create_region(i915->mm.regions[INTEL_REGION_LMEM_0],
size, 0, flags);
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
index b071a58dd6daa..a342fd387d4ef 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c
@@ -88,7 +88,7 @@ static int igt_dmabuf_import_self(void *arg)
static int igt_dmabuf_import_same_driver_lmem(void *arg)
{
struct drm_i915_private *i915 = arg;
- struct intel_memory_region *lmem = i915->mm.regions[INTEL_REGION_LMEM];
+ struct intel_memory_region *lmem = i915->mm.regions[INTEL_REGION_LMEM_0];
struct drm_i915_gem_object *obj;
struct drm_gem_object *import;
struct dma_buf *dmabuf;
@@ -252,10 +252,10 @@ static int igt_dmabuf_import_same_driver_lmem_smem(void *arg)
struct drm_i915_private *i915 = arg;
struct intel_memory_region *regions[2];
- if (!i915->mm.regions[INTEL_REGION_LMEM])
+ if (!i915->mm.regions[INTEL_REGION_LMEM_0])
return 0;
- regions[0] = i915->mm.regions[INTEL_REGION_LMEM];
+ regions[0] = i915->mm.regions[INTEL_REGION_LMEM_0];
regions[1] = i915->mm.regions[INTEL_REGION_SMEM];
return igt_dmabuf_import_same_driver(i915, regions, 2);
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
index d534141b2cf7c..2c63daf932de7 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_migrate.c
@@ -92,17 +92,17 @@ static int igt_create_migrate(struct intel_gt *gt, enum intel_region_id src,
static int igt_smem_create_migrate(void *arg)
{
- return igt_create_migrate(arg, INTEL_REGION_LMEM, INTEL_REGION_SMEM);
+ return igt_create_migrate(arg, INTEL_REGION_LMEM_0, INTEL_REGION_SMEM);
}
static int igt_lmem_create_migrate(void *arg)
{
- return igt_create_migrate(arg, INTEL_REGION_SMEM, INTEL_REGION_LMEM);
+ return igt_create_migrate(arg, INTEL_REGION_SMEM, INTEL_REGION_LMEM_0);
}
static int igt_same_create_migrate(void *arg)
{
- return igt_create_migrate(arg, INTEL_REGION_LMEM, INTEL_REGION_LMEM);
+ return igt_create_migrate(arg, INTEL_REGION_LMEM_0, INTEL_REGION_LMEM_0);
}
static int lmem_pages_migrate_one(struct i915_gem_ww_ctx *ww,
@@ -152,7 +152,7 @@ static int lmem_pages_migrate_one(struct i915_gem_ww_ctx *ww,
}
} else {
- err = i915_gem_object_migrate(obj, ww, INTEL_REGION_LMEM);
+ err = i915_gem_object_migrate(obj, ww, INTEL_REGION_LMEM_0);
if (err) {
pr_err("Object failed migration to lmem\n");
if (err)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 57ca1e6b6203d..ca875ba3e2a9d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -76,7 +76,7 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return err;
}
- id = INTEL_REGION_LMEM;
+ id = INTEL_REGION_LMEM_0;
mem->id = id;
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index ded78b83e0b55..e38d2db1c3e32 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -19,7 +19,7 @@ static const struct {
.class = INTEL_MEMORY_SYSTEM,
.instance = 0,
},
- [INTEL_REGION_LMEM] = {
+ [INTEL_REGION_LMEM_0] = {
.class = INTEL_MEMORY_LOCAL,
.instance = 0,
},
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index beded40c6d71c..cc7078bcbfbfc 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -29,14 +29,14 @@ enum intel_memory_type {
enum intel_region_id {
INTEL_REGION_SMEM = 0,
- INTEL_REGION_LMEM,
+ INTEL_REGION_LMEM_0,
INTEL_REGION_STOLEN_SMEM,
INTEL_REGION_STOLEN_LMEM,
INTEL_REGION_UNKNOWN, /* Should be last */
};
#define REGION_SMEM BIT(INTEL_REGION_SMEM)
-#define REGION_LMEM BIT(INTEL_REGION_LMEM)
+#define REGION_LMEM BIT(INTEL_REGION_LMEM_0)
#define REGION_STOLEN_SMEM BIT(INTEL_REGION_STOLEN_SMEM)
#define REGION_STOLEN_LMEM BIT(INTEL_REGION_STOLEN_LMEM)
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v7 2/7] drm/i915/gt: add gt_is_root() helper
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
@ 2022-03-18 23:39 ` Andi Shyti
-1 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Abdiel Janulgue, Andi Shyti, Tvrtko Ursulin, Lucas De Marchi,
Chris Wilson, Daniele Ceraolo Spurio, Matthew Auld, Andi Shyti,
Sujaritha Sundaresan, Dale B Stimson, Michal Wajdeczko
The "gt_is_root(struct intel_gt *gt)" helper return true if the
gt is the root gt, which means that its id is 0. Return false
otherwise.
Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 996f8f3c17b95..ce471aa5c83d7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -19,6 +19,11 @@ struct drm_printer;
##__VA_ARGS__); \
} while (0)
+static inline bool gt_is_root(struct intel_gt *gt)
+{
+ return !gt->info.id;
+}
+
static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
{
return container_of(uc, struct intel_gt, uc);
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH v7 2/7] drm/i915/gt: add gt_is_root() helper
@ 2022-03-18 23:39 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Matthew Auld
The "gt_is_root(struct intel_gt *gt)" helper return true if the
gt is the root gt, which means that its id is 0. Return false
otherwise.
Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index 996f8f3c17b95..ce471aa5c83d7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -19,6 +19,11 @@ struct drm_printer;
##__VA_ARGS__); \
} while (0)
+static inline bool gt_is_root(struct intel_gt *gt)
+{
+ return !gt->info.id;
+}
+
static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
{
return container_of(uc, struct intel_gt, uc);
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
@ 2022-03-18 23:39 ` Andi Shyti
-1 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Abdiel Janulgue, Andi Shyti, Tvrtko Ursulin, Lucas De Marchi,
Chris Wilson, Daniele Ceraolo Spurio, Matthew Auld, Andi Shyti,
Sujaritha Sundaresan, Dale B Stimson, Michal Wajdeczko
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibility
with legacy driver paths. A for_each_gt macro is added to iterate
over the GTs and will be used by upcoming patches that convert
various parts of the driver to be multi-gt aware.
Only the primary/root tile is initialized for now; the other
tiles will be detected and plugged in by future patches once the
necessary infrastructure is in place to handle them.
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@gmail.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 133 ++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_gt.h | 17 ++-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
drivers/gpu/drm/i915/i915_driver.c | 28 ++--
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/intel_memory_region.h | 3 +
drivers/gpu/drm/i915/intel_uncore.c | 11 +-
drivers/gpu/drm/i915/intel_uncore.h | 3 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 13 +-
10 files changed, 184 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index ca875ba3e2a9d..cfac4a913642e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -29,7 +29,7 @@
#include "intel_uncore.h"
#include "shmem_utils.h"
-void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+static void __intel_gt_init_early(struct intel_gt *gt)
{
spin_lock_init(>->irq_lock);
@@ -51,17 +51,23 @@ void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
intel_rps_init_early(>->rps);
}
-void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+/* Preliminary initialization of Tile 0 */
+void intel_root_gt_init_early(struct drm_i915_private *i915)
{
+ struct intel_gt *gt = to_gt(i915);
+
gt->i915 = i915;
gt->uncore = &i915->uncore;
+
+ __intel_gt_init_early(gt);
}
-int intel_gt_probe_lmem(struct intel_gt *gt)
+static int intel_gt_probe_lmem(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ unsigned int instance = gt->info.id;
+ int id = INTEL_REGION_LMEM_0 + instance;
struct intel_memory_region *mem;
- int id;
int err;
mem = intel_gt_setup_lmem(gt);
@@ -76,9 +82,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return err;
}
- id = INTEL_REGION_LMEM_0;
-
mem->id = id;
+ mem->instance = instance;
intel_memory_region_set_name(mem, "local%u", mem->instance);
@@ -807,16 +812,21 @@ void intel_gt_driver_release(struct intel_gt *gt)
intel_gt_fini_hwconfig(gt);
}
-void intel_gt_driver_late_release(struct intel_gt *gt)
+void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
{
+ struct intel_gt *gt;
+ unsigned int id;
+
/* We need to wait for inflight RCU frees to release their grip */
rcu_barrier();
- intel_uc_driver_late_release(>->uc);
- intel_gt_fini_requests(gt);
- intel_gt_fini_reset(gt);
- intel_gt_fini_timelines(gt);
- intel_engines_free(gt);
+ for_each_gt(gt, i915, id) {
+ intel_uc_driver_late_release(>->uc);
+ intel_gt_fini_requests(gt);
+ intel_gt_fini_reset(gt);
+ intel_gt_fini_timelines(gt);
+ intel_engines_free(gt);
+ }
}
/**
@@ -1013,6 +1023,105 @@ void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
}
}
+static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
+{
+ int ret;
+
+ if (!gt_is_root(gt)) {
+ struct intel_uncore_mmio_debug *mmio_debug;
+ struct intel_uncore *uncore;
+
+ uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
+ if (!uncore)
+ return -ENOMEM;
+
+ mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
+ if (!mmio_debug) {
+ kfree(uncore);
+ return -ENOMEM;
+ }
+
+ gt->uncore = uncore;
+ gt->uncore->debug = mmio_debug;
+
+ __intel_gt_init_early(gt);
+ }
+
+ intel_uncore_init_early(gt->uncore, gt);
+
+ ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
+ if (ret)
+ return ret;
+
+ gt->phys_addr = phys_addr;
+
+ return 0;
+}
+
+static void
+intel_gt_tile_cleanup(struct intel_gt *gt)
+{
+ intel_uncore_cleanup_mmio(gt->uncore);
+
+ if (!gt_is_root(gt)) {
+ kfree(gt->uncore->debug);
+ kfree(gt->uncore);
+ kfree(gt);
+ }
+}
+
+int intel_gt_probe_all(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct intel_gt *gt = &i915->gt0;
+ phys_addr_t phys_addr;
+ unsigned int mmio_bar;
+ int ret;
+
+ mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
+ phys_addr = pci_resource_start(pdev, mmio_bar);
+
+ /*
+ * We always have at least one primary GT on any device
+ * and it has been already initialized early during probe
+ * in i915_driver_probe()
+ */
+ ret = intel_gt_tile_setup(gt, phys_addr);
+ if (ret)
+ return ret;
+
+ i915->gt[0] = gt;
+
+ /* TODO: add more tiles */
+ return 0;
+}
+
+int intel_gt_tiles_init(struct drm_i915_private *i915)
+{
+ struct intel_gt *gt;
+ unsigned int id;
+ int ret;
+
+ for_each_gt(gt, i915, id) {
+ ret = intel_gt_probe_lmem(gt);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+void intel_gt_release_all(struct drm_i915_private *i915)
+{
+ struct intel_gt *gt;
+ unsigned int id;
+
+ for_each_gt(gt, i915, id) {
+ intel_gt_tile_cleanup(gt);
+ i915->gt[id] = NULL;
+ }
+}
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index ce471aa5c83d7..e76168e10a21b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -39,10 +39,8 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
return container_of(huc, struct intel_gt, uc.huc);
}
-void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
-void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
+void intel_root_gt_init_early(struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
-int intel_gt_probe_lmem(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
int __must_check intel_gt_init_hw(struct intel_gt *gt);
int intel_gt_init(struct intel_gt *gt);
@@ -52,7 +50,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt);
void intel_gt_driver_remove(struct intel_gt *gt);
void intel_gt_driver_release(struct intel_gt *gt);
-void intel_gt_driver_late_release(struct intel_gt *gt);
+void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
@@ -97,6 +95,17 @@ u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
bool dump_table);
+
+int intel_gt_probe_all(struct drm_i915_private *i915);
+int intel_gt_tiles_init(struct drm_i915_private *i915);
+void intel_gt_release_all(struct drm_i915_private *i915);
+
+#define for_each_gt(gt__, i915__, id__) \
+ for ((id__) = 0; \
+ (id__) < I915_MAX_GT; \
+ (id__)++) \
+ for_each_if(((gt__) = (i915__)->gt[(id__)]))
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index e4ecc17889d34..eeead40485fbc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -129,7 +129,14 @@ static const struct intel_wakeref_ops wf_ops = {
void intel_gt_pm_init_early(struct intel_gt *gt)
{
- intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
+ /*
+ * We access the runtime_pm structure via gt->i915 here rather than
+ * gt->uncore as we do elsewhere in the file because gt->uncore is not
+ * yet initialized for all tiles at this point in the driver startup.
+ * runtime_pm is per-device rather than per-tile, so this is still the
+ * correct structure.
+ */
+ intel_wakeref_init(>->wakeref, >->i915->runtime_pm, &wf_ops);
seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index bbba885d45bd5..937b2e1a305ed 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -188,7 +188,14 @@ struct intel_gt {
u8 instanceid;
} default_steering;
+ /*
+ * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT.
+ */
+ phys_addr_t phys_addr;
+
struct intel_gt_info {
+ unsigned int id;
+
intel_engine_mask_t engine_mask;
u32 l3bank_mask;
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 92a625a174e22..64e6f76861f95 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -321,9 +321,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
intel_device_info_subplatform_init(dev_priv);
intel_step_init(dev_priv);
- intel_gt_init_early(to_gt(dev_priv), dev_priv);
intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
- intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv));
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock);
@@ -354,7 +352,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
intel_wopcm_init_early(&dev_priv->wopcm);
- __intel_gt_init_early(to_gt(dev_priv), dev_priv);
+ intel_root_gt_init_early(dev_priv);
i915_gem_init_early(dev_priv);
@@ -375,7 +373,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
err_gem:
i915_gem_cleanup_early(dev_priv);
- intel_gt_driver_late_release(to_gt(dev_priv));
+ intel_gt_driver_late_release_all(dev_priv);
intel_region_ttm_device_fini(dev_priv);
err_ttm:
vlv_suspend_cleanup(dev_priv);
@@ -394,7 +392,7 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv)
intel_irq_fini(dev_priv);
intel_power_domains_cleanup(dev_priv);
i915_gem_cleanup_early(dev_priv);
- intel_gt_driver_late_release(to_gt(dev_priv));
+ intel_gt_driver_late_release_all(dev_priv);
intel_region_ttm_device_fini(dev_priv);
vlv_suspend_cleanup(dev_priv);
i915_workqueues_cleanup(dev_priv);
@@ -425,13 +423,9 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
if (ret < 0)
return ret;
- ret = intel_uncore_setup_mmio(&dev_priv->uncore);
- if (ret < 0)
- goto err_bridge;
-
ret = intel_uncore_init_mmio(&dev_priv->uncore);
if (ret)
- goto err_mmio;
+ return ret;
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
@@ -449,9 +443,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
err_uncore:
intel_teardown_mchbar(dev_priv);
intel_uncore_fini_mmio(&dev_priv->uncore);
-err_mmio:
- intel_uncore_cleanup_mmio(&dev_priv->uncore);
-err_bridge:
pci_dev_put(dev_priv->bridge_dev);
return ret;
@@ -465,7 +456,6 @@ static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
{
intel_teardown_mchbar(dev_priv);
intel_uncore_fini_mmio(&dev_priv->uncore);
- intel_uncore_cleanup_mmio(&dev_priv->uncore);
pci_dev_put(dev_priv->bridge_dev);
}
@@ -598,7 +588,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
if (ret)
goto err_ggtt;
- ret = intel_gt_probe_lmem(to_gt(dev_priv));
+ ret = intel_gt_tiles_init(dev_priv);
if (ret)
goto err_mem_regions;
@@ -849,10 +839,14 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
intel_vgpu_detect(i915);
- ret = i915_driver_mmio_probe(i915);
+ ret = intel_gt_probe_all(i915);
if (ret < 0)
goto out_runtime_pm_put;
+ ret = i915_driver_mmio_probe(i915);
+ if (ret < 0)
+ goto out_tiles_cleanup;
+
ret = i915_driver_hw_probe(i915);
if (ret < 0)
goto out_cleanup_mmio;
@@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
i915_ggtt_driver_late_release(i915);
out_cleanup_mmio:
i915_driver_mmio_release(i915);
+out_tiles_cleanup:
+ intel_gt_release_all(i915);
out_runtime_pm_put:
enable_rpm_wakeref_asserts(&i915->runtime_pm);
i915_driver_late_release(i915);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 97622d3ccfc2a..8e4083d413592 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -777,6 +777,12 @@ struct drm_i915_private {
/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
struct intel_gt gt0;
+ /*
+ * i915->gt[0] == &i915->gt0
+ */
+#define I915_MAX_GT 4
+ struct intel_gt *gt[I915_MAX_GT];
+
struct {
struct i915_gem_contexts {
spinlock_t lock; /* locks list */
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index cc7078bcbfbfc..3d8378c1b4478 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -30,6 +30,9 @@ enum intel_memory_type {
enum intel_region_id {
INTEL_REGION_SMEM = 0,
INTEL_REGION_LMEM_0,
+ INTEL_REGION_LMEM_1,
+ INTEL_REGION_LMEM_2,
+ INTEL_REGION_LMEM_3,
INTEL_REGION_STOLEN_SMEM,
INTEL_REGION_STOLEN_LMEM,
INTEL_REGION_UNKNOWN, /* Should be last */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index ef8ffc01ad19c..8b9caaaacc21f 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2039,14 +2039,11 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
return NOTIFY_OK;
}
-int intel_uncore_setup_mmio(struct intel_uncore *uncore)
+int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
{
struct drm_i915_private *i915 = uncore->i915;
- struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
- int mmio_bar;
int mmio_size;
- mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
/*
* Before gen4, the registers and the GTT are behind different BARs.
* However, from gen4 onwards, the registers and the GTT are shared
@@ -2063,7 +2060,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
else
mmio_size = 2 * 1024 * 1024;
- uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
+ uncore->regs = ioremap(phys_addr, mmio_size);
if (uncore->regs == NULL) {
drm_err(&i915->drm, "failed to map registers\n");
return -EIO;
@@ -2074,9 +2071,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
{
- struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
-
- pci_iounmap(pdev, uncore->regs);
+ iounmap(uncore->regs);
}
void intel_uncore_init_early(struct intel_uncore *uncore,
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 9a760952d46af..52fe3d89dd2b8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -29,6 +29,7 @@
#include <linux/notifier.h>
#include <linux/hrtimer.h>
#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/types.h>
#include "i915_reg_defs.h"
@@ -221,7 +222,7 @@ void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
void intel_uncore_init_early(struct intel_uncore *uncore,
struct intel_gt *gt);
-int intel_uncore_setup_mmio(struct intel_uncore *uncore);
+int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
int intel_uncore_init_mmio(struct intel_uncore *uncore);
void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 573d9b2e1a4a3..9c31a16f83800 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -73,7 +73,7 @@ static void mock_device_release(struct drm_device *dev)
destroy_workqueue(i915->wq);
intel_region_ttm_device_fini(i915);
- intel_gt_driver_late_release(to_gt(i915));
+ intel_gt_driver_late_release_all(i915);
intel_memory_regions_driver_release(i915);
drm_mode_config_cleanup(&i915->drm);
@@ -112,6 +112,11 @@ static struct dev_pm_domain pm_domain = {
},
};
+static void mock_gt_probe(struct drm_i915_private *i915)
+{
+ i915->gt[0] = &i915->gt0;
+}
+
struct drm_i915_private *mock_gem_device(void)
{
#if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU)
@@ -180,11 +185,11 @@ struct drm_i915_private *mock_gem_device(void)
spin_lock_init(&i915->gpu_error.lock);
i915_gem_init__mm(i915);
- intel_gt_init_early(to_gt(i915), i915);
- __intel_gt_init_early(to_gt(i915), i915);
+ intel_root_gt_init_early(i915);
mock_uncore_init(&i915->uncore, i915);
atomic_inc(&to_gt(i915)->wakeref.count); /* disable; no hw support */
to_gt(i915)->awake = -ENODEV;
+ mock_gt_probe(i915);
ret = intel_region_ttm_device_init(i915);
if (ret)
@@ -229,7 +234,7 @@ struct drm_i915_private *mock_gem_device(void)
err_drv:
intel_region_ttm_device_fini(i915);
err_ttm:
- intel_gt_driver_late_release(to_gt(i915));
+ intel_gt_driver_late_release_all(i915);
intel_memory_regions_driver_release(i915);
drm_mode_config_cleanup(&i915->drm);
mock_destroy_device(i915);
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
@ 2022-03-18 23:39 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Matthew Auld
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four GTs are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibility
with legacy driver paths. A for_each_gt macro is added to iterate
over the GTs and will be used by upcoming patches that convert
various parts of the driver to be multi-gt aware.
Only the primary/root tile is initialized for now; the other
tiles will be detected and plugged in by future patches once the
necessary infrastructure is in place to handle them.
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@gmail.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 133 ++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_gt.h | 17 ++-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
drivers/gpu/drm/i915/i915_driver.c | 28 ++--
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/intel_memory_region.h | 3 +
drivers/gpu/drm/i915/intel_uncore.c | 11 +-
drivers/gpu/drm/i915/intel_uncore.h | 3 +-
.../gpu/drm/i915/selftests/mock_gem_device.c | 13 +-
10 files changed, 184 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index ca875ba3e2a9d..cfac4a913642e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -29,7 +29,7 @@
#include "intel_uncore.h"
#include "shmem_utils.h"
-void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+static void __intel_gt_init_early(struct intel_gt *gt)
{
spin_lock_init(>->irq_lock);
@@ -51,17 +51,23 @@ void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
intel_rps_init_early(>->rps);
}
-void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
+/* Preliminary initialization of Tile 0 */
+void intel_root_gt_init_early(struct drm_i915_private *i915)
{
+ struct intel_gt *gt = to_gt(i915);
+
gt->i915 = i915;
gt->uncore = &i915->uncore;
+
+ __intel_gt_init_early(gt);
}
-int intel_gt_probe_lmem(struct intel_gt *gt)
+static int intel_gt_probe_lmem(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ unsigned int instance = gt->info.id;
+ int id = INTEL_REGION_LMEM_0 + instance;
struct intel_memory_region *mem;
- int id;
int err;
mem = intel_gt_setup_lmem(gt);
@@ -76,9 +82,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
return err;
}
- id = INTEL_REGION_LMEM_0;
-
mem->id = id;
+ mem->instance = instance;
intel_memory_region_set_name(mem, "local%u", mem->instance);
@@ -807,16 +812,21 @@ void intel_gt_driver_release(struct intel_gt *gt)
intel_gt_fini_hwconfig(gt);
}
-void intel_gt_driver_late_release(struct intel_gt *gt)
+void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
{
+ struct intel_gt *gt;
+ unsigned int id;
+
/* We need to wait for inflight RCU frees to release their grip */
rcu_barrier();
- intel_uc_driver_late_release(>->uc);
- intel_gt_fini_requests(gt);
- intel_gt_fini_reset(gt);
- intel_gt_fini_timelines(gt);
- intel_engines_free(gt);
+ for_each_gt(gt, i915, id) {
+ intel_uc_driver_late_release(>->uc);
+ intel_gt_fini_requests(gt);
+ intel_gt_fini_reset(gt);
+ intel_gt_fini_timelines(gt);
+ intel_engines_free(gt);
+ }
}
/**
@@ -1013,6 +1023,105 @@ void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
}
}
+static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
+{
+ int ret;
+
+ if (!gt_is_root(gt)) {
+ struct intel_uncore_mmio_debug *mmio_debug;
+ struct intel_uncore *uncore;
+
+ uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
+ if (!uncore)
+ return -ENOMEM;
+
+ mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
+ if (!mmio_debug) {
+ kfree(uncore);
+ return -ENOMEM;
+ }
+
+ gt->uncore = uncore;
+ gt->uncore->debug = mmio_debug;
+
+ __intel_gt_init_early(gt);
+ }
+
+ intel_uncore_init_early(gt->uncore, gt);
+
+ ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
+ if (ret)
+ return ret;
+
+ gt->phys_addr = phys_addr;
+
+ return 0;
+}
+
+static void
+intel_gt_tile_cleanup(struct intel_gt *gt)
+{
+ intel_uncore_cleanup_mmio(gt->uncore);
+
+ if (!gt_is_root(gt)) {
+ kfree(gt->uncore->debug);
+ kfree(gt->uncore);
+ kfree(gt);
+ }
+}
+
+int intel_gt_probe_all(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct intel_gt *gt = &i915->gt0;
+ phys_addr_t phys_addr;
+ unsigned int mmio_bar;
+ int ret;
+
+ mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
+ phys_addr = pci_resource_start(pdev, mmio_bar);
+
+ /*
+ * We always have at least one primary GT on any device
+ * and it has been already initialized early during probe
+ * in i915_driver_probe()
+ */
+ ret = intel_gt_tile_setup(gt, phys_addr);
+ if (ret)
+ return ret;
+
+ i915->gt[0] = gt;
+
+ /* TODO: add more tiles */
+ return 0;
+}
+
+int intel_gt_tiles_init(struct drm_i915_private *i915)
+{
+ struct intel_gt *gt;
+ unsigned int id;
+ int ret;
+
+ for_each_gt(gt, i915, id) {
+ ret = intel_gt_probe_lmem(gt);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+void intel_gt_release_all(struct drm_i915_private *i915)
+{
+ struct intel_gt *gt;
+ unsigned int id;
+
+ for_each_gt(gt, i915, id) {
+ intel_gt_tile_cleanup(gt);
+ i915->gt[id] = NULL;
+ }
+}
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index ce471aa5c83d7..e76168e10a21b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -39,10 +39,8 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
return container_of(huc, struct intel_gt, uc.huc);
}
-void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
-void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
+void intel_root_gt_init_early(struct drm_i915_private *i915);
int intel_gt_assign_ggtt(struct intel_gt *gt);
-int intel_gt_probe_lmem(struct intel_gt *gt);
int intel_gt_init_mmio(struct intel_gt *gt);
int __must_check intel_gt_init_hw(struct intel_gt *gt);
int intel_gt_init(struct intel_gt *gt);
@@ -52,7 +50,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt);
void intel_gt_driver_remove(struct intel_gt *gt);
void intel_gt_driver_release(struct intel_gt *gt);
-void intel_gt_driver_late_release(struct intel_gt *gt);
+void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
@@ -97,6 +95,17 @@ u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
bool dump_table);
+
+int intel_gt_probe_all(struct drm_i915_private *i915);
+int intel_gt_tiles_init(struct drm_i915_private *i915);
+void intel_gt_release_all(struct drm_i915_private *i915);
+
+#define for_each_gt(gt__, i915__, id__) \
+ for ((id__) = 0; \
+ (id__) < I915_MAX_GT; \
+ (id__)++) \
+ for_each_if(((gt__) = (i915__)->gt[(id__)]))
+
void intel_gt_info_print(const struct intel_gt_info *info,
struct drm_printer *p);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index e4ecc17889d34..eeead40485fbc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -129,7 +129,14 @@ static const struct intel_wakeref_ops wf_ops = {
void intel_gt_pm_init_early(struct intel_gt *gt)
{
- intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
+ /*
+ * We access the runtime_pm structure via gt->i915 here rather than
+ * gt->uncore as we do elsewhere in the file because gt->uncore is not
+ * yet initialized for all tiles at this point in the driver startup.
+ * runtime_pm is per-device rather than per-tile, so this is still the
+ * correct structure.
+ */
+ intel_wakeref_init(>->wakeref, >->i915->runtime_pm, &wf_ops);
seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index bbba885d45bd5..937b2e1a305ed 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -188,7 +188,14 @@ struct intel_gt {
u8 instanceid;
} default_steering;
+ /*
+ * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT.
+ */
+ phys_addr_t phys_addr;
+
struct intel_gt_info {
+ unsigned int id;
+
intel_engine_mask_t engine_mask;
u32 l3bank_mask;
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 92a625a174e22..64e6f76861f95 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -321,9 +321,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
intel_device_info_subplatform_init(dev_priv);
intel_step_init(dev_priv);
- intel_gt_init_early(to_gt(dev_priv), dev_priv);
intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
- intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv));
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock);
@@ -354,7 +352,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
intel_wopcm_init_early(&dev_priv->wopcm);
- __intel_gt_init_early(to_gt(dev_priv), dev_priv);
+ intel_root_gt_init_early(dev_priv);
i915_gem_init_early(dev_priv);
@@ -375,7 +373,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
err_gem:
i915_gem_cleanup_early(dev_priv);
- intel_gt_driver_late_release(to_gt(dev_priv));
+ intel_gt_driver_late_release_all(dev_priv);
intel_region_ttm_device_fini(dev_priv);
err_ttm:
vlv_suspend_cleanup(dev_priv);
@@ -394,7 +392,7 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv)
intel_irq_fini(dev_priv);
intel_power_domains_cleanup(dev_priv);
i915_gem_cleanup_early(dev_priv);
- intel_gt_driver_late_release(to_gt(dev_priv));
+ intel_gt_driver_late_release_all(dev_priv);
intel_region_ttm_device_fini(dev_priv);
vlv_suspend_cleanup(dev_priv);
i915_workqueues_cleanup(dev_priv);
@@ -425,13 +423,9 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
if (ret < 0)
return ret;
- ret = intel_uncore_setup_mmio(&dev_priv->uncore);
- if (ret < 0)
- goto err_bridge;
-
ret = intel_uncore_init_mmio(&dev_priv->uncore);
if (ret)
- goto err_mmio;
+ return ret;
/* Try to make sure MCHBAR is enabled before poking at it */
intel_setup_mchbar(dev_priv);
@@ -449,9 +443,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
err_uncore:
intel_teardown_mchbar(dev_priv);
intel_uncore_fini_mmio(&dev_priv->uncore);
-err_mmio:
- intel_uncore_cleanup_mmio(&dev_priv->uncore);
-err_bridge:
pci_dev_put(dev_priv->bridge_dev);
return ret;
@@ -465,7 +456,6 @@ static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
{
intel_teardown_mchbar(dev_priv);
intel_uncore_fini_mmio(&dev_priv->uncore);
- intel_uncore_cleanup_mmio(&dev_priv->uncore);
pci_dev_put(dev_priv->bridge_dev);
}
@@ -598,7 +588,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
if (ret)
goto err_ggtt;
- ret = intel_gt_probe_lmem(to_gt(dev_priv));
+ ret = intel_gt_tiles_init(dev_priv);
if (ret)
goto err_mem_regions;
@@ -849,10 +839,14 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
intel_vgpu_detect(i915);
- ret = i915_driver_mmio_probe(i915);
+ ret = intel_gt_probe_all(i915);
if (ret < 0)
goto out_runtime_pm_put;
+ ret = i915_driver_mmio_probe(i915);
+ if (ret < 0)
+ goto out_tiles_cleanup;
+
ret = i915_driver_hw_probe(i915);
if (ret < 0)
goto out_cleanup_mmio;
@@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
i915_ggtt_driver_late_release(i915);
out_cleanup_mmio:
i915_driver_mmio_release(i915);
+out_tiles_cleanup:
+ intel_gt_release_all(i915);
out_runtime_pm_put:
enable_rpm_wakeref_asserts(&i915->runtime_pm);
i915_driver_late_release(i915);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 97622d3ccfc2a..8e4083d413592 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -777,6 +777,12 @@ struct drm_i915_private {
/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
struct intel_gt gt0;
+ /*
+ * i915->gt[0] == &i915->gt0
+ */
+#define I915_MAX_GT 4
+ struct intel_gt *gt[I915_MAX_GT];
+
struct {
struct i915_gem_contexts {
spinlock_t lock; /* locks list */
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index cc7078bcbfbfc..3d8378c1b4478 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -30,6 +30,9 @@ enum intel_memory_type {
enum intel_region_id {
INTEL_REGION_SMEM = 0,
INTEL_REGION_LMEM_0,
+ INTEL_REGION_LMEM_1,
+ INTEL_REGION_LMEM_2,
+ INTEL_REGION_LMEM_3,
INTEL_REGION_STOLEN_SMEM,
INTEL_REGION_STOLEN_LMEM,
INTEL_REGION_UNKNOWN, /* Should be last */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index ef8ffc01ad19c..8b9caaaacc21f 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -2039,14 +2039,11 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
return NOTIFY_OK;
}
-int intel_uncore_setup_mmio(struct intel_uncore *uncore)
+int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
{
struct drm_i915_private *i915 = uncore->i915;
- struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
- int mmio_bar;
int mmio_size;
- mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
/*
* Before gen4, the registers and the GTT are behind different BARs.
* However, from gen4 onwards, the registers and the GTT are shared
@@ -2063,7 +2060,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
else
mmio_size = 2 * 1024 * 1024;
- uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
+ uncore->regs = ioremap(phys_addr, mmio_size);
if (uncore->regs == NULL) {
drm_err(&i915->drm, "failed to map registers\n");
return -EIO;
@@ -2074,9 +2071,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
{
- struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
-
- pci_iounmap(pdev, uncore->regs);
+ iounmap(uncore->regs);
}
void intel_uncore_init_early(struct intel_uncore *uncore,
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index 9a760952d46af..52fe3d89dd2b8 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -29,6 +29,7 @@
#include <linux/notifier.h>
#include <linux/hrtimer.h>
#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/types.h>
#include "i915_reg_defs.h"
@@ -221,7 +222,7 @@ void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
void intel_uncore_init_early(struct intel_uncore *uncore,
struct intel_gt *gt);
-int intel_uncore_setup_mmio(struct intel_uncore *uncore);
+int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
int intel_uncore_init_mmio(struct intel_uncore *uncore);
void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
struct intel_gt *gt);
diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
index 573d9b2e1a4a3..9c31a16f83800 100644
--- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
+++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
@@ -73,7 +73,7 @@ static void mock_device_release(struct drm_device *dev)
destroy_workqueue(i915->wq);
intel_region_ttm_device_fini(i915);
- intel_gt_driver_late_release(to_gt(i915));
+ intel_gt_driver_late_release_all(i915);
intel_memory_regions_driver_release(i915);
drm_mode_config_cleanup(&i915->drm);
@@ -112,6 +112,11 @@ static struct dev_pm_domain pm_domain = {
},
};
+static void mock_gt_probe(struct drm_i915_private *i915)
+{
+ i915->gt[0] = &i915->gt0;
+}
+
struct drm_i915_private *mock_gem_device(void)
{
#if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU)
@@ -180,11 +185,11 @@ struct drm_i915_private *mock_gem_device(void)
spin_lock_init(&i915->gpu_error.lock);
i915_gem_init__mm(i915);
- intel_gt_init_early(to_gt(i915), i915);
- __intel_gt_init_early(to_gt(i915), i915);
+ intel_root_gt_init_early(i915);
mock_uncore_init(&i915->uncore, i915);
atomic_inc(&to_gt(i915)->wakeref.count); /* disable; no hw support */
to_gt(i915)->awake = -ENODEV;
+ mock_gt_probe(i915);
ret = intel_region_ttm_device_init(i915);
if (ret)
@@ -229,7 +234,7 @@ struct drm_i915_private *mock_gem_device(void)
err_drv:
intel_region_ttm_device_fini(i915);
err_ttm:
- intel_gt_driver_late_release(to_gt(i915));
+ intel_gt_driver_late_release_all(i915);
intel_memory_regions_driver_release(i915);
drm_mode_config_cleanup(&i915->drm);
mock_destroy_device(i915);
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v7 4/7] drm/i915/gt: create per-tile sysfs interface
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
@ 2022-03-18 23:39 ` Andi Shyti
-1 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Abdiel Janulgue, Andi Shyti, Tvrtko Ursulin, Lucas De Marchi,
Chris Wilson, Daniele Ceraolo Spurio, Matthew Auld, Andi Shyti,
Sujaritha Sundaresan, Dale B Stimson, Michal Wajdeczko
Now that we have tiles we want each of them to have its own
interface. A directory "gt/" is created under "cardN/" that will
contain as many diroctories as the tiles.
In the coming patches tile related interfaces will be added. For
now the sysfs gt structure simply has an id interface related
to the current tile count.
The directory structure will follow this scheme:
/sys/.../card0
└── gt
├── gt0
│ └── id
:
:
└─- gtN
└── id
This new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +
drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 103 +++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_sysfs.h | 34 ++++++++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_sysfs.c | 7 +-
drivers/gpu/drm/i915/i915_sysfs.h | 3 +
7 files changed, 151 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a54e84e054660..29523848396e4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -105,6 +105,7 @@ gt-y += \
gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
gt/intel_gt_requests.o \
+ gt/intel_gt_sysfs.o \
gt/intel_gtt.o \
gt/intel_llc.o \
gt/intel_lrc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index cfac4a913642e..5001a6168d566 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -26,6 +26,7 @@
#include "intel_rc6.h"
#include "intel_renderstate.h"
#include "intel_rps.h"
+#include "intel_gt_sysfs.h"
#include "intel_uncore.h"
#include "shmem_utils.h"
@@ -458,6 +459,7 @@ void intel_gt_driver_register(struct intel_gt *gt)
intel_rps_driver_register(>->rps);
intel_gt_debugfs_register(gt);
+ intel_gt_sysfs_register(gt);
}
static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
new file mode 100644
index 0000000000000..d508319612944
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <drm/drm_device.h>
+#include <linux/device.h>
+#include <linux/kobject.h>
+#include <linux/printk.h>
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_sysfs.h"
+#include "intel_gt.h"
+#include "intel_gt_sysfs.h"
+#include "intel_gt_types.h"
+#include "intel_rc6.h"
+
+bool is_object_gt(struct kobject *kobj)
+{
+ return !strncmp(kobj->name, "gt", 2);
+}
+
+static struct intel_gt *kobj_to_gt(struct kobject *kobj)
+{
+ return container_of(kobj, struct kobj_gt, base)->gt;
+}
+
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+ const char *name)
+{
+ struct kobject *kobj = &dev->kobj;
+
+ /*
+ * We are interested at knowing from where the interface
+ * has been called, whether it's called from gt/ or from
+ * the parent directory.
+ * From the interface position it depends also the value of
+ * the private data.
+ * If the interface is called from gt/ then private data is
+ * of the "struct intel_gt *" type, otherwise it's * a
+ * "struct drm_i915_private *" type.
+ */
+ if (!is_object_gt(kobj)) {
+ struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
+
+ return to_gt(i915);
+ }
+
+ return kobj_to_gt(kobj);
+}
+
+static ssize_t id_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+
+ return sysfs_emit(buf, "%u\n", gt->info.id);
+}
+static DEVICE_ATTR_RO(id);
+
+static struct attribute *id_attrs[] = {
+ &dev_attr_id.attr,
+ NULL,
+};
+ATTRIBUTE_GROUPS(id);
+
+static void kobj_gt_release(struct kobject *kobj)
+{
+ kfree(kobj);
+}
+
+static struct kobj_type kobj_gt_type = {
+ .release = kobj_gt_release,
+ .sysfs_ops = &kobj_sysfs_ops,
+ .default_groups = id_groups,
+};
+
+void intel_gt_sysfs_register(struct intel_gt *gt)
+{
+ struct kobj_gt *kg;
+
+ kg = kzalloc(sizeof(*kg), GFP_KERNEL);
+ if (!kg)
+ goto exit_fail;
+
+ kobject_init(&kg->base, &kobj_gt_type);
+ kg->gt = gt;
+
+ /* xfer ownership to sysfs tree */
+ if (kobject_add(&kg->base, gt->i915->sysfs_gt, "gt%d", gt->info.id))
+ goto exit_kobj_put;
+
+ return;
+
+exit_kobj_put:
+ kobject_put(&kg->base);
+
+exit_fail:
+ drm_warn(>->i915->drm,
+ "failed to initialize gt%d sysfs root\n", gt->info.id);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
new file mode 100644
index 0000000000000..9471b26752cfc
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __SYSFS_GT_H__
+#define __SYSFS_GT_H__
+
+#include <linux/ctype.h>
+#include <linux/kobject.h>
+
+#include "i915_gem.h" /* GEM_BUG_ON() */
+
+struct intel_gt;
+
+struct kobj_gt {
+ struct kobject base;
+ struct intel_gt *gt;
+};
+
+bool is_object_gt(struct kobject *kobj);
+
+struct drm_i915_private *kobj_to_i915(struct kobject *kobj);
+
+struct kobject *
+intel_gt_create_kobj(struct intel_gt *gt,
+ struct kobject *dir,
+ const char *name);
+
+void intel_gt_sysfs_register(struct intel_gt *gt);
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+ const char *name);
+
+#endif /* SYSFS_GT_H */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8e4083d413592..dc3369188f96f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -783,6 +783,8 @@ struct drm_i915_private {
#define I915_MAX_GT 4
struct intel_gt *gt[I915_MAX_GT];
+ struct kobject *sysfs_gt;
+
struct {
struct i915_gem_contexts {
spinlock_t lock; /* locks list */
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index a4d1759375b9d..5ff915b93c21a 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -39,7 +39,7 @@
#include "i915_sysfs.h"
#include "intel_pm.h"
-static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
+struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
{
struct drm_minor *minor = dev_get_drvdata(kdev);
return to_i915(minor->dev);
@@ -538,6 +538,11 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
if (ret)
drm_err(&dev_priv->drm, "RPS sysfs setup failed\n");
+ dev_priv->sysfs_gt = kobject_create_and_add("gt", &kdev->kobj);
+ if (!dev_priv->sysfs_gt)
+ drm_warn(&dev_priv->drm,
+ "failed to register GT sysfs directory\n");
+
i915_setup_error_capture(kdev);
intel_engines_add_sysfs(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.h b/drivers/gpu/drm/i915/i915_sysfs.h
index 41afd4366416a..243a17741e3f1 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.h
+++ b/drivers/gpu/drm/i915/i915_sysfs.h
@@ -6,8 +6,11 @@
#ifndef __I915_SYSFS_H__
#define __I915_SYSFS_H__
+struct device;
struct drm_i915_private;
+struct drm_i915_private *kdev_minor_to_i915(struct device *kdev);
+
void i915_setup_sysfs(struct drm_i915_private *i915);
void i915_teardown_sysfs(struct drm_i915_private *i915);
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH v7 4/7] drm/i915/gt: create per-tile sysfs interface
@ 2022-03-18 23:39 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Matthew Auld
Now that we have tiles we want each of them to have its own
interface. A directory "gt/" is created under "cardN/" that will
contain as many diroctories as the tiles.
In the coming patches tile related interfaces will be added. For
now the sysfs gt structure simply has an id interface related
to the current tile count.
The directory structure will follow this scheme:
/sys/.../card0
└── gt
├── gt0
│ └── id
:
:
└─- gtN
└── id
This new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +
drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 103 +++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_sysfs.h | 34 ++++++++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/i915_sysfs.c | 7 +-
drivers/gpu/drm/i915/i915_sysfs.h | 3 +
7 files changed, 151 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a54e84e054660..29523848396e4 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -105,6 +105,7 @@ gt-y += \
gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
gt/intel_gt_requests.o \
+ gt/intel_gt_sysfs.o \
gt/intel_gtt.o \
gt/intel_llc.o \
gt/intel_lrc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index cfac4a913642e..5001a6168d566 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -26,6 +26,7 @@
#include "intel_rc6.h"
#include "intel_renderstate.h"
#include "intel_rps.h"
+#include "intel_gt_sysfs.h"
#include "intel_uncore.h"
#include "shmem_utils.h"
@@ -458,6 +459,7 @@ void intel_gt_driver_register(struct intel_gt *gt)
intel_rps_driver_register(>->rps);
intel_gt_debugfs_register(gt);
+ intel_gt_sysfs_register(gt);
}
static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
new file mode 100644
index 0000000000000..d508319612944
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <drm/drm_device.h>
+#include <linux/device.h>
+#include <linux/kobject.h>
+#include <linux/printk.h>
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_sysfs.h"
+#include "intel_gt.h"
+#include "intel_gt_sysfs.h"
+#include "intel_gt_types.h"
+#include "intel_rc6.h"
+
+bool is_object_gt(struct kobject *kobj)
+{
+ return !strncmp(kobj->name, "gt", 2);
+}
+
+static struct intel_gt *kobj_to_gt(struct kobject *kobj)
+{
+ return container_of(kobj, struct kobj_gt, base)->gt;
+}
+
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+ const char *name)
+{
+ struct kobject *kobj = &dev->kobj;
+
+ /*
+ * We are interested at knowing from where the interface
+ * has been called, whether it's called from gt/ or from
+ * the parent directory.
+ * From the interface position it depends also the value of
+ * the private data.
+ * If the interface is called from gt/ then private data is
+ * of the "struct intel_gt *" type, otherwise it's * a
+ * "struct drm_i915_private *" type.
+ */
+ if (!is_object_gt(kobj)) {
+ struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
+
+ return to_gt(i915);
+ }
+
+ return kobj_to_gt(kobj);
+}
+
+static ssize_t id_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+
+ return sysfs_emit(buf, "%u\n", gt->info.id);
+}
+static DEVICE_ATTR_RO(id);
+
+static struct attribute *id_attrs[] = {
+ &dev_attr_id.attr,
+ NULL,
+};
+ATTRIBUTE_GROUPS(id);
+
+static void kobj_gt_release(struct kobject *kobj)
+{
+ kfree(kobj);
+}
+
+static struct kobj_type kobj_gt_type = {
+ .release = kobj_gt_release,
+ .sysfs_ops = &kobj_sysfs_ops,
+ .default_groups = id_groups,
+};
+
+void intel_gt_sysfs_register(struct intel_gt *gt)
+{
+ struct kobj_gt *kg;
+
+ kg = kzalloc(sizeof(*kg), GFP_KERNEL);
+ if (!kg)
+ goto exit_fail;
+
+ kobject_init(&kg->base, &kobj_gt_type);
+ kg->gt = gt;
+
+ /* xfer ownership to sysfs tree */
+ if (kobject_add(&kg->base, gt->i915->sysfs_gt, "gt%d", gt->info.id))
+ goto exit_kobj_put;
+
+ return;
+
+exit_kobj_put:
+ kobject_put(&kg->base);
+
+exit_fail:
+ drm_warn(>->i915->drm,
+ "failed to initialize gt%d sysfs root\n", gt->info.id);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
new file mode 100644
index 0000000000000..9471b26752cfc
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __SYSFS_GT_H__
+#define __SYSFS_GT_H__
+
+#include <linux/ctype.h>
+#include <linux/kobject.h>
+
+#include "i915_gem.h" /* GEM_BUG_ON() */
+
+struct intel_gt;
+
+struct kobj_gt {
+ struct kobject base;
+ struct intel_gt *gt;
+};
+
+bool is_object_gt(struct kobject *kobj);
+
+struct drm_i915_private *kobj_to_i915(struct kobject *kobj);
+
+struct kobject *
+intel_gt_create_kobj(struct intel_gt *gt,
+ struct kobject *dir,
+ const char *name);
+
+void intel_gt_sysfs_register(struct intel_gt *gt);
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+ const char *name);
+
+#endif /* SYSFS_GT_H */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8e4083d413592..dc3369188f96f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -783,6 +783,8 @@ struct drm_i915_private {
#define I915_MAX_GT 4
struct intel_gt *gt[I915_MAX_GT];
+ struct kobject *sysfs_gt;
+
struct {
struct i915_gem_contexts {
spinlock_t lock; /* locks list */
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index a4d1759375b9d..5ff915b93c21a 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -39,7 +39,7 @@
#include "i915_sysfs.h"
#include "intel_pm.h"
-static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
+struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
{
struct drm_minor *minor = dev_get_drvdata(kdev);
return to_i915(minor->dev);
@@ -538,6 +538,11 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
if (ret)
drm_err(&dev_priv->drm, "RPS sysfs setup failed\n");
+ dev_priv->sysfs_gt = kobject_create_and_add("gt", &kdev->kobj);
+ if (!dev_priv->sysfs_gt)
+ drm_warn(&dev_priv->drm,
+ "failed to register GT sysfs directory\n");
+
i915_setup_error_capture(kdev);
intel_engines_add_sysfs(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.h b/drivers/gpu/drm/i915/i915_sysfs.h
index 41afd4366416a..243a17741e3f1 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.h
+++ b/drivers/gpu/drm/i915/i915_sysfs.h
@@ -6,8 +6,11 @@
#ifndef __I915_SYSFS_H__
#define __I915_SYSFS_H__
+struct device;
struct drm_i915_private;
+struct drm_i915_private *kdev_minor_to_i915(struct device *kdev);
+
void i915_setup_sysfs(struct drm_i915_private *i915);
void i915_teardown_sysfs(struct drm_i915_private *i915);
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v7 5/7] drm/i915/gt: Create per-tile RC6 sysfs interface
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
@ 2022-03-18 23:39 ` Andi Shyti
-1 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Abdiel Janulgue, Andi Shyti, Tvrtko Ursulin, Lucas De Marchi,
Chris Wilson, Daniele Ceraolo Spurio, Matthew Auld, Andi Shyti,
Sujaritha Sundaresan, Dale B Stimson, Michal Wajdeczko
Now tiles have their own sysfs interfaces under the gt/
directory. Because RC6 is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│ ├── gt0
│ │ ├── id
│ │ ├── rc6_enable
│ │ ├── rc6_residency_ms
. . .
. . .
. .
│ └── gtN
│ ├── id
│ ├── rc6_enable
│ ├── rc6_residency_ms
│ .
│ .
│
└── power/ -+
├── rc6_enable | Original interface
├── rc6_residency_ms +-> kept as existing ABI;
. | it multiplexes over
. | the GTs
-+
The existing interfaces have been kept in their original location
to preserve the existing ABI. They act on all the GTs: when
reading they provide the average value from all the GTs.
This patch is not really adding exposing new interfaces (new
ABI) other than adapting the existing one to more tiles. In any
case this new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 19 ++
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 244 ++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h | 15 ++
drivers/gpu/drm/i915/i915_sysfs.c | 128 ----------
5 files changed, 279 insertions(+), 128 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 29523848396e4..46af9379803d8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -106,6 +106,7 @@ gt-y += \
gt/intel_gt_pm_irq.o \
gt/intel_gt_requests.o \
gt/intel_gt_sysfs.o \
+ gt/intel_gt_sysfs_pm.o \
gt/intel_gtt.o \
gt/intel_llc.o \
gt/intel_lrc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
index d508319612944..8ec8bc660c8c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
@@ -13,6 +13,7 @@
#include "i915_sysfs.h"
#include "intel_gt.h"
#include "intel_gt_sysfs.h"
+#include "intel_gt_sysfs_pm.h"
#include "intel_gt_types.h"
#include "intel_rc6.h"
@@ -50,6 +51,11 @@ struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
return kobj_to_gt(kobj);
}
+static struct kobject *gt_get_parent_obj(struct intel_gt *gt)
+{
+ return >->i915->drm.primary->kdev->kobj;
+}
+
static ssize_t id_show(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -81,6 +87,17 @@ void intel_gt_sysfs_register(struct intel_gt *gt)
{
struct kobj_gt *kg;
+ /*
+ * We need to make things right with the
+ * ABI compatibility. The files were originally
+ * generated under the parent directory.
+ *
+ * We generate the files only for gt 0
+ * to avoid duplicates.
+ */
+ if (gt_is_root(gt))
+ intel_gt_sysfs_pm_init(gt, gt_get_parent_obj(gt));
+
kg = kzalloc(sizeof(*kg), GFP_KERNEL);
if (!kg)
goto exit_fail;
@@ -92,6 +109,8 @@ void intel_gt_sysfs_register(struct intel_gt *gt)
if (kobject_add(&kg->base, gt->i915->sysfs_gt, "gt%d", gt->info.id))
goto exit_kobj_put;
+ intel_gt_sysfs_pm_init(gt, &kg->base);
+
return;
exit_kobj_put:
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
new file mode 100644
index 0000000000000..144b004e4de82
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <drm/drm_device.h>
+#include <linux/sysfs.h>
+#include <linux/printk.h>
+
+#include "i915_drv.h"
+#include "i915_sysfs.h"
+#include "intel_gt.h"
+#include "intel_gt_regs.h"
+#include "intel_gt_sysfs.h"
+#include "intel_gt_sysfs_pm.h"
+#include "intel_rc6.h"
+
+#ifdef CONFIG_PM
+enum intel_gt_sysfs_op {
+ INTEL_GT_SYSFS_MIN = 0,
+ INTEL_GT_SYSFS_MAX,
+};
+
+static u32
+sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
+ u32 (func)(struct intel_gt *gt),
+ enum intel_gt_sysfs_op op)
+{
+ struct intel_gt *gt;
+ u32 ret;
+
+ ret = (op == INTEL_GT_SYSFS_MAX) ? 0 : (u32) -1;
+
+ if (!is_object_gt(&dev->kobj)) {
+ int i;
+ struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
+
+ for_each_gt(gt, i915, i) {
+ u32 val = func(gt);
+
+ switch (op) {
+ case INTEL_GT_SYSFS_MIN:
+ if (val < ret)
+ ret = val;
+ break;
+
+ case INTEL_GT_SYSFS_MAX:
+ if (val > ret)
+ ret = val;
+ break;
+ }
+ }
+ } else {
+ gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ ret = func(gt);
+ }
+
+ return ret;
+}
+
+/* RC6 interfaces will show the minimum RC6 residency value */
+#define sysfs_gt_attribute_r_min_func(d, a, f) \
+ sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MIN)
+
+#define sysfs_gt_attribute_r_max_func(d, a, f) \
+ sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
+
+static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
+{
+ intel_wakeref_t wakeref;
+ u64 res = 0;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ res = intel_rc6_residency_us(>->rc6, reg);
+
+ return DIV_ROUND_CLOSEST_ULL(res, 1000);
+}
+
+static ssize_t rc6_enable_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ u8 mask = 0;
+
+ if (HAS_RC6(gt->i915))
+ mask |= BIT(0);
+ if (HAS_RC6p(gt->i915))
+ mask |= BIT(1);
+ if (HAS_RC6pp(gt->i915))
+ mask |= BIT(2);
+
+ return sysfs_emit(buff, "%x\n", mask);
+}
+
+static u32 __rc6_residency_ms_show(struct intel_gt *gt)
+{
+ return get_residency(gt, GEN6_GT_GFX_RC6);
+}
+
+static ssize_t rc6_residency_ms_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ u32 rc6_residency = sysfs_gt_attribute_r_min_func(dev, attr,
+ __rc6_residency_ms_show);
+
+ return sysfs_emit(buff, "%u\n", rc6_residency);
+}
+
+static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
+{
+ return get_residency(gt, GEN6_GT_GFX_RC6p);
+}
+
+static ssize_t rc6p_residency_ms_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ u32 rc6p_residency = sysfs_gt_attribute_r_min_func(dev, attr,
+ __rc6p_residency_ms_show);
+
+ return sysfs_emit(buff, "%u\n", rc6p_residency);
+}
+
+static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
+{
+ return get_residency(gt, GEN6_GT_GFX_RC6pp);
+}
+
+static ssize_t rc6pp_residency_ms_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ u32 rc6pp_residency = sysfs_gt_attribute_r_min_func(dev, attr,
+ __rc6pp_residency_ms_show);
+
+ return sysfs_emit(buff, "%u\n", rc6pp_residency);
+}
+
+static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
+{
+ return get_residency(gt, VLV_GT_MEDIA_RC6);
+}
+
+static ssize_t media_rc6_residency_ms_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ u32 rc6_residency = sysfs_gt_attribute_r_min_func(dev, attr,
+ __media_rc6_residency_ms_show);
+
+ return sysfs_emit(buff, "%u\n", rc6_residency);
+}
+
+static DEVICE_ATTR_RO(rc6_enable);
+static DEVICE_ATTR_RO(rc6_residency_ms);
+static DEVICE_ATTR_RO(rc6p_residency_ms);
+static DEVICE_ATTR_RO(rc6pp_residency_ms);
+static DEVICE_ATTR_RO(media_rc6_residency_ms);
+
+static struct attribute *rc6_attrs[] = {
+ &dev_attr_rc6_enable.attr,
+ &dev_attr_rc6_residency_ms.attr,
+ NULL
+};
+
+static struct attribute *rc6p_attrs[] = {
+ &dev_attr_rc6p_residency_ms.attr,
+ &dev_attr_rc6pp_residency_ms.attr,
+ NULL
+};
+
+static struct attribute *media_rc6_attrs[] = {
+ &dev_attr_media_rc6_residency_ms.attr,
+ NULL
+};
+
+static const struct attribute_group rc6_attr_group[] = {
+ { .attrs = rc6_attrs, },
+ { .name = power_group_name, .attrs = rc6_attrs, },
+};
+
+static const struct attribute_group rc6p_attr_group[] = {
+ { .attrs = rc6p_attrs, },
+ { .name = power_group_name, .attrs = rc6p_attrs, },
+};
+
+static const struct attribute_group media_rc6_attr_group[] = {
+ { .attrs = media_rc6_attrs, },
+ { .name = power_group_name, .attrs = media_rc6_attrs, },
+};
+
+static int __intel_gt_sysfs_create_group(struct kobject *kobj,
+ const struct attribute_group *grp)
+{
+ return is_object_gt(kobj) ?
+ sysfs_create_group(kobj, &grp[0]) :
+ sysfs_merge_group(kobj, &grp[1]);
+}
+
+static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
+{
+ int ret;
+
+ if (!HAS_RC6(gt->i915))
+ return;
+
+ ret = __intel_gt_sysfs_create_group(kobj, rc6_attr_group);
+ if (ret)
+ drm_warn(>->i915->drm,
+ "failed to create gt%u RC6 sysfs files (%pe)\n",
+ gt->info.id, ERR_PTR(ret));
+
+ /*
+ * cannot use the is_visible() attribute because
+ * the upper object inherits from the parent group.
+ */
+ if (HAS_RC6p(gt->i915)) {
+ ret = __intel_gt_sysfs_create_group(kobj, rc6p_attr_group);
+ if (ret)
+ drm_warn(>->i915->drm,
+ "failed to create gt%u RC6p sysfs files (%pe)\n",
+ gt->info.id, ERR_PTR(ret));
+ }
+
+ if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
+ ret = __intel_gt_sysfs_create_group(kobj, media_rc6_attr_group);
+ if (ret)
+ drm_warn(>->i915->drm,
+ "failed to create media %u RC6 sysfs files (%pe)\n",
+ gt->info.id, ERR_PTR(ret));
+ }
+}
+#else
+static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
+{
+}
+#endif /* CONFIG_PM */
+
+void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
+{
+ intel_sysfs_rc6_init(gt, kobj);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
new file mode 100644
index 0000000000000..f567105a4a89a
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __SYSFS_GT_PM_H__
+#define __SYSFS_GT_PM_H__
+
+#include <linux/kobject.h>
+
+#include "intel_gt_types.h"
+
+void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj);
+
+#endif /* SYSFS_RC6_H */
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 5ff915b93c21a..2c5d62a521f64 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -45,107 +45,6 @@ struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
return to_i915(minor->dev);
}
-#ifdef CONFIG_PM
-static u32 calc_residency(struct drm_i915_private *dev_priv,
- i915_reg_t reg)
-{
- intel_wakeref_t wakeref;
- u64 res = 0;
-
- with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
- res = intel_rc6_residency_us(&to_gt(dev_priv)->rc6, reg);
-
- return DIV_ROUND_CLOSEST_ULL(res, 1000);
-}
-
-static ssize_t rc6_enable_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- unsigned int mask;
-
- mask = 0;
- if (HAS_RC6(dev_priv))
- mask |= BIT(0);
- if (HAS_RC6p(dev_priv))
- mask |= BIT(1);
- if (HAS_RC6pp(dev_priv))
- mask |= BIT(2);
-
- return sysfs_emit(buf, "%x\n", mask);
-}
-
-static ssize_t rc6_residency_ms_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
- return sysfs_emit(buf, "%u\n", rc6_residency);
-}
-
-static ssize_t rc6p_residency_ms_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
- return sysfs_emit(buf, "%u\n", rc6p_residency);
-}
-
-static ssize_t rc6pp_residency_ms_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
- return sysfs_emit(buf, "%u\n", rc6pp_residency);
-}
-
-static ssize_t media_rc6_residency_ms_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
- return sysfs_emit(buf, "%u\n", rc6_residency);
-}
-
-static DEVICE_ATTR_RO(rc6_enable);
-static DEVICE_ATTR_RO(rc6_residency_ms);
-static DEVICE_ATTR_RO(rc6p_residency_ms);
-static DEVICE_ATTR_RO(rc6pp_residency_ms);
-static DEVICE_ATTR_RO(media_rc6_residency_ms);
-
-static struct attribute *rc6_attrs[] = {
- &dev_attr_rc6_enable.attr,
- &dev_attr_rc6_residency_ms.attr,
- NULL
-};
-
-static const struct attribute_group rc6_attr_group = {
- .name = power_group_name,
- .attrs = rc6_attrs
-};
-
-static struct attribute *rc6p_attrs[] = {
- &dev_attr_rc6p_residency_ms.attr,
- &dev_attr_rc6pp_residency_ms.attr,
- NULL
-};
-
-static const struct attribute_group rc6p_attr_group = {
- .name = power_group_name,
- .attrs = rc6p_attrs
-};
-
-static struct attribute *media_rc6_attrs[] = {
- &dev_attr_media_rc6_residency_ms.attr,
- NULL
-};
-
-static const struct attribute_group media_rc6_attr_group = {
- .name = power_group_name,
- .attrs = media_rc6_attrs
-};
-#endif
-
static int l3_access_valid(struct drm_i915_private *i915, loff_t offset)
{
if (!HAS_L3_DPF(i915))
@@ -492,29 +391,6 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
struct device *kdev = dev_priv->drm.primary->kdev;
int ret;
-#ifdef CONFIG_PM
- if (HAS_RC6(dev_priv)) {
- ret = sysfs_merge_group(&kdev->kobj,
- &rc6_attr_group);
- if (ret)
- drm_err(&dev_priv->drm,
- "RC6 residency sysfs setup failed\n");
- }
- if (HAS_RC6p(dev_priv)) {
- ret = sysfs_merge_group(&kdev->kobj,
- &rc6p_attr_group);
- if (ret)
- drm_err(&dev_priv->drm,
- "RC6p residency sysfs setup failed\n");
- }
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- ret = sysfs_merge_group(&kdev->kobj,
- &media_rc6_attr_group);
- if (ret)
- drm_err(&dev_priv->drm,
- "Media RC6 residency sysfs setup failed\n");
- }
-#endif
if (HAS_L3_DPF(dev_priv)) {
ret = device_create_bin_file(kdev, &dpf_attrs);
if (ret)
@@ -560,8 +436,4 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
sysfs_remove_files(&kdev->kobj, gen6_attrs);
device_remove_bin_file(kdev, &dpf_attrs_1);
device_remove_bin_file(kdev, &dpf_attrs);
-#ifdef CONFIG_PM
- sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group);
- sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);
-#endif
}
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH v7 5/7] drm/i915/gt: Create per-tile RC6 sysfs interface
@ 2022-03-18 23:39 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Matthew Auld
Now tiles have their own sysfs interfaces under the gt/
directory. Because RC6 is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│ ├── gt0
│ │ ├── id
│ │ ├── rc6_enable
│ │ ├── rc6_residency_ms
. . .
. . .
. .
│ └── gtN
│ ├── id
│ ├── rc6_enable
│ ├── rc6_residency_ms
│ .
│ .
│
└── power/ -+
├── rc6_enable | Original interface
├── rc6_residency_ms +-> kept as existing ABI;
. | it multiplexes over
. | the GTs
-+
The existing interfaces have been kept in their original location
to preserve the existing ABI. They act on all the GTs: when
reading they provide the average value from all the GTs.
This patch is not really adding exposing new interfaces (new
ABI) other than adapting the existing one to more tiles. In any
case this new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_sysfs.c | 19 ++
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 244 ++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h | 15 ++
drivers/gpu/drm/i915/i915_sysfs.c | 128 ----------
5 files changed, 279 insertions(+), 128 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 29523848396e4..46af9379803d8 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -106,6 +106,7 @@ gt-y += \
gt/intel_gt_pm_irq.o \
gt/intel_gt_requests.o \
gt/intel_gt_sysfs.o \
+ gt/intel_gt_sysfs_pm.o \
gt/intel_gtt.o \
gt/intel_llc.o \
gt/intel_lrc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
index d508319612944..8ec8bc660c8c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs.c
@@ -13,6 +13,7 @@
#include "i915_sysfs.h"
#include "intel_gt.h"
#include "intel_gt_sysfs.h"
+#include "intel_gt_sysfs_pm.h"
#include "intel_gt_types.h"
#include "intel_rc6.h"
@@ -50,6 +51,11 @@ struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
return kobj_to_gt(kobj);
}
+static struct kobject *gt_get_parent_obj(struct intel_gt *gt)
+{
+ return >->i915->drm.primary->kdev->kobj;
+}
+
static ssize_t id_show(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -81,6 +87,17 @@ void intel_gt_sysfs_register(struct intel_gt *gt)
{
struct kobj_gt *kg;
+ /*
+ * We need to make things right with the
+ * ABI compatibility. The files were originally
+ * generated under the parent directory.
+ *
+ * We generate the files only for gt 0
+ * to avoid duplicates.
+ */
+ if (gt_is_root(gt))
+ intel_gt_sysfs_pm_init(gt, gt_get_parent_obj(gt));
+
kg = kzalloc(sizeof(*kg), GFP_KERNEL);
if (!kg)
goto exit_fail;
@@ -92,6 +109,8 @@ void intel_gt_sysfs_register(struct intel_gt *gt)
if (kobject_add(&kg->base, gt->i915->sysfs_gt, "gt%d", gt->info.id))
goto exit_kobj_put;
+ intel_gt_sysfs_pm_init(gt, &kg->base);
+
return;
exit_kobj_put:
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
new file mode 100644
index 0000000000000..144b004e4de82
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <drm/drm_device.h>
+#include <linux/sysfs.h>
+#include <linux/printk.h>
+
+#include "i915_drv.h"
+#include "i915_sysfs.h"
+#include "intel_gt.h"
+#include "intel_gt_regs.h"
+#include "intel_gt_sysfs.h"
+#include "intel_gt_sysfs_pm.h"
+#include "intel_rc6.h"
+
+#ifdef CONFIG_PM
+enum intel_gt_sysfs_op {
+ INTEL_GT_SYSFS_MIN = 0,
+ INTEL_GT_SYSFS_MAX,
+};
+
+static u32
+sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
+ u32 (func)(struct intel_gt *gt),
+ enum intel_gt_sysfs_op op)
+{
+ struct intel_gt *gt;
+ u32 ret;
+
+ ret = (op == INTEL_GT_SYSFS_MAX) ? 0 : (u32) -1;
+
+ if (!is_object_gt(&dev->kobj)) {
+ int i;
+ struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
+
+ for_each_gt(gt, i915, i) {
+ u32 val = func(gt);
+
+ switch (op) {
+ case INTEL_GT_SYSFS_MIN:
+ if (val < ret)
+ ret = val;
+ break;
+
+ case INTEL_GT_SYSFS_MAX:
+ if (val > ret)
+ ret = val;
+ break;
+ }
+ }
+ } else {
+ gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ ret = func(gt);
+ }
+
+ return ret;
+}
+
+/* RC6 interfaces will show the minimum RC6 residency value */
+#define sysfs_gt_attribute_r_min_func(d, a, f) \
+ sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MIN)
+
+#define sysfs_gt_attribute_r_max_func(d, a, f) \
+ sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
+
+static u32 get_residency(struct intel_gt *gt, i915_reg_t reg)
+{
+ intel_wakeref_t wakeref;
+ u64 res = 0;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ res = intel_rc6_residency_us(>->rc6, reg);
+
+ return DIV_ROUND_CLOSEST_ULL(res, 1000);
+}
+
+static ssize_t rc6_enable_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ u8 mask = 0;
+
+ if (HAS_RC6(gt->i915))
+ mask |= BIT(0);
+ if (HAS_RC6p(gt->i915))
+ mask |= BIT(1);
+ if (HAS_RC6pp(gt->i915))
+ mask |= BIT(2);
+
+ return sysfs_emit(buff, "%x\n", mask);
+}
+
+static u32 __rc6_residency_ms_show(struct intel_gt *gt)
+{
+ return get_residency(gt, GEN6_GT_GFX_RC6);
+}
+
+static ssize_t rc6_residency_ms_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ u32 rc6_residency = sysfs_gt_attribute_r_min_func(dev, attr,
+ __rc6_residency_ms_show);
+
+ return sysfs_emit(buff, "%u\n", rc6_residency);
+}
+
+static u32 __rc6p_residency_ms_show(struct intel_gt *gt)
+{
+ return get_residency(gt, GEN6_GT_GFX_RC6p);
+}
+
+static ssize_t rc6p_residency_ms_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ u32 rc6p_residency = sysfs_gt_attribute_r_min_func(dev, attr,
+ __rc6p_residency_ms_show);
+
+ return sysfs_emit(buff, "%u\n", rc6p_residency);
+}
+
+static u32 __rc6pp_residency_ms_show(struct intel_gt *gt)
+{
+ return get_residency(gt, GEN6_GT_GFX_RC6pp);
+}
+
+static ssize_t rc6pp_residency_ms_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ u32 rc6pp_residency = sysfs_gt_attribute_r_min_func(dev, attr,
+ __rc6pp_residency_ms_show);
+
+ return sysfs_emit(buff, "%u\n", rc6pp_residency);
+}
+
+static u32 __media_rc6_residency_ms_show(struct intel_gt *gt)
+{
+ return get_residency(gt, VLV_GT_MEDIA_RC6);
+}
+
+static ssize_t media_rc6_residency_ms_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ u32 rc6_residency = sysfs_gt_attribute_r_min_func(dev, attr,
+ __media_rc6_residency_ms_show);
+
+ return sysfs_emit(buff, "%u\n", rc6_residency);
+}
+
+static DEVICE_ATTR_RO(rc6_enable);
+static DEVICE_ATTR_RO(rc6_residency_ms);
+static DEVICE_ATTR_RO(rc6p_residency_ms);
+static DEVICE_ATTR_RO(rc6pp_residency_ms);
+static DEVICE_ATTR_RO(media_rc6_residency_ms);
+
+static struct attribute *rc6_attrs[] = {
+ &dev_attr_rc6_enable.attr,
+ &dev_attr_rc6_residency_ms.attr,
+ NULL
+};
+
+static struct attribute *rc6p_attrs[] = {
+ &dev_attr_rc6p_residency_ms.attr,
+ &dev_attr_rc6pp_residency_ms.attr,
+ NULL
+};
+
+static struct attribute *media_rc6_attrs[] = {
+ &dev_attr_media_rc6_residency_ms.attr,
+ NULL
+};
+
+static const struct attribute_group rc6_attr_group[] = {
+ { .attrs = rc6_attrs, },
+ { .name = power_group_name, .attrs = rc6_attrs, },
+};
+
+static const struct attribute_group rc6p_attr_group[] = {
+ { .attrs = rc6p_attrs, },
+ { .name = power_group_name, .attrs = rc6p_attrs, },
+};
+
+static const struct attribute_group media_rc6_attr_group[] = {
+ { .attrs = media_rc6_attrs, },
+ { .name = power_group_name, .attrs = media_rc6_attrs, },
+};
+
+static int __intel_gt_sysfs_create_group(struct kobject *kobj,
+ const struct attribute_group *grp)
+{
+ return is_object_gt(kobj) ?
+ sysfs_create_group(kobj, &grp[0]) :
+ sysfs_merge_group(kobj, &grp[1]);
+}
+
+static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
+{
+ int ret;
+
+ if (!HAS_RC6(gt->i915))
+ return;
+
+ ret = __intel_gt_sysfs_create_group(kobj, rc6_attr_group);
+ if (ret)
+ drm_warn(>->i915->drm,
+ "failed to create gt%u RC6 sysfs files (%pe)\n",
+ gt->info.id, ERR_PTR(ret));
+
+ /*
+ * cannot use the is_visible() attribute because
+ * the upper object inherits from the parent group.
+ */
+ if (HAS_RC6p(gt->i915)) {
+ ret = __intel_gt_sysfs_create_group(kobj, rc6p_attr_group);
+ if (ret)
+ drm_warn(>->i915->drm,
+ "failed to create gt%u RC6p sysfs files (%pe)\n",
+ gt->info.id, ERR_PTR(ret));
+ }
+
+ if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
+ ret = __intel_gt_sysfs_create_group(kobj, media_rc6_attr_group);
+ if (ret)
+ drm_warn(>->i915->drm,
+ "failed to create media %u RC6 sysfs files (%pe)\n",
+ gt->info.id, ERR_PTR(ret));
+ }
+}
+#else
+static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
+{
+}
+#endif /* CONFIG_PM */
+
+void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
+{
+ intel_sysfs_rc6_init(gt, kobj);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
new file mode 100644
index 0000000000000..f567105a4a89a
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __SYSFS_GT_PM_H__
+#define __SYSFS_GT_PM_H__
+
+#include <linux/kobject.h>
+
+#include "intel_gt_types.h"
+
+void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj);
+
+#endif /* SYSFS_RC6_H */
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 5ff915b93c21a..2c5d62a521f64 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -45,107 +45,6 @@ struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
return to_i915(minor->dev);
}
-#ifdef CONFIG_PM
-static u32 calc_residency(struct drm_i915_private *dev_priv,
- i915_reg_t reg)
-{
- intel_wakeref_t wakeref;
- u64 res = 0;
-
- with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
- res = intel_rc6_residency_us(&to_gt(dev_priv)->rc6, reg);
-
- return DIV_ROUND_CLOSEST_ULL(res, 1000);
-}
-
-static ssize_t rc6_enable_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- unsigned int mask;
-
- mask = 0;
- if (HAS_RC6(dev_priv))
- mask |= BIT(0);
- if (HAS_RC6p(dev_priv))
- mask |= BIT(1);
- if (HAS_RC6pp(dev_priv))
- mask |= BIT(2);
-
- return sysfs_emit(buf, "%x\n", mask);
-}
-
-static ssize_t rc6_residency_ms_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
- return sysfs_emit(buf, "%u\n", rc6_residency);
-}
-
-static ssize_t rc6p_residency_ms_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
- return sysfs_emit(buf, "%u\n", rc6p_residency);
-}
-
-static ssize_t rc6pp_residency_ms_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
- return sysfs_emit(buf, "%u\n", rc6pp_residency);
-}
-
-static ssize_t media_rc6_residency_ms_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
- return sysfs_emit(buf, "%u\n", rc6_residency);
-}
-
-static DEVICE_ATTR_RO(rc6_enable);
-static DEVICE_ATTR_RO(rc6_residency_ms);
-static DEVICE_ATTR_RO(rc6p_residency_ms);
-static DEVICE_ATTR_RO(rc6pp_residency_ms);
-static DEVICE_ATTR_RO(media_rc6_residency_ms);
-
-static struct attribute *rc6_attrs[] = {
- &dev_attr_rc6_enable.attr,
- &dev_attr_rc6_residency_ms.attr,
- NULL
-};
-
-static const struct attribute_group rc6_attr_group = {
- .name = power_group_name,
- .attrs = rc6_attrs
-};
-
-static struct attribute *rc6p_attrs[] = {
- &dev_attr_rc6p_residency_ms.attr,
- &dev_attr_rc6pp_residency_ms.attr,
- NULL
-};
-
-static const struct attribute_group rc6p_attr_group = {
- .name = power_group_name,
- .attrs = rc6p_attrs
-};
-
-static struct attribute *media_rc6_attrs[] = {
- &dev_attr_media_rc6_residency_ms.attr,
- NULL
-};
-
-static const struct attribute_group media_rc6_attr_group = {
- .name = power_group_name,
- .attrs = media_rc6_attrs
-};
-#endif
-
static int l3_access_valid(struct drm_i915_private *i915, loff_t offset)
{
if (!HAS_L3_DPF(i915))
@@ -492,29 +391,6 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
struct device *kdev = dev_priv->drm.primary->kdev;
int ret;
-#ifdef CONFIG_PM
- if (HAS_RC6(dev_priv)) {
- ret = sysfs_merge_group(&kdev->kobj,
- &rc6_attr_group);
- if (ret)
- drm_err(&dev_priv->drm,
- "RC6 residency sysfs setup failed\n");
- }
- if (HAS_RC6p(dev_priv)) {
- ret = sysfs_merge_group(&kdev->kobj,
- &rc6p_attr_group);
- if (ret)
- drm_err(&dev_priv->drm,
- "RC6p residency sysfs setup failed\n");
- }
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- ret = sysfs_merge_group(&kdev->kobj,
- &media_rc6_attr_group);
- if (ret)
- drm_err(&dev_priv->drm,
- "Media RC6 residency sysfs setup failed\n");
- }
-#endif
if (HAS_L3_DPF(dev_priv)) {
ret = device_create_bin_file(kdev, &dpf_attrs);
if (ret)
@@ -560,8 +436,4 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
sysfs_remove_files(&kdev->kobj, gen6_attrs);
device_remove_bin_file(kdev, &dpf_attrs_1);
device_remove_bin_file(kdev, &dpf_attrs);
-#ifdef CONFIG_PM
- sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group);
- sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);
-#endif
}
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
@ 2022-03-18 23:39 ` Andi Shyti
-1 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Abdiel Janulgue, Andi Shyti, Tvrtko Ursulin, Lucas De Marchi,
Chris Wilson, Daniele Ceraolo Spurio, Matthew Auld, Andi Shyti,
Sujaritha Sundaresan, Dale B Stimson, Michal Wajdeczko
Now tiles have their own sysfs interfaces under the gt/
directory. Because RPS is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│ ├── gt0
│ │ ├── id
│ │ ├── rc6_enable
│ │ ├── rc6_residency_ms
│ │ ├── rps_act_freq_mhz
│ │ ├── rps_boost_freq_mhz
│ │ ├── rps_cur_freq_mhz
│ │ ├── rps_max_freq_mhz
│ │ ├── rps_min_freq_mhz
│ │ ├── rps_RP0_freq_mhz
│ │ ├── rps_RP1_freq_mhz
│ │ └── rps_RPn_freq_mhz
. .
. .
. .
│ └── gtN
│ ├── id
│ ├── rc6_enable
│ ├── rc6_residency_ms
│ ├── rps_act_freq_mhz
│ ├── rps_boost_freq_mhz
│ ├── rps_cur_freq_mhz
│ ├── rps_max_freq_mhz
│ ├── rps_min_freq_mhz
│ ├── rps_RP0_freq_mhz
│ ├── rps_RP1_freq_mhz
│ └── rps_RPn_freq_mhz
├── gt_act_freq_mhz -+
├── gt_boost_freq_mhz |
├── gt_cur_freq_mhz | Original interface
├── gt_max_freq_mhz +─-> kept as existing ABI;
├── gt_min_freq_mhz | it points to gt0/
├── gt_RP0_freq_mhz |
├── gt_RP1_freq_mhz |
└── gt_RPn_freq_mhz -+
The existing interfaces have been kept in their original location
to preserve the existing ABI. They act on all the GTs: when
writing they loop through all the GTs and write the information
on each interface. When reading they provide the average value
from all the GTs.
This patch is not really adding exposing new interfaces (new
ABI) other than adapting the existing one to more tiles. In any
case this new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 283 ++++++++++++++++++++
drivers/gpu/drm/i915/i915_sysfs.c | 177 ------------
2 files changed, 283 insertions(+), 177 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 144b004e4de82..b0a1ea95d028e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -14,6 +14,7 @@
#include "intel_gt_sysfs.h"
#include "intel_gt_sysfs_pm.h"
#include "intel_rc6.h"
+#include "intel_rps.h"
#ifdef CONFIG_PM
enum intel_gt_sysfs_op {
@@ -21,6 +22,30 @@ enum intel_gt_sysfs_op {
INTEL_GT_SYSFS_MAX,
};
+static int
+sysfs_gt_attribute_w_func(struct device *dev, struct device_attribute *attr,
+ int (func)(struct intel_gt *gt, u32 val), u32 val)
+{
+ struct intel_gt *gt;
+ int ret;
+
+ if (!is_object_gt(&dev->kobj)) {
+ int i;
+ struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
+
+ for_each_gt(gt, i915, i) {
+ ret = func(gt, val);
+ if (ret)
+ break;
+ }
+ } else {
+ gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ ret = func(gt, val);
+ }
+
+ return ret;
+}
+
static u32
sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
u32 (func)(struct intel_gt *gt),
@@ -62,6 +87,7 @@ sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
#define sysfs_gt_attribute_r_min_func(d, a, f) \
sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MIN)
+/* Frequency interfaces will show the maximum frequency value */
#define sysfs_gt_attribute_r_max_func(d, a, f) \
sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
@@ -238,7 +264,264 @@ static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
}
#endif /* CONFIG_PM */
+static u32 __act_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_read_actual_frequency(>->rps);
+}
+
+static ssize_t act_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 actual_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __act_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", actual_freq);
+}
+
+static u32 __cur_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_requested_frequency(>->rps);
+}
+
+static ssize_t cur_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 cur_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __cur_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", cur_freq);
+}
+
+static u32 __boost_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_boost_frequency(>->rps);
+}
+
+static ssize_t boost_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ u32 boost_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __boost_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", boost_freq);
+}
+
+static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)
+{
+ return intel_rps_set_boost_frequency(>->rps, val);
+}
+
+static ssize_t boost_freq_mhz_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buff, size_t count)
+{
+ ssize_t ret;
+ u32 val;
+
+ ret = kstrtou32(buff, 0, &val);
+ if (ret)
+ return ret;
+
+ return sysfs_gt_attribute_w_func(dev, attr,
+ __boost_freq_mhz_store, val) ?: count;
+}
+
+static u32 __rp0_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_rp0_frequency(>->rps);
+}
+
+static ssize_t RP0_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 rp0_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __rp0_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", rp0_freq);
+}
+
+static u32 __rp1_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_rp1_frequency(>->rps);
+}
+
+static ssize_t RP1_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 rp1_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __rp1_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", rp1_freq);
+}
+
+static u32 __rpn_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_rpn_frequency(>->rps);
+}
+
+static ssize_t RPn_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 rpn_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __rpn_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", rpn_freq);
+}
+
+static u32 __max_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_max_frequency(>->rps);
+}
+
+static ssize_t max_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 max_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __max_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", max_freq);
+}
+
+static int __set_max_freq(struct intel_gt *gt, u32 val)
+{
+ return intel_rps_set_max_frequency(>->rps, val);
+}
+
+static ssize_t max_freq_mhz_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buff, size_t count)
+{
+ int ret;
+ u32 val;
+
+ ret = kstrtou32(buff, 0, &val);
+ if (ret)
+ return ret;
+
+ ret = sysfs_gt_attribute_w_func(dev, attr, __set_max_freq, val);
+
+ return ret ?: count;
+}
+
+static u32 __min_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_min_frequency(>->rps);
+}
+
+static ssize_t min_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 min_freq = sysfs_gt_attribute_r_min_func(dev, attr,
+ __min_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", min_freq);
+}
+
+static int __set_min_freq(struct intel_gt *gt, u32 val)
+{
+ return intel_rps_set_min_frequency(>->rps, val);
+}
+
+static ssize_t min_freq_mhz_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buff, size_t count)
+{
+ int ret;
+ u32 val;
+
+ ret = kstrtou32(buff, 0, &val);
+ if (ret)
+ return ret;
+
+ ret = sysfs_gt_attribute_w_func(dev, attr, __set_min_freq, val);
+
+ return ret ?: count;
+}
+
+static u32 __vlv_rpe_freq_mhz_show(struct intel_gt *gt)
+{
+ struct intel_rps *rps = >->rps;
+
+ return intel_gpu_freq(rps, rps->efficient_freq);
+}
+
+static ssize_t vlv_rpe_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 rpe_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __vlv_rpe_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", rpe_freq);
+}
+
+#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \
+ struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \
+ struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)
+
+#define INTEL_GT_RPS_SYSFS_ATTR_RO(_name) \
+ INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL)
+#define INTEL_GT_RPS_SYSFS_ATTR_RW(_name) \
+ INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store)
+
+static INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
+
+static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
+
+#define GEN6_ATTR(s) { \
+ &dev_attr_##s##_act_freq_mhz.attr, \
+ &dev_attr_##s##_cur_freq_mhz.attr, \
+ &dev_attr_##s##_boost_freq_mhz.attr, \
+ &dev_attr_##s##_max_freq_mhz.attr, \
+ &dev_attr_##s##_min_freq_mhz.attr, \
+ &dev_attr_##s##_RP0_freq_mhz.attr, \
+ &dev_attr_##s##_RP1_freq_mhz.attr, \
+ &dev_attr_##s##_RPn_freq_mhz.attr, \
+ NULL, \
+ }
+
+#define GEN6_RPS_ATTR GEN6_ATTR(rps)
+#define GEN6_GT_ATTR GEN6_ATTR(gt)
+
+static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
+static const struct attribute * const gen6_gt_attrs[] = GEN6_GT_ATTR;
+
+static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj,
+ const struct attribute * const *attrs)
+{
+ int ret;
+
+ if (GRAPHICS_VER(gt->i915) < 6)
+ return 0;
+
+ ret = sysfs_create_files(kobj, attrs);
+ if (ret)
+ return ret;
+
+ if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
+ ret = sysfs_create_file(kobj, &dev_attr_vlv_rpe_freq_mhz.attr);
+
+ return ret;
+}
+
void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
{
+ int ret;
+
intel_sysfs_rc6_init(gt, kobj);
+
+ ret = is_object_gt(kobj) ?
+ intel_sysfs_rps_init(gt, kobj, gen6_rps_attrs) :
+ intel_sysfs_rps_init(gt, kobj, gen6_gt_attrs);
+ if (ret)
+ drm_warn(>->i915->drm,
+ "failed to create gt%u RPS sysfs files (%pe)",
+ gt->info.id, ERR_PTR(ret));
}
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 2c5d62a521f64..8521daba212a7 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -156,171 +156,6 @@ static const struct bin_attribute dpf_attrs_1 = {
.private = (void *)1
};
-static ssize_t gt_act_freq_mhz_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(i915)->rps;
-
- return sysfs_emit(buf, "%d\n", intel_rps_read_actual_frequency(rps));
-}
-
-static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(i915)->rps;
-
- return sysfs_emit(buf, "%d\n", intel_rps_get_requested_frequency(rps));
-}
-
-static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(i915)->rps;
-
- return sysfs_emit(buf, "%d\n", intel_rps_get_boost_frequency(rps));
-}
-
-static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(dev_priv)->rps;
- ssize_t ret;
- u32 val;
-
- ret = kstrtou32(buf, 0, &val);
- if (ret)
- return ret;
-
- ret = intel_rps_set_boost_frequency(rps, val);
-
- return ret ?: count;
-}
-
-static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(dev_priv)->rps;
-
- return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->efficient_freq));
-}
-
-static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- struct intel_gt *gt = to_gt(dev_priv);
- struct intel_rps *rps = >->rps;
-
- return sysfs_emit(buf, "%d\n", intel_rps_get_max_frequency(rps));
-}
-
-static ssize_t gt_max_freq_mhz_store(struct device *kdev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- struct intel_gt *gt = to_gt(dev_priv);
- struct intel_rps *rps = >->rps;
- ssize_t ret;
- u32 val;
-
- ret = kstrtou32(buf, 0, &val);
- if (ret)
- return ret;
-
- ret = intel_rps_set_max_frequency(rps, val);
-
- return ret ?: count;
-}
-
-static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
- struct intel_gt *gt = to_gt(i915);
- struct intel_rps *rps = >->rps;
-
- return sysfs_emit(buf, "%d\n", intel_rps_get_min_frequency(rps));
-}
-
-static ssize_t gt_min_freq_mhz_store(struct device *kdev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(i915)->rps;
- ssize_t ret;
- u32 val;
-
- ret = kstrtou32(buf, 0, &val);
- if (ret)
- return ret;
-
- ret = intel_rps_set_min_frequency(rps, val);
-
- return ret ?: count;
-}
-
-static DEVICE_ATTR_RO(gt_act_freq_mhz);
-static DEVICE_ATTR_RO(gt_cur_freq_mhz);
-static DEVICE_ATTR_RW(gt_boost_freq_mhz);
-static DEVICE_ATTR_RW(gt_max_freq_mhz);
-static DEVICE_ATTR_RW(gt_min_freq_mhz);
-
-static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
-
-static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
-static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
-static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
-static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
-
-/* For now we have a static number of RP states */
-static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(dev_priv)->rps;
- u32 val;
-
- if (attr == &dev_attr_gt_RP0_freq_mhz)
- val = intel_rps_get_rp0_frequency(rps);
- else if (attr == &dev_attr_gt_RP1_freq_mhz)
- val = intel_rps_get_rp1_frequency(rps);
- else if (attr == &dev_attr_gt_RPn_freq_mhz)
- val = intel_rps_get_rpn_frequency(rps);
- else
- BUG();
-
- return sysfs_emit(buf, "%d\n", val);
-}
-
-static const struct attribute * const gen6_attrs[] = {
- &dev_attr_gt_act_freq_mhz.attr,
- &dev_attr_gt_cur_freq_mhz.attr,
- &dev_attr_gt_boost_freq_mhz.attr,
- &dev_attr_gt_max_freq_mhz.attr,
- &dev_attr_gt_min_freq_mhz.attr,
- &dev_attr_gt_RP0_freq_mhz.attr,
- &dev_attr_gt_RP1_freq_mhz.attr,
- &dev_attr_gt_RPn_freq_mhz.attr,
- NULL,
-};
-
-static const struct attribute * const vlv_attrs[] = {
- &dev_attr_gt_act_freq_mhz.attr,
- &dev_attr_gt_cur_freq_mhz.attr,
- &dev_attr_gt_boost_freq_mhz.attr,
- &dev_attr_gt_max_freq_mhz.attr,
- &dev_attr_gt_min_freq_mhz.attr,
- &dev_attr_gt_RP0_freq_mhz.attr,
- &dev_attr_gt_RP1_freq_mhz.attr,
- &dev_attr_gt_RPn_freq_mhz.attr,
- &dev_attr_vlv_rpe_freq_mhz.attr,
- NULL,
-};
-
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
@@ -406,14 +241,6 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
}
}
- ret = 0;
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
- else if (GRAPHICS_VER(dev_priv) >= 6)
- ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
- if (ret)
- drm_err(&dev_priv->drm, "RPS sysfs setup failed\n");
-
dev_priv->sysfs_gt = kobject_create_and_add("gt", &kdev->kobj);
if (!dev_priv->sysfs_gt)
drm_warn(&dev_priv->drm,
@@ -430,10 +257,6 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
i915_teardown_error_capture(kdev);
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- sysfs_remove_files(&kdev->kobj, vlv_attrs);
- else
- sysfs_remove_files(&kdev->kobj, gen6_attrs);
device_remove_bin_file(kdev, &dpf_attrs_1);
device_remove_bin_file(kdev, &dpf_attrs);
}
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces
@ 2022-03-18 23:39 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Matthew Auld
Now tiles have their own sysfs interfaces under the gt/
directory. Because RPS is a property that can be configured on a
tile basis, then each tile should have its own interface
The new sysfs structure will have a similar layout for the 4 tile
case:
/sys/.../card0
├── gt
│ ├── gt0
│ │ ├── id
│ │ ├── rc6_enable
│ │ ├── rc6_residency_ms
│ │ ├── rps_act_freq_mhz
│ │ ├── rps_boost_freq_mhz
│ │ ├── rps_cur_freq_mhz
│ │ ├── rps_max_freq_mhz
│ │ ├── rps_min_freq_mhz
│ │ ├── rps_RP0_freq_mhz
│ │ ├── rps_RP1_freq_mhz
│ │ └── rps_RPn_freq_mhz
. .
. .
. .
│ └── gtN
│ ├── id
│ ├── rc6_enable
│ ├── rc6_residency_ms
│ ├── rps_act_freq_mhz
│ ├── rps_boost_freq_mhz
│ ├── rps_cur_freq_mhz
│ ├── rps_max_freq_mhz
│ ├── rps_min_freq_mhz
│ ├── rps_RP0_freq_mhz
│ ├── rps_RP1_freq_mhz
│ └── rps_RPn_freq_mhz
├── gt_act_freq_mhz -+
├── gt_boost_freq_mhz |
├── gt_cur_freq_mhz | Original interface
├── gt_max_freq_mhz +─-> kept as existing ABI;
├── gt_min_freq_mhz | it points to gt0/
├── gt_RP0_freq_mhz |
├── gt_RP1_freq_mhz |
└── gt_RPn_freq_mhz -+
The existing interfaces have been kept in their original location
to preserve the existing ABI. They act on all the GTs: when
writing they loop through all the GTs and write the information
on each interface. When reading they provide the average value
from all the GTs.
This patch is not really adding exposing new interfaces (new
ABI) other than adapting the existing one to more tiles. In any
case this new set of interfaces will be a basic tool for system
managers and administrators when using i915.
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 283 ++++++++++++++++++++
drivers/gpu/drm/i915/i915_sysfs.c | 177 ------------
2 files changed, 283 insertions(+), 177 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index 144b004e4de82..b0a1ea95d028e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -14,6 +14,7 @@
#include "intel_gt_sysfs.h"
#include "intel_gt_sysfs_pm.h"
#include "intel_rc6.h"
+#include "intel_rps.h"
#ifdef CONFIG_PM
enum intel_gt_sysfs_op {
@@ -21,6 +22,30 @@ enum intel_gt_sysfs_op {
INTEL_GT_SYSFS_MAX,
};
+static int
+sysfs_gt_attribute_w_func(struct device *dev, struct device_attribute *attr,
+ int (func)(struct intel_gt *gt, u32 val), u32 val)
+{
+ struct intel_gt *gt;
+ int ret;
+
+ if (!is_object_gt(&dev->kobj)) {
+ int i;
+ struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
+
+ for_each_gt(gt, i915, i) {
+ ret = func(gt, val);
+ if (ret)
+ break;
+ }
+ } else {
+ gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ ret = func(gt, val);
+ }
+
+ return ret;
+}
+
static u32
sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
u32 (func)(struct intel_gt *gt),
@@ -62,6 +87,7 @@ sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
#define sysfs_gt_attribute_r_min_func(d, a, f) \
sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MIN)
+/* Frequency interfaces will show the maximum frequency value */
#define sysfs_gt_attribute_r_max_func(d, a, f) \
sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
@@ -238,7 +264,264 @@ static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
}
#endif /* CONFIG_PM */
+static u32 __act_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_read_actual_frequency(>->rps);
+}
+
+static ssize_t act_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 actual_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __act_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", actual_freq);
+}
+
+static u32 __cur_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_requested_frequency(>->rps);
+}
+
+static ssize_t cur_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 cur_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __cur_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", cur_freq);
+}
+
+static u32 __boost_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_boost_frequency(>->rps);
+}
+
+static ssize_t boost_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ u32 boost_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __boost_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", boost_freq);
+}
+
+static int __boost_freq_mhz_store(struct intel_gt *gt, u32 val)
+{
+ return intel_rps_set_boost_frequency(>->rps, val);
+}
+
+static ssize_t boost_freq_mhz_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buff, size_t count)
+{
+ ssize_t ret;
+ u32 val;
+
+ ret = kstrtou32(buff, 0, &val);
+ if (ret)
+ return ret;
+
+ return sysfs_gt_attribute_w_func(dev, attr,
+ __boost_freq_mhz_store, val) ?: count;
+}
+
+static u32 __rp0_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_rp0_frequency(>->rps);
+}
+
+static ssize_t RP0_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 rp0_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __rp0_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", rp0_freq);
+}
+
+static u32 __rp1_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_rp1_frequency(>->rps);
+}
+
+static ssize_t RP1_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 rp1_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __rp1_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", rp1_freq);
+}
+
+static u32 __rpn_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_rpn_frequency(>->rps);
+}
+
+static ssize_t RPn_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 rpn_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __rpn_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", rpn_freq);
+}
+
+static u32 __max_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_max_frequency(>->rps);
+}
+
+static ssize_t max_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 max_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __max_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", max_freq);
+}
+
+static int __set_max_freq(struct intel_gt *gt, u32 val)
+{
+ return intel_rps_set_max_frequency(>->rps, val);
+}
+
+static ssize_t max_freq_mhz_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buff, size_t count)
+{
+ int ret;
+ u32 val;
+
+ ret = kstrtou32(buff, 0, &val);
+ if (ret)
+ return ret;
+
+ ret = sysfs_gt_attribute_w_func(dev, attr, __set_max_freq, val);
+
+ return ret ?: count;
+}
+
+static u32 __min_freq_mhz_show(struct intel_gt *gt)
+{
+ return intel_rps_get_min_frequency(>->rps);
+}
+
+static ssize_t min_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 min_freq = sysfs_gt_attribute_r_min_func(dev, attr,
+ __min_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", min_freq);
+}
+
+static int __set_min_freq(struct intel_gt *gt, u32 val)
+{
+ return intel_rps_set_min_frequency(>->rps, val);
+}
+
+static ssize_t min_freq_mhz_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buff, size_t count)
+{
+ int ret;
+ u32 val;
+
+ ret = kstrtou32(buff, 0, &val);
+ if (ret)
+ return ret;
+
+ ret = sysfs_gt_attribute_w_func(dev, attr, __set_min_freq, val);
+
+ return ret ?: count;
+}
+
+static u32 __vlv_rpe_freq_mhz_show(struct intel_gt *gt)
+{
+ struct intel_rps *rps = >->rps;
+
+ return intel_gpu_freq(rps, rps->efficient_freq);
+}
+
+static ssize_t vlv_rpe_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr, char *buff)
+{
+ u32 rpe_freq = sysfs_gt_attribute_r_max_func(dev, attr,
+ __vlv_rpe_freq_mhz_show);
+
+ return sysfs_emit(buff, "%u\n", rpe_freq);
+}
+
+#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \
+ struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \
+ struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)
+
+#define INTEL_GT_RPS_SYSFS_ATTR_RO(_name) \
+ INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL)
+#define INTEL_GT_RPS_SYSFS_ATTR_RW(_name) \
+ INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store)
+
+static INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
+static INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
+
+static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
+
+#define GEN6_ATTR(s) { \
+ &dev_attr_##s##_act_freq_mhz.attr, \
+ &dev_attr_##s##_cur_freq_mhz.attr, \
+ &dev_attr_##s##_boost_freq_mhz.attr, \
+ &dev_attr_##s##_max_freq_mhz.attr, \
+ &dev_attr_##s##_min_freq_mhz.attr, \
+ &dev_attr_##s##_RP0_freq_mhz.attr, \
+ &dev_attr_##s##_RP1_freq_mhz.attr, \
+ &dev_attr_##s##_RPn_freq_mhz.attr, \
+ NULL, \
+ }
+
+#define GEN6_RPS_ATTR GEN6_ATTR(rps)
+#define GEN6_GT_ATTR GEN6_ATTR(gt)
+
+static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
+static const struct attribute * const gen6_gt_attrs[] = GEN6_GT_ATTR;
+
+static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj,
+ const struct attribute * const *attrs)
+{
+ int ret;
+
+ if (GRAPHICS_VER(gt->i915) < 6)
+ return 0;
+
+ ret = sysfs_create_files(kobj, attrs);
+ if (ret)
+ return ret;
+
+ if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915))
+ ret = sysfs_create_file(kobj, &dev_attr_vlv_rpe_freq_mhz.attr);
+
+ return ret;
+}
+
void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
{
+ int ret;
+
intel_sysfs_rc6_init(gt, kobj);
+
+ ret = is_object_gt(kobj) ?
+ intel_sysfs_rps_init(gt, kobj, gen6_rps_attrs) :
+ intel_sysfs_rps_init(gt, kobj, gen6_gt_attrs);
+ if (ret)
+ drm_warn(>->i915->drm,
+ "failed to create gt%u RPS sysfs files (%pe)",
+ gt->info.id, ERR_PTR(ret));
}
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 2c5d62a521f64..8521daba212a7 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -156,171 +156,6 @@ static const struct bin_attribute dpf_attrs_1 = {
.private = (void *)1
};
-static ssize_t gt_act_freq_mhz_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(i915)->rps;
-
- return sysfs_emit(buf, "%d\n", intel_rps_read_actual_frequency(rps));
-}
-
-static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(i915)->rps;
-
- return sysfs_emit(buf, "%d\n", intel_rps_get_requested_frequency(rps));
-}
-
-static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(i915)->rps;
-
- return sysfs_emit(buf, "%d\n", intel_rps_get_boost_frequency(rps));
-}
-
-static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(dev_priv)->rps;
- ssize_t ret;
- u32 val;
-
- ret = kstrtou32(buf, 0, &val);
- if (ret)
- return ret;
-
- ret = intel_rps_set_boost_frequency(rps, val);
-
- return ret ?: count;
-}
-
-static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
- struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(dev_priv)->rps;
-
- return sysfs_emit(buf, "%d\n", intel_gpu_freq(rps, rps->efficient_freq));
-}
-
-static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- struct intel_gt *gt = to_gt(dev_priv);
- struct intel_rps *rps = >->rps;
-
- return sysfs_emit(buf, "%d\n", intel_rps_get_max_frequency(rps));
-}
-
-static ssize_t gt_max_freq_mhz_store(struct device *kdev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- struct intel_gt *gt = to_gt(dev_priv);
- struct intel_rps *rps = >->rps;
- ssize_t ret;
- u32 val;
-
- ret = kstrtou32(buf, 0, &val);
- if (ret)
- return ret;
-
- ret = intel_rps_set_max_frequency(rps, val);
-
- return ret ?: count;
-}
-
-static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
- struct intel_gt *gt = to_gt(i915);
- struct intel_rps *rps = >->rps;
-
- return sysfs_emit(buf, "%d\n", intel_rps_get_min_frequency(rps));
-}
-
-static ssize_t gt_min_freq_mhz_store(struct device *kdev,
- struct device_attribute *attr,
- const char *buf, size_t count)
-{
- struct drm_i915_private *i915 = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(i915)->rps;
- ssize_t ret;
- u32 val;
-
- ret = kstrtou32(buf, 0, &val);
- if (ret)
- return ret;
-
- ret = intel_rps_set_min_frequency(rps, val);
-
- return ret ?: count;
-}
-
-static DEVICE_ATTR_RO(gt_act_freq_mhz);
-static DEVICE_ATTR_RO(gt_cur_freq_mhz);
-static DEVICE_ATTR_RW(gt_boost_freq_mhz);
-static DEVICE_ATTR_RW(gt_max_freq_mhz);
-static DEVICE_ATTR_RW(gt_min_freq_mhz);
-
-static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
-
-static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
-static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
-static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
-static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
-
-/* For now we have a static number of RP states */
-static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
-{
- struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- struct intel_rps *rps = &to_gt(dev_priv)->rps;
- u32 val;
-
- if (attr == &dev_attr_gt_RP0_freq_mhz)
- val = intel_rps_get_rp0_frequency(rps);
- else if (attr == &dev_attr_gt_RP1_freq_mhz)
- val = intel_rps_get_rp1_frequency(rps);
- else if (attr == &dev_attr_gt_RPn_freq_mhz)
- val = intel_rps_get_rpn_frequency(rps);
- else
- BUG();
-
- return sysfs_emit(buf, "%d\n", val);
-}
-
-static const struct attribute * const gen6_attrs[] = {
- &dev_attr_gt_act_freq_mhz.attr,
- &dev_attr_gt_cur_freq_mhz.attr,
- &dev_attr_gt_boost_freq_mhz.attr,
- &dev_attr_gt_max_freq_mhz.attr,
- &dev_attr_gt_min_freq_mhz.attr,
- &dev_attr_gt_RP0_freq_mhz.attr,
- &dev_attr_gt_RP1_freq_mhz.attr,
- &dev_attr_gt_RPn_freq_mhz.attr,
- NULL,
-};
-
-static const struct attribute * const vlv_attrs[] = {
- &dev_attr_gt_act_freq_mhz.attr,
- &dev_attr_gt_cur_freq_mhz.attr,
- &dev_attr_gt_boost_freq_mhz.attr,
- &dev_attr_gt_max_freq_mhz.attr,
- &dev_attr_gt_min_freq_mhz.attr,
- &dev_attr_gt_RP0_freq_mhz.attr,
- &dev_attr_gt_RP1_freq_mhz.attr,
- &dev_attr_gt_RPn_freq_mhz.attr,
- &dev_attr_vlv_rpe_freq_mhz.attr,
- NULL,
-};
-
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
@@ -406,14 +241,6 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv)
}
}
- ret = 0;
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
- else if (GRAPHICS_VER(dev_priv) >= 6)
- ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
- if (ret)
- drm_err(&dev_priv->drm, "RPS sysfs setup failed\n");
-
dev_priv->sysfs_gt = kobject_create_and_add("gt", &kdev->kobj);
if (!dev_priv->sysfs_gt)
drm_warn(&dev_priv->drm,
@@ -430,10 +257,6 @@ void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
i915_teardown_error_capture(kdev);
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- sysfs_remove_files(&kdev->kobj, vlv_attrs);
- else
- sysfs_remove_files(&kdev->kobj, gen6_attrs);
device_remove_bin_file(kdev, &dpf_attrs_1);
device_remove_bin_file(kdev, &dpf_attrs);
}
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v7 7/7] drm/i915/gt: Add sysfs throttle frequency interfaces
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
@ 2022-03-18 23:39 ` Andi Shyti
-1 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel
Cc: Abdiel Janulgue, Andi Shyti, Tvrtko Ursulin, Lucas De Marchi,
Chris Wilson, Daniele Ceraolo Spurio, Matthew Auld, Andi Shyti,
Sujaritha Sundaresan, Dale B Stimson, Michal Wajdeczko
From: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Throttling here refers to the GT frequency being clipped. Each of
the throttle reason attributes will have a 0 or 1 value depending
upon whether there is throttling and also the specific reason for
it.
The following is a brief description of the sysfs throttle
frequency attributes added:
- throttle_reason_status: when set indicates that there is GT
frequency clipping.
- throttle_reason_pl1: when set indicates that PBM PL1 (platform
or package PL1) has caused GT frequency clipping.
- throttle_reason_pl2: when set indicates that PBM PL2 or PL3
(platform or package PL2 or PL3) has caused GT frequency
clipping.
- throttle_reason_pl4: when set indicates that PL4 or IccMax has
caused GT frequency clipping.
- throttle_reason_thermal: when set indicates that Thermal event
has caused GT frequency clipping.
- throttle_reason_prochot: when set indicates that PROCHOT# has
caused GT frequency clipping.
- throttle_reason_ratl: when set indicates that Running Average
Thermal Limit has caused GT frequency clipping.
- throttle_reason_vr_thermalert: when set indicates that Hot VR
(any processor VR) has caused GT frequency clipping.
- throttle_reason_vr_tdc: when set indicates that VR TDC
(Thermal Design Current) has caused GT frequency clipping.
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 74 +++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_rps.c | 18 +++++
drivers/gpu/drm/i915/gt/intel_rps.h | 4 ++
drivers/gpu/drm/i915/i915_reg.h | 11 +++
4 files changed, 107 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index b0a1ea95d028e..26cbfa6477d12 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -8,6 +8,7 @@
#include <linux/printk.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_sysfs.h"
#include "intel_gt.h"
#include "intel_gt_regs.h"
@@ -493,6 +494,69 @@ static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
static const struct attribute * const gen6_gt_attrs[] = GEN6_GT_ATTR;
+static ssize_t punit_req_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ u32 preq = intel_rps_read_punit_req_frequency(>->rps);
+
+ return sysfs_emit(buff, "%u\n", preq);
+}
+
+struct intel_gt_bool_throttle_attr {
+ struct attribute attr;
+ ssize_t (*show)(struct device *dev, struct device_attribute *attr,
+ char *buf);
+ i915_reg_t reg32;
+ u32 mask;
+};
+
+static ssize_t throttle_reason_bool_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ struct intel_gt_bool_throttle_attr *t_attr =
+ (struct intel_gt_bool_throttle_attr *) attr;
+ bool val = rps_read_mask_mmio(>->rps, t_attr->reg32, t_attr->mask);
+
+ return sysfs_emit(buff, "%u\n", val);
+}
+
+#define INTEL_GT_RPS_BOOL_ATTR_RO(sysfs_func__, mask__) \
+struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
+ .attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
+ .show = throttle_reason_bool_show, \
+ .reg32 = GT0_PERF_LIMIT_REASONS, \
+ .mask = mask__, \
+}
+
+static DEVICE_ATTR_RO(punit_req_freq_mhz);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status, GT0_PERF_LIMIT_REASONS_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl4, POWER_LIMIT_4_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_thermal, THERMAL_LIMIT_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_prochot, PROCHOT_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_ratl, RATL_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_thermalert, VR_THERMALERT_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_tdc, VR_TDC_MASK);
+
+static const struct attribute *freq_attrs[] = {
+ &dev_attr_punit_req_freq_mhz.attr,
+ &attr_throttle_reason_status.attr,
+ &attr_throttle_reason_pl1.attr,
+ &attr_throttle_reason_pl2.attr,
+ &attr_throttle_reason_pl4.attr,
+ &attr_throttle_reason_thermal.attr,
+ &attr_throttle_reason_prochot.attr,
+ &attr_throttle_reason_ratl.attr,
+ &attr_throttle_reason_vr_thermalert.attr,
+ &attr_throttle_reason_vr_tdc.attr,
+ NULL
+};
+
static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj,
const struct attribute * const *attrs)
{
@@ -524,4 +588,14 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
drm_warn(>->i915->drm,
"failed to create gt%u RPS sysfs files (%pe)",
gt->info.id, ERR_PTR(ret));
+
+ /* end of the legacy interfaces */
+ if (!is_object_gt(kobj))
+ return;
+
+ ret = sysfs_create_files(kobj, freq_attrs);
+ if (ret)
+ drm_warn(>->i915->drm,
+ "failed to create gt%u throttle sysfs files (%pe)",
+ gt->info.id, ERR_PTR(ret));
}
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index a9c13b1a30181..6c9fdf7906c50 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2291,6 +2291,24 @@ void intel_rps_lower_unslice(struct intel_rps *rps)
mutex_unlock(&rps->lock);
}
+static u32 rps_read_mmio(struct intel_rps *rps, i915_reg_t reg32)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ intel_wakeref_t wakeref;
+ u32 val;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ val = intel_uncore_read(gt->uncore, reg32);
+
+ return val;
+}
+
+bool rps_read_mask_mmio(struct intel_rps *rps,
+ i915_reg_t reg32, u32 mask)
+{
+ return rps_read_mmio(rps, reg32) & mask;
+}
+
/* External interface for intel_ips.ko */
static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index c6d76a3d13314..ba1ed9f7ecdab 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -7,6 +7,7 @@
#define INTEL_RPS_H
#include "intel_rps_types.h"
+#include "i915_reg_defs.h"
struct i915_request;
@@ -48,6 +49,9 @@ u32 intel_rps_read_state_cap(struct intel_rps *rps);
void intel_rps_raise_unslice(struct intel_rps *rps);
void intel_rps_lower_unslice(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason(struct intel_rps *rps);
+bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);
+
void gen5_rps_irq_handler(struct intel_rps *rps);
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2acebd5236913..a0d652f19ff93 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1837,6 +1837,17 @@
#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
+#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
+#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
+#define PROCHOT_MASK REG_BIT(1)
+#define THERMAL_LIMIT_MASK REG_BIT(2)
+#define RATL_MASK REG_BIT(6)
+#define VR_THERMALERT_MASK REG_BIT(7)
+#define VR_TDC_MASK REG_BIT(8)
+#define POWER_LIMIT_4_MASK REG_BIT(9)
+#define POWER_LIMIT_1_MASK REG_BIT(11)
+#define POWER_LIMIT_2_MASK REG_BIT(12)
+
#define CHV_CLK_CTL1 _MMIO(0x101100)
#define VLV_CLK_CTL2 _MMIO(0x101104)
#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH v7 7/7] drm/i915/gt: Add sysfs throttle frequency interfaces
@ 2022-03-18 23:39 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-18 23:39 UTC (permalink / raw)
To: Intel GFX, DRI Devel; +Cc: Lucas De Marchi, Chris Wilson, Matthew Auld
From: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Throttling here refers to the GT frequency being clipped. Each of
the throttle reason attributes will have a 0 or 1 value depending
upon whether there is throttling and also the specific reason for
it.
The following is a brief description of the sysfs throttle
frequency attributes added:
- throttle_reason_status: when set indicates that there is GT
frequency clipping.
- throttle_reason_pl1: when set indicates that PBM PL1 (platform
or package PL1) has caused GT frequency clipping.
- throttle_reason_pl2: when set indicates that PBM PL2 or PL3
(platform or package PL2 or PL3) has caused GT frequency
clipping.
- throttle_reason_pl4: when set indicates that PL4 or IccMax has
caused GT frequency clipping.
- throttle_reason_thermal: when set indicates that Thermal event
has caused GT frequency clipping.
- throttle_reason_prochot: when set indicates that PROCHOT# has
caused GT frequency clipping.
- throttle_reason_ratl: when set indicates that Running Average
Thermal Limit has caused GT frequency clipping.
- throttle_reason_vr_thermalert: when set indicates that Hot VR
(any processor VR) has caused GT frequency clipping.
- throttle_reason_vr_tdc: when set indicates that VR TDC
(Thermal Design Current) has caused GT frequency clipping.
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 74 +++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_rps.c | 18 +++++
drivers/gpu/drm/i915/gt/intel_rps.h | 4 ++
drivers/gpu/drm/i915/i915_reg.h | 11 +++
4 files changed, 107 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
index b0a1ea95d028e..26cbfa6477d12 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
@@ -8,6 +8,7 @@
#include <linux/printk.h>
#include "i915_drv.h"
+#include "i915_reg.h"
#include "i915_sysfs.h"
#include "intel_gt.h"
#include "intel_gt_regs.h"
@@ -493,6 +494,69 @@ static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
static const struct attribute * const gen6_rps_attrs[] = GEN6_RPS_ATTR;
static const struct attribute * const gen6_gt_attrs[] = GEN6_GT_ATTR;
+static ssize_t punit_req_freq_mhz_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ u32 preq = intel_rps_read_punit_req_frequency(>->rps);
+
+ return sysfs_emit(buff, "%u\n", preq);
+}
+
+struct intel_gt_bool_throttle_attr {
+ struct attribute attr;
+ ssize_t (*show)(struct device *dev, struct device_attribute *attr,
+ char *buf);
+ i915_reg_t reg32;
+ u32 mask;
+};
+
+static ssize_t throttle_reason_bool_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buff)
+{
+ struct intel_gt *gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
+ struct intel_gt_bool_throttle_attr *t_attr =
+ (struct intel_gt_bool_throttle_attr *) attr;
+ bool val = rps_read_mask_mmio(>->rps, t_attr->reg32, t_attr->mask);
+
+ return sysfs_emit(buff, "%u\n", val);
+}
+
+#define INTEL_GT_RPS_BOOL_ATTR_RO(sysfs_func__, mask__) \
+struct intel_gt_bool_throttle_attr attr_##sysfs_func__ = { \
+ .attr = { .name = __stringify(sysfs_func__), .mode = 0444 }, \
+ .show = throttle_reason_bool_show, \
+ .reg32 = GT0_PERF_LIMIT_REASONS, \
+ .mask = mask__, \
+}
+
+static DEVICE_ATTR_RO(punit_req_freq_mhz);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_status, GT0_PERF_LIMIT_REASONS_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl1, POWER_LIMIT_1_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl2, POWER_LIMIT_2_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_pl4, POWER_LIMIT_4_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_thermal, THERMAL_LIMIT_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_prochot, PROCHOT_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_ratl, RATL_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_thermalert, VR_THERMALERT_MASK);
+static INTEL_GT_RPS_BOOL_ATTR_RO(throttle_reason_vr_tdc, VR_TDC_MASK);
+
+static const struct attribute *freq_attrs[] = {
+ &dev_attr_punit_req_freq_mhz.attr,
+ &attr_throttle_reason_status.attr,
+ &attr_throttle_reason_pl1.attr,
+ &attr_throttle_reason_pl2.attr,
+ &attr_throttle_reason_pl4.attr,
+ &attr_throttle_reason_thermal.attr,
+ &attr_throttle_reason_prochot.attr,
+ &attr_throttle_reason_ratl.attr,
+ &attr_throttle_reason_vr_thermalert.attr,
+ &attr_throttle_reason_vr_tdc.attr,
+ NULL
+};
+
static int intel_sysfs_rps_init(struct intel_gt *gt, struct kobject *kobj,
const struct attribute * const *attrs)
{
@@ -524,4 +588,14 @@ void intel_gt_sysfs_pm_init(struct intel_gt *gt, struct kobject *kobj)
drm_warn(>->i915->drm,
"failed to create gt%u RPS sysfs files (%pe)",
gt->info.id, ERR_PTR(ret));
+
+ /* end of the legacy interfaces */
+ if (!is_object_gt(kobj))
+ return;
+
+ ret = sysfs_create_files(kobj, freq_attrs);
+ if (ret)
+ drm_warn(>->i915->drm,
+ "failed to create gt%u throttle sysfs files (%pe)",
+ gt->info.id, ERR_PTR(ret));
}
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index a9c13b1a30181..6c9fdf7906c50 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2291,6 +2291,24 @@ void intel_rps_lower_unslice(struct intel_rps *rps)
mutex_unlock(&rps->lock);
}
+static u32 rps_read_mmio(struct intel_rps *rps, i915_reg_t reg32)
+{
+ struct intel_gt *gt = rps_to_gt(rps);
+ intel_wakeref_t wakeref;
+ u32 val;
+
+ with_intel_runtime_pm(gt->uncore->rpm, wakeref)
+ val = intel_uncore_read(gt->uncore, reg32);
+
+ return val;
+}
+
+bool rps_read_mask_mmio(struct intel_rps *rps,
+ i915_reg_t reg32, u32 mask)
+{
+ return rps_read_mmio(rps, reg32) & mask;
+}
+
/* External interface for intel_ips.ko */
static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index c6d76a3d13314..ba1ed9f7ecdab 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -7,6 +7,7 @@
#define INTEL_RPS_H
#include "intel_rps_types.h"
+#include "i915_reg_defs.h"
struct i915_request;
@@ -48,6 +49,9 @@ u32 intel_rps_read_state_cap(struct intel_rps *rps);
void intel_rps_raise_unslice(struct intel_rps *rps);
void intel_rps_lower_unslice(struct intel_rps *rps);
+u32 intel_rps_read_throttle_reason(struct intel_rps *rps);
+bool rps_read_mask_mmio(struct intel_rps *rps, i915_reg_t reg32, u32 mask);
+
void gen5_rps_irq_handler(struct intel_rps *rps);
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2acebd5236913..a0d652f19ff93 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1837,6 +1837,17 @@
#define GEN9_RP_STATE_LIMITS _MMIO(0x138148)
#define XEHPSDV_RP_STATE_CAP _MMIO(0x250014)
+#define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8)
+#define GT0_PERF_LIMIT_REASONS_MASK 0xde3
+#define PROCHOT_MASK REG_BIT(1)
+#define THERMAL_LIMIT_MASK REG_BIT(2)
+#define RATL_MASK REG_BIT(6)
+#define VR_THERMALERT_MASK REG_BIT(7)
+#define VR_TDC_MASK REG_BIT(8)
+#define POWER_LIMIT_4_MASK REG_BIT(9)
+#define POWER_LIMIT_1_MASK REG_BIT(11)
+#define POWER_LIMIT_2_MASK REG_BIT(12)
+
#define CHV_CLK_CTL1 _MMIO(0x101100)
#define VLV_CLK_CTL2 _MMIO(0x101104)
#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
--
2.35.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce multitile support
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
` (7 preceding siblings ...)
(?)
@ 2022-03-18 23:53 ` Patchwork
-1 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2022-03-18 23:53 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e394242076f2 drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
e56e16681fc9 drm/i915/gt: add gt_is_root() helper
5bf72a0d1d73 drm/i915: Prepare for multiple GTs
-:249: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'id__' - possible side-effects?
#249: FILE: drivers/gpu/drm/i915/gt/intel_gt.h:103:
+#define for_each_gt(gt__, i915__, id__) \
+ for ((id__) = 0; \
+ (id__) < I915_MAX_GT; \
+ (id__)++) \
+ for_each_if(((gt__) = (i915__)->gt[(id__)]))
total: 0 errors, 0 warnings, 1 checks, 444 lines checked
3dbb22f19314 drm/i915/gt: create per-tile sysfs interface
-:72: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#72:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 196 lines checked
e051f78dc8fa drm/i915/gt: Create per-tile RC6 sysfs interface
-:121: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#121:
new file mode 100644
-:157: CHECK:SPACING: No space is necessary after a cast
#157: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:32:
+ ret = (op == INTEL_GT_SYSFS_MAX) ? 0 : (u32) -1;
total: 0 errors, 1 warnings, 1 checks, 453 lines checked
557499c5d443 drm/i915/gt: Create per-tile RPS sysfs interfaces
-:320: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_mode' - possible side-effects?
#320: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:458:
+#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \
+ struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \
+ struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)
-:320: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_show' - possible side-effects?
#320: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:458:
+#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \
+ struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \
+ struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)
-:320: CHECK:MACRO_ARG_REUSE: Macro argument reuse '_store' - possible side-effects?
#320: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:458:
+#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \
+ struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \
+ struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)
-:334: CHECK:CAMELCASE: Avoid CamelCase: <RPn_freq_mhz>
#334: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:472:
+static INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
-:348: CHECK:CAMELCASE: Avoid CamelCase: <dev_attr_##s##_RPn_freq_mhz>
#348: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:486:
+ &dev_attr_##s##_RPn_freq_mhz.attr, \
total: 0 errors, 0 warnings, 5 checks, 503 lines checked
42ca62b1fbf5 drm/i915/gt: Add sysfs throttle frequency interfaces
-:87: CHECK:SPACING: No space is necessary after a cast
#87: FILE: drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:521:
+ (struct intel_gt_bool_throttle_attr *) attr;
total: 0 errors, 0 warnings, 1 checks, 147 lines checked
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce multitile support
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
` (8 preceding siblings ...)
(?)
@ 2022-03-18 23:55 ` Patchwork
-1 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2022-03-18 23:55 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Introduce multitile support
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
` (9 preceding siblings ...)
(?)
@ 2022-03-19 0:31 ` Patchwork
-1 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2022-03-19 0:31 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5817 bytes --]
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11384 -> Patchwork_22617
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/index.html
Participating hosts (39 -> 40)
------------------------------
Additional (5): bat-dg2-8 bat-dg2-9 fi-pnv-d510 bat-jsl-2 bat-jsl-1
Missing (4): fi-bsw-cyan shard-rkl shard-tglu fi-kbl-8809g
Known issues
------------
Here are the changes found in Patchwork_22617 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-hsw-4770: NOTRUN -> [SKIP][1] ([fdo#109271] / [fdo#109315]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/fi-hsw-4770/igt@amdgpu/amd_basic@cs-gfx.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#5341])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/fi-pnv-d510/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@prime_vgem@basic-userptr:
- fi-pnv-d510: NOTRUN -> [SKIP][3] ([fdo#109271]) +57 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/fi-pnv-d510/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][4] ([i915#4785]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [SKIP][6] ([fdo#109271]) -> [FAIL][7] ([i915#579])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5192]: https://gitlab.freedesktop.org/drm/intel/issues/5192
[i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5276]: https://gitlab.freedesktop.org/drm/intel/issues/5276
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5339]: https://gitlab.freedesktop.org/drm/intel/issues/5339
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
Build changes
-------------
* Linux: CI_DRM_11384 -> Patchwork_22617
CI-20190529: 20190529
CI_DRM_11384: 76874531ffae41683316380bd6d6227bbba12148 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6386: 0fcd59ad25b2960c0b654f90dfe4dd9e7c7b874d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22617: 42ca62b1fbf5c3960654ff09051a0a76f4b14eca @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
42ca62b1fbf5 drm/i915/gt: Add sysfs throttle frequency interfaces
557499c5d443 drm/i915/gt: Create per-tile RPS sysfs interfaces
e051f78dc8fa drm/i915/gt: Create per-tile RC6 sysfs interface
3dbb22f19314 drm/i915/gt: create per-tile sysfs interface
5bf72a0d1d73 drm/i915: Prepare for multiple GTs
e56e16681fc9 drm/i915/gt: add gt_is_root() helper
e394242076f2 drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/index.html
[-- Attachment #2: Type: text/html, Size: 4596 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce multitile support
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
` (10 preceding siblings ...)
(?)
@ 2022-03-19 2:06 ` Patchwork
2022-03-21 10:05 ` Matthew Auld
-1 siblings, 1 reply; 40+ messages in thread
From: Patchwork @ 2022-03-19 2:06 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30251 bytes --]
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11384_full -> Patchwork_22617_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22617_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22617_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22617_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl7/igt@gem_workarounds@suspend-resume.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl6/igt@gem_workarounds@suspend-resume.html
Known issues
------------
Here are the changes found in Patchwork_22617_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][3] ([i915#4991])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl4/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][4] ([i915#180]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
- shard-apl: NOTRUN -> [DMESG-WARN][5] ([i915#180])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_eio@in-flight-immediate:
- shard-tglb: [PASS][6] -> [TIMEOUT][7] ([i915#3063])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb3/igt@gem_eio@in-flight-immediate.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb8/igt@gem_eio@in-flight-immediate.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][8] -> [FAIL][9] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][10] ([i915#2842])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-glk6/igt@gem_exec_fair@basic-pace@vecs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: NOTRUN -> [FAIL][15] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][16] ([fdo#109283])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb6/igt@gem_exec_params@no-blt.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +5 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl10/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@parallel-random:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_pxp@create-valid-protected-context:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#4270])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271]) +34 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_render_copy@yf-tiled-to-vebox-x-tiled:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#768])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_render_copy@yf-tiled-to-vebox-x-tiled.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][22] ([i915#4991])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl3/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][23] ([i915#3318])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-iclb: NOTRUN -> [SKIP][24] ([fdo#109289])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@allowed-all:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#2856]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][26] ([i915#454])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][27] ([fdo#110892])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][28] ([i915#1886])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl10/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@sysfs-reader:
- shard-skl: [PASS][29] -> [INCOMPLETE][30] ([i915#4817])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl10/igt@i915_suspend@sysfs-reader.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl2/igt@i915_suspend@sysfs-reader.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-iclb: NOTRUN -> [SKIP][31] ([i915#1769])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][32] ([i915#5286]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#110725] / [fdo#111614]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][34] ([i915#3743]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777]) +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109278] / [i915#3886]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +12 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3886]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs:
- shard-glk: NOTRUN -> [SKIP][40] ([fdo#109271]) +25 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#3742])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@dp-hpd-with-enabled-mode:
- shard-glk: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +4 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_chamelium@dp-hpd-with-enabled-mode.html
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827]) +5 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_chamelium@dp-hpd-with-enabled-mode.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +24 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_chamelium@vga-hpd.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#109284] / [fdo#111827])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb6/igt@kms_color_chamelium@pipe-b-ctm-max.html
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl1/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][48] ([i915#1319])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271]) +21 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#109279] / [i915#3359])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-random:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109278] / [fdo#109279]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109274] / [fdo#109278]) +3 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_draw_crc@draw-method-rgb565-blt-4tiled:
- shard-iclb: NOTRUN -> [SKIP][53] ([i915#5287]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_draw_crc@draw-method-rgb565-blt-4tiled.html
* igt@kms_flip@2x-absolute-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109274]) +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][55] -> [FAIL][56] ([i915#79]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [PASS][57] -> [DMESG-WARN][58] ([i915#180]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
- shard-iclb: NOTRUN -> [SKIP][59] ([i915#2587])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109280]) +12 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#533]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][62] ([i915#265]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][63] ([fdo#108145] / [i915#265])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][64] ([i915#265])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265]) +3 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
- shard-iclb: NOTRUN -> [SKIP][67] ([fdo#109278]) +8 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
- shard-iclb: [PASS][68] -> [SKIP][69] ([i915#5235]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
* igt@kms_psr2_su@page_flip-p010:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#658])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl1/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][72] -> [SKIP][73] ([fdo#109441]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-iclb: NOTRUN -> [SKIP][74] ([i915#5289])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][75] ([IGT#2])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_sysfs_edid_timing.html
* igt@kms_vrr@flip-dpms:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109502])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_vrr@flip-dpms.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2437])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2437]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-a-source-outp-complete:
- shard-iclb: NOTRUN -> [SKIP][79] ([i915#2530])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@nouveau_crc@pipe-a-source-outp-complete.html
* igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109278] / [i915#2530])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][81] -> [FAIL][82] ([i915#1722])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl4/igt@perf@polling-small-buf.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl2/igt@perf@polling-small-buf.html
* igt@perf_pmu@module-unload:
- shard-apl: [PASS][83] -> [INCOMPLETE][84] ([i915#1373] / [i915#262])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl4/igt@perf_pmu@module-unload.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl1/igt@perf_pmu@module-unload.html
* igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109291]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@prime_nv_api@i915_nv_import_twice_check_flink_name.html
* igt@prime_nv_api@i915_self_import:
- shard-skl: NOTRUN -> [SKIP][86] ([fdo#109271]) +341 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl1/igt@prime_nv_api@i915_self_import.html
* igt@sysfs_clients@busy:
- shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2994]) +4 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@sysfs_clients@busy.html
#### Possible fixes ####
* igt@fbdev@nullptr:
- shard-skl: [DMESG-WARN][88] ([i915#1982]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl7/igt@fbdev@nullptr.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl4/igt@fbdev@nullptr.html
* igt@gem_ctx_persistence@many-contexts:
- {shard-rkl}: [FAIL][90] ([i915#2410]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-rkl-5/igt@gem_ctx_persistence@many-contexts.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-rkl-5/igt@gem_ctx_persistence@many-contexts.html
- shard-iclb: [FAIL][92] ([i915#2410]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb5/igt@gem_ctx_persistence@many-contexts.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb8/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [FAIL][94] ([i915#2842]) -> [PASS][95] +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl3/igt@gem_exec_fair@basic-none@rcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl4/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_nop@basic-series:
- shard-glk: [DMESG-WARN][98] ([i915#118]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-glk2/igt@gem_exec_nop@basic-series.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk2/igt@gem_exec_nop@basic-series.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][100] ([i915#1436] / [i915#716]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-glk6/igt@gen9_exec_parse@allowed-all.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-iclb: [INCOMPLETE][102] -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb4/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-tglb: [SKIP][104] ([i915#579]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb3/igt@i915_pm_rpm@modeset-lpsp-stress.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb8/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_selftest@live@gem_contexts:
- shard-tglb: [DMESG-WARN][106] ([i915#2867]) -> [PASS][107] +16 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb3/igt@i915_selftest@live@gem_contexts.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb8/igt@i915_selftest@live@gem_contexts.html
* igt@i915_suspend@forcewake:
- shard-kbl: [DMESG-WARN][108] ([i915#180]) -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl6/igt@i915_suspend@forcewake.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl6/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@linear-16bpp-rotate-0:
- {shard-tglu}: [DMESG-WARN][110] ([i915#402]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglu-2/igt@kms_big_fb@linear-16bpp-rotate-0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglu-4/igt@kms_big_fb@linear-16bpp-rotate-0.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][112] ([i915#79]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- {shard-rkl}: [SKIP][114] ([i915#4098]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a:
- shard-apl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117] +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl7/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][118] ([fdo#108145] / [i915#265]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][120] ([fdo#109441]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_rotation_crc@cursor-rotation-180:
- {shard-rkl}: [SKIP][122] ([i915#1845] / [i915#4098]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-rkl-4/igt@kms_rotation_crc@cursor-rotation-180.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-rkl-6/igt@kms_rotation_crc@cursor-rotation-180.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][124] ([i915#1542]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl6/igt@perf@polling-parameterized.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [DMESG-WARN][126] ([i915#5076]) -> [SKIP][127] ([i915#4525])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@gem_exec_balancer@parallel-bb-first.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [DMESG-FAIL][128] ([i915#5076]) -> [SKIP][129] ([i915#4525])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][130] ([i915#4525]) -> [DMESG-WARN][131] ([i915#5076]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][132] ([i915#2842]) -> [FAIL][133] ([i915#2851])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@i915_pm_dc@dc9-dpms:
- shard-skl: [SKIP][134] ([fdo#109271]) -> [SKIP][135] ([fdo#109271] / [i915#1888]) +1 similar issue
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl6/igt@i915_pm_dc@dc9-dpms.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-skl: [SKIP][136] ([fdo#109271] / [i915#1888] / [i915#3886]) -> [SKIP][137] ([fdo#109271] / [i915#3886])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl10/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
[137]: https://i
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/index.html
[-- Attachment #2: Type: text/html, Size: 33573 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
@ 2022-03-19 12:08 ` Michal Wajdeczko
-1 siblings, 0 replies; 40+ messages in thread
From: Michal Wajdeczko @ 2022-03-19 12:08 UTC (permalink / raw)
To: Andi Shyti, Intel GFX, DRI Devel
Cc: Abdiel Janulgue, Tvrtko Ursulin, Lucas De Marchi, Chris Wilson,
Daniele Ceraolo Spurio, Matthew Auld, Andi Shyti,
Sujaritha Sundaresan, Dale B Stimson
On 19.03.2022 00:39, Andi Shyti wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four GTs are supported in i915->gt[], with slot zero
> shadowing the existing i915->gt0 to enable source compatibility
> with legacy driver paths. A for_each_gt macro is added to iterate
> over the GTs and will be used by upcoming patches that convert
> various parts of the driver to be multi-gt aware.
>
> Only the primary/root tile is initialized for now; the other
> tiles will be detected and plugged in by future patches once the
> necessary infrastructure is in place to handle them.
>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@gmail.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 133 ++++++++++++++++--
> drivers/gpu/drm/i915/gt/intel_gt.h | 17 ++-
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
> drivers/gpu/drm/i915/i915_driver.c | 28 ++--
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/intel_memory_region.h | 3 +
> drivers/gpu/drm/i915/intel_uncore.c | 11 +-
> drivers/gpu/drm/i915/intel_uncore.h | 3 +-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 13 +-
> 10 files changed, 184 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index ca875ba3e2a9d..cfac4a913642e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -29,7 +29,7 @@
> #include "intel_uncore.h"
> #include "shmem_utils.h"
>
> -void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> +static void __intel_gt_init_early(struct intel_gt *gt)
> {
> spin_lock_init(>->irq_lock);
>
> @@ -51,17 +51,23 @@ void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> intel_rps_init_early(>->rps);
> }
>
> -void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> +/* Preliminary initialization of Tile 0 */
> +void intel_root_gt_init_early(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt = to_gt(i915);
> +
> gt->i915 = i915;
> gt->uncore = &i915->uncore;
> +
> + __intel_gt_init_early(gt);
> }
>
> -int intel_gt_probe_lmem(struct intel_gt *gt)
> +static int intel_gt_probe_lmem(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int instance = gt->info.id;
> + int id = INTEL_REGION_LMEM_0 + instance;
> struct intel_memory_region *mem;
> - int id;
> int err;
>
> mem = intel_gt_setup_lmem(gt);
> @@ -76,9 +82,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
> return err;
> }
>
> - id = INTEL_REGION_LMEM_0;
> -
> mem->id = id;
> + mem->instance = instance;
>
> intel_memory_region_set_name(mem, "local%u", mem->instance);
>
> @@ -807,16 +812,21 @@ void intel_gt_driver_release(struct intel_gt *gt)
> intel_gt_fini_hwconfig(gt);
> }
>
> -void intel_gt_driver_late_release(struct intel_gt *gt)
> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt;
> + unsigned int id;
> +
> /* We need to wait for inflight RCU frees to release their grip */
> rcu_barrier();
>
> - intel_uc_driver_late_release(>->uc);
> - intel_gt_fini_requests(gt);
> - intel_gt_fini_reset(gt);
> - intel_gt_fini_timelines(gt);
> - intel_engines_free(gt);
> + for_each_gt(gt, i915, id) {
> + intel_uc_driver_late_release(>->uc);
> + intel_gt_fini_requests(gt);
> + intel_gt_fini_reset(gt);
> + intel_gt_fini_timelines(gt);
> + intel_engines_free(gt);
> + }
> }
>
> /**
> @@ -1013,6 +1023,105 @@ void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
> }
> }
>
> +static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> +{
> + int ret;
> +
> + if (!gt_is_root(gt)) {
> + struct intel_uncore_mmio_debug *mmio_debug;
> + struct intel_uncore *uncore;
> +
> + uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
> + if (!uncore)
> + return -ENOMEM;
> +
> + mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
> + if (!mmio_debug) {
> + kfree(uncore);
> + return -ENOMEM;
> + }
> +
> + gt->uncore = uncore;
> + gt->uncore->debug = mmio_debug;
> +
> + __intel_gt_init_early(gt);
> + }
> +
> + intel_uncore_init_early(gt->uncore, gt);
> +
> + ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
> + if (ret)
> + return ret;
(little guessing as in this patch we don't have non-root gt yet)
if the future, when we will be doing setup of non-root gt, if we return
here then likely we will leak both uncore/mmio_debug as gt will not be
added to i915->gts thus it will not be visible in for_each_gt loop used
to release/cleanup all gts.
since in above code you are doing cleanup in case of kzalloc failure,
same should be done in case of mmio setup failure.
Michal
> +
> + gt->phys_addr = phys_addr;
> +
> + return 0;
> +}
> +
> +static void
> +intel_gt_tile_cleanup(struct intel_gt *gt)
> +{
> + intel_uncore_cleanup_mmio(gt->uncore);
> +
> + if (!gt_is_root(gt)) {
> + kfree(gt->uncore->debug);
> + kfree(gt->uncore);
> + kfree(gt);
> + }
> +}
> +
> +int intel_gt_probe_all(struct drm_i915_private *i915)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct intel_gt *gt = &i915->gt0;
> + phys_addr_t phys_addr;
> + unsigned int mmio_bar;
> + int ret;
> +
> + mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
> + phys_addr = pci_resource_start(pdev, mmio_bar);
> +
> + /*
> + * We always have at least one primary GT on any device
> + * and it has been already initialized early during probe
> + * in i915_driver_probe()
> + */
> + ret = intel_gt_tile_setup(gt, phys_addr);
> + if (ret)
> + return ret;
> +
> + i915->gt[0] = gt;
> +
> + /* TODO: add more tiles */
> + return 0;
> +}
> +
> +int intel_gt_tiles_init(struct drm_i915_private *i915)
> +{
> + struct intel_gt *gt;
> + unsigned int id;
> + int ret;
> +
> + for_each_gt(gt, i915, id) {
> + ret = intel_gt_probe_lmem(gt);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +void intel_gt_release_all(struct drm_i915_private *i915)
> +{
> + struct intel_gt *gt;
> + unsigned int id;
> +
> + for_each_gt(gt, i915, id) {
> + intel_gt_tile_cleanup(gt);
> + i915->gt[id] = NULL;
> + }
> +}
> +
> void intel_gt_info_print(const struct intel_gt_info *info,
> struct drm_printer *p)
> {
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index ce471aa5c83d7..e76168e10a21b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -39,10 +39,8 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
> return container_of(huc, struct intel_gt, uc.huc);
> }
>
> -void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
> -void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
> +void intel_root_gt_init_early(struct drm_i915_private *i915);
> int intel_gt_assign_ggtt(struct intel_gt *gt);
> -int intel_gt_probe_lmem(struct intel_gt *gt);
> int intel_gt_init_mmio(struct intel_gt *gt);
> int __must_check intel_gt_init_hw(struct intel_gt *gt);
> int intel_gt_init(struct intel_gt *gt);
> @@ -52,7 +50,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt);
> void intel_gt_driver_remove(struct intel_gt *gt);
> void intel_gt_driver_release(struct intel_gt *gt);
>
> -void intel_gt_driver_late_release(struct intel_gt *gt);
> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
>
> int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
>
> @@ -97,6 +95,17 @@ u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
>
> void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
> bool dump_table);
> +
> +int intel_gt_probe_all(struct drm_i915_private *i915);
> +int intel_gt_tiles_init(struct drm_i915_private *i915);
> +void intel_gt_release_all(struct drm_i915_private *i915);
> +
> +#define for_each_gt(gt__, i915__, id__) \
> + for ((id__) = 0; \
> + (id__) < I915_MAX_GT; \
> + (id__)++) \
> + for_each_if(((gt__) = (i915__)->gt[(id__)]))
> +
> void intel_gt_info_print(const struct intel_gt_info *info,
> struct drm_printer *p);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index e4ecc17889d34..eeead40485fbc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -129,7 +129,14 @@ static const struct intel_wakeref_ops wf_ops = {
>
> void intel_gt_pm_init_early(struct intel_gt *gt)
> {
> - intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
> + /*
> + * We access the runtime_pm structure via gt->i915 here rather than
> + * gt->uncore as we do elsewhere in the file because gt->uncore is not
> + * yet initialized for all tiles at this point in the driver startup.
> + * runtime_pm is per-device rather than per-tile, so this is still the
> + * correct structure.
> + */
> + intel_wakeref_init(>->wakeref, >->i915->runtime_pm, &wf_ops);
> seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index bbba885d45bd5..937b2e1a305ed 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -188,7 +188,14 @@ struct intel_gt {
> u8 instanceid;
> } default_steering;
>
> + /*
> + * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT.
> + */
> + phys_addr_t phys_addr;
> +
> struct intel_gt_info {
> + unsigned int id;
> +
> intel_engine_mask_t engine_mask;
>
> u32 l3bank_mask;
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 92a625a174e22..64e6f76861f95 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -321,9 +321,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> intel_device_info_subplatform_init(dev_priv);
> intel_step_init(dev_priv);
>
> - intel_gt_init_early(to_gt(dev_priv), dev_priv);
> intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
> - intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv));
>
> spin_lock_init(&dev_priv->irq_lock);
> spin_lock_init(&dev_priv->gpu_error.lock);
> @@ -354,7 +352,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> intel_wopcm_init_early(&dev_priv->wopcm);
>
> - __intel_gt_init_early(to_gt(dev_priv), dev_priv);
> + intel_root_gt_init_early(dev_priv);
>
> i915_gem_init_early(dev_priv);
>
> @@ -375,7 +373,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> err_gem:
> i915_gem_cleanup_early(dev_priv);
> - intel_gt_driver_late_release(to_gt(dev_priv));
> + intel_gt_driver_late_release_all(dev_priv);
> intel_region_ttm_device_fini(dev_priv);
> err_ttm:
> vlv_suspend_cleanup(dev_priv);
> @@ -394,7 +392,7 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv)
> intel_irq_fini(dev_priv);
> intel_power_domains_cleanup(dev_priv);
> i915_gem_cleanup_early(dev_priv);
> - intel_gt_driver_late_release(to_gt(dev_priv));
> + intel_gt_driver_late_release_all(dev_priv);
> intel_region_ttm_device_fini(dev_priv);
> vlv_suspend_cleanup(dev_priv);
> i915_workqueues_cleanup(dev_priv);
> @@ -425,13 +423,9 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
> if (ret < 0)
> return ret;
>
> - ret = intel_uncore_setup_mmio(&dev_priv->uncore);
> - if (ret < 0)
> - goto err_bridge;
> -
> ret = intel_uncore_init_mmio(&dev_priv->uncore);
> if (ret)
> - goto err_mmio;
> + return ret;
>
> /* Try to make sure MCHBAR is enabled before poking at it */
> intel_setup_mchbar(dev_priv);
> @@ -449,9 +443,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
> err_uncore:
> intel_teardown_mchbar(dev_priv);
> intel_uncore_fini_mmio(&dev_priv->uncore);
> -err_mmio:
> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
> -err_bridge:
> pci_dev_put(dev_priv->bridge_dev);
>
> return ret;
> @@ -465,7 +456,6 @@ static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
> {
> intel_teardown_mchbar(dev_priv);
> intel_uncore_fini_mmio(&dev_priv->uncore);
> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
> pci_dev_put(dev_priv->bridge_dev);
> }
>
> @@ -598,7 +588,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
> if (ret)
> goto err_ggtt;
>
> - ret = intel_gt_probe_lmem(to_gt(dev_priv));
> + ret = intel_gt_tiles_init(dev_priv);
> if (ret)
> goto err_mem_regions;
>
> @@ -849,10 +839,14 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>
> intel_vgpu_detect(i915);
>
> - ret = i915_driver_mmio_probe(i915);
> + ret = intel_gt_probe_all(i915);
> if (ret < 0)
> goto out_runtime_pm_put;
>
> + ret = i915_driver_mmio_probe(i915);
> + if (ret < 0)
> + goto out_tiles_cleanup;
> +
> ret = i915_driver_hw_probe(i915);
> if (ret < 0)
> goto out_cleanup_mmio;
> @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> i915_ggtt_driver_late_release(i915);
> out_cleanup_mmio:
> i915_driver_mmio_release(i915);
> +out_tiles_cleanup:
> + intel_gt_release_all(i915);
> out_runtime_pm_put:
> enable_rpm_wakeref_asserts(&i915->runtime_pm);
> i915_driver_late_release(i915);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 97622d3ccfc2a..8e4083d413592 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -777,6 +777,12 @@ struct drm_i915_private {
> /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
> struct intel_gt gt0;
>
> + /*
> + * i915->gt[0] == &i915->gt0
> + */
> +#define I915_MAX_GT 4
> + struct intel_gt *gt[I915_MAX_GT];
> +
> struct {
> struct i915_gem_contexts {
> spinlock_t lock; /* locks list */
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
> index cc7078bcbfbfc..3d8378c1b4478 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.h
> +++ b/drivers/gpu/drm/i915/intel_memory_region.h
> @@ -30,6 +30,9 @@ enum intel_memory_type {
> enum intel_region_id {
> INTEL_REGION_SMEM = 0,
> INTEL_REGION_LMEM_0,
> + INTEL_REGION_LMEM_1,
> + INTEL_REGION_LMEM_2,
> + INTEL_REGION_LMEM_3,
> INTEL_REGION_STOLEN_SMEM,
> INTEL_REGION_STOLEN_LMEM,
> INTEL_REGION_UNKNOWN, /* Should be last */
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index ef8ffc01ad19c..8b9caaaacc21f 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2039,14 +2039,11 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
> return NOTIFY_OK;
> }
>
> -int intel_uncore_setup_mmio(struct intel_uncore *uncore)
> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
> {
> struct drm_i915_private *i915 = uncore->i915;
> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> - int mmio_bar;
> int mmio_size;
>
> - mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
> /*
> * Before gen4, the registers and the GTT are behind different BARs.
> * However, from gen4 onwards, the registers and the GTT are shared
> @@ -2063,7 +2060,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
> else
> mmio_size = 2 * 1024 * 1024;
>
> - uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
> + uncore->regs = ioremap(phys_addr, mmio_size);
> if (uncore->regs == NULL) {
> drm_err(&i915->drm, "failed to map registers\n");
> return -EIO;
> @@ -2074,9 +2071,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
>
> void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
> {
> - struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
> -
> - pci_iounmap(pdev, uncore->regs);
> + iounmap(uncore->regs);
> }
>
> void intel_uncore_init_early(struct intel_uncore *uncore,
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 9a760952d46af..52fe3d89dd2b8 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -29,6 +29,7 @@
> #include <linux/notifier.h>
> #include <linux/hrtimer.h>
> #include <linux/io-64-nonatomic-lo-hi.h>
> +#include <linux/types.h>
>
> #include "i915_reg_defs.h"
>
> @@ -221,7 +222,7 @@ void
> intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
> void intel_uncore_init_early(struct intel_uncore *uncore,
> struct intel_gt *gt);
> -int intel_uncore_setup_mmio(struct intel_uncore *uncore);
> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
> int intel_uncore_init_mmio(struct intel_uncore *uncore);
> void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
> struct intel_gt *gt);
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 573d9b2e1a4a3..9c31a16f83800 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -73,7 +73,7 @@ static void mock_device_release(struct drm_device *dev)
> destroy_workqueue(i915->wq);
>
> intel_region_ttm_device_fini(i915);
> - intel_gt_driver_late_release(to_gt(i915));
> + intel_gt_driver_late_release_all(i915);
> intel_memory_regions_driver_release(i915);
>
> drm_mode_config_cleanup(&i915->drm);
> @@ -112,6 +112,11 @@ static struct dev_pm_domain pm_domain = {
> },
> };
>
> +static void mock_gt_probe(struct drm_i915_private *i915)
> +{
> + i915->gt[0] = &i915->gt0;
> +}
> +
> struct drm_i915_private *mock_gem_device(void)
> {
> #if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU)
> @@ -180,11 +185,11 @@ struct drm_i915_private *mock_gem_device(void)
> spin_lock_init(&i915->gpu_error.lock);
>
> i915_gem_init__mm(i915);
> - intel_gt_init_early(to_gt(i915), i915);
> - __intel_gt_init_early(to_gt(i915), i915);
> + intel_root_gt_init_early(i915);
> mock_uncore_init(&i915->uncore, i915);
> atomic_inc(&to_gt(i915)->wakeref.count); /* disable; no hw support */
> to_gt(i915)->awake = -ENODEV;
> + mock_gt_probe(i915);
>
> ret = intel_region_ttm_device_init(i915);
> if (ret)
> @@ -229,7 +234,7 @@ struct drm_i915_private *mock_gem_device(void)
> err_drv:
> intel_region_ttm_device_fini(i915);
> err_ttm:
> - intel_gt_driver_late_release(to_gt(i915));
> + intel_gt_driver_late_release_all(i915);
> intel_memory_regions_driver_release(i915);
> drm_mode_config_cleanup(&i915->drm);
> mock_destroy_device(i915);
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
@ 2022-03-19 12:08 ` Michal Wajdeczko
0 siblings, 0 replies; 40+ messages in thread
From: Michal Wajdeczko @ 2022-03-19 12:08 UTC (permalink / raw)
To: Andi Shyti, Intel GFX, DRI Devel
Cc: Lucas De Marchi, Chris Wilson, Matthew Auld
On 19.03.2022 00:39, Andi Shyti wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four GTs are supported in i915->gt[], with slot zero
> shadowing the existing i915->gt0 to enable source compatibility
> with legacy driver paths. A for_each_gt macro is added to iterate
> over the GTs and will be used by upcoming patches that convert
> various parts of the driver to be multi-gt aware.
>
> Only the primary/root tile is initialized for now; the other
> tiles will be detected and plugged in by future patches once the
> necessary infrastructure is in place to handle them.
>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@gmail.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 133 ++++++++++++++++--
> drivers/gpu/drm/i915/gt/intel_gt.h | 17 ++-
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
> drivers/gpu/drm/i915/i915_driver.c | 28 ++--
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/intel_memory_region.h | 3 +
> drivers/gpu/drm/i915/intel_uncore.c | 11 +-
> drivers/gpu/drm/i915/intel_uncore.h | 3 +-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 13 +-
> 10 files changed, 184 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index ca875ba3e2a9d..cfac4a913642e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -29,7 +29,7 @@
> #include "intel_uncore.h"
> #include "shmem_utils.h"
>
> -void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> +static void __intel_gt_init_early(struct intel_gt *gt)
> {
> spin_lock_init(>->irq_lock);
>
> @@ -51,17 +51,23 @@ void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> intel_rps_init_early(>->rps);
> }
>
> -void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> +/* Preliminary initialization of Tile 0 */
> +void intel_root_gt_init_early(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt = to_gt(i915);
> +
> gt->i915 = i915;
> gt->uncore = &i915->uncore;
> +
> + __intel_gt_init_early(gt);
> }
>
> -int intel_gt_probe_lmem(struct intel_gt *gt)
> +static int intel_gt_probe_lmem(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int instance = gt->info.id;
> + int id = INTEL_REGION_LMEM_0 + instance;
> struct intel_memory_region *mem;
> - int id;
> int err;
>
> mem = intel_gt_setup_lmem(gt);
> @@ -76,9 +82,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
> return err;
> }
>
> - id = INTEL_REGION_LMEM_0;
> -
> mem->id = id;
> + mem->instance = instance;
>
> intel_memory_region_set_name(mem, "local%u", mem->instance);
>
> @@ -807,16 +812,21 @@ void intel_gt_driver_release(struct intel_gt *gt)
> intel_gt_fini_hwconfig(gt);
> }
>
> -void intel_gt_driver_late_release(struct intel_gt *gt)
> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt;
> + unsigned int id;
> +
> /* We need to wait for inflight RCU frees to release their grip */
> rcu_barrier();
>
> - intel_uc_driver_late_release(>->uc);
> - intel_gt_fini_requests(gt);
> - intel_gt_fini_reset(gt);
> - intel_gt_fini_timelines(gt);
> - intel_engines_free(gt);
> + for_each_gt(gt, i915, id) {
> + intel_uc_driver_late_release(>->uc);
> + intel_gt_fini_requests(gt);
> + intel_gt_fini_reset(gt);
> + intel_gt_fini_timelines(gt);
> + intel_engines_free(gt);
> + }
> }
>
> /**
> @@ -1013,6 +1023,105 @@ void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
> }
> }
>
> +static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> +{
> + int ret;
> +
> + if (!gt_is_root(gt)) {
> + struct intel_uncore_mmio_debug *mmio_debug;
> + struct intel_uncore *uncore;
> +
> + uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
> + if (!uncore)
> + return -ENOMEM;
> +
> + mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
> + if (!mmio_debug) {
> + kfree(uncore);
> + return -ENOMEM;
> + }
> +
> + gt->uncore = uncore;
> + gt->uncore->debug = mmio_debug;
> +
> + __intel_gt_init_early(gt);
> + }
> +
> + intel_uncore_init_early(gt->uncore, gt);
> +
> + ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
> + if (ret)
> + return ret;
(little guessing as in this patch we don't have non-root gt yet)
if the future, when we will be doing setup of non-root gt, if we return
here then likely we will leak both uncore/mmio_debug as gt will not be
added to i915->gts thus it will not be visible in for_each_gt loop used
to release/cleanup all gts.
since in above code you are doing cleanup in case of kzalloc failure,
same should be done in case of mmio setup failure.
Michal
> +
> + gt->phys_addr = phys_addr;
> +
> + return 0;
> +}
> +
> +static void
> +intel_gt_tile_cleanup(struct intel_gt *gt)
> +{
> + intel_uncore_cleanup_mmio(gt->uncore);
> +
> + if (!gt_is_root(gt)) {
> + kfree(gt->uncore->debug);
> + kfree(gt->uncore);
> + kfree(gt);
> + }
> +}
> +
> +int intel_gt_probe_all(struct drm_i915_private *i915)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct intel_gt *gt = &i915->gt0;
> + phys_addr_t phys_addr;
> + unsigned int mmio_bar;
> + int ret;
> +
> + mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
> + phys_addr = pci_resource_start(pdev, mmio_bar);
> +
> + /*
> + * We always have at least one primary GT on any device
> + * and it has been already initialized early during probe
> + * in i915_driver_probe()
> + */
> + ret = intel_gt_tile_setup(gt, phys_addr);
> + if (ret)
> + return ret;
> +
> + i915->gt[0] = gt;
> +
> + /* TODO: add more tiles */
> + return 0;
> +}
> +
> +int intel_gt_tiles_init(struct drm_i915_private *i915)
> +{
> + struct intel_gt *gt;
> + unsigned int id;
> + int ret;
> +
> + for_each_gt(gt, i915, id) {
> + ret = intel_gt_probe_lmem(gt);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +void intel_gt_release_all(struct drm_i915_private *i915)
> +{
> + struct intel_gt *gt;
> + unsigned int id;
> +
> + for_each_gt(gt, i915, id) {
> + intel_gt_tile_cleanup(gt);
> + i915->gt[id] = NULL;
> + }
> +}
> +
> void intel_gt_info_print(const struct intel_gt_info *info,
> struct drm_printer *p)
> {
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index ce471aa5c83d7..e76168e10a21b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -39,10 +39,8 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
> return container_of(huc, struct intel_gt, uc.huc);
> }
>
> -void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
> -void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
> +void intel_root_gt_init_early(struct drm_i915_private *i915);
> int intel_gt_assign_ggtt(struct intel_gt *gt);
> -int intel_gt_probe_lmem(struct intel_gt *gt);
> int intel_gt_init_mmio(struct intel_gt *gt);
> int __must_check intel_gt_init_hw(struct intel_gt *gt);
> int intel_gt_init(struct intel_gt *gt);
> @@ -52,7 +50,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt);
> void intel_gt_driver_remove(struct intel_gt *gt);
> void intel_gt_driver_release(struct intel_gt *gt);
>
> -void intel_gt_driver_late_release(struct intel_gt *gt);
> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
>
> int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
>
> @@ -97,6 +95,17 @@ u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
>
> void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
> bool dump_table);
> +
> +int intel_gt_probe_all(struct drm_i915_private *i915);
> +int intel_gt_tiles_init(struct drm_i915_private *i915);
> +void intel_gt_release_all(struct drm_i915_private *i915);
> +
> +#define for_each_gt(gt__, i915__, id__) \
> + for ((id__) = 0; \
> + (id__) < I915_MAX_GT; \
> + (id__)++) \
> + for_each_if(((gt__) = (i915__)->gt[(id__)]))
> +
> void intel_gt_info_print(const struct intel_gt_info *info,
> struct drm_printer *p);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index e4ecc17889d34..eeead40485fbc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -129,7 +129,14 @@ static const struct intel_wakeref_ops wf_ops = {
>
> void intel_gt_pm_init_early(struct intel_gt *gt)
> {
> - intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
> + /*
> + * We access the runtime_pm structure via gt->i915 here rather than
> + * gt->uncore as we do elsewhere in the file because gt->uncore is not
> + * yet initialized for all tiles at this point in the driver startup.
> + * runtime_pm is per-device rather than per-tile, so this is still the
> + * correct structure.
> + */
> + intel_wakeref_init(>->wakeref, >->i915->runtime_pm, &wf_ops);
> seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index bbba885d45bd5..937b2e1a305ed 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -188,7 +188,14 @@ struct intel_gt {
> u8 instanceid;
> } default_steering;
>
> + /*
> + * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT.
> + */
> + phys_addr_t phys_addr;
> +
> struct intel_gt_info {
> + unsigned int id;
> +
> intel_engine_mask_t engine_mask;
>
> u32 l3bank_mask;
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 92a625a174e22..64e6f76861f95 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -321,9 +321,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> intel_device_info_subplatform_init(dev_priv);
> intel_step_init(dev_priv);
>
> - intel_gt_init_early(to_gt(dev_priv), dev_priv);
> intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
> - intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv));
>
> spin_lock_init(&dev_priv->irq_lock);
> spin_lock_init(&dev_priv->gpu_error.lock);
> @@ -354,7 +352,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> intel_wopcm_init_early(&dev_priv->wopcm);
>
> - __intel_gt_init_early(to_gt(dev_priv), dev_priv);
> + intel_root_gt_init_early(dev_priv);
>
> i915_gem_init_early(dev_priv);
>
> @@ -375,7 +373,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> err_gem:
> i915_gem_cleanup_early(dev_priv);
> - intel_gt_driver_late_release(to_gt(dev_priv));
> + intel_gt_driver_late_release_all(dev_priv);
> intel_region_ttm_device_fini(dev_priv);
> err_ttm:
> vlv_suspend_cleanup(dev_priv);
> @@ -394,7 +392,7 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv)
> intel_irq_fini(dev_priv);
> intel_power_domains_cleanup(dev_priv);
> i915_gem_cleanup_early(dev_priv);
> - intel_gt_driver_late_release(to_gt(dev_priv));
> + intel_gt_driver_late_release_all(dev_priv);
> intel_region_ttm_device_fini(dev_priv);
> vlv_suspend_cleanup(dev_priv);
> i915_workqueues_cleanup(dev_priv);
> @@ -425,13 +423,9 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
> if (ret < 0)
> return ret;
>
> - ret = intel_uncore_setup_mmio(&dev_priv->uncore);
> - if (ret < 0)
> - goto err_bridge;
> -
> ret = intel_uncore_init_mmio(&dev_priv->uncore);
> if (ret)
> - goto err_mmio;
> + return ret;
>
> /* Try to make sure MCHBAR is enabled before poking at it */
> intel_setup_mchbar(dev_priv);
> @@ -449,9 +443,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
> err_uncore:
> intel_teardown_mchbar(dev_priv);
> intel_uncore_fini_mmio(&dev_priv->uncore);
> -err_mmio:
> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
> -err_bridge:
> pci_dev_put(dev_priv->bridge_dev);
>
> return ret;
> @@ -465,7 +456,6 @@ static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
> {
> intel_teardown_mchbar(dev_priv);
> intel_uncore_fini_mmio(&dev_priv->uncore);
> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
> pci_dev_put(dev_priv->bridge_dev);
> }
>
> @@ -598,7 +588,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
> if (ret)
> goto err_ggtt;
>
> - ret = intel_gt_probe_lmem(to_gt(dev_priv));
> + ret = intel_gt_tiles_init(dev_priv);
> if (ret)
> goto err_mem_regions;
>
> @@ -849,10 +839,14 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>
> intel_vgpu_detect(i915);
>
> - ret = i915_driver_mmio_probe(i915);
> + ret = intel_gt_probe_all(i915);
> if (ret < 0)
> goto out_runtime_pm_put;
>
> + ret = i915_driver_mmio_probe(i915);
> + if (ret < 0)
> + goto out_tiles_cleanup;
> +
> ret = i915_driver_hw_probe(i915);
> if (ret < 0)
> goto out_cleanup_mmio;
> @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> i915_ggtt_driver_late_release(i915);
> out_cleanup_mmio:
> i915_driver_mmio_release(i915);
> +out_tiles_cleanup:
> + intel_gt_release_all(i915);
> out_runtime_pm_put:
> enable_rpm_wakeref_asserts(&i915->runtime_pm);
> i915_driver_late_release(i915);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 97622d3ccfc2a..8e4083d413592 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -777,6 +777,12 @@ struct drm_i915_private {
> /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
> struct intel_gt gt0;
>
> + /*
> + * i915->gt[0] == &i915->gt0
> + */
> +#define I915_MAX_GT 4
> + struct intel_gt *gt[I915_MAX_GT];
> +
> struct {
> struct i915_gem_contexts {
> spinlock_t lock; /* locks list */
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
> index cc7078bcbfbfc..3d8378c1b4478 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.h
> +++ b/drivers/gpu/drm/i915/intel_memory_region.h
> @@ -30,6 +30,9 @@ enum intel_memory_type {
> enum intel_region_id {
> INTEL_REGION_SMEM = 0,
> INTEL_REGION_LMEM_0,
> + INTEL_REGION_LMEM_1,
> + INTEL_REGION_LMEM_2,
> + INTEL_REGION_LMEM_3,
> INTEL_REGION_STOLEN_SMEM,
> INTEL_REGION_STOLEN_LMEM,
> INTEL_REGION_UNKNOWN, /* Should be last */
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index ef8ffc01ad19c..8b9caaaacc21f 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2039,14 +2039,11 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
> return NOTIFY_OK;
> }
>
> -int intel_uncore_setup_mmio(struct intel_uncore *uncore)
> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
> {
> struct drm_i915_private *i915 = uncore->i915;
> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> - int mmio_bar;
> int mmio_size;
>
> - mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
> /*
> * Before gen4, the registers and the GTT are behind different BARs.
> * However, from gen4 onwards, the registers and the GTT are shared
> @@ -2063,7 +2060,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
> else
> mmio_size = 2 * 1024 * 1024;
>
> - uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
> + uncore->regs = ioremap(phys_addr, mmio_size);
> if (uncore->regs == NULL) {
> drm_err(&i915->drm, "failed to map registers\n");
> return -EIO;
> @@ -2074,9 +2071,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
>
> void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
> {
> - struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
> -
> - pci_iounmap(pdev, uncore->regs);
> + iounmap(uncore->regs);
> }
>
> void intel_uncore_init_early(struct intel_uncore *uncore,
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 9a760952d46af..52fe3d89dd2b8 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -29,6 +29,7 @@
> #include <linux/notifier.h>
> #include <linux/hrtimer.h>
> #include <linux/io-64-nonatomic-lo-hi.h>
> +#include <linux/types.h>
>
> #include "i915_reg_defs.h"
>
> @@ -221,7 +222,7 @@ void
> intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
> void intel_uncore_init_early(struct intel_uncore *uncore,
> struct intel_gt *gt);
> -int intel_uncore_setup_mmio(struct intel_uncore *uncore);
> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
> int intel_uncore_init_mmio(struct intel_uncore *uncore);
> void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
> struct intel_gt *gt);
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 573d9b2e1a4a3..9c31a16f83800 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -73,7 +73,7 @@ static void mock_device_release(struct drm_device *dev)
> destroy_workqueue(i915->wq);
>
> intel_region_ttm_device_fini(i915);
> - intel_gt_driver_late_release(to_gt(i915));
> + intel_gt_driver_late_release_all(i915);
> intel_memory_regions_driver_release(i915);
>
> drm_mode_config_cleanup(&i915->drm);
> @@ -112,6 +112,11 @@ static struct dev_pm_domain pm_domain = {
> },
> };
>
> +static void mock_gt_probe(struct drm_i915_private *i915)
> +{
> + i915->gt[0] = &i915->gt0;
> +}
> +
> struct drm_i915_private *mock_gem_device(void)
> {
> #if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU)
> @@ -180,11 +185,11 @@ struct drm_i915_private *mock_gem_device(void)
> spin_lock_init(&i915->gpu_error.lock);
>
> i915_gem_init__mm(i915);
> - intel_gt_init_early(to_gt(i915), i915);
> - __intel_gt_init_early(to_gt(i915), i915);
> + intel_root_gt_init_early(i915);
> mock_uncore_init(&i915->uncore, i915);
> atomic_inc(&to_gt(i915)->wakeref.count); /* disable; no hw support */
> to_gt(i915)->awake = -ENODEV;
> + mock_gt_probe(i915);
>
> ret = intel_region_ttm_device_init(i915);
> if (ret)
> @@ -229,7 +234,7 @@ struct drm_i915_private *mock_gem_device(void)
> err_drv:
> intel_region_ttm_device_fini(i915);
> err_ttm:
> - intel_gt_driver_late_release(to_gt(i915));
> + intel_gt_driver_late_release_all(i915);
> intel_memory_regions_driver_release(i915);
> drm_mode_config_cleanup(&i915->drm);
> mock_destroy_device(i915);
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
2022-03-19 12:08 ` [Intel-gfx] " Michal Wajdeczko
@ 2022-03-20 15:51 ` Andi Shyti
-1 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-20 15:51 UTC (permalink / raw)
To: Michal Wajdeczko
Cc: Abdiel Janulgue, Andi Shyti, Tvrtko Ursulin, Intel GFX,
Lucas De Marchi, DRI Devel, Chris Wilson, Daniele Ceraolo Spurio,
Matthew Auld, Andi Shyti, Sujaritha Sundaresan, Dale B Stimson
Hi Michal,
[...]
> > +static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> > +{
> > + int ret;
> > +
> > + if (!gt_is_root(gt)) {
> > + struct intel_uncore_mmio_debug *mmio_debug;
> > + struct intel_uncore *uncore;
> > +
> > + uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
> > + if (!uncore)
> > + return -ENOMEM;
> > +
> > + mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
> > + if (!mmio_debug) {
> > + kfree(uncore);
> > + return -ENOMEM;
> > + }
> > +
> > + gt->uncore = uncore;
> > + gt->uncore->debug = mmio_debug;
> > +
> > + __intel_gt_init_early(gt);
> > + }
> > +
> > + intel_uncore_init_early(gt->uncore, gt);
> > +
> > + ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
> > + if (ret)
> > + return ret;
>
> (little guessing as in this patch we don't have non-root gt yet)
>
> if the future, when we will be doing setup of non-root gt, if we return
> here then likely we will leak both uncore/mmio_debug as gt will not be
> added to i915->gts thus it will not be visible in for_each_gt loop used
> to release/cleanup all gts.
>
> since in above code you are doing cleanup in case of kzalloc failure,
> same should be done in case of mmio setup failure.
that's a good point. In the next patch I am going to add support
for the first multitile platform and, because it's too old to
remember, I had a look and I think this part is not properly
managed.
Thanks for the note!
Andi
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
@ 2022-03-20 15:51 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-03-20 15:51 UTC (permalink / raw)
To: Michal Wajdeczko
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson, Matthew Auld
Hi Michal,
[...]
> > +static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> > +{
> > + int ret;
> > +
> > + if (!gt_is_root(gt)) {
> > + struct intel_uncore_mmio_debug *mmio_debug;
> > + struct intel_uncore *uncore;
> > +
> > + uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
> > + if (!uncore)
> > + return -ENOMEM;
> > +
> > + mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
> > + if (!mmio_debug) {
> > + kfree(uncore);
> > + return -ENOMEM;
> > + }
> > +
> > + gt->uncore = uncore;
> > + gt->uncore->debug = mmio_debug;
> > +
> > + __intel_gt_init_early(gt);
> > + }
> > +
> > + intel_uncore_init_early(gt->uncore, gt);
> > +
> > + ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
> > + if (ret)
> > + return ret;
>
> (little guessing as in this patch we don't have non-root gt yet)
>
> if the future, when we will be doing setup of non-root gt, if we return
> here then likely we will leak both uncore/mmio_debug as gt will not be
> added to i915->gts thus it will not be visible in for_each_gt loop used
> to release/cleanup all gts.
>
> since in above code you are doing cleanup in case of kzalloc failure,
> same should be done in case of mmio setup failure.
that's a good point. In the next patch I am going to add support
for the first multitile platform and, because it's too old to
remember, I had a look and I think this part is not properly
managed.
Thanks for the note!
Andi
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce multitile support
2022-03-19 2:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-03-21 10:05 ` Matthew Auld
2022-03-21 16:44 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 40+ messages in thread
From: Matthew Auld @ 2022-03-21 10:05 UTC (permalink / raw)
To: Intel Graphics Development, lakshminarayana.vudum
On Sat, 19 Mar 2022 at 02:06, Patchwork
<patchwork@emeril.freedesktop.org> wrote:
>
> Patch Details
> Series:Introduce multitile support
> URL:https://patchwork.freedesktop.org/series/101551/
> State:failure
> Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/index.html
>
> CI Bug Log - changes from CI_DRM_11384_full -> Patchwork_22617_full
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with Patchwork_22617_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_22617_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> Participating hosts (12 -> 12)
>
> No changes in participating hosts
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in Patchwork_22617_full:
>
> IGT changes
>
> Possible regressions
>
> igt@gem_workarounds@suspend-resume:
>
> shard-kbl: PASS -> INCOMPLETE
Unrelated failure. Looks like filesystem related issue:
<4>[ 122.379815] EXT4-fs warning (device nvme0n1p2):
ext4_end_bio:346: I/O error 10 writing to inode 27001858 starting
block 13317428)
<6>[ 122.379827] nvme0n1: detected capacity change from 1000215216 to 0
<3>[ 122.379933] Buffer I/O error on device nvme0n1p2, logical block 13186100
<2>[ 122.380063] EXT4-fs error (device nvme0n1p2):
__ext4_find_entry:1614: inode #24510583: comm systemd-udevd: reading
directory lblock 0
<3>[ 122.380358] Aborting journal on device nvme0n1p2-8.
<2>[ 122.380488] EXT4-fs error (device nvme0n1p2) in
ext4_reserve_inode_write:5706: Journal has aborted
<2>[ 122.380612] EXT4-fs error (device nvme0n1p2):
ext4_journal_check_start:83: comm dmesg: Detected aborted journal
<3>[ 122.380671] Buffer I/O error on dev nvme0n1p2, logical block
62423040, lost sync page write
<3>[ 122.380721] JBD2: Error -5 detected when updating journal
superblock for nvme0n1p2-8.
<2>[ 122.380935] EXT4-fs error (device nvme0n1p2):
ext4_journal_check_start:83: comm rs:main Q:Reg: Detected aborted
journal
<4>[ 122.381311] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory
block
<4>[ 122.381428] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory
block
<4>[ 122.381517] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory
block
<4>[ 122.381588] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory
block
<4>[ 122.381659] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory
block
<3>[ 122.381728] Buffer I/O error on dev nvme0n1p2, logical block 0,
lost sync page write
<4>[ 122.381734] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory
block
<3>[ 122.381741] EXT4-fs (nvme0n1p2): I/O error while writing superblock
<0>[ 122.381744] Kernel panic - not syncing: EXT4-fs (device
nvme0n1p2): panic forced after error
<0>[ 122.381750] Kernel Offset: disabled
<4>[ 122.381762] CPU: 2 PID: 378 Comm: rs:main Q:Reg Not tainted
5.17.0-rc8-CI-Patchwork_22617+ #1
<4>[ 122.381766] Hardware name: /NUC7i5BNB, BIOS
BNKBL357.86A.0083.2020.0714.1344 07/14/2020
<4>[ 122.381771] Call Trace:
<4>[ 122.381775] <TASK>
<4>[ 122.381777] dump_stack_lvl+0x56/0x7b
<4>[ 122.381783] panic+0x12a/0x2c3
<4>[ 122.381794] ext4_handle_error.cold.167+0x13/0x13
<4>[ 122.381801] __ext4_error+0x104/0x1f0
<4>[ 122.381819] ext4_journal_check_start+0x84/0xa0
<4>[ 122.381823] __ext4_journal_start_sb+0x41/0x180
<4>[ 122.381829] ext4_dirty_inode+0x2f/0x70
<4>[ 122.381833] __mark_inode_dirty+0x181/0x580
<4>[ 122.381838] generic_update_time+0x98/0xc0
<4>[ 122.381842] file_update_time+0xc3/0x110
<4>[ 122.381844] ? generic_write_checks+0x5c/0xc0
<4>[ 122.381851] ext4_buffered_write_iter+0x4b/0x100
<4>[ 122.381858] ext4_file_write_iter+0x5a/0x830
<4>[ 122.381869] new_sync_write+0x120/0x1b0
<4>[ 122.381880] vfs_write+0x251/0x3b0
<4>[ 122.381886] ksys_write+0x5a/0xd0
<4>[ 122.381892] do_syscall_64+0x3a/0xb0
<4>[ 122.381896] entry_SYSCALL_64_after_hwframe+0x44/0xae
<4>[ 122.381899] RIP: 0033:0x7fd894e062cf
>
> Known issues
>
> Here are the changes found in Patchwork_22617_full that come from known issues:
>
> IGT changes
>
> Issues hit
>
> igt@gem_create@create-massive:
>
> shard-kbl: NOTRUN -> DMESG-WARN ([i915#4991])
>
> igt@gem_ctx_isolation@preservation-s3@vcs0:
>
> shard-kbl: NOTRUN -> DMESG-WARN ([i915#180]) +3 similar issues
>
> shard-apl: NOTRUN -> DMESG-WARN ([i915#180])
>
> igt@gem_eio@in-flight-immediate:
>
> shard-tglb: PASS -> TIMEOUT ([i915#3063])
>
> igt@gem_exec_fair@basic-none@vcs0:
>
> shard-kbl: PASS -> FAIL ([i915#2842])
>
> igt@gem_exec_fair@basic-none@vcs1:
>
> shard-iclb: NOTRUN -> FAIL ([i915#2842])
>
> igt@gem_exec_fair@basic-pace-share@rcs0:
>
> shard-tglb: PASS -> FAIL ([i915#2842]) +1 similar issue
>
> igt@gem_exec_fair@basic-pace@vecs0:
>
> shard-glk: PASS -> FAIL ([i915#2842])
>
> igt@gem_exec_fair@basic-throttle@rcs0:
>
> shard-glk: NOTRUN -> FAIL ([i915#2842])
>
> igt@gem_exec_params@no-blt:
>
> shard-tglb: NOTRUN -> SKIP ([fdo#109283])
>
> igt@gem_lmem_swapping@heavy-verify-multi:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#4613]) +5 similar issues
>
> igt@gem_lmem_swapping@parallel-random:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#4613])
>
> igt@gem_pxp@create-valid-protected-context:
>
> shard-iclb: NOTRUN -> SKIP ([i915#4270])
>
> igt@gem_render_copy@linear-to-vebox-y-tiled:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271]) +34 similar issues
>
> igt@gem_render_copy@yf-tiled-to-vebox-x-tiled:
>
> shard-iclb: NOTRUN -> SKIP ([i915#768])
>
> igt@gem_userptr_blits@input-checking:
>
> shard-skl: NOTRUN -> DMESG-WARN ([i915#4991])
>
> igt@gem_userptr_blits@vma-merge:
>
> shard-skl: NOTRUN -> FAIL ([i915#3318])
>
> igt@gen7_exec_parse@oacontrol-tracking:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109289])
>
> igt@gen9_exec_parse@allowed-all:
>
> shard-iclb: NOTRUN -> SKIP ([i915#2856]) +1 similar issue
>
> igt@i915_pm_dc@dc6-dpms:
>
> shard-skl: NOTRUN -> FAIL ([i915#454])
>
> igt@i915_pm_rpm@modeset-non-lpsp:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#110892])
>
> igt@i915_selftest@live@gt_pm:
>
> shard-skl: NOTRUN -> DMESG-FAIL ([i915#1886])
>
> igt@i915_suspend@sysfs-reader:
>
> shard-skl: PASS -> INCOMPLETE ([i915#4817])
>
> igt@kms_atomic_transition@plane-all-modeset-transition:
>
> shard-iclb: NOTRUN -> SKIP ([i915#1769])
>
> igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
>
> shard-iclb: NOTRUN -> SKIP ([i915#5286]) +3 similar issues
>
> igt@kms_big_fb@linear-32bpp-rotate-90:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#110725] / [fdo#111614]) +1 similar issue
>
> igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
>
> shard-skl: NOTRUN -> FAIL ([i915#3743]) +3 similar issues
>
> igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#3777]) +4 similar issues
>
> igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
>
> shard-glk: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +1 similar issue
>
> igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [i915#3886]) +2 similar issues
>
> igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +12 similar issues
>
> igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +2 similar issues
>
> igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs:
>
> shard-glk: NOTRUN -> SKIP ([fdo#109271]) +25 similar issues
>
> igt@kms_cdclk@mode-transition:
>
> shard-iclb: NOTRUN -> SKIP ([i915#3742])
>
> igt@kms_chamelium@dp-hpd-with-enabled-mode:
>
> shard-glk: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +4 similar issues
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109284] / [fdo#111827]) +5 similar issues
>
> igt@kms_chamelium@hdmi-aspect-ratio:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +24 similar issues
>
> igt@kms_chamelium@vga-hpd:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +2 similar issues
>
> igt@kms_color_chamelium@pipe-b-ctm-max:
>
> shard-tglb: NOTRUN -> SKIP ([fdo#109284] / [fdo#111827])
>
> shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +1 similar issue
>
> igt@kms_content_protection@srm:
>
> shard-apl: NOTRUN -> TIMEOUT ([i915#1319])
>
> igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding:
>
> shard-kbl: NOTRUN -> SKIP ([fdo#109271]) +21 similar issues
>
> shard-tglb: NOTRUN -> SKIP ([fdo#109279] / [i915#3359])
>
> igt@kms_cursor_crc@pipe-c-cursor-512x170-random:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [fdo#109279]) +2 similar issues
>
> igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109274] / [fdo#109278]) +3 similar issues
>
> igt@kms_draw_crc@draw-method-rgb565-blt-4tiled:
>
> shard-iclb: NOTRUN -> SKIP ([i915#5287]) +2 similar issues
>
> igt@kms_flip@2x-absolute-wf_vblank-interruptible:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109274]) +2 similar issues
>
> igt@kms_flip@flip-vs-expired-vblank@a-edp1:
>
> shard-skl: PASS -> FAIL ([i915#79]) +1 similar issue
>
> igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
>
> shard-apl: PASS -> DMESG-WARN ([i915#180]) +1 similar issue
>
> igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
>
> shard-iclb: NOTRUN -> SKIP ([i915#2587])
>
> igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109280]) +12 similar issues
>
> igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#533]) +2 similar issues
>
> igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
>
> shard-skl: NOTRUN -> FAIL ([i915#265]) +1 similar issue
>
> igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
>
> shard-apl: NOTRUN -> FAIL ([fdo#108145] / [i915#265])
>
> igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
>
> shard-apl: NOTRUN -> FAIL ([i915#265])
>
> igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
>
> shard-glk: NOTRUN -> FAIL ([fdo#108145] / [i915#265])
>
> igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
>
> shard-skl: NOTRUN -> FAIL ([fdo#108145] / [i915#265]) +3 similar issues
>
> igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109278]) +8 similar issues
>
> igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
>
> shard-iclb: PASS -> SKIP ([i915#5235]) +2 similar issues
>
> igt@kms_psr2_su@page_flip-p010:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#658])
>
> igt@kms_psr2_su@page_flip-xrgb8888:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#658]) +2 similar issues
>
> igt@kms_psr@psr2_cursor_render:
>
> shard-iclb: PASS -> SKIP ([fdo#109441]) +1 similar issue
>
> igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
>
> shard-iclb: NOTRUN -> SKIP ([i915#5289])
>
> igt@kms_sysfs_edid_timing:
>
> shard-apl: NOTRUN -> FAIL ([IGT#2])
>
> igt@kms_vrr@flip-dpms:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109502])
>
> igt@kms_writeback@writeback-check-output:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#2437])
>
> igt@kms_writeback@writeback-pixel-formats:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#2437]) +1 similar issue
>
> igt@nouveau_crc@pipe-a-source-outp-complete:
>
> shard-iclb: NOTRUN -> SKIP ([i915#2530])
>
> igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [i915#2530])
>
> igt@perf@polling-small-buf:
>
> shard-skl: PASS -> FAIL ([i915#1722])
>
> igt@perf_pmu@module-unload:
>
> shard-apl: PASS -> INCOMPLETE ([i915#1373] / [i915#262])
>
> igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109291]) +1 similar issue
>
> igt@prime_nv_api@i915_self_import:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271]) +341 similar issues
>
> igt@sysfs_clients@busy:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#2994]) +4 similar issues
>
> Possible fixes
>
> igt@fbdev@nullptr:
>
> shard-skl: DMESG-WARN ([i915#1982]) -> PASS
>
> igt@gem_ctx_persistence@many-contexts:
>
> {shard-rkl}: FAIL ([i915#2410]) -> PASS
>
> shard-iclb: FAIL ([i915#2410]) -> PASS
>
> igt@gem_exec_fair@basic-none@rcs0:
>
> shard-kbl: FAIL ([i915#2842]) -> PASS +1 similar issue
>
> igt@gem_exec_fair@basic-none@vcs0:
>
> shard-apl: FAIL ([i915#2842]) -> PASS
>
> igt@gem_exec_nop@basic-series:
>
> shard-glk: DMESG-WARN ([i915#118]) -> PASS
>
> igt@gen9_exec_parse@allowed-all:
>
> shard-glk: DMESG-WARN ([i915#1436] / [i915#716]) -> PASS
>
> igt@i915_pm_rpm@dpms-mode-unset-lpsp:
>
> shard-iclb: INCOMPLETE -> PASS
>
> igt@i915_pm_rpm@modeset-lpsp-stress:
>
> shard-tglb: SKIP ([i915#579]) -> PASS
>
> igt@i915_selftest@live@gem_contexts:
>
> shard-tglb: DMESG-WARN ([i915#2867]) -> PASS +16 similar issues
>
> igt@i915_suspend@forcewake:
>
> shard-kbl: DMESG-WARN ([i915#180]) -> PASS +1 similar issue
>
> igt@kms_big_fb@linear-16bpp-rotate-0:
>
> {shard-tglu}: DMESG-WARN ([i915#402]) -> PASS
>
> igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
>
> shard-skl: FAIL ([i915#79]) -> PASS
>
> igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
>
> {shard-rkl}: SKIP ([i915#4098]) -> PASS
>
> igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a:
>
> shard-apl: DMESG-WARN ([i915#180]) -> PASS +2 similar issues
>
> igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
>
> shard-skl: FAIL ([fdo#108145] / [i915#265]) -> PASS
>
> igt@kms_psr@psr2_sprite_plane_move:
>
> shard-iclb: SKIP ([fdo#109441]) -> PASS +1 similar issue
>
> igt@kms_rotation_crc@cursor-rotation-180:
>
> {shard-rkl}: SKIP ([i915#1845] / [i915#4098]) -> PASS
>
> igt@perf@polling-parameterized:
>
> shard-skl: FAIL ([i915#1542]) -> PASS
>
> Warnings
>
> igt@gem_exec_balancer@parallel-bb-first:
>
> shard-iclb: DMESG-WARN ([i915#5076]) -> SKIP ([i915#4525])
>
> igt@gem_exec_balancer@parallel-ordering:
>
> shard-iclb: DMESG-FAIL ([i915#5076]) -> SKIP ([i915#4525])
>
> igt@gem_exec_balancer@parallel-out-fence:
>
> shard-iclb: SKIP ([i915#4525]) -> DMESG-WARN ([i915#5076]) +1 similar issue
>
> igt@gem_exec_fair@basic-pace-solo@rcs0:
>
> shard-kbl: FAIL ([i915#2842]) -> FAIL ([i915#2851])
>
> igt@i915_pm_dc@dc9-dpms:
>
> shard-skl: SKIP ([fdo#109271]) -> SKIP ([fdo#109271] / [i915#1888]) +1 similar issue
>
> igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
>
> shard-skl: SKIP ([fdo#109271] / [i915#1888] / [i915#3886]) -> SKIP ([fdo#109271] / [i915#3886])
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Introduce multitile support
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
` (11 preceding siblings ...)
(?)
@ 2022-03-21 16:28 ` Patchwork
-1 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2022-03-21 16:28 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30251 bytes --]
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11384_full -> Patchwork_22617_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 13)
------------------------------
Additional (1): shard-dg1
Known issues
------------
Here are the changes found in Patchwork_22617_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#4991])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl4/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][2] ([i915#180]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
- shard-apl: NOTRUN -> [DMESG-WARN][3] ([i915#180])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_eio@in-flight-immediate:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb3/igt@gem_eio@in-flight-immediate.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb8/igt@gem_eio@in-flight-immediate.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-glk6/igt@gem_exec_fair@basic-pace@vecs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][14] ([fdo#109283])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb6/igt@gem_exec_params@no-blt.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +5 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl10/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@parallel-random:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_pxp@create-valid-protected-context:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#4270])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271]) +34 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_render_copy@yf-tiled-to-vebox-x-tiled:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#768])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_render_copy@yf-tiled-to-vebox-x-tiled.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][20] ([i915#4991])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl3/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][21] ([i915#3318])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@gem_userptr_blits@vma-merge.html
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [PASS][22] -> [INCOMPLETE][23] ([i915#1373])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl7/igt@gem_workarounds@suspend-resume.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl6/igt@gem_workarounds@suspend-resume.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-iclb: NOTRUN -> [SKIP][24] ([fdo#109289])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@allowed-all:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#2856]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][26] ([i915#454])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][27] ([fdo#110892])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][28] ([i915#1886])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl10/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@sysfs-reader:
- shard-skl: [PASS][29] -> [INCOMPLETE][30] ([i915#4817])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl10/igt@i915_suspend@sysfs-reader.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl2/igt@i915_suspend@sysfs-reader.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-iclb: NOTRUN -> [SKIP][31] ([i915#1769])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][32] ([i915#5286]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#110725] / [fdo#111614]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][34] ([i915#3743]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777]) +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109278] / [i915#3886]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +12 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3886]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs:
- shard-glk: NOTRUN -> [SKIP][40] ([fdo#109271]) +25 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#3742])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@dp-hpd-with-enabled-mode:
- shard-glk: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +4 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_chamelium@dp-hpd-with-enabled-mode.html
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827]) +5 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_chamelium@dp-hpd-with-enabled-mode.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +24 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_chamelium@vga-hpd.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#109284] / [fdo#111827])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb6/igt@kms_color_chamelium@pipe-b-ctm-max.html
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl1/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][48] ([i915#1319])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271]) +21 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#109279] / [i915#3359])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-random:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109278] / [fdo#109279]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109274] / [fdo#109278]) +3 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_draw_crc@draw-method-rgb565-blt-4tiled:
- shard-iclb: NOTRUN -> [SKIP][53] ([i915#5287]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_draw_crc@draw-method-rgb565-blt-4tiled.html
* igt@kms_flip@2x-absolute-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109274]) +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][55] -> [FAIL][56] ([i915#79]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [PASS][57] -> [DMESG-WARN][58] ([i915#180]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
- shard-iclb: NOTRUN -> [SKIP][59] ([i915#2587])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109280]) +12 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#533]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][62] ([i915#265]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][63] ([fdo#108145] / [i915#265])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][64] ([i915#265])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265]) +3 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
- shard-iclb: NOTRUN -> [SKIP][67] ([fdo#109278]) +8 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
- shard-iclb: [PASS][68] -> [SKIP][69] ([i915#5235]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
* igt@kms_psr2_su@page_flip-p010:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#658])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl1/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][72] -> [SKIP][73] ([fdo#109441]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-iclb: NOTRUN -> [SKIP][74] ([i915#5289])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][75] ([IGT#2])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_sysfs_edid_timing.html
* igt@kms_vrr@flip-dpms:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109502])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_vrr@flip-dpms.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2437])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2437]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-a-source-outp-complete:
- shard-iclb: NOTRUN -> [SKIP][79] ([i915#2530])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@nouveau_crc@pipe-a-source-outp-complete.html
* igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109278] / [i915#2530])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][81] -> [FAIL][82] ([i915#1722])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl4/igt@perf@polling-small-buf.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl2/igt@perf@polling-small-buf.html
* igt@perf_pmu@module-unload:
- shard-apl: [PASS][83] -> [INCOMPLETE][84] ([i915#1373] / [i915#262])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl4/igt@perf_pmu@module-unload.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl1/igt@perf_pmu@module-unload.html
* igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109291]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@prime_nv_api@i915_nv_import_twice_check_flink_name.html
* igt@prime_nv_api@i915_self_import:
- shard-skl: NOTRUN -> [SKIP][86] ([fdo#109271]) +341 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl1/igt@prime_nv_api@i915_self_import.html
* igt@sysfs_clients@busy:
- shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2994]) +4 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@sysfs_clients@busy.html
#### Possible fixes ####
* igt@fbdev@nullptr:
- shard-skl: [DMESG-WARN][88] ([i915#1982]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl7/igt@fbdev@nullptr.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl4/igt@fbdev@nullptr.html
* igt@gem_ctx_persistence@many-contexts:
- {shard-rkl}: [FAIL][90] ([i915#2410]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-rkl-5/igt@gem_ctx_persistence@many-contexts.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-rkl-5/igt@gem_ctx_persistence@many-contexts.html
- shard-iclb: [FAIL][92] ([i915#2410]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb5/igt@gem_ctx_persistence@many-contexts.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb8/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [FAIL][94] ([i915#2842]) -> [PASS][95] +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl3/igt@gem_exec_fair@basic-none@rcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl4/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_nop@basic-series:
- shard-glk: [DMESG-WARN][98] ([i915#118]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-glk2/igt@gem_exec_nop@basic-series.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk2/igt@gem_exec_nop@basic-series.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][100] ([i915#1436] / [i915#716]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-glk6/igt@gen9_exec_parse@allowed-all.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-iclb: [INCOMPLETE][102] -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb4/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-tglb: [SKIP][104] ([i915#579]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb3/igt@i915_pm_rpm@modeset-lpsp-stress.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb8/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_selftest@live@gem_contexts:
- shard-tglb: [DMESG-WARN][106] ([i915#2867]) -> [PASS][107] +16 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb3/igt@i915_selftest@live@gem_contexts.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb8/igt@i915_selftest@live@gem_contexts.html
* igt@i915_suspend@forcewake:
- shard-kbl: [DMESG-WARN][108] ([i915#180]) -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl6/igt@i915_suspend@forcewake.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl6/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@linear-16bpp-rotate-0:
- {shard-tglu}: [DMESG-WARN][110] ([i915#402]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglu-2/igt@kms_big_fb@linear-16bpp-rotate-0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglu-4/igt@kms_big_fb@linear-16bpp-rotate-0.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][112] ([i915#79]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- {shard-rkl}: [SKIP][114] ([i915#4098]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a:
- shard-apl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117] +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl7/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][118] ([fdo#108145] / [i915#265]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][120] ([fdo#109441]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_rotation_crc@cursor-rotation-180:
- {shard-rkl}: [SKIP][122] ([i915#1845] / [i915#4098]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-rkl-4/igt@kms_rotation_crc@cursor-rotation-180.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-rkl-6/igt@kms_rotation_crc@cursor-rotation-180.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][124] ([i915#1542]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl6/igt@perf@polling-parameterized.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [DMESG-WARN][126] ([i915#5076]) -> [SKIP][127] ([i915#4525])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@gem_exec_balancer@parallel-bb-first.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [DMESG-FAIL][128] ([i915#5076]) -> [SKIP][129] ([i915#4525])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][130] ([i915#4525]) -> [DMESG-WARN][131] ([i915#5076]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][132] ([i915#2842]) -> [FAIL][133] ([i915#2851])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@i915_pm_dc@dc9-dpms:
- shard-skl: [SKIP][134] ([fdo#109271]) -> [SKIP][135] ([fdo#109271] / [i915#1888]) +1 similar issue
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl6/igt@i915_pm_dc@dc9-dpms.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-skl: [SKIP][136] ([fdo#109271] / [i915#1888] / [i915#3886]) -> [SKIP][137] ([fdo#109271] / [i915#3886])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl10/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl2/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][138] ([fdo#111068] / [i915#658]) -> [SKIP][139] ([i915#2920]) +1 similar issue
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/sh
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/index.html
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* [Intel-gfx] ✓ Fi.CI.IGT: success for Introduce multitile support
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
` (12 preceding siblings ...)
(?)
@ 2022-03-21 16:43 ` Patchwork
-1 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2022-03-21 16:43 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30251 bytes --]
== Series Details ==
Series: Introduce multitile support
URL : https://patchwork.freedesktop.org/series/101551/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11384_full -> Patchwork_22617_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 13)
------------------------------
Additional (1): shard-dg1
Known issues
------------
Here are the changes found in Patchwork_22617_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#4991])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl4/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: NOTRUN -> [DMESG-WARN][2] ([i915#180]) +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
- shard-apl: NOTRUN -> [DMESG-WARN][3] ([i915#180])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_eio@in-flight-immediate:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb3/igt@gem_eio@in-flight-immediate.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb8/igt@gem_eio@in-flight-immediate.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl3/igt@gem_exec_fair@basic-none@vcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][8] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-glk6/igt@gem_exec_fair@basic-pace@vecs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][14] ([fdo#109283])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb6/igt@gem_exec_params@no-blt.html
* igt@gem_lmem_swapping@heavy-verify-multi:
- shard-skl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) +5 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl10/igt@gem_lmem_swapping@heavy-verify-multi.html
* igt@gem_lmem_swapping@parallel-random:
- shard-apl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_pxp@create-valid-protected-context:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#4270])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_pxp@create-valid-protected-context.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271]) +34 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_render_copy@yf-tiled-to-vebox-x-tiled:
- shard-iclb: NOTRUN -> [SKIP][19] ([i915#768])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_render_copy@yf-tiled-to-vebox-x-tiled.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][20] ([i915#4991])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl3/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][21] ([i915#3318])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@gem_userptr_blits@vma-merge.html
* igt@gem_workarounds@suspend-resume:
- shard-kbl: [PASS][22] -> [INCOMPLETE][23] ([i915#1373])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl7/igt@gem_workarounds@suspend-resume.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl6/igt@gem_workarounds@suspend-resume.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-iclb: NOTRUN -> [SKIP][24] ([fdo#109289])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@allowed-all:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#2856]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][26] ([i915#454])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-iclb: NOTRUN -> [SKIP][27] ([fdo#110892])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][28] ([i915#1886])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl10/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@sysfs-reader:
- shard-skl: [PASS][29] -> [INCOMPLETE][30] ([i915#4817])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl10/igt@i915_suspend@sysfs-reader.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl2/igt@i915_suspend@sysfs-reader.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-iclb: NOTRUN -> [SKIP][31] ([i915#1769])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][32] ([i915#5286]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#110725] / [fdo#111614]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][34] ([i915#3743]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-skl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777]) +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3886]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#109278] / [i915#3886]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +12 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3886]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs:
- shard-glk: NOTRUN -> [SKIP][40] ([fdo#109271]) +25 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#3742])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@dp-hpd-with-enabled-mode:
- shard-glk: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +4 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_chamelium@dp-hpd-with-enabled-mode.html
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109284] / [fdo#111827]) +5 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_chamelium@dp-hpd-with-enabled-mode.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +24 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@vga-hpd:
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +2 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_chamelium@vga-hpd.html
* igt@kms_color_chamelium@pipe-b-ctm-max:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#109284] / [fdo#111827])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb6/igt@kms_color_chamelium@pipe-b-ctm-max.html
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl1/igt@kms_color_chamelium@pipe-b-ctm-max.html
* igt@kms_content_protection@srm:
- shard-apl: NOTRUN -> [TIMEOUT][48] ([i915#1319])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding:
- shard-kbl: NOTRUN -> [SKIP][49] ([fdo#109271]) +21 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#109279] / [i915#3359])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-random:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109278] / [fdo#109279]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_cursor_crc@pipe-c-cursor-512x170-random.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109274] / [fdo#109278]) +3 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
* igt@kms_draw_crc@draw-method-rgb565-blt-4tiled:
- shard-iclb: NOTRUN -> [SKIP][53] ([i915#5287]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_draw_crc@draw-method-rgb565-blt-4tiled.html
* igt@kms_flip@2x-absolute-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][54] ([fdo#109274]) +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][55] -> [FAIL][56] ([i915#79]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-apl: [PASS][57] -> [DMESG-WARN][58] ([i915#180]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
- shard-iclb: NOTRUN -> [SKIP][59] ([i915#2587])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move:
- shard-iclb: NOTRUN -> [SKIP][60] ([fdo#109280]) +12 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#533]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][62] ([i915#265]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][63] ([fdo#108145] / [i915#265])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][64] ([i915#265])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][66] ([fdo#108145] / [i915#265]) +3 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
- shard-iclb: NOTRUN -> [SKIP][67] ([fdo#109278]) +8 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
- shard-iclb: [PASS][68] -> [SKIP][69] ([i915#5235]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
* igt@kms_psr2_su@page_flip-p010:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#658])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-skl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl1/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][72] -> [SKIP][73] ([fdo#109441]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-iclb: NOTRUN -> [SKIP][74] ([i915#5289])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][75] ([IGT#2])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_sysfs_edid_timing.html
* igt@kms_vrr@flip-dpms:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109502])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_vrr@flip-dpms.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2437])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-skl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2437]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-a-source-outp-complete:
- shard-iclb: NOTRUN -> [SKIP][79] ([i915#2530])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@nouveau_crc@pipe-a-source-outp-complete.html
* igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109278] / [i915#2530])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html
* igt@perf@polling-small-buf:
- shard-skl: [PASS][81] -> [FAIL][82] ([i915#1722])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl4/igt@perf@polling-small-buf.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl2/igt@perf@polling-small-buf.html
* igt@perf_pmu@module-unload:
- shard-apl: [PASS][83] -> [INCOMPLETE][84] ([i915#1373] / [i915#262])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl4/igt@perf_pmu@module-unload.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl1/igt@perf_pmu@module-unload.html
* igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109291]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@prime_nv_api@i915_nv_import_twice_check_flink_name.html
* igt@prime_nv_api@i915_self_import:
- shard-skl: NOTRUN -> [SKIP][86] ([fdo#109271]) +341 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl1/igt@prime_nv_api@i915_self_import.html
* igt@sysfs_clients@busy:
- shard-skl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#2994]) +4 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl7/igt@sysfs_clients@busy.html
#### Possible fixes ####
* igt@fbdev@nullptr:
- shard-skl: [DMESG-WARN][88] ([i915#1982]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl7/igt@fbdev@nullptr.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl4/igt@fbdev@nullptr.html
* igt@gem_ctx_persistence@many-contexts:
- {shard-rkl}: [FAIL][90] ([i915#2410]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-rkl-5/igt@gem_ctx_persistence@many-contexts.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-rkl-5/igt@gem_ctx_persistence@many-contexts.html
- shard-iclb: [FAIL][92] ([i915#2410]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb5/igt@gem_ctx_persistence@many-contexts.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb8/igt@gem_ctx_persistence@many-contexts.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl: [FAIL][94] ([i915#2842]) -> [PASS][95] +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl3/igt@gem_exec_fair@basic-none@rcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl4/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][96] ([i915#2842]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl8/igt@gem_exec_fair@basic-none@vcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_nop@basic-series:
- shard-glk: [DMESG-WARN][98] ([i915#118]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-glk2/igt@gem_exec_nop@basic-series.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk2/igt@gem_exec_nop@basic-series.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][100] ([i915#1436] / [i915#716]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-glk6/igt@gen9_exec_parse@allowed-all.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-glk1/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-iclb: [INCOMPLETE][102] -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb4/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-tglb: [SKIP][104] ([i915#579]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb3/igt@i915_pm_rpm@modeset-lpsp-stress.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb8/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_selftest@live@gem_contexts:
- shard-tglb: [DMESG-WARN][106] ([i915#2867]) -> [PASS][107] +16 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglb3/igt@i915_selftest@live@gem_contexts.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglb8/igt@i915_selftest@live@gem_contexts.html
* igt@i915_suspend@forcewake:
- shard-kbl: [DMESG-WARN][108] ([i915#180]) -> [PASS][109] +1 similar issue
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl6/igt@i915_suspend@forcewake.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl6/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@linear-16bpp-rotate-0:
- {shard-tglu}: [DMESG-WARN][110] ([i915#402]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-tglu-2/igt@kms_big_fb@linear-16bpp-rotate-0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-tglu-4/igt@kms_big_fb@linear-16bpp-rotate-0.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][112] ([i915#79]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- {shard-rkl}: [SKIP][114] ([i915#4098]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a:
- shard-apl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117] +2 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-apl7/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-apl6/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][118] ([fdo#108145] / [i915#265]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][120] ([fdo#109441]) -> [PASS][121] +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_rotation_crc@cursor-rotation-180:
- {shard-rkl}: [SKIP][122] ([i915#1845] / [i915#4098]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-rkl-4/igt@kms_rotation_crc@cursor-rotation-180.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-rkl-6/igt@kms_rotation_crc@cursor-rotation-180.html
* igt@perf@polling-parameterized:
- shard-skl: [FAIL][124] ([i915#1542]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl6/igt@perf@polling-parameterized.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [DMESG-WARN][126] ([i915#5076]) -> [SKIP][127] ([i915#4525])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@gem_exec_balancer@parallel-bb-first.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [DMESG-FAIL][128] ([i915#5076]) -> [SKIP][129] ([i915#4525])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb5/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][130] ([i915#4525]) -> [DMESG-WARN][131] ([i915#5076]) +1 similar issue
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb6/igt@gem_exec_balancer@parallel-out-fence.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [FAIL][132] ([i915#2842]) -> [FAIL][133] ([i915#2851])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-kbl1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@i915_pm_dc@dc9-dpms:
- shard-skl: [SKIP][134] ([fdo#109271]) -> [SKIP][135] ([fdo#109271] / [i915#1888]) +1 similar issue
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl6/igt@i915_pm_dc@dc9-dpms.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl9/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-skl: [SKIP][136] ([fdo#109271] / [i915#1888] / [i915#3886]) -> [SKIP][137] ([fdo#109271] / [i915#3886])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-skl10/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/shard-skl2/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][138] ([fdo#111068] / [i915#658]) -> [SKIP][139] ([i915#2920]) +1 similar issue
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11384/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/sh
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/index.html
[-- Attachment #2: Type: text/html, Size: 33588 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce multitile support
2022-03-21 10:05 ` Matthew Auld
@ 2022-03-21 16:44 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 40+ messages in thread
From: Vudum, Lakshminarayana @ 2022-03-21 16:44 UTC (permalink / raw)
To: Matthew Auld, Intel Graphics Development
Issue is related to
https://gitlab.freedesktop.org/drm/intel/-/issues/1373
Few tests - incomplete - Kernel panic - not syncing: EXT4-fs (device nvme0n1p2): panic forced after error|Kernel panic - not syncing: EXT4-fs panic from previous error
Lakshmi.
-----Original Message-----
From: Matthew Auld <matthew.william.auld@gmail.com>
Sent: Monday, March 21, 2022 3:05 AM
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Introduce multitile support
On Sat, 19 Mar 2022 at 02:06, Patchwork
<patchwork@emeril.freedesktop.org> wrote:
>
> Patch Details
> Series:Introduce multitile support
> URL:https://patchwork.freedesktop.org/series/101551/
> State:failure
> Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22617/index
> .html
>
> CI Bug Log - changes from CI_DRM_11384_full -> Patchwork_22617_full
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with Patchwork_22617_full absolutely
> need to be verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_22617_full, please notify your bug team to
> allow them to document this new failure mode, which will reduce false positives in CI.
>
> Participating hosts (12 -> 12)
>
> No changes in participating hosts
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in Patchwork_22617_full:
>
> IGT changes
>
> Possible regressions
>
> igt@gem_workarounds@suspend-resume:
>
> shard-kbl: PASS -> INCOMPLETE
Unrelated failure. Looks like filesystem related issue:
<4>[ 122.379815] EXT4-fs warning (device nvme0n1p2):
ext4_end_bio:346: I/O error 10 writing to inode 27001858 starting block 13317428) <6>[ 122.379827] nvme0n1: detected capacity change from 1000215216 to 0 <3>[ 122.379933] Buffer I/O error on device nvme0n1p2, logical block 13186100 <2>[ 122.380063] EXT4-fs error (device nvme0n1p2):
__ext4_find_entry:1614: inode #24510583: comm systemd-udevd: reading directory lblock 0 <3>[ 122.380358] Aborting journal on device nvme0n1p2-8.
<2>[ 122.380488] EXT4-fs error (device nvme0n1p2) in
ext4_reserve_inode_write:5706: Journal has aborted <2>[ 122.380612] EXT4-fs error (device nvme0n1p2):
ext4_journal_check_start:83: comm dmesg: Detected aborted journal <3>[ 122.380671] Buffer I/O error on dev nvme0n1p2, logical block 62423040, lost sync page write <3>[ 122.380721] JBD2: Error -5 detected when updating journal superblock for nvme0n1p2-8.
<2>[ 122.380935] EXT4-fs error (device nvme0n1p2):
ext4_journal_check_start:83: comm rs:main Q:Reg: Detected aborted journal <4>[ 122.381311] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory block <4>[ 122.381428] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory block <4>[ 122.381517] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory block <4>[ 122.381588] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory block <4>[ 122.381659] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory block <3>[ 122.381728] Buffer I/O error on dev nvme0n1p2, logical block 0, lost sync page write <4>[ 122.381734] EXT4-fs warning (device nvme0n1p2): dx_probe:788:
inode #3539533: lblock 0: comm systemd: error -5 reading directory block <3>[ 122.381741] EXT4-fs (nvme0n1p2): I/O error while writing superblock <0>[ 122.381744] Kernel panic - not syncing: EXT4-fs (device
nvme0n1p2): panic forced after error
<0>[ 122.381750] Kernel Offset: disabled <4>[ 122.381762] CPU: 2 PID: 378 Comm: rs:main Q:Reg Not tainted 5.17.0-rc8-CI-Patchwork_22617+ #1 <4>[ 122.381766] Hardware name: /NUC7i5BNB, BIOS
BNKBL357.86A.0083.2020.0714.1344 07/14/2020 <4>[ 122.381771] Call Trace:
<4>[ 122.381775] <TASK>
<4>[ 122.381777] dump_stack_lvl+0x56/0x7b <4>[ 122.381783] panic+0x12a/0x2c3 <4>[ 122.381794] ext4_handle_error.cold.167+0x13/0x13
<4>[ 122.381801] __ext4_error+0x104/0x1f0 <4>[ 122.381819] ext4_journal_check_start+0x84/0xa0
<4>[ 122.381823] __ext4_journal_start_sb+0x41/0x180
<4>[ 122.381829] ext4_dirty_inode+0x2f/0x70 <4>[ 122.381833] __mark_inode_dirty+0x181/0x580 <4>[ 122.381838] generic_update_time+0x98/0xc0 <4>[ 122.381842] file_update_time+0xc3/0x110 <4>[ 122.381844] ? generic_write_checks+0x5c/0xc0 <4>[ 122.381851] ext4_buffered_write_iter+0x4b/0x100
<4>[ 122.381858] ext4_file_write_iter+0x5a/0x830 <4>[ 122.381869] new_sync_write+0x120/0x1b0 <4>[ 122.381880] vfs_write+0x251/0x3b0 <4>[ 122.381886] ksys_write+0x5a/0xd0 <4>[ 122.381892] do_syscall_64+0x3a/0xb0 <4>[ 122.381896] entry_SYSCALL_64_after_hwframe+0x44/0xae
<4>[ 122.381899] RIP: 0033:0x7fd894e062cf
>
> Known issues
>
> Here are the changes found in Patchwork_22617_full that come from known issues:
>
> IGT changes
>
> Issues hit
>
> igt@gem_create@create-massive:
>
> shard-kbl: NOTRUN -> DMESG-WARN ([i915#4991])
>
> igt@gem_ctx_isolation@preservation-s3@vcs0:
>
> shard-kbl: NOTRUN -> DMESG-WARN ([i915#180]) +3 similar issues
>
> shard-apl: NOTRUN -> DMESG-WARN ([i915#180])
>
> igt@gem_eio@in-flight-immediate:
>
> shard-tglb: PASS -> TIMEOUT ([i915#3063])
>
> igt@gem_exec_fair@basic-none@vcs0:
>
> shard-kbl: PASS -> FAIL ([i915#2842])
>
> igt@gem_exec_fair@basic-none@vcs1:
>
> shard-iclb: NOTRUN -> FAIL ([i915#2842])
>
> igt@gem_exec_fair@basic-pace-share@rcs0:
>
> shard-tglb: PASS -> FAIL ([i915#2842]) +1 similar issue
>
> igt@gem_exec_fair@basic-pace@vecs0:
>
> shard-glk: PASS -> FAIL ([i915#2842])
>
> igt@gem_exec_fair@basic-throttle@rcs0:
>
> shard-glk: NOTRUN -> FAIL ([i915#2842])
>
> igt@gem_exec_params@no-blt:
>
> shard-tglb: NOTRUN -> SKIP ([fdo#109283])
>
> igt@gem_lmem_swapping@heavy-verify-multi:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#4613]) +5 similar
> issues
>
> igt@gem_lmem_swapping@parallel-random:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#4613])
>
> igt@gem_pxp@create-valid-protected-context:
>
> shard-iclb: NOTRUN -> SKIP ([i915#4270])
>
> igt@gem_render_copy@linear-to-vebox-y-tiled:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271]) +34 similar issues
>
> igt@gem_render_copy@yf-tiled-to-vebox-x-tiled:
>
> shard-iclb: NOTRUN -> SKIP ([i915#768])
>
> igt@gem_userptr_blits@input-checking:
>
> shard-skl: NOTRUN -> DMESG-WARN ([i915#4991])
>
> igt@gem_userptr_blits@vma-merge:
>
> shard-skl: NOTRUN -> FAIL ([i915#3318])
>
> igt@gen7_exec_parse@oacontrol-tracking:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109289])
>
> igt@gen9_exec_parse@allowed-all:
>
> shard-iclb: NOTRUN -> SKIP ([i915#2856]) +1 similar issue
>
> igt@i915_pm_dc@dc6-dpms:
>
> shard-skl: NOTRUN -> FAIL ([i915#454])
>
> igt@i915_pm_rpm@modeset-non-lpsp:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#110892])
>
> igt@i915_selftest@live@gt_pm:
>
> shard-skl: NOTRUN -> DMESG-FAIL ([i915#1886])
>
> igt@i915_suspend@sysfs-reader:
>
> shard-skl: PASS -> INCOMPLETE ([i915#4817])
>
> igt@kms_atomic_transition@plane-all-modeset-transition:
>
> shard-iclb: NOTRUN -> SKIP ([i915#1769])
>
> igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
>
> shard-iclb: NOTRUN -> SKIP ([i915#5286]) +3 similar issues
>
> igt@kms_big_fb@linear-32bpp-rotate-90:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#110725] / [fdo#111614]) +1 similar
> issue
>
> igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
>
> shard-skl: NOTRUN -> FAIL ([i915#3743]) +3 similar issues
>
> igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#3777]) +4 similar
> issues
>
> igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
>
> shard-glk: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +1 similar
> issue
>
> igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_rc_ccs_cc:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [i915#3886]) +2 similar
> issues
>
> igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +12 similar
> issues
>
> igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#3886]) +2 similar
> issues
>
> igt@kms_ccs@pipe-d-crc-sprite-planes-basic-yf_tiled_ccs:
>
> shard-glk: NOTRUN -> SKIP ([fdo#109271]) +25 similar issues
>
> igt@kms_cdclk@mode-transition:
>
> shard-iclb: NOTRUN -> SKIP ([i915#3742])
>
> igt@kms_chamelium@dp-hpd-with-enabled-mode:
>
> shard-glk: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +4 similar
> issues
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109284] / [fdo#111827]) +5 similar
> issues
>
> igt@kms_chamelium@hdmi-aspect-ratio:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +24 similar
> issues
>
> igt@kms_chamelium@vga-hpd:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +2 similar
> issues
>
> igt@kms_color_chamelium@pipe-b-ctm-max:
>
> shard-tglb: NOTRUN -> SKIP ([fdo#109284] / [fdo#111827])
>
> shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [fdo#111827]) +1 similar
> issue
>
> igt@kms_content_protection@srm:
>
> shard-apl: NOTRUN -> TIMEOUT ([i915#1319])
>
> igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding:
>
> shard-kbl: NOTRUN -> SKIP ([fdo#109271]) +21 similar issues
>
> shard-tglb: NOTRUN -> SKIP ([fdo#109279] / [i915#3359])
>
> igt@kms_cursor_crc@pipe-c-cursor-512x170-random:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [fdo#109279]) +2 similar
> issues
>
> igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109274] / [fdo#109278]) +3 similar
> issues
>
> igt@kms_draw_crc@draw-method-rgb565-blt-4tiled:
>
> shard-iclb: NOTRUN -> SKIP ([i915#5287]) +2 similar issues
>
> igt@kms_flip@2x-absolute-wf_vblank-interruptible:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109274]) +2 similar issues
>
> igt@kms_flip@flip-vs-expired-vblank@a-edp1:
>
> shard-skl: PASS -> FAIL ([i915#79]) +1 similar issue
>
> igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
>
> shard-apl: PASS -> DMESG-WARN ([i915#180]) +1 similar issue
>
> igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling:
>
> shard-iclb: NOTRUN -> SKIP ([i915#2587])
>
> igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-move:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109280]) +12 similar issues
>
> igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#533]) +2 similar
> issues
>
> igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
>
> shard-skl: NOTRUN -> FAIL ([i915#265]) +1 similar issue
>
> igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
>
> shard-apl: NOTRUN -> FAIL ([fdo#108145] / [i915#265])
>
> igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
>
> shard-apl: NOTRUN -> FAIL ([i915#265])
>
> igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
>
> shard-glk: NOTRUN -> FAIL ([fdo#108145] / [i915#265])
>
> igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
>
> shard-skl: NOTRUN -> FAIL ([fdo#108145] / [i915#265]) +3 similar
> issues
>
> igt@kms_plane_alpha_blend@pipe-d-constant-alpha-max:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109278]) +8 similar issues
>
> igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
>
> shard-iclb: PASS -> SKIP ([i915#5235]) +2 similar issues
>
> igt@kms_psr2_su@page_flip-p010:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#658])
>
> igt@kms_psr2_su@page_flip-xrgb8888:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#658]) +2 similar
> issues
>
> igt@kms_psr@psr2_cursor_render:
>
> shard-iclb: PASS -> SKIP ([fdo#109441]) +1 similar issue
>
> igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
>
> shard-iclb: NOTRUN -> SKIP ([i915#5289])
>
> igt@kms_sysfs_edid_timing:
>
> shard-apl: NOTRUN -> FAIL ([IGT#2])
>
> igt@kms_vrr@flip-dpms:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109502])
>
> igt@kms_writeback@writeback-check-output:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#2437])
>
> igt@kms_writeback@writeback-pixel-formats:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#2437]) +1 similar
> issue
>
> igt@nouveau_crc@pipe-a-source-outp-complete:
>
> shard-iclb: NOTRUN -> SKIP ([i915#2530])
>
> igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109278] / [i915#2530])
>
> igt@perf@polling-small-buf:
>
> shard-skl: PASS -> FAIL ([i915#1722])
>
> igt@perf_pmu@module-unload:
>
> shard-apl: PASS -> INCOMPLETE ([i915#1373] / [i915#262])
>
> igt@prime_nv_api@i915_nv_import_twice_check_flink_name:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109291]) +1 similar issue
>
> igt@prime_nv_api@i915_self_import:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271]) +341 similar issues
>
> igt@sysfs_clients@busy:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#2994]) +4 similar
> issues
>
> Possible fixes
>
> igt@fbdev@nullptr:
>
> shard-skl: DMESG-WARN ([i915#1982]) -> PASS
>
> igt@gem_ctx_persistence@many-contexts:
>
> {shard-rkl}: FAIL ([i915#2410]) -> PASS
>
> shard-iclb: FAIL ([i915#2410]) -> PASS
>
> igt@gem_exec_fair@basic-none@rcs0:
>
> shard-kbl: FAIL ([i915#2842]) -> PASS +1 similar issue
>
> igt@gem_exec_fair@basic-none@vcs0:
>
> shard-apl: FAIL ([i915#2842]) -> PASS
>
> igt@gem_exec_nop@basic-series:
>
> shard-glk: DMESG-WARN ([i915#118]) -> PASS
>
> igt@gen9_exec_parse@allowed-all:
>
> shard-glk: DMESG-WARN ([i915#1436] / [i915#716]) -> PASS
>
> igt@i915_pm_rpm@dpms-mode-unset-lpsp:
>
> shard-iclb: INCOMPLETE -> PASS
>
> igt@i915_pm_rpm@modeset-lpsp-stress:
>
> shard-tglb: SKIP ([i915#579]) -> PASS
>
> igt@i915_selftest@live@gem_contexts:
>
> shard-tglb: DMESG-WARN ([i915#2867]) -> PASS +16 similar issues
>
> igt@i915_suspend@forcewake:
>
> shard-kbl: DMESG-WARN ([i915#180]) -> PASS +1 similar issue
>
> igt@kms_big_fb@linear-16bpp-rotate-0:
>
> {shard-tglu}: DMESG-WARN ([i915#402]) -> PASS
>
> igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
>
> shard-skl: FAIL ([i915#79]) -> PASS
>
> igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
>
> {shard-rkl}: SKIP ([i915#4098]) -> PASS
>
> igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-dp-1-pipe-a:
>
> shard-apl: DMESG-WARN ([i915#180]) -> PASS +2 similar issues
>
> igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
>
> shard-skl: FAIL ([fdo#108145] / [i915#265]) -> PASS
>
> igt@kms_psr@psr2_sprite_plane_move:
>
> shard-iclb: SKIP ([fdo#109441]) -> PASS +1 similar issue
>
> igt@kms_rotation_crc@cursor-rotation-180:
>
> {shard-rkl}: SKIP ([i915#1845] / [i915#4098]) -> PASS
>
> igt@perf@polling-parameterized:
>
> shard-skl: FAIL ([i915#1542]) -> PASS
>
> Warnings
>
> igt@gem_exec_balancer@parallel-bb-first:
>
> shard-iclb: DMESG-WARN ([i915#5076]) -> SKIP ([i915#4525])
>
> igt@gem_exec_balancer@parallel-ordering:
>
> shard-iclb: DMESG-FAIL ([i915#5076]) -> SKIP ([i915#4525])
>
> igt@gem_exec_balancer@parallel-out-fence:
>
> shard-iclb: SKIP ([i915#4525]) -> DMESG-WARN ([i915#5076]) +1 similar
> issue
>
> igt@gem_exec_fair@basic-pace-solo@rcs0:
>
> shard-kbl: FAIL ([i915#2842]) -> FAIL ([i915#2851])
>
> igt@i915_pm_dc@dc9-dpms:
>
> shard-skl: SKIP ([fdo#109271]) -> SKIP ([fdo#109271] / [i915#1888]) +1
> similar issue
>
> igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
>
> shard-skl: SKIP ([fdo#109271] / [i915#1888] / [i915#3886]) -> SKIP
> ([fdo#109271] / [i915#3886])
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
(?)
@ 2022-05-05 13:14 ` Tvrtko Ursulin
2022-05-05 13:27 ` Andi Shyti
-1 siblings, 1 reply; 40+ messages in thread
From: Tvrtko Ursulin @ 2022-05-05 13:14 UTC (permalink / raw)
To: Andi Shyti, Intel GFX, DRI Devel
Cc: Lucas De Marchi, Matthew Auld, Chris Wilson
Hi Andi,
On 18/03/2022 23:39, Andi Shyti wrote:
> Now tiles have their own sysfs interfaces under the gt/
> directory. Because RPS is a property that can be configured on a
> tile basis, then each tile should have its own interface
>
> The new sysfs structure will have a similar layout for the 4 tile
> case:
>
> /sys/.../card0
> ├── gt
> │ ├── gt0
> │ │ ├── id
> │ │ ├── rc6_enable
> │ │ ├── rc6_residency_ms
> │ │ ├── rps_act_freq_mhz
> │ │ ├── rps_boost_freq_mhz
> │ │ ├── rps_cur_freq_mhz
> │ │ ├── rps_max_freq_mhz
> │ │ ├── rps_min_freq_mhz
> │ │ ├── rps_RP0_freq_mhz
> │ │ ├── rps_RP1_freq_mhz
> │ │ └── rps_RPn_freq_mhz
> . .
> . .
> . .
> │ └── gtN
> │ ├── id
> │ ├── rc6_enable
> │ ├── rc6_residency_ms
> │ ├── rps_act_freq_mhz
> │ ├── rps_boost_freq_mhz
> │ ├── rps_cur_freq_mhz
> │ ├── rps_max_freq_mhz
> │ ├── rps_min_freq_mhz
> │ ├── rps_RP0_freq_mhz
> │ ├── rps_RP1_freq_mhz
> │ └── rps_RPn_freq_mhz
> ├── gt_act_freq_mhz -+
> ├── gt_boost_freq_mhz |
> ├── gt_cur_freq_mhz | Original interface
> ├── gt_max_freq_mhz +─-> kept as existing ABI;
> ├── gt_min_freq_mhz | it points to gt0/
> ├── gt_RP0_freq_mhz |
> ├── gt_RP1_freq_mhz |
> └── gt_RPn_freq_mhz -+
>
> The existing interfaces have been kept in their original location
> to preserve the existing ABI. They act on all the GTs: when
> writing they loop through all the GTs and write the information
> on each interface. When reading they provide the average value
> from all the GTs.
>
> This patch is not really adding exposing new interfaces (new
> ABI) other than adapting the existing one to more tiles. In any
> case this new set of interfaces will be a basic tool for system
> managers and administrators when using i915.
>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 283 ++++++++++++++++++++
> drivers/gpu/drm/i915/i915_sysfs.c | 177 ------------
> 2 files changed, 283 insertions(+), 177 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> index 144b004e4de82..b0a1ea95d028e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> @@ -14,6 +14,7 @@
> #include "intel_gt_sysfs.h"
> #include "intel_gt_sysfs_pm.h"
> #include "intel_rc6.h"
> +#include "intel_rps.h"
>
> #ifdef CONFIG_PM
> enum intel_gt_sysfs_op {
> @@ -21,6 +22,30 @@ enum intel_gt_sysfs_op {
> INTEL_GT_SYSFS_MAX,
> };
>
> +static int
> +sysfs_gt_attribute_w_func(struct device *dev, struct device_attribute *attr,
> + int (func)(struct intel_gt *gt, u32 val), u32 val)
> +{
> + struct intel_gt *gt;
> + int ret;
> +
> + if (!is_object_gt(&dev->kobj)) {
> + int i;
> + struct drm_i915_private *i915 = kdev_minor_to_i915(dev);
> +
> + for_each_gt(gt, i915, i) {
> + ret = func(gt, val);
> + if (ret)
> + break;
> + }
> + } else {
> + gt = intel_gt_sysfs_get_drvdata(dev, attr->attr.name);
> + ret = func(gt, val);
> + }
> +
> + return ret;
> +}
> +
> static u32
> sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
> u32 (func)(struct intel_gt *gt),
> @@ -62,6 +87,7 @@ sysfs_gt_attribute_r_func(struct device *dev, struct device_attribute *attr,
> #define sysfs_gt_attribute_r_min_func(d, a, f) \
> sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MIN)
>
> +/* Frequency interfaces will show the maximum frequency value */
> #define sysfs_gt_attribute_r_max_func(d, a, f) \
> sysfs_gt_attribute_r_func(d, a, f, INTEL_GT_SYSFS_MAX)
>
> @@ -238,7 +264,264 @@ static void intel_sysfs_rc6_init(struct intel_gt *gt, struct kobject *kobj)
> }
> #endif /* CONFIG_PM */
>
> +static u32 __act_freq_mhz_show(struct intel_gt *gt)
> +{
> + return intel_rps_read_actual_frequency(>->rps);
> +}
> +
> +static ssize_t act_freq_mhz_show(struct device *dev,
> + struct device_attribute *attr, char *buff)
> +{
> + u32 actual_freq = sysfs_gt_attribute_r_max_func(dev, attr,
> + __act_freq_mhz_show);
Because sysfs_gt_attribute_r_max_func is only defined if CONFIG_PM is
set, the !CONFIG_PM builds are broken. I guess just move it to be always
available.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces
2022-05-05 13:14 ` Tvrtko Ursulin
@ 2022-05-05 13:27 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-05-05 13:27 UTC (permalink / raw)
To: Tvrtko Ursulin
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson,
Matthew Auld, Andi Shyti
Hi Tvrtko,
[...]
> > +static ssize_t act_freq_mhz_show(struct device *dev,
> > + struct device_attribute *attr, char *buff)
> > +{
> > + u32 actual_freq = sysfs_gt_attribute_r_max_func(dev, attr,
> > + __act_freq_mhz_show);
>
> Because sysfs_gt_attribute_r_max_func is only defined if CONFIG_PM is set,
> the !CONFIG_PM builds are broken. I guess just move it to be always
> available.
oh, right! Thanks for letting me know, will fix it.
Thanks,
Andi
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces
@ 2022-05-05 13:27 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-05-05 13:27 UTC (permalink / raw)
To: Tvrtko Ursulin
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson, Matthew Auld
Hi Tvrtko,
[...]
> > +static ssize_t act_freq_mhz_show(struct device *dev,
> > + struct device_attribute *attr, char *buff)
> > +{
> > + u32 actual_freq = sysfs_gt_attribute_r_max_func(dev, attr,
> > + __act_freq_mhz_show);
>
> Because sysfs_gt_attribute_r_max_func is only defined if CONFIG_PM is set,
> the !CONFIG_PM builds are broken. I guess just move it to be always
> available.
oh, right! Thanks for letting me know, will fix it.
Thanks,
Andi
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
(?)
(?)
@ 2022-05-06 11:53 ` Jani Nikula
2022-05-06 15:21 ` Andi Shyti
-1 siblings, 1 reply; 40+ messages in thread
From: Jani Nikula @ 2022-05-06 11:53 UTC (permalink / raw)
To: Andi Shyti, Intel GFX, DRI Devel
Cc: Lucas De Marchi, Matthew Auld, Chris Wilson
On Sat, 19 Mar 2022, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> +#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \
> + struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \
> + struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)
Consider this macro...
> +
> +#define INTEL_GT_RPS_SYSFS_ATTR_RO(_name) \
> + INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL)
> +#define INTEL_GT_RPS_SYSFS_ATTR_RW(_name) \
> + INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store)
> +
> +static INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
> +static INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
> +static INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
> +static INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
> +static INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
> +static INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
> +static INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
> +static INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
...and the static keyword here.
All of the dev_attr_rps_* attributes become non-static, as the static
only applies to the dev_attr_gt_* attributes:
CHECK drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:468:8: warning: symbol 'dev_attr_rps_act_freq_mhz' was not declared. Should it be static?
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:469:8: warning: symbol 'dev_attr_rps_cur_freq_mhz' was not declared. Should it be static?
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:470:8: warning: symbol 'dev_attr_rps_boost_freq_mhz' was not declared. Should it be static?
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:471:8: warning: symbol 'dev_attr_rps_RP0_freq_mhz' was not declared. Should it be static?
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:472:8: warning: symbol 'dev_attr_rps_RP1_freq_mhz' was not declared. Should it be static?
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:473:8: warning: symbol 'dev_attr_rps_RPn_freq_mhz' was not declared. Should it be static?
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:474:8: warning: symbol 'dev_attr_rps_max_freq_mhz' was not declared. Should it be static?
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:475:8: warning: symbol 'dev_attr_rps_min_freq_mhz' was not declared. Should it be static?
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces
2022-05-06 11:53 ` Jani Nikula
@ 2022-05-06 15:21 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-05-06 15:21 UTC (permalink / raw)
To: Jani Nikula
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson,
Matthew Auld, Andi Shyti
Hi Jani,
On Fri, May 06, 2022 at 02:53:50PM +0300, Jani Nikula wrote:
> On Sat, 19 Mar 2022, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> > +#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \
> > + struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \
> > + struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)
>
> Consider this macro...
>
> > +
> > +#define INTEL_GT_RPS_SYSFS_ATTR_RO(_name) \
> > + INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL)
> > +#define INTEL_GT_RPS_SYSFS_ATTR_RW(_name) \
> > + INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store)
> > +
> > +static INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
>
> ...and the static keyword here.
>
> All of the dev_attr_rps_* attributes become non-static, as the static
> only applies to the dev_attr_gt_* attributes:
right! Missed that! Thanks, will send the fix.
Thanks,
Andi
> CHECK drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:468:8: warning: symbol 'dev_attr_rps_act_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:469:8: warning: symbol 'dev_attr_rps_cur_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:470:8: warning: symbol 'dev_attr_rps_boost_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:471:8: warning: symbol 'dev_attr_rps_RP0_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:472:8: warning: symbol 'dev_attr_rps_RP1_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:473:8: warning: symbol 'dev_attr_rps_RPn_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:474:8: warning: symbol 'dev_attr_rps_max_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:475:8: warning: symbol 'dev_attr_rps_min_freq_mhz' was not declared. Should it be static?
>
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces
@ 2022-05-06 15:21 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-05-06 15:21 UTC (permalink / raw)
To: Jani Nikula
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson, Matthew Auld
Hi Jani,
On Fri, May 06, 2022 at 02:53:50PM +0300, Jani Nikula wrote:
> On Sat, 19 Mar 2022, Andi Shyti <andi.shyti@linux.intel.com> wrote:
> > +#define INTEL_GT_RPS_SYSFS_ATTR(_name, _mode, _show, _store) \
> > + struct device_attribute dev_attr_gt_##_name = __ATTR(gt_##_name, _mode, _show, _store); \
> > + struct device_attribute dev_attr_rps_##_name = __ATTR(rps_##_name, _mode, _show, _store)
>
> Consider this macro...
>
> > +
> > +#define INTEL_GT_RPS_SYSFS_ATTR_RO(_name) \
> > + INTEL_GT_RPS_SYSFS_ATTR(_name, 0444, _name##_show, NULL)
> > +#define INTEL_GT_RPS_SYSFS_ATTR_RW(_name) \
> > + INTEL_GT_RPS_SYSFS_ATTR(_name, 0644, _name##_show, _name##_store)
> > +
> > +static INTEL_GT_RPS_SYSFS_ATTR_RO(act_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RO(cur_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RW(boost_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RP0_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RP1_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RO(RPn_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RW(max_freq_mhz);
> > +static INTEL_GT_RPS_SYSFS_ATTR_RW(min_freq_mhz);
>
> ...and the static keyword here.
>
> All of the dev_attr_rps_* attributes become non-static, as the static
> only applies to the dev_attr_gt_* attributes:
right! Missed that! Thanks, will send the fix.
Thanks,
Andi
> CHECK drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:468:8: warning: symbol 'dev_attr_rps_act_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:469:8: warning: symbol 'dev_attr_rps_cur_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:470:8: warning: symbol 'dev_attr_rps_boost_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:471:8: warning: symbol 'dev_attr_rps_RP0_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:472:8: warning: symbol 'dev_attr_rps_RP1_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:473:8: warning: symbol 'dev_attr_rps_RPn_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:474:8: warning: symbol 'dev_attr_rps_max_freq_mhz' was not declared. Should it be static?
> drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c:475:8: warning: symbol 'dev_attr_rps_min_freq_mhz' was not declared. Should it be static?
>
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
@ 2022-05-11 19:11 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 40+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-05-11 19:11 UTC (permalink / raw)
To: Andi Shyti, Intel GFX, DRI Devel
Cc: Sujaritha Sundaresan, Tvrtko Ursulin, Lucas De Marchi,
Chris Wilson, Matthew Auld, Andi Shyti, Michal Wajdeczko
On 3/18/2022 4:39 PM, Andi Shyti wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four GTs are supported in i915->gt[], with slot zero
> shadowing the existing i915->gt0 to enable source compatibility
> with legacy driver paths. A for_each_gt macro is added to iterate
> over the GTs and will be used by upcoming patches that convert
> various parts of the driver to be multi-gt aware.
>
> Only the primary/root tile is initialized for now; the other
> tiles will be detected and plugged in by future patches once the
> necessary infrastructure is in place to handle them.
>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@gmail.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 133 ++++++++++++++++--
> drivers/gpu/drm/i915/gt/intel_gt.h | 17 ++-
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
> drivers/gpu/drm/i915/i915_driver.c | 28 ++--
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/intel_memory_region.h | 3 +
> drivers/gpu/drm/i915/intel_uncore.c | 11 +-
> drivers/gpu/drm/i915/intel_uncore.h | 3 +-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 13 +-
> 10 files changed, 184 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index ca875ba3e2a9d..cfac4a913642e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -29,7 +29,7 @@
> #include "intel_uncore.h"
> #include "shmem_utils.h"
>
> -void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> +static void __intel_gt_init_early(struct intel_gt *gt)
> {
> spin_lock_init(>->irq_lock);
>
> @@ -51,17 +51,23 @@ void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> intel_rps_init_early(>->rps);
> }
>
> -void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> +/* Preliminary initialization of Tile 0 */
> +void intel_root_gt_init_early(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt = to_gt(i915);
> +
> gt->i915 = i915;
> gt->uncore = &i915->uncore;
> +
> + __intel_gt_init_early(gt);
> }
>
> -int intel_gt_probe_lmem(struct intel_gt *gt)
> +static int intel_gt_probe_lmem(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int instance = gt->info.id;
> + int id = INTEL_REGION_LMEM_0 + instance;
> struct intel_memory_region *mem;
> - int id;
> int err;
>
> mem = intel_gt_setup_lmem(gt);
> @@ -76,9 +82,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
> return err;
> }
>
> - id = INTEL_REGION_LMEM_0;
> -
> mem->id = id;
> + mem->instance = instance;
>
> intel_memory_region_set_name(mem, "local%u", mem->instance);
>
> @@ -807,16 +812,21 @@ void intel_gt_driver_release(struct intel_gt *gt)
> intel_gt_fini_hwconfig(gt);
> }
>
> -void intel_gt_driver_late_release(struct intel_gt *gt)
> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt;
> + unsigned int id;
> +
> /* We need to wait for inflight RCU frees to release their grip */
> rcu_barrier();
>
> - intel_uc_driver_late_release(>->uc);
> - intel_gt_fini_requests(gt);
> - intel_gt_fini_reset(gt);
> - intel_gt_fini_timelines(gt);
> - intel_engines_free(gt);
> + for_each_gt(gt, i915, id) {
> + intel_uc_driver_late_release(>->uc);
> + intel_gt_fini_requests(gt);
> + intel_gt_fini_reset(gt);
> + intel_gt_fini_timelines(gt);
> + intel_engines_free(gt);
> + }
> }
>
> /**
> @@ -1013,6 +1023,105 @@ void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
> }
> }
>
> +static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> +{
> + int ret;
> +
> + if (!gt_is_root(gt)) {
> + struct intel_uncore_mmio_debug *mmio_debug;
> + struct intel_uncore *uncore;
> +
> + uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
> + if (!uncore)
> + return -ENOMEM;
> +
> + mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
> + if (!mmio_debug) {
> + kfree(uncore);
> + return -ENOMEM;
> + }
> +
> + gt->uncore = uncore;
> + gt->uncore->debug = mmio_debug;
> +
> + __intel_gt_init_early(gt);
> + }
> +
> + intel_uncore_init_early(gt->uncore, gt);
> +
> + ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
> + if (ret)
> + return ret;
> +
> + gt->phys_addr = phys_addr;
> +
> + return 0;
> +}
> +
> +static void
> +intel_gt_tile_cleanup(struct intel_gt *gt)
> +{
> + intel_uncore_cleanup_mmio(gt->uncore);
> +
> + if (!gt_is_root(gt)) {
> + kfree(gt->uncore->debug);
> + kfree(gt->uncore);
> + kfree(gt);
> + }
> +}
> +
> +int intel_gt_probe_all(struct drm_i915_private *i915)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct intel_gt *gt = &i915->gt0;
> + phys_addr_t phys_addr;
> + unsigned int mmio_bar;
> + int ret;
> +
> + mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
> + phys_addr = pci_resource_start(pdev, mmio_bar);
> +
> + /*
> + * We always have at least one primary GT on any device
> + * and it has been already initialized early during probe
> + * in i915_driver_probe()
> + */
> + ret = intel_gt_tile_setup(gt, phys_addr);
> + if (ret)
> + return ret;
> +
> + i915->gt[0] = gt;
> +
> + /* TODO: add more tiles */
> + return 0;
> +}
> +
> +int intel_gt_tiles_init(struct drm_i915_private *i915)
> +{
> + struct intel_gt *gt;
> + unsigned int id;
> + int ret;
> +
> + for_each_gt(gt, i915, id) {
> + ret = intel_gt_probe_lmem(gt);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +void intel_gt_release_all(struct drm_i915_private *i915)
> +{
> + struct intel_gt *gt;
> + unsigned int id;
> +
> + for_each_gt(gt, i915, id) {
> + intel_gt_tile_cleanup(gt);
> + i915->gt[id] = NULL;
> + }
> +}
> +
> void intel_gt_info_print(const struct intel_gt_info *info,
> struct drm_printer *p)
> {
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index ce471aa5c83d7..e76168e10a21b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -39,10 +39,8 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
> return container_of(huc, struct intel_gt, uc.huc);
> }
>
> -void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
> -void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
> +void intel_root_gt_init_early(struct drm_i915_private *i915);
> int intel_gt_assign_ggtt(struct intel_gt *gt);
> -int intel_gt_probe_lmem(struct intel_gt *gt);
> int intel_gt_init_mmio(struct intel_gt *gt);
> int __must_check intel_gt_init_hw(struct intel_gt *gt);
> int intel_gt_init(struct intel_gt *gt);
> @@ -52,7 +50,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt);
> void intel_gt_driver_remove(struct intel_gt *gt);
> void intel_gt_driver_release(struct intel_gt *gt);
>
> -void intel_gt_driver_late_release(struct intel_gt *gt);
> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
>
> int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
>
> @@ -97,6 +95,17 @@ u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
>
> void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
> bool dump_table);
> +
> +int intel_gt_probe_all(struct drm_i915_private *i915);
> +int intel_gt_tiles_init(struct drm_i915_private *i915);
> +void intel_gt_release_all(struct drm_i915_private *i915);
> +
> +#define for_each_gt(gt__, i915__, id__) \
> + for ((id__) = 0; \
> + (id__) < I915_MAX_GT; \
> + (id__)++) \
> + for_each_if(((gt__) = (i915__)->gt[(id__)]))
> +
> void intel_gt_info_print(const struct intel_gt_info *info,
> struct drm_printer *p);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index e4ecc17889d34..eeead40485fbc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -129,7 +129,14 @@ static const struct intel_wakeref_ops wf_ops = {
>
> void intel_gt_pm_init_early(struct intel_gt *gt)
> {
> - intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
> + /*
> + * We access the runtime_pm structure via gt->i915 here rather than
> + * gt->uncore as we do elsewhere in the file because gt->uncore is not
> + * yet initialized for all tiles at this point in the driver startup.
> + * runtime_pm is per-device rather than per-tile, so this is still the
> + * correct structure.
> + */
> + intel_wakeref_init(>->wakeref, >->i915->runtime_pm, &wf_ops);
> seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index bbba885d45bd5..937b2e1a305ed 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -188,7 +188,14 @@ struct intel_gt {
> u8 instanceid;
> } default_steering;
>
> + /*
> + * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT.
> + */
> + phys_addr_t phys_addr;
> +
> struct intel_gt_info {
> + unsigned int id;
> +
> intel_engine_mask_t engine_mask;
>
> u32 l3bank_mask;
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 92a625a174e22..64e6f76861f95 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -321,9 +321,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> intel_device_info_subplatform_init(dev_priv);
> intel_step_init(dev_priv);
>
> - intel_gt_init_early(to_gt(dev_priv), dev_priv);
> intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
> - intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv));
>
> spin_lock_init(&dev_priv->irq_lock);
> spin_lock_init(&dev_priv->gpu_error.lock);
> @@ -354,7 +352,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> intel_wopcm_init_early(&dev_priv->wopcm);
>
> - __intel_gt_init_early(to_gt(dev_priv), dev_priv);
> + intel_root_gt_init_early(dev_priv);
>
> i915_gem_init_early(dev_priv);
>
> @@ -375,7 +373,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> err_gem:
> i915_gem_cleanup_early(dev_priv);
> - intel_gt_driver_late_release(to_gt(dev_priv));
> + intel_gt_driver_late_release_all(dev_priv);
> intel_region_ttm_device_fini(dev_priv);
> err_ttm:
> vlv_suspend_cleanup(dev_priv);
> @@ -394,7 +392,7 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv)
> intel_irq_fini(dev_priv);
> intel_power_domains_cleanup(dev_priv);
> i915_gem_cleanup_early(dev_priv);
> - intel_gt_driver_late_release(to_gt(dev_priv));
> + intel_gt_driver_late_release_all(dev_priv);
> intel_region_ttm_device_fini(dev_priv);
> vlv_suspend_cleanup(dev_priv);
> i915_workqueues_cleanup(dev_priv);
> @@ -425,13 +423,9 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
> if (ret < 0)
> return ret;
>
> - ret = intel_uncore_setup_mmio(&dev_priv->uncore);
> - if (ret < 0)
> - goto err_bridge;
> -
> ret = intel_uncore_init_mmio(&dev_priv->uncore);
> if (ret)
> - goto err_mmio;
> + return ret;
>
> /* Try to make sure MCHBAR is enabled before poking at it */
> intel_setup_mchbar(dev_priv);
> @@ -449,9 +443,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
> err_uncore:
> intel_teardown_mchbar(dev_priv);
> intel_uncore_fini_mmio(&dev_priv->uncore);
> -err_mmio:
> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
> -err_bridge:
> pci_dev_put(dev_priv->bridge_dev);
>
> return ret;
> @@ -465,7 +456,6 @@ static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
> {
> intel_teardown_mchbar(dev_priv);
> intel_uncore_fini_mmio(&dev_priv->uncore);
> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
> pci_dev_put(dev_priv->bridge_dev);
> }
>
> @@ -598,7 +588,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
> if (ret)
> goto err_ggtt;
>
> - ret = intel_gt_probe_lmem(to_gt(dev_priv));
> + ret = intel_gt_tiles_init(dev_priv);
> if (ret)
> goto err_mem_regions;
>
> @@ -849,10 +839,14 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>
> intel_vgpu_detect(i915);
>
> - ret = i915_driver_mmio_probe(i915);
> + ret = intel_gt_probe_all(i915);
> if (ret < 0)
> goto out_runtime_pm_put;
>
> + ret = i915_driver_mmio_probe(i915);
> + if (ret < 0)
> + goto out_tiles_cleanup;
> +
> ret = i915_driver_hw_probe(i915);
> if (ret < 0)
> goto out_cleanup_mmio;
> @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> i915_ggtt_driver_late_release(i915);
> out_cleanup_mmio:
> i915_driver_mmio_release(i915);
> +out_tiles_cleanup:
> + intel_gt_release_all(i915);
We don't seem to call intel_gt_release_all() from driver_release(), so
we might be leaking something there. I wanted to send a patch to add the
call at the same place in the flow as in this error path, but then I
noticed that i915_driver_late_release(), which we call a few lines
below, calls intel_gt_driver_late_release_all(), which seems to expect
that the GTs are still allocated, so we probably need to flip the order
those are called in, or move the cleanup code from late_release() to
late_release_all() (or vice versa).
Andi, can you have a look at this?
Thanks,
Daniele
> out_runtime_pm_put:
> enable_rpm_wakeref_asserts(&i915->runtime_pm);
> i915_driver_late_release(i915);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 97622d3ccfc2a..8e4083d413592 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -777,6 +777,12 @@ struct drm_i915_private {
> /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
> struct intel_gt gt0;
>
> + /*
> + * i915->gt[0] == &i915->gt0
> + */
> +#define I915_MAX_GT 4
> + struct intel_gt *gt[I915_MAX_GT];
> +
> struct {
> struct i915_gem_contexts {
> spinlock_t lock; /* locks list */
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
> index cc7078bcbfbfc..3d8378c1b4478 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.h
> +++ b/drivers/gpu/drm/i915/intel_memory_region.h
> @@ -30,6 +30,9 @@ enum intel_memory_type {
> enum intel_region_id {
> INTEL_REGION_SMEM = 0,
> INTEL_REGION_LMEM_0,
> + INTEL_REGION_LMEM_1,
> + INTEL_REGION_LMEM_2,
> + INTEL_REGION_LMEM_3,
> INTEL_REGION_STOLEN_SMEM,
> INTEL_REGION_STOLEN_LMEM,
> INTEL_REGION_UNKNOWN, /* Should be last */
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index ef8ffc01ad19c..8b9caaaacc21f 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2039,14 +2039,11 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
> return NOTIFY_OK;
> }
>
> -int intel_uncore_setup_mmio(struct intel_uncore *uncore)
> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
> {
> struct drm_i915_private *i915 = uncore->i915;
> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> - int mmio_bar;
> int mmio_size;
>
> - mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
> /*
> * Before gen4, the registers and the GTT are behind different BARs.
> * However, from gen4 onwards, the registers and the GTT are shared
> @@ -2063,7 +2060,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
> else
> mmio_size = 2 * 1024 * 1024;
>
> - uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
> + uncore->regs = ioremap(phys_addr, mmio_size);
> if (uncore->regs == NULL) {
> drm_err(&i915->drm, "failed to map registers\n");
> return -EIO;
> @@ -2074,9 +2071,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
>
> void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
> {
> - struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
> -
> - pci_iounmap(pdev, uncore->regs);
> + iounmap(uncore->regs);
> }
>
> void intel_uncore_init_early(struct intel_uncore *uncore,
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 9a760952d46af..52fe3d89dd2b8 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -29,6 +29,7 @@
> #include <linux/notifier.h>
> #include <linux/hrtimer.h>
> #include <linux/io-64-nonatomic-lo-hi.h>
> +#include <linux/types.h>
>
> #include "i915_reg_defs.h"
>
> @@ -221,7 +222,7 @@ void
> intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
> void intel_uncore_init_early(struct intel_uncore *uncore,
> struct intel_gt *gt);
> -int intel_uncore_setup_mmio(struct intel_uncore *uncore);
> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
> int intel_uncore_init_mmio(struct intel_uncore *uncore);
> void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
> struct intel_gt *gt);
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 573d9b2e1a4a3..9c31a16f83800 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -73,7 +73,7 @@ static void mock_device_release(struct drm_device *dev)
> destroy_workqueue(i915->wq);
>
> intel_region_ttm_device_fini(i915);
> - intel_gt_driver_late_release(to_gt(i915));
> + intel_gt_driver_late_release_all(i915);
> intel_memory_regions_driver_release(i915);
>
> drm_mode_config_cleanup(&i915->drm);
> @@ -112,6 +112,11 @@ static struct dev_pm_domain pm_domain = {
> },
> };
>
> +static void mock_gt_probe(struct drm_i915_private *i915)
> +{
> + i915->gt[0] = &i915->gt0;
> +}
> +
> struct drm_i915_private *mock_gem_device(void)
> {
> #if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU)
> @@ -180,11 +185,11 @@ struct drm_i915_private *mock_gem_device(void)
> spin_lock_init(&i915->gpu_error.lock);
>
> i915_gem_init__mm(i915);
> - intel_gt_init_early(to_gt(i915), i915);
> - __intel_gt_init_early(to_gt(i915), i915);
> + intel_root_gt_init_early(i915);
> mock_uncore_init(&i915->uncore, i915);
> atomic_inc(&to_gt(i915)->wakeref.count); /* disable; no hw support */
> to_gt(i915)->awake = -ENODEV;
> + mock_gt_probe(i915);
>
> ret = intel_region_ttm_device_init(i915);
> if (ret)
> @@ -229,7 +234,7 @@ struct drm_i915_private *mock_gem_device(void)
> err_drv:
> intel_region_ttm_device_fini(i915);
> err_ttm:
> - intel_gt_driver_late_release(to_gt(i915));
> + intel_gt_driver_late_release_all(i915);
> intel_memory_regions_driver_release(i915);
> drm_mode_config_cleanup(&i915->drm);
> mock_destroy_device(i915);
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
@ 2022-05-11 19:11 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 40+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-05-11 19:11 UTC (permalink / raw)
To: Andi Shyti, Intel GFX, DRI Devel
Cc: Lucas De Marchi, Chris Wilson, Matthew Auld
On 3/18/2022 4:39 PM, Andi Shyti wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four GTs are supported in i915->gt[], with slot zero
> shadowing the existing i915->gt0 to enable source compatibility
> with legacy driver paths. A for_each_gt macro is added to iterate
> over the GTs and will be used by upcoming patches that convert
> various parts of the driver to be multi-gt aware.
>
> Only the primary/root tile is initialized for now; the other
> tiles will be detected and plugged in by future patches once the
> necessary infrastructure is in place to handle them.
>
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@gmail.com>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 133 ++++++++++++++++--
> drivers/gpu/drm/i915/gt/intel_gt.h | 17 ++-
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
> drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
> drivers/gpu/drm/i915/i915_driver.c | 28 ++--
> drivers/gpu/drm/i915/i915_drv.h | 6 +
> drivers/gpu/drm/i915/intel_memory_region.h | 3 +
> drivers/gpu/drm/i915/intel_uncore.c | 11 +-
> drivers/gpu/drm/i915/intel_uncore.h | 3 +-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 13 +-
> 10 files changed, 184 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index ca875ba3e2a9d..cfac4a913642e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -29,7 +29,7 @@
> #include "intel_uncore.h"
> #include "shmem_utils.h"
>
> -void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> +static void __intel_gt_init_early(struct intel_gt *gt)
> {
> spin_lock_init(>->irq_lock);
>
> @@ -51,17 +51,23 @@ void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> intel_rps_init_early(>->rps);
> }
>
> -void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915)
> +/* Preliminary initialization of Tile 0 */
> +void intel_root_gt_init_early(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt = to_gt(i915);
> +
> gt->i915 = i915;
> gt->uncore = &i915->uncore;
> +
> + __intel_gt_init_early(gt);
> }
>
> -int intel_gt_probe_lmem(struct intel_gt *gt)
> +static int intel_gt_probe_lmem(struct intel_gt *gt)
> {
> struct drm_i915_private *i915 = gt->i915;
> + unsigned int instance = gt->info.id;
> + int id = INTEL_REGION_LMEM_0 + instance;
> struct intel_memory_region *mem;
> - int id;
> int err;
>
> mem = intel_gt_setup_lmem(gt);
> @@ -76,9 +82,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
> return err;
> }
>
> - id = INTEL_REGION_LMEM_0;
> -
> mem->id = id;
> + mem->instance = instance;
>
> intel_memory_region_set_name(mem, "local%u", mem->instance);
>
> @@ -807,16 +812,21 @@ void intel_gt_driver_release(struct intel_gt *gt)
> intel_gt_fini_hwconfig(gt);
> }
>
> -void intel_gt_driver_late_release(struct intel_gt *gt)
> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
> {
> + struct intel_gt *gt;
> + unsigned int id;
> +
> /* We need to wait for inflight RCU frees to release their grip */
> rcu_barrier();
>
> - intel_uc_driver_late_release(>->uc);
> - intel_gt_fini_requests(gt);
> - intel_gt_fini_reset(gt);
> - intel_gt_fini_timelines(gt);
> - intel_engines_free(gt);
> + for_each_gt(gt, i915, id) {
> + intel_uc_driver_late_release(>->uc);
> + intel_gt_fini_requests(gt);
> + intel_gt_fini_reset(gt);
> + intel_gt_fini_timelines(gt);
> + intel_engines_free(gt);
> + }
> }
>
> /**
> @@ -1013,6 +1023,105 @@ void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
> }
> }
>
> +static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t phys_addr)
> +{
> + int ret;
> +
> + if (!gt_is_root(gt)) {
> + struct intel_uncore_mmio_debug *mmio_debug;
> + struct intel_uncore *uncore;
> +
> + uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
> + if (!uncore)
> + return -ENOMEM;
> +
> + mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
> + if (!mmio_debug) {
> + kfree(uncore);
> + return -ENOMEM;
> + }
> +
> + gt->uncore = uncore;
> + gt->uncore->debug = mmio_debug;
> +
> + __intel_gt_init_early(gt);
> + }
> +
> + intel_uncore_init_early(gt->uncore, gt);
> +
> + ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
> + if (ret)
> + return ret;
> +
> + gt->phys_addr = phys_addr;
> +
> + return 0;
> +}
> +
> +static void
> +intel_gt_tile_cleanup(struct intel_gt *gt)
> +{
> + intel_uncore_cleanup_mmio(gt->uncore);
> +
> + if (!gt_is_root(gt)) {
> + kfree(gt->uncore->debug);
> + kfree(gt->uncore);
> + kfree(gt);
> + }
> +}
> +
> +int intel_gt_probe_all(struct drm_i915_private *i915)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct intel_gt *gt = &i915->gt0;
> + phys_addr_t phys_addr;
> + unsigned int mmio_bar;
> + int ret;
> +
> + mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
> + phys_addr = pci_resource_start(pdev, mmio_bar);
> +
> + /*
> + * We always have at least one primary GT on any device
> + * and it has been already initialized early during probe
> + * in i915_driver_probe()
> + */
> + ret = intel_gt_tile_setup(gt, phys_addr);
> + if (ret)
> + return ret;
> +
> + i915->gt[0] = gt;
> +
> + /* TODO: add more tiles */
> + return 0;
> +}
> +
> +int intel_gt_tiles_init(struct drm_i915_private *i915)
> +{
> + struct intel_gt *gt;
> + unsigned int id;
> + int ret;
> +
> + for_each_gt(gt, i915, id) {
> + ret = intel_gt_probe_lmem(gt);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +void intel_gt_release_all(struct drm_i915_private *i915)
> +{
> + struct intel_gt *gt;
> + unsigned int id;
> +
> + for_each_gt(gt, i915, id) {
> + intel_gt_tile_cleanup(gt);
> + i915->gt[id] = NULL;
> + }
> +}
> +
> void intel_gt_info_print(const struct intel_gt_info *info,
> struct drm_printer *p)
> {
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index ce471aa5c83d7..e76168e10a21b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -39,10 +39,8 @@ static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
> return container_of(huc, struct intel_gt, uc.huc);
> }
>
> -void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
> -void __intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915);
> +void intel_root_gt_init_early(struct drm_i915_private *i915);
> int intel_gt_assign_ggtt(struct intel_gt *gt);
> -int intel_gt_probe_lmem(struct intel_gt *gt);
> int intel_gt_init_mmio(struct intel_gt *gt);
> int __must_check intel_gt_init_hw(struct intel_gt *gt);
> int intel_gt_init(struct intel_gt *gt);
> @@ -52,7 +50,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt);
> void intel_gt_driver_remove(struct intel_gt *gt);
> void intel_gt_driver_release(struct intel_gt *gt);
>
> -void intel_gt_driver_late_release(struct intel_gt *gt);
> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
>
> int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
>
> @@ -97,6 +95,17 @@ u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
>
> void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
> bool dump_table);
> +
> +int intel_gt_probe_all(struct drm_i915_private *i915);
> +int intel_gt_tiles_init(struct drm_i915_private *i915);
> +void intel_gt_release_all(struct drm_i915_private *i915);
> +
> +#define for_each_gt(gt__, i915__, id__) \
> + for ((id__) = 0; \
> + (id__) < I915_MAX_GT; \
> + (id__)++) \
> + for_each_if(((gt__) = (i915__)->gt[(id__)]))
> +
> void intel_gt_info_print(const struct intel_gt_info *info,
> struct drm_printer *p);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index e4ecc17889d34..eeead40485fbc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -129,7 +129,14 @@ static const struct intel_wakeref_ops wf_ops = {
>
> void intel_gt_pm_init_early(struct intel_gt *gt)
> {
> - intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
> + /*
> + * We access the runtime_pm structure via gt->i915 here rather than
> + * gt->uncore as we do elsewhere in the file because gt->uncore is not
> + * yet initialized for all tiles at this point in the driver startup.
> + * runtime_pm is per-device rather than per-tile, so this is still the
> + * correct structure.
> + */
> + intel_wakeref_init(>->wakeref, >->i915->runtime_pm, &wf_ops);
> seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index bbba885d45bd5..937b2e1a305ed 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -188,7 +188,14 @@ struct intel_gt {
> u8 instanceid;
> } default_steering;
>
> + /*
> + * Base of per-tile GTTMMADR where we can derive the MMIO and the GGTT.
> + */
> + phys_addr_t phys_addr;
> +
> struct intel_gt_info {
> + unsigned int id;
> +
> intel_engine_mask_t engine_mask;
>
> u32 l3bank_mask;
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 92a625a174e22..64e6f76861f95 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -321,9 +321,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> intel_device_info_subplatform_init(dev_priv);
> intel_step_init(dev_priv);
>
> - intel_gt_init_early(to_gt(dev_priv), dev_priv);
> intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
> - intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv));
>
> spin_lock_init(&dev_priv->irq_lock);
> spin_lock_init(&dev_priv->gpu_error.lock);
> @@ -354,7 +352,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> intel_wopcm_init_early(&dev_priv->wopcm);
>
> - __intel_gt_init_early(to_gt(dev_priv), dev_priv);
> + intel_root_gt_init_early(dev_priv);
>
> i915_gem_init_early(dev_priv);
>
> @@ -375,7 +373,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> err_gem:
> i915_gem_cleanup_early(dev_priv);
> - intel_gt_driver_late_release(to_gt(dev_priv));
> + intel_gt_driver_late_release_all(dev_priv);
> intel_region_ttm_device_fini(dev_priv);
> err_ttm:
> vlv_suspend_cleanup(dev_priv);
> @@ -394,7 +392,7 @@ static void i915_driver_late_release(struct drm_i915_private *dev_priv)
> intel_irq_fini(dev_priv);
> intel_power_domains_cleanup(dev_priv);
> i915_gem_cleanup_early(dev_priv);
> - intel_gt_driver_late_release(to_gt(dev_priv));
> + intel_gt_driver_late_release_all(dev_priv);
> intel_region_ttm_device_fini(dev_priv);
> vlv_suspend_cleanup(dev_priv);
> i915_workqueues_cleanup(dev_priv);
> @@ -425,13 +423,9 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
> if (ret < 0)
> return ret;
>
> - ret = intel_uncore_setup_mmio(&dev_priv->uncore);
> - if (ret < 0)
> - goto err_bridge;
> -
> ret = intel_uncore_init_mmio(&dev_priv->uncore);
> if (ret)
> - goto err_mmio;
> + return ret;
>
> /* Try to make sure MCHBAR is enabled before poking at it */
> intel_setup_mchbar(dev_priv);
> @@ -449,9 +443,6 @@ static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
> err_uncore:
> intel_teardown_mchbar(dev_priv);
> intel_uncore_fini_mmio(&dev_priv->uncore);
> -err_mmio:
> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
> -err_bridge:
> pci_dev_put(dev_priv->bridge_dev);
>
> return ret;
> @@ -465,7 +456,6 @@ static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
> {
> intel_teardown_mchbar(dev_priv);
> intel_uncore_fini_mmio(&dev_priv->uncore);
> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
> pci_dev_put(dev_priv->bridge_dev);
> }
>
> @@ -598,7 +588,7 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
> if (ret)
> goto err_ggtt;
>
> - ret = intel_gt_probe_lmem(to_gt(dev_priv));
> + ret = intel_gt_tiles_init(dev_priv);
> if (ret)
> goto err_mem_regions;
>
> @@ -849,10 +839,14 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>
> intel_vgpu_detect(i915);
>
> - ret = i915_driver_mmio_probe(i915);
> + ret = intel_gt_probe_all(i915);
> if (ret < 0)
> goto out_runtime_pm_put;
>
> + ret = i915_driver_mmio_probe(i915);
> + if (ret < 0)
> + goto out_tiles_cleanup;
> +
> ret = i915_driver_hw_probe(i915);
> if (ret < 0)
> goto out_cleanup_mmio;
> @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> i915_ggtt_driver_late_release(i915);
> out_cleanup_mmio:
> i915_driver_mmio_release(i915);
> +out_tiles_cleanup:
> + intel_gt_release_all(i915);
We don't seem to call intel_gt_release_all() from driver_release(), so
we might be leaking something there. I wanted to send a patch to add the
call at the same place in the flow as in this error path, but then I
noticed that i915_driver_late_release(), which we call a few lines
below, calls intel_gt_driver_late_release_all(), which seems to expect
that the GTs are still allocated, so we probably need to flip the order
those are called in, or move the cleanup code from late_release() to
late_release_all() (or vice versa).
Andi, can you have a look at this?
Thanks,
Daniele
> out_runtime_pm_put:
> enable_rpm_wakeref_asserts(&i915->runtime_pm);
> i915_driver_late_release(i915);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 97622d3ccfc2a..8e4083d413592 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -777,6 +777,12 @@ struct drm_i915_private {
> /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
> struct intel_gt gt0;
>
> + /*
> + * i915->gt[0] == &i915->gt0
> + */
> +#define I915_MAX_GT 4
> + struct intel_gt *gt[I915_MAX_GT];
> +
> struct {
> struct i915_gem_contexts {
> spinlock_t lock; /* locks list */
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
> index cc7078bcbfbfc..3d8378c1b4478 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.h
> +++ b/drivers/gpu/drm/i915/intel_memory_region.h
> @@ -30,6 +30,9 @@ enum intel_memory_type {
> enum intel_region_id {
> INTEL_REGION_SMEM = 0,
> INTEL_REGION_LMEM_0,
> + INTEL_REGION_LMEM_1,
> + INTEL_REGION_LMEM_2,
> + INTEL_REGION_LMEM_3,
> INTEL_REGION_STOLEN_SMEM,
> INTEL_REGION_STOLEN_LMEM,
> INTEL_REGION_UNKNOWN, /* Should be last */
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index ef8ffc01ad19c..8b9caaaacc21f 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -2039,14 +2039,11 @@ static int i915_pmic_bus_access_notifier(struct notifier_block *nb,
> return NOTIFY_OK;
> }
>
> -int intel_uncore_setup_mmio(struct intel_uncore *uncore)
> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr)
> {
> struct drm_i915_private *i915 = uncore->i915;
> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> - int mmio_bar;
> int mmio_size;
>
> - mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
> /*
> * Before gen4, the registers and the GTT are behind different BARs.
> * However, from gen4 onwards, the registers and the GTT are shared
> @@ -2063,7 +2060,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
> else
> mmio_size = 2 * 1024 * 1024;
>
> - uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
> + uncore->regs = ioremap(phys_addr, mmio_size);
> if (uncore->regs == NULL) {
> drm_err(&i915->drm, "failed to map registers\n");
> return -EIO;
> @@ -2074,9 +2071,7 @@ int intel_uncore_setup_mmio(struct intel_uncore *uncore)
>
> void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
> {
> - struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
> -
> - pci_iounmap(pdev, uncore->regs);
> + iounmap(uncore->regs);
> }
>
> void intel_uncore_init_early(struct intel_uncore *uncore,
> diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
> index 9a760952d46af..52fe3d89dd2b8 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.h
> +++ b/drivers/gpu/drm/i915/intel_uncore.h
> @@ -29,6 +29,7 @@
> #include <linux/notifier.h>
> #include <linux/hrtimer.h>
> #include <linux/io-64-nonatomic-lo-hi.h>
> +#include <linux/types.h>
>
> #include "i915_reg_defs.h"
>
> @@ -221,7 +222,7 @@ void
> intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug);
> void intel_uncore_init_early(struct intel_uncore *uncore,
> struct intel_gt *gt);
> -int intel_uncore_setup_mmio(struct intel_uncore *uncore);
> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr);
> int intel_uncore_init_mmio(struct intel_uncore *uncore);
> void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
> struct intel_gt *gt);
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index 573d9b2e1a4a3..9c31a16f83800 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -73,7 +73,7 @@ static void mock_device_release(struct drm_device *dev)
> destroy_workqueue(i915->wq);
>
> intel_region_ttm_device_fini(i915);
> - intel_gt_driver_late_release(to_gt(i915));
> + intel_gt_driver_late_release_all(i915);
> intel_memory_regions_driver_release(i915);
>
> drm_mode_config_cleanup(&i915->drm);
> @@ -112,6 +112,11 @@ static struct dev_pm_domain pm_domain = {
> },
> };
>
> +static void mock_gt_probe(struct drm_i915_private *i915)
> +{
> + i915->gt[0] = &i915->gt0;
> +}
> +
> struct drm_i915_private *mock_gem_device(void)
> {
> #if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU)
> @@ -180,11 +185,11 @@ struct drm_i915_private *mock_gem_device(void)
> spin_lock_init(&i915->gpu_error.lock);
>
> i915_gem_init__mm(i915);
> - intel_gt_init_early(to_gt(i915), i915);
> - __intel_gt_init_early(to_gt(i915), i915);
> + intel_root_gt_init_early(i915);
> mock_uncore_init(&i915->uncore, i915);
> atomic_inc(&to_gt(i915)->wakeref.count); /* disable; no hw support */
> to_gt(i915)->awake = -ENODEV;
> + mock_gt_probe(i915);
>
> ret = intel_region_ttm_device_init(i915);
> if (ret)
> @@ -229,7 +234,7 @@ struct drm_i915_private *mock_gem_device(void)
> err_drv:
> intel_region_ttm_device_fini(i915);
> err_ttm:
> - intel_gt_driver_late_release(to_gt(i915));
> + intel_gt_driver_late_release_all(i915);
> intel_memory_regions_driver_release(i915);
> drm_mode_config_cleanup(&i915->drm);
> mock_destroy_device(i915);
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
2022-05-11 19:11 ` [Intel-gfx] " Ceraolo Spurio, Daniele
@ 2022-05-19 14:53 ` Ceraolo Spurio, Daniele
-1 siblings, 0 replies; 40+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-05-19 14:53 UTC (permalink / raw)
To: Andi Shyti, Intel GFX, DRI Devel
Cc: Sujaritha Sundaresan, Tvrtko Ursulin, Lucas De Marchi,
Chris Wilson, Matthew Auld, Andi Shyti, Michal Wajdeczko
On 5/11/2022 12:11 PM, Ceraolo Spurio, Daniele wrote:
>
>
> On 3/18/2022 4:39 PM, Andi Shyti wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> On a multi-tile platform, each tile has its own registers + GGTT
>> space, and BAR 0 is extended to cover all of them.
>>
>> Up to four GTs are supported in i915->gt[], with slot zero
>> shadowing the existing i915->gt0 to enable source compatibility
>> with legacy driver paths. A for_each_gt macro is added to iterate
>> over the GTs and will be used by upcoming patches that convert
>> various parts of the driver to be multi-gt aware.
>>
>> Only the primary/root tile is initialized for now; the other
>> tiles will be detected and plugged in by future patches once the
>> necessary infrastructure is in place to handle them.
>>
>> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@gmail.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Matthew Auld <matthew.auld@intel.com>
>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_gt.c | 133 ++++++++++++++++--
>> drivers/gpu/drm/i915/gt/intel_gt.h | 17 ++-
>> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
>> drivers/gpu/drm/i915/i915_driver.c | 28 ++--
>> drivers/gpu/drm/i915/i915_drv.h | 6 +
>> drivers/gpu/drm/i915/intel_memory_region.h | 3 +
>> drivers/gpu/drm/i915/intel_uncore.c | 11 +-
>> drivers/gpu/drm/i915/intel_uncore.h | 3 +-
>> .../gpu/drm/i915/selftests/mock_gem_device.c | 13 +-
>> 10 files changed, 184 insertions(+), 46 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
>> b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index ca875ba3e2a9d..cfac4a913642e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -29,7 +29,7 @@
>> #include "intel_uncore.h"
>> #include "shmem_utils.h"
>> -void __intel_gt_init_early(struct intel_gt *gt, struct
>> drm_i915_private *i915)
>> +static void __intel_gt_init_early(struct intel_gt *gt)
>> {
>> spin_lock_init(>->irq_lock);
>> @@ -51,17 +51,23 @@ void __intel_gt_init_early(struct intel_gt *gt,
>> struct drm_i915_private *i915)
>> intel_rps_init_early(>->rps);
>> }
>> -void intel_gt_init_early(struct intel_gt *gt, struct
>> drm_i915_private *i915)
>> +/* Preliminary initialization of Tile 0 */
>> +void intel_root_gt_init_early(struct drm_i915_private *i915)
>> {
>> + struct intel_gt *gt = to_gt(i915);
>> +
>> gt->i915 = i915;
>> gt->uncore = &i915->uncore;
>> +
>> + __intel_gt_init_early(gt);
>> }
>> -int intel_gt_probe_lmem(struct intel_gt *gt)
>> +static int intel_gt_probe_lmem(struct intel_gt *gt)
>> {
>> struct drm_i915_private *i915 = gt->i915;
>> + unsigned int instance = gt->info.id;
>> + int id = INTEL_REGION_LMEM_0 + instance;
>> struct intel_memory_region *mem;
>> - int id;
>> int err;
>> mem = intel_gt_setup_lmem(gt);
>> @@ -76,9 +82,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
>> return err;
>> }
>> - id = INTEL_REGION_LMEM_0;
>> -
>> mem->id = id;
>> + mem->instance = instance;
>> intel_memory_region_set_name(mem, "local%u", mem->instance);
>> @@ -807,16 +812,21 @@ void intel_gt_driver_release(struct intel_gt
>> *gt)
>> intel_gt_fini_hwconfig(gt);
>> }
>> -void intel_gt_driver_late_release(struct intel_gt *gt)
>> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
>> {
>> + struct intel_gt *gt;
>> + unsigned int id;
>> +
>> /* We need to wait for inflight RCU frees to release their grip */
>> rcu_barrier();
>> - intel_uc_driver_late_release(>->uc);
>> - intel_gt_fini_requests(gt);
>> - intel_gt_fini_reset(gt);
>> - intel_gt_fini_timelines(gt);
>> - intel_engines_free(gt);
>> + for_each_gt(gt, i915, id) {
>> + intel_uc_driver_late_release(>->uc);
>> + intel_gt_fini_requests(gt);
>> + intel_gt_fini_reset(gt);
>> + intel_gt_fini_timelines(gt);
>> + intel_engines_free(gt);
>> + }
>> }
>> /**
>> @@ -1013,6 +1023,105 @@ void intel_gt_report_steering(struct
>> drm_printer *p, struct intel_gt *gt,
>> }
>> }
>> +static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t
>> phys_addr)
>> +{
>> + int ret;
>> +
>> + if (!gt_is_root(gt)) {
>> + struct intel_uncore_mmio_debug *mmio_debug;
>> + struct intel_uncore *uncore;
>> +
>> + uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
>> + if (!uncore)
>> + return -ENOMEM;
>> +
>> + mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
>> + if (!mmio_debug) {
>> + kfree(uncore);
>> + return -ENOMEM;
>> + }
>> +
>> + gt->uncore = uncore;
>> + gt->uncore->debug = mmio_debug;
>> +
>> + __intel_gt_init_early(gt);
>> + }
>> +
>> + intel_uncore_init_early(gt->uncore, gt);
>> +
>> + ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
>> + if (ret)
>> + return ret;
>> +
>> + gt->phys_addr = phys_addr;
>> +
>> + return 0;
>> +}
>> +
>> +static void
>> +intel_gt_tile_cleanup(struct intel_gt *gt)
>> +{
>> + intel_uncore_cleanup_mmio(gt->uncore);
>> +
>> + if (!gt_is_root(gt)) {
>> + kfree(gt->uncore->debug);
>> + kfree(gt->uncore);
>> + kfree(gt);
>> + }
>> +}
>> +
>> +int intel_gt_probe_all(struct drm_i915_private *i915)
>> +{
>> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> + struct intel_gt *gt = &i915->gt0;
>> + phys_addr_t phys_addr;
>> + unsigned int mmio_bar;
>> + int ret;
>> +
>> + mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
>> + phys_addr = pci_resource_start(pdev, mmio_bar);
>> +
>> + /*
>> + * We always have at least one primary GT on any device
>> + * and it has been already initialized early during probe
>> + * in i915_driver_probe()
>> + */
>> + ret = intel_gt_tile_setup(gt, phys_addr);
>> + if (ret)
>> + return ret;
>> +
>> + i915->gt[0] = gt;
>> +
>> + /* TODO: add more tiles */
>> + return 0;
>> +}
>> +
>> +int intel_gt_tiles_init(struct drm_i915_private *i915)
>> +{
>> + struct intel_gt *gt;
>> + unsigned int id;
>> + int ret;
>> +
>> + for_each_gt(gt, i915, id) {
>> + ret = intel_gt_probe_lmem(gt);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +void intel_gt_release_all(struct drm_i915_private *i915)
>> +{
>> + struct intel_gt *gt;
>> + unsigned int id;
>> +
>> + for_each_gt(gt, i915, id) {
>> + intel_gt_tile_cleanup(gt);
>> + i915->gt[id] = NULL;
>> + }
>> +}
>> +
>> void intel_gt_info_print(const struct intel_gt_info *info,
>> struct drm_printer *p)
>> {
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
>> b/drivers/gpu/drm/i915/gt/intel_gt.h
>> index ce471aa5c83d7..e76168e10a21b 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>> @@ -39,10 +39,8 @@ static inline struct intel_gt *huc_to_gt(struct
>> intel_huc *huc)
>> return container_of(huc, struct intel_gt, uc.huc);
>> }
>> -void intel_gt_init_early(struct intel_gt *gt, struct
>> drm_i915_private *i915);
>> -void __intel_gt_init_early(struct intel_gt *gt, struct
>> drm_i915_private *i915);
>> +void intel_root_gt_init_early(struct drm_i915_private *i915);
>> int intel_gt_assign_ggtt(struct intel_gt *gt);
>> -int intel_gt_probe_lmem(struct intel_gt *gt);
>> int intel_gt_init_mmio(struct intel_gt *gt);
>> int __must_check intel_gt_init_hw(struct intel_gt *gt);
>> int intel_gt_init(struct intel_gt *gt);
>> @@ -52,7 +50,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt);
>> void intel_gt_driver_remove(struct intel_gt *gt);
>> void intel_gt_driver_release(struct intel_gt *gt);
>> -void intel_gt_driver_late_release(struct intel_gt *gt);
>> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
>> int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
>> @@ -97,6 +95,17 @@ u32 intel_gt_read_register(struct intel_gt *gt,
>> i915_reg_t reg);
>> void intel_gt_report_steering(struct drm_printer *p, struct
>> intel_gt *gt,
>> bool dump_table);
>> +
>> +int intel_gt_probe_all(struct drm_i915_private *i915);
>> +int intel_gt_tiles_init(struct drm_i915_private *i915);
>> +void intel_gt_release_all(struct drm_i915_private *i915);
>> +
>> +#define for_each_gt(gt__, i915__, id__) \
>> + for ((id__) = 0; \
>> + (id__) < I915_MAX_GT; \
>> + (id__)++) \
>> + for_each_if(((gt__) = (i915__)->gt[(id__)]))
>> +
>> void intel_gt_info_print(const struct intel_gt_info *info,
>> struct drm_printer *p);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> index e4ecc17889d34..eeead40485fbc 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> @@ -129,7 +129,14 @@ static const struct intel_wakeref_ops wf_ops = {
>> void intel_gt_pm_init_early(struct intel_gt *gt)
>> {
>> - intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
>> + /*
>> + * We access the runtime_pm structure via gt->i915 here rather than
>> + * gt->uncore as we do elsewhere in the file because gt->uncore
>> is not
>> + * yet initialized for all tiles at this point in the driver
>> startup.
>> + * runtime_pm is per-device rather than per-tile, so this is
>> still the
>> + * correct structure.
>> + */
>> + intel_wakeref_init(>->wakeref, >->i915->runtime_pm, &wf_ops);
>> seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> index bbba885d45bd5..937b2e1a305ed 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> @@ -188,7 +188,14 @@ struct intel_gt {
>> u8 instanceid;
>> } default_steering;
>> + /*
>> + * Base of per-tile GTTMMADR where we can derive the MMIO and
>> the GGTT.
>> + */
>> + phys_addr_t phys_addr;
>> +
>> struct intel_gt_info {
>> + unsigned int id;
>> +
>> intel_engine_mask_t engine_mask;
>> u32 l3bank_mask;
>> diff --git a/drivers/gpu/drm/i915/i915_driver.c
>> b/drivers/gpu/drm/i915/i915_driver.c
>> index 92a625a174e22..64e6f76861f95 100644
>> --- a/drivers/gpu/drm/i915/i915_driver.c
>> +++ b/drivers/gpu/drm/i915/i915_driver.c
>> @@ -321,9 +321,7 @@ static int i915_driver_early_probe(struct
>> drm_i915_private *dev_priv)
>> intel_device_info_subplatform_init(dev_priv);
>> intel_step_init(dev_priv);
>> - intel_gt_init_early(to_gt(dev_priv), dev_priv);
>> intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
>> - intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv));
>> spin_lock_init(&dev_priv->irq_lock);
>> spin_lock_init(&dev_priv->gpu_error.lock);
>> @@ -354,7 +352,7 @@ static int i915_driver_early_probe(struct
>> drm_i915_private *dev_priv)
>> intel_wopcm_init_early(&dev_priv->wopcm);
>> - __intel_gt_init_early(to_gt(dev_priv), dev_priv);
>> + intel_root_gt_init_early(dev_priv);
>> i915_gem_init_early(dev_priv);
>> @@ -375,7 +373,7 @@ static int i915_driver_early_probe(struct
>> drm_i915_private *dev_priv)
>> err_gem:
>> i915_gem_cleanup_early(dev_priv);
>> - intel_gt_driver_late_release(to_gt(dev_priv));
>> + intel_gt_driver_late_release_all(dev_priv);
>> intel_region_ttm_device_fini(dev_priv);
>> err_ttm:
>> vlv_suspend_cleanup(dev_priv);
>> @@ -394,7 +392,7 @@ static void i915_driver_late_release(struct
>> drm_i915_private *dev_priv)
>> intel_irq_fini(dev_priv);
>> intel_power_domains_cleanup(dev_priv);
>> i915_gem_cleanup_early(dev_priv);
>> - intel_gt_driver_late_release(to_gt(dev_priv));
>> + intel_gt_driver_late_release_all(dev_priv);
>> intel_region_ttm_device_fini(dev_priv);
>> vlv_suspend_cleanup(dev_priv);
>> i915_workqueues_cleanup(dev_priv);
>> @@ -425,13 +423,9 @@ static int i915_driver_mmio_probe(struct
>> drm_i915_private *dev_priv)
>> if (ret < 0)
>> return ret;
>> - ret = intel_uncore_setup_mmio(&dev_priv->uncore);
>> - if (ret < 0)
>> - goto err_bridge;
>> -
>> ret = intel_uncore_init_mmio(&dev_priv->uncore);
>> if (ret)
>> - goto err_mmio;
>> + return ret;
>> /* Try to make sure MCHBAR is enabled before poking at it */
>> intel_setup_mchbar(dev_priv);
>> @@ -449,9 +443,6 @@ static int i915_driver_mmio_probe(struct
>> drm_i915_private *dev_priv)
>> err_uncore:
>> intel_teardown_mchbar(dev_priv);
>> intel_uncore_fini_mmio(&dev_priv->uncore);
>> -err_mmio:
>> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
>> -err_bridge:
>> pci_dev_put(dev_priv->bridge_dev);
>> return ret;
>> @@ -465,7 +456,6 @@ static void i915_driver_mmio_release(struct
>> drm_i915_private *dev_priv)
>> {
>> intel_teardown_mchbar(dev_priv);
>> intel_uncore_fini_mmio(&dev_priv->uncore);
>> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
>> pci_dev_put(dev_priv->bridge_dev);
>> }
>> @@ -598,7 +588,7 @@ static int i915_driver_hw_probe(struct
>> drm_i915_private *dev_priv)
>> if (ret)
>> goto err_ggtt;
>> - ret = intel_gt_probe_lmem(to_gt(dev_priv));
>> + ret = intel_gt_tiles_init(dev_priv);
>> if (ret)
>> goto err_mem_regions;
>> @@ -849,10 +839,14 @@ int i915_driver_probe(struct pci_dev *pdev,
>> const struct pci_device_id *ent)
>> intel_vgpu_detect(i915);
>> - ret = i915_driver_mmio_probe(i915);
>> + ret = intel_gt_probe_all(i915);
>> if (ret < 0)
>> goto out_runtime_pm_put;
>> + ret = i915_driver_mmio_probe(i915);
>> + if (ret < 0)
>> + goto out_tiles_cleanup;
>> +
>> ret = i915_driver_hw_probe(i915);
>> if (ret < 0)
>> goto out_cleanup_mmio;
>> @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev, const
>> struct pci_device_id *ent)
>> i915_ggtt_driver_late_release(i915);
>> out_cleanup_mmio:
>> i915_driver_mmio_release(i915);
>> +out_tiles_cleanup:
>> + intel_gt_release_all(i915);
>
> We don't seem to call intel_gt_release_all() from driver_release(), so
> we might be leaking something there. I wanted to send a patch to add
> the call at the same place in the flow as in this error path, but then
> I noticed that i915_driver_late_release(), which we call a few lines
> below, calls intel_gt_driver_late_release_all(), which seems to expect
> that the GTs are still allocated, so we probably need to flip the
> order those are called in, or move the cleanup code from
> late_release() to late_release_all() (or vice versa).
> Andi, can you have a look at this?
>
Ping! :)
Daniele
> Thanks,
> Daniele
>
>> out_runtime_pm_put:
>> enable_rpm_wakeref_asserts(&i915->runtime_pm);
>> i915_driver_late_release(i915);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 97622d3ccfc2a..8e4083d413592 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -777,6 +777,12 @@ struct drm_i915_private {
>> /* Abstract the submission mechanism (legacy ringbuffer or
>> execlists) away */
>> struct intel_gt gt0;
>> + /*
>> + * i915->gt[0] == &i915->gt0
>> + */
>> +#define I915_MAX_GT 4
>> + struct intel_gt *gt[I915_MAX_GT];
>> +
>> struct {
>> struct i915_gem_contexts {
>> spinlock_t lock; /* locks list */
>> diff --git a/drivers/gpu/drm/i915/intel_memory_region.h
>> b/drivers/gpu/drm/i915/intel_memory_region.h
>> index cc7078bcbfbfc..3d8378c1b4478 100644
>> --- a/drivers/gpu/drm/i915/intel_memory_region.h
>> +++ b/drivers/gpu/drm/i915/intel_memory_region.h
>> @@ -30,6 +30,9 @@ enum intel_memory_type {
>> enum intel_region_id {
>> INTEL_REGION_SMEM = 0,
>> INTEL_REGION_LMEM_0,
>> + INTEL_REGION_LMEM_1,
>> + INTEL_REGION_LMEM_2,
>> + INTEL_REGION_LMEM_3,
>> INTEL_REGION_STOLEN_SMEM,
>> INTEL_REGION_STOLEN_LMEM,
>> INTEL_REGION_UNKNOWN, /* Should be last */
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
>> b/drivers/gpu/drm/i915/intel_uncore.c
>> index ef8ffc01ad19c..8b9caaaacc21f 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -2039,14 +2039,11 @@ static int
>> i915_pmic_bus_access_notifier(struct notifier_block *nb,
>> return NOTIFY_OK;
>> }
>> -int intel_uncore_setup_mmio(struct intel_uncore *uncore)
>> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t
>> phys_addr)
>> {
>> struct drm_i915_private *i915 = uncore->i915;
>> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> - int mmio_bar;
>> int mmio_size;
>> - mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
>> /*
>> * Before gen4, the registers and the GTT are behind different
>> BARs.
>> * However, from gen4 onwards, the registers and the GTT are
>> shared
>> @@ -2063,7 +2060,7 @@ int intel_uncore_setup_mmio(struct intel_uncore
>> *uncore)
>> else
>> mmio_size = 2 * 1024 * 1024;
>> - uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
>> + uncore->regs = ioremap(phys_addr, mmio_size);
>> if (uncore->regs == NULL) {
>> drm_err(&i915->drm, "failed to map registers\n");
>> return -EIO;
>> @@ -2074,9 +2071,7 @@ int intel_uncore_setup_mmio(struct intel_uncore
>> *uncore)
>> void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
>> {
>> - struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
>> -
>> - pci_iounmap(pdev, uncore->regs);
>> + iounmap(uncore->regs);
>> }
>> void intel_uncore_init_early(struct intel_uncore *uncore,
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.h
>> b/drivers/gpu/drm/i915/intel_uncore.h
>> index 9a760952d46af..52fe3d89dd2b8 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.h
>> +++ b/drivers/gpu/drm/i915/intel_uncore.h
>> @@ -29,6 +29,7 @@
>> #include <linux/notifier.h>
>> #include <linux/hrtimer.h>
>> #include <linux/io-64-nonatomic-lo-hi.h>
>> +#include <linux/types.h>
>> #include "i915_reg_defs.h"
>> @@ -221,7 +222,7 @@ void
>> intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug
>> *mmio_debug);
>> void intel_uncore_init_early(struct intel_uncore *uncore,
>> struct intel_gt *gt);
>> -int intel_uncore_setup_mmio(struct intel_uncore *uncore);
>> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t
>> phys_addr);
>> int intel_uncore_init_mmio(struct intel_uncore *uncore);
>> void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
>> struct intel_gt *gt);
>> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> index 573d9b2e1a4a3..9c31a16f83800 100644
>> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> @@ -73,7 +73,7 @@ static void mock_device_release(struct drm_device
>> *dev)
>> destroy_workqueue(i915->wq);
>> intel_region_ttm_device_fini(i915);
>> - intel_gt_driver_late_release(to_gt(i915));
>> + intel_gt_driver_late_release_all(i915);
>> intel_memory_regions_driver_release(i915);
>> drm_mode_config_cleanup(&i915->drm);
>> @@ -112,6 +112,11 @@ static struct dev_pm_domain pm_domain = {
>> },
>> };
>> +static void mock_gt_probe(struct drm_i915_private *i915)
>> +{
>> + i915->gt[0] = &i915->gt0;
>> +}
>> +
>> struct drm_i915_private *mock_gem_device(void)
>> {
>> #if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU)
>> @@ -180,11 +185,11 @@ struct drm_i915_private *mock_gem_device(void)
>> spin_lock_init(&i915->gpu_error.lock);
>> i915_gem_init__mm(i915);
>> - intel_gt_init_early(to_gt(i915), i915);
>> - __intel_gt_init_early(to_gt(i915), i915);
>> + intel_root_gt_init_early(i915);
>> mock_uncore_init(&i915->uncore, i915);
>> atomic_inc(&to_gt(i915)->wakeref.count); /* disable; no hw
>> support */
>> to_gt(i915)->awake = -ENODEV;
>> + mock_gt_probe(i915);
>> ret = intel_region_ttm_device_init(i915);
>> if (ret)
>> @@ -229,7 +234,7 @@ struct drm_i915_private *mock_gem_device(void)
>> err_drv:
>> intel_region_ttm_device_fini(i915);
>> err_ttm:
>> - intel_gt_driver_late_release(to_gt(i915));
>> + intel_gt_driver_late_release_all(i915);
>> intel_memory_regions_driver_release(i915);
>> drm_mode_config_cleanup(&i915->drm);
>> mock_destroy_device(i915);
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
@ 2022-05-19 14:53 ` Ceraolo Spurio, Daniele
0 siblings, 0 replies; 40+ messages in thread
From: Ceraolo Spurio, Daniele @ 2022-05-19 14:53 UTC (permalink / raw)
To: Andi Shyti, Intel GFX, DRI Devel
Cc: Lucas De Marchi, Chris Wilson, Matthew Auld
On 5/11/2022 12:11 PM, Ceraolo Spurio, Daniele wrote:
>
>
> On 3/18/2022 4:39 PM, Andi Shyti wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> On a multi-tile platform, each tile has its own registers + GGTT
>> space, and BAR 0 is extended to cover all of them.
>>
>> Up to four GTs are supported in i915->gt[], with slot zero
>> shadowing the existing i915->gt0 to enable source compatibility
>> with legacy driver paths. A for_each_gt macro is added to iterate
>> over the GTs and will be used by upcoming patches that convert
>> various parts of the driver to be multi-gt aware.
>>
>> Only the primary/root tile is initialized for now; the other
>> tiles will be detected and plugged in by future patches once the
>> necessary infrastructure is in place to handle them.
>>
>> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@gmail.com>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Matthew Auld <matthew.auld@intel.com>
>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_gt.c | 133 ++++++++++++++++--
>> drivers/gpu/drm/i915/gt/intel_gt.h | 17 ++-
>> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 9 +-
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 7 +
>> drivers/gpu/drm/i915/i915_driver.c | 28 ++--
>> drivers/gpu/drm/i915/i915_drv.h | 6 +
>> drivers/gpu/drm/i915/intel_memory_region.h | 3 +
>> drivers/gpu/drm/i915/intel_uncore.c | 11 +-
>> drivers/gpu/drm/i915/intel_uncore.h | 3 +-
>> .../gpu/drm/i915/selftests/mock_gem_device.c | 13 +-
>> 10 files changed, 184 insertions(+), 46 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
>> b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index ca875ba3e2a9d..cfac4a913642e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -29,7 +29,7 @@
>> #include "intel_uncore.h"
>> #include "shmem_utils.h"
>> -void __intel_gt_init_early(struct intel_gt *gt, struct
>> drm_i915_private *i915)
>> +static void __intel_gt_init_early(struct intel_gt *gt)
>> {
>> spin_lock_init(>->irq_lock);
>> @@ -51,17 +51,23 @@ void __intel_gt_init_early(struct intel_gt *gt,
>> struct drm_i915_private *i915)
>> intel_rps_init_early(>->rps);
>> }
>> -void intel_gt_init_early(struct intel_gt *gt, struct
>> drm_i915_private *i915)
>> +/* Preliminary initialization of Tile 0 */
>> +void intel_root_gt_init_early(struct drm_i915_private *i915)
>> {
>> + struct intel_gt *gt = to_gt(i915);
>> +
>> gt->i915 = i915;
>> gt->uncore = &i915->uncore;
>> +
>> + __intel_gt_init_early(gt);
>> }
>> -int intel_gt_probe_lmem(struct intel_gt *gt)
>> +static int intel_gt_probe_lmem(struct intel_gt *gt)
>> {
>> struct drm_i915_private *i915 = gt->i915;
>> + unsigned int instance = gt->info.id;
>> + int id = INTEL_REGION_LMEM_0 + instance;
>> struct intel_memory_region *mem;
>> - int id;
>> int err;
>> mem = intel_gt_setup_lmem(gt);
>> @@ -76,9 +82,8 @@ int intel_gt_probe_lmem(struct intel_gt *gt)
>> return err;
>> }
>> - id = INTEL_REGION_LMEM_0;
>> -
>> mem->id = id;
>> + mem->instance = instance;
>> intel_memory_region_set_name(mem, "local%u", mem->instance);
>> @@ -807,16 +812,21 @@ void intel_gt_driver_release(struct intel_gt
>> *gt)
>> intel_gt_fini_hwconfig(gt);
>> }
>> -void intel_gt_driver_late_release(struct intel_gt *gt)
>> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915)
>> {
>> + struct intel_gt *gt;
>> + unsigned int id;
>> +
>> /* We need to wait for inflight RCU frees to release their grip */
>> rcu_barrier();
>> - intel_uc_driver_late_release(>->uc);
>> - intel_gt_fini_requests(gt);
>> - intel_gt_fini_reset(gt);
>> - intel_gt_fini_timelines(gt);
>> - intel_engines_free(gt);
>> + for_each_gt(gt, i915, id) {
>> + intel_uc_driver_late_release(>->uc);
>> + intel_gt_fini_requests(gt);
>> + intel_gt_fini_reset(gt);
>> + intel_gt_fini_timelines(gt);
>> + intel_engines_free(gt);
>> + }
>> }
>> /**
>> @@ -1013,6 +1023,105 @@ void intel_gt_report_steering(struct
>> drm_printer *p, struct intel_gt *gt,
>> }
>> }
>> +static int intel_gt_tile_setup(struct intel_gt *gt, phys_addr_t
>> phys_addr)
>> +{
>> + int ret;
>> +
>> + if (!gt_is_root(gt)) {
>> + struct intel_uncore_mmio_debug *mmio_debug;
>> + struct intel_uncore *uncore;
>> +
>> + uncore = kzalloc(sizeof(*uncore), GFP_KERNEL);
>> + if (!uncore)
>> + return -ENOMEM;
>> +
>> + mmio_debug = kzalloc(sizeof(*mmio_debug), GFP_KERNEL);
>> + if (!mmio_debug) {
>> + kfree(uncore);
>> + return -ENOMEM;
>> + }
>> +
>> + gt->uncore = uncore;
>> + gt->uncore->debug = mmio_debug;
>> +
>> + __intel_gt_init_early(gt);
>> + }
>> +
>> + intel_uncore_init_early(gt->uncore, gt);
>> +
>> + ret = intel_uncore_setup_mmio(gt->uncore, phys_addr);
>> + if (ret)
>> + return ret;
>> +
>> + gt->phys_addr = phys_addr;
>> +
>> + return 0;
>> +}
>> +
>> +static void
>> +intel_gt_tile_cleanup(struct intel_gt *gt)
>> +{
>> + intel_uncore_cleanup_mmio(gt->uncore);
>> +
>> + if (!gt_is_root(gt)) {
>> + kfree(gt->uncore->debug);
>> + kfree(gt->uncore);
>> + kfree(gt);
>> + }
>> +}
>> +
>> +int intel_gt_probe_all(struct drm_i915_private *i915)
>> +{
>> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> + struct intel_gt *gt = &i915->gt0;
>> + phys_addr_t phys_addr;
>> + unsigned int mmio_bar;
>> + int ret;
>> +
>> + mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
>> + phys_addr = pci_resource_start(pdev, mmio_bar);
>> +
>> + /*
>> + * We always have at least one primary GT on any device
>> + * and it has been already initialized early during probe
>> + * in i915_driver_probe()
>> + */
>> + ret = intel_gt_tile_setup(gt, phys_addr);
>> + if (ret)
>> + return ret;
>> +
>> + i915->gt[0] = gt;
>> +
>> + /* TODO: add more tiles */
>> + return 0;
>> +}
>> +
>> +int intel_gt_tiles_init(struct drm_i915_private *i915)
>> +{
>> + struct intel_gt *gt;
>> + unsigned int id;
>> + int ret;
>> +
>> + for_each_gt(gt, i915, id) {
>> + ret = intel_gt_probe_lmem(gt);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +void intel_gt_release_all(struct drm_i915_private *i915)
>> +{
>> + struct intel_gt *gt;
>> + unsigned int id;
>> +
>> + for_each_gt(gt, i915, id) {
>> + intel_gt_tile_cleanup(gt);
>> + i915->gt[id] = NULL;
>> + }
>> +}
>> +
>> void intel_gt_info_print(const struct intel_gt_info *info,
>> struct drm_printer *p)
>> {
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h
>> b/drivers/gpu/drm/i915/gt/intel_gt.h
>> index ce471aa5c83d7..e76168e10a21b 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
>> @@ -39,10 +39,8 @@ static inline struct intel_gt *huc_to_gt(struct
>> intel_huc *huc)
>> return container_of(huc, struct intel_gt, uc.huc);
>> }
>> -void intel_gt_init_early(struct intel_gt *gt, struct
>> drm_i915_private *i915);
>> -void __intel_gt_init_early(struct intel_gt *gt, struct
>> drm_i915_private *i915);
>> +void intel_root_gt_init_early(struct drm_i915_private *i915);
>> int intel_gt_assign_ggtt(struct intel_gt *gt);
>> -int intel_gt_probe_lmem(struct intel_gt *gt);
>> int intel_gt_init_mmio(struct intel_gt *gt);
>> int __must_check intel_gt_init_hw(struct intel_gt *gt);
>> int intel_gt_init(struct intel_gt *gt);
>> @@ -52,7 +50,7 @@ void intel_gt_driver_unregister(struct intel_gt *gt);
>> void intel_gt_driver_remove(struct intel_gt *gt);
>> void intel_gt_driver_release(struct intel_gt *gt);
>> -void intel_gt_driver_late_release(struct intel_gt *gt);
>> +void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
>> int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
>> @@ -97,6 +95,17 @@ u32 intel_gt_read_register(struct intel_gt *gt,
>> i915_reg_t reg);
>> void intel_gt_report_steering(struct drm_printer *p, struct
>> intel_gt *gt,
>> bool dump_table);
>> +
>> +int intel_gt_probe_all(struct drm_i915_private *i915);
>> +int intel_gt_tiles_init(struct drm_i915_private *i915);
>> +void intel_gt_release_all(struct drm_i915_private *i915);
>> +
>> +#define for_each_gt(gt__, i915__, id__) \
>> + for ((id__) = 0; \
>> + (id__) < I915_MAX_GT; \
>> + (id__)++) \
>> + for_each_if(((gt__) = (i915__)->gt[(id__)]))
>> +
>> void intel_gt_info_print(const struct intel_gt_info *info,
>> struct drm_printer *p);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> index e4ecc17889d34..eeead40485fbc 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> @@ -129,7 +129,14 @@ static const struct intel_wakeref_ops wf_ops = {
>> void intel_gt_pm_init_early(struct intel_gt *gt)
>> {
>> - intel_wakeref_init(>->wakeref, gt->uncore->rpm, &wf_ops);
>> + /*
>> + * We access the runtime_pm structure via gt->i915 here rather than
>> + * gt->uncore as we do elsewhere in the file because gt->uncore
>> is not
>> + * yet initialized for all tiles at this point in the driver
>> startup.
>> + * runtime_pm is per-device rather than per-tile, so this is
>> still the
>> + * correct structure.
>> + */
>> + intel_wakeref_init(>->wakeref, >->i915->runtime_pm, &wf_ops);
>> seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> index bbba885d45bd5..937b2e1a305ed 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> @@ -188,7 +188,14 @@ struct intel_gt {
>> u8 instanceid;
>> } default_steering;
>> + /*
>> + * Base of per-tile GTTMMADR where we can derive the MMIO and
>> the GGTT.
>> + */
>> + phys_addr_t phys_addr;
>> +
>> struct intel_gt_info {
>> + unsigned int id;
>> +
>> intel_engine_mask_t engine_mask;
>> u32 l3bank_mask;
>> diff --git a/drivers/gpu/drm/i915/i915_driver.c
>> b/drivers/gpu/drm/i915/i915_driver.c
>> index 92a625a174e22..64e6f76861f95 100644
>> --- a/drivers/gpu/drm/i915/i915_driver.c
>> +++ b/drivers/gpu/drm/i915/i915_driver.c
>> @@ -321,9 +321,7 @@ static int i915_driver_early_probe(struct
>> drm_i915_private *dev_priv)
>> intel_device_info_subplatform_init(dev_priv);
>> intel_step_init(dev_priv);
>> - intel_gt_init_early(to_gt(dev_priv), dev_priv);
>> intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
>> - intel_uncore_init_early(&dev_priv->uncore, to_gt(dev_priv));
>> spin_lock_init(&dev_priv->irq_lock);
>> spin_lock_init(&dev_priv->gpu_error.lock);
>> @@ -354,7 +352,7 @@ static int i915_driver_early_probe(struct
>> drm_i915_private *dev_priv)
>> intel_wopcm_init_early(&dev_priv->wopcm);
>> - __intel_gt_init_early(to_gt(dev_priv), dev_priv);
>> + intel_root_gt_init_early(dev_priv);
>> i915_gem_init_early(dev_priv);
>> @@ -375,7 +373,7 @@ static int i915_driver_early_probe(struct
>> drm_i915_private *dev_priv)
>> err_gem:
>> i915_gem_cleanup_early(dev_priv);
>> - intel_gt_driver_late_release(to_gt(dev_priv));
>> + intel_gt_driver_late_release_all(dev_priv);
>> intel_region_ttm_device_fini(dev_priv);
>> err_ttm:
>> vlv_suspend_cleanup(dev_priv);
>> @@ -394,7 +392,7 @@ static void i915_driver_late_release(struct
>> drm_i915_private *dev_priv)
>> intel_irq_fini(dev_priv);
>> intel_power_domains_cleanup(dev_priv);
>> i915_gem_cleanup_early(dev_priv);
>> - intel_gt_driver_late_release(to_gt(dev_priv));
>> + intel_gt_driver_late_release_all(dev_priv);
>> intel_region_ttm_device_fini(dev_priv);
>> vlv_suspend_cleanup(dev_priv);
>> i915_workqueues_cleanup(dev_priv);
>> @@ -425,13 +423,9 @@ static int i915_driver_mmio_probe(struct
>> drm_i915_private *dev_priv)
>> if (ret < 0)
>> return ret;
>> - ret = intel_uncore_setup_mmio(&dev_priv->uncore);
>> - if (ret < 0)
>> - goto err_bridge;
>> -
>> ret = intel_uncore_init_mmio(&dev_priv->uncore);
>> if (ret)
>> - goto err_mmio;
>> + return ret;
>> /* Try to make sure MCHBAR is enabled before poking at it */
>> intel_setup_mchbar(dev_priv);
>> @@ -449,9 +443,6 @@ static int i915_driver_mmio_probe(struct
>> drm_i915_private *dev_priv)
>> err_uncore:
>> intel_teardown_mchbar(dev_priv);
>> intel_uncore_fini_mmio(&dev_priv->uncore);
>> -err_mmio:
>> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
>> -err_bridge:
>> pci_dev_put(dev_priv->bridge_dev);
>> return ret;
>> @@ -465,7 +456,6 @@ static void i915_driver_mmio_release(struct
>> drm_i915_private *dev_priv)
>> {
>> intel_teardown_mchbar(dev_priv);
>> intel_uncore_fini_mmio(&dev_priv->uncore);
>> - intel_uncore_cleanup_mmio(&dev_priv->uncore);
>> pci_dev_put(dev_priv->bridge_dev);
>> }
>> @@ -598,7 +588,7 @@ static int i915_driver_hw_probe(struct
>> drm_i915_private *dev_priv)
>> if (ret)
>> goto err_ggtt;
>> - ret = intel_gt_probe_lmem(to_gt(dev_priv));
>> + ret = intel_gt_tiles_init(dev_priv);
>> if (ret)
>> goto err_mem_regions;
>> @@ -849,10 +839,14 @@ int i915_driver_probe(struct pci_dev *pdev,
>> const struct pci_device_id *ent)
>> intel_vgpu_detect(i915);
>> - ret = i915_driver_mmio_probe(i915);
>> + ret = intel_gt_probe_all(i915);
>> if (ret < 0)
>> goto out_runtime_pm_put;
>> + ret = i915_driver_mmio_probe(i915);
>> + if (ret < 0)
>> + goto out_tiles_cleanup;
>> +
>> ret = i915_driver_hw_probe(i915);
>> if (ret < 0)
>> goto out_cleanup_mmio;
>> @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev, const
>> struct pci_device_id *ent)
>> i915_ggtt_driver_late_release(i915);
>> out_cleanup_mmio:
>> i915_driver_mmio_release(i915);
>> +out_tiles_cleanup:
>> + intel_gt_release_all(i915);
>
> We don't seem to call intel_gt_release_all() from driver_release(), so
> we might be leaking something there. I wanted to send a patch to add
> the call at the same place in the flow as in this error path, but then
> I noticed that i915_driver_late_release(), which we call a few lines
> below, calls intel_gt_driver_late_release_all(), which seems to expect
> that the GTs are still allocated, so we probably need to flip the
> order those are called in, or move the cleanup code from
> late_release() to late_release_all() (or vice versa).
> Andi, can you have a look at this?
>
Ping! :)
Daniele
> Thanks,
> Daniele
>
>> out_runtime_pm_put:
>> enable_rpm_wakeref_asserts(&i915->runtime_pm);
>> i915_driver_late_release(i915);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 97622d3ccfc2a..8e4083d413592 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -777,6 +777,12 @@ struct drm_i915_private {
>> /* Abstract the submission mechanism (legacy ringbuffer or
>> execlists) away */
>> struct intel_gt gt0;
>> + /*
>> + * i915->gt[0] == &i915->gt0
>> + */
>> +#define I915_MAX_GT 4
>> + struct intel_gt *gt[I915_MAX_GT];
>> +
>> struct {
>> struct i915_gem_contexts {
>> spinlock_t lock; /* locks list */
>> diff --git a/drivers/gpu/drm/i915/intel_memory_region.h
>> b/drivers/gpu/drm/i915/intel_memory_region.h
>> index cc7078bcbfbfc..3d8378c1b4478 100644
>> --- a/drivers/gpu/drm/i915/intel_memory_region.h
>> +++ b/drivers/gpu/drm/i915/intel_memory_region.h
>> @@ -30,6 +30,9 @@ enum intel_memory_type {
>> enum intel_region_id {
>> INTEL_REGION_SMEM = 0,
>> INTEL_REGION_LMEM_0,
>> + INTEL_REGION_LMEM_1,
>> + INTEL_REGION_LMEM_2,
>> + INTEL_REGION_LMEM_3,
>> INTEL_REGION_STOLEN_SMEM,
>> INTEL_REGION_STOLEN_LMEM,
>> INTEL_REGION_UNKNOWN, /* Should be last */
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c
>> b/drivers/gpu/drm/i915/intel_uncore.c
>> index ef8ffc01ad19c..8b9caaaacc21f 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -2039,14 +2039,11 @@ static int
>> i915_pmic_bus_access_notifier(struct notifier_block *nb,
>> return NOTIFY_OK;
>> }
>> -int intel_uncore_setup_mmio(struct intel_uncore *uncore)
>> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t
>> phys_addr)
>> {
>> struct drm_i915_private *i915 = uncore->i915;
>> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> - int mmio_bar;
>> int mmio_size;
>> - mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
>> /*
>> * Before gen4, the registers and the GTT are behind different
>> BARs.
>> * However, from gen4 onwards, the registers and the GTT are
>> shared
>> @@ -2063,7 +2060,7 @@ int intel_uncore_setup_mmio(struct intel_uncore
>> *uncore)
>> else
>> mmio_size = 2 * 1024 * 1024;
>> - uncore->regs = pci_iomap(pdev, mmio_bar, mmio_size);
>> + uncore->regs = ioremap(phys_addr, mmio_size);
>> if (uncore->regs == NULL) {
>> drm_err(&i915->drm, "failed to map registers\n");
>> return -EIO;
>> @@ -2074,9 +2071,7 @@ int intel_uncore_setup_mmio(struct intel_uncore
>> *uncore)
>> void intel_uncore_cleanup_mmio(struct intel_uncore *uncore)
>> {
>> - struct pci_dev *pdev = to_pci_dev(uncore->i915->drm.dev);
>> -
>> - pci_iounmap(pdev, uncore->regs);
>> + iounmap(uncore->regs);
>> }
>> void intel_uncore_init_early(struct intel_uncore *uncore,
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.h
>> b/drivers/gpu/drm/i915/intel_uncore.h
>> index 9a760952d46af..52fe3d89dd2b8 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.h
>> +++ b/drivers/gpu/drm/i915/intel_uncore.h
>> @@ -29,6 +29,7 @@
>> #include <linux/notifier.h>
>> #include <linux/hrtimer.h>
>> #include <linux/io-64-nonatomic-lo-hi.h>
>> +#include <linux/types.h>
>> #include "i915_reg_defs.h"
>> @@ -221,7 +222,7 @@ void
>> intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug
>> *mmio_debug);
>> void intel_uncore_init_early(struct intel_uncore *uncore,
>> struct intel_gt *gt);
>> -int intel_uncore_setup_mmio(struct intel_uncore *uncore);
>> +int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t
>> phys_addr);
>> int intel_uncore_init_mmio(struct intel_uncore *uncore);
>> void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore,
>> struct intel_gt *gt);
>> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> index 573d9b2e1a4a3..9c31a16f83800 100644
>> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
>> @@ -73,7 +73,7 @@ static void mock_device_release(struct drm_device
>> *dev)
>> destroy_workqueue(i915->wq);
>> intel_region_ttm_device_fini(i915);
>> - intel_gt_driver_late_release(to_gt(i915));
>> + intel_gt_driver_late_release_all(i915);
>> intel_memory_regions_driver_release(i915);
>> drm_mode_config_cleanup(&i915->drm);
>> @@ -112,6 +112,11 @@ static struct dev_pm_domain pm_domain = {
>> },
>> };
>> +static void mock_gt_probe(struct drm_i915_private *i915)
>> +{
>> + i915->gt[0] = &i915->gt0;
>> +}
>> +
>> struct drm_i915_private *mock_gem_device(void)
>> {
>> #if IS_ENABLED(CONFIG_IOMMU_API) && defined(CONFIG_INTEL_IOMMU)
>> @@ -180,11 +185,11 @@ struct drm_i915_private *mock_gem_device(void)
>> spin_lock_init(&i915->gpu_error.lock);
>> i915_gem_init__mm(i915);
>> - intel_gt_init_early(to_gt(i915), i915);
>> - __intel_gt_init_early(to_gt(i915), i915);
>> + intel_root_gt_init_early(i915);
>> mock_uncore_init(&i915->uncore, i915);
>> atomic_inc(&to_gt(i915)->wakeref.count); /* disable; no hw
>> support */
>> to_gt(i915)->awake = -ENODEV;
>> + mock_gt_probe(i915);
>> ret = intel_region_ttm_device_init(i915);
>> if (ret)
>> @@ -229,7 +234,7 @@ struct drm_i915_private *mock_gem_device(void)
>> err_drv:
>> intel_region_ttm_device_fini(i915);
>> err_ttm:
>> - intel_gt_driver_late_release(to_gt(i915));
>> + intel_gt_driver_late_release_all(i915);
>> intel_memory_regions_driver_release(i915);
>> drm_mode_config_cleanup(&i915->drm);
>> mock_destroy_device(i915);
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
2022-05-19 14:53 ` [Intel-gfx] " Ceraolo Spurio, Daniele
@ 2022-05-19 22:03 ` Andi Shyti
-1 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-05-19 22:03 UTC (permalink / raw)
To: Ceraolo Spurio, Daniele
Cc: Sujaritha Sundaresan, Andi Shyti, Tvrtko Ursulin, Intel GFX,
Lucas De Marchi, DRI Devel, Chris Wilson, Matthew Auld,
Andi Shyti, Michal Wajdeczko
Hi Daniele,
> > > @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev,
> > > const struct pci_device_id *ent)
> > > i915_ggtt_driver_late_release(i915);
> > > out_cleanup_mmio:
> > > i915_driver_mmio_release(i915);
> > > +out_tiles_cleanup:
> > > + intel_gt_release_all(i915);
> >
> > We don't seem to call intel_gt_release_all() from driver_release(), so
> > we might be leaking something there. I wanted to send a patch to add the
> > call at the same place in the flow as in this error path, but then I
> > noticed that i915_driver_late_release(), which we call a few lines
> > below, calls intel_gt_driver_late_release_all(), which seems to expect
> > that the GTs are still allocated, so we probably need to flip the order
> > those are called in, or move the cleanup code from late_release() to
> > late_release_all() (or vice versa).
> > Andi, can you have a look at this?
well spotted! I will check it.
> Ping! :)
Sorry for taking so long for replying. I'm on it, now.
Thank you,
Andi
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [Intel-gfx] [PATCH v7 3/7] drm/i915: Prepare for multiple GTs
@ 2022-05-19 22:03 ` Andi Shyti
0 siblings, 0 replies; 40+ messages in thread
From: Andi Shyti @ 2022-05-19 22:03 UTC (permalink / raw)
To: Ceraolo Spurio, Daniele
Cc: Intel GFX, Lucas De Marchi, DRI Devel, Chris Wilson, Matthew Auld
Hi Daniele,
> > > @@ -909,6 +903,8 @@ int i915_driver_probe(struct pci_dev *pdev,
> > > const struct pci_device_id *ent)
> > > i915_ggtt_driver_late_release(i915);
> > > out_cleanup_mmio:
> > > i915_driver_mmio_release(i915);
> > > +out_tiles_cleanup:
> > > + intel_gt_release_all(i915);
> >
> > We don't seem to call intel_gt_release_all() from driver_release(), so
> > we might be leaking something there. I wanted to send a patch to add the
> > call at the same place in the flow as in this error path, but then I
> > noticed that i915_driver_late_release(), which we call a few lines
> > below, calls intel_gt_driver_late_release_all(), which seems to expect
> > that the GTs are still allocated, so we probably need to flip the order
> > those are called in, or move the cleanup code from late_release() to
> > late_release_all() (or vice versa).
> > Andi, can you have a look at this?
well spotted! I will check it.
> Ping! :)
Sorry for taking so long for replying. I'm on it, now.
Thank you,
Andi
^ permalink raw reply [flat|nested] 40+ messages in thread
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-- links below jump to the message on this page --
2022-03-18 23:39 [PATCH v7 0/7] Introduce multitile support Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
2022-03-18 23:39 ` [PATCH v7 1/7] drm/i915: Rename INTEL_REGION_LMEM with INTEL_REGION_LMEM_0 Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
2022-03-18 23:39 ` [PATCH v7 2/7] drm/i915/gt: add gt_is_root() helper Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
2022-03-18 23:39 ` [PATCH v7 3/7] drm/i915: Prepare for multiple GTs Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
2022-03-19 12:08 ` Michal Wajdeczko
2022-03-19 12:08 ` [Intel-gfx] " Michal Wajdeczko
2022-03-20 15:51 ` Andi Shyti
2022-03-20 15:51 ` [Intel-gfx] " Andi Shyti
2022-05-11 19:11 ` Ceraolo Spurio, Daniele
2022-05-11 19:11 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-05-19 14:53 ` Ceraolo Spurio, Daniele
2022-05-19 14:53 ` [Intel-gfx] " Ceraolo Spurio, Daniele
2022-05-19 22:03 ` Andi Shyti
2022-05-19 22:03 ` [Intel-gfx] " Andi Shyti
2022-03-18 23:39 ` [PATCH v7 4/7] drm/i915/gt: create per-tile sysfs interface Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
2022-03-18 23:39 ` [PATCH v7 5/7] drm/i915/gt: Create per-tile RC6 " Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
2022-03-18 23:39 ` [PATCH v7 6/7] drm/i915/gt: Create per-tile RPS sysfs interfaces Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
2022-05-05 13:14 ` Tvrtko Ursulin
2022-05-05 13:27 ` Andi Shyti
2022-05-05 13:27 ` Andi Shyti
2022-05-06 11:53 ` Jani Nikula
2022-05-06 15:21 ` Andi Shyti
2022-05-06 15:21 ` Andi Shyti
2022-03-18 23:39 ` [PATCH v7 7/7] drm/i915/gt: Add sysfs throttle frequency interfaces Andi Shyti
2022-03-18 23:39 ` [Intel-gfx] " Andi Shyti
2022-03-18 23:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce multitile support Patchwork
2022-03-18 23:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-03-19 0:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-19 2:06 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-03-21 10:05 ` Matthew Auld
2022-03-21 16:44 ` Vudum, Lakshminarayana
2022-03-21 16:28 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2022-03-21 16:43 ` Patchwork
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