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* [PATCH net-next v2 0/7] pcs-xpcs, stmmac: add 1000BASE-X AN for network switch
@ 2022-06-10  3:29 ` Ong Boon Leong
  0 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

Hi,

Thanks Russell King [1] and Andrew Lunn [2] for v1 review and suggestion.
Since then, I have worked on refactoring the implementation as follow:

v2 changes:
1/7 - [New] Update xpcs_do_config to accept advertising input
2/7 - [New] Fix to compilation issue introduced v1. Update xpcs_do_config
            for sja1105.
3/7 - Same as 3/4 of v1 series.
4/7 - [Fix] Fix numerous issues identified by Russell King [1].
5/7 - [New] Make fixed-link setting takes precedence over ovr_an_inband.
            This is a fix to a bug introduced earlier. Separate patch
            will be sent later.
6/7 - [New] Allow phy-mode ACPI _DSD setting for dwmac-intel to overwrite
            the phy_interface detected through PCI DevID.
7/7 - [New] Make mdio register flow to skip PHY scanning if fixed-link
            is specified.

I have tested the patch-series on a 3-port SGMII Ethernet on Elkhart Lake
customer platform and PSE GbE1 (0000:00:1d.2) is setup for fixed-link
with below ACPI _DSD modification based on [3]:-

        Device (OTN1)
        {
            <snippet-remove>

            Name (_DSD, Package () {
                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
                    Package () {
                        Package () {"phy-mode", "1000base-x"},
                    },
                ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
                    Package () {
                        Package () {"fixed-link", "LNK0"}
                    }
            })

            Name (LNK0, Package(){ // Data-only subnode of port
                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
                    Package () {
                        Package () {"speed", 1000},
                        Package () {"full-duplex", 1}
                    }
            })
        }

The modified ACPI DSDT table is inserted into OS based on [4] for
testing purpose. This method will not be required if respective BIOS has
the matching ACPI _DSD changes. In gist, we avoid the need to add board
specific DMI based configuration to Linux driver and let ACPI DSDT table
customized according to hardware/port configuration design to decide how
the driver is loaded up per port-basis.

From dmesg below (whereby non-relevant section removed), we can see that:-

[    4.112037] intel-eth-pci 0000:00:1d.1 eno1: configuring for inband/sgmii link mode
[    4.132016] intel-eth-pci 0000:00:1d.2 eno2: configuring for fixed/1000base-x link mode
[    4.162069] intel-eth-pci 0000:00:1e.4 eno3: configuring for inband/sgmii link mode

-----------------------------------------------------------------------------------------------------------
[    1.471347] intel-eth-pci 0000:00:1d.1: stmmac_config_multi_msi: multi MSI enablement successful
[    1.471518] intel-eth-pci 0000:00:1d.1: User ID: 0x51, Synopsys ID: 0x52
[    1.471525] intel-eth-pci 0000:00:1d.1:      DWMAC4/5
[    1.471531] intel-eth-pci 0000:00:1d.1: DMA HW capability register supported
[    1.471533] intel-eth-pci 0000:00:1d.1: RX Checksum Offload Engine supported
[    1.471535] intel-eth-pci 0000:00:1d.1: TX Checksum insertion supported
[    1.471536] intel-eth-pci 0000:00:1d.1: TSO supported
[    1.471537] intel-eth-pci 0000:00:1d.1: Enable RX Mitigation via HW Watchdog Timer
[    1.471542] intel-eth-pci 0000:00:1d.1: device MAC address a8:a1:59:9d:2b:64
[    1.471545] intel-eth-pci 0000:00:1d.1: Enabled L3L4 Flow TC (entries=2)
[    1.471547] intel-eth-pci 0000:00:1d.1: Enabled RFS Flow TC (entries=10)
[    1.471552] intel-eth-pci 0000:00:1d.1: Enabling HW TC (entries=256, max_off=256)
[    1.471555] intel-eth-pci 0000:00:1d.1: TSO feature enabled
[    1.471556] intel-eth-pci 0000:00:1d.1: Using 32 bits DMA width
[    1.471770] mdio_bus stmmac-2: GPIO lookup for consumer reset
[    1.471774] mdio_bus stmmac-2: using lookup tables for GPIO lookup
[    1.471777] mdio_bus stmmac-2: No GPIO consumer reset found
[    1.481872] mdio_bus stmmac-2:01: GPIO lookup for consumer reset
[    1.481879] mdio_bus stmmac-2:01: using lookup tables for GPIO lookup
[    1.481881] mdio_bus stmmac-2:01: No GPIO consumer reset found
[    1.483206] Maxlinear Ethernet GPY215B stmmac-2:01: Firmware Version: 0x8764 (release)

[    1.683631] Maxlinear Ethernet GPY215B stmmac-2:01: attached PHY driver (mii_bus:phy_addr=stmmac-2:01, irq=POLL)

[    1.749607] intel-eth-pci 0000:00:1d.2: stmmac_config_multi_msi: multi MSI enablement successful
[    1.749677] intel-eth-pci 0000:00:1d.2: User ID: 0x51, Synopsys ID: 0x52
[    1.749681] intel-eth-pci 0000:00:1d.2:      DWMAC4/5
[    1.749688] intel-eth-pci 0000:00:1d.2: DMA HW capability register supported
[    1.749690] intel-eth-pci 0000:00:1d.2: RX Checksum Offload Engine supported
[    1.749692] intel-eth-pci 0000:00:1d.2: TX Checksum insertion supported
[    1.749693] intel-eth-pci 0000:00:1d.2: TSO supported
[    1.749694] intel-eth-pci 0000:00:1d.2: Enable RX Mitigation via HW Watchdog Timer
[    1.749701] intel-eth-pci 0000:00:1d.2: device MAC address a8:a1:59:9d:2b:46
[    1.749703] intel-eth-pci 0000:00:1d.2: Enabled L3L4 Flow TC (entries=2)
[    1.749705] intel-eth-pci 0000:00:1d.2: Enabled RFS Flow TC (entries=10)
[    1.749710] intel-eth-pci 0000:00:1d.2: Enabling HW TC (entries=256, max_off=256)
[    1.749712] intel-eth-pci 0000:00:1d.2: TSO feature enabled
[    1.749714] intel-eth-pci 0000:00:1d.2: Using 32 bits DMA width

[    1.749821] mdio_bus stmmac-3: GPIO lookup for consumer reset
[    1.749823] mdio_bus stmmac-3: using lookup tables for GPIO lookup
[    1.749825] mdio_bus stmmac-3: No GPIO consumer reset found
[    1.759184] mdio_bus stmmac-3:01: GPIO lookup for consumer reset
[    1.759188] mdio_bus stmmac-3:01: using lookup tables for GPIO lookup
[    1.759190] mdio_bus stmmac-3:01: No GPIO consumer reset found
[    1.760419] Maxlinear Ethernet GPY215B stmmac-3:01: Firmware Version: 0x8764 (release)

[    2.025792] intel-eth-pci 0000:00:1e.4: stmmac_config_multi_msi: multi MSI enablement successful
[    2.025876] intel-eth-pci 0000:00:1e.4: User ID: 0x51, Synopsys ID: 0x52
[    2.025881] intel-eth-pci 0000:00:1e.4:      DWMAC4/5
[    2.025887] sdhci-pci 0000:00:1a.1: No GPIO consumer (null) found
[    2.025888] intel-eth-pci 0000:00:1e.4: DMA HW capability register supported
[    2.025891] intel-eth-pci 0000:00:1e.4: RX Checksum Offload Engine supported
[    2.025893] intel-eth-pci 0000:00:1e.4: TX Checksum insertion supported
[    2.025894] intel-eth-pci 0000:00:1e.4: TSO supported
[    2.025896] intel-eth-pci 0000:00:1e.4: Enable RX Mitigation via HW Watchdog Timer
[    2.025913] intel-eth-pci 0000:00:1e.4: device MAC address a8:a1:59:9d:2b:7a
[    2.025915] intel-eth-pci 0000:00:1e.4: Enabled L3L4 Flow TC (entries=2)
[    2.025917] intel-eth-pci 0000:00:1e.4: Enabled RFS Flow TC (entries=10)
[    2.025924] intel-eth-pci 0000:00:1e.4: Enabling HW TC (entries=256, max_off=256)
[    2.025926] intel-eth-pci 0000:00:1e.4: TSO feature enabled
[    2.025928] intel-eth-pci 0000:00:1e.4: Using 40 bits DMA width
[    2.026024] mdio_bus stmmac-1: GPIO lookup for consumer reset
[    2.026027] mdio_bus stmmac-1: using lookup tables for GPIO lookup
[    2.026029] mdio_bus stmmac-1: No GPIO consumer reset found
[    2.035547] mdio_bus stmmac-1:01: GPIO lookup for consumer reset
[    2.035551] mdio_bus stmmac-1:01: using lookup tables for GPIO lookup
[    2.035553] mdio_bus stmmac-1:01: No GPIO consumer reset found
[    2.036905] Maxlinear Ethernet GPY215B stmmac-1:01: Firmware Version: 0x8764 (release)

[    2.239477] Maxlinear Ethernet GPY215B stmmac-1:01: attached PHY driver (mii_bus:phy_addr=stmmac-1:01, irq=POLL)

[    2.305510] intel-eth-pci 0000:00:1d.2 eno2: renamed from eth1
[    2.315038] intel-eth-pci 0000:00:1d.1 eno1: renamed from eth0
[    2.320776] intel-eth-pci 0000:00:1e.4 eno3: renamed from eth2

[    4.098137] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-0
[    4.098647] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-1
[    4.099187] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-2
[    4.099695] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-3
[    4.100168] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-4
[    4.100636] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-5
[    4.101114] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-6
[    4.101586] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-7
[    4.111664] dwmac4: Master AXI performs any burst length
[    4.111750] intel-eth-pci 0000:00:1d.1 eno1: Enabling Safety Features
[    4.111795] intel-eth-pci 0000:00:1d.1 eno1: IEEE 1588-2008 Advanced Timestamp supported
[    4.111897] intel-eth-pci 0000:00:1d.1 eno1: registered PTP clock
[    4.112033] intel-eth-pci 0000:00:1d.1 eno1: FPE workqueue start
[    4.112037] intel-eth-pci 0000:00:1d.1 eno1: configuring for inband/sgmii link mode
[    4.113621] 8021q: adding VLAN 0 to HW filter on device eno1

[    4.118316] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-0
[    4.118835] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-1
[    4.119338] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-2
[    4.119815] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-3
[    4.120282] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-4
[    4.120758] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-5
[    4.121228] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-6
[    4.121706] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-7
[    4.131662] dwmac4: Master AXI performs any burst length
[    4.131744] intel-eth-pci 0000:00:1d.2 eno2: Enabling Safety Features
[    4.131790] intel-eth-pci 0000:00:1d.2 eno2: IEEE 1588-2008 Advanced Timestamp supported
[    4.131873] intel-eth-pci 0000:00:1d.2 eno2: registered PTP clock
[    4.132010] intel-eth-pci 0000:00:1d.2 eno2: FPE workqueue start
[    4.132016] intel-eth-pci 0000:00:1d.2 eno2: configuring for fixed/1000base-x link mode
[    4.133517] 8021q: adding VLAN 0 to HW filter on device eno2
[    4.133677] intel-eth-pci 0000:00:1d.2 eno2: Link is Up - 1Gbps/Full - flow control off
[    4.133687] IPv6: ADDRCONF(NETDEV_CHANGE): eno2: link becomes ready

[    4.138058] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-0
[    4.138557] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-1
[    4.139105] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-2
[    4.139581] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-3
[    4.140071] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-4
[    4.140547] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-5
[    4.141041] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-6
[    4.141519] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-7
[    4.151671] dwmac4: Master AXI performs any burst length
[    4.151751] intel-eth-pci 0000:00:1e.4 eno3: Enabling Safety Features
[    4.161830] intel-eth-pci 0000:00:1e.4 eno3: IEEE 1588-2008 Advanced Timestamp supported
[    4.161916] intel-eth-pci 0000:00:1e.4 eno3: registered PTP clock
[    4.162063] intel-eth-pci 0000:00:1e.4 eno3: FPE workqueue start
[    4.162069] intel-eth-pci 0000:00:1e.4 eno3: configuring for inband/sgmii link mode
-----------------------------------------------------------------------------------------------------------

Also, thanks to Emilio Riva from Ericsson who has been helping me in testing the patch
on his system too.

Reference:
[1] https://patchwork.kernel.org/comment/24826650/
[2] https://patchwork.kernel.org/comment/24827101/
[3] https://www.kernel.org/doc/html/latest/firmware-guide/acpi/dsd/phy.html#mac-node-example-with-a-fixed-link-subnode
[4] https://www.kernel.org/doc/html/latest/admin-guide/acpi/initrd_table_override.html

Thanks
Boon Leong

Ong Boon Leong (7):
  net: pcs: xpcs: prepare xpcs_do_config to accept advertising input
  net: dsa: sja1105: update xpcs_do_config additional input
  stmmac: intel: prepare to support 1000BASE-X phy interface setting
  net: pcs: xpcs: add CL37 1000BASE-X AN support
  net: phylink: unset ovr_an_inband if fixed-link is selected
  stmmac: intel: add phy-mode ACPI _DSD setting support
  net: stmmac: make mdio register skips PHY scanning for fixed-link

 drivers/net/dsa/sja1105/sja1105_main.c        |   2 +-
 .../net/ethernet/stmicro/stmmac/dwmac-intel.c |  19 +-
 .../net/ethernet/stmicro/stmmac/stmmac_main.c |  11 +-
 .../net/ethernet/stmicro/stmmac/stmmac_mdio.c |  14 ++
 drivers/net/pcs/pcs-xpcs.c                    | 186 +++++++++++++++++-
 drivers/net/phy/phylink.c                     |   4 +-
 include/linux/pcs/pcs-xpcs.h                  |   3 +-
 7 files changed, 226 insertions(+), 13 deletions(-)

--
2.25.1


^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 0/7] pcs-xpcs, stmmac: add 1000BASE-X AN for network switch
@ 2022-06-10  3:29 ` Ong Boon Leong
  0 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

Hi,

Thanks Russell King [1] and Andrew Lunn [2] for v1 review and suggestion.
Since then, I have worked on refactoring the implementation as follow:

v2 changes:
1/7 - [New] Update xpcs_do_config to accept advertising input
2/7 - [New] Fix to compilation issue introduced v1. Update xpcs_do_config
            for sja1105.
3/7 - Same as 3/4 of v1 series.
4/7 - [Fix] Fix numerous issues identified by Russell King [1].
5/7 - [New] Make fixed-link setting takes precedence over ovr_an_inband.
            This is a fix to a bug introduced earlier. Separate patch
            will be sent later.
6/7 - [New] Allow phy-mode ACPI _DSD setting for dwmac-intel to overwrite
            the phy_interface detected through PCI DevID.
7/7 - [New] Make mdio register flow to skip PHY scanning if fixed-link
            is specified.

I have tested the patch-series on a 3-port SGMII Ethernet on Elkhart Lake
customer platform and PSE GbE1 (0000:00:1d.2) is setup for fixed-link
with below ACPI _DSD modification based on [3]:-

        Device (OTN1)
        {
            <snippet-remove>

            Name (_DSD, Package () {
                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
                    Package () {
                        Package () {"phy-mode", "1000base-x"},
                    },
                ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
                    Package () {
                        Package () {"fixed-link", "LNK0"}
                    }
            })

            Name (LNK0, Package(){ // Data-only subnode of port
                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
                    Package () {
                        Package () {"speed", 1000},
                        Package () {"full-duplex", 1}
                    }
            })
        }

The modified ACPI DSDT table is inserted into OS based on [4] for
testing purpose. This method will not be required if respective BIOS has
the matching ACPI _DSD changes. In gist, we avoid the need to add board
specific DMI based configuration to Linux driver and let ACPI DSDT table
customized according to hardware/port configuration design to decide how
the driver is loaded up per port-basis.

From dmesg below (whereby non-relevant section removed), we can see that:-

[    4.112037] intel-eth-pci 0000:00:1d.1 eno1: configuring for inband/sgmii link mode
[    4.132016] intel-eth-pci 0000:00:1d.2 eno2: configuring for fixed/1000base-x link mode
[    4.162069] intel-eth-pci 0000:00:1e.4 eno3: configuring for inband/sgmii link mode

-----------------------------------------------------------------------------------------------------------
[    1.471347] intel-eth-pci 0000:00:1d.1: stmmac_config_multi_msi: multi MSI enablement successful
[    1.471518] intel-eth-pci 0000:00:1d.1: User ID: 0x51, Synopsys ID: 0x52
[    1.471525] intel-eth-pci 0000:00:1d.1:      DWMAC4/5
[    1.471531] intel-eth-pci 0000:00:1d.1: DMA HW capability register supported
[    1.471533] intel-eth-pci 0000:00:1d.1: RX Checksum Offload Engine supported
[    1.471535] intel-eth-pci 0000:00:1d.1: TX Checksum insertion supported
[    1.471536] intel-eth-pci 0000:00:1d.1: TSO supported
[    1.471537] intel-eth-pci 0000:00:1d.1: Enable RX Mitigation via HW Watchdog Timer
[    1.471542] intel-eth-pci 0000:00:1d.1: device MAC address a8:a1:59:9d:2b:64
[    1.471545] intel-eth-pci 0000:00:1d.1: Enabled L3L4 Flow TC (entries=2)
[    1.471547] intel-eth-pci 0000:00:1d.1: Enabled RFS Flow TC (entries=10)
[    1.471552] intel-eth-pci 0000:00:1d.1: Enabling HW TC (entries=256, max_off=256)
[    1.471555] intel-eth-pci 0000:00:1d.1: TSO feature enabled
[    1.471556] intel-eth-pci 0000:00:1d.1: Using 32 bits DMA width
[    1.471770] mdio_bus stmmac-2: GPIO lookup for consumer reset
[    1.471774] mdio_bus stmmac-2: using lookup tables for GPIO lookup
[    1.471777] mdio_bus stmmac-2: No GPIO consumer reset found
[    1.481872] mdio_bus stmmac-2:01: GPIO lookup for consumer reset
[    1.481879] mdio_bus stmmac-2:01: using lookup tables for GPIO lookup
[    1.481881] mdio_bus stmmac-2:01: No GPIO consumer reset found
[    1.483206] Maxlinear Ethernet GPY215B stmmac-2:01: Firmware Version: 0x8764 (release)

[    1.683631] Maxlinear Ethernet GPY215B stmmac-2:01: attached PHY driver (mii_bus:phy_addr=stmmac-2:01, irq=POLL)

[    1.749607] intel-eth-pci 0000:00:1d.2: stmmac_config_multi_msi: multi MSI enablement successful
[    1.749677] intel-eth-pci 0000:00:1d.2: User ID: 0x51, Synopsys ID: 0x52
[    1.749681] intel-eth-pci 0000:00:1d.2:      DWMAC4/5
[    1.749688] intel-eth-pci 0000:00:1d.2: DMA HW capability register supported
[    1.749690] intel-eth-pci 0000:00:1d.2: RX Checksum Offload Engine supported
[    1.749692] intel-eth-pci 0000:00:1d.2: TX Checksum insertion supported
[    1.749693] intel-eth-pci 0000:00:1d.2: TSO supported
[    1.749694] intel-eth-pci 0000:00:1d.2: Enable RX Mitigation via HW Watchdog Timer
[    1.749701] intel-eth-pci 0000:00:1d.2: device MAC address a8:a1:59:9d:2b:46
[    1.749703] intel-eth-pci 0000:00:1d.2: Enabled L3L4 Flow TC (entries=2)
[    1.749705] intel-eth-pci 0000:00:1d.2: Enabled RFS Flow TC (entries=10)
[    1.749710] intel-eth-pci 0000:00:1d.2: Enabling HW TC (entries=256, max_off=256)
[    1.749712] intel-eth-pci 0000:00:1d.2: TSO feature enabled
[    1.749714] intel-eth-pci 0000:00:1d.2: Using 32 bits DMA width

[    1.749821] mdio_bus stmmac-3: GPIO lookup for consumer reset
[    1.749823] mdio_bus stmmac-3: using lookup tables for GPIO lookup
[    1.749825] mdio_bus stmmac-3: No GPIO consumer reset found
[    1.759184] mdio_bus stmmac-3:01: GPIO lookup for consumer reset
[    1.759188] mdio_bus stmmac-3:01: using lookup tables for GPIO lookup
[    1.759190] mdio_bus stmmac-3:01: No GPIO consumer reset found
[    1.760419] Maxlinear Ethernet GPY215B stmmac-3:01: Firmware Version: 0x8764 (release)

[    2.025792] intel-eth-pci 0000:00:1e.4: stmmac_config_multi_msi: multi MSI enablement successful
[    2.025876] intel-eth-pci 0000:00:1e.4: User ID: 0x51, Synopsys ID: 0x52
[    2.025881] intel-eth-pci 0000:00:1e.4:      DWMAC4/5
[    2.025887] sdhci-pci 0000:00:1a.1: No GPIO consumer (null) found
[    2.025888] intel-eth-pci 0000:00:1e.4: DMA HW capability register supported
[    2.025891] intel-eth-pci 0000:00:1e.4: RX Checksum Offload Engine supported
[    2.025893] intel-eth-pci 0000:00:1e.4: TX Checksum insertion supported
[    2.025894] intel-eth-pci 0000:00:1e.4: TSO supported
[    2.025896] intel-eth-pci 0000:00:1e.4: Enable RX Mitigation via HW Watchdog Timer
[    2.025913] intel-eth-pci 0000:00:1e.4: device MAC address a8:a1:59:9d:2b:7a
[    2.025915] intel-eth-pci 0000:00:1e.4: Enabled L3L4 Flow TC (entries=2)
[    2.025917] intel-eth-pci 0000:00:1e.4: Enabled RFS Flow TC (entries=10)
[    2.025924] intel-eth-pci 0000:00:1e.4: Enabling HW TC (entries=256, max_off=256)
[    2.025926] intel-eth-pci 0000:00:1e.4: TSO feature enabled
[    2.025928] intel-eth-pci 0000:00:1e.4: Using 40 bits DMA width
[    2.026024] mdio_bus stmmac-1: GPIO lookup for consumer reset
[    2.026027] mdio_bus stmmac-1: using lookup tables for GPIO lookup
[    2.026029] mdio_bus stmmac-1: No GPIO consumer reset found
[    2.035547] mdio_bus stmmac-1:01: GPIO lookup for consumer reset
[    2.035551] mdio_bus stmmac-1:01: using lookup tables for GPIO lookup
[    2.035553] mdio_bus stmmac-1:01: No GPIO consumer reset found
[    2.036905] Maxlinear Ethernet GPY215B stmmac-1:01: Firmware Version: 0x8764 (release)

[    2.239477] Maxlinear Ethernet GPY215B stmmac-1:01: attached PHY driver (mii_bus:phy_addr=stmmac-1:01, irq=POLL)

[    2.305510] intel-eth-pci 0000:00:1d.2 eno2: renamed from eth1
[    2.315038] intel-eth-pci 0000:00:1d.1 eno1: renamed from eth0
[    2.320776] intel-eth-pci 0000:00:1e.4 eno3: renamed from eth2

[    4.098137] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-0
[    4.098647] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-1
[    4.099187] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-2
[    4.099695] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-3
[    4.100168] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-4
[    4.100636] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-5
[    4.101114] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-6
[    4.101586] intel-eth-pci 0000:00:1d.1 eno1: Register MEM_TYPE_PAGE_POOL RxQ-7
[    4.111664] dwmac4: Master AXI performs any burst length
[    4.111750] intel-eth-pci 0000:00:1d.1 eno1: Enabling Safety Features
[    4.111795] intel-eth-pci 0000:00:1d.1 eno1: IEEE 1588-2008 Advanced Timestamp supported
[    4.111897] intel-eth-pci 0000:00:1d.1 eno1: registered PTP clock
[    4.112033] intel-eth-pci 0000:00:1d.1 eno1: FPE workqueue start
[    4.112037] intel-eth-pci 0000:00:1d.1 eno1: configuring for inband/sgmii link mode
[    4.113621] 8021q: adding VLAN 0 to HW filter on device eno1

[    4.118316] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-0
[    4.118835] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-1
[    4.119338] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-2
[    4.119815] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-3
[    4.120282] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-4
[    4.120758] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-5
[    4.121228] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-6
[    4.121706] intel-eth-pci 0000:00:1d.2 eno2: Register MEM_TYPE_PAGE_POOL RxQ-7
[    4.131662] dwmac4: Master AXI performs any burst length
[    4.131744] intel-eth-pci 0000:00:1d.2 eno2: Enabling Safety Features
[    4.131790] intel-eth-pci 0000:00:1d.2 eno2: IEEE 1588-2008 Advanced Timestamp supported
[    4.131873] intel-eth-pci 0000:00:1d.2 eno2: registered PTP clock
[    4.132010] intel-eth-pci 0000:00:1d.2 eno2: FPE workqueue start
[    4.132016] intel-eth-pci 0000:00:1d.2 eno2: configuring for fixed/1000base-x link mode
[    4.133517] 8021q: adding VLAN 0 to HW filter on device eno2
[    4.133677] intel-eth-pci 0000:00:1d.2 eno2: Link is Up - 1Gbps/Full - flow control off
[    4.133687] IPv6: ADDRCONF(NETDEV_CHANGE): eno2: link becomes ready

[    4.138058] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-0
[    4.138557] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-1
[    4.139105] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-2
[    4.139581] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-3
[    4.140071] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-4
[    4.140547] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-5
[    4.141041] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-6
[    4.141519] intel-eth-pci 0000:00:1e.4 eno3: Register MEM_TYPE_PAGE_POOL RxQ-7
[    4.151671] dwmac4: Master AXI performs any burst length
[    4.151751] intel-eth-pci 0000:00:1e.4 eno3: Enabling Safety Features
[    4.161830] intel-eth-pci 0000:00:1e.4 eno3: IEEE 1588-2008 Advanced Timestamp supported
[    4.161916] intel-eth-pci 0000:00:1e.4 eno3: registered PTP clock
[    4.162063] intel-eth-pci 0000:00:1e.4 eno3: FPE workqueue start
[    4.162069] intel-eth-pci 0000:00:1e.4 eno3: configuring for inband/sgmii link mode
-----------------------------------------------------------------------------------------------------------

Also, thanks to Emilio Riva from Ericsson who has been helping me in testing the patch
on his system too.

Reference:
[1] https://patchwork.kernel.org/comment/24826650/
[2] https://patchwork.kernel.org/comment/24827101/
[3] https://www.kernel.org/doc/html/latest/firmware-guide/acpi/dsd/phy.html#mac-node-example-with-a-fixed-link-subnode
[4] https://www.kernel.org/doc/html/latest/admin-guide/acpi/initrd_table_override.html

Thanks
Boon Leong

Ong Boon Leong (7):
  net: pcs: xpcs: prepare xpcs_do_config to accept advertising input
  net: dsa: sja1105: update xpcs_do_config additional input
  stmmac: intel: prepare to support 1000BASE-X phy interface setting
  net: pcs: xpcs: add CL37 1000BASE-X AN support
  net: phylink: unset ovr_an_inband if fixed-link is selected
  stmmac: intel: add phy-mode ACPI _DSD setting support
  net: stmmac: make mdio register skips PHY scanning for fixed-link

 drivers/net/dsa/sja1105/sja1105_main.c        |   2 +-
 .../net/ethernet/stmicro/stmmac/dwmac-intel.c |  19 +-
 .../net/ethernet/stmicro/stmmac/stmmac_main.c |  11 +-
 .../net/ethernet/stmicro/stmmac/stmmac_mdio.c |  14 ++
 drivers/net/pcs/pcs-xpcs.c                    | 186 +++++++++++++++++-
 drivers/net/phy/phylink.c                     |   4 +-
 include/linux/pcs/pcs-xpcs.h                  |   3 +-
 7 files changed, 226 insertions(+), 13 deletions(-)

--
2.25.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 1/6] net: dsa: sja1105: update xpcs_do_config additional input
  2022-06-10  3:29 ` Ong Boon Leong
@ 2022-06-10  3:29   ` Ong Boon Leong
  -1 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

xpcs_do_config() is used for xpcs configuration without depending on
advertising input, so set to NULL.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/dsa/sja1105/sja1105_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/dsa/sja1105/sja1105_main.c b/drivers/net/dsa/sja1105/sja1105_main.c
index 72b6fc1932b..b253e27bcfb 100644
--- a/drivers/net/dsa/sja1105/sja1105_main.c
+++ b/drivers/net/dsa/sja1105/sja1105_main.c
@@ -2330,7 +2330,7 @@ int sja1105_static_config_reload(struct sja1105_private *priv,
 		else
 			mode = MLO_AN_PHY;
 
-		rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode);
+		rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode, NULL);
 		if (rc < 0)
 			goto out;
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 1/6] net: dsa: sja1105: update xpcs_do_config additional input
@ 2022-06-10  3:29   ` Ong Boon Leong
  0 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

xpcs_do_config() is used for xpcs configuration without depending on
advertising input, so set to NULL.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/dsa/sja1105/sja1105_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/dsa/sja1105/sja1105_main.c b/drivers/net/dsa/sja1105/sja1105_main.c
index 72b6fc1932b..b253e27bcfb 100644
--- a/drivers/net/dsa/sja1105/sja1105_main.c
+++ b/drivers/net/dsa/sja1105/sja1105_main.c
@@ -2330,7 +2330,7 @@ int sja1105_static_config_reload(struct sja1105_private *priv,
 		else
 			mode = MLO_AN_PHY;
 
-		rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode);
+		rc = xpcs_do_config(xpcs, priv->phy_mode[i], mode, NULL);
 		if (rc < 0)
 			goto out;
 
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 2/6] stmmac: intel: prepare to support 1000BASE-X phy interface setting
  2022-06-10  3:29 ` Ong Boon Leong
@ 2022-06-10  3:29   ` Ong Boon Leong
  -1 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

Currently, intel_speed_mode_2500() redundantly fix-up phy_interface to
PHY_INTERFACE_MODE_SGMII if the underlying controller is in 1000Mbps
SGMII mode. The value of phy_interface has been initialized earlier.

This patch removes such redundancy to prepare for setting 1000BASE-X
mode for certain hardware platform configuration.

Also update the intel_mgbe_common_data() to include 1000BASE-X setup.

Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index 38fe77d1035..675dfb89b76 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -251,7 +251,6 @@ static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
 		priv->plat->mdio_bus_data->xpcs_an_inband = false;
 	} else {
 		priv->plat->max_speed = 1000;
-		priv->plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
 		priv->plat->mdio_bus_data->xpcs_an_inband = true;
 	}
 }
@@ -562,7 +561,8 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
 	plat->vlan_fail_q = plat->rx_queues_to_use - 1;
 
 	/* Intel mgbe SGMII interface uses pcs-xcps */
-	if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+	if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+	    plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
 		plat->mdio_bus_data->has_xpcs = true;
 		plat->mdio_bus_data->xpcs_an_inband = true;
 	}
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 2/6] stmmac: intel: prepare to support 1000BASE-X phy interface setting
@ 2022-06-10  3:29   ` Ong Boon Leong
  0 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

Currently, intel_speed_mode_2500() redundantly fix-up phy_interface to
PHY_INTERFACE_MODE_SGMII if the underlying controller is in 1000Mbps
SGMII mode. The value of phy_interface has been initialized earlier.

This patch removes such redundancy to prepare for setting 1000BASE-X
mode for certain hardware platform configuration.

Also update the intel_mgbe_common_data() to include 1000BASE-X setup.

Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index 38fe77d1035..675dfb89b76 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -251,7 +251,6 @@ static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
 		priv->plat->mdio_bus_data->xpcs_an_inband = false;
 	} else {
 		priv->plat->max_speed = 1000;
-		priv->plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
 		priv->plat->mdio_bus_data->xpcs_an_inband = true;
 	}
 }
@@ -562,7 +561,8 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
 	plat->vlan_fail_q = plat->rx_queues_to_use - 1;
 
 	/* Intel mgbe SGMII interface uses pcs-xcps */
-	if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+	if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+	    plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
 		plat->mdio_bus_data->has_xpcs = true;
 		plat->mdio_bus_data->xpcs_an_inband = true;
 	}
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 3/6] net: pcs: xpcs: add CL37 1000BASE-X AN support
  2022-06-10  3:29 ` Ong Boon Leong
@ 2022-06-10  3:29   ` Ong Boon Leong
  -1 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

For CL37 1000BASE-X AN, DW xPCS does not support C22 method but offers
C45 vendor-specific MII MMD for programming.

We also add the ability to disable Autoneg (through ethtool for certain
network switch that supports 1000BASE-X (1000Mbps and Full-Duplex) but
not Autoneg capability.

v2: Fixes to issues spotted by Russell King in v1. Thanks!
    https://patchwork.kernel.org/comment/24826650/
    Use phylink_mii_c22_pcs_encode_advertisement() and implement
    C45 MII ADV handling since IP only support C45 access.

Tested-by: Emilio Riva <emilio.riva@ericsson.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/pcs/pcs-xpcs.c   | 180 +++++++++++++++++++++++++++++++++++
 include/linux/pcs/pcs-xpcs.h |   1 +
 2 files changed, 181 insertions(+)

diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c
index 48d81c40aab..5f75ad503ef 100644
--- a/drivers/net/pcs/pcs-xpcs.c
+++ b/drivers/net/pcs/pcs-xpcs.c
@@ -77,6 +77,14 @@ static const int xpcs_sgmii_features[] = {
 	__ETHTOOL_LINK_MODE_MASK_NBITS,
 };
 
+static const int xpcs_1000basex_features[] = {
+	ETHTOOL_LINK_MODE_Pause_BIT,
+	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+	ETHTOOL_LINK_MODE_Autoneg_BIT,
+	ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+	__ETHTOOL_LINK_MODE_MASK_NBITS,
+};
+
 static const int xpcs_2500basex_features[] = {
 	ETHTOOL_LINK_MODE_Pause_BIT,
 	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
@@ -102,6 +110,10 @@ static const phy_interface_t xpcs_sgmii_interfaces[] = {
 	PHY_INTERFACE_MODE_SGMII,
 };
 
+static const phy_interface_t xpcs_1000basex_interfaces[] = {
+	PHY_INTERFACE_MODE_1000BASEX,
+};
+
 static const phy_interface_t xpcs_2500basex_interfaces[] = {
 	PHY_INTERFACE_MODE_2500BASEX,
 	PHY_INTERFACE_MODE_MAX,
@@ -112,6 +124,7 @@ enum {
 	DW_XPCS_10GKR,
 	DW_XPCS_XLGMII,
 	DW_XPCS_SGMII,
+	DW_XPCS_1000BASEX,
 	DW_XPCS_2500BASEX,
 	DW_XPCS_INTERFACE_MAX,
 };
@@ -189,6 +202,16 @@ int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
 	return mdiobus_c45_write(bus, addr, dev, reg, val);
 }
 
+int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg,
+			u16 mask, u16 set)
+{
+	u32 reg_addr = mdiobus_c45_addr(dev, reg);
+	struct mii_bus *bus = xpcs->mdiodev->bus;
+	int addr = xpcs->mdiodev->addr;
+
+	return mdiobus_modify_changed(bus, addr, reg_addr, mask, set);
+}
+
 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
 {
 	return xpcs_read(xpcs, dev, DW_VENDOR | reg);
@@ -237,6 +260,7 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs,
 		break;
 	case DW_AN_C37_SGMII:
 	case DW_2500BASEX:
+	case DW_AN_C37_1000BASEX:
 		dev = MDIO_MMD_VEND2;
 		break;
 	default:
@@ -772,6 +796,68 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode)
 	return ret;
 }
 
+static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, unsigned int mode,
+					  const unsigned long *advertising)
+{
+	phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX;
+	int ret, mdio_ctrl, adv;
+	bool changed = 0;
+
+	/* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must
+	 * be disabled first:-
+	 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b
+	 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37)
+	 */
+	mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
+	if (mdio_ctrl < 0)
+		return mdio_ctrl;
+
+	if (mdio_ctrl & AN_CL37_EN) {
+		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
+				 mdio_ctrl & ~AN_CL37_EN);
+		if (ret < 0)
+			return ret;
+	}
+
+	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
+	if (ret < 0)
+		return ret;
+
+	ret &= ~DW_VR_MII_PCS_MODE_MASK;
+	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
+	if (ret < 0)
+		return ret;
+
+	/* Check for advertising changes and update the C45 MII ADV
+	 * register accordingly.
+	 */
+	adv = phylink_mii_c22_pcs_encode_advertisement(interface,
+						       advertising);
+	if (adv >= 0) {
+		ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2,
+					  MII_ADVERTISE, 0xffff, adv);
+		if (ret < 0)
+			return ret;
+
+		changed = ret;
+	}
+
+	/* Clear CL37 AN complete status */
+	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
+	if (ret < 0)
+		return ret;
+
+	if (phylink_autoneg_inband(mode) &&
+	    linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)) {
+		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
+				 mdio_ctrl | AN_CL37_EN);
+		if (ret < 0)
+			return ret;
+	}
+
+	return changed;
+}
+
 static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
 {
 	int ret;
@@ -817,6 +903,12 @@ int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
 		if (ret)
 			return ret;
 		break;
+	case DW_AN_C37_1000BASEX:
+		ret = xpcs_config_aneg_c37_1000basex(xpcs, mode,
+						     advertising);
+		if (ret)
+			return ret;
+		break;
 	case DW_2500BASEX:
 		ret = xpcs_config_2500basex(xpcs);
 		if (ret)
@@ -921,6 +1013,40 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
 	return 0;
 }
 
+static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
+					struct phylink_link_state *state)
+{
+	int lpa, adv;
+	int ret;
+
+	if (state->an_enabled) {
+		/* Reset link state */
+		state->link = false;
+
+		lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
+		if (lpa < 0 || lpa & LPA_RFAULT)
+			return lpa;
+
+		adv = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
+		if (adv < 0)
+			return adv;
+
+		if (lpa & ADVERTISE_1000XFULL &&
+		    adv & ADVERTISE_1000XFULL) {
+			state->link = true;
+			state->speed = SPEED_1000;
+			state->duplex = DUPLEX_FULL;
+		}
+
+		/* Clear CL37 AN complete status */
+		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
 static void xpcs_get_state(struct phylink_pcs *pcs,
 			   struct phylink_link_state *state)
 {
@@ -948,6 +1074,13 @@ static void xpcs_get_state(struct phylink_pcs *pcs,
 			       ERR_PTR(ret));
 		}
 		break;
+	case DW_AN_C37_1000BASEX:
+		ret = xpcs_get_state_c37_1000basex(xpcs, state);
+		if (ret) {
+			pr_err("xpcs_get_state_c37_1000basex returned %pe\n",
+			       ERR_PTR(ret));
+		}
+		break;
 	default:
 		return;
 	}
@@ -983,6 +1116,32 @@ static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int mode,
 		pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
 }
 
+static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, int speed,
+				   int duplex)
+{
+	int val, ret;
+
+	switch (speed) {
+	case SPEED_1000:
+		val = BMCR_SPEED1000;
+		break;
+	case SPEED_100:
+	case SPEED_10:
+	default:
+		pr_err("%s: speed = %d\n", __func__, speed);
+		return;
+	}
+
+	if (duplex == DUPLEX_FULL)
+		val |= BMCR_FULLDPLX;
+	else
+		pr_err("%s: half duplex not supported\n", __func__);
+
+	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
+	if (ret)
+		pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
+}
+
 void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
 		  phy_interface_t interface, int speed, int duplex)
 {
@@ -992,9 +1151,23 @@ void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
 		return xpcs_config_usxgmii(xpcs, speed);
 	if (interface == PHY_INTERFACE_MODE_SGMII)
 		return xpcs_link_up_sgmii(xpcs, mode, speed, duplex);
+	if (interface == PHY_INTERFACE_MODE_1000BASEX)
+		return xpcs_link_up_1000basex(xpcs, speed, duplex);
 }
 EXPORT_SYMBOL_GPL(xpcs_link_up);
 
+static void xpcs_an_restart(struct phylink_pcs *pcs)
+{
+	struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
+	int ret;
+
+	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
+	if (ret >= 0) {
+		ret |= BMCR_ANRESTART;
+		xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
+	}
+}
+
 static u32 xpcs_get_id(struct dw_xpcs *xpcs)
 {
 	int ret;
@@ -1060,6 +1233,12 @@ static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
 		.num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
 		.an_mode = DW_AN_C37_SGMII,
 	},
+	[DW_XPCS_1000BASEX] = {
+		.supported = xpcs_1000basex_features,
+		.interface = xpcs_1000basex_interfaces,
+		.num_interfaces = ARRAY_SIZE(xpcs_1000basex_interfaces),
+		.an_mode = DW_AN_C37_1000BASEX,
+	},
 	[DW_XPCS_2500BASEX] = {
 		.supported = xpcs_2500basex_features,
 		.interface = xpcs_2500basex_interfaces,
@@ -1115,6 +1294,7 @@ static const struct phylink_pcs_ops xpcs_phylink_ops = {
 	.pcs_validate = xpcs_validate,
 	.pcs_config = xpcs_config,
 	.pcs_get_state = xpcs_get_state,
+	.pcs_an_restart = xpcs_an_restart,
 	.pcs_link_up = xpcs_link_up,
 };
 
diff --git a/include/linux/pcs/pcs-xpcs.h b/include/linux/pcs/pcs-xpcs.h
index 37eb97cc228..d2da1e0b4a9 100644
--- a/include/linux/pcs/pcs-xpcs.h
+++ b/include/linux/pcs/pcs-xpcs.h
@@ -17,6 +17,7 @@
 #define DW_AN_C73			1
 #define DW_AN_C37_SGMII			2
 #define DW_2500BASEX			3
+#define DW_AN_C37_1000BASEX		4
 
 struct xpcs_id;
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 3/6] net: pcs: xpcs: add CL37 1000BASE-X AN support
@ 2022-06-10  3:29   ` Ong Boon Leong
  0 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

For CL37 1000BASE-X AN, DW xPCS does not support C22 method but offers
C45 vendor-specific MII MMD for programming.

We also add the ability to disable Autoneg (through ethtool for certain
network switch that supports 1000BASE-X (1000Mbps and Full-Duplex) but
not Autoneg capability.

v2: Fixes to issues spotted by Russell King in v1. Thanks!
    https://patchwork.kernel.org/comment/24826650/
    Use phylink_mii_c22_pcs_encode_advertisement() and implement
    C45 MII ADV handling since IP only support C45 access.

Tested-by: Emilio Riva <emilio.riva@ericsson.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/pcs/pcs-xpcs.c   | 180 +++++++++++++++++++++++++++++++++++
 include/linux/pcs/pcs-xpcs.h |   1 +
 2 files changed, 181 insertions(+)

diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c
index 48d81c40aab..5f75ad503ef 100644
--- a/drivers/net/pcs/pcs-xpcs.c
+++ b/drivers/net/pcs/pcs-xpcs.c
@@ -77,6 +77,14 @@ static const int xpcs_sgmii_features[] = {
 	__ETHTOOL_LINK_MODE_MASK_NBITS,
 };
 
+static const int xpcs_1000basex_features[] = {
+	ETHTOOL_LINK_MODE_Pause_BIT,
+	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+	ETHTOOL_LINK_MODE_Autoneg_BIT,
+	ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+	__ETHTOOL_LINK_MODE_MASK_NBITS,
+};
+
 static const int xpcs_2500basex_features[] = {
 	ETHTOOL_LINK_MODE_Pause_BIT,
 	ETHTOOL_LINK_MODE_Asym_Pause_BIT,
@@ -102,6 +110,10 @@ static const phy_interface_t xpcs_sgmii_interfaces[] = {
 	PHY_INTERFACE_MODE_SGMII,
 };
 
+static const phy_interface_t xpcs_1000basex_interfaces[] = {
+	PHY_INTERFACE_MODE_1000BASEX,
+};
+
 static const phy_interface_t xpcs_2500basex_interfaces[] = {
 	PHY_INTERFACE_MODE_2500BASEX,
 	PHY_INTERFACE_MODE_MAX,
@@ -112,6 +124,7 @@ enum {
 	DW_XPCS_10GKR,
 	DW_XPCS_XLGMII,
 	DW_XPCS_SGMII,
+	DW_XPCS_1000BASEX,
 	DW_XPCS_2500BASEX,
 	DW_XPCS_INTERFACE_MAX,
 };
@@ -189,6 +202,16 @@ int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val)
 	return mdiobus_c45_write(bus, addr, dev, reg, val);
 }
 
+int xpcs_modify_changed(struct dw_xpcs *xpcs, int dev, u32 reg,
+			u16 mask, u16 set)
+{
+	u32 reg_addr = mdiobus_c45_addr(dev, reg);
+	struct mii_bus *bus = xpcs->mdiodev->bus;
+	int addr = xpcs->mdiodev->addr;
+
+	return mdiobus_modify_changed(bus, addr, reg_addr, mask, set);
+}
+
 static int xpcs_read_vendor(struct dw_xpcs *xpcs, int dev, u32 reg)
 {
 	return xpcs_read(xpcs, dev, DW_VENDOR | reg);
@@ -237,6 +260,7 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs,
 		break;
 	case DW_AN_C37_SGMII:
 	case DW_2500BASEX:
+	case DW_AN_C37_1000BASEX:
 		dev = MDIO_MMD_VEND2;
 		break;
 	default:
@@ -772,6 +796,68 @@ static int xpcs_config_aneg_c37_sgmii(struct dw_xpcs *xpcs, unsigned int mode)
 	return ret;
 }
 
+static int xpcs_config_aneg_c37_1000basex(struct dw_xpcs *xpcs, unsigned int mode,
+					  const unsigned long *advertising)
+{
+	phy_interface_t interface = PHY_INTERFACE_MODE_1000BASEX;
+	int ret, mdio_ctrl, adv;
+	bool changed = 0;
+
+	/* According to Chap 7.12, to set 1000BASE-X C37 AN, AN must
+	 * be disabled first:-
+	 * 1) VR_MII_MMD_CTRL Bit(12)[AN_ENABLE] = 0b
+	 * 2) VR_MII_AN_CTRL Bit(2:1)[PCS_MODE] = 00b (1000BASE-X C37)
+	 */
+	mdio_ctrl = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
+	if (mdio_ctrl < 0)
+		return mdio_ctrl;
+
+	if (mdio_ctrl & AN_CL37_EN) {
+		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
+				 mdio_ctrl & ~AN_CL37_EN);
+		if (ret < 0)
+			return ret;
+	}
+
+	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL);
+	if (ret < 0)
+		return ret;
+
+	ret &= ~DW_VR_MII_PCS_MODE_MASK;
+	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_CTRL, ret);
+	if (ret < 0)
+		return ret;
+
+	/* Check for advertising changes and update the C45 MII ADV
+	 * register accordingly.
+	 */
+	adv = phylink_mii_c22_pcs_encode_advertisement(interface,
+						       advertising);
+	if (adv >= 0) {
+		ret = xpcs_modify_changed(xpcs, MDIO_MMD_VEND2,
+					  MII_ADVERTISE, 0xffff, adv);
+		if (ret < 0)
+			return ret;
+
+		changed = ret;
+	}
+
+	/* Clear CL37 AN complete status */
+	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
+	if (ret < 0)
+		return ret;
+
+	if (phylink_autoneg_inband(mode) &&
+	    linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)) {
+		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL,
+				 mdio_ctrl | AN_CL37_EN);
+		if (ret < 0)
+			return ret;
+	}
+
+	return changed;
+}
+
 static int xpcs_config_2500basex(struct dw_xpcs *xpcs)
 {
 	int ret;
@@ -817,6 +903,12 @@ int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
 		if (ret)
 			return ret;
 		break;
+	case DW_AN_C37_1000BASEX:
+		ret = xpcs_config_aneg_c37_1000basex(xpcs, mode,
+						     advertising);
+		if (ret)
+			return ret;
+		break;
 	case DW_2500BASEX:
 		ret = xpcs_config_2500basex(xpcs);
 		if (ret)
@@ -921,6 +1013,40 @@ static int xpcs_get_state_c37_sgmii(struct dw_xpcs *xpcs,
 	return 0;
 }
 
+static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
+					struct phylink_link_state *state)
+{
+	int lpa, adv;
+	int ret;
+
+	if (state->an_enabled) {
+		/* Reset link state */
+		state->link = false;
+
+		lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
+		if (lpa < 0 || lpa & LPA_RFAULT)
+			return lpa;
+
+		adv = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
+		if (adv < 0)
+			return adv;
+
+		if (lpa & ADVERTISE_1000XFULL &&
+		    adv & ADVERTISE_1000XFULL) {
+			state->link = true;
+			state->speed = SPEED_1000;
+			state->duplex = DUPLEX_FULL;
+		}
+
+		/* Clear CL37 AN complete status */
+		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
 static void xpcs_get_state(struct phylink_pcs *pcs,
 			   struct phylink_link_state *state)
 {
@@ -948,6 +1074,13 @@ static void xpcs_get_state(struct phylink_pcs *pcs,
 			       ERR_PTR(ret));
 		}
 		break;
+	case DW_AN_C37_1000BASEX:
+		ret = xpcs_get_state_c37_1000basex(xpcs, state);
+		if (ret) {
+			pr_err("xpcs_get_state_c37_1000basex returned %pe\n",
+			       ERR_PTR(ret));
+		}
+		break;
 	default:
 		return;
 	}
@@ -983,6 +1116,32 @@ static void xpcs_link_up_sgmii(struct dw_xpcs *xpcs, unsigned int mode,
 		pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
 }
 
+static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, int speed,
+				   int duplex)
+{
+	int val, ret;
+
+	switch (speed) {
+	case SPEED_1000:
+		val = BMCR_SPEED1000;
+		break;
+	case SPEED_100:
+	case SPEED_10:
+	default:
+		pr_err("%s: speed = %d\n", __func__, speed);
+		return;
+	}
+
+	if (duplex == DUPLEX_FULL)
+		val |= BMCR_FULLDPLX;
+	else
+		pr_err("%s: half duplex not supported\n", __func__);
+
+	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
+	if (ret)
+		pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));
+}
+
 void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
 		  phy_interface_t interface, int speed, int duplex)
 {
@@ -992,9 +1151,23 @@ void xpcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
 		return xpcs_config_usxgmii(xpcs, speed);
 	if (interface == PHY_INTERFACE_MODE_SGMII)
 		return xpcs_link_up_sgmii(xpcs, mode, speed, duplex);
+	if (interface == PHY_INTERFACE_MODE_1000BASEX)
+		return xpcs_link_up_1000basex(xpcs, speed, duplex);
 }
 EXPORT_SYMBOL_GPL(xpcs_link_up);
 
+static void xpcs_an_restart(struct phylink_pcs *pcs)
+{
+	struct dw_xpcs *xpcs = phylink_pcs_to_xpcs(pcs);
+	int ret;
+
+	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1);
+	if (ret >= 0) {
+		ret |= BMCR_ANRESTART;
+		xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, ret);
+	}
+}
+
 static u32 xpcs_get_id(struct dw_xpcs *xpcs)
 {
 	int ret;
@@ -1060,6 +1233,12 @@ static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
 		.num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
 		.an_mode = DW_AN_C37_SGMII,
 	},
+	[DW_XPCS_1000BASEX] = {
+		.supported = xpcs_1000basex_features,
+		.interface = xpcs_1000basex_interfaces,
+		.num_interfaces = ARRAY_SIZE(xpcs_1000basex_interfaces),
+		.an_mode = DW_AN_C37_1000BASEX,
+	},
 	[DW_XPCS_2500BASEX] = {
 		.supported = xpcs_2500basex_features,
 		.interface = xpcs_2500basex_interfaces,
@@ -1115,6 +1294,7 @@ static const struct phylink_pcs_ops xpcs_phylink_ops = {
 	.pcs_validate = xpcs_validate,
 	.pcs_config = xpcs_config,
 	.pcs_get_state = xpcs_get_state,
+	.pcs_an_restart = xpcs_an_restart,
 	.pcs_link_up = xpcs_link_up,
 };
 
diff --git a/include/linux/pcs/pcs-xpcs.h b/include/linux/pcs/pcs-xpcs.h
index 37eb97cc228..d2da1e0b4a9 100644
--- a/include/linux/pcs/pcs-xpcs.h
+++ b/include/linux/pcs/pcs-xpcs.h
@@ -17,6 +17,7 @@
 #define DW_AN_C73			1
 #define DW_AN_C37_SGMII			2
 #define DW_2500BASEX			3
+#define DW_AN_C37_1000BASEX		4
 
 struct xpcs_id;
 
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 4/6] net: phylink: unset ovr_an_inband if fixed-link is selected
  2022-06-10  3:29 ` Ong Boon Leong
@ 2022-06-10  3:29   ` Ong Boon Leong
  -1 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

If "fixed-link" DT or ACPI _DSD subnode is selected, it should take
precedence over the value of ovr_an_inband passed by MAC driver.

Fixes: ab39385021d1 ("net: phylink: make phylink_parse_mode() support non-DT platform")
Tested-by: Emilio Riva <emilio.riva@ericsson.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/phy/phylink.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 066684b8091..566852815e0 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -609,8 +609,10 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
 	const char *managed;
 
 	dn = fwnode_get_named_child_node(fwnode, "fixed-link");
-	if (dn || fwnode_property_present(fwnode, "fixed-link"))
+	if (dn || fwnode_property_present(fwnode, "fixed-link")) {
 		pl->cfg_link_an_mode = MLO_AN_FIXED;
+		pl->config->ovr_an_inband = false;
+	}
 	fwnode_handle_put(dn);
 
 	if ((fwnode_property_read_string(fwnode, "managed", &managed) == 0 &&
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 4/6] net: phylink: unset ovr_an_inband if fixed-link is selected
@ 2022-06-10  3:29   ` Ong Boon Leong
  0 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

If "fixed-link" DT or ACPI _DSD subnode is selected, it should take
precedence over the value of ovr_an_inband passed by MAC driver.

Fixes: ab39385021d1 ("net: phylink: make phylink_parse_mode() support non-DT platform")
Tested-by: Emilio Riva <emilio.riva@ericsson.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/phy/phylink.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
index 066684b8091..566852815e0 100644
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
@@ -609,8 +609,10 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
 	const char *managed;
 
 	dn = fwnode_get_named_child_node(fwnode, "fixed-link");
-	if (dn || fwnode_property_present(fwnode, "fixed-link"))
+	if (dn || fwnode_property_present(fwnode, "fixed-link")) {
 		pl->cfg_link_an_mode = MLO_AN_FIXED;
+		pl->config->ovr_an_inband = false;
+	}
 	fwnode_handle_put(dn);
 
 	if ((fwnode_property_read_string(fwnode, "managed", &managed) == 0 &&
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 5/6] stmmac: intel: add phy-mode ACPI _DSD setting support
  2022-06-10  3:29 ` Ong Boon Leong
@ 2022-06-10  3:29   ` Ong Boon Leong
  -1 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

Currently, phy_interface for TSN controller instance is set based on its
PCI Device ID. For SGMII PHY interface, phy_interface default to
PHY_INTERFACE_MODE_SGMII. As C37 AN supports both SGMII and 1000BASE-X
mode, we add support for 'phy-mode' ACPI _DSD for port-specific
and customer platform specific customization.

Thanks to Andrew Lunn's guidance in
https://patchwork.kernel.org/comment/24827101/

Tested-by: Emilio Riva <emilio.riva@ericsson.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index 675dfb89b76..e5f3d7deec3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -442,6 +442,7 @@ static void common_default_data(struct plat_stmmacenet_data *plat)
 static int intel_mgbe_common_data(struct pci_dev *pdev,
 				  struct plat_stmmacenet_data *plat)
 {
+	struct fwnode_handle *fwnode;
 	char clk_name[20];
 	int ret;
 	int i;
@@ -560,6 +561,20 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
 	/* Use the last Rx queue */
 	plat->vlan_fail_q = plat->rx_queues_to_use - 1;
 
+	/* For fixed-link setup, we allow phy-mode setting */
+	fwnode = dev_fwnode(&pdev->dev);
+	if (fwnode) {
+		const char *phy_mode;
+
+		if (!fwnode_property_read_string(fwnode, "phy-mode",
+						 &phy_mode)) {
+			if (!strcmp(phy_mode, "sgmii"))
+				plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+			if (!strcmp(phy_mode, "1000base-x"))
+				plat->phy_interface = PHY_INTERFACE_MODE_1000BASEX;
+		}
+	}
+
 	/* Intel mgbe SGMII interface uses pcs-xcps */
 	if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
 	    plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 5/6] stmmac: intel: add phy-mode ACPI _DSD setting support
@ 2022-06-10  3:29   ` Ong Boon Leong
  0 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

Currently, phy_interface for TSN controller instance is set based on its
PCI Device ID. For SGMII PHY interface, phy_interface default to
PHY_INTERFACE_MODE_SGMII. As C37 AN supports both SGMII and 1000BASE-X
mode, we add support for 'phy-mode' ACPI _DSD for port-specific
and customer platform specific customization.

Thanks to Andrew Lunn's guidance in
https://patchwork.kernel.org/comment/24827101/

Tested-by: Emilio Riva <emilio.riva@ericsson.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index 675dfb89b76..e5f3d7deec3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -442,6 +442,7 @@ static void common_default_data(struct plat_stmmacenet_data *plat)
 static int intel_mgbe_common_data(struct pci_dev *pdev,
 				  struct plat_stmmacenet_data *plat)
 {
+	struct fwnode_handle *fwnode;
 	char clk_name[20];
 	int ret;
 	int i;
@@ -560,6 +561,20 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
 	/* Use the last Rx queue */
 	plat->vlan_fail_q = plat->rx_queues_to_use - 1;
 
+	/* For fixed-link setup, we allow phy-mode setting */
+	fwnode = dev_fwnode(&pdev->dev);
+	if (fwnode) {
+		const char *phy_mode;
+
+		if (!fwnode_property_read_string(fwnode, "phy-mode",
+						 &phy_mode)) {
+			if (!strcmp(phy_mode, "sgmii"))
+				plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+			if (!strcmp(phy_mode, "1000base-x"))
+				plat->phy_interface = PHY_INTERFACE_MODE_1000BASEX;
+		}
+	}
+
 	/* Intel mgbe SGMII interface uses pcs-xcps */
 	if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
 	    plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 6/6] net: stmmac: make mdio register skips PHY scanning for fixed-link
  2022-06-10  3:29 ` Ong Boon Leong
@ 2022-06-10  3:29   ` Ong Boon Leong
  -1 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

stmmac_mdio_register() lacks fixed-link consideration and only skip PHY
scanning if it has done DT style PHY discovery. So, for DT or ACPI _DSD
setting of fixed-link, the PHY scanning should not happen.

Tested-by: Emilio Riva <emilio.riva@ericsson.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 11 ++++++-----
 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 14 ++++++++++++++
 2 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 73cae2938f6..bc8edd88175 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1141,19 +1141,20 @@ static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
  */
 static int stmmac_init_phy(struct net_device *dev)
 {
+	struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
 	struct stmmac_priv *priv = netdev_priv(dev);
-	struct device_node *node;
 	int ret;
 
-	node = priv->plat->phylink_node;
+	if (!fwnode)
+		fwnode = dev_fwnode(priv->device);
 
-	if (node)
-		ret = phylink_of_phy_connect(priv->phylink, node, 0);
+	if (fwnode)
+		ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0);
 
 	/* Some DT bindings do not set-up the PHY handle. Let's try to
 	 * manually parse it
 	 */
-	if (!node || ret) {
+	if (!fwnode || ret) {
 		int addr = priv->plat->phy_addr;
 		struct phy_device *phydev;
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index 03d3d1f7aa4..5f177ea8072 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -434,9 +434,11 @@ int stmmac_mdio_register(struct net_device *ndev)
 	int err = 0;
 	struct mii_bus *new_bus;
 	struct stmmac_priv *priv = netdev_priv(ndev);
+	struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
 	struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
 	struct device_node *mdio_node = priv->plat->mdio_node;
 	struct device *dev = ndev->dev.parent;
+	struct fwnode_handle *fixed_node;
 	int addr, found, max_addr;
 
 	if (!mdio_bus_data)
@@ -490,6 +492,18 @@ int stmmac_mdio_register(struct net_device *ndev)
 	if (priv->plat->has_xgmac)
 		stmmac_xgmac2_mdio_read(new_bus, 0, MII_ADDR_C45);
 
+	/* If fixed-link is set, skip PHY scanning */
+	if (!fwnode)
+		fwnode = dev_fwnode(priv->device);
+
+	if (fwnode) {
+		fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
+		if (fixed_node) {
+			fwnode_handle_put(fixed_node);
+			goto bus_register_done;
+		}
+	}
+
 	if (priv->plat->phy_node || mdio_node)
 		goto bus_register_done;
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 24+ messages in thread
* [PATCH net-next v2 6/6] net: stmmac: make mdio register skips PHY scanning for fixed-link
@ 2022-06-10  3:29   ` Ong Boon Leong
  0 siblings, 0 replies; 24+ messages in thread
From: Ong Boon Leong @ 2022-06-10  3:29 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Emilio Riva,
	Ong Boon Leong

stmmac_mdio_register() lacks fixed-link consideration and only skip PHY
scanning if it has done DT style PHY discovery. So, for DT or ACPI _DSD
setting of fixed-link, the PHY scanning should not happen.

Tested-by: Emilio Riva <emilio.riva@ericsson.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 11 ++++++-----
 drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c | 14 ++++++++++++++
 2 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 73cae2938f6..bc8edd88175 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1141,19 +1141,20 @@ static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
  */
 static int stmmac_init_phy(struct net_device *dev)
 {
+	struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
 	struct stmmac_priv *priv = netdev_priv(dev);
-	struct device_node *node;
 	int ret;
 
-	node = priv->plat->phylink_node;
+	if (!fwnode)
+		fwnode = dev_fwnode(priv->device);
 
-	if (node)
-		ret = phylink_of_phy_connect(priv->phylink, node, 0);
+	if (fwnode)
+		ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0);
 
 	/* Some DT bindings do not set-up the PHY handle. Let's try to
 	 * manually parse it
 	 */
-	if (!node || ret) {
+	if (!fwnode || ret) {
 		int addr = priv->plat->phy_addr;
 		struct phy_device *phydev;
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index 03d3d1f7aa4..5f177ea8072 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -434,9 +434,11 @@ int stmmac_mdio_register(struct net_device *ndev)
 	int err = 0;
 	struct mii_bus *new_bus;
 	struct stmmac_priv *priv = netdev_priv(ndev);
+	struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
 	struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
 	struct device_node *mdio_node = priv->plat->mdio_node;
 	struct device *dev = ndev->dev.parent;
+	struct fwnode_handle *fixed_node;
 	int addr, found, max_addr;
 
 	if (!mdio_bus_data)
@@ -490,6 +492,18 @@ int stmmac_mdio_register(struct net_device *ndev)
 	if (priv->plat->has_xgmac)
 		stmmac_xgmac2_mdio_read(new_bus, 0, MII_ADDR_C45);
 
+	/* If fixed-link is set, skip PHY scanning */
+	if (!fwnode)
+		fwnode = dev_fwnode(priv->device);
+
+	if (fwnode) {
+		fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
+		if (fixed_node) {
+			fwnode_handle_put(fixed_node);
+			goto bus_register_done;
+		}
+	}
+
 	if (priv->plat->phy_node || mdio_node)
 		goto bus_register_done;
 
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 24+ messages in thread
* RE: [PATCH net-next v2 0/7] pcs-xpcs, stmmac: add 1000BASE-X AN for network switch
  2022-06-10  3:29 ` Ong Boon Leong
@ 2022-06-10  3:37   ` Ong, Boon Leong
  -1 siblings, 0 replies; 24+ messages in thread
From: Ong, Boon Leong @ 2022-06-10  3:37 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Riva, Emilio

My bad in missing the 1/7 patch. Please ignore these series. I will be sending v3. 

>-----Original Message-----
>From: Ong, Boon Leong <boon.leong.ong@intel.com>
>Sent: Friday, June 10, 2022 11:30 AM
>To: Alexandre Torgue <alexandre.torgue@foss.st.com>; Jose Abreu
><Jose.Abreu@synopsys.com>; Andrew Lunn <andrew@lunn.ch>; Heiner
>Kallweit <hkallweit1@gmail.com>; Russell King <linux@armlinux.org.uk>; Paolo
>Abeni <pabeni@redhat.com>; David S . Miller <davem@davemloft.net>; Eric
>Dumazet <edumazet@google.com>; Jakub Kicinski <kuba@kernel.org>;
>Vladimir Oltean <olteanv@gmail.com>; Vivien Didelot
><vivien.didelot@gmail.com>; Florian Fainelli <f.fainelli@gmail.com>; Maxime
>Coquelin <mcoquelin.stm32@gmail.com>; Giuseppe Cavallaro
><peppe.cavallaro@st.com>
>Cc: netdev@vger.kernel.org; linux-stm32@st-md-mailman.stormreply.com;
>linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Riva,
>Emilio <emilio.riva@ericsson.com>; Ong, Boon Leong
><boon.leong.ong@intel.com>
>Subject: [PATCH net-next v2 0/7] pcs-xpcs, stmmac: add 1000BASE-X AN for
>network switch
>
>Hi,
>
>Thanks Russell King [1] and Andrew Lunn [2] for v1 review and suggestion.
>Since then, I have worked on refactoring the implementation as follow:
>
>v2 changes:
>1/7 - [New] Update xpcs_do_config to accept advertising input
>2/7 - [New] Fix to compilation issue introduced v1. Update xpcs_do_config
>            for sja1105.
>3/7 - Same as 3/4 of v1 series.
>4/7 - [Fix] Fix numerous issues identified by Russell King [1].
>5/7 - [New] Make fixed-link setting takes precedence over ovr_an_inband.
>            This is a fix to a bug introduced earlier. Separate patch
>            will be sent later.
>6/7 - [New] Allow phy-mode ACPI _DSD setting for dwmac-intel to overwrite
>            the phy_interface detected through PCI DevID.
>7/7 - [New] Make mdio register flow to skip PHY scanning if fixed-link
>            is specified.
>
>I have tested the patch-series on a 3-port SGMII Ethernet on Elkhart Lake
>customer platform and PSE GbE1 (0000:00:1d.2) is setup for fixed-link
>with below ACPI _DSD modification based on [3]:-
>
>        Device (OTN1)
>        {
>            <snippet-remove>
>
>            Name (_DSD, Package () {
>                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
>                    Package () {
>                        Package () {"phy-mode", "1000base-x"},
>                    },
>                ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
>                    Package () {
>                        Package () {"fixed-link", "LNK0"}
>                    }
>            })
>
>            Name (LNK0, Package(){ // Data-only subnode of port
>                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
>                    Package () {
>                        Package () {"speed", 1000},
>                        Package () {"full-duplex", 1}
>                    }
>            })
>        }
>
>The modified ACPI DSDT table is inserted into OS based on [4] for
>testing purpose. This method will not be required if respective BIOS has
>the matching ACPI _DSD changes. In gist, we avoid the need to add board
>specific DMI based configuration to Linux driver and let ACPI DSDT table
>customized according to hardware/port configuration design to decide how
>the driver is loaded up per port-basis.
>
>From dmesg below (whereby non-relevant section removed), we can see that:-
>
>[    4.112037] intel-eth-pci 0000:00:1d.1 eno1: configuring for inband/sgmii
>link mode
>[    4.132016] intel-eth-pci 0000:00:1d.2 eno2: configuring for
>fixed/1000base-x link mode
>[    4.162069] intel-eth-pci 0000:00:1e.4 eno3: configuring for inband/sgmii
>link mode
>
>----------------------------------------------------------------------------------------------------------
>-
>[    1.471347] intel-eth-pci 0000:00:1d.1: stmmac_config_multi_msi: multi MSI
>enablement successful
>[    1.471518] intel-eth-pci 0000:00:1d.1: User ID: 0x51, Synopsys ID: 0x52
>[    1.471525] intel-eth-pci 0000:00:1d.1:      DWMAC4/5
>[    1.471531] intel-eth-pci 0000:00:1d.1: DMA HW capability register
>supported
>[    1.471533] intel-eth-pci 0000:00:1d.1: RX Checksum Offload Engine
>supported
>[    1.471535] intel-eth-pci 0000:00:1d.1: TX Checksum insertion supported
>[    1.471536] intel-eth-pci 0000:00:1d.1: TSO supported
>[    1.471537] intel-eth-pci 0000:00:1d.1: Enable RX Mitigation via HW
>Watchdog Timer
>[    1.471542] intel-eth-pci 0000:00:1d.1: device MAC address
>a8:a1:59:9d:2b:64
>[    1.471545] intel-eth-pci 0000:00:1d.1: Enabled L3L4 Flow TC (entries=2)
>[    1.471547] intel-eth-pci 0000:00:1d.1: Enabled RFS Flow TC (entries=10)
>[    1.471552] intel-eth-pci 0000:00:1d.1: Enabling HW TC (entries=256,
>max_off=256)
>[    1.471555] intel-eth-pci 0000:00:1d.1: TSO feature enabled
>[    1.471556] intel-eth-pci 0000:00:1d.1: Using 32 bits DMA width
>[    1.471770] mdio_bus stmmac-2: GPIO lookup for consumer reset
>[    1.471774] mdio_bus stmmac-2: using lookup tables for GPIO lookup
>[    1.471777] mdio_bus stmmac-2: No GPIO consumer reset found
>[    1.481872] mdio_bus stmmac-2:01: GPIO lookup for consumer reset
>[    1.481879] mdio_bus stmmac-2:01: using lookup tables for GPIO lookup
>[    1.481881] mdio_bus stmmac-2:01: No GPIO consumer reset found
>[    1.483206] Maxlinear Ethernet GPY215B stmmac-2:01: Firmware Version:
>0x8764 (release)
>
>[    1.683631] Maxlinear Ethernet GPY215B stmmac-2:01: attached PHY driver
>(mii_bus:phy_addr=stmmac-2:01, irq=POLL)
>
>[    1.749607] intel-eth-pci 0000:00:1d.2: stmmac_config_multi_msi: multi MSI
>enablement successful
>[    1.749677] intel-eth-pci 0000:00:1d.2: User ID: 0x51, Synopsys ID: 0x52
>[    1.749681] intel-eth-pci 0000:00:1d.2:      DWMAC4/5
>[    1.749688] intel-eth-pci 0000:00:1d.2: DMA HW capability register
>supported
>[    1.749690] intel-eth-pci 0000:00:1d.2: RX Checksum Offload Engine
>supported
>[    1.749692] intel-eth-pci 0000:00:1d.2: TX Checksum insertion supported
>[    1.749693] intel-eth-pci 0000:00:1d.2: TSO supported
>[    1.749694] intel-eth-pci 0000:00:1d.2: Enable RX Mitigation via HW
>Watchdog Timer
>[    1.749701] intel-eth-pci 0000:00:1d.2: device MAC address
>a8:a1:59:9d:2b:46
>[    1.749703] intel-eth-pci 0000:00:1d.2: Enabled L3L4 Flow TC (entries=2)
>[    1.749705] intel-eth-pci 0000:00:1d.2: Enabled RFS Flow TC (entries=10)
>[    1.749710] intel-eth-pci 0000:00:1d.2: Enabling HW TC (entries=256,
>max_off=256)
>[    1.749712] intel-eth-pci 0000:00:1d.2: TSO feature enabled
>[    1.749714] intel-eth-pci 0000:00:1d.2: Using 32 bits DMA width
>
>[    1.749821] mdio_bus stmmac-3: GPIO lookup for consumer reset
>[    1.749823] mdio_bus stmmac-3: using lookup tables for GPIO lookup
>[    1.749825] mdio_bus stmmac-3: No GPIO consumer reset found
>[    1.759184] mdio_bus stmmac-3:01: GPIO lookup for consumer reset
>[    1.759188] mdio_bus stmmac-3:01: using lookup tables for GPIO lookup
>[    1.759190] mdio_bus stmmac-3:01: No GPIO consumer reset found
>[    1.760419] Maxlinear Ethernet GPY215B stmmac-3:01: Firmware Version:
>0x8764 (release)
>
>[    2.025792] intel-eth-pci 0000:00:1e.4: stmmac_config_multi_msi: multi MSI
>enablement successful
>[    2.025876] intel-eth-pci 0000:00:1e.4: User ID: 0x51, Synopsys ID: 0x52
>[    2.025881] intel-eth-pci 0000:00:1e.4:      DWMAC4/5
>[    2.025887] sdhci-pci 0000:00:1a.1: No GPIO consumer (null) found
>[    2.025888] intel-eth-pci 0000:00:1e.4: DMA HW capability register
>supported
>[    2.025891] intel-eth-pci 0000:00:1e.4: RX Checksum Offload Engine
>supported
>[    2.025893] intel-eth-pci 0000:00:1e.4: TX Checksum insertion supported
>[    2.025894] intel-eth-pci 0000:00:1e.4: TSO supported
>[    2.025896] intel-eth-pci 0000:00:1e.4: Enable RX Mitigation via HW
>Watchdog Timer
>[    2.025913] intel-eth-pci 0000:00:1e.4: device MAC address
>a8:a1:59:9d:2b:7a
>[    2.025915] intel-eth-pci 0000:00:1e.4: Enabled L3L4 Flow TC (entries=2)
>[    2.025917] intel-eth-pci 0000:00:1e.4: Enabled RFS Flow TC (entries=10)
>[    2.025924] intel-eth-pci 0000:00:1e.4: Enabling HW TC (entries=256,
>max_off=256)
>[    2.025926] intel-eth-pci 0000:00:1e.4: TSO feature enabled
>[    2.025928] intel-eth-pci 0000:00:1e.4: Using 40 bits DMA width
>[    2.026024] mdio_bus stmmac-1: GPIO lookup for consumer reset
>[    2.026027] mdio_bus stmmac-1: using lookup tables for GPIO lookup
>[    2.026029] mdio_bus stmmac-1: No GPIO consumer reset found
>[    2.035547] mdio_bus stmmac-1:01: GPIO lookup for consumer reset
>[    2.035551] mdio_bus stmmac-1:01: using lookup tables for GPIO lookup
>[    2.035553] mdio_bus stmmac-1:01: No GPIO consumer reset found
>[    2.036905] Maxlinear Ethernet GPY215B stmmac-1:01: Firmware Version:
>0x8764 (release)
>
>[    2.239477] Maxlinear Ethernet GPY215B stmmac-1:01: attached PHY driver
>(mii_bus:phy_addr=stmmac-1:01, irq=POLL)
>
>[    2.305510] intel-eth-pci 0000:00:1d.2 eno2: renamed from eth1
>[    2.315038] intel-eth-pci 0000:00:1d.1 eno1: renamed from eth0
>[    2.320776] intel-eth-pci 0000:00:1e.4 eno3: renamed from eth2
>
>[    4.098137] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-0
>[    4.098647] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-1
>[    4.099187] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-2
>[    4.099695] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-3
>[    4.100168] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-4
>[    4.100636] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-5
>[    4.101114] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-6
>[    4.101586] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-7
>[    4.111664] dwmac4: Master AXI performs any burst length
>[    4.111750] intel-eth-pci 0000:00:1d.1 eno1: Enabling Safety Features
>[    4.111795] intel-eth-pci 0000:00:1d.1 eno1: IEEE 1588-2008 Advanced
>Timestamp supported
>[    4.111897] intel-eth-pci 0000:00:1d.1 eno1: registered PTP clock
>[    4.112033] intel-eth-pci 0000:00:1d.1 eno1: FPE workqueue start
>[    4.112037] intel-eth-pci 0000:00:1d.1 eno1: configuring for inband/sgmii
>link mode
>[    4.113621] 8021q: adding VLAN 0 to HW filter on device eno1
>
>[    4.118316] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-0
>[    4.118835] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-1
>[    4.119338] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-2
>[    4.119815] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-3
>[    4.120282] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-4
>[    4.120758] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-5
>[    4.121228] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-6
>[    4.121706] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-7
>[    4.131662] dwmac4: Master AXI performs any burst length
>[    4.131744] intel-eth-pci 0000:00:1d.2 eno2: Enabling Safety Features
>[    4.131790] intel-eth-pci 0000:00:1d.2 eno2: IEEE 1588-2008 Advanced
>Timestamp supported
>[    4.131873] intel-eth-pci 0000:00:1d.2 eno2: registered PTP clock
>[    4.132010] intel-eth-pci 0000:00:1d.2 eno2: FPE workqueue start
>[    4.132016] intel-eth-pci 0000:00:1d.2 eno2: configuring for
>fixed/1000base-x link mode
>[    4.133517] 8021q: adding VLAN 0 to HW filter on device eno2
>[    4.133677] intel-eth-pci 0000:00:1d.2 eno2: Link is Up - 1Gbps/Full - flow
>control off
>[    4.133687] IPv6: ADDRCONF(NETDEV_CHANGE): eno2: link becomes ready
>
>[    4.138058] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-0
>[    4.138557] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-1
>[    4.139105] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-2
>[    4.139581] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-3
>[    4.140071] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-4
>[    4.140547] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-5
>[    4.141041] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-6
>[    4.141519] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-7
>[    4.151671] dwmac4: Master AXI performs any burst length
>[    4.151751] intel-eth-pci 0000:00:1e.4 eno3: Enabling Safety Features
>[    4.161830] intel-eth-pci 0000:00:1e.4 eno3: IEEE 1588-2008 Advanced
>Timestamp supported
>[    4.161916] intel-eth-pci 0000:00:1e.4 eno3: registered PTP clock
>[    4.162063] intel-eth-pci 0000:00:1e.4 eno3: FPE workqueue start
>[    4.162069] intel-eth-pci 0000:00:1e.4 eno3: configuring for inband/sgmii
>link mode
>----------------------------------------------------------------------------------------------------------
>-
>
>Also, thanks to Emilio Riva from Ericsson who has been helping me in testing
>the patch
>on his system too.
>
>Reference:
>[1] https://patchwork.kernel.org/comment/24826650/
>[2] https://patchwork.kernel.org/comment/24827101/
>[3] https://www.kernel.org/doc/html/latest/firmware-
>guide/acpi/dsd/phy.html#mac-node-example-with-a-fixed-link-subnode
>[4] https://www.kernel.org/doc/html/latest/admin-
>guide/acpi/initrd_table_override.html
>
>Thanks
>Boon Leong
>
>Ong Boon Leong (7):
>  net: pcs: xpcs: prepare xpcs_do_config to accept advertising input
>  net: dsa: sja1105: update xpcs_do_config additional input
>  stmmac: intel: prepare to support 1000BASE-X phy interface setting
>  net: pcs: xpcs: add CL37 1000BASE-X AN support
>  net: phylink: unset ovr_an_inband if fixed-link is selected
>  stmmac: intel: add phy-mode ACPI _DSD setting support
>  net: stmmac: make mdio register skips PHY scanning for fixed-link
>
> drivers/net/dsa/sja1105/sja1105_main.c        |   2 +-
> .../net/ethernet/stmicro/stmmac/dwmac-intel.c |  19 +-
> .../net/ethernet/stmicro/stmmac/stmmac_main.c |  11 +-
> .../net/ethernet/stmicro/stmmac/stmmac_mdio.c |  14 ++
> drivers/net/pcs/pcs-xpcs.c                    | 186 +++++++++++++++++-
> drivers/net/phy/phylink.c                     |   4 +-
> include/linux/pcs/pcs-xpcs.h                  |   3 +-
> 7 files changed, 226 insertions(+), 13 deletions(-)
>
>--
>2.25.1


^ permalink raw reply	[flat|nested] 24+ messages in thread
* RE: [PATCH net-next v2 0/7] pcs-xpcs, stmmac: add 1000BASE-X AN for network switch
@ 2022-06-10  3:37   ` Ong, Boon Leong
  0 siblings, 0 replies; 24+ messages in thread
From: Ong, Boon Leong @ 2022-06-10  3:37 UTC (permalink / raw)
  To: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Russell King, Paolo Abeni, David S . Miller, Eric Dumazet,
	Jakub Kicinski, Vladimir Oltean, Vivien Didelot,
	Florian Fainelli, Maxime Coquelin, Giuseppe Cavallaro
  Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel, Riva, Emilio

My bad in missing the 1/7 patch. Please ignore these series. I will be sending v3. 

>-----Original Message-----
>From: Ong, Boon Leong <boon.leong.ong@intel.com>
>Sent: Friday, June 10, 2022 11:30 AM
>To: Alexandre Torgue <alexandre.torgue@foss.st.com>; Jose Abreu
><Jose.Abreu@synopsys.com>; Andrew Lunn <andrew@lunn.ch>; Heiner
>Kallweit <hkallweit1@gmail.com>; Russell King <linux@armlinux.org.uk>; Paolo
>Abeni <pabeni@redhat.com>; David S . Miller <davem@davemloft.net>; Eric
>Dumazet <edumazet@google.com>; Jakub Kicinski <kuba@kernel.org>;
>Vladimir Oltean <olteanv@gmail.com>; Vivien Didelot
><vivien.didelot@gmail.com>; Florian Fainelli <f.fainelli@gmail.com>; Maxime
>Coquelin <mcoquelin.stm32@gmail.com>; Giuseppe Cavallaro
><peppe.cavallaro@st.com>
>Cc: netdev@vger.kernel.org; linux-stm32@st-md-mailman.stormreply.com;
>linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Riva,
>Emilio <emilio.riva@ericsson.com>; Ong, Boon Leong
><boon.leong.ong@intel.com>
>Subject: [PATCH net-next v2 0/7] pcs-xpcs, stmmac: add 1000BASE-X AN for
>network switch
>
>Hi,
>
>Thanks Russell King [1] and Andrew Lunn [2] for v1 review and suggestion.
>Since then, I have worked on refactoring the implementation as follow:
>
>v2 changes:
>1/7 - [New] Update xpcs_do_config to accept advertising input
>2/7 - [New] Fix to compilation issue introduced v1. Update xpcs_do_config
>            for sja1105.
>3/7 - Same as 3/4 of v1 series.
>4/7 - [Fix] Fix numerous issues identified by Russell King [1].
>5/7 - [New] Make fixed-link setting takes precedence over ovr_an_inband.
>            This is a fix to a bug introduced earlier. Separate patch
>            will be sent later.
>6/7 - [New] Allow phy-mode ACPI _DSD setting for dwmac-intel to overwrite
>            the phy_interface detected through PCI DevID.
>7/7 - [New] Make mdio register flow to skip PHY scanning if fixed-link
>            is specified.
>
>I have tested the patch-series on a 3-port SGMII Ethernet on Elkhart Lake
>customer platform and PSE GbE1 (0000:00:1d.2) is setup for fixed-link
>with below ACPI _DSD modification based on [3]:-
>
>        Device (OTN1)
>        {
>            <snippet-remove>
>
>            Name (_DSD, Package () {
>                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
>                    Package () {
>                        Package () {"phy-mode", "1000base-x"},
>                    },
>                ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
>                    Package () {
>                        Package () {"fixed-link", "LNK0"}
>                    }
>            })
>
>            Name (LNK0, Package(){ // Data-only subnode of port
>                ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
>                    Package () {
>                        Package () {"speed", 1000},
>                        Package () {"full-duplex", 1}
>                    }
>            })
>        }
>
>The modified ACPI DSDT table is inserted into OS based on [4] for
>testing purpose. This method will not be required if respective BIOS has
>the matching ACPI _DSD changes. In gist, we avoid the need to add board
>specific DMI based configuration to Linux driver and let ACPI DSDT table
>customized according to hardware/port configuration design to decide how
>the driver is loaded up per port-basis.
>
>From dmesg below (whereby non-relevant section removed), we can see that:-
>
>[    4.112037] intel-eth-pci 0000:00:1d.1 eno1: configuring for inband/sgmii
>link mode
>[    4.132016] intel-eth-pci 0000:00:1d.2 eno2: configuring for
>fixed/1000base-x link mode
>[    4.162069] intel-eth-pci 0000:00:1e.4 eno3: configuring for inband/sgmii
>link mode
>
>----------------------------------------------------------------------------------------------------------
>-
>[    1.471347] intel-eth-pci 0000:00:1d.1: stmmac_config_multi_msi: multi MSI
>enablement successful
>[    1.471518] intel-eth-pci 0000:00:1d.1: User ID: 0x51, Synopsys ID: 0x52
>[    1.471525] intel-eth-pci 0000:00:1d.1:      DWMAC4/5
>[    1.471531] intel-eth-pci 0000:00:1d.1: DMA HW capability register
>supported
>[    1.471533] intel-eth-pci 0000:00:1d.1: RX Checksum Offload Engine
>supported
>[    1.471535] intel-eth-pci 0000:00:1d.1: TX Checksum insertion supported
>[    1.471536] intel-eth-pci 0000:00:1d.1: TSO supported
>[    1.471537] intel-eth-pci 0000:00:1d.1: Enable RX Mitigation via HW
>Watchdog Timer
>[    1.471542] intel-eth-pci 0000:00:1d.1: device MAC address
>a8:a1:59:9d:2b:64
>[    1.471545] intel-eth-pci 0000:00:1d.1: Enabled L3L4 Flow TC (entries=2)
>[    1.471547] intel-eth-pci 0000:00:1d.1: Enabled RFS Flow TC (entries=10)
>[    1.471552] intel-eth-pci 0000:00:1d.1: Enabling HW TC (entries=256,
>max_off=256)
>[    1.471555] intel-eth-pci 0000:00:1d.1: TSO feature enabled
>[    1.471556] intel-eth-pci 0000:00:1d.1: Using 32 bits DMA width
>[    1.471770] mdio_bus stmmac-2: GPIO lookup for consumer reset
>[    1.471774] mdio_bus stmmac-2: using lookup tables for GPIO lookup
>[    1.471777] mdio_bus stmmac-2: No GPIO consumer reset found
>[    1.481872] mdio_bus stmmac-2:01: GPIO lookup for consumer reset
>[    1.481879] mdio_bus stmmac-2:01: using lookup tables for GPIO lookup
>[    1.481881] mdio_bus stmmac-2:01: No GPIO consumer reset found
>[    1.483206] Maxlinear Ethernet GPY215B stmmac-2:01: Firmware Version:
>0x8764 (release)
>
>[    1.683631] Maxlinear Ethernet GPY215B stmmac-2:01: attached PHY driver
>(mii_bus:phy_addr=stmmac-2:01, irq=POLL)
>
>[    1.749607] intel-eth-pci 0000:00:1d.2: stmmac_config_multi_msi: multi MSI
>enablement successful
>[    1.749677] intel-eth-pci 0000:00:1d.2: User ID: 0x51, Synopsys ID: 0x52
>[    1.749681] intel-eth-pci 0000:00:1d.2:      DWMAC4/5
>[    1.749688] intel-eth-pci 0000:00:1d.2: DMA HW capability register
>supported
>[    1.749690] intel-eth-pci 0000:00:1d.2: RX Checksum Offload Engine
>supported
>[    1.749692] intel-eth-pci 0000:00:1d.2: TX Checksum insertion supported
>[    1.749693] intel-eth-pci 0000:00:1d.2: TSO supported
>[    1.749694] intel-eth-pci 0000:00:1d.2: Enable RX Mitigation via HW
>Watchdog Timer
>[    1.749701] intel-eth-pci 0000:00:1d.2: device MAC address
>a8:a1:59:9d:2b:46
>[    1.749703] intel-eth-pci 0000:00:1d.2: Enabled L3L4 Flow TC (entries=2)
>[    1.749705] intel-eth-pci 0000:00:1d.2: Enabled RFS Flow TC (entries=10)
>[    1.749710] intel-eth-pci 0000:00:1d.2: Enabling HW TC (entries=256,
>max_off=256)
>[    1.749712] intel-eth-pci 0000:00:1d.2: TSO feature enabled
>[    1.749714] intel-eth-pci 0000:00:1d.2: Using 32 bits DMA width
>
>[    1.749821] mdio_bus stmmac-3: GPIO lookup for consumer reset
>[    1.749823] mdio_bus stmmac-3: using lookup tables for GPIO lookup
>[    1.749825] mdio_bus stmmac-3: No GPIO consumer reset found
>[    1.759184] mdio_bus stmmac-3:01: GPIO lookup for consumer reset
>[    1.759188] mdio_bus stmmac-3:01: using lookup tables for GPIO lookup
>[    1.759190] mdio_bus stmmac-3:01: No GPIO consumer reset found
>[    1.760419] Maxlinear Ethernet GPY215B stmmac-3:01: Firmware Version:
>0x8764 (release)
>
>[    2.025792] intel-eth-pci 0000:00:1e.4: stmmac_config_multi_msi: multi MSI
>enablement successful
>[    2.025876] intel-eth-pci 0000:00:1e.4: User ID: 0x51, Synopsys ID: 0x52
>[    2.025881] intel-eth-pci 0000:00:1e.4:      DWMAC4/5
>[    2.025887] sdhci-pci 0000:00:1a.1: No GPIO consumer (null) found
>[    2.025888] intel-eth-pci 0000:00:1e.4: DMA HW capability register
>supported
>[    2.025891] intel-eth-pci 0000:00:1e.4: RX Checksum Offload Engine
>supported
>[    2.025893] intel-eth-pci 0000:00:1e.4: TX Checksum insertion supported
>[    2.025894] intel-eth-pci 0000:00:1e.4: TSO supported
>[    2.025896] intel-eth-pci 0000:00:1e.4: Enable RX Mitigation via HW
>Watchdog Timer
>[    2.025913] intel-eth-pci 0000:00:1e.4: device MAC address
>a8:a1:59:9d:2b:7a
>[    2.025915] intel-eth-pci 0000:00:1e.4: Enabled L3L4 Flow TC (entries=2)
>[    2.025917] intel-eth-pci 0000:00:1e.4: Enabled RFS Flow TC (entries=10)
>[    2.025924] intel-eth-pci 0000:00:1e.4: Enabling HW TC (entries=256,
>max_off=256)
>[    2.025926] intel-eth-pci 0000:00:1e.4: TSO feature enabled
>[    2.025928] intel-eth-pci 0000:00:1e.4: Using 40 bits DMA width
>[    2.026024] mdio_bus stmmac-1: GPIO lookup for consumer reset
>[    2.026027] mdio_bus stmmac-1: using lookup tables for GPIO lookup
>[    2.026029] mdio_bus stmmac-1: No GPIO consumer reset found
>[    2.035547] mdio_bus stmmac-1:01: GPIO lookup for consumer reset
>[    2.035551] mdio_bus stmmac-1:01: using lookup tables for GPIO lookup
>[    2.035553] mdio_bus stmmac-1:01: No GPIO consumer reset found
>[    2.036905] Maxlinear Ethernet GPY215B stmmac-1:01: Firmware Version:
>0x8764 (release)
>
>[    2.239477] Maxlinear Ethernet GPY215B stmmac-1:01: attached PHY driver
>(mii_bus:phy_addr=stmmac-1:01, irq=POLL)
>
>[    2.305510] intel-eth-pci 0000:00:1d.2 eno2: renamed from eth1
>[    2.315038] intel-eth-pci 0000:00:1d.1 eno1: renamed from eth0
>[    2.320776] intel-eth-pci 0000:00:1e.4 eno3: renamed from eth2
>
>[    4.098137] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-0
>[    4.098647] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-1
>[    4.099187] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-2
>[    4.099695] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-3
>[    4.100168] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-4
>[    4.100636] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-5
>[    4.101114] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-6
>[    4.101586] intel-eth-pci 0000:00:1d.1 eno1: Register
>MEM_TYPE_PAGE_POOL RxQ-7
>[    4.111664] dwmac4: Master AXI performs any burst length
>[    4.111750] intel-eth-pci 0000:00:1d.1 eno1: Enabling Safety Features
>[    4.111795] intel-eth-pci 0000:00:1d.1 eno1: IEEE 1588-2008 Advanced
>Timestamp supported
>[    4.111897] intel-eth-pci 0000:00:1d.1 eno1: registered PTP clock
>[    4.112033] intel-eth-pci 0000:00:1d.1 eno1: FPE workqueue start
>[    4.112037] intel-eth-pci 0000:00:1d.1 eno1: configuring for inband/sgmii
>link mode
>[    4.113621] 8021q: adding VLAN 0 to HW filter on device eno1
>
>[    4.118316] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-0
>[    4.118835] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-1
>[    4.119338] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-2
>[    4.119815] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-3
>[    4.120282] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-4
>[    4.120758] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-5
>[    4.121228] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-6
>[    4.121706] intel-eth-pci 0000:00:1d.2 eno2: Register
>MEM_TYPE_PAGE_POOL RxQ-7
>[    4.131662] dwmac4: Master AXI performs any burst length
>[    4.131744] intel-eth-pci 0000:00:1d.2 eno2: Enabling Safety Features
>[    4.131790] intel-eth-pci 0000:00:1d.2 eno2: IEEE 1588-2008 Advanced
>Timestamp supported
>[    4.131873] intel-eth-pci 0000:00:1d.2 eno2: registered PTP clock
>[    4.132010] intel-eth-pci 0000:00:1d.2 eno2: FPE workqueue start
>[    4.132016] intel-eth-pci 0000:00:1d.2 eno2: configuring for
>fixed/1000base-x link mode
>[    4.133517] 8021q: adding VLAN 0 to HW filter on device eno2
>[    4.133677] intel-eth-pci 0000:00:1d.2 eno2: Link is Up - 1Gbps/Full - flow
>control off
>[    4.133687] IPv6: ADDRCONF(NETDEV_CHANGE): eno2: link becomes ready
>
>[    4.138058] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-0
>[    4.138557] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-1
>[    4.139105] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-2
>[    4.139581] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-3
>[    4.140071] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-4
>[    4.140547] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-5
>[    4.141041] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-6
>[    4.141519] intel-eth-pci 0000:00:1e.4 eno3: Register
>MEM_TYPE_PAGE_POOL RxQ-7
>[    4.151671] dwmac4: Master AXI performs any burst length
>[    4.151751] intel-eth-pci 0000:00:1e.4 eno3: Enabling Safety Features
>[    4.161830] intel-eth-pci 0000:00:1e.4 eno3: IEEE 1588-2008 Advanced
>Timestamp supported
>[    4.161916] intel-eth-pci 0000:00:1e.4 eno3: registered PTP clock
>[    4.162063] intel-eth-pci 0000:00:1e.4 eno3: FPE workqueue start
>[    4.162069] intel-eth-pci 0000:00:1e.4 eno3: configuring for inband/sgmii
>link mode
>----------------------------------------------------------------------------------------------------------
>-
>
>Also, thanks to Emilio Riva from Ericsson who has been helping me in testing
>the patch
>on his system too.
>
>Reference:
>[1] https://patchwork.kernel.org/comment/24826650/
>[2] https://patchwork.kernel.org/comment/24827101/
>[3] https://www.kernel.org/doc/html/latest/firmware-
>guide/acpi/dsd/phy.html#mac-node-example-with-a-fixed-link-subnode
>[4] https://www.kernel.org/doc/html/latest/admin-
>guide/acpi/initrd_table_override.html
>
>Thanks
>Boon Leong
>
>Ong Boon Leong (7):
>  net: pcs: xpcs: prepare xpcs_do_config to accept advertising input
>  net: dsa: sja1105: update xpcs_do_config additional input
>  stmmac: intel: prepare to support 1000BASE-X phy interface setting
>  net: pcs: xpcs: add CL37 1000BASE-X AN support
>  net: phylink: unset ovr_an_inband if fixed-link is selected
>  stmmac: intel: add phy-mode ACPI _DSD setting support
>  net: stmmac: make mdio register skips PHY scanning for fixed-link
>
> drivers/net/dsa/sja1105/sja1105_main.c        |   2 +-
> .../net/ethernet/stmicro/stmmac/dwmac-intel.c |  19 +-
> .../net/ethernet/stmicro/stmmac/stmmac_main.c |  11 +-
> .../net/ethernet/stmicro/stmmac/stmmac_mdio.c |  14 ++
> drivers/net/pcs/pcs-xpcs.c                    | 186 +++++++++++++++++-
> drivers/net/phy/phylink.c                     |   4 +-
> include/linux/pcs/pcs-xpcs.h                  |   3 +-
> 7 files changed, 226 insertions(+), 13 deletions(-)
>
>--
>2.25.1


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH net-next v2 3/6] net: pcs: xpcs: add CL37 1000BASE-X AN support
  2022-06-10  3:29   ` Ong Boon Leong
@ 2022-06-10  7:26     ` Russell King (Oracle)
  -1 siblings, 0 replies; 24+ messages in thread
From: Russell King (Oracle) @ 2022-06-10  7:26 UTC (permalink / raw)
  To: Ong Boon Leong
  Cc: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Paolo Abeni, David S . Miller, Eric Dumazet, Jakub Kicinski,
	Vladimir Oltean, Vivien Didelot, Florian Fainelli,
	Maxime Coquelin, Giuseppe Cavallaro, netdev, linux-stm32,
	linux-arm-kernel, linux-kernel, Emilio Riva

On Fri, Jun 10, 2022 at 11:29:38AM +0800, Ong Boon Leong wrote:
> +static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
> +					struct phylink_link_state *state)
> +{
> +	int lpa, adv;
> +	int ret;
> +
> +	if (state->an_enabled) {
> +		/* Reset link state */
> +		state->link = false;
> +
> +		lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
> +		if (lpa < 0 || lpa & LPA_RFAULT)
> +			return lpa;
> +
> +		adv = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
> +		if (adv < 0)
> +			return adv;
> +
> +		if (lpa & ADVERTISE_1000XFULL &&
> +		    adv & ADVERTISE_1000XFULL) {
> +			state->link = true;
> +			state->speed = SPEED_1000;
> +			state->duplex = DUPLEX_FULL;
> +		}

phylink_mii_c22_pcs_decode_state() is your friend here, will implement
this correctly, and will set lp_advertising correctly as well.

> +
> +		/* Clear CL37 AN complete status */
> +		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
> +		if (ret < 0)
> +			return ret;

Why do you need to clear the interrupt status here? This function will
be called from a work queue sometime later after an interrupt has fired.
It will also be called at random times when userspace enquires what the
link parameters are, so clearing the interrupt here can result in lost
link changes.

> +static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, int speed,
> +				   int duplex)
> +{
> +	int val, ret;
> +
> +	switch (speed) {
> +	case SPEED_1000:
> +		val = BMCR_SPEED1000;
> +		break;
> +	case SPEED_100:
> +	case SPEED_10:
> +	default:
> +		pr_err("%s: speed = %d\n", __func__, speed);
> +		return;
> +	}
> +
> +	if (duplex == DUPLEX_FULL)
> +		val |= BMCR_FULLDPLX;
> +	else
> +		pr_err("%s: half duplex not supported\n", __func__);
> +
> +	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
> +	if (ret)
> +		pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));

Does this need to be done even when AN is enabled?

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH net-next v2 3/6] net: pcs: xpcs: add CL37 1000BASE-X AN support
@ 2022-06-10  7:26     ` Russell King (Oracle)
  0 siblings, 0 replies; 24+ messages in thread
From: Russell King (Oracle) @ 2022-06-10  7:26 UTC (permalink / raw)
  To: Ong Boon Leong
  Cc: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Paolo Abeni, David S . Miller, Eric Dumazet, Jakub Kicinski,
	Vladimir Oltean, Vivien Didelot, Florian Fainelli,
	Maxime Coquelin, Giuseppe Cavallaro, netdev, linux-stm32,
	linux-arm-kernel, linux-kernel, Emilio Riva

On Fri, Jun 10, 2022 at 11:29:38AM +0800, Ong Boon Leong wrote:
> +static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
> +					struct phylink_link_state *state)
> +{
> +	int lpa, adv;
> +	int ret;
> +
> +	if (state->an_enabled) {
> +		/* Reset link state */
> +		state->link = false;
> +
> +		lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
> +		if (lpa < 0 || lpa & LPA_RFAULT)
> +			return lpa;
> +
> +		adv = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
> +		if (adv < 0)
> +			return adv;
> +
> +		if (lpa & ADVERTISE_1000XFULL &&
> +		    adv & ADVERTISE_1000XFULL) {
> +			state->link = true;
> +			state->speed = SPEED_1000;
> +			state->duplex = DUPLEX_FULL;
> +		}

phylink_mii_c22_pcs_decode_state() is your friend here, will implement
this correctly, and will set lp_advertising correctly as well.

> +
> +		/* Clear CL37 AN complete status */
> +		ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_AN_INTR_STS, 0);
> +		if (ret < 0)
> +			return ret;

Why do you need to clear the interrupt status here? This function will
be called from a work queue sometime later after an interrupt has fired.
It will also be called at random times when userspace enquires what the
link parameters are, so clearing the interrupt here can result in lost
link changes.

> +static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, int speed,
> +				   int duplex)
> +{
> +	int val, ret;
> +
> +	switch (speed) {
> +	case SPEED_1000:
> +		val = BMCR_SPEED1000;
> +		break;
> +	case SPEED_100:
> +	case SPEED_10:
> +	default:
> +		pr_err("%s: speed = %d\n", __func__, speed);
> +		return;
> +	}
> +
> +	if (duplex == DUPLEX_FULL)
> +		val |= BMCR_FULLDPLX;
> +	else
> +		pr_err("%s: half duplex not supported\n", __func__);
> +
> +	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
> +	if (ret)
> +		pr_err("%s: xpcs_write returned %pe\n", __func__, ERR_PTR(ret));

Does this need to be done even when AN is enabled?

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
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^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH net-next v2 4/6] net: phylink: unset ovr_an_inband if fixed-link is selected
  2022-06-10  3:29   ` Ong Boon Leong
@ 2022-06-10  7:31     ` Russell King (Oracle)
  -1 siblings, 0 replies; 24+ messages in thread
From: Russell King (Oracle) @ 2022-06-10  7:31 UTC (permalink / raw)
  To: Ong Boon Leong
  Cc: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Paolo Abeni, David S . Miller, Eric Dumazet, Jakub Kicinski,
	Vladimir Oltean, Vivien Didelot, Florian Fainelli,
	Maxime Coquelin, Giuseppe Cavallaro, netdev, linux-stm32,
	linux-arm-kernel, linux-kernel, Emilio Riva

On Fri, Jun 10, 2022 at 11:29:39AM +0800, Ong Boon Leong wrote:
> If "fixed-link" DT or ACPI _DSD subnode is selected, it should take
> precedence over the value of ovr_an_inband passed by MAC driver.
> 
> Fixes: ab39385021d1 ("net: phylink: make phylink_parse_mode() support non-DT platform")
> Tested-by: Emilio Riva <emilio.riva@ericsson.com>
> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
> ---
>  drivers/net/phy/phylink.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
> index 066684b8091..566852815e0 100644
> --- a/drivers/net/phy/phylink.c
> +++ b/drivers/net/phy/phylink.c
> @@ -609,8 +609,10 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
>  	const char *managed;
>  
>  	dn = fwnode_get_named_child_node(fwnode, "fixed-link");
> -	if (dn || fwnode_property_present(fwnode, "fixed-link"))
> +	if (dn || fwnode_property_present(fwnode, "fixed-link")) {
>  		pl->cfg_link_an_mode = MLO_AN_FIXED;
> +		pl->config->ovr_an_inband = false;
> +	}

ovr_an_inband was added to support "non-DT" platforms, and the only
place it's set is stmmac. I don't see why you'd want a driver to always
set this member, and then have phylink clear it - the driver should be
setting it correctly itself, otherwise it becomes a "maybe override AN
inband if certain conditions are met" flag inside phylink.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

^ permalink raw reply	[flat|nested] 24+ messages in thread
* Re: [PATCH net-next v2 4/6] net: phylink: unset ovr_an_inband if fixed-link is selected
@ 2022-06-10  7:31     ` Russell King (Oracle)
  0 siblings, 0 replies; 24+ messages in thread
From: Russell King (Oracle) @ 2022-06-10  7:31 UTC (permalink / raw)
  To: Ong Boon Leong
  Cc: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Paolo Abeni, David S . Miller, Eric Dumazet, Jakub Kicinski,
	Vladimir Oltean, Vivien Didelot, Florian Fainelli,
	Maxime Coquelin, Giuseppe Cavallaro, netdev, linux-stm32,
	linux-arm-kernel, linux-kernel, Emilio Riva

On Fri, Jun 10, 2022 at 11:29:39AM +0800, Ong Boon Leong wrote:
> If "fixed-link" DT or ACPI _DSD subnode is selected, it should take
> precedence over the value of ovr_an_inband passed by MAC driver.
> 
> Fixes: ab39385021d1 ("net: phylink: make phylink_parse_mode() support non-DT platform")
> Tested-by: Emilio Riva <emilio.riva@ericsson.com>
> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
> ---
>  drivers/net/phy/phylink.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
> index 066684b8091..566852815e0 100644
> --- a/drivers/net/phy/phylink.c
> +++ b/drivers/net/phy/phylink.c
> @@ -609,8 +609,10 @@ static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
>  	const char *managed;
>  
>  	dn = fwnode_get_named_child_node(fwnode, "fixed-link");
> -	if (dn || fwnode_property_present(fwnode, "fixed-link"))
> +	if (dn || fwnode_property_present(fwnode, "fixed-link")) {
>  		pl->cfg_link_an_mode = MLO_AN_FIXED;
> +		pl->config->ovr_an_inband = false;
> +	}

ovr_an_inband was added to support "non-DT" platforms, and the only
place it's set is stmmac. I don't see why you'd want a driver to always
set this member, and then have phylink clear it - the driver should be
setting it correctly itself, otherwise it becomes a "maybe override AN
inband if certain conditions are met" flag inside phylink.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 24+ messages in thread
* RE: [PATCH net-next v2 3/6] net: pcs: xpcs: add CL37 1000BASE-X AN support
  2022-06-10  7:26     ` Russell King (Oracle)
@ 2022-06-13 23:44       ` Ong, Boon Leong
  -1 siblings, 0 replies; 24+ messages in thread
From: Ong, Boon Leong @ 2022-06-13 23:44 UTC (permalink / raw)
  To: Russell King
  Cc: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Paolo Abeni, David S . Miller, Eric Dumazet, Jakub Kicinski,
	Vladimir Oltean, Vivien Didelot, Florian Fainelli,
	Maxime Coquelin, Giuseppe Cavallaro, netdev, linux-stm32,
	linux-arm-kernel, linux-kernel, Riva, Emilio

>> +static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
>> +					struct phylink_link_state *state)
>> +{
>> +	int lpa, adv;
>> +	int ret;
>> +
>> +	if (state->an_enabled) {
>> +		/* Reset link state */
>> +		state->link = false;
>> +
>> +		lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
>> +		if (lpa < 0 || lpa & LPA_RFAULT)
>> +			return lpa;
>> +
>> +		adv = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
>> +		if (adv < 0)
>> +			return adv;
>> +
>> +		if (lpa & ADVERTISE_1000XFULL &&
>> +		    adv & ADVERTISE_1000XFULL) {
>> +			state->link = true;
>> +			state->speed = SPEED_1000;
>> +			state->duplex = DUPLEX_FULL;
>> +		}
>
>phylink_mii_c22_pcs_decode_state() is your friend here, will implement
>this correctly, and will set lp_advertising correctly as well.
Thank for the suggestion. I will change it accordingly to use
phylink_mii_c22_pcs_decode_state()

>
>> +
>> +		/* Clear CL37 AN complete status */
>> +		ret = xpcs_write(xpcs, MDIO_MMD_VEND2,
>DW_VR_MII_AN_INTR_STS, 0);
>> +		if (ret < 0)
>> +			return ret;
>
>Why do you need to clear the interrupt status here? This function will
>be called from a work queue sometime later after an interrupt has fired.
>It will also be called at random times when userspace enquires what the
>link parameters are, so clearing the interrupt here can result in lost
>link changes.
Thanks for pointing it. Ya, it is unnecessary.

>
>> +static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, int speed,
>> +				   int duplex)
>> +{
>> +	int val, ret;
>> +
>> +	switch (speed) {
>> +	case SPEED_1000:
>> +		val = BMCR_SPEED1000;
>> +		break;
>> +	case SPEED_100:
>> +	case SPEED_10:
>> +	default:
>> +		pr_err("%s: speed = %d\n", __func__, speed);
>> +		return;
>> +	}
>> +
>> +	if (duplex == DUPLEX_FULL)
>> +		val |= BMCR_FULLDPLX;
>> +	else
>> +		pr_err("%s: half duplex not supported\n", __func__);
>> +
>> +	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
>> +	if (ret)
>> +		pr_err("%s: xpcs_write returned %pe\n", __func__,
>ERR_PTR(ret));
>
>Does this need to be done even when AN is enabled?
Thanks. Ya, it does not need. Will fix. 


>
>--
>RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
>FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

^ permalink raw reply	[flat|nested] 24+ messages in thread
* RE: [PATCH net-next v2 3/6] net: pcs: xpcs: add CL37 1000BASE-X AN support
@ 2022-06-13 23:44       ` Ong, Boon Leong
  0 siblings, 0 replies; 24+ messages in thread
From: Ong, Boon Leong @ 2022-06-13 23:44 UTC (permalink / raw)
  To: Russell King
  Cc: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Paolo Abeni, David S . Miller, Eric Dumazet, Jakub Kicinski,
	Vladimir Oltean, Vivien Didelot, Florian Fainelli,
	Maxime Coquelin, Giuseppe Cavallaro, netdev, linux-stm32,
	linux-arm-kernel, linux-kernel, Riva, Emilio

>> +static int xpcs_get_state_c37_1000basex(struct dw_xpcs *xpcs,
>> +					struct phylink_link_state *state)
>> +{
>> +	int lpa, adv;
>> +	int ret;
>> +
>> +	if (state->an_enabled) {
>> +		/* Reset link state */
>> +		state->link = false;
>> +
>> +		lpa = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_LPA);
>> +		if (lpa < 0 || lpa & LPA_RFAULT)
>> +			return lpa;
>> +
>> +		adv = xpcs_read(xpcs, MDIO_MMD_VEND2, MII_ADVERTISE);
>> +		if (adv < 0)
>> +			return adv;
>> +
>> +		if (lpa & ADVERTISE_1000XFULL &&
>> +		    adv & ADVERTISE_1000XFULL) {
>> +			state->link = true;
>> +			state->speed = SPEED_1000;
>> +			state->duplex = DUPLEX_FULL;
>> +		}
>
>phylink_mii_c22_pcs_decode_state() is your friend here, will implement
>this correctly, and will set lp_advertising correctly as well.
Thank for the suggestion. I will change it accordingly to use
phylink_mii_c22_pcs_decode_state()

>
>> +
>> +		/* Clear CL37 AN complete status */
>> +		ret = xpcs_write(xpcs, MDIO_MMD_VEND2,
>DW_VR_MII_AN_INTR_STS, 0);
>> +		if (ret < 0)
>> +			return ret;
>
>Why do you need to clear the interrupt status here? This function will
>be called from a work queue sometime later after an interrupt has fired.
>It will also be called at random times when userspace enquires what the
>link parameters are, so clearing the interrupt here can result in lost
>link changes.
Thanks for pointing it. Ya, it is unnecessary.

>
>> +static void xpcs_link_up_1000basex(struct dw_xpcs *xpcs, int speed,
>> +				   int duplex)
>> +{
>> +	int val, ret;
>> +
>> +	switch (speed) {
>> +	case SPEED_1000:
>> +		val = BMCR_SPEED1000;
>> +		break;
>> +	case SPEED_100:
>> +	case SPEED_10:
>> +	default:
>> +		pr_err("%s: speed = %d\n", __func__, speed);
>> +		return;
>> +	}
>> +
>> +	if (duplex == DUPLEX_FULL)
>> +		val |= BMCR_FULLDPLX;
>> +	else
>> +		pr_err("%s: half duplex not supported\n", __func__);
>> +
>> +	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, MDIO_CTRL1, val);
>> +	if (ret)
>> +		pr_err("%s: xpcs_write returned %pe\n", __func__,
>ERR_PTR(ret));
>
>Does this need to be done even when AN is enabled?
Thanks. Ya, it does not need. Will fix. 


>
>--
>RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
>FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

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^ permalink raw reply	[flat|nested] 24+ messages in thread
* RE: [PATCH net-next v2 4/6] net: phylink: unset ovr_an_inband if fixed-link is selected
  2022-06-10  7:31     ` Russell King (Oracle)
@ 2022-06-14  1:54       ` Ong, Boon Leong
  -1 siblings, 0 replies; 24+ messages in thread
From: Ong, Boon Leong @ 2022-06-14  1:54 UTC (permalink / raw)
  To: Russell King
  Cc: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Paolo Abeni, David S . Miller, Eric Dumazet, Jakub Kicinski,
	Vladimir Oltean, Vivien Didelot, Florian Fainelli,
	Maxime Coquelin, Giuseppe Cavallaro, netdev, linux-stm32,
	linux-arm-kernel, linux-kernel, Riva, Emilio

>On Fri, Jun 10, 2022 at 11:29:39AM +0800, Ong Boon Leong wrote:
>> If "fixed-link" DT or ACPI _DSD subnode is selected, it should take
>> precedence over the value of ovr_an_inband passed by MAC driver.
>>
>> Fixes: ab39385021d1 ("net: phylink: make phylink_parse_mode() support
>non-DT platform")
>> Tested-by: Emilio Riva <emilio.riva@ericsson.com>
>> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
>> ---
>>  drivers/net/phy/phylink.c | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
>> index 066684b8091..566852815e0 100644
>> --- a/drivers/net/phy/phylink.c
>> +++ b/drivers/net/phy/phylink.c
>> @@ -609,8 +609,10 @@ static int phylink_parse_mode(struct phylink *pl,
>struct fwnode_handle *fwnode)
>>  	const char *managed;
>>
>>  	dn = fwnode_get_named_child_node(fwnode, "fixed-link");
>> -	if (dn || fwnode_property_present(fwnode, "fixed-link"))
>> +	if (dn || fwnode_property_present(fwnode, "fixed-link")) {
>>  		pl->cfg_link_an_mode = MLO_AN_FIXED;
>> +		pl->config->ovr_an_inband = false;
>> +	}
>
>ovr_an_inband was added to support "non-DT" platforms, and the only
>place it's set is stmmac. I don't see why you'd want a driver to always
>set this member, and then have phylink clear it - the driver should be
>setting it correctly itself, otherwise it becomes a "maybe override AN
>inband if certain conditions are met" flag inside phylink.
Good point. Will make the "ovr_an_inband" not set inside the dwmac-intel
if fixed-link is used. 



^ permalink raw reply	[flat|nested] 24+ messages in thread
* RE: [PATCH net-next v2 4/6] net: phylink: unset ovr_an_inband if fixed-link is selected
@ 2022-06-14  1:54       ` Ong, Boon Leong
  0 siblings, 0 replies; 24+ messages in thread
From: Ong, Boon Leong @ 2022-06-14  1:54 UTC (permalink / raw)
  To: Russell King
  Cc: Alexandre Torgue, Jose Abreu, Andrew Lunn, Heiner Kallweit,
	Paolo Abeni, David S . Miller, Eric Dumazet, Jakub Kicinski,
	Vladimir Oltean, Vivien Didelot, Florian Fainelli,
	Maxime Coquelin, Giuseppe Cavallaro, netdev, linux-stm32,
	linux-arm-kernel, linux-kernel, Riva, Emilio

>On Fri, Jun 10, 2022 at 11:29:39AM +0800, Ong Boon Leong wrote:
>> If "fixed-link" DT or ACPI _DSD subnode is selected, it should take
>> precedence over the value of ovr_an_inband passed by MAC driver.
>>
>> Fixes: ab39385021d1 ("net: phylink: make phylink_parse_mode() support
>non-DT platform")
>> Tested-by: Emilio Riva <emilio.riva@ericsson.com>
>> Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
>> ---
>>  drivers/net/phy/phylink.c | 4 +++-
>>  1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
>> index 066684b8091..566852815e0 100644
>> --- a/drivers/net/phy/phylink.c
>> +++ b/drivers/net/phy/phylink.c
>> @@ -609,8 +609,10 @@ static int phylink_parse_mode(struct phylink *pl,
>struct fwnode_handle *fwnode)
>>  	const char *managed;
>>
>>  	dn = fwnode_get_named_child_node(fwnode, "fixed-link");
>> -	if (dn || fwnode_property_present(fwnode, "fixed-link"))
>> +	if (dn || fwnode_property_present(fwnode, "fixed-link")) {
>>  		pl->cfg_link_an_mode = MLO_AN_FIXED;
>> +		pl->config->ovr_an_inband = false;
>> +	}
>
>ovr_an_inband was added to support "non-DT" platforms, and the only
>place it's set is stmmac. I don't see why you'd want a driver to always
>set this member, and then have phylink clear it - the driver should be
>setting it correctly itself, otherwise it becomes a "maybe override AN
>inband if certain conditions are met" flag inside phylink.
Good point. Will make the "ovr_an_inband" not set inside the dwmac-intel
if fixed-link is used. 



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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 24+ messages in thread
end of thread, other threads:[~2022-06-14  1:57 UTC | newest]

Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-10  3:29 [PATCH net-next v2 0/7] pcs-xpcs, stmmac: add 1000BASE-X AN for network switch Ong Boon Leong
2022-06-10  3:29 ` Ong Boon Leong
2022-06-10  3:29 ` [PATCH net-next v2 1/6] net: dsa: sja1105: update xpcs_do_config additional input Ong Boon Leong
2022-06-10  3:29   ` Ong Boon Leong
2022-06-10  3:29 ` [PATCH net-next v2 2/6] stmmac: intel: prepare to support 1000BASE-X phy interface setting Ong Boon Leong
2022-06-10  3:29   ` Ong Boon Leong
2022-06-10  3:29 ` [PATCH net-next v2 3/6] net: pcs: xpcs: add CL37 1000BASE-X AN support Ong Boon Leong
2022-06-10  3:29   ` Ong Boon Leong
2022-06-10  7:26   ` Russell King (Oracle)
2022-06-10  7:26     ` Russell King (Oracle)
2022-06-13 23:44     ` Ong, Boon Leong
2022-06-13 23:44       ` Ong, Boon Leong
2022-06-10  3:29 ` [PATCH net-next v2 4/6] net: phylink: unset ovr_an_inband if fixed-link is selected Ong Boon Leong
2022-06-10  3:29   ` Ong Boon Leong
2022-06-10  7:31   ` Russell King (Oracle)
2022-06-10  7:31     ` Russell King (Oracle)
2022-06-14  1:54     ` Ong, Boon Leong
2022-06-14  1:54       ` Ong, Boon Leong
2022-06-10  3:29 ` [PATCH net-next v2 5/6] stmmac: intel: add phy-mode ACPI _DSD setting support Ong Boon Leong
2022-06-10  3:29   ` Ong Boon Leong
2022-06-10  3:29 ` [PATCH net-next v2 6/6] net: stmmac: make mdio register skips PHY scanning for fixed-link Ong Boon Leong
2022-06-10  3:29   ` Ong Boon Leong
2022-06-10  3:37 ` [PATCH net-next v2 0/7] pcs-xpcs, stmmac: add 1000BASE-X AN for network switch Ong, Boon Leong
2022-06-10  3:37   ` Ong, Boon Leong

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