[Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel

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* [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c
@ 2022-06-15 12:47 Jani Nikula
  2022-06-15 12:47 ` [Intel-gfx] [PATCH 1/7] drm/i915/wm: move wm state verification to intel_pm.c Jani Nikula
                   ` (11 more replies)
  0 siblings, 12 replies; 18+ messages in thread
From: Jani Nikula @ 2022-06-15 12:47 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

The state verification and pipe config comparison/dumping are fairly
isolated pieces of code within intel_display.c. Move them to separate
files in a long overdue cleanup.

Jani Nikula (7):
  drm/i915/wm: move wm state verification to intel_pm.c
  drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.c
  drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings
  drm/i915/mpllb: move mpllb state check to intel_snps_phy.c
  drm/i915/display: split out modeset verification code
  drm/i915/display: split out pipe config compare to a separate file
  drm/i915/display: split out pipe config dump to a separate file

 drivers/gpu/drm/i915/Makefile                 |    3 +
 drivers/gpu/drm/i915/display/intel_display.c  | 1373 +----------------
 drivers/gpu/drm/i915/display/intel_display.h  |    3 +
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   88 ++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |    5 +
 .../drm/i915/display/intel_modeset_verify.c   |  247 +++
 .../drm/i915/display/intel_modeset_verify.h   |   21 +
 .../i915/display/intel_pipe_config_compare.c  |  581 +++++++
 .../i915/display/intel_pipe_config_compare.h  |   17 +
 .../drm/i915/display/intel_pipe_config_dump.c |  314 ++++
 .../drm/i915/display/intel_pipe_config_dump.h |   16 +
 drivers/gpu/drm/i915/display/intel_snps_phy.c |   43 +
 drivers/gpu/drm/i915/display/intel_snps_phy.h |    5 +-
 drivers/gpu/drm/i915/intel_pm.c               |  138 +-
 drivers/gpu/drm/i915/intel_pm.h               |   14 +-
 15 files changed, 1482 insertions(+), 1386 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_compare.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_compare.h
 create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.h

-- 
2.30.2


^ permalink raw reply	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 1/7] drm/i915/wm: move wm state verification to intel_pm.c
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
@ 2022-06-15 12:47 ` Jani Nikula
  2022-06-15 12:47 ` [Intel-gfx] [PATCH 2/7] drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.c Jani Nikula
                   ` (10 subsequent siblings)
  11 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2022-06-15 12:47 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

By moving wm state verification to intel_pm.c, we can make a bunch of
functions static, hiding the wm details better. Also declutter
intel_display.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 122 +---------------
 drivers/gpu/drm/i915/intel_pm.c              | 138 +++++++++++++++++--
 drivers/gpu/drm/i915/intel_pm.h              |  14 +-
 3 files changed, 132 insertions(+), 142 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7d9c8aeef686..17492f9f94ed 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6424,126 +6424,6 @@ static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
 	}
 }
 
-static void verify_wm_state(struct intel_crtc *crtc,
-			    struct intel_crtc_state *new_crtc_state)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct skl_hw_state {
-		struct skl_ddb_entry ddb[I915_MAX_PLANES];
-		struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
-		struct skl_pipe_wm wm;
-	} *hw;
-	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
-	int level, max_level = ilk_wm_max_level(dev_priv);
-	struct intel_plane *plane;
-	u8 hw_enabled_slices;
-
-	if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)
-		return;
-
-	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
-	if (!hw)
-		return;
-
-	skl_pipe_wm_get_hw_state(crtc, &hw->wm);
-
-	skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);
-
-	hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
-
-	if (DISPLAY_VER(dev_priv) >= 11 &&
-	    hw_enabled_slices != dev_priv->dbuf.enabled_slices)
-		drm_err(&dev_priv->drm,
-			"mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
-			dev_priv->dbuf.enabled_slices,
-			hw_enabled_slices);
-
-	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
-		const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
-		const struct skl_wm_level *hw_wm_level, *sw_wm_level;
-
-		/* Watermarks */
-		for (level = 0; level <= max_level; level++) {
-			hw_wm_level = &hw->wm.planes[plane->id].wm[level];
-			sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
-
-			if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
-				continue;
-
-			drm_err(&dev_priv->drm,
-				"[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name, level,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
-		}
-
-		hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
-		sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
-
-		if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
-			drm_err(&dev_priv->drm,
-				"[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
-		}
-
-		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
-		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
-
-		if (HAS_HW_SAGV_WM(dev_priv) &&
-		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
-			drm_err(&dev_priv->drm,
-				"[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
-		}
-
-		hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
-		sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
-
-		if (HAS_HW_SAGV_WM(dev_priv) &&
-		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
-			drm_err(&dev_priv->drm,
-				"[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
-				plane->base.base.id, plane->base.name,
-				sw_wm_level->enable,
-				sw_wm_level->blocks,
-				sw_wm_level->lines,
-				hw_wm_level->enable,
-				hw_wm_level->blocks,
-				hw_wm_level->lines);
-		}
-
-		/* DDB */
-		hw_ddb_entry = &hw->ddb[PLANE_CURSOR];
-		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
-
-		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
-			drm_err(&dev_priv->drm,
-				"[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
-				plane->base.base.id, plane->base.name,
-				sw_ddb_entry->start, sw_ddb_entry->end,
-				hw_ddb_entry->start, hw_ddb_entry->end);
-		}
-	}
-
-	kfree(hw);
-}
-
 static void
 verify_connector_state(struct intel_atomic_state *state,
 		       struct intel_crtc *crtc)
@@ -6836,7 +6716,7 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
 	if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
 		return;
 
-	verify_wm_state(crtc, new_crtc_state);
+	intel_wm_verify_state(crtc, new_crtc_state);
 	verify_connector_state(state, crtc);
 	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
 	verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5a61fc3f26c1..0ce65d3a0e79 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4368,9 +4368,9 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
 	skl_ddb_entry_init_from_hw(ddb_y, val);
 }
 
-void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
-			       struct skl_ddb_entry *ddb,
-			       struct skl_ddb_entry *ddb_y)
+static void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
+				      struct skl_ddb_entry *ddb,
+				      struct skl_ddb_entry *ddb_y)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum intel_display_power_domain power_domain;
@@ -4950,7 +4950,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
 	return data_rate;
 }
 
-const struct skl_wm_level *
+static const struct skl_wm_level *
 skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
 		   enum plane_id plane_id,
 		   int level)
@@ -4963,7 +4963,7 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
 	return &wm->wm[level];
 }
 
-const struct skl_wm_level *
+static const struct skl_wm_level *
 skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
 		   enum plane_id plane_id)
 {
@@ -5915,8 +5915,8 @@ void skl_write_cursor_wm(struct intel_plane *plane,
 	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
 }
 
-bool skl_wm_level_equals(const struct skl_wm_level *l1,
-			 const struct skl_wm_level *l2)
+static bool skl_wm_level_equals(const struct skl_wm_level *l1,
+				const struct skl_wm_level *l2)
 {
 	return l1->enable == l2->enable &&
 		l1->ignore_lines == l2->ignore_lines &&
@@ -6488,8 +6488,8 @@ static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
 	level->lines = REG_FIELD_GET(PLANE_WM_LINES_MASK, val);
 }
 
-void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
-			      struct skl_pipe_wm *out)
+static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
+				     struct skl_pipe_wm *out)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
@@ -7166,6 +7166,126 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
 		!(intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) & DISP_FBC_WM_DIS);
 }
 
+void intel_wm_verify_state(struct intel_crtc *crtc,
+			   struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct skl_hw_state {
+		struct skl_ddb_entry ddb[I915_MAX_PLANES];
+		struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
+		struct skl_pipe_wm wm;
+	} *hw;
+	const struct skl_pipe_wm *sw_wm = &new_crtc_state->wm.skl.optimal;
+	int level, max_level = ilk_wm_max_level(dev_priv);
+	struct intel_plane *plane;
+	u8 hw_enabled_slices;
+
+	if (DISPLAY_VER(dev_priv) < 9 || !new_crtc_state->hw.active)
+		return;
+
+	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
+	if (!hw)
+		return;
+
+	skl_pipe_wm_get_hw_state(crtc, &hw->wm);
+
+	skl_pipe_ddb_get_hw_state(crtc, hw->ddb, hw->ddb_y);
+
+	hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
+
+	if (DISPLAY_VER(dev_priv) >= 11 &&
+	    hw_enabled_slices != dev_priv->dbuf.enabled_slices)
+		drm_err(&dev_priv->drm,
+			"mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
+			dev_priv->dbuf.enabled_slices,
+			hw_enabled_slices);
+
+	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+		const struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
+		const struct skl_wm_level *hw_wm_level, *sw_wm_level;
+
+		/* Watermarks */
+		for (level = 0; level <= max_level; level++) {
+			hw_wm_level = &hw->wm.planes[plane->id].wm[level];
+			sw_wm_level = skl_plane_wm_level(sw_wm, plane->id, level);
+
+			if (skl_wm_level_equals(hw_wm_level, sw_wm_level))
+				continue;
+
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in WM%d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				plane->base.base.id, plane->base.name, level,
+				sw_wm_level->enable,
+				sw_wm_level->blocks,
+				sw_wm_level->lines,
+				hw_wm_level->enable,
+				hw_wm_level->blocks,
+				hw_wm_level->lines);
+		}
+
+		hw_wm_level = &hw->wm.planes[plane->id].trans_wm;
+		sw_wm_level = skl_plane_trans_wm(sw_wm, plane->id);
+
+		if (!skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				plane->base.base.id, plane->base.name,
+				sw_wm_level->enable,
+				sw_wm_level->blocks,
+				sw_wm_level->lines,
+				hw_wm_level->enable,
+				hw_wm_level->blocks,
+				hw_wm_level->lines);
+		}
+
+		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
+		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
+
+		if (HAS_HW_SAGV_WM(dev_priv) &&
+		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				plane->base.base.id, plane->base.name,
+				sw_wm_level->enable,
+				sw_wm_level->blocks,
+				sw_wm_level->lines,
+				hw_wm_level->enable,
+				hw_wm_level->blocks,
+				hw_wm_level->lines);
+		}
+
+		hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
+		sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
+
+		if (HAS_HW_SAGV_WM(dev_priv) &&
+		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				plane->base.base.id, plane->base.name,
+				sw_wm_level->enable,
+				sw_wm_level->blocks,
+				sw_wm_level->lines,
+				hw_wm_level->enable,
+				hw_wm_level->blocks,
+				hw_wm_level->lines);
+		}
+
+		/* DDB */
+		hw_ddb_entry = &hw->ddb[PLANE_CURSOR];
+		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb[PLANE_CURSOR];
+
+		if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in DDB (expected (%u,%u), found (%u,%u))\n",
+				plane->base.base.id, plane->base.name,
+				sw_ddb_entry->start, sw_ddb_entry->end,
+				hw_ddb_entry->start, hw_ddb_entry->end);
+		}
+	}
+
+	kfree(hw);
+}
+
 void intel_enable_ipc(struct drm_i915_private *dev_priv)
 {
 	u32 val;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 50604cf7398c..070630630f16 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -35,15 +35,12 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
 void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
+void intel_wm_verify_state(struct intel_crtc *crtc,
+			   struct intel_crtc_state *new_crtc_state);
 u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
-void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
-			       struct skl_ddb_entry *ddb_y,
-			       struct skl_ddb_entry *ddb_uv);
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
 			    const struct skl_ddb_entry *entry);
-void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
-			      struct skl_pipe_wm *out);
 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
 void skl_wm_sanitize(struct drm_i915_private *dev_priv);
@@ -51,13 +48,6 @@ bool intel_can_enable_sagv(struct drm_i915_private *dev_priv,
 			   const struct intel_bw_state *bw_state);
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
 void intel_sagv_post_plane_update(struct intel_atomic_state *state);
-const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm,
-					      enum plane_id plane_id,
-					      int level);
-const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm,
-					      enum plane_id plane_id);
-bool skl_wm_level_equals(const struct skl_wm_level *l1,
-			 const struct skl_wm_level *l2);
 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb,
 				 const struct skl_ddb_entry *entries,
 				 int num_entries, int ignore_idx);
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 2/7] drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.c
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
  2022-06-15 12:47 ` [Intel-gfx] [PATCH 1/7] drm/i915/wm: move wm state verification to intel_pm.c Jani Nikula
@ 2022-06-15 12:47 ` Jani Nikula
  2022-06-15 12:47 ` [Intel-gfx] [PATCH 3/7] drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings Jani Nikula
                   ` (9 subsequent siblings)
  11 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2022-06-15 12:47 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Keep the shared dpll implementation details together by moving the dpll
state verification to intel_dpll_mgr.c. Also declutter intel_display.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 94 +------------------
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 88 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_dpll_mgr.h |  5 +
 3 files changed, 95 insertions(+), 92 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 17492f9f94ed..ffceda77dea6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6582,85 +6582,6 @@ intel_verify_planes(struct intel_atomic_state *state)
 			     plane_state->uapi.visible);
 }
 
-static void
-verify_single_dpll_state(struct drm_i915_private *dev_priv,
-			 struct intel_shared_dpll *pll,
-			 struct intel_crtc *crtc,
-			 struct intel_crtc_state *new_crtc_state)
-{
-	struct intel_dpll_hw_state dpll_hw_state;
-	u8 pipe_mask;
-	bool active;
-
-	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
-
-	drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
-
-	active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
-
-	if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
-		I915_STATE_WARN(!pll->on && pll->active_mask,
-		     "pll in active use but not on in sw tracking\n");
-		I915_STATE_WARN(pll->on && !pll->active_mask,
-		     "pll is on but not used by any active pipe\n");
-		I915_STATE_WARN(pll->on != active,
-		     "pll on state mismatch (expected %i, found %i)\n",
-		     pll->on, active);
-	}
-
-	if (!crtc) {
-		I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask,
-				"more active pll users than references: 0x%x vs 0x%x\n",
-				pll->active_mask, pll->state.pipe_mask);
-
-		return;
-	}
-
-	pipe_mask = BIT(crtc->pipe);
-
-	if (new_crtc_state->hw.active)
-		I915_STATE_WARN(!(pll->active_mask & pipe_mask),
-				"pll active mismatch (expected pipe %c in active mask 0x%x)\n",
-				pipe_name(crtc->pipe), pll->active_mask);
-	else
-		I915_STATE_WARN(pll->active_mask & pipe_mask,
-				"pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
-				pipe_name(crtc->pipe), pll->active_mask);
-
-	I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),
-			"pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
-			pipe_mask, pll->state.pipe_mask);
-
-	I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
-					  &dpll_hw_state,
-					  sizeof(dpll_hw_state)),
-			"pll hw state mismatch\n");
-}
-
-static void
-verify_shared_dpll_state(struct intel_crtc *crtc,
-			 struct intel_crtc_state *old_crtc_state,
-			 struct intel_crtc_state *new_crtc_state)
-{
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-
-	if (new_crtc_state->shared_dpll)
-		verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll, crtc, new_crtc_state);
-
-	if (old_crtc_state->shared_dpll &&
-	    old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
-		u8 pipe_mask = BIT(crtc->pipe);
-		struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
-
-		I915_STATE_WARN(pll->active_mask & pipe_mask,
-				"pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
-				pipe_name(crtc->pipe), pll->active_mask);
-		I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,
-				"pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
-				pipe_name(crtc->pipe), pll->state.pipe_mask);
-	}
-}
-
 static void
 verify_mpllb_state(struct intel_atomic_state *state,
 		   struct intel_crtc_state *new_crtc_state)
@@ -6719,28 +6640,17 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
 	intel_wm_verify_state(crtc, new_crtc_state);
 	verify_connector_state(state, crtc);
 	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
-	verify_shared_dpll_state(crtc, old_crtc_state, new_crtc_state);
+	intel_shared_dpll_verify_state(crtc, old_crtc_state, new_crtc_state);
 	verify_mpllb_state(state, new_crtc_state);
 }
 
-static void
-verify_disabled_dpll_state(struct drm_i915_private *dev_priv)
-{
-	int i;
-
-	for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++)
-		verify_single_dpll_state(dev_priv,
-					 &dev_priv->dpll.shared_dplls[i],
-					 NULL, NULL);
-}
-
 static void
 intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
 			      struct intel_atomic_state *state)
 {
 	verify_encoder_state(dev_priv, state);
 	verify_connector_state(state, NULL);
-	verify_disabled_dpll_state(dev_priv);
+	intel_shared_dpll_verify_disabled(dev_priv);
 }
 
 int intel_modeset_all_pipes(struct intel_atomic_state *state)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 64708e874b13..535b08d9d50f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -4449,3 +4449,91 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
 			    hw_state->fp1);
 	}
 }
+
+static void
+verify_single_dpll_state(struct drm_i915_private *dev_priv,
+			 struct intel_shared_dpll *pll,
+			 struct intel_crtc *crtc,
+			 struct intel_crtc_state *new_crtc_state)
+{
+	struct intel_dpll_hw_state dpll_hw_state;
+	u8 pipe_mask;
+	bool active;
+
+	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
+
+	drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
+
+	active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
+
+	if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
+		I915_STATE_WARN(!pll->on && pll->active_mask,
+				"pll in active use but not on in sw tracking\n");
+		I915_STATE_WARN(pll->on && !pll->active_mask,
+				"pll is on but not used by any active pipe\n");
+		I915_STATE_WARN(pll->on != active,
+				"pll on state mismatch (expected %i, found %i)\n",
+				pll->on, active);
+	}
+
+	if (!crtc) {
+		I915_STATE_WARN(pll->active_mask & ~pll->state.pipe_mask,
+				"more active pll users than references: 0x%x vs 0x%x\n",
+				pll->active_mask, pll->state.pipe_mask);
+
+		return;
+	}
+
+	pipe_mask = BIT(crtc->pipe);
+
+	if (new_crtc_state->hw.active)
+		I915_STATE_WARN(!(pll->active_mask & pipe_mask),
+				"pll active mismatch (expected pipe %c in active mask 0x%x)\n",
+				pipe_name(crtc->pipe), pll->active_mask);
+	else
+		I915_STATE_WARN(pll->active_mask & pipe_mask,
+				"pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
+				pipe_name(crtc->pipe), pll->active_mask);
+
+	I915_STATE_WARN(!(pll->state.pipe_mask & pipe_mask),
+			"pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
+			pipe_mask, pll->state.pipe_mask);
+
+	I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
+					  &dpll_hw_state,
+					  sizeof(dpll_hw_state)),
+			"pll hw state mismatch\n");
+}
+
+void intel_shared_dpll_verify_state(struct intel_crtc *crtc,
+				    struct intel_crtc_state *old_crtc_state,
+				    struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+	if (new_crtc_state->shared_dpll)
+		verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll,
+					 crtc, new_crtc_state);
+
+	if (old_crtc_state->shared_dpll &&
+	    old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
+		u8 pipe_mask = BIT(crtc->pipe);
+		struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
+
+		I915_STATE_WARN(pll->active_mask & pipe_mask,
+				"pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
+				pipe_name(crtc->pipe), pll->active_mask);
+		I915_STATE_WARN(pll->state.pipe_mask & pipe_mask,
+				"pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
+				pipe_name(crtc->pipe), pll->state.pipe_mask);
+	}
+}
+
+void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915)
+{
+	int i;
+
+	for (i = 0; i < i915->dpll.num_shared_dpll; i++)
+		verify_single_dpll_state(i915, &i915->dpll.shared_dplls[i],
+					 NULL, NULL);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
index 02412bf7625c..97c333e525ce 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
@@ -368,4 +368,9 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
 bool intel_dpll_is_combophy(enum intel_dpll_id id);
 
+void intel_shared_dpll_verify_state(struct intel_crtc *crtc,
+				    struct intel_crtc_state *old_crtc_state,
+				    struct intel_crtc_state *new_crtc_state);
+void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915);
+
 #endif /* _INTEL_DPLL_MGR_H_ */
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 3/7] drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
  2022-06-15 12:47 ` [Intel-gfx] [PATCH 1/7] drm/i915/wm: move wm state verification to intel_pm.c Jani Nikula
  2022-06-15 12:47 ` [Intel-gfx] [PATCH 2/7] drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.c Jani Nikula
@ 2022-06-15 12:47 ` Jani Nikula
  2022-06-15 12:47 ` [Intel-gfx] [PATCH 4/7] drm/i915/mpllb: move mpllb state check to intel_snps_phy.c Jani Nikula
                   ` (8 subsequent siblings)
  11 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2022-06-15 12:47 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

The pipe_config_mismatch() function is primarily for logging comparison
results.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ffceda77dea6..064fa2391e85 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6601,14 +6601,12 @@ verify_mpllb_state(struct intel_atomic_state *state,
 	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
 	intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
 
-#define MPLLB_CHECK(name) do { \
-	if (mpllb_sw_state->name != mpllb_hw_state.name) { \
-		pipe_config_mismatch(false, crtc, "MPLLB:" __stringify(name), \
-				     "(expected 0x%08x, found 0x%08x)", \
-				     mpllb_sw_state->name, \
-				     mpllb_hw_state.name); \
-	} \
-} while (0)
+#define MPLLB_CHECK(__name)						\
+	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\
+			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
+			crtc->base.base.id, crtc->base.name,		\
+			__stringify(__name),				\
+			mpllb_sw_state->__name, mpllb_hw_state.__name)
 
 	MPLLB_CHECK(mpllb_cp);
 	MPLLB_CHECK(mpllb_div);
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 4/7] drm/i915/mpllb: move mpllb state check to intel_snps_phy.c
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
                   ` (2 preceding siblings ...)
  2022-06-15 12:47 ` [Intel-gfx] [PATCH 3/7] drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings Jani Nikula
@ 2022-06-15 12:47 ` Jani Nikula
  2022-06-15 12:47 ` [Intel-gfx] [PATCH 5/7] drm/i915/display: split out modeset verification code Jani Nikula
                   ` (7 subsequent siblings)
  11 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2022-06-15 12:47 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Keep the mpllb implementation details together in intel_snps_phy.c. Also
declutter intel_display.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 46 +------------------
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 43 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_snps_phy.h |  5 +-
 3 files changed, 48 insertions(+), 46 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 064fa2391e85..e0ed9425e0d3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6582,50 +6582,6 @@ intel_verify_planes(struct intel_atomic_state *state)
 			     plane_state->uapi.visible);
 }
 
-static void
-verify_mpllb_state(struct intel_atomic_state *state,
-		   struct intel_crtc_state *new_crtc_state)
-{
-	struct drm_i915_private *i915 = to_i915(state->base.dev);
-	struct intel_mpllb_state mpllb_hw_state = { 0 };
-	struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;
-	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
-	struct intel_encoder *encoder;
-
-	if (!IS_DG2(i915))
-		return;
-
-	if (!new_crtc_state->hw.active)
-		return;
-
-	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
-	intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
-
-#define MPLLB_CHECK(__name)						\
-	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\
-			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
-			crtc->base.base.id, crtc->base.name,		\
-			__stringify(__name),				\
-			mpllb_sw_state->__name, mpllb_hw_state.__name)
-
-	MPLLB_CHECK(mpllb_cp);
-	MPLLB_CHECK(mpllb_div);
-	MPLLB_CHECK(mpllb_div2);
-	MPLLB_CHECK(mpllb_fracn1);
-	MPLLB_CHECK(mpllb_fracn2);
-	MPLLB_CHECK(mpllb_sscen);
-	MPLLB_CHECK(mpllb_sscstep);
-
-	/*
-	 * ref_control is handled by the hardware/firemware and never
-	 * programmed by the software, but the proper values are supplied
-	 * in the bspec for verification purposes.
-	 */
-	MPLLB_CHECK(ref_control);
-
-#undef MPLLB_CHECK
-}
-
 static void
 intel_modeset_verify_crtc(struct intel_crtc *crtc,
 			  struct intel_atomic_state *state,
@@ -6639,7 +6595,7 @@ intel_modeset_verify_crtc(struct intel_crtc *crtc,
 	verify_connector_state(state, crtc);
 	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
 	intel_shared_dpll_verify_state(crtc, old_crtc_state, new_crtc_state);
-	verify_mpllb_state(state, new_crtc_state);
+	intel_mpllb_verify_state(state, new_crtc_state);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index b48f42f1832a..ae8792bbef58 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -813,3 +813,46 @@ int intel_snps_phy_check_hdmi_link_rate(int clock)
 
 	return MODE_CLOCK_RANGE;
 }
+
+void intel_mpllb_verify_state(struct intel_atomic_state *state,
+			      struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_i915_private *i915 = to_i915(state->base.dev);
+	struct intel_mpllb_state mpllb_hw_state = { 0 };
+	struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state;
+	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+	struct intel_encoder *encoder;
+
+	if (!IS_DG2(i915))
+		return;
+
+	if (!new_crtc_state->hw.active)
+		return;
+
+	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);
+	intel_mpllb_readout_hw_state(encoder, &mpllb_hw_state);
+
+#define MPLLB_CHECK(__name)						\
+	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\
+			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
+			crtc->base.base.id, crtc->base.name,		\
+			__stringify(__name),				\
+			mpllb_sw_state->__name, mpllb_hw_state.__name)
+
+	MPLLB_CHECK(mpllb_cp);
+	MPLLB_CHECK(mpllb_div);
+	MPLLB_CHECK(mpllb_div2);
+	MPLLB_CHECK(mpllb_fracn1);
+	MPLLB_CHECK(mpllb_fracn2);
+	MPLLB_CHECK(mpllb_sscen);
+	MPLLB_CHECK(mpllb_sscstep);
+
+	/*
+	 * ref_control is handled by the hardware/firemware and never
+	 * programmed by the software, but the proper values are supplied
+	 * in the bspec for verification purposes.
+	 */
+	MPLLB_CHECK(ref_control);
+
+#undef MPLLB_CHECK
+}
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.h b/drivers/gpu/drm/i915/display/intel_snps_phy.h
index 11dcd6deb070..aeb1dd098040 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.h
@@ -9,8 +9,9 @@
 #include <linux/types.h>
 
 struct drm_i915_private;
-struct intel_encoder;
+struct intel_atomic_state;
 struct intel_crtc_state;
+struct intel_encoder;
 struct intel_mpllb_state;
 enum phy;
 
@@ -31,5 +32,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
 int intel_snps_phy_check_hdmi_link_rate(int clock);
 void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
 				      const struct intel_crtc_state *crtc_state);
+void intel_mpllb_verify_state(struct intel_atomic_state *state,
+			      struct intel_crtc_state *new_crtc_state);
 
 #endif /* __INTEL_SNPS_PHY_H__ */
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 5/7] drm/i915/display: split out modeset verification code
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
                   ` (3 preceding siblings ...)
  2022-06-15 12:47 ` [Intel-gfx] [PATCH 4/7] drm/i915/mpllb: move mpllb state check to intel_snps_phy.c Jani Nikula
@ 2022-06-15 12:47 ` Jani Nikula
  2022-06-15 12:48 ` [Intel-gfx] [PATCH 6/7] drm/i915/display: split out pipe config compare to a separate file Jani Nikula
                   ` (6 subsequent siblings)
  11 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2022-06-15 12:47 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Add new file intel_modeset_verify.c for high level modeset verification
code to declutter intel_display.h. The new file is supposed to be about
crtc/encoder/connector verification; the state verification for very
specific functionality such as plls or wm should be placed next to the
code it verifies.

Fix some minor checkpatch issues while at it.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_display.c  | 243 +----------------
 drivers/gpu/drm/i915/display/intel_display.h  |   9 +
 .../drm/i915/display/intel_modeset_verify.c   | 245 ++++++++++++++++++
 .../drm/i915/display/intel_modeset_verify.h   |  21 ++
 5 files changed, 284 insertions(+), 235 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d2b18f03a33c..e4f008e9ace9 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -242,6 +242,7 @@ i915-y += \
 	display/intel_hdcp.o \
 	display/intel_hotplug.o \
 	display/intel_lpe_audio.o \
+	display/intel_modeset_verify.o \
 	display/intel_overlay.o \
 	display/intel_pch_display.o \
 	display/intel_pch_refclk.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e0ed9425e0d3..be91a9afdf36 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -99,6 +99,7 @@
 #include "intel_frontbuffer.h"
 #include "intel_hdcp.h"
 #include "intel_hotplug.h"
+#include "intel_modeset_verify.h"
 #include "intel_overlay.h"
 #include "intel_panel.h"
 #include "intel_pch_display.h"
@@ -2529,45 +2530,6 @@ void intel_encoder_destroy(struct drm_encoder *encoder)
 	kfree(intel_encoder);
 }
 
-/* Cross check the actual hw state with our own modeset state tracking (and it's
- * internal consistency). */
-static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
-					 struct drm_connector_state *conn_state)
-{
-	struct intel_connector *connector = to_intel_connector(conn_state->connector);
-	struct drm_i915_private *i915 = to_i915(connector->base.dev);
-
-	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
-		    connector->base.base.id, connector->base.name);
-
-	if (connector->get_hw_state(connector)) {
-		struct intel_encoder *encoder = intel_attached_encoder(connector);
-
-		I915_STATE_WARN(!crtc_state,
-			 "connector enabled without attached crtc\n");
-
-		if (!crtc_state)
-			return;
-
-		I915_STATE_WARN(!crtc_state->hw.active,
-				"connector is active, but attached crtc isn't\n");
-
-		if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
-			return;
-
-		I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
-			"atomic encoder doesn't match attached encoder\n");
-
-		I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
-			"attached encoder crtc differs from connector crtc\n");
-	} else {
-		I915_STATE_WARN(crtc_state && crtc_state->hw.active,
-				"attached crtc is active, but connector isn't\n");
-		I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
-			"best encoder set without crtc!\n");
-	}
-}
-
 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
 {
 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2709,8 +2671,8 @@ static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state
 	intel_crtc_compute_pixel_rate(crtc_state);
 }
 
-static void intel_encoder_get_config(struct intel_encoder *encoder,
-				     struct intel_crtc_state *crtc_state)
+void intel_encoder_get_config(struct intel_encoder *encoder,
+			      struct intel_crtc_state *crtc_state)
 {
 	encoder->get_config(encoder, crtc_state);
 
@@ -4251,7 +4213,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
 	return active;
 }
 
-static bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
+bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -5230,9 +5192,9 @@ static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
 			    DRM_RECT_ARG(&plane_state->uapi.dst));
 }
 
-static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
-				   struct intel_atomic_state *state,
-				   const char *context)
+void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
+			    struct intel_atomic_state *state,
+			    const char *context)
 {
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -5982,7 +5944,7 @@ static bool fastboot_enabled(struct drm_i915_private *dev_priv)
 	return false;
 }
 
-static bool
+bool
 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 			  const struct intel_crtc_state *pipe_config,
 			  bool fastset)
@@ -6405,170 +6367,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	return ret;
 }
 
-static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
-					   const struct intel_crtc_state *pipe_config)
-{
-	if (pipe_config->has_pch_encoder) {
-		int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
-							    &pipe_config->fdi_m_n);
-		int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
-
-		/*
-		 * FDI already provided one idea for the dotclock.
-		 * Yell if the encoder disagrees.
-		 */
-		drm_WARN(&dev_priv->drm,
-			 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
-			 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
-			 fdi_dotclock, dotclock);
-	}
-}
-
-static void
-verify_connector_state(struct intel_atomic_state *state,
-		       struct intel_crtc *crtc)
-{
-	struct drm_connector *connector;
-	struct drm_connector_state *new_conn_state;
-	int i;
-
-	for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
-		struct drm_encoder *encoder = connector->encoder;
-		struct intel_crtc_state *crtc_state = NULL;
-
-		if (new_conn_state->crtc != &crtc->base)
-			continue;
-
-		if (crtc)
-			crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
-
-		intel_connector_verify_state(crtc_state, new_conn_state);
-
-		I915_STATE_WARN(new_conn_state->best_encoder != encoder,
-		     "connector's atomic encoder doesn't match legacy encoder\n");
-	}
-}
-
-static void
-verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
-{
-	struct intel_encoder *encoder;
-	struct drm_connector *connector;
-	struct drm_connector_state *old_conn_state, *new_conn_state;
-	int i;
-
-	for_each_intel_encoder(&dev_priv->drm, encoder) {
-		bool enabled = false, found = false;
-		enum pipe pipe;
-
-		drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
-			    encoder->base.base.id,
-			    encoder->base.name);
-
-		for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
-						   new_conn_state, i) {
-			if (old_conn_state->best_encoder == &encoder->base)
-				found = true;
-
-			if (new_conn_state->best_encoder != &encoder->base)
-				continue;
-			found = enabled = true;
-
-			I915_STATE_WARN(new_conn_state->crtc !=
-					encoder->base.crtc,
-			     "connector's crtc doesn't match encoder crtc\n");
-		}
-
-		if (!found)
-			continue;
-
-		I915_STATE_WARN(!!encoder->base.crtc != enabled,
-		     "encoder's enabled state mismatch "
-		     "(expected %i, found %i)\n",
-		     !!encoder->base.crtc, enabled);
-
-		if (!encoder->base.crtc) {
-			bool active;
-
-			active = encoder->get_hw_state(encoder, &pipe);
-			I915_STATE_WARN(active,
-			     "encoder detached but still enabled on pipe %c.\n",
-			     pipe_name(pipe));
-		}
-	}
-}
-
-static void
-verify_crtc_state(struct intel_crtc *crtc,
-		  struct intel_crtc_state *old_crtc_state,
-		  struct intel_crtc_state *new_crtc_state)
-{
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_encoder *encoder;
-	struct intel_crtc_state *pipe_config = old_crtc_state;
-	struct drm_atomic_state *state = old_crtc_state->uapi.state;
-	struct intel_crtc *master_crtc;
-
-	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
-	intel_crtc_free_hw_state(old_crtc_state);
-	intel_crtc_state_reset(old_crtc_state, crtc);
-	old_crtc_state->uapi.state = state;
-
-	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
-		    crtc->base.name);
-
-	pipe_config->hw.enable = new_crtc_state->hw.enable;
-
-	intel_crtc_get_pipe_config(pipe_config);
-
-	/* we keep both pipes enabled on 830 */
-	if (IS_I830(dev_priv) && pipe_config->hw.active)
-		pipe_config->hw.active = new_crtc_state->hw.active;
-
-	I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
-			"crtc active state doesn't match with hw state "
-			"(expected %i, found %i)\n",
-			new_crtc_state->hw.active, pipe_config->hw.active);
-
-	I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
-			"transitional active state does not match atomic hw state "
-			"(expected %i, found %i)\n",
-			new_crtc_state->hw.active, crtc->active);
-
-	master_crtc = intel_master_crtc(new_crtc_state);
-
-	for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) {
-		enum pipe pipe;
-		bool active;
-
-		active = encoder->get_hw_state(encoder, &pipe);
-		I915_STATE_WARN(active != new_crtc_state->hw.active,
-				"[ENCODER:%i] active %i with crtc active %i\n",
-				encoder->base.base.id, active,
-				new_crtc_state->hw.active);
-
-		I915_STATE_WARN(active && master_crtc->pipe != pipe,
-				"Encoder connected to wrong pipe %c\n",
-				pipe_name(pipe));
-
-		if (active)
-			intel_encoder_get_config(encoder, pipe_config);
-	}
-
-	if (!new_crtc_state->hw.active)
-		return;
-
-	intel_pipe_config_sanity_check(dev_priv, pipe_config);
-
-	if (!intel_pipe_config_compare(new_crtc_state,
-				       pipe_config, false)) {
-		I915_STATE_WARN(1, "pipe state doesn't match!\n");
-		intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
-		intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
-	}
-}
-
 static void
 intel_verify_planes(struct intel_atomic_state *state)
 {
@@ -6582,31 +6380,6 @@ intel_verify_planes(struct intel_atomic_state *state)
 			     plane_state->uapi.visible);
 }
 
-static void
-intel_modeset_verify_crtc(struct intel_crtc *crtc,
-			  struct intel_atomic_state *state,
-			  struct intel_crtc_state *old_crtc_state,
-			  struct intel_crtc_state *new_crtc_state)
-{
-	if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
-		return;
-
-	intel_wm_verify_state(crtc, new_crtc_state);
-	verify_connector_state(state, crtc);
-	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
-	intel_shared_dpll_verify_state(crtc, old_crtc_state, new_crtc_state);
-	intel_mpllb_verify_state(state, new_crtc_state);
-}
-
-static void
-intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
-			      struct intel_atomic_state *state)
-{
-	verify_encoder_state(dev_priv, state);
-	verify_connector_state(state, NULL);
-	intel_shared_dpll_verify_disabled(dev_priv);
-}
-
 int intel_modeset_all_pipes(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 7af6b5a413dc..70410eeb19c8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -559,6 +559,13 @@ bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state);
 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
+bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
+bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
+			       const struct intel_crtc_state *pipe_config,
+			       bool fastset);
+void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
+			    struct intel_atomic_state *state,
+			    const char *context);
 
 void intel_plane_destroy(struct drm_plane *plane);
 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
@@ -583,6 +590,8 @@ int intel_display_suspend(struct drm_device *dev);
 void intel_encoder_destroy(struct drm_encoder *encoder);
 struct drm_display_mode *
 intel_encoder_current_mode(struct intel_encoder *encoder);
+void intel_encoder_get_config(struct intel_encoder *encoder,
+			      struct intel_crtc_state *crtc_state);
 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy);
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy);
 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
new file mode 100644
index 000000000000..7a91c926598b
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -0,0 +1,245 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ *
+ * High level crtc/connector/encoder modeset state verification.
+ */
+
+#include <drm/drm_atomic_state_helper.h>
+
+#include "i915_drv.h"
+#include "intel_atomic.h"
+#include "intel_crtc.h"
+#include "intel_display.h"
+#include "intel_display_types.h"
+#include "intel_fdi.h"
+#include "intel_modeset_verify.h"
+#include "intel_pm.h"
+#include "intel_snps_phy.h"
+
+/*
+ * Cross check the actual hw state with our own modeset state tracking (and its
+ * internal consistency).
+ */
+static void intel_connector_verify_state(struct intel_crtc_state *crtc_state,
+					 struct drm_connector_state *conn_state)
+{
+	struct intel_connector *connector = to_intel_connector(conn_state->connector);
+	struct drm_i915_private *i915 = to_i915(connector->base.dev);
+
+	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
+		    connector->base.base.id, connector->base.name);
+
+	if (connector->get_hw_state(connector)) {
+		struct intel_encoder *encoder = intel_attached_encoder(connector);
+
+		I915_STATE_WARN(!crtc_state,
+				"connector enabled without attached crtc\n");
+
+		if (!crtc_state)
+			return;
+
+		I915_STATE_WARN(!crtc_state->hw.active,
+				"connector is active, but attached crtc isn't\n");
+
+		if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
+			return;
+
+		I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
+				"atomic encoder doesn't match attached encoder\n");
+
+		I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
+				"attached encoder crtc differs from connector crtc\n");
+	} else {
+		I915_STATE_WARN(crtc_state && crtc_state->hw.active,
+				"attached crtc is active, but connector isn't\n");
+		I915_STATE_WARN(!crtc_state && conn_state->best_encoder,
+				"best encoder set without crtc!\n");
+	}
+}
+
+static void
+verify_connector_state(struct intel_atomic_state *state,
+		       struct intel_crtc *crtc)
+{
+	struct drm_connector *connector;
+	struct drm_connector_state *new_conn_state;
+	int i;
+
+	for_each_new_connector_in_state(&state->base, connector, new_conn_state, i) {
+		struct drm_encoder *encoder = connector->encoder;
+		struct intel_crtc_state *crtc_state = NULL;
+
+		if (new_conn_state->crtc != &crtc->base)
+			continue;
+
+		if (crtc)
+			crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+		intel_connector_verify_state(crtc_state, new_conn_state);
+
+		I915_STATE_WARN(new_conn_state->best_encoder != encoder,
+				"connector's atomic encoder doesn't match legacy encoder\n");
+	}
+}
+
+static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
+					   const struct intel_crtc_state *pipe_config)
+{
+	if (pipe_config->has_pch_encoder) {
+		int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
+							    &pipe_config->fdi_m_n);
+		int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
+
+		/*
+		 * FDI already provided one idea for the dotclock.
+		 * Yell if the encoder disagrees.
+		 */
+		drm_WARN(&dev_priv->drm,
+			 !intel_fuzzy_clock_check(fdi_dotclock, dotclock),
+			 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
+			 fdi_dotclock, dotclock);
+	}
+}
+
+static void
+verify_encoder_state(struct drm_i915_private *dev_priv, struct intel_atomic_state *state)
+{
+	struct intel_encoder *encoder;
+	struct drm_connector *connector;
+	struct drm_connector_state *old_conn_state, *new_conn_state;
+	int i;
+
+	for_each_intel_encoder(&dev_priv->drm, encoder) {
+		bool enabled = false, found = false;
+		enum pipe pipe;
+
+		drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s]\n",
+			    encoder->base.base.id,
+			    encoder->base.name);
+
+		for_each_oldnew_connector_in_state(&state->base, connector, old_conn_state,
+						   new_conn_state, i) {
+			if (old_conn_state->best_encoder == &encoder->base)
+				found = true;
+
+			if (new_conn_state->best_encoder != &encoder->base)
+				continue;
+
+			found = true;
+			enabled = true;
+
+			I915_STATE_WARN(new_conn_state->crtc !=
+					encoder->base.crtc,
+					"connector's crtc doesn't match encoder crtc\n");
+		}
+
+		if (!found)
+			continue;
+
+		I915_STATE_WARN(!!encoder->base.crtc != enabled,
+				"encoder's enabled state mismatch (expected %i, found %i)\n",
+				!!encoder->base.crtc, enabled);
+
+		if (!encoder->base.crtc) {
+			bool active;
+
+			active = encoder->get_hw_state(encoder, &pipe);
+			I915_STATE_WARN(active,
+					"encoder detached but still enabled on pipe %c.\n",
+					pipe_name(pipe));
+		}
+	}
+}
+
+static void
+verify_crtc_state(struct intel_crtc *crtc,
+		  struct intel_crtc_state *old_crtc_state,
+		  struct intel_crtc_state *new_crtc_state)
+{
+	struct drm_device *dev = crtc->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_encoder *encoder;
+	struct intel_crtc_state *pipe_config = old_crtc_state;
+	struct drm_atomic_state *state = old_crtc_state->uapi.state;
+	struct intel_crtc *master_crtc;
+
+	__drm_atomic_helper_crtc_destroy_state(&old_crtc_state->uapi);
+	intel_crtc_free_hw_state(old_crtc_state);
+	intel_crtc_state_reset(old_crtc_state, crtc);
+	old_crtc_state->uapi.state = state;
+
+	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s]\n", crtc->base.base.id,
+		    crtc->base.name);
+
+	pipe_config->hw.enable = new_crtc_state->hw.enable;
+
+	intel_crtc_get_pipe_config(pipe_config);
+
+	/* we keep both pipes enabled on 830 */
+	if (IS_I830(dev_priv) && pipe_config->hw.active)
+		pipe_config->hw.active = new_crtc_state->hw.active;
+
+	I915_STATE_WARN(new_crtc_state->hw.active != pipe_config->hw.active,
+			"crtc active state doesn't match with hw state (expected %i, found %i)\n",
+			new_crtc_state->hw.active, pipe_config->hw.active);
+
+	I915_STATE_WARN(crtc->active != new_crtc_state->hw.active,
+			"transitional active state does not match atomic hw state (expected %i, found %i)\n",
+			new_crtc_state->hw.active, crtc->active);
+
+	master_crtc = intel_master_crtc(new_crtc_state);
+
+	for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) {
+		enum pipe pipe;
+		bool active;
+
+		active = encoder->get_hw_state(encoder, &pipe);
+		I915_STATE_WARN(active != new_crtc_state->hw.active,
+				"[ENCODER:%i] active %i with crtc active %i\n",
+				encoder->base.base.id, active,
+				new_crtc_state->hw.active);
+
+		I915_STATE_WARN(active && master_crtc->pipe != pipe,
+				"Encoder connected to wrong pipe %c\n",
+				pipe_name(pipe));
+
+		if (active)
+			intel_encoder_get_config(encoder, pipe_config);
+	}
+
+	if (!new_crtc_state->hw.active)
+		return;
+
+	intel_pipe_config_sanity_check(dev_priv, pipe_config);
+
+	if (!intel_pipe_config_compare(new_crtc_state,
+				       pipe_config, false)) {
+		I915_STATE_WARN(1, "pipe state doesn't match!\n");
+		intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
+		intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
+	}
+}
+
+void intel_modeset_verify_crtc(struct intel_crtc *crtc,
+			       struct intel_atomic_state *state,
+			       struct intel_crtc_state *old_crtc_state,
+			       struct intel_crtc_state *new_crtc_state)
+{
+	if (!intel_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->update_pipe)
+		return;
+
+	intel_wm_verify_state(crtc, new_crtc_state);
+	verify_connector_state(state, crtc);
+	verify_crtc_state(crtc, old_crtc_state, new_crtc_state);
+	intel_shared_dpll_verify_state(crtc, old_crtc_state, new_crtc_state);
+	intel_mpllb_verify_state(state, new_crtc_state);
+}
+
+void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
+				   struct intel_atomic_state *state)
+{
+	verify_encoder_state(dev_priv, state);
+	verify_connector_state(state, NULL);
+	intel_shared_dpll_verify_disabled(dev_priv);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.h b/drivers/gpu/drm/i915/display/intel_modeset_verify.h
new file mode 100644
index 000000000000..2d6fbe4f7846
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_MODESET_VERIFY_H__
+#define __INTEL_MODESET_VERIFY_H__
+
+struct drm_i915_private;
+struct intel_atomic_state;
+struct intel_crtc;
+struct intel_crtc_state;
+
+void intel_modeset_verify_crtc(struct intel_crtc *crtc,
+			       struct intel_atomic_state *state,
+			       struct intel_crtc_state *old_crtc_state,
+			       struct intel_crtc_state *new_crtc_state);
+void intel_modeset_verify_disabled(struct drm_i915_private *dev_priv,
+				   struct intel_atomic_state *state);
+
+#endif /* __INTEL_MODESET_VERIFY_H__ */
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 6/7] drm/i915/display: split out pipe config compare to a separate file
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
                   ` (4 preceding siblings ...)
  2022-06-15 12:47 ` [Intel-gfx] [PATCH 5/7] drm/i915/display: split out modeset verification code Jani Nikula
@ 2022-06-15 12:48 ` Jani Nikula
  2022-06-15 12:48 ` [Intel-gfx] [PATCH 7/7] drm/i915/display: split out pipe config dump " Jani Nikula
                   ` (5 subsequent siblings)
  11 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2022-06-15 12:48 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Declutter intel_display.c by splitting out pipe config comparison to a
separate file.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_display.c  | 571 +----------------
 drivers/gpu/drm/i915/display/intel_display.h  |   3 -
 .../drm/i915/display/intel_modeset_verify.c   |   1 +
 .../i915/display/intel_pipe_config_compare.c  | 581 ++++++++++++++++++
 .../i915/display/intel_pipe_config_compare.h  |  17 +
 6 files changed, 601 insertions(+), 573 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_compare.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_compare.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e4f008e9ace9..8b4e5c59ee70 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -246,6 +246,7 @@ i915-y += \
 	display/intel_overlay.o \
 	display/intel_pch_display.o \
 	display/intel_pch_refclk.o \
+	display/intel_pipe_config_compare.o \
 	display/intel_plane_initial.o \
 	display/intel_psr.o \
 	display/intel_quirks.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index be91a9afdf36..093ba6bde105 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -105,6 +105,7 @@
 #include "intel_pch_display.h"
 #include "intel_pch_refclk.h"
 #include "intel_pcode.h"
+#include "intel_pipe_config_compare.h"
 #include "intel_pipe_crc.h"
 #include "intel_plane_initial.h"
 #include "intel_pm.h"
@@ -5797,576 +5798,6 @@ bool intel_fuzzy_clock_check(int clock1, int clock2)
 	return false;
 }
 
-static bool
-intel_compare_m_n(unsigned int m, unsigned int n,
-		  unsigned int m2, unsigned int n2,
-		  bool exact)
-{
-	if (m == m2 && n == n2)
-		return true;
-
-	if (exact || !m || !n || !m2 || !n2)
-		return false;
-
-	BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
-
-	if (n > n2) {
-		while (n > n2) {
-			m2 <<= 1;
-			n2 <<= 1;
-		}
-	} else if (n < n2) {
-		while (n < n2) {
-			m <<= 1;
-			n <<= 1;
-		}
-	}
-
-	if (n != n2)
-		return false;
-
-	return intel_fuzzy_clock_check(m, m2);
-}
-
-static bool
-intel_compare_link_m_n(const struct intel_link_m_n *m_n,
-		       const struct intel_link_m_n *m2_n2,
-		       bool exact)
-{
-	return m_n->tu == m2_n2->tu &&
-		intel_compare_m_n(m_n->data_m, m_n->data_n,
-				  m2_n2->data_m, m2_n2->data_n, exact) &&
-		intel_compare_m_n(m_n->link_m, m_n->link_n,
-				  m2_n2->link_m, m2_n2->link_n, exact);
-}
-
-static bool
-intel_compare_infoframe(const union hdmi_infoframe *a,
-			const union hdmi_infoframe *b)
-{
-	return memcmp(a, b, sizeof(*a)) == 0;
-}
-
-static bool
-intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
-			 const struct drm_dp_vsc_sdp *b)
-{
-	return memcmp(a, b, sizeof(*a)) == 0;
-}
-
-static void
-pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
-			       bool fastset, const char *name,
-			       const union hdmi_infoframe *a,
-			       const union hdmi_infoframe *b)
-{
-	if (fastset) {
-		if (!drm_debug_enabled(DRM_UT_KMS))
-			return;
-
-		drm_dbg_kms(&dev_priv->drm,
-			    "fastset mismatch in %s infoframe\n", name);
-		drm_dbg_kms(&dev_priv->drm, "expected:\n");
-		hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
-		drm_dbg_kms(&dev_priv->drm, "found:\n");
-		hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
-	} else {
-		drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
-		drm_err(&dev_priv->drm, "expected:\n");
-		hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
-		drm_err(&dev_priv->drm, "found:\n");
-		hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
-	}
-}
-
-static void
-pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
-				bool fastset, const char *name,
-				const struct drm_dp_vsc_sdp *a,
-				const struct drm_dp_vsc_sdp *b)
-{
-	if (fastset) {
-		if (!drm_debug_enabled(DRM_UT_KMS))
-			return;
-
-		drm_dbg_kms(&dev_priv->drm,
-			    "fastset mismatch in %s dp sdp\n", name);
-		drm_dbg_kms(&dev_priv->drm, "expected:\n");
-		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
-		drm_dbg_kms(&dev_priv->drm, "found:\n");
-		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
-	} else {
-		drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
-		drm_err(&dev_priv->drm, "expected:\n");
-		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
-		drm_err(&dev_priv->drm, "found:\n");
-		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
-	}
-}
-
-static void __printf(4, 5)
-pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
-		     const char *name, const char *format, ...)
-{
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
-	struct va_format vaf;
-	va_list args;
-
-	va_start(args, format);
-	vaf.fmt = format;
-	vaf.va = &args;
-
-	if (fastset)
-		drm_dbg_kms(&i915->drm,
-			    "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
-			    crtc->base.base.id, crtc->base.name, name, &vaf);
-	else
-		drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
-			crtc->base.base.id, crtc->base.name, name, &vaf);
-
-	va_end(args);
-}
-
-static bool fastboot_enabled(struct drm_i915_private *dev_priv)
-{
-	if (dev_priv->params.fastboot != -1)
-		return dev_priv->params.fastboot;
-
-	/* Enable fastboot by default on Skylake and newer */
-	if (DISPLAY_VER(dev_priv) >= 9)
-		return true;
-
-	/* Enable fastboot by default on VLV and CHV */
-	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-		return true;
-
-	/* Disabled by default on all others */
-	return false;
-}
-
-bool
-intel_pipe_config_compare(const struct intel_crtc_state *current_config,
-			  const struct intel_crtc_state *pipe_config,
-			  bool fastset)
-{
-	struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
-	bool ret = true;
-	u32 bp_gamma = 0;
-	bool fixup_inherited = fastset &&
-		current_config->inherited && !pipe_config->inherited;
-
-	if (fixup_inherited && !fastboot_enabled(dev_priv)) {
-		drm_dbg_kms(&dev_priv->drm,
-			    "initial modeset and fastboot not set\n");
-		ret = false;
-	}
-
-#define PIPE_CONF_CHECK_X(name) do { \
-	if (current_config->name != pipe_config->name) { \
-		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "(expected 0x%08x, found 0x%08x)", \
-				     current_config->name, \
-				     pipe_config->name); \
-		ret = false; \
-	} \
-} while (0)
-
-#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
-	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
-		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "(expected 0x%08x, found 0x%08x)", \
-				     current_config->name & (mask), \
-				     pipe_config->name & (mask)); \
-		ret = false; \
-	} \
-} while (0)
-
-#define PIPE_CONF_CHECK_I(name) do { \
-	if (current_config->name != pipe_config->name) { \
-		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "(expected %i, found %i)", \
-				     current_config->name, \
-				     pipe_config->name); \
-		ret = false; \
-	} \
-} while (0)
-
-#define PIPE_CONF_CHECK_BOOL(name) do { \
-	if (current_config->name != pipe_config->name) { \
-		pipe_config_mismatch(fastset, crtc,  __stringify(name), \
-				     "(expected %s, found %s)", \
-				     str_yes_no(current_config->name), \
-				     str_yes_no(pipe_config->name)); \
-		ret = false; \
-	} \
-} while (0)
-
-/*
- * Checks state where we only read out the enabling, but not the entire
- * state itself (like full infoframes or ELD for audio). These states
- * require a full modeset on bootup to fix up.
- */
-#define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
-	if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
-		PIPE_CONF_CHECK_BOOL(name); \
-	} else { \
-		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
-				     str_yes_no(current_config->name), \
-				     str_yes_no(pipe_config->name)); \
-		ret = false; \
-	} \
-} while (0)
-
-#define PIPE_CONF_CHECK_P(name) do { \
-	if (current_config->name != pipe_config->name) { \
-		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "(expected %p, found %p)", \
-				     current_config->name, \
-				     pipe_config->name); \
-		ret = false; \
-	} \
-} while (0)
-
-#define PIPE_CONF_CHECK_M_N(name) do { \
-	if (!intel_compare_link_m_n(&current_config->name, \
-				    &pipe_config->name,\
-				    !fastset)) { \
-		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "(expected tu %i data %i/%i link %i/%i, " \
-				     "found tu %i, data %i/%i link %i/%i)", \
-				     current_config->name.tu, \
-				     current_config->name.data_m, \
-				     current_config->name.data_n, \
-				     current_config->name.link_m, \
-				     current_config->name.link_n, \
-				     pipe_config->name.tu, \
-				     pipe_config->name.data_m, \
-				     pipe_config->name.data_n, \
-				     pipe_config->name.link_m, \
-				     pipe_config->name.link_n); \
-		ret = false; \
-	} \
-} while (0)
-
-#define PIPE_CONF_CHECK_TIMINGS(name) do { \
-	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
-	PIPE_CONF_CHECK_I(name.crtc_htotal); \
-	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
-	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
-	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
-	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
-	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
-	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
-	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
-	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
-	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
-	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
-} while (0)
-
-#define PIPE_CONF_CHECK_RECT(name) do { \
-	PIPE_CONF_CHECK_I(name.x1); \
-	PIPE_CONF_CHECK_I(name.x2); \
-	PIPE_CONF_CHECK_I(name.y1); \
-	PIPE_CONF_CHECK_I(name.y2); \
-} while (0)
-
-/* This is required for BDW+ where there is only one set of registers for
- * switching between high and low RR.
- * This macro can be used whenever a comparison has to be made between one
- * hw state and multiple sw state variables.
- */
-#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
-	if (!intel_compare_link_m_n(&current_config->name, \
-				    &pipe_config->name, !fastset) && \
-	    !intel_compare_link_m_n(&current_config->alt_name, \
-				    &pipe_config->name, !fastset)) { \
-		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "(expected tu %i data %i/%i link %i/%i, " \
-				     "or tu %i data %i/%i link %i/%i, " \
-				     "found tu %i, data %i/%i link %i/%i)", \
-				     current_config->name.tu, \
-				     current_config->name.data_m, \
-				     current_config->name.data_n, \
-				     current_config->name.link_m, \
-				     current_config->name.link_n, \
-				     current_config->alt_name.tu, \
-				     current_config->alt_name.data_m, \
-				     current_config->alt_name.data_n, \
-				     current_config->alt_name.link_m, \
-				     current_config->alt_name.link_n, \
-				     pipe_config->name.tu, \
-				     pipe_config->name.data_m, \
-				     pipe_config->name.data_n, \
-				     pipe_config->name.link_m, \
-				     pipe_config->name.link_n); \
-		ret = false; \
-	} \
-} while (0)
-
-#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
-	if ((current_config->name ^ pipe_config->name) & (mask)) { \
-		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "(%x) (expected %i, found %i)", \
-				     (mask), \
-				     current_config->name & (mask), \
-				     pipe_config->name & (mask)); \
-		ret = false; \
-	} \
-} while (0)
-
-#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
-	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
-		pipe_config_mismatch(fastset, crtc, __stringify(name), \
-				     "(expected %i, found %i)", \
-				     current_config->name, \
-				     pipe_config->name); \
-		ret = false; \
-	} \
-} while (0)
-
-#define PIPE_CONF_CHECK_INFOFRAME(name) do { \
-	if (!intel_compare_infoframe(&current_config->infoframes.name, \
-				     &pipe_config->infoframes.name)) { \
-		pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
-					       &current_config->infoframes.name, \
-					       &pipe_config->infoframes.name); \
-		ret = false; \
-	} \
-} while (0)
-
-#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
-	if (!current_config->has_psr && !pipe_config->has_psr && \
-	    !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
-				      &pipe_config->infoframes.name)) { \
-		pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
-						&current_config->infoframes.name, \
-						&pipe_config->infoframes.name); \
-		ret = false; \
-	} \
-} while (0)
-
-#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
-	if (current_config->name1 != pipe_config->name1) { \
-		pipe_config_mismatch(fastset, crtc, __stringify(name1), \
-				"(expected %i, found %i, won't compare lut values)", \
-				current_config->name1, \
-				pipe_config->name1); \
-		ret = false;\
-	} else { \
-		if (!intel_color_lut_equal(current_config->name2, \
-					pipe_config->name2, pipe_config->name1, \
-					bit_precision)) { \
-			pipe_config_mismatch(fastset, crtc, __stringify(name2), \
-					"hw_state doesn't match sw_state"); \
-			ret = false; \
-		} \
-	} \
-} while (0)
-
-#define PIPE_CONF_QUIRK(quirk) \
-	((current_config->quirks | pipe_config->quirks) & (quirk))
-
-	PIPE_CONF_CHECK_I(hw.enable);
-	PIPE_CONF_CHECK_I(hw.active);
-
-	PIPE_CONF_CHECK_I(cpu_transcoder);
-	PIPE_CONF_CHECK_I(mst_master_transcoder);
-
-	PIPE_CONF_CHECK_BOOL(has_pch_encoder);
-	PIPE_CONF_CHECK_I(fdi_lanes);
-	PIPE_CONF_CHECK_M_N(fdi_m_n);
-
-	PIPE_CONF_CHECK_I(lane_count);
-	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
-
-	if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
-		PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
-	} else {
-		PIPE_CONF_CHECK_M_N(dp_m_n);
-		PIPE_CONF_CHECK_M_N(dp_m2_n2);
-	}
-
-	PIPE_CONF_CHECK_X(output_types);
-
-	PIPE_CONF_CHECK_I(framestart_delay);
-	PIPE_CONF_CHECK_I(msa_timing_delay);
-
-	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
-	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
-
-	PIPE_CONF_CHECK_I(pixel_multiplier);
-
-	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
-			      DRM_MODE_FLAG_INTERLACE);
-
-	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
-		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
-				      DRM_MODE_FLAG_PHSYNC);
-		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
-				      DRM_MODE_FLAG_NHSYNC);
-		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
-				      DRM_MODE_FLAG_PVSYNC);
-		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
-				      DRM_MODE_FLAG_NVSYNC);
-	}
-
-	PIPE_CONF_CHECK_I(output_format);
-	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
-	if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
-	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-		PIPE_CONF_CHECK_BOOL(limited_color_range);
-
-	PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
-	PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
-	PIPE_CONF_CHECK_BOOL(has_infoframe);
-	PIPE_CONF_CHECK_BOOL(fec_enable);
-
-	PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
-
-	PIPE_CONF_CHECK_X(gmch_pfit.control);
-	/* pfit ratios are autocomputed by the hw on gen4+ */
-	if (DISPLAY_VER(dev_priv) < 4)
-		PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
-	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
-
-	/*
-	 * Changing the EDP transcoder input mux
-	 * (A_ONOFF vs. A_ON) requires a full modeset.
-	 */
-	PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
-
-	if (!fastset) {
-		PIPE_CONF_CHECK_RECT(pipe_src);
-
-		PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
-		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
-
-		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
-		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
-
-		PIPE_CONF_CHECK_X(gamma_mode);
-		if (IS_CHERRYVIEW(dev_priv))
-			PIPE_CONF_CHECK_X(cgm_mode);
-		else
-			PIPE_CONF_CHECK_X(csc_mode);
-		PIPE_CONF_CHECK_BOOL(gamma_enable);
-		PIPE_CONF_CHECK_BOOL(csc_enable);
-
-		PIPE_CONF_CHECK_I(linetime);
-		PIPE_CONF_CHECK_I(ips_linetime);
-
-		bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
-		if (bp_gamma)
-			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
-
-		if (current_config->active_planes) {
-			PIPE_CONF_CHECK_BOOL(has_psr);
-			PIPE_CONF_CHECK_BOOL(has_psr2);
-			PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
-			PIPE_CONF_CHECK_I(dc3co_exitline);
-		}
-	}
-
-	PIPE_CONF_CHECK_BOOL(double_wide);
-
-	if (dev_priv->dpll.mgr) {
-		PIPE_CONF_CHECK_P(shared_dpll);
-
-		PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
-		PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
-		PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
-		PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
-		PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
-		PIPE_CONF_CHECK_X(dpll_hw_state.spll);
-		PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
-		PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
-		PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
-		PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
-		PIPE_CONF_CHECK_X(dpll_hw_state.div0);
-		PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
-		PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
-		PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
-		PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
-		PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
-		PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
-		PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
-		PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
-		PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
-		PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
-		PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
-		PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
-		PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
-		PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
-		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
-		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
-		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
-		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
-		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
-		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
-		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
-	}
-
-	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
-	PIPE_CONF_CHECK_X(dsi_pll.div);
-
-	if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
-		PIPE_CONF_CHECK_I(pipe_bpp);
-
-	PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
-	PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
-	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
-
-	PIPE_CONF_CHECK_I(min_voltage_level);
-
-	if (current_config->has_psr || pipe_config->has_psr)
-		PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
-					    ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
-	else
-		PIPE_CONF_CHECK_X(infoframes.enable);
-
-	PIPE_CONF_CHECK_X(infoframes.gcp);
-	PIPE_CONF_CHECK_INFOFRAME(avi);
-	PIPE_CONF_CHECK_INFOFRAME(spd);
-	PIPE_CONF_CHECK_INFOFRAME(hdmi);
-	PIPE_CONF_CHECK_INFOFRAME(drm);
-	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
-
-	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
-	PIPE_CONF_CHECK_I(master_transcoder);
-	PIPE_CONF_CHECK_X(bigjoiner_pipes);
-
-	PIPE_CONF_CHECK_I(dsc.compression_enable);
-	PIPE_CONF_CHECK_I(dsc.dsc_split);
-	PIPE_CONF_CHECK_I(dsc.compressed_bpp);
-
-	PIPE_CONF_CHECK_BOOL(splitter.enable);
-	PIPE_CONF_CHECK_I(splitter.link_count);
-	PIPE_CONF_CHECK_I(splitter.pixel_overlap);
-
-	PIPE_CONF_CHECK_BOOL(vrr.enable);
-	PIPE_CONF_CHECK_I(vrr.vmin);
-	PIPE_CONF_CHECK_I(vrr.vmax);
-	PIPE_CONF_CHECK_I(vrr.flipline);
-	PIPE_CONF_CHECK_I(vrr.pipeline_full);
-	PIPE_CONF_CHECK_I(vrr.guardband);
-
-#undef PIPE_CONF_CHECK_X
-#undef PIPE_CONF_CHECK_I
-#undef PIPE_CONF_CHECK_BOOL
-#undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
-#undef PIPE_CONF_CHECK_P
-#undef PIPE_CONF_CHECK_FLAGS
-#undef PIPE_CONF_CHECK_CLOCK_FUZZY
-#undef PIPE_CONF_CHECK_COLOR_LUT
-#undef PIPE_CONF_CHECK_TIMINGS
-#undef PIPE_CONF_CHECK_RECT
-#undef PIPE_CONF_QUIRK
-
-	return ret;
-}
-
 static void
 intel_verify_planes(struct intel_atomic_state *state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 70410eeb19c8..e827c84ece56 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -560,9 +560,6 @@ bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
-bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
-			       const struct intel_crtc_state *pipe_config,
-			       bool fastset);
 void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 			    struct intel_atomic_state *state,
 			    const char *context);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 7a91c926598b..fd752c61d854 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -14,6 +14,7 @@
 #include "intel_display_types.h"
 #include "intel_fdi.h"
 #include "intel_modeset_verify.h"
+#include "intel_pipe_config_compare.h"
 #include "intel_pm.h"
 #include "intel_snps_phy.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_config_compare.c b/drivers/gpu/drm/i915/display/intel_pipe_config_compare.c
new file mode 100644
index 000000000000..ec50373e0242
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pipe_config_compare.c
@@ -0,0 +1,581 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+#include "intel_color.h"
+#include "intel_display_types.h"
+#include "intel_hdmi.h"
+#include "intel_pipe_config_compare.h"
+
+static bool fastboot_enabled(struct drm_i915_private *dev_priv)
+{
+	if (dev_priv->params.fastboot != -1)
+		return dev_priv->params.fastboot;
+
+	/* Enable fastboot by default on Skylake and newer */
+	if (DISPLAY_VER(dev_priv) >= 9)
+		return true;
+
+	/* Enable fastboot by default on VLV and CHV */
+	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+		return true;
+
+	/* Disabled by default on all others */
+	return false;
+}
+
+static bool
+intel_compare_m_n(unsigned int m, unsigned int n,
+		  unsigned int m2, unsigned int n2,
+		  bool exact)
+{
+	if (m == m2 && n == n2)
+		return true;
+
+	if (exact || !m || !n || !m2 || !n2)
+		return false;
+
+	BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
+
+	if (n > n2) {
+		while (n > n2) {
+			m2 <<= 1;
+			n2 <<= 1;
+		}
+	} else if (n < n2) {
+		while (n < n2) {
+			m <<= 1;
+			n <<= 1;
+		}
+	}
+
+	if (n != n2)
+		return false;
+
+	return intel_fuzzy_clock_check(m, m2);
+}
+
+static bool
+intel_compare_link_m_n(const struct intel_link_m_n *m_n,
+		       const struct intel_link_m_n *m2_n2,
+		       bool exact)
+{
+	return m_n->tu == m2_n2->tu &&
+		intel_compare_m_n(m_n->data_m, m_n->data_n,
+				  m2_n2->data_m, m2_n2->data_n, exact) &&
+		intel_compare_m_n(m_n->link_m, m_n->link_n,
+				  m2_n2->link_m, m2_n2->link_n, exact);
+}
+
+static bool
+intel_compare_infoframe(const union hdmi_infoframe *a,
+			const union hdmi_infoframe *b)
+{
+	return memcmp(a, b, sizeof(*a)) == 0;
+}
+
+static bool
+intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
+			 const struct drm_dp_vsc_sdp *b)
+{
+	return memcmp(a, b, sizeof(*a)) == 0;
+}
+
+static void
+pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
+			       bool fastset, const char *name,
+			       const union hdmi_infoframe *a,
+			       const union hdmi_infoframe *b)
+{
+	if (fastset) {
+		if (!drm_debug_enabled(DRM_UT_KMS))
+			return;
+
+		drm_dbg_kms(&dev_priv->drm,
+			    "fastset mismatch in %s infoframe\n", name);
+		drm_dbg_kms(&dev_priv->drm, "expected:\n");
+		hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
+		drm_dbg_kms(&dev_priv->drm, "found:\n");
+		hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
+	} else {
+		drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
+		drm_err(&dev_priv->drm, "expected:\n");
+		hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
+		drm_err(&dev_priv->drm, "found:\n");
+		hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
+	}
+}
+
+static void
+pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
+				bool fastset, const char *name,
+				const struct drm_dp_vsc_sdp *a,
+				const struct drm_dp_vsc_sdp *b)
+{
+	if (fastset) {
+		if (!drm_debug_enabled(DRM_UT_KMS))
+			return;
+
+		drm_dbg_kms(&dev_priv->drm,
+			    "fastset mismatch in %s dp sdp\n", name);
+		drm_dbg_kms(&dev_priv->drm, "expected:\n");
+		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
+		drm_dbg_kms(&dev_priv->drm, "found:\n");
+		drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
+	} else {
+		drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
+		drm_err(&dev_priv->drm, "expected:\n");
+		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
+		drm_err(&dev_priv->drm, "found:\n");
+		drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
+	}
+}
+
+static void __printf(4, 5)
+pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
+		     const char *name, const char *format, ...)
+{
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct va_format vaf;
+	va_list args;
+
+	va_start(args, format);
+	vaf.fmt = format;
+	vaf.va = &args;
+
+	if (fastset)
+		drm_dbg_kms(&i915->drm,
+			    "[CRTC:%d:%s] fastset mismatch in %s %pV\n",
+			    crtc->base.base.id, crtc->base.name, name, &vaf);
+	else
+		drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
+			crtc->base.base.id, crtc->base.name, name, &vaf);
+
+	va_end(args);
+}
+
+bool
+intel_pipe_config_compare(const struct intel_crtc_state *current_config,
+			  const struct intel_crtc_state *pipe_config,
+			  bool fastset)
+{
+	struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+	bool ret = true;
+	u32 bp_gamma = 0;
+	bool fixup_inherited = fastset &&
+		current_config->inherited && !pipe_config->inherited;
+
+	if (fixup_inherited && !fastboot_enabled(dev_priv)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "initial modeset and fastboot not set\n");
+		ret = false;
+	}
+
+#define PIPE_CONF_CHECK_X(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected 0x%08x, found 0x%08x)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)
+
+#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
+	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected 0x%08x, found 0x%08x)", \
+				     current_config->name & (mask), \
+				     pipe_config->name & (mask)); \
+		ret = false; \
+	} \
+} while (0)
+
+#define PIPE_CONF_CHECK_I(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected %i, found %i)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)
+
+#define PIPE_CONF_CHECK_BOOL(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc,  __stringify(name), \
+				     "(expected %s, found %s)", \
+				     str_yes_no(current_config->name), \
+				     str_yes_no(pipe_config->name)); \
+		ret = false; \
+	} \
+} while (0)
+
+/*
+ * Checks state where we only read out the enabling, but not the entire
+ * state itself (like full infoframes or ELD for audio). These states
+ * require a full modeset on bootup to fix up.
+ */
+#define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
+	if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
+		PIPE_CONF_CHECK_BOOL(name); \
+	} else { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
+				     str_yes_no(current_config->name), \
+				     str_yes_no(pipe_config->name)); \
+		ret = false; \
+	} \
+} while (0)
+
+#define PIPE_CONF_CHECK_P(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected %p, found %p)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)
+
+#define PIPE_CONF_CHECK_M_N(name) do { \
+	if (!intel_compare_link_m_n(&current_config->name, \
+				    &pipe_config->name,\
+				    !fastset)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected tu %i data %i/%i link %i/%i, " \
+				     "found tu %i, data %i/%i link %i/%i)", \
+				     current_config->name.tu, \
+				     current_config->name.data_m, \
+				     current_config->name.data_n, \
+				     current_config->name.link_m, \
+				     current_config->name.link_n, \
+				     pipe_config->name.tu, \
+				     pipe_config->name.data_m, \
+				     pipe_config->name.data_n, \
+				     pipe_config->name.link_m, \
+				     pipe_config->name.link_n); \
+		ret = false; \
+	} \
+} while (0)
+
+#define PIPE_CONF_CHECK_TIMINGS(name) do { \
+	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_htotal); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+} while (0)
+
+#define PIPE_CONF_CHECK_RECT(name) do { \
+	PIPE_CONF_CHECK_I(name.x1); \
+	PIPE_CONF_CHECK_I(name.x2); \
+	PIPE_CONF_CHECK_I(name.y1); \
+	PIPE_CONF_CHECK_I(name.y2); \
+} while (0)
+
+/* This is required for BDW+ where there is only one set of registers for
+ * switching between high and low RR.
+ * This macro can be used whenever a comparison has to be made between one
+ * hw state and multiple sw state variables.
+ */
+#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
+	if (!intel_compare_link_m_n(&current_config->name, \
+				    &pipe_config->name, !fastset) && \
+	    !intel_compare_link_m_n(&current_config->alt_name, \
+				    &pipe_config->name, !fastset)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected tu %i data %i/%i link %i/%i, " \
+				     "or tu %i data %i/%i link %i/%i, " \
+				     "found tu %i, data %i/%i link %i/%i)", \
+				     current_config->name.tu, \
+				     current_config->name.data_m, \
+				     current_config->name.data_n, \
+				     current_config->name.link_m, \
+				     current_config->name.link_n, \
+				     current_config->alt_name.tu, \
+				     current_config->alt_name.data_m, \
+				     current_config->alt_name.data_n, \
+				     current_config->alt_name.link_m, \
+				     current_config->alt_name.link_n, \
+				     pipe_config->name.tu, \
+				     pipe_config->name.data_m, \
+				     pipe_config->name.data_n, \
+				     pipe_config->name.link_m, \
+				     pipe_config->name.link_n); \
+		ret = false; \
+	} \
+} while (0)
+
+#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
+	if ((current_config->name ^ pipe_config->name) & (mask)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(%x) (expected %i, found %i)", \
+				     (mask), \
+				     current_config->name & (mask), \
+				     pipe_config->name & (mask)); \
+		ret = false; \
+	} \
+} while (0)
+
+#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
+	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected %i, found %i)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)
+
+#define PIPE_CONF_CHECK_INFOFRAME(name) do { \
+	if (!intel_compare_infoframe(&current_config->infoframes.name, \
+				     &pipe_config->infoframes.name)) { \
+		pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
+					       &current_config->infoframes.name, \
+					       &pipe_config->infoframes.name); \
+		ret = false; \
+	} \
+} while (0)
+
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+	if (!current_config->has_psr && !pipe_config->has_psr && \
+	    !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
+				      &pipe_config->infoframes.name)) { \
+		pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
+						&current_config->infoframes.name, \
+						&pipe_config->infoframes.name); \
+		ret = false; \
+	} \
+} while (0)
+
+#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
+	if (current_config->name1 != pipe_config->name1) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name1), \
+				"(expected %i, found %i, won't compare lut values)", \
+				current_config->name1, \
+				pipe_config->name1); \
+		ret = false;\
+	} else { \
+		if (!intel_color_lut_equal(current_config->name2, \
+					pipe_config->name2, pipe_config->name1, \
+					bit_precision)) { \
+			pipe_config_mismatch(fastset, crtc, __stringify(name2), \
+					"hw_state doesn't match sw_state"); \
+			ret = false; \
+		} \
+	} \
+} while (0)
+
+#define PIPE_CONF_QUIRK(quirk) \
+	((current_config->quirks | pipe_config->quirks) & (quirk))
+
+	PIPE_CONF_CHECK_I(hw.enable);
+	PIPE_CONF_CHECK_I(hw.active);
+
+	PIPE_CONF_CHECK_I(cpu_transcoder);
+	PIPE_CONF_CHECK_I(mst_master_transcoder);
+
+	PIPE_CONF_CHECK_BOOL(has_pch_encoder);
+	PIPE_CONF_CHECK_I(fdi_lanes);
+	PIPE_CONF_CHECK_M_N(fdi_m_n);
+
+	PIPE_CONF_CHECK_I(lane_count);
+	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
+
+	if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv)) {
+		PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
+	} else {
+		PIPE_CONF_CHECK_M_N(dp_m_n);
+		PIPE_CONF_CHECK_M_N(dp_m2_n2);
+	}
+
+	PIPE_CONF_CHECK_X(output_types);
+
+	PIPE_CONF_CHECK_I(framestart_delay);
+	PIPE_CONF_CHECK_I(msa_timing_delay);
+
+	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
+	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
+
+	PIPE_CONF_CHECK_I(pixel_multiplier);
+
+	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+			      DRM_MODE_FLAG_INTERLACE);
+
+	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+				      DRM_MODE_FLAG_PHSYNC);
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+				      DRM_MODE_FLAG_NHSYNC);
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+				      DRM_MODE_FLAG_PVSYNC);
+		PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
+				      DRM_MODE_FLAG_NVSYNC);
+	}
+
+	PIPE_CONF_CHECK_I(output_format);
+	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
+	if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
+	    IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+		PIPE_CONF_CHECK_BOOL(limited_color_range);
+
+	PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
+	PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
+	PIPE_CONF_CHECK_BOOL(has_infoframe);
+	PIPE_CONF_CHECK_BOOL(fec_enable);
+
+	PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
+
+	PIPE_CONF_CHECK_X(gmch_pfit.control);
+	/* pfit ratios are autocomputed by the hw on gen4+ */
+	if (DISPLAY_VER(dev_priv) < 4)
+		PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
+	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
+
+	/*
+	 * Changing the EDP transcoder input mux
+	 * (A_ONOFF vs. A_ON) requires a full modeset.
+	 */
+	PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
+
+	if (!fastset) {
+		PIPE_CONF_CHECK_RECT(pipe_src);
+
+		PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
+		PIPE_CONF_CHECK_RECT(pch_pfit.dst);
+
+		PIPE_CONF_CHECK_I(scaler_state.scaler_id);
+		PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
+
+		PIPE_CONF_CHECK_X(gamma_mode);
+		if (IS_CHERRYVIEW(dev_priv))
+			PIPE_CONF_CHECK_X(cgm_mode);
+		else
+			PIPE_CONF_CHECK_X(csc_mode);
+		PIPE_CONF_CHECK_BOOL(gamma_enable);
+		PIPE_CONF_CHECK_BOOL(csc_enable);
+
+		PIPE_CONF_CHECK_I(linetime);
+		PIPE_CONF_CHECK_I(ips_linetime);
+
+		bp_gamma = intel_color_get_gamma_bit_precision(pipe_config);
+		if (bp_gamma)
+			PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma);
+
+		if (current_config->active_planes) {
+			PIPE_CONF_CHECK_BOOL(has_psr);
+			PIPE_CONF_CHECK_BOOL(has_psr2);
+			PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+			PIPE_CONF_CHECK_I(dc3co_exitline);
+		}
+	}
+
+	PIPE_CONF_CHECK_BOOL(double_wide);
+
+	if (dev_priv->dpll.mgr) {
+		PIPE_CONF_CHECK_P(shared_dpll);
+
+		PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
+		PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
+		PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
+		PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
+		PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
+		PIPE_CONF_CHECK_X(dpll_hw_state.spll);
+		PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
+		PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
+		PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
+		PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
+		PIPE_CONF_CHECK_X(dpll_hw_state.div0);
+		PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
+		PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
+		PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
+		PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
+		PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
+		PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
+		PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
+		PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
+		PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
+		PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
+		PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
+		PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
+		PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
+		PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
+		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
+		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
+		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
+		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
+		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
+		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
+		PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
+	}
+
+	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
+	PIPE_CONF_CHECK_X(dsi_pll.div);
+
+	if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
+		PIPE_CONF_CHECK_I(pipe_bpp);
+
+	PIPE_CONF_CHECK_CLOCK_FUZZY(hw.pipe_mode.crtc_clock);
+	PIPE_CONF_CHECK_CLOCK_FUZZY(hw.adjusted_mode.crtc_clock);
+	PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
+
+	PIPE_CONF_CHECK_I(min_voltage_level);
+
+	if (current_config->has_psr || pipe_config->has_psr)
+		PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
+					    ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
+	else
+		PIPE_CONF_CHECK_X(infoframes.enable);
+
+	PIPE_CONF_CHECK_X(infoframes.gcp);
+	PIPE_CONF_CHECK_INFOFRAME(avi);
+	PIPE_CONF_CHECK_INFOFRAME(spd);
+	PIPE_CONF_CHECK_INFOFRAME(hdmi);
+	PIPE_CONF_CHECK_INFOFRAME(drm);
+	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
+
+	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
+	PIPE_CONF_CHECK_I(master_transcoder);
+	PIPE_CONF_CHECK_X(bigjoiner_pipes);
+
+	PIPE_CONF_CHECK_I(dsc.compression_enable);
+	PIPE_CONF_CHECK_I(dsc.dsc_split);
+	PIPE_CONF_CHECK_I(dsc.compressed_bpp);
+
+	PIPE_CONF_CHECK_BOOL(splitter.enable);
+	PIPE_CONF_CHECK_I(splitter.link_count);
+	PIPE_CONF_CHECK_I(splitter.pixel_overlap);
+
+	PIPE_CONF_CHECK_BOOL(vrr.enable);
+	PIPE_CONF_CHECK_I(vrr.vmin);
+	PIPE_CONF_CHECK_I(vrr.vmax);
+	PIPE_CONF_CHECK_I(vrr.flipline);
+	PIPE_CONF_CHECK_I(vrr.pipeline_full);
+	PIPE_CONF_CHECK_I(vrr.guardband);
+
+#undef PIPE_CONF_CHECK_X
+#undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_BOOL
+#undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
+#undef PIPE_CONF_CHECK_P
+#undef PIPE_CONF_CHECK_FLAGS
+#undef PIPE_CONF_CHECK_CLOCK_FUZZY
+#undef PIPE_CONF_CHECK_COLOR_LUT
+#undef PIPE_CONF_CHECK_TIMINGS
+#undef PIPE_CONF_CHECK_RECT
+#undef PIPE_CONF_QUIRK
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_config_compare.h b/drivers/gpu/drm/i915/display/intel_pipe_config_compare.h
new file mode 100644
index 000000000000..f57d6c7a305e
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pipe_config_compare.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_PIPE_CONFIG_COMPARE_H__
+#define __INTEL_PIPE_CONFIG_COMPARE_H__
+
+#include <linux/types.h>
+
+struct intel_crtc_state;
+
+bool intel_pipe_config_compare(const struct intel_crtc_state *current_config,
+			       const struct intel_crtc_state *pipe_config,
+			       bool fastset);
+
+#endif /* __INTEL_PIPE_CONFIG_COMPARE_H__ */
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 7/7] drm/i915/display: split out pipe config dump to a separate file
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
                   ` (5 preceding siblings ...)
  2022-06-15 12:48 ` [Intel-gfx] [PATCH 6/7] drm/i915/display: split out pipe config compare to a separate file Jani Nikula
@ 2022-06-15 12:48 ` Jani Nikula
  2022-06-15 13:14   ` Ville Syrjälä
  2022-06-15 13:27 ` [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Ville Syrjälä
                   ` (4 subsequent siblings)
  11 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2022-06-15 12:48 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

Declutter intel_display.c by splitting out pipe config dumping to a
separate file.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_display.c  | 311 +----------------
 drivers/gpu/drm/i915/display/intel_display.h  |   3 -
 .../drm/i915/display/intel_modeset_verify.c   |   5 +-
 .../drm/i915/display/intel_pipe_config_dump.c | 314 ++++++++++++++++++
 .../drm/i915/display/intel_pipe_config_dump.h |  16 +
 6 files changed, 338 insertions(+), 312 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 8b4e5c59ee70..d69881506dc7 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -247,6 +247,7 @@ i915-y += \
 	display/intel_pch_display.o \
 	display/intel_pch_refclk.o \
 	display/intel_pipe_config_compare.o \
+	display/intel_pipe_config_dump.o \
 	display/intel_plane_initial.o \
 	display/intel_psr.o \
 	display/intel_quirks.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 093ba6bde105..8741ae5e6108 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -106,6 +106,7 @@
 #include "intel_pch_refclk.h"
 #include "intel_pcode.h"
 #include "intel_pipe_config_compare.h"
+#include "intel_pipe_config_dump.h"
 #include "intel_pipe_crc.h"
 #include "intel_plane_initial.h"
 #include "intel_pm.h"
@@ -5059,310 +5060,6 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
 	return 0;
 }
 
-static void intel_dump_crtc_timings(struct drm_i915_private *i915,
-				    const struct drm_display_mode *mode)
-{
-	drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
-		    "type: 0x%x flags: 0x%x\n",
-		    mode->crtc_clock,
-		    mode->crtc_hdisplay, mode->crtc_hsync_start,
-		    mode->crtc_hsync_end, mode->crtc_htotal,
-		    mode->crtc_vdisplay, mode->crtc_vsync_start,
-		    mode->crtc_vsync_end, mode->crtc_vtotal,
-		    mode->type, mode->flags);
-}
-
-static void
-intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
-		      const char *id, unsigned int lane_count,
-		      const struct intel_link_m_n *m_n)
-{
-	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
-
-	drm_dbg_kms(&i915->drm,
-		    "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
-		    id, lane_count,
-		    m_n->data_m, m_n->data_n,
-		    m_n->link_m, m_n->link_n, m_n->tu);
-}
-
-static void
-intel_dump_infoframe(struct drm_i915_private *dev_priv,
-		     const union hdmi_infoframe *frame)
-{
-	if (!drm_debug_enabled(DRM_UT_KMS))
-		return;
-
-	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
-}
-
-static void
-intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
-		      const struct drm_dp_vsc_sdp *vsc)
-{
-	if (!drm_debug_enabled(DRM_UT_KMS))
-		return;
-
-	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
-}
-
-#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
-
-static const char * const output_type_str[] = {
-	OUTPUT_TYPE(UNUSED),
-	OUTPUT_TYPE(ANALOG),
-	OUTPUT_TYPE(DVO),
-	OUTPUT_TYPE(SDVO),
-	OUTPUT_TYPE(LVDS),
-	OUTPUT_TYPE(TVOUT),
-	OUTPUT_TYPE(HDMI),
-	OUTPUT_TYPE(DP),
-	OUTPUT_TYPE(EDP),
-	OUTPUT_TYPE(DSI),
-	OUTPUT_TYPE(DDI),
-	OUTPUT_TYPE(DP_MST),
-};
-
-#undef OUTPUT_TYPE
-
-static void snprintf_output_types(char *buf, size_t len,
-				  unsigned int output_types)
-{
-	char *str = buf;
-	int i;
-
-	str[0] = '\0';
-
-	for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
-		int r;
-
-		if ((output_types & BIT(i)) == 0)
-			continue;
-
-		r = snprintf(str, len, "%s%s",
-			     str != buf ? "," : "", output_type_str[i]);
-		if (r >= len)
-			break;
-		str += r;
-		len -= r;
-
-		output_types &= ~BIT(i);
-	}
-
-	WARN_ON_ONCE(output_types != 0);
-}
-
-static const char * const output_format_str[] = {
-	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
-	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
-	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
-};
-
-static const char *output_formats(enum intel_output_format format)
-{
-	if (format >= ARRAY_SIZE(output_format_str))
-		return "invalid";
-	return output_format_str[format];
-}
-
-static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
-{
-	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
-	struct drm_i915_private *i915 = to_i915(plane->base.dev);
-	const struct drm_framebuffer *fb = plane_state->hw.fb;
-
-	if (!fb) {
-		drm_dbg_kms(&i915->drm,
-			    "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
-			    plane->base.base.id, plane->base.name,
-			    str_yes_no(plane_state->uapi.visible));
-		return;
-	}
-
-	drm_dbg_kms(&i915->drm,
-		    "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
-		    plane->base.base.id, plane->base.name,
-		    fb->base.id, fb->width, fb->height, &fb->format->format,
-		    fb->modifier, str_yes_no(plane_state->uapi.visible));
-	drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
-		    plane_state->hw.rotation, plane_state->scaler_id);
-	if (plane_state->uapi.visible)
-		drm_dbg_kms(&i915->drm,
-			    "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
-			    DRM_RECT_FP_ARG(&plane_state->uapi.src),
-			    DRM_RECT_ARG(&plane_state->uapi.dst));
-}
-
-void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
-			    struct intel_atomic_state *state,
-			    const char *context)
-{
-	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	const struct intel_plane_state *plane_state;
-	struct intel_plane *plane;
-	char buf[64];
-	int i;
-
-	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
-		    crtc->base.base.id, crtc->base.name,
-		    str_yes_no(pipe_config->hw.enable), context);
-
-	if (!pipe_config->hw.enable)
-		goto dump_planes;
-
-	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
-	drm_dbg_kms(&dev_priv->drm,
-		    "active: %s, output_types: %s (0x%x), output format: %s\n",
-		    str_yes_no(pipe_config->hw.active),
-		    buf, pipe_config->output_types,
-		    output_formats(pipe_config->output_format));
-
-	drm_dbg_kms(&dev_priv->drm,
-		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
-		    transcoder_name(pipe_config->cpu_transcoder),
-		    pipe_config->pipe_bpp, pipe_config->dither);
-
-	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
-		    transcoder_name(pipe_config->mst_master_transcoder));
-
-	drm_dbg_kms(&dev_priv->drm,
-		    "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
-		    transcoder_name(pipe_config->master_transcoder),
-		    pipe_config->sync_mode_slaves_mask);
-
-	drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n",
-		    intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
-		    intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
-		    pipe_config->bigjoiner_pipes);
-
-	drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
-		    str_enabled_disabled(pipe_config->splitter.enable),
-		    pipe_config->splitter.link_count,
-		    pipe_config->splitter.pixel_overlap);
-
-	if (pipe_config->has_pch_encoder)
-		intel_dump_m_n_config(pipe_config, "fdi",
-				      pipe_config->fdi_lanes,
-				      &pipe_config->fdi_m_n);
-
-	if (intel_crtc_has_dp_encoder(pipe_config)) {
-		intel_dump_m_n_config(pipe_config, "dp m_n",
-				      pipe_config->lane_count,
-				      &pipe_config->dp_m_n);
-		intel_dump_m_n_config(pipe_config, "dp m2_n2",
-				      pipe_config->lane_count,
-				      &pipe_config->dp_m2_n2);
-	}
-
-	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
-		    pipe_config->framestart_delay, pipe_config->msa_timing_delay);
-
-	drm_dbg_kms(&dev_priv->drm,
-		    "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
-		    pipe_config->has_audio, pipe_config->has_infoframe,
-		    pipe_config->infoframes.enable);
-
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
-		drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
-			    pipe_config->infoframes.gcp);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
-		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
-	if (pipe_config->infoframes.enable &
-	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
-		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
-
-	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
-		    str_yes_no(pipe_config->vrr.enable),
-		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
-		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
-		    pipe_config->vrr.flipline,
-		    intel_vrr_vmin_vblank_start(pipe_config),
-		    intel_vrr_vmax_vblank_start(pipe_config));
-
-	drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n",
-		    DRM_MODE_ARG(&pipe_config->hw.mode));
-	drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n",
-		    DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
-	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
-	drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n",
-		    DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
-	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
-	drm_dbg_kms(&dev_priv->drm,
-		    "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
-		    pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
-		    pipe_config->pixel_rate);
-
-	drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
-		    pipe_config->linetime, pipe_config->ips_linetime);
-
-	if (DISPLAY_VER(dev_priv) >= 9)
-		drm_dbg_kms(&dev_priv->drm,
-			    "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
-			    crtc->num_scalers,
-			    pipe_config->scaler_state.scaler_users,
-			    pipe_config->scaler_state.scaler_id);
-
-	if (HAS_GMCH(dev_priv))
-		drm_dbg_kms(&dev_priv->drm,
-			    "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
-			    pipe_config->gmch_pfit.control,
-			    pipe_config->gmch_pfit.pgm_ratios,
-			    pipe_config->gmch_pfit.lvds_border_bits);
-	else
-		drm_dbg_kms(&dev_priv->drm,
-			    "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
-			    DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
-			    str_enabled_disabled(pipe_config->pch_pfit.enabled),
-			    str_yes_no(pipe_config->pch_pfit.force_thru));
-
-	drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
-		    pipe_config->ips_enabled, pipe_config->double_wide,
-		    pipe_config->has_drrs);
-
-	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
-
-	if (IS_CHERRYVIEW(dev_priv))
-		drm_dbg_kms(&dev_priv->drm,
-			    "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
-			    pipe_config->cgm_mode, pipe_config->gamma_mode,
-			    pipe_config->gamma_enable, pipe_config->csc_enable);
-	else
-		drm_dbg_kms(&dev_priv->drm,
-			    "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
-			    pipe_config->csc_mode, pipe_config->gamma_mode,
-			    pipe_config->gamma_enable, pipe_config->csc_enable);
-
-	drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
-		    pipe_config->hw.degamma_lut ?
-		    drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
-		    pipe_config->hw.gamma_lut ?
-		    drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
-
-dump_planes:
-	if (!state)
-		return;
-
-	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
-		if (plane->pipe == crtc->pipe)
-			intel_dump_plane_state(plane_state);
-	}
-}
-
 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
 {
 	struct drm_device *dev = state->base.dev;
@@ -6823,7 +6520,7 @@ static int intel_atomic_check(struct drm_device *dev,
 		    !new_crtc_state->update_pipe)
 			continue;
 
-		intel_dump_pipe_config(new_crtc_state, state,
+		intel_pipe_config_dump(new_crtc_state, state,
 				       intel_crtc_needs_modeset(new_crtc_state) ?
 				       "[modeset]" : "[fastset]");
 	}
@@ -6840,7 +6537,7 @@ static int intel_atomic_check(struct drm_device *dev,
 	 */
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
 					    new_crtc_state, i)
-		intel_dump_pipe_config(new_crtc_state, state, "[failed]");
+		intel_pipe_config_dump(new_crtc_state, state, "[failed]");
 
 	return ret;
 }
@@ -9320,7 +9017,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
 			to_intel_crtc_state(crtc->base.state);
 
 		intel_sanitize_crtc(crtc, ctx);
-		intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
+		intel_pipe_config_dump(crtc_state, NULL, "[setup_hw_state]");
 	}
 
 	intel_modeset_update_connector_atomic_state(dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index e827c84ece56..68477eb82049 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -560,9 +560,6 @@ bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
-void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
-			    struct intel_atomic_state *state,
-			    const char *context);
 
 void intel_plane_destroy(struct drm_plane *plane);
 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index fd752c61d854..de034ccef289 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -15,6 +15,7 @@
 #include "intel_fdi.h"
 #include "intel_modeset_verify.h"
 #include "intel_pipe_config_compare.h"
+#include "intel_pipe_config_dump.h"
 #include "intel_pm.h"
 #include "intel_snps_phy.h"
 
@@ -217,8 +218,8 @@ verify_crtc_state(struct intel_crtc *crtc,
 	if (!intel_pipe_config_compare(new_crtc_state,
 				       pipe_config, false)) {
 		I915_STATE_WARN(1, "pipe state doesn't match!\n");
-		intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
-		intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
+		intel_pipe_config_dump(pipe_config, NULL, "[hw state]");
+		intel_pipe_config_dump(new_crtc_state, NULL, "[sw state]");
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_config_dump.c b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
new file mode 100644
index 000000000000..c290cf009407
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "intel_display_types.h"
+#include "intel_hdmi.h"
+#include "intel_pipe_config_dump.h"
+#include "intel_vrr.h"
+
+static void intel_dump_crtc_timings(struct drm_i915_private *i915,
+				    const struct drm_display_mode *mode)
+{
+	drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
+		    "type: 0x%x flags: 0x%x\n",
+		    mode->crtc_clock,
+		    mode->crtc_hdisplay, mode->crtc_hsync_start,
+		    mode->crtc_hsync_end, mode->crtc_htotal,
+		    mode->crtc_vdisplay, mode->crtc_vsync_start,
+		    mode->crtc_vsync_end, mode->crtc_vtotal,
+		    mode->type, mode->flags);
+}
+
+static void
+intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
+		      const char *id, unsigned int lane_count,
+		      const struct intel_link_m_n *m_n)
+{
+	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
+
+	drm_dbg_kms(&i915->drm,
+		    "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
+		    id, lane_count,
+		    m_n->data_m, m_n->data_n,
+		    m_n->link_m, m_n->link_n, m_n->tu);
+}
+
+static void
+intel_dump_infoframe(struct drm_i915_private *dev_priv,
+		     const union hdmi_infoframe *frame)
+{
+	if (!drm_debug_enabled(DRM_UT_KMS))
+		return;
+
+	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
+}
+
+static void
+intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
+		      const struct drm_dp_vsc_sdp *vsc)
+{
+	if (!drm_debug_enabled(DRM_UT_KMS))
+		return;
+
+	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
+}
+
+#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
+
+static const char * const output_type_str[] = {
+	OUTPUT_TYPE(UNUSED),
+	OUTPUT_TYPE(ANALOG),
+	OUTPUT_TYPE(DVO),
+	OUTPUT_TYPE(SDVO),
+	OUTPUT_TYPE(LVDS),
+	OUTPUT_TYPE(TVOUT),
+	OUTPUT_TYPE(HDMI),
+	OUTPUT_TYPE(DP),
+	OUTPUT_TYPE(EDP),
+	OUTPUT_TYPE(DSI),
+	OUTPUT_TYPE(DDI),
+	OUTPUT_TYPE(DP_MST),
+};
+
+#undef OUTPUT_TYPE
+
+static void snprintf_output_types(char *buf, size_t len,
+				  unsigned int output_types)
+{
+	char *str = buf;
+	int i;
+
+	str[0] = '\0';
+
+	for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
+		int r;
+
+		if ((output_types & BIT(i)) == 0)
+			continue;
+
+		r = snprintf(str, len, "%s%s",
+			     str != buf ? "," : "", output_type_str[i]);
+		if (r >= len)
+			break;
+		str += r;
+		len -= r;
+
+		output_types &= ~BIT(i);
+	}
+
+	WARN_ON_ONCE(output_types != 0);
+}
+
+static const char * const output_format_str[] = {
+	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
+	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
+	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
+};
+
+static const char *output_formats(enum intel_output_format format)
+{
+	if (format >= ARRAY_SIZE(output_format_str))
+		return "invalid";
+	return output_format_str[format];
+}
+
+static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
+{
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+	struct drm_i915_private *i915 = to_i915(plane->base.dev);
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+	if (!fb) {
+		drm_dbg_kms(&i915->drm,
+			    "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
+			    plane->base.base.id, plane->base.name,
+			    str_yes_no(plane_state->uapi.visible));
+		return;
+	}
+
+	drm_dbg_kms(&i915->drm,
+		    "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
+		    plane->base.base.id, plane->base.name,
+		    fb->base.id, fb->width, fb->height, &fb->format->format,
+		    fb->modifier, str_yes_no(plane_state->uapi.visible));
+	drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
+		    plane_state->hw.rotation, plane_state->scaler_id);
+	if (plane_state->uapi.visible)
+		drm_dbg_kms(&i915->drm,
+			    "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
+			    DRM_RECT_FP_ARG(&plane_state->uapi.src),
+			    DRM_RECT_ARG(&plane_state->uapi.dst));
+}
+
+void intel_pipe_config_dump(const struct intel_crtc_state *pipe_config,
+			    struct intel_atomic_state *state,
+			    const char *context)
+{
+	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct intel_plane_state *plane_state;
+	struct intel_plane *plane;
+	char buf[64];
+	int i;
+
+	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
+		    crtc->base.base.id, crtc->base.name,
+		    str_yes_no(pipe_config->hw.enable), context);
+
+	if (!pipe_config->hw.enable)
+		goto dump_planes;
+
+	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
+	drm_dbg_kms(&dev_priv->drm,
+		    "active: %s, output_types: %s (0x%x), output format: %s\n",
+		    str_yes_no(pipe_config->hw.active),
+		    buf, pipe_config->output_types,
+		    output_formats(pipe_config->output_format));
+
+	drm_dbg_kms(&dev_priv->drm,
+		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
+		    transcoder_name(pipe_config->cpu_transcoder),
+		    pipe_config->pipe_bpp, pipe_config->dither);
+
+	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
+		    transcoder_name(pipe_config->mst_master_transcoder));
+
+	drm_dbg_kms(&dev_priv->drm,
+		    "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
+		    transcoder_name(pipe_config->master_transcoder),
+		    pipe_config->sync_mode_slaves_mask);
+
+	drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n",
+		    intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
+		    intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
+		    pipe_config->bigjoiner_pipes);
+
+	drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
+		    str_enabled_disabled(pipe_config->splitter.enable),
+		    pipe_config->splitter.link_count,
+		    pipe_config->splitter.pixel_overlap);
+
+	if (pipe_config->has_pch_encoder)
+		intel_dump_m_n_config(pipe_config, "fdi",
+				      pipe_config->fdi_lanes,
+				      &pipe_config->fdi_m_n);
+
+	if (intel_crtc_has_dp_encoder(pipe_config)) {
+		intel_dump_m_n_config(pipe_config, "dp m_n",
+				      pipe_config->lane_count,
+				      &pipe_config->dp_m_n);
+		intel_dump_m_n_config(pipe_config, "dp m2_n2",
+				      pipe_config->lane_count,
+				      &pipe_config->dp_m2_n2);
+	}
+
+	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
+		    pipe_config->framestart_delay, pipe_config->msa_timing_delay);
+
+	drm_dbg_kms(&dev_priv->drm,
+		    "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
+		    pipe_config->has_audio, pipe_config->has_infoframe,
+		    pipe_config->infoframes.enable);
+
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
+		drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
+			    pipe_config->infoframes.gcp);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
+		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
+	if (pipe_config->infoframes.enable &
+	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
+		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
+
+	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
+		    str_yes_no(pipe_config->vrr.enable),
+		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
+		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
+		    pipe_config->vrr.flipline,
+		    intel_vrr_vmin_vblank_start(pipe_config),
+		    intel_vrr_vmax_vblank_start(pipe_config));
+
+	drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n",
+		    DRM_MODE_ARG(&pipe_config->hw.mode));
+	drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n",
+		    DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
+	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
+	drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n",
+		    DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
+	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
+	drm_dbg_kms(&dev_priv->drm,
+		    "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
+		    pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
+		    pipe_config->pixel_rate);
+
+	drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
+		    pipe_config->linetime, pipe_config->ips_linetime);
+
+	if (DISPLAY_VER(dev_priv) >= 9)
+		drm_dbg_kms(&dev_priv->drm,
+			    "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
+			    crtc->num_scalers,
+			    pipe_config->scaler_state.scaler_users,
+			    pipe_config->scaler_state.scaler_id);
+
+	if (HAS_GMCH(dev_priv))
+		drm_dbg_kms(&dev_priv->drm,
+			    "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
+			    pipe_config->gmch_pfit.control,
+			    pipe_config->gmch_pfit.pgm_ratios,
+			    pipe_config->gmch_pfit.lvds_border_bits);
+	else
+		drm_dbg_kms(&dev_priv->drm,
+			    "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
+			    DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
+			    str_enabled_disabled(pipe_config->pch_pfit.enabled),
+			    str_yes_no(pipe_config->pch_pfit.force_thru));
+
+	drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
+		    pipe_config->ips_enabled, pipe_config->double_wide,
+		    pipe_config->has_drrs);
+
+	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
+
+	if (IS_CHERRYVIEW(dev_priv))
+		drm_dbg_kms(&dev_priv->drm,
+			    "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
+			    pipe_config->cgm_mode, pipe_config->gamma_mode,
+			    pipe_config->gamma_enable, pipe_config->csc_enable);
+	else
+		drm_dbg_kms(&dev_priv->drm,
+			    "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
+			    pipe_config->csc_mode, pipe_config->gamma_mode,
+			    pipe_config->gamma_enable, pipe_config->csc_enable);
+
+	drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
+		    pipe_config->hw.degamma_lut ?
+		    drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
+		    pipe_config->hw.gamma_lut ?
+		    drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
+
+dump_planes:
+	if (!state)
+		return;
+
+	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
+		if (plane->pipe == crtc->pipe)
+			intel_dump_plane_state(plane_state);
+	}
+}
diff --git a/drivers/gpu/drm/i915/display/intel_pipe_config_dump.h b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.h
new file mode 100644
index 000000000000..20bbe11f0527
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_PIPE_CONFIG_DUMP_H__
+#define __INTEL_PIPE_CONFIG_DUMP_H__
+
+struct intel_crtc_state;
+struct intel_atomic_state;
+
+void intel_pipe_config_dump(const struct intel_crtc_state *pipe_config,
+			    struct intel_atomic_state *state,
+			    const char *context);
+
+#endif /* __INTEL_PIPE_CONFIG_DUMP_H__ */
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH 7/7] drm/i915/display: split out pipe config dump to a separate file
  2022-06-15 12:48 ` [Intel-gfx] [PATCH 7/7] drm/i915/display: split out pipe config dump " Jani Nikula
@ 2022-06-15 13:14   ` Ville Syrjälä
  2022-06-15 14:25     ` Jani Nikula
  0 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2022-06-15 13:14 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Wed, Jun 15, 2022 at 03:48:01PM +0300, Jani Nikula wrote:
> Declutter intel_display.c by splitting out pipe config dumping to a
> separate file.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/Makefile                 |   1 +
>  drivers/gpu/drm/i915/display/intel_display.c  | 311 +----------------
>  drivers/gpu/drm/i915/display/intel_display.h  |   3 -
>  .../drm/i915/display/intel_modeset_verify.c   |   5 +-
>  .../drm/i915/display/intel_pipe_config_dump.c | 314 ++++++++++++++++++
>  .../drm/i915/display/intel_pipe_config_dump.h |  16 +
>  6 files changed, 338 insertions(+), 312 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index 8b4e5c59ee70..d69881506dc7 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -247,6 +247,7 @@ i915-y += \
>  	display/intel_pch_display.o \
>  	display/intel_pch_refclk.o \
>  	display/intel_pipe_config_compare.o \
> +	display/intel_pipe_config_dump.o \

I would like to get rid of the pipe_config naming here. Just
foo_state_dump() I guess would be good. That would sort of match
the core state_dump() midlayer, which we may want to a) demidlayer
and b) start to use at some point.

>  	display/intel_plane_initial.o \
>  	display/intel_psr.o \
>  	display/intel_quirks.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 093ba6bde105..8741ae5e6108 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -106,6 +106,7 @@
>  #include "intel_pch_refclk.h"
>  #include "intel_pcode.h"
>  #include "intel_pipe_config_compare.h"
> +#include "intel_pipe_config_dump.h"
>  #include "intel_pipe_crc.h"
>  #include "intel_plane_initial.h"
>  #include "intel_pm.h"
> @@ -5059,310 +5060,6 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
>  	return 0;
>  }
>  
> -static void intel_dump_crtc_timings(struct drm_i915_private *i915,
> -				    const struct drm_display_mode *mode)
> -{
> -	drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
> -		    "type: 0x%x flags: 0x%x\n",
> -		    mode->crtc_clock,
> -		    mode->crtc_hdisplay, mode->crtc_hsync_start,
> -		    mode->crtc_hsync_end, mode->crtc_htotal,
> -		    mode->crtc_vdisplay, mode->crtc_vsync_start,
> -		    mode->crtc_vsync_end, mode->crtc_vtotal,
> -		    mode->type, mode->flags);
> -}
> -
> -static void
> -intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
> -		      const char *id, unsigned int lane_count,
> -		      const struct intel_link_m_n *m_n)
> -{
> -	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
> -
> -	drm_dbg_kms(&i915->drm,
> -		    "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
> -		    id, lane_count,
> -		    m_n->data_m, m_n->data_n,
> -		    m_n->link_m, m_n->link_n, m_n->tu);
> -}
> -
> -static void
> -intel_dump_infoframe(struct drm_i915_private *dev_priv,
> -		     const union hdmi_infoframe *frame)
> -{
> -	if (!drm_debug_enabled(DRM_UT_KMS))
> -		return;
> -
> -	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
> -}
> -
> -static void
> -intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
> -		      const struct drm_dp_vsc_sdp *vsc)
> -{
> -	if (!drm_debug_enabled(DRM_UT_KMS))
> -		return;
> -
> -	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
> -}
> -
> -#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
> -
> -static const char * const output_type_str[] = {
> -	OUTPUT_TYPE(UNUSED),
> -	OUTPUT_TYPE(ANALOG),
> -	OUTPUT_TYPE(DVO),
> -	OUTPUT_TYPE(SDVO),
> -	OUTPUT_TYPE(LVDS),
> -	OUTPUT_TYPE(TVOUT),
> -	OUTPUT_TYPE(HDMI),
> -	OUTPUT_TYPE(DP),
> -	OUTPUT_TYPE(EDP),
> -	OUTPUT_TYPE(DSI),
> -	OUTPUT_TYPE(DDI),
> -	OUTPUT_TYPE(DP_MST),
> -};
> -
> -#undef OUTPUT_TYPE
> -
> -static void snprintf_output_types(char *buf, size_t len,
> -				  unsigned int output_types)
> -{
> -	char *str = buf;
> -	int i;
> -
> -	str[0] = '\0';
> -
> -	for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
> -		int r;
> -
> -		if ((output_types & BIT(i)) == 0)
> -			continue;
> -
> -		r = snprintf(str, len, "%s%s",
> -			     str != buf ? "," : "", output_type_str[i]);
> -		if (r >= len)
> -			break;
> -		str += r;
> -		len -= r;
> -
> -		output_types &= ~BIT(i);
> -	}
> -
> -	WARN_ON_ONCE(output_types != 0);
> -}
> -
> -static const char * const output_format_str[] = {
> -	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
> -	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
> -	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
> -};
> -
> -static const char *output_formats(enum intel_output_format format)
> -{
> -	if (format >= ARRAY_SIZE(output_format_str))
> -		return "invalid";
> -	return output_format_str[format];
> -}
> -
> -static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
> -{
> -	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> -	struct drm_i915_private *i915 = to_i915(plane->base.dev);
> -	const struct drm_framebuffer *fb = plane_state->hw.fb;
> -
> -	if (!fb) {
> -		drm_dbg_kms(&i915->drm,
> -			    "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
> -			    plane->base.base.id, plane->base.name,
> -			    str_yes_no(plane_state->uapi.visible));
> -		return;
> -	}
> -
> -	drm_dbg_kms(&i915->drm,
> -		    "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
> -		    plane->base.base.id, plane->base.name,
> -		    fb->base.id, fb->width, fb->height, &fb->format->format,
> -		    fb->modifier, str_yes_no(plane_state->uapi.visible));
> -	drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
> -		    plane_state->hw.rotation, plane_state->scaler_id);
> -	if (plane_state->uapi.visible)
> -		drm_dbg_kms(&i915->drm,
> -			    "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
> -			    DRM_RECT_FP_ARG(&plane_state->uapi.src),
> -			    DRM_RECT_ARG(&plane_state->uapi.dst));
> -}
> -
> -void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
> -			    struct intel_atomic_state *state,
> -			    const char *context)
> -{
> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	const struct intel_plane_state *plane_state;
> -	struct intel_plane *plane;
> -	char buf[64];
> -	int i;
> -
> -	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
> -		    crtc->base.base.id, crtc->base.name,
> -		    str_yes_no(pipe_config->hw.enable), context);
> -
> -	if (!pipe_config->hw.enable)
> -		goto dump_planes;
> -
> -	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
> -	drm_dbg_kms(&dev_priv->drm,
> -		    "active: %s, output_types: %s (0x%x), output format: %s\n",
> -		    str_yes_no(pipe_config->hw.active),
> -		    buf, pipe_config->output_types,
> -		    output_formats(pipe_config->output_format));
> -
> -	drm_dbg_kms(&dev_priv->drm,
> -		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
> -		    transcoder_name(pipe_config->cpu_transcoder),
> -		    pipe_config->pipe_bpp, pipe_config->dither);
> -
> -	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
> -		    transcoder_name(pipe_config->mst_master_transcoder));
> -
> -	drm_dbg_kms(&dev_priv->drm,
> -		    "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
> -		    transcoder_name(pipe_config->master_transcoder),
> -		    pipe_config->sync_mode_slaves_mask);
> -
> -	drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n",
> -		    intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
> -		    intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
> -		    pipe_config->bigjoiner_pipes);
> -
> -	drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
> -		    str_enabled_disabled(pipe_config->splitter.enable),
> -		    pipe_config->splitter.link_count,
> -		    pipe_config->splitter.pixel_overlap);
> -
> -	if (pipe_config->has_pch_encoder)
> -		intel_dump_m_n_config(pipe_config, "fdi",
> -				      pipe_config->fdi_lanes,
> -				      &pipe_config->fdi_m_n);
> -
> -	if (intel_crtc_has_dp_encoder(pipe_config)) {
> -		intel_dump_m_n_config(pipe_config, "dp m_n",
> -				      pipe_config->lane_count,
> -				      &pipe_config->dp_m_n);
> -		intel_dump_m_n_config(pipe_config, "dp m2_n2",
> -				      pipe_config->lane_count,
> -				      &pipe_config->dp_m2_n2);
> -	}
> -
> -	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
> -		    pipe_config->framestart_delay, pipe_config->msa_timing_delay);
> -
> -	drm_dbg_kms(&dev_priv->drm,
> -		    "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
> -		    pipe_config->has_audio, pipe_config->has_infoframe,
> -		    pipe_config->infoframes.enable);
> -
> -	if (pipe_config->infoframes.enable &
> -	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
> -		drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
> -			    pipe_config->infoframes.gcp);
> -	if (pipe_config->infoframes.enable &
> -	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
> -		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
> -	if (pipe_config->infoframes.enable &
> -	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
> -		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
> -	if (pipe_config->infoframes.enable &
> -	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
> -		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
> -	if (pipe_config->infoframes.enable &
> -	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
> -		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> -	if (pipe_config->infoframes.enable &
> -	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
> -		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> -	if (pipe_config->infoframes.enable &
> -	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
> -		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
> -
> -	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
> -		    str_yes_no(pipe_config->vrr.enable),
> -		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
> -		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
> -		    pipe_config->vrr.flipline,
> -		    intel_vrr_vmin_vblank_start(pipe_config),
> -		    intel_vrr_vmax_vblank_start(pipe_config));
> -
> -	drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n",
> -		    DRM_MODE_ARG(&pipe_config->hw.mode));
> -	drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n",
> -		    DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
> -	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
> -	drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n",
> -		    DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
> -	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
> -	drm_dbg_kms(&dev_priv->drm,
> -		    "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
> -		    pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
> -		    pipe_config->pixel_rate);
> -
> -	drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
> -		    pipe_config->linetime, pipe_config->ips_linetime);
> -
> -	if (DISPLAY_VER(dev_priv) >= 9)
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
> -			    crtc->num_scalers,
> -			    pipe_config->scaler_state.scaler_users,
> -			    pipe_config->scaler_state.scaler_id);
> -
> -	if (HAS_GMCH(dev_priv))
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
> -			    pipe_config->gmch_pfit.control,
> -			    pipe_config->gmch_pfit.pgm_ratios,
> -			    pipe_config->gmch_pfit.lvds_border_bits);
> -	else
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
> -			    DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
> -			    str_enabled_disabled(pipe_config->pch_pfit.enabled),
> -			    str_yes_no(pipe_config->pch_pfit.force_thru));
> -
> -	drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
> -		    pipe_config->ips_enabled, pipe_config->double_wide,
> -		    pipe_config->has_drrs);
> -
> -	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
> -
> -	if (IS_CHERRYVIEW(dev_priv))
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
> -			    pipe_config->cgm_mode, pipe_config->gamma_mode,
> -			    pipe_config->gamma_enable, pipe_config->csc_enable);
> -	else
> -		drm_dbg_kms(&dev_priv->drm,
> -			    "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
> -			    pipe_config->csc_mode, pipe_config->gamma_mode,
> -			    pipe_config->gamma_enable, pipe_config->csc_enable);
> -
> -	drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
> -		    pipe_config->hw.degamma_lut ?
> -		    drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
> -		    pipe_config->hw.gamma_lut ?
> -		    drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
> -
> -dump_planes:
> -	if (!state)
> -		return;
> -
> -	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> -		if (plane->pipe == crtc->pipe)
> -			intel_dump_plane_state(plane_state);
> -	}
> -}
> -
>  static bool check_digital_port_conflicts(struct intel_atomic_state *state)
>  {
>  	struct drm_device *dev = state->base.dev;
> @@ -6823,7 +6520,7 @@ static int intel_atomic_check(struct drm_device *dev,
>  		    !new_crtc_state->update_pipe)
>  			continue;
>  
> -		intel_dump_pipe_config(new_crtc_state, state,
> +		intel_pipe_config_dump(new_crtc_state, state,
>  				       intel_crtc_needs_modeset(new_crtc_state) ?
>  				       "[modeset]" : "[fastset]");
>  	}
> @@ -6840,7 +6537,7 @@ static int intel_atomic_check(struct drm_device *dev,
>  	 */
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>  					    new_crtc_state, i)
> -		intel_dump_pipe_config(new_crtc_state, state, "[failed]");
> +		intel_pipe_config_dump(new_crtc_state, state, "[failed]");
>  
>  	return ret;
>  }
> @@ -9320,7 +9017,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
>  			to_intel_crtc_state(crtc->base.state);
>  
>  		intel_sanitize_crtc(crtc, ctx);
> -		intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
> +		intel_pipe_config_dump(crtc_state, NULL, "[setup_hw_state]");
>  	}
>  
>  	intel_modeset_update_connector_atomic_state(dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index e827c84ece56..68477eb82049 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -560,9 +560,6 @@ bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
>  u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
>  struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
>  bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
> -void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
> -			    struct intel_atomic_state *state,
> -			    const char *context);
>  
>  void intel_plane_destroy(struct drm_plane *plane);
>  void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> index fd752c61d854..de034ccef289 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
> @@ -15,6 +15,7 @@
>  #include "intel_fdi.h"
>  #include "intel_modeset_verify.h"
>  #include "intel_pipe_config_compare.h"
> +#include "intel_pipe_config_dump.h"
>  #include "intel_pm.h"
>  #include "intel_snps_phy.h"
>  
> @@ -217,8 +218,8 @@ verify_crtc_state(struct intel_crtc *crtc,
>  	if (!intel_pipe_config_compare(new_crtc_state,
>  				       pipe_config, false)) {
>  		I915_STATE_WARN(1, "pipe state doesn't match!\n");
> -		intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
> -		intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
> +		intel_pipe_config_dump(pipe_config, NULL, "[hw state]");
> +		intel_pipe_config_dump(new_crtc_state, NULL, "[sw state]");
>  	}
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_config_dump.c b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
> new file mode 100644
> index 000000000000..c290cf009407
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
> @@ -0,0 +1,314 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "intel_display_types.h"
> +#include "intel_hdmi.h"
> +#include "intel_pipe_config_dump.h"
> +#include "intel_vrr.h"
> +
> +static void intel_dump_crtc_timings(struct drm_i915_private *i915,
> +				    const struct drm_display_mode *mode)
> +{
> +	drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
> +		    "type: 0x%x flags: 0x%x\n",
> +		    mode->crtc_clock,
> +		    mode->crtc_hdisplay, mode->crtc_hsync_start,
> +		    mode->crtc_hsync_end, mode->crtc_htotal,
> +		    mode->crtc_vdisplay, mode->crtc_vsync_start,
> +		    mode->crtc_vsync_end, mode->crtc_vtotal,
> +		    mode->type, mode->flags);
> +}
> +
> +static void
> +intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
> +		      const char *id, unsigned int lane_count,
> +		      const struct intel_link_m_n *m_n)
> +{
> +	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
> +
> +	drm_dbg_kms(&i915->drm,
> +		    "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
> +		    id, lane_count,
> +		    m_n->data_m, m_n->data_n,
> +		    m_n->link_m, m_n->link_n, m_n->tu);
> +}
> +
> +static void
> +intel_dump_infoframe(struct drm_i915_private *dev_priv,
> +		     const union hdmi_infoframe *frame)
> +{
> +	if (!drm_debug_enabled(DRM_UT_KMS))
> +		return;
> +
> +	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
> +}
> +
> +static void
> +intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
> +		      const struct drm_dp_vsc_sdp *vsc)
> +{
> +	if (!drm_debug_enabled(DRM_UT_KMS))
> +		return;
> +
> +	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
> +}
> +
> +#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
> +
> +static const char * const output_type_str[] = {
> +	OUTPUT_TYPE(UNUSED),
> +	OUTPUT_TYPE(ANALOG),
> +	OUTPUT_TYPE(DVO),
> +	OUTPUT_TYPE(SDVO),
> +	OUTPUT_TYPE(LVDS),
> +	OUTPUT_TYPE(TVOUT),
> +	OUTPUT_TYPE(HDMI),
> +	OUTPUT_TYPE(DP),
> +	OUTPUT_TYPE(EDP),
> +	OUTPUT_TYPE(DSI),
> +	OUTPUT_TYPE(DDI),
> +	OUTPUT_TYPE(DP_MST),
> +};
> +
> +#undef OUTPUT_TYPE
> +
> +static void snprintf_output_types(char *buf, size_t len,
> +				  unsigned int output_types)
> +{
> +	char *str = buf;
> +	int i;
> +
> +	str[0] = '\0';
> +
> +	for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
> +		int r;
> +
> +		if ((output_types & BIT(i)) == 0)
> +			continue;
> +
> +		r = snprintf(str, len, "%s%s",
> +			     str != buf ? "," : "", output_type_str[i]);
> +		if (r >= len)
> +			break;
> +		str += r;
> +		len -= r;
> +
> +		output_types &= ~BIT(i);
> +	}
> +
> +	WARN_ON_ONCE(output_types != 0);
> +}
> +
> +static const char * const output_format_str[] = {
> +	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
> +	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
> +	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
> +};
> +
> +static const char *output_formats(enum intel_output_format format)
> +{
> +	if (format >= ARRAY_SIZE(output_format_str))
> +		return "invalid";
> +	return output_format_str[format];
> +}
> +
> +static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
> +{
> +	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> +	struct drm_i915_private *i915 = to_i915(plane->base.dev);
> +	const struct drm_framebuffer *fb = plane_state->hw.fb;
> +
> +	if (!fb) {
> +		drm_dbg_kms(&i915->drm,
> +			    "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
> +			    plane->base.base.id, plane->base.name,
> +			    str_yes_no(plane_state->uapi.visible));
> +		return;
> +	}
> +
> +	drm_dbg_kms(&i915->drm,
> +		    "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
> +		    plane->base.base.id, plane->base.name,
> +		    fb->base.id, fb->width, fb->height, &fb->format->format,
> +		    fb->modifier, str_yes_no(plane_state->uapi.visible));
> +	drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
> +		    plane_state->hw.rotation, plane_state->scaler_id);
> +	if (plane_state->uapi.visible)
> +		drm_dbg_kms(&i915->drm,
> +			    "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
> +			    DRM_RECT_FP_ARG(&plane_state->uapi.src),
> +			    DRM_RECT_ARG(&plane_state->uapi.dst));
> +}
> +
> +void intel_pipe_config_dump(const struct intel_crtc_state *pipe_config,
> +			    struct intel_atomic_state *state,
> +			    const char *context)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct intel_plane_state *plane_state;
> +	struct intel_plane *plane;
> +	char buf[64];
> +	int i;
> +
> +	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
> +		    crtc->base.base.id, crtc->base.name,
> +		    str_yes_no(pipe_config->hw.enable), context);
> +
> +	if (!pipe_config->hw.enable)
> +		goto dump_planes;
> +
> +	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
> +	drm_dbg_kms(&dev_priv->drm,
> +		    "active: %s, output_types: %s (0x%x), output format: %s\n",
> +		    str_yes_no(pipe_config->hw.active),
> +		    buf, pipe_config->output_types,
> +		    output_formats(pipe_config->output_format));
> +
> +	drm_dbg_kms(&dev_priv->drm,
> +		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
> +		    transcoder_name(pipe_config->cpu_transcoder),
> +		    pipe_config->pipe_bpp, pipe_config->dither);
> +
> +	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
> +		    transcoder_name(pipe_config->mst_master_transcoder));
> +
> +	drm_dbg_kms(&dev_priv->drm,
> +		    "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
> +		    transcoder_name(pipe_config->master_transcoder),
> +		    pipe_config->sync_mode_slaves_mask);
> +
> +	drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n",
> +		    intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
> +		    intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
> +		    pipe_config->bigjoiner_pipes);
> +
> +	drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
> +		    str_enabled_disabled(pipe_config->splitter.enable),
> +		    pipe_config->splitter.link_count,
> +		    pipe_config->splitter.pixel_overlap);
> +
> +	if (pipe_config->has_pch_encoder)
> +		intel_dump_m_n_config(pipe_config, "fdi",
> +				      pipe_config->fdi_lanes,
> +				      &pipe_config->fdi_m_n);
> +
> +	if (intel_crtc_has_dp_encoder(pipe_config)) {
> +		intel_dump_m_n_config(pipe_config, "dp m_n",
> +				      pipe_config->lane_count,
> +				      &pipe_config->dp_m_n);
> +		intel_dump_m_n_config(pipe_config, "dp m2_n2",
> +				      pipe_config->lane_count,
> +				      &pipe_config->dp_m2_n2);
> +	}
> +
> +	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
> +		    pipe_config->framestart_delay, pipe_config->msa_timing_delay);
> +
> +	drm_dbg_kms(&dev_priv->drm,
> +		    "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
> +		    pipe_config->has_audio, pipe_config->has_infoframe,
> +		    pipe_config->infoframes.enable);
> +
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
> +		drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
> +			    pipe_config->infoframes.gcp);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
> +	if (pipe_config->infoframes.enable &
> +	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
> +		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
> +
> +	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
> +		    str_yes_no(pipe_config->vrr.enable),
> +		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
> +		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
> +		    pipe_config->vrr.flipline,
> +		    intel_vrr_vmin_vblank_start(pipe_config),
> +		    intel_vrr_vmax_vblank_start(pipe_config));
> +
> +	drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n",
> +		    DRM_MODE_ARG(&pipe_config->hw.mode));
> +	drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n",
> +		    DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
> +	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
> +	drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n",
> +		    DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
> +	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
> +	drm_dbg_kms(&dev_priv->drm,
> +		    "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
> +		    pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
> +		    pipe_config->pixel_rate);
> +
> +	drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
> +		    pipe_config->linetime, pipe_config->ips_linetime);
> +
> +	if (DISPLAY_VER(dev_priv) >= 9)
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
> +			    crtc->num_scalers,
> +			    pipe_config->scaler_state.scaler_users,
> +			    pipe_config->scaler_state.scaler_id);
> +
> +	if (HAS_GMCH(dev_priv))
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
> +			    pipe_config->gmch_pfit.control,
> +			    pipe_config->gmch_pfit.pgm_ratios,
> +			    pipe_config->gmch_pfit.lvds_border_bits);
> +	else
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
> +			    DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
> +			    str_enabled_disabled(pipe_config->pch_pfit.enabled),
> +			    str_yes_no(pipe_config->pch_pfit.force_thru));
> +
> +	drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
> +		    pipe_config->ips_enabled, pipe_config->double_wide,
> +		    pipe_config->has_drrs);
> +
> +	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
> +
> +	if (IS_CHERRYVIEW(dev_priv))
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
> +			    pipe_config->cgm_mode, pipe_config->gamma_mode,
> +			    pipe_config->gamma_enable, pipe_config->csc_enable);
> +	else
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
> +			    pipe_config->csc_mode, pipe_config->gamma_mode,
> +			    pipe_config->gamma_enable, pipe_config->csc_enable);
> +
> +	drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
> +		    pipe_config->hw.degamma_lut ?
> +		    drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
> +		    pipe_config->hw.gamma_lut ?
> +		    drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
> +
> +dump_planes:
> +	if (!state)
> +		return;
> +
> +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
> +		if (plane->pipe == crtc->pipe)
> +			intel_dump_plane_state(plane_state);
> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_config_dump.h b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.h
> new file mode 100644
> index 000000000000..20bbe11f0527
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_PIPE_CONFIG_DUMP_H__
> +#define __INTEL_PIPE_CONFIG_DUMP_H__
> +
> +struct intel_crtc_state;
> +struct intel_atomic_state;
> +
> +void intel_pipe_config_dump(const struct intel_crtc_state *pipe_config,
> +			    struct intel_atomic_state *state,
> +			    const char *context);
> +
> +#endif /* __INTEL_PIPE_CONFIG_DUMP_H__ */
> -- 
> 2.30.2

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
                   ` (6 preceding siblings ...)
  2022-06-15 12:48 ` [Intel-gfx] [PATCH 7/7] drm/i915/display: split out pipe config dump " Jani Nikula
@ 2022-06-15 13:27 ` Ville Syrjälä
  2022-06-15 14:31   ` Jani Nikula
  2022-06-15 13:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
                   ` (3 subsequent siblings)
  11 siblings, 1 reply; 18+ messages in thread
From: Ville Syrjälä @ 2022-06-15 13:27 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Wed, Jun 15, 2022 at 03:47:54PM +0300, Jani Nikula wrote:
> The state verification and pipe config comparison/dumping are fairly
> isolated pieces of code within intel_display.c. Move them to separate
> files in a long overdue cleanup.
> 
> Jani Nikula (7):
>   drm/i915/wm: move wm state verification to intel_pm.c
>   drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.c
>   drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings
>   drm/i915/mpllb: move mpllb state check to intel_snps_phy.c

I'd perhaps go for foo_state_verify() naming convention. Would
match the foo_state_dump() naming convention I suggested
for the dumping stuff.

Apart from that these ^ four are
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>   drm/i915/display: split out modeset verification code

I really hate some of that code. I guess hiding it is one option :P
This one ^ is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

>   drm/i915/display: split out pipe config compare to a separate file

Not entirely sure I like moving this one. The fastset stuff
within needs to stay in sync with the fastset codepaths which
are in intel_display.c. Not sure if we risk more bugs if it's
too well hidden...

>   drm/i915/display: split out pipe config dump to a separate file
> 
>  drivers/gpu/drm/i915/Makefile                 |    3 +
>  drivers/gpu/drm/i915/display/intel_display.c  | 1373 +----------------
>  drivers/gpu/drm/i915/display/intel_display.h  |    3 +
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   88 ++
>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |    5 +
>  .../drm/i915/display/intel_modeset_verify.c   |  247 +++
>  .../drm/i915/display/intel_modeset_verify.h   |   21 +
>  .../i915/display/intel_pipe_config_compare.c  |  581 +++++++
>  .../i915/display/intel_pipe_config_compare.h  |   17 +
>  .../drm/i915/display/intel_pipe_config_dump.c |  314 ++++
>  .../drm/i915/display/intel_pipe_config_dump.h |   16 +
>  drivers/gpu/drm/i915/display/intel_snps_phy.c |   43 +
>  drivers/gpu/drm/i915/display/intel_snps_phy.h |    5 +-
>  drivers/gpu/drm/i915/intel_pm.c               |  138 +-
>  drivers/gpu/drm/i915/intel_pm.h               |   14 +-
>  15 files changed, 1482 insertions(+), 1386 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.h
>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_compare.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_compare.h
>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.h
> 
> -- 
> 2.30.2

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: split out verifation, compare and dump from intel_display.c
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
                   ` (7 preceding siblings ...)
  2022-06-15 13:27 ` [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Ville Syrjälä
@ 2022-06-15 13:30 ` Patchwork
  2022-06-15 13:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
                   ` (2 subsequent siblings)
  11 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-06-15 13:30 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/display: split out verifation, compare and dump from intel_display.c
URL   : https://patchwork.freedesktop.org/series/105156/
State : warning

== Summary ==

Error: dim checkpatch failed
e82e76f8105d drm/i915/wm: move wm state verification to intel_pm.c
63ac5d8ed86c drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.c
2e52ab5d8db4 drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings
-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__name' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_display.c:6604:
+#define MPLLB_CHECK(__name)						\
+	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\
+			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
+			crtc->base.base.id, crtc->base.name,		\
+			__stringify(__name),				\
+			mpllb_sw_state->__name, mpllb_hw_state.__name)

-:28: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '__name' may be better as '(__name)' to avoid precedence issues
#28: FILE: drivers/gpu/drm/i915/display/intel_display.c:6604:
+#define MPLLB_CHECK(__name)						\
+	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\
+			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
+			crtc->base.base.id, crtc->base.name,		\
+			__stringify(__name),				\
+			mpllb_sw_state->__name, mpllb_hw_state.__name)

total: 0 errors, 0 warnings, 2 checks, 20 lines checked
97bfe3a05e43 drm/i915/mpllb: move mpllb state check to intel_snps_phy.c
-:102: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__name' - possible side-effects?
#102: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:835:
+#define MPLLB_CHECK(__name)						\
+	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\
+			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
+			crtc->base.base.id, crtc->base.name,		\
+			__stringify(__name),				\
+			mpllb_sw_state->__name, mpllb_hw_state.__name)

-:102: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '__name' may be better as '(__name)' to avoid precedence issues
#102: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:835:
+#define MPLLB_CHECK(__name)						\
+	I915_STATE_WARN(mpllb_sw_state->__name != mpllb_hw_state.__name,	\
+			"[CRTC:%d:%s] mismatch in MPLLB: %s (expected 0x%08x, found 0x%08x)", \
+			crtc->base.base.id, crtc->base.name,		\
+			__stringify(__name),				\
+			mpllb_sw_state->__name, mpllb_hw_state.__name)

total: 0 errors, 0 warnings, 2 checks, 121 lines checked
874079603084 drm/i915/display: split out modeset verification code
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:359: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#359: 
new file mode 100644

-:453: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#453: FILE: drivers/gpu/drm/i915/display/intel_modeset_verify.c:90:
+		int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),

total: 0 errors, 2 warnings, 0 checks, 585 lines checked
c55b940f4017 drm/i915/display: split out pipe config compare to a separate file
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:640: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#640: 
new file mode 100644

-:822: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#822: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:178:
+#define PIPE_CONF_CHECK_X(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected 0x%08x, found 0x%08x)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)

-:822: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#822: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:178:
+#define PIPE_CONF_CHECK_X(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected 0x%08x, found 0x%08x)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)

-:832: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#832: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:188:
+#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
+	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected 0x%08x, found 0x%08x)", \
+				     current_config->name & (mask), \
+				     pipe_config->name & (mask)); \
+		ret = false; \
+	} \
+} while (0)

-:832: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#832: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:188:
+#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
+	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected 0x%08x, found 0x%08x)", \
+				     current_config->name & (mask), \
+				     pipe_config->name & (mask)); \
+		ret = false; \
+	} \
+} while (0)

-:832: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects?
#832: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:188:
+#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
+	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected 0x%08x, found 0x%08x)", \
+				     current_config->name & (mask), \
+				     pipe_config->name & (mask)); \
+		ret = false; \
+	} \
+} while (0)

-:842: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#842: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:198:
+#define PIPE_CONF_CHECK_I(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected %i, found %i)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)

-:842: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#842: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:198:
+#define PIPE_CONF_CHECK_I(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected %i, found %i)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)

-:852: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#852: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:208:
+#define PIPE_CONF_CHECK_BOOL(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc,  __stringify(name), \
+				     "(expected %s, found %s)", \
+				     str_yes_no(current_config->name), \
+				     str_yes_no(pipe_config->name)); \
+		ret = false; \
+	} \
+} while (0)

-:852: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#852: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:208:
+#define PIPE_CONF_CHECK_BOOL(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc,  __stringify(name), \
+				     "(expected %s, found %s)", \
+				     str_yes_no(current_config->name), \
+				     str_yes_no(pipe_config->name)); \
+		ret = false; \
+	} \
+} while (0)

-:867: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#867: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:223:
+#define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
+	if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
+		PIPE_CONF_CHECK_BOOL(name); \
+	} else { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
+				     str_yes_no(current_config->name), \
+				     str_yes_no(pipe_config->name)); \
+		ret = false; \
+	} \
+} while (0)

-:867: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#867: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:223:
+#define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
+	if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
+		PIPE_CONF_CHECK_BOOL(name); \
+	} else { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
+				     str_yes_no(current_config->name), \
+				     str_yes_no(pipe_config->name)); \
+		ret = false; \
+	} \
+} while (0)

-:872: WARNING:LONG_LINE: line length of 129 exceeds 100 columns
#872: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:228:
+				     "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \

-:879: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#879: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:235:
+#define PIPE_CONF_CHECK_P(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected %p, found %p)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)

-:879: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#879: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:235:
+#define PIPE_CONF_CHECK_P(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected %p, found %p)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)

-:889: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#889: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:245:
+#define PIPE_CONF_CHECK_M_N(name) do { \
+	if (!intel_compare_link_m_n(&current_config->name, \
+				    &pipe_config->name,\
+				    !fastset)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected tu %i data %i/%i link %i/%i, " \
+				     "found tu %i, data %i/%i link %i/%i)", \
+				     current_config->name.tu, \
+				     current_config->name.data_m, \
+				     current_config->name.data_n, \
+				     current_config->name.link_m, \
+				     current_config->name.link_n, \
+				     pipe_config->name.tu, \
+				     pipe_config->name.data_m, \
+				     pipe_config->name.data_n, \
+				     pipe_config->name.link_m, \
+				     pipe_config->name.link_n); \
+		ret = false; \
+	} \
+} while (0)

-:889: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#889: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:245:
+#define PIPE_CONF_CHECK_M_N(name) do { \
+	if (!intel_compare_link_m_n(&current_config->name, \
+				    &pipe_config->name,\
+				    !fastset)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected tu %i data %i/%i link %i/%i, " \
+				     "found tu %i, data %i/%i link %i/%i)", \
+				     current_config->name.tu, \
+				     current_config->name.data_m, \
+				     current_config->name.data_n, \
+				     current_config->name.link_m, \
+				     current_config->name.link_n, \
+				     pipe_config->name.tu, \
+				     pipe_config->name.data_m, \
+				     pipe_config->name.data_n, \
+				     pipe_config->name.link_m, \
+				     pipe_config->name.link_n); \
+		ret = false; \
+	} \
+} while (0)

-:910: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#910: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:266:
+#define PIPE_CONF_CHECK_TIMINGS(name) do { \
+	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_htotal); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
+	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
+	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
+} while (0)

-:925: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#925: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:281:
+#define PIPE_CONF_CHECK_RECT(name) do { \
+	PIPE_CONF_CHECK_I(name.x1); \
+	PIPE_CONF_CHECK_I(name.x2); \
+	PIPE_CONF_CHECK_I(name.y1); \
+	PIPE_CONF_CHECK_I(name.y2); \
+} while (0)

-:937: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#937: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:293:
+#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
+	if (!intel_compare_link_m_n(&current_config->name, \
+				    &pipe_config->name, !fastset) && \
+	    !intel_compare_link_m_n(&current_config->alt_name, \
+				    &pipe_config->name, !fastset)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected tu %i data %i/%i link %i/%i, " \
+				     "or tu %i data %i/%i link %i/%i, " \
+				     "found tu %i, data %i/%i link %i/%i)", \
+				     current_config->name.tu, \
+				     current_config->name.data_m, \
+				     current_config->name.data_n, \
+				     current_config->name.link_m, \
+				     current_config->name.link_n, \
+				     current_config->alt_name.tu, \
+				     current_config->alt_name.data_m, \
+				     current_config->alt_name.data_n, \
+				     current_config->alt_name.link_m, \
+				     current_config->alt_name.link_n, \
+				     pipe_config->name.tu, \
+				     pipe_config->name.data_m, \
+				     pipe_config->name.data_n, \
+				     pipe_config->name.link_m, \
+				     pipe_config->name.link_n); \
+		ret = false; \
+	} \
+} while (0)

-:937: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#937: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:293:
+#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
+	if (!intel_compare_link_m_n(&current_config->name, \
+				    &pipe_config->name, !fastset) && \
+	    !intel_compare_link_m_n(&current_config->alt_name, \
+				    &pipe_config->name, !fastset)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected tu %i data %i/%i link %i/%i, " \
+				     "or tu %i data %i/%i link %i/%i, " \
+				     "found tu %i, data %i/%i link %i/%i)", \
+				     current_config->name.tu, \
+				     current_config->name.data_m, \
+				     current_config->name.data_n, \
+				     current_config->name.link_m, \
+				     current_config->name.link_n, \
+				     current_config->alt_name.tu, \
+				     current_config->alt_name.data_m, \
+				     current_config->alt_name.data_n, \
+				     current_config->alt_name.link_m, \
+				     current_config->alt_name.link_n, \
+				     pipe_config->name.tu, \
+				     pipe_config->name.data_m, \
+				     pipe_config->name.data_n, \
+				     pipe_config->name.link_m, \
+				     pipe_config->name.link_n); \
+		ret = false; \
+	} \
+} while (0)

-:937: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'alt_name' - possible side-effects?
#937: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:293:
+#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
+	if (!intel_compare_link_m_n(&current_config->name, \
+				    &pipe_config->name, !fastset) && \
+	    !intel_compare_link_m_n(&current_config->alt_name, \
+				    &pipe_config->name, !fastset)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected tu %i data %i/%i link %i/%i, " \
+				     "or tu %i data %i/%i link %i/%i, " \
+				     "found tu %i, data %i/%i link %i/%i)", \
+				     current_config->name.tu, \
+				     current_config->name.data_m, \
+				     current_config->name.data_n, \
+				     current_config->name.link_m, \
+				     current_config->name.link_n, \
+				     current_config->alt_name.tu, \
+				     current_config->alt_name.data_m, \
+				     current_config->alt_name.data_n, \
+				     current_config->alt_name.link_m, \
+				     current_config->alt_name.link_n, \
+				     pipe_config->name.tu, \
+				     pipe_config->name.data_m, \
+				     pipe_config->name.data_n, \
+				     pipe_config->name.link_m, \
+				     pipe_config->name.link_n); \
+		ret = false; \
+	} \
+} while (0)

-:937: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'alt_name' may be better as '(alt_name)' to avoid precedence issues
#937: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:293:
+#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
+	if (!intel_compare_link_m_n(&current_config->name, \
+				    &pipe_config->name, !fastset) && \
+	    !intel_compare_link_m_n(&current_config->alt_name, \
+				    &pipe_config->name, !fastset)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected tu %i data %i/%i link %i/%i, " \
+				     "or tu %i data %i/%i link %i/%i, " \
+				     "found tu %i, data %i/%i link %i/%i)", \
+				     current_config->name.tu, \
+				     current_config->name.data_m, \
+				     current_config->name.data_n, \
+				     current_config->name.link_m, \
+				     current_config->name.link_n, \
+				     current_config->alt_name.tu, \
+				     current_config->alt_name.data_m, \
+				     current_config->alt_name.data_n, \
+				     current_config->alt_name.link_m, \
+				     current_config->alt_name.link_n, \
+				     pipe_config->name.tu, \
+				     pipe_config->name.data_m, \
+				     pipe_config->name.data_n, \
+				     pipe_config->name.link_m, \
+				     pipe_config->name.link_n); \
+		ret = false; \
+	} \
+} while (0)

-:965: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#965: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:321:
+#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
+	if ((current_config->name ^ pipe_config->name) & (mask)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(%x) (expected %i, found %i)", \
+				     (mask), \
+				     current_config->name & (mask), \
+				     pipe_config->name & (mask)); \
+		ret = false; \
+	} \
+} while (0)

-:965: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#965: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:321:
+#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
+	if ((current_config->name ^ pipe_config->name) & (mask)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(%x) (expected %i, found %i)", \
+				     (mask), \
+				     current_config->name & (mask), \
+				     pipe_config->name & (mask)); \
+		ret = false; \
+	} \
+} while (0)

-:965: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'mask' - possible side-effects?
#965: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:321:
+#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
+	if ((current_config->name ^ pipe_config->name) & (mask)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(%x) (expected %i, found %i)", \
+				     (mask), \
+				     current_config->name & (mask), \
+				     pipe_config->name & (mask)); \
+		ret = false; \
+	} \
+} while (0)

-:976: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#976: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:332:
+#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
+	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected %i, found %i)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)

-:976: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name' may be better as '(name)' to avoid precedence issues
#976: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:332:
+#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) do { \
+	if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name), \
+				     "(expected %i, found %i)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)

-:986: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#986: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:342:
+#define PIPE_CONF_CHECK_INFOFRAME(name) do { \
+	if (!intel_compare_infoframe(&current_config->infoframes.name, \
+				     &pipe_config->infoframes.name)) { \
+		pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
+					       &current_config->infoframes.name, \
+					       &pipe_config->infoframes.name); \
+		ret = false; \
+	} \
+} while (0)

-:996: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name' - possible side-effects?
#996: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:352:
+#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
+	if (!current_config->has_psr && !pipe_config->has_psr && \
+	    !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
+				      &pipe_config->infoframes.name)) { \
+		pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
+						&current_config->infoframes.name, \
+						&pipe_config->infoframes.name); \
+		ret = false; \
+	} \
+} while (0)

-:1007: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name1' - possible side-effects?
#1007: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:363:
+#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
+	if (current_config->name1 != pipe_config->name1) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name1), \
+				"(expected %i, found %i, won't compare lut values)", \
+				current_config->name1, \
+				pipe_config->name1); \
+		ret = false;\
+	} else { \
+		if (!intel_color_lut_equal(current_config->name2, \
+					pipe_config->name2, pipe_config->name1, \
+					bit_precision)) { \
+			pipe_config_mismatch(fastset, crtc, __stringify(name2), \
+					"hw_state doesn't match sw_state"); \
+			ret = false; \
+		} \
+	} \
+} while (0)

-:1007: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name1' may be better as '(name1)' to avoid precedence issues
#1007: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:363:
+#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
+	if (current_config->name1 != pipe_config->name1) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name1), \
+				"(expected %i, found %i, won't compare lut values)", \
+				current_config->name1, \
+				pipe_config->name1); \
+		ret = false;\
+	} else { \
+		if (!intel_color_lut_equal(current_config->name2, \
+					pipe_config->name2, pipe_config->name1, \
+					bit_precision)) { \
+			pipe_config_mismatch(fastset, crtc, __stringify(name2), \
+					"hw_state doesn't match sw_state"); \
+			ret = false; \
+		} \
+	} \
+} while (0)

-:1007: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'name2' - possible side-effects?
#1007: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:363:
+#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
+	if (current_config->name1 != pipe_config->name1) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name1), \
+				"(expected %i, found %i, won't compare lut values)", \
+				current_config->name1, \
+				pipe_config->name1); \
+		ret = false;\
+	} else { \
+		if (!intel_color_lut_equal(current_config->name2, \
+					pipe_config->name2, pipe_config->name1, \
+					bit_precision)) { \
+			pipe_config_mismatch(fastset, crtc, __stringify(name2), \
+					"hw_state doesn't match sw_state"); \
+			ret = false; \
+		} \
+	} \
+} while (0)

-:1007: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'name2' may be better as '(name2)' to avoid precedence issues
#1007: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_compare.c:363:
+#define PIPE_CONF_CHECK_COLOR_LUT(name1, name2, bit_precision) do { \
+	if (current_config->name1 != pipe_config->name1) { \
+		pipe_config_mismatch(fastset, crtc, __stringify(name1), \
+				"(expected %i, found %i, won't compare lut values)", \
+				current_config->name1, \
+				pipe_config->name1); \
+		ret = false;\
+	} else { \
+		if (!intel_color_lut_equal(current_config->name2, \
+					pipe_config->name2, pipe_config->name1, \
+					bit_precision)) { \
+			pipe_config_mismatch(fastset, crtc, __stringify(name2), \
+					"hw_state doesn't match sw_state"); \
+			ret = false; \
+		} \
+	} \
+} while (0)

total: 0 errors, 2 warnings, 32 checks, 1204 lines checked
7acf4374c30b drm/i915/display: split out pipe config dump to a separate file
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
  File "scripts/spdxcheck.py", line 6, in <module>
    from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:412: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#412: 
new file mode 100644

-:475: ERROR:BRACKET_SPACE: space prohibited before open square bracket '['
#475: FILE: drivers/gpu/drm/i915/display/intel_pipe_config_dump.c:59:
+#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x

total: 1 errors, 1 warnings, 0 checks, 704 lines checked



^ permalink raw reply	[flat|nested] 18+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/display: split out verifation, compare and dump from intel_display.c
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
                   ` (8 preceding siblings ...)
  2022-06-15 13:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2022-06-15 13:30 ` Patchwork
  2022-06-15 13:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
  2022-06-15 19:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  11 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-06-15 13:30 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/display: split out verifation, compare and dump from intel_display.c
URL   : https://patchwork.freedesktop.org/series/105156/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.



^ permalink raw reply	[flat|nested] 18+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: split out verifation, compare and dump from intel_display.c
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
                   ` (9 preceding siblings ...)
  2022-06-15 13:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-06-15 13:58 ` Patchwork
  2022-06-15 19:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  11 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-06-15 13:58 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 8620 bytes --]

== Series Details ==

Series: drm/i915/display: split out verifation, compare and dump from intel_display.c
URL   : https://patchwork.freedesktop.org/series/105156/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11759 -> Patchwork_105156v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/index.html

Participating hosts (44 -> 43)
------------------------------

  Additional (1): bat-dg2-8 
  Missing    (2): bat-jsl-2 fi-bdw-samus 

Known issues
------------

  Here are the changes found in Patchwork_105156v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@gem:
    - fi-blb-e6850:       NOTRUN -> [DMESG-FAIL][1] ([i915#4528])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/fi-blb-e6850/igt@i915_selftest@live@gem.html
    - fi-pnv-d510:        NOTRUN -> [DMESG-FAIL][2] ([i915#4528])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/fi-pnv-d510/igt@i915_selftest@live@gem.html

  * igt@i915_selftest@live@gt_engines:
    - fi-rkl-guc:         [PASS][3] -> [INCOMPLETE][4] ([i915#4418])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/fi-rkl-guc/igt@i915_selftest@live@gt_engines.html

  * igt@i915_selftest@live@mman:
    - fi-bdw-5557u:       [PASS][5] -> [INCOMPLETE][6] ([i915#5704])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-bdw-5557u/igt@i915_selftest@live@mman.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/fi-bdw-5557u/igt@i915_selftest@live@mman.html

  * igt@kms_busy@basic@flip:
    - bat-adlp-4:         [PASS][7] -> [DMESG-WARN][8] ([i915#3576]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/bat-adlp-4/igt@kms_busy@basic@flip.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/bat-adlp-4/igt@kms_busy@basic@flip.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
    - fi-tgl-u2:          [PASS][9] -> [DMESG-WARN][10] ([i915#402]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/fi-tgl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html

  * igt@runner@aborted:
    - fi-rkl-guc:         NOTRUN -> [FAIL][11] ([i915#4312])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/fi-rkl-guc/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - {fi-ehl-2}:         [DMESG-WARN][12] ([i915#5122]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_pm_rpm@module-reload:
    - bat-adlp-4:         [DMESG-WARN][14] ([i915#3576]) -> [PASS][15] +2 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/bat-adlp-4/igt@i915_pm_rpm@module-reload.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/bat-adlp-4/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-cfl-guc:         [DMESG-FAIL][16] ([i915#5334]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@requests:
    - fi-pnv-d510:        [DMESG-FAIL][18] ([i915#4528]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-pnv-d510/igt@i915_selftest@live@requests.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/fi-pnv-d510/igt@i915_selftest@live@requests.html
    - fi-blb-e6850:       [DMESG-FAIL][20] ([i915#4528]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-blb-e6850/igt@i915_selftest@live@requests.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/fi-blb-e6850/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@sanitycheck:
    - {bat-dg2-9}:        [DMESG-WARN][22] ([i915#5763]) -> [PASS][23] +4 similar issues
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/bat-dg2-9/igt@i915_selftest@live@sanitycheck.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/bat-dg2-9/igt@i915_selftest@live@sanitycheck.html

  * igt@kms_busy@basic@flip:
    - {bat-adlp-6}:       [DMESG-WARN][24] ([i915#3576]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/bat-adlp-6/igt@kms_busy@basic@flip.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/bat-adlp-6/igt@kms_busy@basic@flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
  [i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5704]: https://gitlab.freedesktop.org/drm/intel/issues/5704
  [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
  [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227


Build changes
-------------

  * Linux: CI_DRM_11759 -> Patchwork_105156v1

  CI-20190529: 20190529
  CI_DRM_11759: fa66b647ce886c01bbe1e9f3017a141e90d87539 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6529: b96bf5a0307fc0bdbf6c8e86872817306e102883 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105156v1: fa66b647ce886c01bbe1e9f3017a141e90d87539 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

62cbed730016 drm/i915/display: split out pipe config dump to a separate file
4e4bd0def66e drm/i915/display: split out pipe config compare to a separate file
f30b6d483951 drm/i915/display: split out modeset verification code
9cd2c2dd537d drm/i915/mpllb: move mpllb state check to intel_snps_phy.c
42e981ffc70a drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings
3508aa62646b drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.c
222b29226598 drm/i915/wm: move wm state verification to intel_pm.c

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/index.html

[-- Attachment #2: Type: text/html, Size: 8253 bytes --]

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH 7/7] drm/i915/display: split out pipe config dump to a separate file
  2022-06-15 13:14   ` Ville Syrjälä
@ 2022-06-15 14:25     ` Jani Nikula
  0 siblings, 0 replies; 18+ messages in thread
From: Jani Nikula @ 2022-06-15 14:25 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Wed, 15 Jun 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Jun 15, 2022 at 03:48:01PM +0300, Jani Nikula wrote:
>> Declutter intel_display.c by splitting out pipe config dumping to a
>> separate file.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/Makefile                 |   1 +
>>  drivers/gpu/drm/i915/display/intel_display.c  | 311 +----------------
>>  drivers/gpu/drm/i915/display/intel_display.h  |   3 -
>>  .../drm/i915/display/intel_modeset_verify.c   |   5 +-
>>  .../drm/i915/display/intel_pipe_config_dump.c | 314 ++++++++++++++++++
>>  .../drm/i915/display/intel_pipe_config_dump.h |  16 +
>>  6 files changed, 338 insertions(+), 312 deletions(-)
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.h
>> 
>> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>> index 8b4e5c59ee70..d69881506dc7 100644
>> --- a/drivers/gpu/drm/i915/Makefile
>> +++ b/drivers/gpu/drm/i915/Makefile
>> @@ -247,6 +247,7 @@ i915-y += \
>>  	display/intel_pch_display.o \
>>  	display/intel_pch_refclk.o \
>>  	display/intel_pipe_config_compare.o \
>> +	display/intel_pipe_config_dump.o \
>
> I would like to get rid of the pipe_config naming here. Just
> foo_state_dump() I guess would be good. That would sort of match
> the core state_dump() midlayer, which we may want to a) demidlayer
> and b) start to use at some point.

I knew the naming would be a point of contention, but I was hoping for a
concrete suggestion. Other than foo, that is. ;)

BR,
Jani.

>
>>  	display/intel_plane_initial.o \
>>  	display/intel_psr.o \
>>  	display/intel_quirks.o \
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 093ba6bde105..8741ae5e6108 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -106,6 +106,7 @@
>>  #include "intel_pch_refclk.h"
>>  #include "intel_pcode.h"
>>  #include "intel_pipe_config_compare.h"
>> +#include "intel_pipe_config_dump.h"
>>  #include "intel_pipe_crc.h"
>>  #include "intel_plane_initial.h"
>>  #include "intel_pm.h"
>> @@ -5059,310 +5060,6 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
>>  	return 0;
>>  }
>>  
>> -static void intel_dump_crtc_timings(struct drm_i915_private *i915,
>> -				    const struct drm_display_mode *mode)
>> -{
>> -	drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
>> -		    "type: 0x%x flags: 0x%x\n",
>> -		    mode->crtc_clock,
>> -		    mode->crtc_hdisplay, mode->crtc_hsync_start,
>> -		    mode->crtc_hsync_end, mode->crtc_htotal,
>> -		    mode->crtc_vdisplay, mode->crtc_vsync_start,
>> -		    mode->crtc_vsync_end, mode->crtc_vtotal,
>> -		    mode->type, mode->flags);
>> -}
>> -
>> -static void
>> -intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
>> -		      const char *id, unsigned int lane_count,
>> -		      const struct intel_link_m_n *m_n)
>> -{
>> -	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
>> -
>> -	drm_dbg_kms(&i915->drm,
>> -		    "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
>> -		    id, lane_count,
>> -		    m_n->data_m, m_n->data_n,
>> -		    m_n->link_m, m_n->link_n, m_n->tu);
>> -}
>> -
>> -static void
>> -intel_dump_infoframe(struct drm_i915_private *dev_priv,
>> -		     const union hdmi_infoframe *frame)
>> -{
>> -	if (!drm_debug_enabled(DRM_UT_KMS))
>> -		return;
>> -
>> -	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
>> -}
>> -
>> -static void
>> -intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
>> -		      const struct drm_dp_vsc_sdp *vsc)
>> -{
>> -	if (!drm_debug_enabled(DRM_UT_KMS))
>> -		return;
>> -
>> -	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
>> -}
>> -
>> -#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
>> -
>> -static const char * const output_type_str[] = {
>> -	OUTPUT_TYPE(UNUSED),
>> -	OUTPUT_TYPE(ANALOG),
>> -	OUTPUT_TYPE(DVO),
>> -	OUTPUT_TYPE(SDVO),
>> -	OUTPUT_TYPE(LVDS),
>> -	OUTPUT_TYPE(TVOUT),
>> -	OUTPUT_TYPE(HDMI),
>> -	OUTPUT_TYPE(DP),
>> -	OUTPUT_TYPE(EDP),
>> -	OUTPUT_TYPE(DSI),
>> -	OUTPUT_TYPE(DDI),
>> -	OUTPUT_TYPE(DP_MST),
>> -};
>> -
>> -#undef OUTPUT_TYPE
>> -
>> -static void snprintf_output_types(char *buf, size_t len,
>> -				  unsigned int output_types)
>> -{
>> -	char *str = buf;
>> -	int i;
>> -
>> -	str[0] = '\0';
>> -
>> -	for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
>> -		int r;
>> -
>> -		if ((output_types & BIT(i)) == 0)
>> -			continue;
>> -
>> -		r = snprintf(str, len, "%s%s",
>> -			     str != buf ? "," : "", output_type_str[i]);
>> -		if (r >= len)
>> -			break;
>> -		str += r;
>> -		len -= r;
>> -
>> -		output_types &= ~BIT(i);
>> -	}
>> -
>> -	WARN_ON_ONCE(output_types != 0);
>> -}
>> -
>> -static const char * const output_format_str[] = {
>> -	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
>> -	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
>> -	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
>> -};
>> -
>> -static const char *output_formats(enum intel_output_format format)
>> -{
>> -	if (format >= ARRAY_SIZE(output_format_str))
>> -		return "invalid";
>> -	return output_format_str[format];
>> -}
>> -
>> -static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
>> -{
>> -	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
>> -	struct drm_i915_private *i915 = to_i915(plane->base.dev);
>> -	const struct drm_framebuffer *fb = plane_state->hw.fb;
>> -
>> -	if (!fb) {
>> -		drm_dbg_kms(&i915->drm,
>> -			    "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
>> -			    plane->base.base.id, plane->base.name,
>> -			    str_yes_no(plane_state->uapi.visible));
>> -		return;
>> -	}
>> -
>> -	drm_dbg_kms(&i915->drm,
>> -		    "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
>> -		    plane->base.base.id, plane->base.name,
>> -		    fb->base.id, fb->width, fb->height, &fb->format->format,
>> -		    fb->modifier, str_yes_no(plane_state->uapi.visible));
>> -	drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
>> -		    plane_state->hw.rotation, plane_state->scaler_id);
>> -	if (plane_state->uapi.visible)
>> -		drm_dbg_kms(&i915->drm,
>> -			    "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
>> -			    DRM_RECT_FP_ARG(&plane_state->uapi.src),
>> -			    DRM_RECT_ARG(&plane_state->uapi.dst));
>> -}
>> -
>> -void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>> -			    struct intel_atomic_state *state,
>> -			    const char *context)
>> -{
>> -	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> -	const struct intel_plane_state *plane_state;
>> -	struct intel_plane *plane;
>> -	char buf[64];
>> -	int i;
>> -
>> -	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
>> -		    crtc->base.base.id, crtc->base.name,
>> -		    str_yes_no(pipe_config->hw.enable), context);
>> -
>> -	if (!pipe_config->hw.enable)
>> -		goto dump_planes;
>> -
>> -	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
>> -	drm_dbg_kms(&dev_priv->drm,
>> -		    "active: %s, output_types: %s (0x%x), output format: %s\n",
>> -		    str_yes_no(pipe_config->hw.active),
>> -		    buf, pipe_config->output_types,
>> -		    output_formats(pipe_config->output_format));
>> -
>> -	drm_dbg_kms(&dev_priv->drm,
>> -		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
>> -		    transcoder_name(pipe_config->cpu_transcoder),
>> -		    pipe_config->pipe_bpp, pipe_config->dither);
>> -
>> -	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
>> -		    transcoder_name(pipe_config->mst_master_transcoder));
>> -
>> -	drm_dbg_kms(&dev_priv->drm,
>> -		    "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
>> -		    transcoder_name(pipe_config->master_transcoder),
>> -		    pipe_config->sync_mode_slaves_mask);
>> -
>> -	drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n",
>> -		    intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
>> -		    intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
>> -		    pipe_config->bigjoiner_pipes);
>> -
>> -	drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
>> -		    str_enabled_disabled(pipe_config->splitter.enable),
>> -		    pipe_config->splitter.link_count,
>> -		    pipe_config->splitter.pixel_overlap);
>> -
>> -	if (pipe_config->has_pch_encoder)
>> -		intel_dump_m_n_config(pipe_config, "fdi",
>> -				      pipe_config->fdi_lanes,
>> -				      &pipe_config->fdi_m_n);
>> -
>> -	if (intel_crtc_has_dp_encoder(pipe_config)) {
>> -		intel_dump_m_n_config(pipe_config, "dp m_n",
>> -				      pipe_config->lane_count,
>> -				      &pipe_config->dp_m_n);
>> -		intel_dump_m_n_config(pipe_config, "dp m2_n2",
>> -				      pipe_config->lane_count,
>> -				      &pipe_config->dp_m2_n2);
>> -	}
>> -
>> -	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
>> -		    pipe_config->framestart_delay, pipe_config->msa_timing_delay);
>> -
>> -	drm_dbg_kms(&dev_priv->drm,
>> -		    "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
>> -		    pipe_config->has_audio, pipe_config->has_infoframe,
>> -		    pipe_config->infoframes.enable);
>> -
>> -	if (pipe_config->infoframes.enable &
>> -	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
>> -		drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
>> -			    pipe_config->infoframes.gcp);
>> -	if (pipe_config->infoframes.enable &
>> -	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
>> -		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
>> -	if (pipe_config->infoframes.enable &
>> -	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
>> -		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
>> -	if (pipe_config->infoframes.enable &
>> -	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
>> -		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
>> -	if (pipe_config->infoframes.enable &
>> -	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
>> -		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
>> -	if (pipe_config->infoframes.enable &
>> -	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
>> -		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
>> -	if (pipe_config->infoframes.enable &
>> -	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
>> -		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
>> -
>> -	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
>> -		    str_yes_no(pipe_config->vrr.enable),
>> -		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
>> -		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
>> -		    pipe_config->vrr.flipline,
>> -		    intel_vrr_vmin_vblank_start(pipe_config),
>> -		    intel_vrr_vmax_vblank_start(pipe_config));
>> -
>> -	drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n",
>> -		    DRM_MODE_ARG(&pipe_config->hw.mode));
>> -	drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n",
>> -		    DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
>> -	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
>> -	drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n",
>> -		    DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
>> -	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
>> -	drm_dbg_kms(&dev_priv->drm,
>> -		    "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
>> -		    pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
>> -		    pipe_config->pixel_rate);
>> -
>> -	drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
>> -		    pipe_config->linetime, pipe_config->ips_linetime);
>> -
>> -	if (DISPLAY_VER(dev_priv) >= 9)
>> -		drm_dbg_kms(&dev_priv->drm,
>> -			    "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
>> -			    crtc->num_scalers,
>> -			    pipe_config->scaler_state.scaler_users,
>> -			    pipe_config->scaler_state.scaler_id);
>> -
>> -	if (HAS_GMCH(dev_priv))
>> -		drm_dbg_kms(&dev_priv->drm,
>> -			    "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
>> -			    pipe_config->gmch_pfit.control,
>> -			    pipe_config->gmch_pfit.pgm_ratios,
>> -			    pipe_config->gmch_pfit.lvds_border_bits);
>> -	else
>> -		drm_dbg_kms(&dev_priv->drm,
>> -			    "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
>> -			    DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
>> -			    str_enabled_disabled(pipe_config->pch_pfit.enabled),
>> -			    str_yes_no(pipe_config->pch_pfit.force_thru));
>> -
>> -	drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
>> -		    pipe_config->ips_enabled, pipe_config->double_wide,
>> -		    pipe_config->has_drrs);
>> -
>> -	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
>> -
>> -	if (IS_CHERRYVIEW(dev_priv))
>> -		drm_dbg_kms(&dev_priv->drm,
>> -			    "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
>> -			    pipe_config->cgm_mode, pipe_config->gamma_mode,
>> -			    pipe_config->gamma_enable, pipe_config->csc_enable);
>> -	else
>> -		drm_dbg_kms(&dev_priv->drm,
>> -			    "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
>> -			    pipe_config->csc_mode, pipe_config->gamma_mode,
>> -			    pipe_config->gamma_enable, pipe_config->csc_enable);
>> -
>> -	drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
>> -		    pipe_config->hw.degamma_lut ?
>> -		    drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
>> -		    pipe_config->hw.gamma_lut ?
>> -		    drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
>> -
>> -dump_planes:
>> -	if (!state)
>> -		return;
>> -
>> -	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
>> -		if (plane->pipe == crtc->pipe)
>> -			intel_dump_plane_state(plane_state);
>> -	}
>> -}
>> -
>>  static bool check_digital_port_conflicts(struct intel_atomic_state *state)
>>  {
>>  	struct drm_device *dev = state->base.dev;
>> @@ -6823,7 +6520,7 @@ static int intel_atomic_check(struct drm_device *dev,
>>  		    !new_crtc_state->update_pipe)
>>  			continue;
>>  
>> -		intel_dump_pipe_config(new_crtc_state, state,
>> +		intel_pipe_config_dump(new_crtc_state, state,
>>  				       intel_crtc_needs_modeset(new_crtc_state) ?
>>  				       "[modeset]" : "[fastset]");
>>  	}
>> @@ -6840,7 +6537,7 @@ static int intel_atomic_check(struct drm_device *dev,
>>  	 */
>>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>>  					    new_crtc_state, i)
>> -		intel_dump_pipe_config(new_crtc_state, state, "[failed]");
>> +		intel_pipe_config_dump(new_crtc_state, state, "[failed]");
>>  
>>  	return ret;
>>  }
>> @@ -9320,7 +9017,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
>>  			to_intel_crtc_state(crtc->base.state);
>>  
>>  		intel_sanitize_crtc(crtc, ctx);
>> -		intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
>> +		intel_pipe_config_dump(crtc_state, NULL, "[setup_hw_state]");
>>  	}
>>  
>>  	intel_modeset_update_connector_atomic_state(dev);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
>> index e827c84ece56..68477eb82049 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display.h
>> @@ -560,9 +560,6 @@ bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state);
>>  u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state);
>>  struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state);
>>  bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state);
>> -void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>> -			    struct intel_atomic_state *state,
>> -			    const char *context);
>>  
>>  void intel_plane_destroy(struct drm_plane *plane);
>>  void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
>> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
>> index fd752c61d854..de034ccef289 100644
>> --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
>> +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
>> @@ -15,6 +15,7 @@
>>  #include "intel_fdi.h"
>>  #include "intel_modeset_verify.h"
>>  #include "intel_pipe_config_compare.h"
>> +#include "intel_pipe_config_dump.h"
>>  #include "intel_pm.h"
>>  #include "intel_snps_phy.h"
>>  
>> @@ -217,8 +218,8 @@ verify_crtc_state(struct intel_crtc *crtc,
>>  	if (!intel_pipe_config_compare(new_crtc_state,
>>  				       pipe_config, false)) {
>>  		I915_STATE_WARN(1, "pipe state doesn't match!\n");
>> -		intel_dump_pipe_config(pipe_config, NULL, "[hw state]");
>> -		intel_dump_pipe_config(new_crtc_state, NULL, "[sw state]");
>> +		intel_pipe_config_dump(pipe_config, NULL, "[hw state]");
>> +		intel_pipe_config_dump(new_crtc_state, NULL, "[sw state]");
>>  	}
>>  }
>>  
>> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_config_dump.c b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
>> new file mode 100644
>> index 000000000000..c290cf009407
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
>> @@ -0,0 +1,314 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#include "i915_drv.h"
>> +#include "intel_display_types.h"
>> +#include "intel_hdmi.h"
>> +#include "intel_pipe_config_dump.h"
>> +#include "intel_vrr.h"
>> +
>> +static void intel_dump_crtc_timings(struct drm_i915_private *i915,
>> +				    const struct drm_display_mode *mode)
>> +{
>> +	drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
>> +		    "type: 0x%x flags: 0x%x\n",
>> +		    mode->crtc_clock,
>> +		    mode->crtc_hdisplay, mode->crtc_hsync_start,
>> +		    mode->crtc_hsync_end, mode->crtc_htotal,
>> +		    mode->crtc_vdisplay, mode->crtc_vsync_start,
>> +		    mode->crtc_vsync_end, mode->crtc_vtotal,
>> +		    mode->type, mode->flags);
>> +}
>> +
>> +static void
>> +intel_dump_m_n_config(const struct intel_crtc_state *pipe_config,
>> +		      const char *id, unsigned int lane_count,
>> +		      const struct intel_link_m_n *m_n)
>> +{
>> +	struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
>> +
>> +	drm_dbg_kms(&i915->drm,
>> +		    "%s: lanes: %i; data_m: %u, data_n: %u, link_m: %u, link_n: %u, tu: %u\n",
>> +		    id, lane_count,
>> +		    m_n->data_m, m_n->data_n,
>> +		    m_n->link_m, m_n->link_n, m_n->tu);
>> +}
>> +
>> +static void
>> +intel_dump_infoframe(struct drm_i915_private *dev_priv,
>> +		     const union hdmi_infoframe *frame)
>> +{
>> +	if (!drm_debug_enabled(DRM_UT_KMS))
>> +		return;
>> +
>> +	hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, frame);
>> +}
>> +
>> +static void
>> +intel_dump_dp_vsc_sdp(struct drm_i915_private *dev_priv,
>> +		      const struct drm_dp_vsc_sdp *vsc)
>> +{
>> +	if (!drm_debug_enabled(DRM_UT_KMS))
>> +		return;
>> +
>> +	drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, vsc);
>> +}
>> +
>> +#define OUTPUT_TYPE(x) [INTEL_OUTPUT_ ## x] = #x
>> +
>> +static const char * const output_type_str[] = {
>> +	OUTPUT_TYPE(UNUSED),
>> +	OUTPUT_TYPE(ANALOG),
>> +	OUTPUT_TYPE(DVO),
>> +	OUTPUT_TYPE(SDVO),
>> +	OUTPUT_TYPE(LVDS),
>> +	OUTPUT_TYPE(TVOUT),
>> +	OUTPUT_TYPE(HDMI),
>> +	OUTPUT_TYPE(DP),
>> +	OUTPUT_TYPE(EDP),
>> +	OUTPUT_TYPE(DSI),
>> +	OUTPUT_TYPE(DDI),
>> +	OUTPUT_TYPE(DP_MST),
>> +};
>> +
>> +#undef OUTPUT_TYPE
>> +
>> +static void snprintf_output_types(char *buf, size_t len,
>> +				  unsigned int output_types)
>> +{
>> +	char *str = buf;
>> +	int i;
>> +
>> +	str[0] = '\0';
>> +
>> +	for (i = 0; i < ARRAY_SIZE(output_type_str); i++) {
>> +		int r;
>> +
>> +		if ((output_types & BIT(i)) == 0)
>> +			continue;
>> +
>> +		r = snprintf(str, len, "%s%s",
>> +			     str != buf ? "," : "", output_type_str[i]);
>> +		if (r >= len)
>> +			break;
>> +		str += r;
>> +		len -= r;
>> +
>> +		output_types &= ~BIT(i);
>> +	}
>> +
>> +	WARN_ON_ONCE(output_types != 0);
>> +}
>> +
>> +static const char * const output_format_str[] = {
>> +	[INTEL_OUTPUT_FORMAT_RGB] = "RGB",
>> +	[INTEL_OUTPUT_FORMAT_YCBCR420] = "YCBCR4:2:0",
>> +	[INTEL_OUTPUT_FORMAT_YCBCR444] = "YCBCR4:4:4",
>> +};
>> +
>> +static const char *output_formats(enum intel_output_format format)
>> +{
>> +	if (format >= ARRAY_SIZE(output_format_str))
>> +		return "invalid";
>> +	return output_format_str[format];
>> +}
>> +
>> +static void intel_dump_plane_state(const struct intel_plane_state *plane_state)
>> +{
>> +	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
>> +	struct drm_i915_private *i915 = to_i915(plane->base.dev);
>> +	const struct drm_framebuffer *fb = plane_state->hw.fb;
>> +
>> +	if (!fb) {
>> +		drm_dbg_kms(&i915->drm,
>> +			    "[PLANE:%d:%s] fb: [NOFB], visible: %s\n",
>> +			    plane->base.base.id, plane->base.name,
>> +			    str_yes_no(plane_state->uapi.visible));
>> +		return;
>> +	}
>> +
>> +	drm_dbg_kms(&i915->drm,
>> +		    "[PLANE:%d:%s] fb: [FB:%d] %ux%u format = %p4cc modifier = 0x%llx, visible: %s\n",
>> +		    plane->base.base.id, plane->base.name,
>> +		    fb->base.id, fb->width, fb->height, &fb->format->format,
>> +		    fb->modifier, str_yes_no(plane_state->uapi.visible));
>> +	drm_dbg_kms(&i915->drm, "\trotation: 0x%x, scaler: %d\n",
>> +		    plane_state->hw.rotation, plane_state->scaler_id);
>> +	if (plane_state->uapi.visible)
>> +		drm_dbg_kms(&i915->drm,
>> +			    "\tsrc: " DRM_RECT_FP_FMT " dst: " DRM_RECT_FMT "\n",
>> +			    DRM_RECT_FP_ARG(&plane_state->uapi.src),
>> +			    DRM_RECT_ARG(&plane_state->uapi.dst));
>> +}
>> +
>> +void intel_pipe_config_dump(const struct intel_crtc_state *pipe_config,
>> +			    struct intel_atomic_state *state,
>> +			    const char *context)
>> +{
>> +	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>> +	const struct intel_plane_state *plane_state;
>> +	struct intel_plane *plane;
>> +	char buf[64];
>> +	int i;
>> +
>> +	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] enable: %s %s\n",
>> +		    crtc->base.base.id, crtc->base.name,
>> +		    str_yes_no(pipe_config->hw.enable), context);
>> +
>> +	if (!pipe_config->hw.enable)
>> +		goto dump_planes;
>> +
>> +	snprintf_output_types(buf, sizeof(buf), pipe_config->output_types);
>> +	drm_dbg_kms(&dev_priv->drm,
>> +		    "active: %s, output_types: %s (0x%x), output format: %s\n",
>> +		    str_yes_no(pipe_config->hw.active),
>> +		    buf, pipe_config->output_types,
>> +		    output_formats(pipe_config->output_format));
>> +
>> +	drm_dbg_kms(&dev_priv->drm,
>> +		    "cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
>> +		    transcoder_name(pipe_config->cpu_transcoder),
>> +		    pipe_config->pipe_bpp, pipe_config->dither);
>> +
>> +	drm_dbg_kms(&dev_priv->drm, "MST master transcoder: %s\n",
>> +		    transcoder_name(pipe_config->mst_master_transcoder));
>> +
>> +	drm_dbg_kms(&dev_priv->drm,
>> +		    "port sync: master transcoder: %s, slave transcoder bitmask = 0x%x\n",
>> +		    transcoder_name(pipe_config->master_transcoder),
>> +		    pipe_config->sync_mode_slaves_mask);
>> +
>> +	drm_dbg_kms(&dev_priv->drm, "bigjoiner: %s, pipes: 0x%x\n",
>> +		    intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" :
>> +		    intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no",
>> +		    pipe_config->bigjoiner_pipes);
>> +
>> +	drm_dbg_kms(&dev_priv->drm, "splitter: %s, link count %d, overlap %d\n",
>> +		    str_enabled_disabled(pipe_config->splitter.enable),
>> +		    pipe_config->splitter.link_count,
>> +		    pipe_config->splitter.pixel_overlap);
>> +
>> +	if (pipe_config->has_pch_encoder)
>> +		intel_dump_m_n_config(pipe_config, "fdi",
>> +				      pipe_config->fdi_lanes,
>> +				      &pipe_config->fdi_m_n);
>> +
>> +	if (intel_crtc_has_dp_encoder(pipe_config)) {
>> +		intel_dump_m_n_config(pipe_config, "dp m_n",
>> +				      pipe_config->lane_count,
>> +				      &pipe_config->dp_m_n);
>> +		intel_dump_m_n_config(pipe_config, "dp m2_n2",
>> +				      pipe_config->lane_count,
>> +				      &pipe_config->dp_m2_n2);
>> +	}
>> +
>> +	drm_dbg_kms(&dev_priv->drm, "framestart delay: %d, MSA timing delay: %d\n",
>> +		    pipe_config->framestart_delay, pipe_config->msa_timing_delay);
>> +
>> +	drm_dbg_kms(&dev_priv->drm,
>> +		    "audio: %i, infoframes: %i, infoframes enabled: 0x%x\n",
>> +		    pipe_config->has_audio, pipe_config->has_infoframe,
>> +		    pipe_config->infoframes.enable);
>> +
>> +	if (pipe_config->infoframes.enable &
>> +	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL))
>> +		drm_dbg_kms(&dev_priv->drm, "GCP: 0x%x\n",
>> +			    pipe_config->infoframes.gcp);
>> +	if (pipe_config->infoframes.enable &
>> +	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI))
>> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.avi);
>> +	if (pipe_config->infoframes.enable &
>> +	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD))
>> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.spd);
>> +	if (pipe_config->infoframes.enable &
>> +	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR))
>> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.hdmi);
>> +	if (pipe_config->infoframes.enable &
>> +	    intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM))
>> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
>> +	if (pipe_config->infoframes.enable &
>> +	    intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA))
>> +		intel_dump_infoframe(dev_priv, &pipe_config->infoframes.drm);
>> +	if (pipe_config->infoframes.enable &
>> +	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
>> +		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
>> +
>> +	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
>> +		    str_yes_no(pipe_config->vrr.enable),
>> +		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
>> +		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
>> +		    pipe_config->vrr.flipline,
>> +		    intel_vrr_vmin_vblank_start(pipe_config),
>> +		    intel_vrr_vmax_vblank_start(pipe_config));
>> +
>> +	drm_dbg_kms(&dev_priv->drm, "requested mode: " DRM_MODE_FMT "\n",
>> +		    DRM_MODE_ARG(&pipe_config->hw.mode));
>> +	drm_dbg_kms(&dev_priv->drm, "adjusted mode: " DRM_MODE_FMT "\n",
>> +		    DRM_MODE_ARG(&pipe_config->hw.adjusted_mode));
>> +	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.adjusted_mode);
>> +	drm_dbg_kms(&dev_priv->drm, "pipe mode: " DRM_MODE_FMT "\n",
>> +		    DRM_MODE_ARG(&pipe_config->hw.pipe_mode));
>> +	intel_dump_crtc_timings(dev_priv, &pipe_config->hw.pipe_mode);
>> +	drm_dbg_kms(&dev_priv->drm,
>> +		    "port clock: %d, pipe src: " DRM_RECT_FMT ", pixel rate %d\n",
>> +		    pipe_config->port_clock, DRM_RECT_ARG(&pipe_config->pipe_src),
>> +		    pipe_config->pixel_rate);
>> +
>> +	drm_dbg_kms(&dev_priv->drm, "linetime: %d, ips linetime: %d\n",
>> +		    pipe_config->linetime, pipe_config->ips_linetime);
>> +
>> +	if (DISPLAY_VER(dev_priv) >= 9)
>> +		drm_dbg_kms(&dev_priv->drm,
>> +			    "num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
>> +			    crtc->num_scalers,
>> +			    pipe_config->scaler_state.scaler_users,
>> +			    pipe_config->scaler_state.scaler_id);
>> +
>> +	if (HAS_GMCH(dev_priv))
>> +		drm_dbg_kms(&dev_priv->drm,
>> +			    "gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
>> +			    pipe_config->gmch_pfit.control,
>> +			    pipe_config->gmch_pfit.pgm_ratios,
>> +			    pipe_config->gmch_pfit.lvds_border_bits);
>> +	else
>> +		drm_dbg_kms(&dev_priv->drm,
>> +			    "pch pfit: " DRM_RECT_FMT ", %s, force thru: %s\n",
>> +			    DRM_RECT_ARG(&pipe_config->pch_pfit.dst),
>> +			    str_enabled_disabled(pipe_config->pch_pfit.enabled),
>> +			    str_yes_no(pipe_config->pch_pfit.force_thru));
>> +
>> +	drm_dbg_kms(&dev_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
>> +		    pipe_config->ips_enabled, pipe_config->double_wide,
>> +		    pipe_config->has_drrs);
>> +
>> +	intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
>> +
>> +	if (IS_CHERRYVIEW(dev_priv))
>> +		drm_dbg_kms(&dev_priv->drm,
>> +			    "cgm_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
>> +			    pipe_config->cgm_mode, pipe_config->gamma_mode,
>> +			    pipe_config->gamma_enable, pipe_config->csc_enable);
>> +	else
>> +		drm_dbg_kms(&dev_priv->drm,
>> +			    "csc_mode: 0x%x gamma_mode: 0x%x gamma_enable: %d csc_enable: %d\n",
>> +			    pipe_config->csc_mode, pipe_config->gamma_mode,
>> +			    pipe_config->gamma_enable, pipe_config->csc_enable);
>> +
>> +	drm_dbg_kms(&dev_priv->drm, "degamma lut: %d entries, gamma lut: %d entries\n",
>> +		    pipe_config->hw.degamma_lut ?
>> +		    drm_color_lut_size(pipe_config->hw.degamma_lut) : 0,
>> +		    pipe_config->hw.gamma_lut ?
>> +		    drm_color_lut_size(pipe_config->hw.gamma_lut) : 0);
>> +
>> +dump_planes:
>> +	if (!state)
>> +		return;
>> +
>> +	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
>> +		if (plane->pipe == crtc->pipe)
>> +			intel_dump_plane_state(plane_state);
>> +	}
>> +}
>> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_config_dump.h b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.h
>> new file mode 100644
>> index 000000000000..20bbe11f0527
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_pipe_config_dump.h
>> @@ -0,0 +1,16 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_PIPE_CONFIG_DUMP_H__
>> +#define __INTEL_PIPE_CONFIG_DUMP_H__
>> +
>> +struct intel_crtc_state;
>> +struct intel_atomic_state;
>> +
>> +void intel_pipe_config_dump(const struct intel_crtc_state *pipe_config,
>> +			    struct intel_atomic_state *state,
>> +			    const char *context);
>> +
>> +#endif /* __INTEL_PIPE_CONFIG_DUMP_H__ */
>> -- 
>> 2.30.2

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c
  2022-06-15 13:27 ` [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Ville Syrjälä
@ 2022-06-15 14:31   ` Jani Nikula
  2022-06-15 15:15     ` Jani Nikula
  0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2022-06-15 14:31 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Wed, 15 Jun 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Jun 15, 2022 at 03:47:54PM +0300, Jani Nikula wrote:
>> The state verification and pipe config comparison/dumping are fairly
>> isolated pieces of code within intel_display.c. Move them to separate
>> files in a long overdue cleanup.
>> 
>> Jani Nikula (7):
>>   drm/i915/wm: move wm state verification to intel_pm.c
>>   drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.c
>>   drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings
>>   drm/i915/mpllb: move mpllb state check to intel_snps_phy.c
>
> I'd perhaps go for foo_state_verify() naming convention. Would
> match the foo_state_dump() naming convention I suggested
> for the dumping stuff.

Roger.

>
> Apart from that these ^ four are
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
>>   drm/i915/display: split out modeset verification code
>
> I really hate some of that code. I guess hiding it is one option :P
> This one ^ is
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Yeah, there's some weird stuff. For example we only call
verify_encoder_state() only to verify it's disabled.

>
>>   drm/i915/display: split out pipe config compare to a separate file
>
> Not entirely sure I like moving this one. The fastset stuff
> within needs to stay in sync with the fastset codepaths which
> are in intel_display.c. Not sure if we risk more bugs if it's
> too well hidden...

Mixed feelings. The problem remains, the file is still too damn big, and
it's hard to draw the lines what to extract. Maybe all the modeset code
needs to be lifted, along with the config compare, but then I think that
has too many dependencies to axe out cleanly. Damned if you do, damned
if you don't.

BR,
Jani.


>
>>   drm/i915/display: split out pipe config dump to a separate file
>> 
>>  drivers/gpu/drm/i915/Makefile                 |    3 +
>>  drivers/gpu/drm/i915/display/intel_display.c  | 1373 +----------------
>>  drivers/gpu/drm/i915/display/intel_display.h  |    3 +
>>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   88 ++
>>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |    5 +
>>  .../drm/i915/display/intel_modeset_verify.c   |  247 +++
>>  .../drm/i915/display/intel_modeset_verify.h   |   21 +
>>  .../i915/display/intel_pipe_config_compare.c  |  581 +++++++
>>  .../i915/display/intel_pipe_config_compare.h  |   17 +
>>  .../drm/i915/display/intel_pipe_config_dump.c |  314 ++++
>>  .../drm/i915/display/intel_pipe_config_dump.h |   16 +
>>  drivers/gpu/drm/i915/display/intel_snps_phy.c |   43 +
>>  drivers/gpu/drm/i915/display/intel_snps_phy.h |    5 +-
>>  drivers/gpu/drm/i915/intel_pm.c               |  138 +-
>>  drivers/gpu/drm/i915/intel_pm.h               |   14 +-
>>  15 files changed, 1482 insertions(+), 1386 deletions(-)
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.c
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.h
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_compare.c
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_compare.h
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
>>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.h
>> 
>> -- 
>> 2.30.2

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c
  2022-06-15 14:31   ` Jani Nikula
@ 2022-06-15 15:15     ` Jani Nikula
  2022-06-15 15:24       ` Ville Syrjälä
  0 siblings, 1 reply; 18+ messages in thread
From: Jani Nikula @ 2022-06-15 15:15 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

On Wed, 15 Jun 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> On Wed, 15 Jun 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
>> On Wed, Jun 15, 2022 at 03:47:54PM +0300, Jani Nikula wrote:
>>> The state verification and pipe config comparison/dumping are fairly
>>> isolated pieces of code within intel_display.c. Move them to separate
>>> files in a long overdue cleanup.
>>> 
>>> Jani Nikula (7):
>>>   drm/i915/wm: move wm state verification to intel_pm.c
>>>   drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.c
>>>   drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings
>>>   drm/i915/mpllb: move mpllb state check to intel_snps_phy.c
>>
>> I'd perhaps go for foo_state_verify() naming convention. Would
>> match the foo_state_dump() naming convention I suggested
>> for the dumping stuff.
>
> Roger.
>
>>
>> Apart from that these ^ four are
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>>>   drm/i915/display: split out modeset verification code
>>
>> I really hate some of that code. I guess hiding it is one option :P
>> This one ^ is
>> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Yeah, there's some weird stuff. For example we only call
> verify_encoder_state() only to verify it's disabled.
>
>>
>>>   drm/i915/display: split out pipe config compare to a separate file
>>
>> Not entirely sure I like moving this one. The fastset stuff
>> within needs to stay in sync with the fastset codepaths which
>> are in intel_display.c. Not sure if we risk more bugs if it's
>> too well hidden...
>
> Mixed feelings. The problem remains, the file is still too damn big, and
> it's hard to draw the lines what to extract. Maybe all the modeset code
> needs to be lifted, along with the config compare, but then I think that
> has too many dependencies to axe out cleanly. Damned if you do, damned
> if you don't.

I've also got a patch to move intel_modeset_setup_hw_state() and all the
static functions only it calls to another file. Do you also think that
needs to be together with the modeset code...?

BR,
Jani.


>
> BR,
> Jani.
>
>
>>
>>>   drm/i915/display: split out pipe config dump to a separate file
>>> 
>>>  drivers/gpu/drm/i915/Makefile                 |    3 +
>>>  drivers/gpu/drm/i915/display/intel_display.c  | 1373 +----------------
>>>  drivers/gpu/drm/i915/display/intel_display.h  |    3 +
>>>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   88 ++
>>>  drivers/gpu/drm/i915/display/intel_dpll_mgr.h |    5 +
>>>  .../drm/i915/display/intel_modeset_verify.c   |  247 +++
>>>  .../drm/i915/display/intel_modeset_verify.h   |   21 +
>>>  .../i915/display/intel_pipe_config_compare.c  |  581 +++++++
>>>  .../i915/display/intel_pipe_config_compare.h  |   17 +
>>>  .../drm/i915/display/intel_pipe_config_dump.c |  314 ++++
>>>  .../drm/i915/display/intel_pipe_config_dump.h |   16 +
>>>  drivers/gpu/drm/i915/display/intel_snps_phy.c |   43 +
>>>  drivers/gpu/drm/i915/display/intel_snps_phy.h |    5 +-
>>>  drivers/gpu/drm/i915/intel_pm.c               |  138 +-
>>>  drivers/gpu/drm/i915/intel_pm.h               |   14 +-
>>>  15 files changed, 1482 insertions(+), 1386 deletions(-)
>>>  create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.c
>>>  create mode 100644 drivers/gpu/drm/i915/display/intel_modeset_verify.h
>>>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_compare.c
>>>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_compare.h
>>>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.c
>>>  create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_config_dump.h
>>> 
>>> -- 
>>> 2.30.2

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c
  2022-06-15 15:15     ` Jani Nikula
@ 2022-06-15 15:24       ` Ville Syrjälä
  0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2022-06-15 15:24 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

On Wed, Jun 15, 2022 at 06:15:58PM +0300, Jani Nikula wrote:
> On Wed, 15 Jun 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> > On Wed, 15 Jun 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> >> On Wed, Jun 15, 2022 at 03:47:54PM +0300, Jani Nikula wrote:
> >>> The state verification and pipe config comparison/dumping are fairly
> >>> isolated pieces of code within intel_display.c. Move them to separate
> >>> files in a long overdue cleanup.
> >>> 
> >>> Jani Nikula (7):
> >>>   drm/i915/wm: move wm state verification to intel_pm.c
> >>>   drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.c
> >>>   drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings
> >>>   drm/i915/mpllb: move mpllb state check to intel_snps_phy.c
> >>
> >> I'd perhaps go for foo_state_verify() naming convention. Would
> >> match the foo_state_dump() naming convention I suggested
> >> for the dumping stuff.
> >
> > Roger.
> >
> >>
> >> Apart from that these ^ four are
> >> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >>>   drm/i915/display: split out modeset verification code
> >>
> >> I really hate some of that code. I guess hiding it is one option :P
> >> This one ^ is
> >> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Yeah, there's some weird stuff. For example we only call
> > verify_encoder_state() only to verify it's disabled.
> >
> >>
> >>>   drm/i915/display: split out pipe config compare to a separate file
> >>
> >> Not entirely sure I like moving this one. The fastset stuff
> >> within needs to stay in sync with the fastset codepaths which
> >> are in intel_display.c. Not sure if we risk more bugs if it's
> >> too well hidden...
> >
> > Mixed feelings. The problem remains, the file is still too damn big, and
> > it's hard to draw the lines what to extract. Maybe all the modeset code
> > needs to be lifted, along with the config compare, but then I think that
> > has too many dependencies to axe out cleanly. Damned if you do, damned
> > if you don't.
> 
> I've also got a patch to move intel_modeset_setup_hw_state() and all the
> static functions only it calls to another file. Do you also think that
> needs to be together with the modeset code...?

Readout+sanitation... I guess that's pretty self contained so a fairly
good candidate for moving out.

Though it does mean I get to rebase my "nuke the legacy state pointers"
branch at some point :/ Oh well, that's life.

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 18+ messages in thread

* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: split out verifation, compare and dump from intel_display.c
  2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
                   ` (10 preceding siblings ...)
  2022-06-15 13:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-06-15 19:44 ` Patchwork
  11 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-06-15 19:44 UTC (permalink / raw)
  To: Jani Nikula; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 37284 bytes --]

== Series Details ==

Series: drm/i915/display: split out verifation, compare and dump from intel_display.c
URL   : https://patchwork.freedesktop.org/series/105156/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11759_full -> Patchwork_105156v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (10 -> 12)
------------------------------

  Additional (2): shard-rkl shard-tglu 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_105156v1_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@device_reset@unbind-reset-rebind:
    - {shard-rkl}:        NOTRUN -> [DMESG-WARN][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-rkl-2/igt@device_reset@unbind-reset-rebind.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs:
    - {shard-rkl}:        NOTRUN -> [SKIP][2] +12 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-rkl-5/igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html

  * {igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1}:
    - {shard-tglu}:       NOTRUN -> [SKIP][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-tglu-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  
Known issues
------------

  Here are the changes found in Patchwork_105156v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@device_reset@unbind-reset-rebind:
    - shard-skl:          NOTRUN -> [DMESG-WARN][4] ([i915#1982])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl4/igt@device_reset@unbind-reset-rebind.html

  * igt@drm_buddy@all@buddy_alloc_smoke:
    - shard-skl:          [PASS][5] -> [INCOMPLETE][6] ([i915#5800])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-skl9/igt@drm_buddy@all@buddy_alloc_smoke.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl6/igt@drm_buddy@all@buddy_alloc_smoke.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-skl:          NOTRUN -> [SKIP][7] ([fdo#109271]) +189 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl1/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-kbl:          [PASS][8] -> [DMESG-WARN][9] ([i915#180]) +3 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@gem_ctx_persistence@smoketest:
    - shard-iclb:         [PASS][10] -> [FAIL][11] ([i915#5099])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb8/igt@gem_ctx_persistence@smoketest.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb4/igt@gem_ctx_persistence@smoketest.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-iclb:         [PASS][12] -> [SKIP][13] ([i915#4525])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb2/igt@gem_exec_balancer@parallel-contexts.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb3/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_capture@pi@rcs0:
    - shard-skl:          NOTRUN -> [INCOMPLETE][14] ([i915#3371])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl1/igt@gem_exec_capture@pi@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-tglb:         [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-apl:          [PASS][17] -> [FAIL][18] ([i915#2842]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_lmem_swapping@verify-random:
    - shard-skl:          NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl6/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_pread@exhaustion:
    - shard-skl:          NOTRUN -> [WARN][20] ([i915#2658])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl4/igt@gem_pread@exhaustion.html

  * igt@i915_module_load@load:
    - shard-skl:          NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#6227])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl1/igt@i915_module_load@load.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
    - shard-skl:          NOTRUN -> [FAIL][22] ([i915#2521])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl4/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html

  * igt@kms_big_fb@x-tiled-addfb-size-offset-overflow:
    - shard-skl:          NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#1888])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl4/igt@kms_big_fb@x-tiled-addfb-size-offset-overflow.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3886]) +7 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl1/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3886]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl3/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886]) +2 similar issues
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl2/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@hdmi-frame-dump:
    - shard-kbl:          NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl3/igt@kms_chamelium@hdmi-frame-dump.html

  * igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
    - shard-apl:          NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl2/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-d-ctm-0-25:
    - shard-skl:          NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl1/igt@kms_color_chamelium@pipe-d-ctm-0-25.html

  * igt@kms_content_protection@lic:
    - shard-kbl:          NOTRUN -> [TIMEOUT][30] ([i915#1319])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@kms_content_protection@lic.html

  * igt@kms_cursor_crc@pipe-d-cursor-32x32-random:
    - shard-apl:          NOTRUN -> [SKIP][31] ([fdo#109271]) +65 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl2/igt@kms_cursor_crc@pipe-d-cursor-32x32-random.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          NOTRUN -> [FAIL][32] ([i915#2346])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-skl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#533]) +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl1/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
    - shard-skl:          [PASS][34] -> [FAIL][35] ([i915#79])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
    - shard-apl:          [PASS][36] -> [DMESG-WARN][37] ([i915#180]) +1 similar issue
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate@c-edp1:
    - shard-skl:          [PASS][38] -> [FAIL][39] ([i915#2122]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-skl10/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@c-edp1.html

  * igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
    - shard-skl:          NOTRUN -> [FAIL][40] ([i915#2122])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
    - shard-iclb:         [PASS][41] -> [SKIP][42] ([i915#3701]) +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
    - shard-kbl:          NOTRUN -> [SKIP][43] ([fdo#109271]) +96 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][44] ([i915#180])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-kbl:          NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#533])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
    - shard-apl:          NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#533])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl2/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-skl:          NOTRUN -> [FAIL][47] ([i915#265])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          NOTRUN -> [FAIL][48] ([fdo#108145] / [i915#265])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
    - shard-skl:          NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#658]) +1 similar issue
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl6/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
    - shard-kbl:          NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#658]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
    - shard-apl:          NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#658]) +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [PASS][52] -> [SKIP][53] ([fdo#109441]) +2 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb7/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-iclb:         [PASS][54] -> [SKIP][55] ([i915#5519])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@sw_sync@sync_merge_same:
    - shard-skl:          NOTRUN -> [FAIL][56] ([i915#6140])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl6/igt@sw_sync@sync_merge_same.html

  * igt@sw_sync@sync_multi_timeline_wait:
    - shard-kbl:          NOTRUN -> [FAIL][57] ([i915#6140])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@sw_sync@sync_multi_timeline_wait.html

  * igt@sysfs_clients@busy:
    - shard-skl:          NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#2994]) +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl1/igt@sysfs_clients@busy.html

  * igt@sysfs_clients@pidname:
    - shard-apl:          NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2994])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl2/igt@sysfs_clients@pidname.html
    - shard-kbl:          NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#2994])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@sysfs_clients@pidname.html

  
#### Possible fixes ####

  * igt@gem_exec_balancer@parallel:
    - shard-iclb:         [SKIP][61] ([i915#4525]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb6/igt@gem_exec_balancer@parallel.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb2/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [FAIL][63] ([i915#2842]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][65] ([i915#2842]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          [FAIL][67] ([i915#2842]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [FAIL][69] ([i915#2842]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][71] ([i915#454]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb8/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_cursor_legacy@flip-vs-cursor-legacy:
    - shard-skl:          [FAIL][73] ([i915#2346]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [INCOMPLETE][75] ([i915#180]) -> [PASS][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
    - shard-apl:          [FAIL][77] ([i915#79]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html

  * igt@kms_flip@flip-vs-suspend@a-dp1:
    - shard-apl:          [DMESG-WARN][79] ([i915#180]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
    - shard-iclb:         [SKIP][81] ([i915#3701]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-glk:          [FAIL][83] ([i915#4911]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-glk6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
    - shard-kbl:          [FAIL][85] ([i915#1188]) -> [PASS][86] +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl1/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl1/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
    - shard-kbl:          [DMESG-WARN][87] ([i915#180]) -> [PASS][88] +2 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [SKIP][89] ([fdo#109441]) -> [PASS][90] +3 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb6/igt@kms_psr@psr2_primary_mmap_cpu.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-tglb:         [SKIP][91] ([i915#5519]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-tglb6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-tglb7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  
#### Warnings ####

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-iclb:         [FAIL][93] ([i915#6117]) -> [SKIP][94] ([i915#4525])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb2/igt@gem_exec_balancer@parallel-ordering.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb7/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-iclb:         [FAIL][95] ([i915#2852]) -> [FAIL][96] ([i915#2842])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb6/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][97] ([i915#588]) -> [SKIP][98] ([i915#658])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [INCOMPLETE][99] ([i915#180]) -> [FAIL][100] ([i915#4767])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
    - shard-iclb:         [SKIP][101] ([i915#2920]) -> [SKIP][102] ([fdo#111068] / [i915#658]) +1 similar issue
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
    - shard-iclb:         [SKIP][103] ([fdo#111068] / [i915#658]) -> [SKIP][104] ([i915#2920])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-iclb:         [SKIP][105] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][106] ([i915#5939])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb5/igt@kms_psr2_su@page_flip-nv12.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html

  * igt@runner@aborted:
    - shard-skl:          [FAIL][107] ([i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112]) ([i915#2029] / [i915#3002] / [i915#4312] / [i915#5257])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-skl2/igt@runner@aborted.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl2/igt@runner@aborted.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl2/igt@runner@aborted.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl1/igt@runner@aborted.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl4/igt@runner@aborted.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-skl10/igt@runner@aborted.html
    - shard-kbl:          ([FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#92]) -> ([FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl1/igt@runner@aborted.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl1/igt@runner@aborted.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl1/igt@runner@aborted.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl7/igt@runner@aborted.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl4/igt@runner@aborted.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl4/igt@runner@aborted.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl4/igt@runner@aborted.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@runner@aborted.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@runner@aborted.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@runner@aborted.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl7/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/shard-kbl1/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
  [i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3371]: https://gitlab.freedesktop.org/drm/intel/issues/3371
  [i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
  [i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
  [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
  [i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5030]: https://gitlab.freedesktop.org/drm/intel/issues/5030
  [i915#5099]: https://gitlab.freedesktop.org/drm/intel/issues/5099
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5507]: https://gitlab.freedesktop.org/drm/intel/issues/5507
  [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
  [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
  [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
  [i915#5800]: https://gitlab.freedesktop.org/drm/intel/issues/5800
  [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
  [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
  [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
  [i915#6141]: https://gitlab.freedesktop.org/drm/intel/issues/6141
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92


Build changes
-------------

  * Linux: CI_DRM_11759 -> Patchwork_105156v1

  CI-20190529: 20190529
  CI_DRM_11759: fa66b647ce886c01bbe1e9f3017a141e90d87539 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6529: b96bf5a0307fc0bdbf6c8e86872817306e102883 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_105156v1: fa66b647ce886c01bbe1e9f3017a141e90d87539 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105156v1/index.html

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^ permalink raw reply	[flat|nested] 18+ messages in thread

end of thread, other threads:[~2022-06-15 19:44 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-15 12:47 [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Jani Nikula
2022-06-15 12:47 ` [Intel-gfx] [PATCH 1/7] drm/i915/wm: move wm state verification to intel_pm.c Jani Nikula
2022-06-15 12:47 ` [Intel-gfx] [PATCH 2/7] drm/i915/dpll: move shared dpll state verification to intel_dpll_mgr.c Jani Nikula
2022-06-15 12:47 ` [Intel-gfx] [PATCH 3/7] drm/i915/mpllb: use I915_STATE_WARN() for state mismatch warnings Jani Nikula
2022-06-15 12:47 ` [Intel-gfx] [PATCH 4/7] drm/i915/mpllb: move mpllb state check to intel_snps_phy.c Jani Nikula
2022-06-15 12:47 ` [Intel-gfx] [PATCH 5/7] drm/i915/display: split out modeset verification code Jani Nikula
2022-06-15 12:48 ` [Intel-gfx] [PATCH 6/7] drm/i915/display: split out pipe config compare to a separate file Jani Nikula
2022-06-15 12:48 ` [Intel-gfx] [PATCH 7/7] drm/i915/display: split out pipe config dump " Jani Nikula
2022-06-15 13:14   ` Ville Syrjälä
2022-06-15 14:25     ` Jani Nikula
2022-06-15 13:27 ` [Intel-gfx] [PATCH 0/7] drm/i915/display: split out verifation, compare and dump from intel_display.c Ville Syrjälä
2022-06-15 14:31   ` Jani Nikula
2022-06-15 15:15     ` Jani Nikula
2022-06-15 15:24       ` Ville Syrjälä
2022-06-15 13:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-06-15 13:30 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-06-15 13:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-15 19:44 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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