From: Andi Shyti <andi@etezian.org> To: Chanho Park <chanho61.park@samsung.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, Andi Shyti <andi@etezian.org>, Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Alim Akhtar <alim.akhtar@samsung.com>, devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 2/4] spi: s3c64xx: support custom value of internal clock divider Date: Wed, 29 Jun 2022 12:42:56 +0300 [thread overview] Message-ID: <YrweoNCL3BjqUNWV@jack.zhora.eu> (raw) In-Reply-To: <20220628044222.152794-3-chanho61.park@samsung.com> Hi Chanho, On Tue, Jun 28, 2022 at 01:42:20PM +0900, Chanho Park wrote: > Modern exynos SoCs such as Exynos Auto v9 has different internal clock /has/have/ > divider, for example "4". To support this internal value, this adds > clk_div of the s3c64xx_spi_port_config and assign "2" as the default > value to existing s3c64xx_spi_port_config. > > Signed-off-by: Chanho Park <chanho61.park@samsung.com> > --- > drivers/spi/spi-s3c64xx.c | 28 ++++++++++++++++++++-------- > 1 file changed, 20 insertions(+), 8 deletions(-) > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > index b3c50c7665fc..51a0e830441b 100644 > --- a/drivers/spi/spi-s3c64xx.c > +++ b/drivers/spi/spi-s3c64xx.c > @@ -131,6 +131,7 @@ struct s3c64xx_spi_dma_data { > * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. > * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. > * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. > + * @clk_div: Internal clock divider, if not specified, use 2 as the default. is it default? Is it not specified anywhere? I think you are assigning '2' to everyone. I would just leave it "Internal clock divider." [...] > @@ -871,6 +873,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) > struct s3c64xx_spi_csinfo *cs = spi->controller_data; > struct s3c64xx_spi_driver_data *sdd; > int err; > + u32 div = 2; As per Krzystof review. > sdd = spi_master_get_devdata(spi->master); > if (spi->dev.of_node) { > @@ -889,22 +892,24 @@ static int s3c64xx_spi_setup(struct spi_device *spi) > > pm_runtime_get_sync(&sdd->pdev->dev); > > + div = sdd->port_conf->clk_div; Can you please be consistent with the data type? div is u32, but clk_div is int. [...] Andi _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi@etezian.org> To: Chanho Park <chanho61.park@samsung.com> Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, Andi Shyti <andi@etezian.org>, Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Alim Akhtar <alim.akhtar@samsung.com>, devicetree@vger.kernel.org, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 2/4] spi: s3c64xx: support custom value of internal clock divider Date: Wed, 29 Jun 2022 12:42:56 +0300 [thread overview] Message-ID: <YrweoNCL3BjqUNWV@jack.zhora.eu> (raw) In-Reply-To: <20220628044222.152794-3-chanho61.park@samsung.com> Hi Chanho, On Tue, Jun 28, 2022 at 01:42:20PM +0900, Chanho Park wrote: > Modern exynos SoCs such as Exynos Auto v9 has different internal clock /has/have/ > divider, for example "4". To support this internal value, this adds > clk_div of the s3c64xx_spi_port_config and assign "2" as the default > value to existing s3c64xx_spi_port_config. > > Signed-off-by: Chanho Park <chanho61.park@samsung.com> > --- > drivers/spi/spi-s3c64xx.c | 28 ++++++++++++++++++++-------- > 1 file changed, 20 insertions(+), 8 deletions(-) > > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c > index b3c50c7665fc..51a0e830441b 100644 > --- a/drivers/spi/spi-s3c64xx.c > +++ b/drivers/spi/spi-s3c64xx.c > @@ -131,6 +131,7 @@ struct s3c64xx_spi_dma_data { > * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. > * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. > * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. > + * @clk_div: Internal clock divider, if not specified, use 2 as the default. is it default? Is it not specified anywhere? I think you are assigning '2' to everyone. I would just leave it "Internal clock divider." [...] > @@ -871,6 +873,7 @@ static int s3c64xx_spi_setup(struct spi_device *spi) > struct s3c64xx_spi_csinfo *cs = spi->controller_data; > struct s3c64xx_spi_driver_data *sdd; > int err; > + u32 div = 2; As per Krzystof review. > sdd = spi_master_get_devdata(spi->master); > if (spi->dev.of_node) { > @@ -889,22 +892,24 @@ static int s3c64xx_spi_setup(struct spi_device *spi) > > pm_runtime_get_sync(&sdd->pdev->dev); > > + div = sdd->port_conf->clk_div; Can you please be consistent with the data type? div is u32, but clk_div is int. [...] Andi
next prev parent reply other threads:[~2022-06-29 9:44 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20220628044432epcas2p13af378bf5c8cdb767f4f06804e07f7c7@epcas2p1.samsung.com> 2022-06-28 4:42 ` [PATCH v2 0/4] spi support for Exynos Auto v9 SoC Chanho Park 2022-06-28 4:42 ` Chanho Park [not found] ` <CGME20220628044432epcas2p2116480d15be87cb723855b7a39ced6dc@epcas2p2.samsung.com> 2022-06-28 4:42 ` [PATCH v2 1/4] spi: s3c64xx: support loopback mode Chanho Park 2022-06-28 4:42 ` Chanho Park 2022-06-29 9:33 ` Andi Shyti 2022-06-29 9:33 ` Andi Shyti [not found] ` <CGME20220628044432epcas2p11e6f927321c30cf5557dbd41d749ef28@epcas2p1.samsung.com> 2022-06-28 4:42 ` [PATCH v2 2/4] spi: s3c64xx: support custom value of internal clock divider Chanho Park 2022-06-28 4:42 ` Chanho Park 2022-06-29 9:20 ` Krzysztof Kozlowski 2022-06-29 9:20 ` Krzysztof Kozlowski 2022-06-29 9:26 ` Chanho Park 2022-06-29 9:26 ` Chanho Park 2022-06-29 9:42 ` Andi Shyti [this message] 2022-06-29 9:42 ` Andi Shyti 2022-06-29 10:04 ` Chanho Park 2022-06-29 10:04 ` Chanho Park [not found] ` <CGME20220628044432epcas2p3781648b3cade1dcac6b8e0f3899d7299@epcas2p3.samsung.com> 2022-06-28 4:42 ` [PATCH v2 3/4] dt-bindings: samsung,spi: define exynosautov9 compatible Chanho Park 2022-06-28 4:42 ` Chanho Park 2022-06-29 9:45 ` Andi Shyti 2022-06-29 9:45 ` Andi Shyti [not found] ` <CGME20220628044432epcas2p2e2b4c0d52f11c0bf543c537e819224bc@epcas2p2.samsung.com> 2022-06-28 4:42 ` [PATCH v2 4/4] spi: s3c64xx: add spi port configuration for Exynos Auto v9 SoC Chanho Park 2022-06-28 4:42 ` Chanho Park 2022-06-29 9:19 ` Krzysztof Kozlowski 2022-06-29 9:19 ` Krzysztof Kozlowski 2022-06-29 9:48 ` Andi Shyti 2022-06-29 9:48 ` Andi Shyti
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