* [PATCH v2 00/11] OpenRISC Virtual Machine
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc
Hello,
This is the OpenRISC Virtual Machine plaform which we are now using for OpenRISC
CI such as the wireguard testing that Jason has been working on.
The first few patches help get OpenRISC QEMU ready for the virtual machine.
There is one bug fix for GDB debugging there too.
Next we have the Virt patch followed by a separate patch to add PCI support
which is split out because it's a bit easier to review that way I thought. The
next few patches are fixes to get the Multicore platform stable, such as adding
MTTCG support and fixing some interrupt and timer related bugs.
The platform is relatively stable now, but every few boots we get ~10 second soft
lockups. My hunch is that this is another interrupt race condition where IPI's
end up getting lost. However, overall the is much more stable than the SMP
support we had before. So I want to submit this for review and maybe upstream
it before tracking down these last issues which might take significant more
time.
This is being tested with my or1k-virt kernel branch here:
https://github.com/stffrdhrn/linux/commits/or1k-virt
This tree has support for: OpenRISC PCI and virt_defconfig and an irqchip bug
fix.
Changes since v1:
- Dropped semihosting support
- Added PCI support
- Added OpenRISC documentation
- Added OpenRISC support for MTTCG
- Support Configurating Goldfish RTC endianness
- Added a few bug fix patches
-Stafford
Jason A. Donenfeld (1):
hw/openrisc: virt: pass random seed to fdt
Stafford Horne (10):
hw/openrisc: Split re-usable boot time apis out to boot.c
target/openrisc: Fix memory reading in debugger
goldfish_rtc: Add endianness property
hw/openrisc: Add the OpenRISC virtual machine
hw/openrisc: Add PCI bus support to virt
hw/openrisc: Initialize timer time at startup
target/openrisc: Add interrupted CPU to log
target/openrisc: Enable MTTCG
target/openrisc: Interrupt handling fixes
docs/system: openrisc: Add OpenRISC documentation
configs/devices/or1k-softmmu/default.mak | 1 +
configs/targets/or1k-softmmu.mak | 1 +
docs/system/openrisc/cpu-features.rst | 15 +
docs/system/openrisc/emulation.rst | 17 +
docs/system/openrisc/or1k-sim.rst | 43 ++
docs/system/openrisc/virt.rst | 50 ++
docs/system/target-openrisc.rst | 72 +++
docs/system/targets.rst | 1 +
hw/openrisc/Kconfig | 12 +
hw/openrisc/boot.c | 117 +++++
hw/openrisc/cputimer.c | 18 +
hw/openrisc/meson.build | 2 +
hw/openrisc/openrisc_sim.c | 106 +----
hw/openrisc/virt.c | 578 +++++++++++++++++++++++
hw/rtc/goldfish_rtc.c | 46 +-
include/hw/openrisc/boot.h | 34 ++
include/hw/rtc/goldfish_rtc.h | 2 +
target/openrisc/cpu.c | 1 -
target/openrisc/cpu.h | 3 +
target/openrisc/interrupt.c | 4 +-
target/openrisc/mmu.c | 8 +-
target/openrisc/sys_helper.c | 18 +-
22 files changed, 1035 insertions(+), 114 deletions(-)
create mode 100644 docs/system/openrisc/cpu-features.rst
create mode 100644 docs/system/openrisc/emulation.rst
create mode 100644 docs/system/openrisc/or1k-sim.rst
create mode 100644 docs/system/openrisc/virt.rst
create mode 100644 docs/system/target-openrisc.rst
create mode 100644 hw/openrisc/boot.c
create mode 100644 hw/openrisc/virt.c
create mode 100644 include/hw/openrisc/boot.h
--
2.36.1
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 00/11] OpenRISC Virtual Machine
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Stafford Horne
Hello,
This is the OpenRISC Virtual Machine plaform which we are now using for OpenRISC
CI such as the wireguard testing that Jason has been working on.
The first few patches help get OpenRISC QEMU ready for the virtual machine.
There is one bug fix for GDB debugging there too.
Next we have the Virt patch followed by a separate patch to add PCI support
which is split out because it's a bit easier to review that way I thought. The
next few patches are fixes to get the Multicore platform stable, such as adding
MTTCG support and fixing some interrupt and timer related bugs.
The platform is relatively stable now, but every few boots we get ~10 second soft
lockups. My hunch is that this is another interrupt race condition where IPI's
end up getting lost. However, overall the is much more stable than the SMP
support we had before. So I want to submit this for review and maybe upstream
it before tracking down these last issues which might take significant more
time.
This is being tested with my or1k-virt kernel branch here:
https://github.com/stffrdhrn/linux/commits/or1k-virt
This tree has support for: OpenRISC PCI and virt_defconfig and an irqchip bug
fix.
Changes since v1:
- Dropped semihosting support
- Added PCI support
- Added OpenRISC documentation
- Added OpenRISC support for MTTCG
- Support Configurating Goldfish RTC endianness
- Added a few bug fix patches
-Stafford
Jason A. Donenfeld (1):
hw/openrisc: virt: pass random seed to fdt
Stafford Horne (10):
hw/openrisc: Split re-usable boot time apis out to boot.c
target/openrisc: Fix memory reading in debugger
goldfish_rtc: Add endianness property
hw/openrisc: Add the OpenRISC virtual machine
hw/openrisc: Add PCI bus support to virt
hw/openrisc: Initialize timer time at startup
target/openrisc: Add interrupted CPU to log
target/openrisc: Enable MTTCG
target/openrisc: Interrupt handling fixes
docs/system: openrisc: Add OpenRISC documentation
configs/devices/or1k-softmmu/default.mak | 1 +
configs/targets/or1k-softmmu.mak | 1 +
docs/system/openrisc/cpu-features.rst | 15 +
docs/system/openrisc/emulation.rst | 17 +
docs/system/openrisc/or1k-sim.rst | 43 ++
docs/system/openrisc/virt.rst | 50 ++
docs/system/target-openrisc.rst | 72 +++
docs/system/targets.rst | 1 +
hw/openrisc/Kconfig | 12 +
hw/openrisc/boot.c | 117 +++++
hw/openrisc/cputimer.c | 18 +
hw/openrisc/meson.build | 2 +
hw/openrisc/openrisc_sim.c | 106 +----
hw/openrisc/virt.c | 578 +++++++++++++++++++++++
hw/rtc/goldfish_rtc.c | 46 +-
include/hw/openrisc/boot.h | 34 ++
include/hw/rtc/goldfish_rtc.h | 2 +
target/openrisc/cpu.c | 1 -
target/openrisc/cpu.h | 3 +
target/openrisc/interrupt.c | 4 +-
target/openrisc/mmu.c | 8 +-
target/openrisc/sys_helper.c | 18 +-
22 files changed, 1035 insertions(+), 114 deletions(-)
create mode 100644 docs/system/openrisc/cpu-features.rst
create mode 100644 docs/system/openrisc/emulation.rst
create mode 100644 docs/system/openrisc/or1k-sim.rst
create mode 100644 docs/system/openrisc/virt.rst
create mode 100644 docs/system/target-openrisc.rst
create mode 100644 hw/openrisc/boot.c
create mode 100644 hw/openrisc/virt.c
create mode 100644 include/hw/openrisc/boot.h
--
2.36.1
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v2 01/11] hw/openrisc: Split re-usable boot time apis out to boot.c
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-03 21:28 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Richard Henderson, Jia Liu
These will be shared with the virt platform.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/boot.c | 117 +++++++++++++++++++++++++++++++++++++
hw/openrisc/meson.build | 1 +
hw/openrisc/openrisc_sim.c | 106 ++-------------------------------
include/hw/openrisc/boot.h | 34 +++++++++++
4 files changed, 158 insertions(+), 100 deletions(-)
create mode 100644 hw/openrisc/boot.c
create mode 100644 include/hw/openrisc/boot.h
diff --git a/hw/openrisc/boot.c b/hw/openrisc/boot.c
new file mode 100644
index 0000000000..ca773b385e
--- /dev/null
+++ b/hw/openrisc/boot.c
@@ -0,0 +1,117 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * QEMU OpenRISC boot helpers.
+ *
+ * (c) 2022 Stafford Horne <shorne@gmail.com>
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/cpu-defs.h"
+#include "elf.h"
+#include "hw/loader.h"
+#include "hw/openrisc/boot.h"
+#include "sysemu/device_tree.h"
+#include "sysemu/qtest.h"
+
+#include <libfdt.h>
+
+#define KERNEL_LOAD_ADDR 0x100
+
+hwaddr openrisc_load_kernel(ram_addr_t ram_size,
+ const char *kernel_filename,
+ uint32_t *bootstrap_pc)
+{
+ long kernel_size;
+ uint64_t elf_entry;
+ uint64_t high_addr;
+ hwaddr entry;
+
+ if (kernel_filename && !qtest_enabled()) {
+ kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
+ &elf_entry, NULL, &high_addr, NULL, 1,
+ EM_OPENRISC, 1, 0);
+ entry = elf_entry;
+ if (kernel_size < 0) {
+ kernel_size = load_uimage(kernel_filename,
+ &entry, NULL, NULL, NULL, NULL);
+ high_addr = entry + kernel_size;
+ }
+ if (kernel_size < 0) {
+ kernel_size = load_image_targphys(kernel_filename,
+ KERNEL_LOAD_ADDR,
+ ram_size - KERNEL_LOAD_ADDR);
+ high_addr = KERNEL_LOAD_ADDR + kernel_size;
+ }
+
+ if (entry <= 0) {
+ entry = KERNEL_LOAD_ADDR;
+ }
+
+ if (kernel_size < 0) {
+ error_report("couldn't load the kernel '%s'", kernel_filename);
+ exit(1);
+ }
+ *bootstrap_pc = entry;
+
+ return high_addr;
+ }
+ return 0;
+}
+
+hwaddr openrisc_load_initrd(void *fdt, const char *filename,
+ hwaddr load_start, uint64_t mem_size)
+{
+ int size;
+ hwaddr start;
+
+ /* We put the initrd right after the kernel; page aligned. */
+ start = TARGET_PAGE_ALIGN(load_start);
+
+ size = load_ramdisk(filename, start, mem_size - start);
+ if (size < 0) {
+ size = load_image_targphys(filename, start, mem_size - start);
+ if (size < 0) {
+ error_report("could not load ramdisk '%s'", filename);
+ exit(1);
+ }
+ }
+
+ if (fdt) {
+ qemu_fdt_setprop_cell(fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(fdt, "/chosen",
+ "linux,initrd-end", start + size);
+ }
+
+ return start + size;
+}
+
+uint32_t openrisc_load_fdt(void *fdt, hwaddr load_start,
+ uint64_t mem_size)
+{
+ uint32_t fdt_addr;
+ int ret;
+ int fdtsize = fdt_totalsize(fdt);
+
+ if (fdtsize <= 0) {
+ error_report("invalid device-tree");
+ exit(1);
+ }
+
+ /* We put fdt right after the kernel and/or initrd. */
+ fdt_addr = TARGET_PAGE_ALIGN(load_start);
+
+ ret = fdt_pack(fdt);
+ /* Should only fail if we've built a corrupted tree */
+ g_assert(ret == 0);
+ /* copy in the device tree */
+ qemu_fdt_dumpdtb(fdt, fdtsize);
+
+ rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
+ &address_space_memory);
+
+ return fdt_addr;
+}
+
diff --git a/hw/openrisc/meson.build b/hw/openrisc/meson.build
index ec48172c9d..ab563820c5 100644
--- a/hw/openrisc/meson.build
+++ b/hw/openrisc/meson.build
@@ -1,5 +1,6 @@
openrisc_ss = ss.source_set()
openrisc_ss.add(files('cputimer.c'))
+openrisc_ss.add(files('boot.c'))
openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: [files('openrisc_sim.c'), fdt])
hw_arch += {'openrisc': openrisc_ss}
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 35adce17ac..35da123aef 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -24,10 +24,9 @@
#include "cpu.h"
#include "hw/irq.h"
#include "hw/boards.h"
-#include "elf.h"
#include "hw/char/serial.h"
#include "net/net.h"
-#include "hw/loader.h"
+#include "hw/openrisc/boot.h"
#include "hw/qdev-properties.h"
#include "exec/address-spaces.h"
#include "sysemu/device_tree.h"
@@ -283,101 +282,6 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
g_free(nodename);
}
-static hwaddr openrisc_load_kernel(ram_addr_t ram_size,
- const char *kernel_filename)
-{
- long kernel_size;
- uint64_t elf_entry;
- uint64_t high_addr;
- hwaddr entry;
-
- if (kernel_filename && !qtest_enabled()) {
- kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
- &elf_entry, NULL, &high_addr, NULL, 1,
- EM_OPENRISC, 1, 0);
- entry = elf_entry;
- if (kernel_size < 0) {
- kernel_size = load_uimage(kernel_filename,
- &entry, NULL, NULL, NULL, NULL);
- high_addr = entry + kernel_size;
- }
- if (kernel_size < 0) {
- kernel_size = load_image_targphys(kernel_filename,
- KERNEL_LOAD_ADDR,
- ram_size - KERNEL_LOAD_ADDR);
- high_addr = KERNEL_LOAD_ADDR + kernel_size;
- }
-
- if (entry <= 0) {
- entry = KERNEL_LOAD_ADDR;
- }
-
- if (kernel_size < 0) {
- error_report("couldn't load the kernel '%s'", kernel_filename);
- exit(1);
- }
- boot_info.bootstrap_pc = entry;
-
- return high_addr;
- }
- return 0;
-}
-
-static hwaddr openrisc_load_initrd(Or1ksimState *state, const char *filename,
- hwaddr load_start, uint64_t mem_size)
-{
- void *fdt = state->fdt;
- int size;
- hwaddr start;
-
- /* We put the initrd right after the kernel; page aligned. */
- start = TARGET_PAGE_ALIGN(load_start);
-
- size = load_ramdisk(filename, start, mem_size - start);
- if (size < 0) {
- size = load_image_targphys(filename, start, mem_size - start);
- if (size < 0) {
- error_report("could not load ramdisk '%s'", filename);
- exit(1);
- }
- }
-
- qemu_fdt_setprop_cell(fdt, "/chosen",
- "linux,initrd-start", start);
- qemu_fdt_setprop_cell(fdt, "/chosen",
- "linux,initrd-end", start + size);
-
- return start + size;
-}
-
-static uint32_t openrisc_load_fdt(Or1ksimState *state, hwaddr load_start,
- uint64_t mem_size)
-{
- void *fdt = state->fdt;
- uint32_t fdt_addr;
- int ret;
- int fdtsize = fdt_totalsize(fdt);
-
- if (fdtsize <= 0) {
- error_report("invalid device-tree");
- exit(1);
- }
-
- /* We put fdt right after the kernel and/or initrd. */
- fdt_addr = TARGET_PAGE_ALIGN(load_start);
-
- ret = fdt_pack(fdt);
- /* Should only fail if we've built a corrupted tree */
- g_assert(ret == 0);
- /* copy in the device tree */
- qemu_fdt_dumpdtb(fdt, fdtsize);
-
- rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
- &address_space_memory);
-
- return fdt_addr;
-}
-
static void openrisc_sim_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
@@ -428,13 +332,15 @@ static void openrisc_sim_init(MachineState *machine)
or1ksim_memmap[OR1KSIM_UART].size,
smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
- load_addr = openrisc_load_kernel(ram_size, kernel_filename);
+ load_addr = openrisc_load_kernel(ram_size, kernel_filename,
+ &boot_info.bootstrap_pc);
if (load_addr > 0) {
if (machine->initrd_filename) {
- load_addr = openrisc_load_initrd(state, machine->initrd_filename,
+ load_addr = openrisc_load_initrd(state->fdt,
+ machine->initrd_filename,
load_addr, machine->ram_size);
}
- boot_info.fdt_addr = openrisc_load_fdt(state, load_addr,
+ boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
machine->ram_size);
}
}
diff --git a/include/hw/openrisc/boot.h b/include/hw/openrisc/boot.h
new file mode 100644
index 0000000000..25a313d63a
--- /dev/null
+++ b/include/hw/openrisc/boot.h
@@ -0,0 +1,34 @@
+/*
+ * QEMU OpenRISC boot helpers.
+ *
+ * Copyright (c) 2022 Stafford Horne <shorne@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef OPENRISC_BOOT_H
+#define OPENRISC_BOOT_H
+
+#include "exec/cpu-defs.h"
+
+hwaddr openrisc_load_kernel(ram_addr_t ram_size,
+ const char *kernel_filename,
+ uint32_t *bootstrap_pc);
+
+hwaddr openrisc_load_initrd(void *fdt, const char *filename,
+ hwaddr load_start, uint64_t mem_size);
+
+uint32_t openrisc_load_fdt(void *fdt, hwaddr load_start,
+ uint64_t mem_size);
+
+#endif /* OPENRISC_BOOT_H */
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 01/11] hw/openrisc: Split re-usable boot time apis out to boot.c
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Stafford Horne, Richard Henderson, Jia Liu
These will be shared with the virt platform.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/boot.c | 117 +++++++++++++++++++++++++++++++++++++
hw/openrisc/meson.build | 1 +
hw/openrisc/openrisc_sim.c | 106 ++-------------------------------
include/hw/openrisc/boot.h | 34 +++++++++++
4 files changed, 158 insertions(+), 100 deletions(-)
create mode 100644 hw/openrisc/boot.c
create mode 100644 include/hw/openrisc/boot.h
diff --git a/hw/openrisc/boot.c b/hw/openrisc/boot.c
new file mode 100644
index 0000000000..ca773b385e
--- /dev/null
+++ b/hw/openrisc/boot.c
@@ -0,0 +1,117 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * QEMU OpenRISC boot helpers.
+ *
+ * (c) 2022 Stafford Horne <shorne@gmail.com>
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/cpu-defs.h"
+#include "elf.h"
+#include "hw/loader.h"
+#include "hw/openrisc/boot.h"
+#include "sysemu/device_tree.h"
+#include "sysemu/qtest.h"
+
+#include <libfdt.h>
+
+#define KERNEL_LOAD_ADDR 0x100
+
+hwaddr openrisc_load_kernel(ram_addr_t ram_size,
+ const char *kernel_filename,
+ uint32_t *bootstrap_pc)
+{
+ long kernel_size;
+ uint64_t elf_entry;
+ uint64_t high_addr;
+ hwaddr entry;
+
+ if (kernel_filename && !qtest_enabled()) {
+ kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
+ &elf_entry, NULL, &high_addr, NULL, 1,
+ EM_OPENRISC, 1, 0);
+ entry = elf_entry;
+ if (kernel_size < 0) {
+ kernel_size = load_uimage(kernel_filename,
+ &entry, NULL, NULL, NULL, NULL);
+ high_addr = entry + kernel_size;
+ }
+ if (kernel_size < 0) {
+ kernel_size = load_image_targphys(kernel_filename,
+ KERNEL_LOAD_ADDR,
+ ram_size - KERNEL_LOAD_ADDR);
+ high_addr = KERNEL_LOAD_ADDR + kernel_size;
+ }
+
+ if (entry <= 0) {
+ entry = KERNEL_LOAD_ADDR;
+ }
+
+ if (kernel_size < 0) {
+ error_report("couldn't load the kernel '%s'", kernel_filename);
+ exit(1);
+ }
+ *bootstrap_pc = entry;
+
+ return high_addr;
+ }
+ return 0;
+}
+
+hwaddr openrisc_load_initrd(void *fdt, const char *filename,
+ hwaddr load_start, uint64_t mem_size)
+{
+ int size;
+ hwaddr start;
+
+ /* We put the initrd right after the kernel; page aligned. */
+ start = TARGET_PAGE_ALIGN(load_start);
+
+ size = load_ramdisk(filename, start, mem_size - start);
+ if (size < 0) {
+ size = load_image_targphys(filename, start, mem_size - start);
+ if (size < 0) {
+ error_report("could not load ramdisk '%s'", filename);
+ exit(1);
+ }
+ }
+
+ if (fdt) {
+ qemu_fdt_setprop_cell(fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(fdt, "/chosen",
+ "linux,initrd-end", start + size);
+ }
+
+ return start + size;
+}
+
+uint32_t openrisc_load_fdt(void *fdt, hwaddr load_start,
+ uint64_t mem_size)
+{
+ uint32_t fdt_addr;
+ int ret;
+ int fdtsize = fdt_totalsize(fdt);
+
+ if (fdtsize <= 0) {
+ error_report("invalid device-tree");
+ exit(1);
+ }
+
+ /* We put fdt right after the kernel and/or initrd. */
+ fdt_addr = TARGET_PAGE_ALIGN(load_start);
+
+ ret = fdt_pack(fdt);
+ /* Should only fail if we've built a corrupted tree */
+ g_assert(ret == 0);
+ /* copy in the device tree */
+ qemu_fdt_dumpdtb(fdt, fdtsize);
+
+ rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
+ &address_space_memory);
+
+ return fdt_addr;
+}
+
diff --git a/hw/openrisc/meson.build b/hw/openrisc/meson.build
index ec48172c9d..ab563820c5 100644
--- a/hw/openrisc/meson.build
+++ b/hw/openrisc/meson.build
@@ -1,5 +1,6 @@
openrisc_ss = ss.source_set()
openrisc_ss.add(files('cputimer.c'))
+openrisc_ss.add(files('boot.c'))
openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: [files('openrisc_sim.c'), fdt])
hw_arch += {'openrisc': openrisc_ss}
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 35adce17ac..35da123aef 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -24,10 +24,9 @@
#include "cpu.h"
#include "hw/irq.h"
#include "hw/boards.h"
-#include "elf.h"
#include "hw/char/serial.h"
#include "net/net.h"
-#include "hw/loader.h"
+#include "hw/openrisc/boot.h"
#include "hw/qdev-properties.h"
#include "exec/address-spaces.h"
#include "sysemu/device_tree.h"
@@ -283,101 +282,6 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
g_free(nodename);
}
-static hwaddr openrisc_load_kernel(ram_addr_t ram_size,
- const char *kernel_filename)
-{
- long kernel_size;
- uint64_t elf_entry;
- uint64_t high_addr;
- hwaddr entry;
-
- if (kernel_filename && !qtest_enabled()) {
- kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
- &elf_entry, NULL, &high_addr, NULL, 1,
- EM_OPENRISC, 1, 0);
- entry = elf_entry;
- if (kernel_size < 0) {
- kernel_size = load_uimage(kernel_filename,
- &entry, NULL, NULL, NULL, NULL);
- high_addr = entry + kernel_size;
- }
- if (kernel_size < 0) {
- kernel_size = load_image_targphys(kernel_filename,
- KERNEL_LOAD_ADDR,
- ram_size - KERNEL_LOAD_ADDR);
- high_addr = KERNEL_LOAD_ADDR + kernel_size;
- }
-
- if (entry <= 0) {
- entry = KERNEL_LOAD_ADDR;
- }
-
- if (kernel_size < 0) {
- error_report("couldn't load the kernel '%s'", kernel_filename);
- exit(1);
- }
- boot_info.bootstrap_pc = entry;
-
- return high_addr;
- }
- return 0;
-}
-
-static hwaddr openrisc_load_initrd(Or1ksimState *state, const char *filename,
- hwaddr load_start, uint64_t mem_size)
-{
- void *fdt = state->fdt;
- int size;
- hwaddr start;
-
- /* We put the initrd right after the kernel; page aligned. */
- start = TARGET_PAGE_ALIGN(load_start);
-
- size = load_ramdisk(filename, start, mem_size - start);
- if (size < 0) {
- size = load_image_targphys(filename, start, mem_size - start);
- if (size < 0) {
- error_report("could not load ramdisk '%s'", filename);
- exit(1);
- }
- }
-
- qemu_fdt_setprop_cell(fdt, "/chosen",
- "linux,initrd-start", start);
- qemu_fdt_setprop_cell(fdt, "/chosen",
- "linux,initrd-end", start + size);
-
- return start + size;
-}
-
-static uint32_t openrisc_load_fdt(Or1ksimState *state, hwaddr load_start,
- uint64_t mem_size)
-{
- void *fdt = state->fdt;
- uint32_t fdt_addr;
- int ret;
- int fdtsize = fdt_totalsize(fdt);
-
- if (fdtsize <= 0) {
- error_report("invalid device-tree");
- exit(1);
- }
-
- /* We put fdt right after the kernel and/or initrd. */
- fdt_addr = TARGET_PAGE_ALIGN(load_start);
-
- ret = fdt_pack(fdt);
- /* Should only fail if we've built a corrupted tree */
- g_assert(ret == 0);
- /* copy in the device tree */
- qemu_fdt_dumpdtb(fdt, fdtsize);
-
- rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr,
- &address_space_memory);
-
- return fdt_addr;
-}
-
static void openrisc_sim_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
@@ -428,13 +332,15 @@ static void openrisc_sim_init(MachineState *machine)
or1ksim_memmap[OR1KSIM_UART].size,
smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
- load_addr = openrisc_load_kernel(ram_size, kernel_filename);
+ load_addr = openrisc_load_kernel(ram_size, kernel_filename,
+ &boot_info.bootstrap_pc);
if (load_addr > 0) {
if (machine->initrd_filename) {
- load_addr = openrisc_load_initrd(state, machine->initrd_filename,
+ load_addr = openrisc_load_initrd(state->fdt,
+ machine->initrd_filename,
load_addr, machine->ram_size);
}
- boot_info.fdt_addr = openrisc_load_fdt(state, load_addr,
+ boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
machine->ram_size);
}
}
diff --git a/include/hw/openrisc/boot.h b/include/hw/openrisc/boot.h
new file mode 100644
index 0000000000..25a313d63a
--- /dev/null
+++ b/include/hw/openrisc/boot.h
@@ -0,0 +1,34 @@
+/*
+ * QEMU OpenRISC boot helpers.
+ *
+ * Copyright (c) 2022 Stafford Horne <shorne@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef OPENRISC_BOOT_H
+#define OPENRISC_BOOT_H
+
+#include "exec/cpu-defs.h"
+
+hwaddr openrisc_load_kernel(ram_addr_t ram_size,
+ const char *kernel_filename,
+ uint32_t *bootstrap_pc);
+
+hwaddr openrisc_load_initrd(void *fdt, const char *filename,
+ hwaddr load_start, uint64_t mem_size);
+
+uint32_t openrisc_load_fdt(void *fdt, hwaddr load_start,
+ uint64_t mem_size);
+
+#endif /* OPENRISC_BOOT_H */
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 02/11] target/openrisc: Fix memory reading in debugger
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-03 21:28 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc
In commit f0655423ca ("target/openrisc: Reorg tlb lookup") data and
instruction TLB reads were combined. This, broke debugger reads where
we first tried to map using the data tlb then fall back to the
instruction tlb.
This patch replicates this logic by first requesting a PAGE_READ
protection mapping then falling back to PAGE_EXEC.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/mmu.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index d7e1320998..0b8afdbacf 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -148,7 +148,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
case SR_DME | SR_IME:
/* The mmu is definitely enabled. */
excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
- PAGE_EXEC | PAGE_READ | PAGE_WRITE,
+ PAGE_READ,
+ (sr & SR_SM) != 0);
+ if (!excp) {
+ return phys_addr;
+ }
+ excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
+ PAGE_EXEC,
(sr & SR_SM) != 0);
return excp ? -1 : phys_addr;
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 02/11] target/openrisc: Fix memory reading in debugger
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Stafford Horne
In commit f0655423ca ("target/openrisc: Reorg tlb lookup") data and
instruction TLB reads were combined. This, broke debugger reads where
we first tried to map using the data tlb then fall back to the
instruction tlb.
This patch replicates this logic by first requesting a PAGE_READ
protection mapping then falling back to PAGE_EXEC.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/mmu.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index d7e1320998..0b8afdbacf 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -148,7 +148,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
case SR_DME | SR_IME:
/* The mmu is definitely enabled. */
excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
- PAGE_EXEC | PAGE_READ | PAGE_WRITE,
+ PAGE_READ,
+ (sr & SR_SM) != 0);
+ if (!excp) {
+ return phys_addr;
+ }
+ excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
+ PAGE_EXEC,
(sr & SR_SM) != 0);
return excp ? -1 : phys_addr;
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 03/11] goldfish_rtc: Add endianness property
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-03 21:28 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development
Cc: Laurent Vivier, open list:Goldfish RTC, Anup Patel, Openrisc,
Alistair Francis
Add an endianness property to allow configuring the RTC as either
native, little or big endian.
Cc: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/rtc/goldfish_rtc.c | 46 ++++++++++++++++++++++++++++-------
include/hw/rtc/goldfish_rtc.h | 2 ++
2 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c
index 35e493be31..24f6587086 100644
--- a/hw/rtc/goldfish_rtc.c
+++ b/hw/rtc/goldfish_rtc.c
@@ -216,14 +216,34 @@ static int goldfish_rtc_post_load(void *opaque, int version_id)
return 0;
}
-static const MemoryRegionOps goldfish_rtc_ops = {
- .read = goldfish_rtc_read,
- .write = goldfish_rtc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
- .min_access_size = 4,
- .max_access_size = 4
- }
+static const MemoryRegionOps goldfish_rtc_ops[3] = {
+ [DEVICE_NATIVE_ENDIAN] = {
+ .read = goldfish_rtc_read,
+ .write = goldfish_rtc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+ },
+ [DEVICE_LITTLE_ENDIAN] = {
+ .read = goldfish_rtc_read,
+ .write = goldfish_rtc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+ },
+ [DEVICE_BIG_ENDIAN] = {
+ .read = goldfish_rtc_read,
+ .write = goldfish_rtc_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+ },
};
static const VMStateDescription goldfish_rtc_vmstate = {
@@ -265,7 +285,8 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
SysBusDevice *dev = SYS_BUS_DEVICE(d);
GoldfishRTCState *s = GOLDFISH_RTC(d);
- memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_rtc_ops, s,
+ memory_region_init_io(&s->iomem, OBJECT(s),
+ &goldfish_rtc_ops[s->endianness], s,
"goldfish_rtc", 0x24);
sysbus_init_mmio(dev, &s->iomem);
@@ -274,10 +295,17 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s);
}
+static Property goldfish_rtc_properties[] = {
+ DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
+ DEVICE_NATIVE_ENDIAN),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void goldfish_rtc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ device_class_set_props(dc, goldfish_rtc_properties);
dc->realize = goldfish_rtc_realize;
dc->reset = goldfish_rtc_reset;
dc->vmsd = &goldfish_rtc_vmstate;
diff --git a/include/hw/rtc/goldfish_rtc.h b/include/hw/rtc/goldfish_rtc.h
index 79ca7daf5d..8e1aeb85e3 100644
--- a/include/hw/rtc/goldfish_rtc.h
+++ b/include/hw/rtc/goldfish_rtc.h
@@ -42,6 +42,8 @@ struct GoldfishRTCState {
uint32_t irq_pending;
uint32_t irq_enabled;
uint32_t time_high;
+
+ uint8_t endianness;
};
#endif
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 03/11] goldfish_rtc: Add endianness property
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development
Cc: Openrisc, Stafford Horne, Laurent Vivier, Anup Patel,
Alistair Francis, open list:Goldfish RTC
Add an endianness property to allow configuring the RTC as either
native, little or big endian.
Cc: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/rtc/goldfish_rtc.c | 46 ++++++++++++++++++++++++++++-------
include/hw/rtc/goldfish_rtc.h | 2 ++
2 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c
index 35e493be31..24f6587086 100644
--- a/hw/rtc/goldfish_rtc.c
+++ b/hw/rtc/goldfish_rtc.c
@@ -216,14 +216,34 @@ static int goldfish_rtc_post_load(void *opaque, int version_id)
return 0;
}
-static const MemoryRegionOps goldfish_rtc_ops = {
- .read = goldfish_rtc_read,
- .write = goldfish_rtc_write,
- .endianness = DEVICE_NATIVE_ENDIAN,
- .valid = {
- .min_access_size = 4,
- .max_access_size = 4
- }
+static const MemoryRegionOps goldfish_rtc_ops[3] = {
+ [DEVICE_NATIVE_ENDIAN] = {
+ .read = goldfish_rtc_read,
+ .write = goldfish_rtc_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+ },
+ [DEVICE_LITTLE_ENDIAN] = {
+ .read = goldfish_rtc_read,
+ .write = goldfish_rtc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+ },
+ [DEVICE_BIG_ENDIAN] = {
+ .read = goldfish_rtc_read,
+ .write = goldfish_rtc_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4
+ }
+ },
};
static const VMStateDescription goldfish_rtc_vmstate = {
@@ -265,7 +285,8 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
SysBusDevice *dev = SYS_BUS_DEVICE(d);
GoldfishRTCState *s = GOLDFISH_RTC(d);
- memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_rtc_ops, s,
+ memory_region_init_io(&s->iomem, OBJECT(s),
+ &goldfish_rtc_ops[s->endianness], s,
"goldfish_rtc", 0x24);
sysbus_init_mmio(dev, &s->iomem);
@@ -274,10 +295,17 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s);
}
+static Property goldfish_rtc_properties[] = {
+ DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
+ DEVICE_NATIVE_ENDIAN),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
static void goldfish_rtc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ device_class_set_props(dc, goldfish_rtc_properties);
dc->realize = goldfish_rtc_realize;
dc->reset = goldfish_rtc_reset;
dc->vmsd = &goldfish_rtc_vmstate;
diff --git a/include/hw/rtc/goldfish_rtc.h b/include/hw/rtc/goldfish_rtc.h
index 79ca7daf5d..8e1aeb85e3 100644
--- a/include/hw/rtc/goldfish_rtc.h
+++ b/include/hw/rtc/goldfish_rtc.h
@@ -42,6 +42,8 @@ struct GoldfishRTCState {
uint32_t irq_pending;
uint32_t irq_enabled;
uint32_t time_high;
+
+ uint8_t endianness;
};
#endif
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 04/11] hw/openrisc: Add the OpenRISC virtual machine
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-03 21:28 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc
This patch adds the OpenRISC virtual machine 'virt' for OpenRISC. This
platform allows for a convenient CI platform for toolchain, software
ports and the OpenRISC linux kernel port.
Much of this has been sourced from the m68k and riscv virt platforms.
The platform provides:
- OpenRISC SMP with up to 4 cpus
- A virtio bus with up to 8 devices
- Standard ns16550a serial
- Goldfish RTC
- SiFive TEST device for poweroff and reboot
- Generated Device Tree to automatically configure the guest kernel
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
configs/devices/or1k-softmmu/default.mak | 1 +
hw/openrisc/Kconfig | 9 +
hw/openrisc/meson.build | 1 +
hw/openrisc/virt.c | 424 +++++++++++++++++++++++
4 files changed, 435 insertions(+)
create mode 100644 hw/openrisc/virt.c
diff --git a/configs/devices/or1k-softmmu/default.mak b/configs/devices/or1k-softmmu/default.mak
index 168101c39a..89c39e3123 100644
--- a/configs/devices/or1k-softmmu/default.mak
+++ b/configs/devices/or1k-softmmu/default.mak
@@ -3,3 +3,4 @@
# Boards:
#
CONFIG_OR1K_SIM=y
+CONFIG_OR1K_VIRT=y
diff --git a/hw/openrisc/Kconfig b/hw/openrisc/Kconfig
index 8f284f3ba0..202134668e 100644
--- a/hw/openrisc/Kconfig
+++ b/hw/openrisc/Kconfig
@@ -4,3 +4,12 @@ config OR1K_SIM
select OPENCORES_ETH
select OMPIC
select SPLIT_IRQ
+
+config OR1K_VIRT
+ bool
+ imply VIRTIO_VGA
+ imply TEST_DEVICES
+ select GOLDFISH_RTC
+ select SERIAL
+ select SIFIVE_TEST
+ select VIRTIO_MMIO
diff --git a/hw/openrisc/meson.build b/hw/openrisc/meson.build
index ab563820c5..2dbc6365bb 100644
--- a/hw/openrisc/meson.build
+++ b/hw/openrisc/meson.build
@@ -2,5 +2,6 @@ openrisc_ss = ss.source_set()
openrisc_ss.add(files('cputimer.c'))
openrisc_ss.add(files('boot.c'))
openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: [files('openrisc_sim.c'), fdt])
+openrisc_ss.add(when: 'CONFIG_OR1K_VIRT', if_true: [files('virt.c'), fdt])
hw_arch += {'openrisc': openrisc_ss}
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
new file mode 100644
index 0000000000..bdb00f6e32
--- /dev/null
+++ b/hw/openrisc/virt.c
@@ -0,0 +1,424 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * OpenRISC QEMU virtual machine.
+ *
+ * (c) 2022 Stafford Horne <shorne@gmail.com>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "exec/address-spaces.h"
+#include "hw/irq.h"
+#include "hw/boards.h"
+#include "hw/char/serial.h"
+#include "hw/core/split-irq.h"
+#include "hw/openrisc/boot.h"
+#include "hw/misc/sifive_test.h"
+#include "hw/qdev-properties.h"
+#include "hw/rtc/goldfish_rtc.h"
+#include "hw/sysbus.h"
+#include "hw/virtio/virtio-mmio.h"
+#include "sysemu/device_tree.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+
+#include <libfdt.h>
+
+#define VIRT_CPUS_MAX 4
+#define VIRT_CLK_MHZ 20000000
+
+#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
+#define VIRT_MACHINE(obj) \
+ OBJECT_CHECK(OR1KVirtState, (obj), TYPE_VIRT_MACHINE)
+
+typedef struct OR1KVirtState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+ void *fdt;
+ int fdt_size;
+
+} OR1KVirtState;
+
+enum {
+ VIRT_DRAM,
+ VIRT_TEST,
+ VIRT_RTC,
+ VIRT_VIRTIO,
+ VIRT_UART,
+ VIRT_OMPIC,
+};
+
+enum {
+ VIRT_OMPIC_IRQ = 1,
+ VIRT_UART_IRQ = 2,
+ VIRT_RTC_IRQ = 3,
+ VIRT_VIRTIO_IRQ = 4, /* to 12 */
+ VIRTIO_COUNT = 8,
+};
+
+static const struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+} virt_memmap[] = {
+ [VIRT_DRAM] = { 0x00000000, 0 },
+ [VIRT_UART] = { 0x90000000, 0x100 },
+ [VIRT_TEST] = { 0x96000000, 0x8 },
+ [VIRT_RTC] = { 0x96005000, 0x1000 },
+ [VIRT_VIRTIO] = { 0x97000000, 0x1000 },
+ [VIRT_OMPIC] = { 0x98000000, VIRT_CPUS_MAX * 8 },
+};
+
+static struct openrisc_boot_info {
+ uint32_t bootstrap_pc;
+ uint32_t fdt_addr;
+} boot_info;
+
+static void main_cpu_reset(void *opaque)
+{
+ OpenRISCCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+
+ cpu_reset(CPU(cpu));
+
+ cpu_set_pc(cs, boot_info.bootstrap_pc);
+ cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr);
+}
+
+static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
+{
+ return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);
+}
+
+static qemu_irq get_per_cpu_irq(OpenRISCCPU *cpus[], int num_cpus, int irq_pin)
+{
+ int i;
+
+ if (num_cpus > 1) {
+ DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
+ qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
+ qdev_realize_and_unref(splitter, NULL, &error_fatal);
+ for (i = 0; i < num_cpus; i++) {
+ qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
+ }
+ return qdev_get_gpio_in(splitter, 0);
+ } else {
+ return get_cpu_irq(cpus, 0, irq_pin);
+ }
+}
+
+static void openrisc_create_fdt(OR1KVirtState *state,
+ const struct MemmapEntry *memmap,
+ int num_cpus, uint64_t mem_size,
+ const char *cmdline)
+{
+ void *fdt;
+ int cpu;
+ char *nodename;
+ int pic_ph;
+
+ fdt = state->fdt = create_device_tree(&state->fdt_size);
+ if (!fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
+ }
+
+ qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim");
+ qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);
+ qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);
+
+ qemu_fdt_add_subnode(fdt, "/soc");
+ qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
+ qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
+ qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1);
+ qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1);
+
+ nodename = g_strdup_printf("/memory@%" HWADDR_PRIx,
+ memmap[VIRT_DRAM].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ memmap[VIRT_DRAM].base, mem_size);
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
+ g_free(nodename);
+
+ qemu_fdt_add_subnode(fdt, "/cpus");
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
+
+ for (cpu = 0; cpu < num_cpus; cpu++) {
+ nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "opencores,or1200-rtlsvn481");
+ qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ VIRT_CLK_MHZ);
+ g_free(nodename);
+ }
+
+ nodename = (char *)"/pic";
+ qemu_fdt_add_subnode(fdt, nodename);
+ pic_ph = qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "opencores,or1k-pic-level");
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", pic_ph);
+
+ qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", pic_ph);
+
+ qemu_fdt_add_subnode(fdt, "/chosen");
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
+
+ /* Create aliases node for use by devices. */
+ qemu_fdt_add_subnode(fdt, "/aliases");
+}
+
+static void openrisc_virt_ompic_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ DeviceState *dev;
+ SysBusDevice *s;
+ char *nodename;
+ int i;
+
+ dev = qdev_new("or1k-ompic");
+ qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
+
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
+ for (i = 0; i < num_cpus; i++) {
+ sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));
+ }
+ sysbus_mmio_map(s, 0, base);
+
+ /* Add device tree node for ompic. */
+ nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+}
+
+static void openrisc_virt_serial_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ qemu_irq serial_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
+ serial_hd(0), DEVICE_NATIVE_ENDIAN);
+
+ /* Add device tree node for serial. */
+ nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", VIRT_CLK_MHZ);
+ qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
+
+ /* The /chosen node is created during fdt creation. */
+ qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
+ qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);
+ g_free(nodename);
+}
+
+static void openrisc_virt_test_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size)
+{
+ void *fdt = state->fdt;
+ int test_ph;
+ char *nodename;
+
+ /* SiFive Test MMIO device */
+ sifive_test_create(base);
+
+ /* SiFive Test MMIO Reset device FDT */
+ nodename = g_strdup_printf("/soc/test@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon");
+ test_ph = qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_ph);
+ qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/reboot");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
+ qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
+ qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
+ qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/poweroff");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
+ qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
+ qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
+ qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
+ g_free(nodename);
+
+}
+static void openrisc_virt_rtc_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ DeviceState *dev;
+ SysBusDevice *sysbus;
+ qemu_irq rtc_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ /* Goldfish RTC */
+ dev = qdev_new(TYPE_GOLDFISH_RTC);
+ qdev_prop_set_uint8(dev, "endianness", DEVICE_LITTLE_ENDIAN);
+ sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
+ sysbus_connect_irq(sysbus, 0, rtc_irq);
+ sysbus_mmio_map(sysbus, 0, base);
+
+ /* Goldfish RTC FDT */
+ nodename = g_strdup_printf("/soc/rtc@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "google,goldfish-rtc");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+
+}
+static void openrisc_virt_virtio_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ DeviceState *dev;
+ SysBusDevice *sysbus;
+ qemu_irq virtio_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ /* VirtIO MMIO devices */
+ dev = qdev_new(TYPE_VIRTIO_MMIO);
+ qdev_prop_set_bit(dev, "force-legacy", false);
+ sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
+ sysbus_connect_irq(sysbus, 0, virtio_irq);
+ sysbus_mmio_map(sysbus, 0, base);
+
+ /* VirtIO MMIO devices FDT */
+ nodename = g_strdup_printf("/soc/virtio_mmio@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+}
+
+static void openrisc_virt_init(MachineState *machine)
+{
+ ram_addr_t ram_size = machine->ram_size;
+ const char *kernel_filename = machine->kernel_filename;
+ OpenRISCCPU *cpus[VIRT_CPUS_MAX] = {};
+ OR1KVirtState *state = VIRT_MACHINE(machine);
+ MemoryRegion *ram;
+ hwaddr load_addr;
+ int n;
+ unsigned int smp_cpus = machine->smp.cpus;
+
+ assert(smp_cpus >= 1 && smp_cpus <= VIRT_CPUS_MAX);
+ for (n = 0; n < smp_cpus; n++) {
+ cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
+ if (cpus[n] == NULL) {
+ fprintf(stderr, "Unable to find CPU definition!\n");
+ exit(1);
+ }
+
+ cpu_openrisc_clock_init(cpus[n]);
+
+ qemu_register_reset(main_cpu_reset, cpus[n]);
+ }
+
+ ram = g_malloc(sizeof(*ram));
+ memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), 0, ram);
+
+ openrisc_create_fdt(state, virt_memmap, smp_cpus, machine->ram_size,
+ machine->kernel_cmdline);
+
+ if (smp_cpus > 1) {
+ openrisc_virt_ompic_init(state, virt_memmap[VIRT_OMPIC].base,
+ virt_memmap[VIRT_OMPIC].size,
+ smp_cpus, cpus, VIRT_OMPIC_IRQ);
+ }
+
+ openrisc_virt_serial_init(state, virt_memmap[VIRT_UART].base,
+ virt_memmap[VIRT_UART].size,
+ smp_cpus, cpus, VIRT_UART_IRQ);
+
+ openrisc_virt_test_init(state, virt_memmap[VIRT_TEST].base,
+ virt_memmap[VIRT_TEST].size);
+
+ openrisc_virt_rtc_init(state, virt_memmap[VIRT_RTC].base,
+ virt_memmap[VIRT_RTC].size, smp_cpus, cpus,
+ VIRT_RTC_IRQ);
+
+ for (n = 0; n < VIRTIO_COUNT; n++) {
+ openrisc_virt_virtio_init(state, virt_memmap[VIRT_VIRTIO].base
+ + n * virt_memmap[VIRT_VIRTIO].size,
+ virt_memmap[VIRT_VIRTIO].size,
+ smp_cpus, cpus, VIRT_VIRTIO_IRQ + n);
+ }
+
+ load_addr = openrisc_load_kernel(ram_size, kernel_filename,
+ &boot_info.bootstrap_pc);
+ if (load_addr > 0) {
+ if (machine->initrd_filename) {
+ load_addr = openrisc_load_initrd(state->fdt,
+ machine->initrd_filename,
+ load_addr, machine->ram_size);
+ }
+ boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
+ machine->ram_size);
+ }
+}
+
+static void openrisc_virt_machine_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "or1k virtual machine";
+ mc->init = openrisc_virt_init;
+ mc->max_cpus = VIRT_CPUS_MAX;
+ mc->is_default = false;
+ mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
+}
+
+static const TypeInfo or1ksim_machine_typeinfo = {
+ .name = TYPE_VIRT_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = openrisc_virt_machine_init,
+ .instance_size = sizeof(OR1KVirtState),
+};
+
+static void or1ksim_machine_init_register_types(void)
+{
+ type_register_static(&or1ksim_machine_typeinfo);
+}
+
+type_init(or1ksim_machine_init_register_types)
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 04/11] hw/openrisc: Add the OpenRISC virtual machine
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Stafford Horne
This patch adds the OpenRISC virtual machine 'virt' for OpenRISC. This
platform allows for a convenient CI platform for toolchain, software
ports and the OpenRISC linux kernel port.
Much of this has been sourced from the m68k and riscv virt platforms.
The platform provides:
- OpenRISC SMP with up to 4 cpus
- A virtio bus with up to 8 devices
- Standard ns16550a serial
- Goldfish RTC
- SiFive TEST device for poweroff and reboot
- Generated Device Tree to automatically configure the guest kernel
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
configs/devices/or1k-softmmu/default.mak | 1 +
hw/openrisc/Kconfig | 9 +
hw/openrisc/meson.build | 1 +
hw/openrisc/virt.c | 424 +++++++++++++++++++++++
4 files changed, 435 insertions(+)
create mode 100644 hw/openrisc/virt.c
diff --git a/configs/devices/or1k-softmmu/default.mak b/configs/devices/or1k-softmmu/default.mak
index 168101c39a..89c39e3123 100644
--- a/configs/devices/or1k-softmmu/default.mak
+++ b/configs/devices/or1k-softmmu/default.mak
@@ -3,3 +3,4 @@
# Boards:
#
CONFIG_OR1K_SIM=y
+CONFIG_OR1K_VIRT=y
diff --git a/hw/openrisc/Kconfig b/hw/openrisc/Kconfig
index 8f284f3ba0..202134668e 100644
--- a/hw/openrisc/Kconfig
+++ b/hw/openrisc/Kconfig
@@ -4,3 +4,12 @@ config OR1K_SIM
select OPENCORES_ETH
select OMPIC
select SPLIT_IRQ
+
+config OR1K_VIRT
+ bool
+ imply VIRTIO_VGA
+ imply TEST_DEVICES
+ select GOLDFISH_RTC
+ select SERIAL
+ select SIFIVE_TEST
+ select VIRTIO_MMIO
diff --git a/hw/openrisc/meson.build b/hw/openrisc/meson.build
index ab563820c5..2dbc6365bb 100644
--- a/hw/openrisc/meson.build
+++ b/hw/openrisc/meson.build
@@ -2,5 +2,6 @@ openrisc_ss = ss.source_set()
openrisc_ss.add(files('cputimer.c'))
openrisc_ss.add(files('boot.c'))
openrisc_ss.add(when: 'CONFIG_OR1K_SIM', if_true: [files('openrisc_sim.c'), fdt])
+openrisc_ss.add(when: 'CONFIG_OR1K_VIRT', if_true: [files('virt.c'), fdt])
hw_arch += {'openrisc': openrisc_ss}
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
new file mode 100644
index 0000000000..bdb00f6e32
--- /dev/null
+++ b/hw/openrisc/virt.c
@@ -0,0 +1,424 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * OpenRISC QEMU virtual machine.
+ *
+ * (c) 2022 Stafford Horne <shorne@gmail.com>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "exec/address-spaces.h"
+#include "hw/irq.h"
+#include "hw/boards.h"
+#include "hw/char/serial.h"
+#include "hw/core/split-irq.h"
+#include "hw/openrisc/boot.h"
+#include "hw/misc/sifive_test.h"
+#include "hw/qdev-properties.h"
+#include "hw/rtc/goldfish_rtc.h"
+#include "hw/sysbus.h"
+#include "hw/virtio/virtio-mmio.h"
+#include "sysemu/device_tree.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/qtest.h"
+#include "sysemu/reset.h"
+
+#include <libfdt.h>
+
+#define VIRT_CPUS_MAX 4
+#define VIRT_CLK_MHZ 20000000
+
+#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
+#define VIRT_MACHINE(obj) \
+ OBJECT_CHECK(OR1KVirtState, (obj), TYPE_VIRT_MACHINE)
+
+typedef struct OR1KVirtState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+ void *fdt;
+ int fdt_size;
+
+} OR1KVirtState;
+
+enum {
+ VIRT_DRAM,
+ VIRT_TEST,
+ VIRT_RTC,
+ VIRT_VIRTIO,
+ VIRT_UART,
+ VIRT_OMPIC,
+};
+
+enum {
+ VIRT_OMPIC_IRQ = 1,
+ VIRT_UART_IRQ = 2,
+ VIRT_RTC_IRQ = 3,
+ VIRT_VIRTIO_IRQ = 4, /* to 12 */
+ VIRTIO_COUNT = 8,
+};
+
+static const struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+} virt_memmap[] = {
+ [VIRT_DRAM] = { 0x00000000, 0 },
+ [VIRT_UART] = { 0x90000000, 0x100 },
+ [VIRT_TEST] = { 0x96000000, 0x8 },
+ [VIRT_RTC] = { 0x96005000, 0x1000 },
+ [VIRT_VIRTIO] = { 0x97000000, 0x1000 },
+ [VIRT_OMPIC] = { 0x98000000, VIRT_CPUS_MAX * 8 },
+};
+
+static struct openrisc_boot_info {
+ uint32_t bootstrap_pc;
+ uint32_t fdt_addr;
+} boot_info;
+
+static void main_cpu_reset(void *opaque)
+{
+ OpenRISCCPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
+
+ cpu_reset(CPU(cpu));
+
+ cpu_set_pc(cs, boot_info.bootstrap_pc);
+ cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr);
+}
+
+static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin)
+{
+ return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin);
+}
+
+static qemu_irq get_per_cpu_irq(OpenRISCCPU *cpus[], int num_cpus, int irq_pin)
+{
+ int i;
+
+ if (num_cpus > 1) {
+ DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ);
+ qdev_prop_set_uint32(splitter, "num-lines", num_cpus);
+ qdev_realize_and_unref(splitter, NULL, &error_fatal);
+ for (i = 0; i < num_cpus; i++) {
+ qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin));
+ }
+ return qdev_get_gpio_in(splitter, 0);
+ } else {
+ return get_cpu_irq(cpus, 0, irq_pin);
+ }
+}
+
+static void openrisc_create_fdt(OR1KVirtState *state,
+ const struct MemmapEntry *memmap,
+ int num_cpus, uint64_t mem_size,
+ const char *cmdline)
+{
+ void *fdt;
+ int cpu;
+ char *nodename;
+ int pic_ph;
+
+ fdt = state->fdt = create_device_tree(&state->fdt_size);
+ if (!fdt) {
+ error_report("create_device_tree() failed");
+ exit(1);
+ }
+
+ qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim");
+ qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1);
+ qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);
+
+ qemu_fdt_add_subnode(fdt, "/soc");
+ qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
+ qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
+ qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1);
+ qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1);
+
+ nodename = g_strdup_printf("/memory@%" HWADDR_PRIx,
+ memmap[VIRT_DRAM].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ memmap[VIRT_DRAM].base, mem_size);
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
+ g_free(nodename);
+
+ qemu_fdt_add_subnode(fdt, "/cpus");
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
+ qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
+
+ for (cpu = 0; cpu < num_cpus; cpu++) {
+ nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "opencores,or1200-rtlsvn481");
+ qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
+ VIRT_CLK_MHZ);
+ g_free(nodename);
+ }
+
+ nodename = (char *)"/pic";
+ qemu_fdt_add_subnode(fdt, nodename);
+ pic_ph = qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "opencores,or1k-pic-level");
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", pic_ph);
+
+ qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", pic_ph);
+
+ qemu_fdt_add_subnode(fdt, "/chosen");
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
+
+ /* Create aliases node for use by devices. */
+ qemu_fdt_add_subnode(fdt, "/aliases");
+}
+
+static void openrisc_virt_ompic_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ DeviceState *dev;
+ SysBusDevice *s;
+ char *nodename;
+ int i;
+
+ dev = qdev_new("or1k-ompic");
+ qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
+
+ s = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(s, &error_fatal);
+ for (i = 0; i < num_cpus; i++) {
+ sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin));
+ }
+ sysbus_mmio_map(s, 0, base);
+
+ /* Add device tree node for ompic. */
+ nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+}
+
+static void openrisc_virt_serial_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ qemu_irq serial_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
+ serial_hd(0), DEVICE_NATIVE_ENDIAN);
+
+ /* Add device tree node for serial. */
+ nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", VIRT_CLK_MHZ);
+ qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
+
+ /* The /chosen node is created during fdt creation. */
+ qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
+ qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);
+ g_free(nodename);
+}
+
+static void openrisc_virt_test_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size)
+{
+ void *fdt = state->fdt;
+ int test_ph;
+ char *nodename;
+
+ /* SiFive Test MMIO device */
+ sifive_test_create(base);
+
+ /* SiFive Test MMIO Reset device FDT */
+ nodename = g_strdup_printf("/soc/test@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon");
+ test_ph = qemu_fdt_alloc_phandle(fdt);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_ph);
+ qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/reboot");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot");
+ qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
+ qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
+ qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET);
+ g_free(nodename);
+
+ nodename = g_strdup_printf("/soc/poweroff");
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff");
+ qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph);
+ qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0);
+ qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS);
+ g_free(nodename);
+
+}
+static void openrisc_virt_rtc_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ DeviceState *dev;
+ SysBusDevice *sysbus;
+ qemu_irq rtc_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ /* Goldfish RTC */
+ dev = qdev_new(TYPE_GOLDFISH_RTC);
+ qdev_prop_set_uint8(dev, "endianness", DEVICE_LITTLE_ENDIAN);
+ sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
+ sysbus_connect_irq(sysbus, 0, rtc_irq);
+ sysbus_mmio_map(sysbus, 0, base);
+
+ /* Goldfish RTC FDT */
+ nodename = g_strdup_printf("/soc/rtc@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "google,goldfish-rtc");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+
+}
+static void openrisc_virt_virtio_init(OR1KVirtState *state, hwaddr base,
+ hwaddr size, int num_cpus,
+ OpenRISCCPU *cpus[], int irq_pin)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ DeviceState *dev;
+ SysBusDevice *sysbus;
+ qemu_irq virtio_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin);
+
+ /* VirtIO MMIO devices */
+ dev = qdev_new(TYPE_VIRTIO_MMIO);
+ qdev_prop_set_bit(dev, "force-legacy", false);
+ sysbus = SYS_BUS_DEVICE(dev);
+ sysbus_realize_and_unref(sysbus, &error_fatal);
+ sysbus_connect_irq(sysbus, 0, virtio_irq);
+ sysbus_mmio_map(sysbus, 0, base);
+
+ /* VirtIO MMIO devices FDT */
+ nodename = g_strdup_printf("/soc/virtio_mmio@%" HWADDR_PRIx, base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio");
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin);
+ g_free(nodename);
+}
+
+static void openrisc_virt_init(MachineState *machine)
+{
+ ram_addr_t ram_size = machine->ram_size;
+ const char *kernel_filename = machine->kernel_filename;
+ OpenRISCCPU *cpus[VIRT_CPUS_MAX] = {};
+ OR1KVirtState *state = VIRT_MACHINE(machine);
+ MemoryRegion *ram;
+ hwaddr load_addr;
+ int n;
+ unsigned int smp_cpus = machine->smp.cpus;
+
+ assert(smp_cpus >= 1 && smp_cpus <= VIRT_CPUS_MAX);
+ for (n = 0; n < smp_cpus; n++) {
+ cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
+ if (cpus[n] == NULL) {
+ fprintf(stderr, "Unable to find CPU definition!\n");
+ exit(1);
+ }
+
+ cpu_openrisc_clock_init(cpus[n]);
+
+ qemu_register_reset(main_cpu_reset, cpus[n]);
+ }
+
+ ram = g_malloc(sizeof(*ram));
+ memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), 0, ram);
+
+ openrisc_create_fdt(state, virt_memmap, smp_cpus, machine->ram_size,
+ machine->kernel_cmdline);
+
+ if (smp_cpus > 1) {
+ openrisc_virt_ompic_init(state, virt_memmap[VIRT_OMPIC].base,
+ virt_memmap[VIRT_OMPIC].size,
+ smp_cpus, cpus, VIRT_OMPIC_IRQ);
+ }
+
+ openrisc_virt_serial_init(state, virt_memmap[VIRT_UART].base,
+ virt_memmap[VIRT_UART].size,
+ smp_cpus, cpus, VIRT_UART_IRQ);
+
+ openrisc_virt_test_init(state, virt_memmap[VIRT_TEST].base,
+ virt_memmap[VIRT_TEST].size);
+
+ openrisc_virt_rtc_init(state, virt_memmap[VIRT_RTC].base,
+ virt_memmap[VIRT_RTC].size, smp_cpus, cpus,
+ VIRT_RTC_IRQ);
+
+ for (n = 0; n < VIRTIO_COUNT; n++) {
+ openrisc_virt_virtio_init(state, virt_memmap[VIRT_VIRTIO].base
+ + n * virt_memmap[VIRT_VIRTIO].size,
+ virt_memmap[VIRT_VIRTIO].size,
+ smp_cpus, cpus, VIRT_VIRTIO_IRQ + n);
+ }
+
+ load_addr = openrisc_load_kernel(ram_size, kernel_filename,
+ &boot_info.bootstrap_pc);
+ if (load_addr > 0) {
+ if (machine->initrd_filename) {
+ load_addr = openrisc_load_initrd(state->fdt,
+ machine->initrd_filename,
+ load_addr, machine->ram_size);
+ }
+ boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr,
+ machine->ram_size);
+ }
+}
+
+static void openrisc_virt_machine_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "or1k virtual machine";
+ mc->init = openrisc_virt_init;
+ mc->max_cpus = VIRT_CPUS_MAX;
+ mc->is_default = false;
+ mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
+}
+
+static const TypeInfo or1ksim_machine_typeinfo = {
+ .name = TYPE_VIRT_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = openrisc_virt_machine_init,
+ .instance_size = sizeof(OR1KVirtState),
+};
+
+static void or1ksim_machine_init_register_types(void)
+{
+ type_register_static(&or1ksim_machine_typeinfo);
+}
+
+type_init(or1ksim_machine_init_register_types)
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 05/11] hw/openrisc: Add PCI bus support to virt
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-03 21:28 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc
This is mostly borrowed from xtensa and riscv as examples. The
create_pcie_irq_map swizzle function is almost and exact copy
but here we use a single cell interrupt, possibly we can make
this generic.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/Kconfig | 3 +
hw/openrisc/virt.c | 160 ++++++++++++++++++++++++++++++++++++++++++--
2 files changed, 157 insertions(+), 6 deletions(-)
diff --git a/hw/openrisc/Kconfig b/hw/openrisc/Kconfig
index 202134668e..97af258b55 100644
--- a/hw/openrisc/Kconfig
+++ b/hw/openrisc/Kconfig
@@ -7,8 +7,11 @@ config OR1K_SIM
config OR1K_VIRT
bool
+ imply PCI_DEVICES
imply VIRTIO_VGA
imply TEST_DEVICES
+ select PCI
+ select PCI_EXPRESS_GENERIC_BRIDGE
select GOLDFISH_RTC
select SERIAL
select SIFIVE_TEST
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
index bdb00f6e32..f1d1293eeb 100644
--- a/hw/openrisc/virt.c
+++ b/hw/openrisc/virt.c
@@ -17,6 +17,8 @@
#include "hw/core/split-irq.h"
#include "hw/openrisc/boot.h"
#include "hw/misc/sifive_test.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/gpex.h"
#include "hw/qdev-properties.h"
#include "hw/rtc/goldfish_rtc.h"
#include "hw/sysbus.h"
@@ -47,6 +49,9 @@ typedef struct OR1KVirtState {
enum {
VIRT_DRAM,
+ VIRT_ECAM,
+ VIRT_MMIO,
+ VIRT_PIO,
VIRT_TEST,
VIRT_RTC,
VIRT_VIRTIO,
@@ -60,6 +65,7 @@ enum {
VIRT_RTC_IRQ = 3,
VIRT_VIRTIO_IRQ = 4, /* to 12 */
VIRTIO_COUNT = 8,
+ VIRT_PCI_IRQ_BASE = 13, /* to 17 */
};
static const struct MemmapEntry {
@@ -72,6 +78,9 @@ static const struct MemmapEntry {
[VIRT_RTC] = { 0x96005000, 0x1000 },
[VIRT_VIRTIO] = { 0x97000000, 0x1000 },
[VIRT_OMPIC] = { 0x98000000, VIRT_CPUS_MAX * 8 },
+ [VIRT_ECAM] = { 0x9e000000, 0x1000000 },
+ [VIRT_PIO] = { 0x9f000000, 0x1000000 },
+ [VIRT_MMIO] = { 0xa0000000, 0x10000000 },
};
static struct openrisc_boot_info {
@@ -115,12 +124,12 @@ static qemu_irq get_per_cpu_irq(OpenRISCCPU *cpus[], int num_cpus, int irq_pin)
static void openrisc_create_fdt(OR1KVirtState *state,
const struct MemmapEntry *memmap,
int num_cpus, uint64_t mem_size,
- const char *cmdline)
+ const char *cmdline,
+ int32_t *pic_phandle)
{
void *fdt;
int cpu;
char *nodename;
- int pic_ph;
fdt = state->fdt = create_device_tree(&state->fdt_size);
if (!fdt) {
@@ -163,14 +172,14 @@ static void openrisc_create_fdt(OR1KVirtState *state,
nodename = (char *)"/pic";
qemu_fdt_add_subnode(fdt, nodename);
- pic_ph = qemu_fdt_alloc_phandle(fdt);
+ *pic_phandle = qemu_fdt_alloc_phandle(fdt);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"opencores,or1k-pic-level");
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop_cell(fdt, nodename, "phandle", pic_ph);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", *pic_phandle);
- qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", pic_ph);
+ qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", *pic_phandle);
qemu_fdt_add_subnode(fdt, "/chosen");
if (cmdline) {
@@ -275,6 +284,7 @@ static void openrisc_virt_test_init(OR1KVirtState *state, hwaddr base,
g_free(nodename);
}
+
static void openrisc_virt_rtc_init(OR1KVirtState *state, hwaddr base,
hwaddr size, int num_cpus,
OpenRISCCPU *cpus[], int irq_pin)
@@ -303,6 +313,134 @@ static void openrisc_virt_rtc_init(OR1KVirtState *state, hwaddr base,
g_free(nodename);
}
+
+static void create_pcie_irq_map(void *fdt, char *nodename, int irq_base,
+ uint32_t irqchip_phandle)
+{
+ int pin, dev;
+ uint32_t irq_map_stride = 0;
+ uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 6] = {};
+ uint32_t *irq_map = full_irq_map;
+
+ /*
+ * This code creates a standard swizzle of interrupts such that
+ * each device's first interrupt is based on it's PCI_SLOT number.
+ * (See pci_swizzle_map_irq_fn())
+ *
+ * We only need one entry per interrupt in the table (not one per
+ * possible slot) seeing the interrupt-map-mask will allow the table
+ * to wrap to any number of devices.
+ */
+ for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
+ int devfn = dev << 3;
+
+ for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
+ int irq_nr = irq_base + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
+ int i = 0;
+
+ /* Fill PCI address cells */
+ irq_map[i++] = cpu_to_be32(devfn << 8);
+ irq_map[i++] = 0;
+ irq_map[i++] = 0;
+
+ /* Fill PCI Interrupt cells */
+ irq_map[i++] = cpu_to_be32(pin + 1);
+
+ /* Fill interrupt controller phandle and cells */
+ irq_map[i++] = cpu_to_be32(irqchip_phandle);
+ irq_map[i++] = cpu_to_be32(irq_nr);
+
+ if (!irq_map_stride) {
+ irq_map_stride = i;
+ }
+ irq_map += irq_map_stride;
+ }
+ }
+
+ qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
+ GPEX_NUM_IRQS * GPEX_NUM_IRQS *
+ irq_map_stride * sizeof(uint32_t));
+
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
+ 0x1800, 0, 0, 0x7);
+}
+
+static void openrisc_virt_pcie_init(OR1KVirtState *state,
+ hwaddr ecam_base, hwaddr ecam_size,
+ hwaddr pio_base, hwaddr pio_size,
+ hwaddr mmio_base, hwaddr mmio_size,
+ int num_cpus, OpenRISCCPU *cpus[],
+ int irq_base, int32_t pic_phandle)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ MemoryRegion *alias;
+ MemoryRegion *reg;
+ DeviceState *dev;
+ qemu_irq pcie_irq;
+ int i;
+
+ dev = qdev_new(TYPE_GPEX_HOST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ /* Map ECAM space. */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-ecam",
+ reg, 0, ecam_size);
+ memory_region_add_subregion(get_system_memory(), ecam_base, alias);
+
+ /*
+ * Map the MMIO window into system address space so as to expose
+ * the section of PCI MMIO space which starts at the same base address
+ * (ie 1:1 mapping for that part of PCI MMIO space visible through
+ * the window).
+ */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-mmio",
+ reg, mmio_base, mmio_size);
+ memory_region_add_subregion(get_system_memory(), mmio_base, alias);
+
+ /* Map IO port space. */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-pio",
+ reg, 0, pio_size);
+ memory_region_add_subregion(get_system_memory(), pio_base, alias);
+
+ /* Connect IRQ lines. */
+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
+ pcie_irq = get_per_cpu_irq(cpus, num_cpus, irq_base + i);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pcie_irq);
+ gpex_set_irq_num(GPEX_HOST(dev), i, irq_base + i);
+ }
+
+ nodename = g_strdup_printf("/soc/pci@%" HWADDR_PRIx, ecam_base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
+ qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 3);
+ qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 2);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "pci-host-ecam-generic");
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
+ qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
+ qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
+ ecam_size / PCIE_MMCFG_SIZE_MIN - 1);
+ qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", ecam_base, ecam_size);
+ /* pci-address(3) cpu-address(1) pci-size(2) */
+ qemu_fdt_setprop_cells(fdt, nodename, "ranges",
+ FDT_PCI_RANGE_IOPORT, 0, 0,
+ pio_base, 0, pio_size,
+ FDT_PCI_RANGE_MMIO, 0, mmio_base,
+ mmio_base, 0, mmio_size);
+
+ create_pcie_irq_map(fdt, nodename, irq_base, pic_phandle);
+ g_free(nodename);
+}
+
static void openrisc_virt_virtio_init(OR1KVirtState *state, hwaddr base,
hwaddr size, int num_cpus,
OpenRISCCPU *cpus[], int irq_pin)
@@ -340,6 +478,7 @@ static void openrisc_virt_init(MachineState *machine)
hwaddr load_addr;
int n;
unsigned int smp_cpus = machine->smp.cpus;
+ int32_t pic_phandle;
assert(smp_cpus >= 1 && smp_cpus <= VIRT_CPUS_MAX);
for (n = 0; n < smp_cpus; n++) {
@@ -359,7 +498,7 @@ static void openrisc_virt_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), 0, ram);
openrisc_create_fdt(state, virt_memmap, smp_cpus, machine->ram_size,
- machine->kernel_cmdline);
+ machine->kernel_cmdline, &pic_phandle);
if (smp_cpus > 1) {
openrisc_virt_ompic_init(state, virt_memmap[VIRT_OMPIC].base,
@@ -378,6 +517,15 @@ static void openrisc_virt_init(MachineState *machine)
virt_memmap[VIRT_RTC].size, smp_cpus, cpus,
VIRT_RTC_IRQ);
+ openrisc_virt_pcie_init(state, virt_memmap[VIRT_ECAM].base,
+ virt_memmap[VIRT_ECAM].size,
+ virt_memmap[VIRT_PIO].base,
+ virt_memmap[VIRT_PIO].size,
+ virt_memmap[VIRT_MMIO].base,
+ virt_memmap[VIRT_MMIO].size,
+ smp_cpus, cpus,
+ VIRT_PCI_IRQ_BASE, pic_phandle);
+
for (n = 0; n < VIRTIO_COUNT; n++) {
openrisc_virt_virtio_init(state, virt_memmap[VIRT_VIRTIO].base
+ n * virt_memmap[VIRT_VIRTIO].size,
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 05/11] hw/openrisc: Add PCI bus support to virt
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Stafford Horne
This is mostly borrowed from xtensa and riscv as examples. The
create_pcie_irq_map swizzle function is almost and exact copy
but here we use a single cell interrupt, possibly we can make
this generic.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/Kconfig | 3 +
hw/openrisc/virt.c | 160 ++++++++++++++++++++++++++++++++++++++++++--
2 files changed, 157 insertions(+), 6 deletions(-)
diff --git a/hw/openrisc/Kconfig b/hw/openrisc/Kconfig
index 202134668e..97af258b55 100644
--- a/hw/openrisc/Kconfig
+++ b/hw/openrisc/Kconfig
@@ -7,8 +7,11 @@ config OR1K_SIM
config OR1K_VIRT
bool
+ imply PCI_DEVICES
imply VIRTIO_VGA
imply TEST_DEVICES
+ select PCI
+ select PCI_EXPRESS_GENERIC_BRIDGE
select GOLDFISH_RTC
select SERIAL
select SIFIVE_TEST
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
index bdb00f6e32..f1d1293eeb 100644
--- a/hw/openrisc/virt.c
+++ b/hw/openrisc/virt.c
@@ -17,6 +17,8 @@
#include "hw/core/split-irq.h"
#include "hw/openrisc/boot.h"
#include "hw/misc/sifive_test.h"
+#include "hw/pci/pci.h"
+#include "hw/pci-host/gpex.h"
#include "hw/qdev-properties.h"
#include "hw/rtc/goldfish_rtc.h"
#include "hw/sysbus.h"
@@ -47,6 +49,9 @@ typedef struct OR1KVirtState {
enum {
VIRT_DRAM,
+ VIRT_ECAM,
+ VIRT_MMIO,
+ VIRT_PIO,
VIRT_TEST,
VIRT_RTC,
VIRT_VIRTIO,
@@ -60,6 +65,7 @@ enum {
VIRT_RTC_IRQ = 3,
VIRT_VIRTIO_IRQ = 4, /* to 12 */
VIRTIO_COUNT = 8,
+ VIRT_PCI_IRQ_BASE = 13, /* to 17 */
};
static const struct MemmapEntry {
@@ -72,6 +78,9 @@ static const struct MemmapEntry {
[VIRT_RTC] = { 0x96005000, 0x1000 },
[VIRT_VIRTIO] = { 0x97000000, 0x1000 },
[VIRT_OMPIC] = { 0x98000000, VIRT_CPUS_MAX * 8 },
+ [VIRT_ECAM] = { 0x9e000000, 0x1000000 },
+ [VIRT_PIO] = { 0x9f000000, 0x1000000 },
+ [VIRT_MMIO] = { 0xa0000000, 0x10000000 },
};
static struct openrisc_boot_info {
@@ -115,12 +124,12 @@ static qemu_irq get_per_cpu_irq(OpenRISCCPU *cpus[], int num_cpus, int irq_pin)
static void openrisc_create_fdt(OR1KVirtState *state,
const struct MemmapEntry *memmap,
int num_cpus, uint64_t mem_size,
- const char *cmdline)
+ const char *cmdline,
+ int32_t *pic_phandle)
{
void *fdt;
int cpu;
char *nodename;
- int pic_ph;
fdt = state->fdt = create_device_tree(&state->fdt_size);
if (!fdt) {
@@ -163,14 +172,14 @@ static void openrisc_create_fdt(OR1KVirtState *state,
nodename = (char *)"/pic";
qemu_fdt_add_subnode(fdt, nodename);
- pic_ph = qemu_fdt_alloc_phandle(fdt);
+ *pic_phandle = qemu_fdt_alloc_phandle(fdt);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"opencores,or1k-pic-level");
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
- qemu_fdt_setprop_cell(fdt, nodename, "phandle", pic_ph);
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", *pic_phandle);
- qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", pic_ph);
+ qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", *pic_phandle);
qemu_fdt_add_subnode(fdt, "/chosen");
if (cmdline) {
@@ -275,6 +284,7 @@ static void openrisc_virt_test_init(OR1KVirtState *state, hwaddr base,
g_free(nodename);
}
+
static void openrisc_virt_rtc_init(OR1KVirtState *state, hwaddr base,
hwaddr size, int num_cpus,
OpenRISCCPU *cpus[], int irq_pin)
@@ -303,6 +313,134 @@ static void openrisc_virt_rtc_init(OR1KVirtState *state, hwaddr base,
g_free(nodename);
}
+
+static void create_pcie_irq_map(void *fdt, char *nodename, int irq_base,
+ uint32_t irqchip_phandle)
+{
+ int pin, dev;
+ uint32_t irq_map_stride = 0;
+ uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 6] = {};
+ uint32_t *irq_map = full_irq_map;
+
+ /*
+ * This code creates a standard swizzle of interrupts such that
+ * each device's first interrupt is based on it's PCI_SLOT number.
+ * (See pci_swizzle_map_irq_fn())
+ *
+ * We only need one entry per interrupt in the table (not one per
+ * possible slot) seeing the interrupt-map-mask will allow the table
+ * to wrap to any number of devices.
+ */
+ for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
+ int devfn = dev << 3;
+
+ for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
+ int irq_nr = irq_base + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
+ int i = 0;
+
+ /* Fill PCI address cells */
+ irq_map[i++] = cpu_to_be32(devfn << 8);
+ irq_map[i++] = 0;
+ irq_map[i++] = 0;
+
+ /* Fill PCI Interrupt cells */
+ irq_map[i++] = cpu_to_be32(pin + 1);
+
+ /* Fill interrupt controller phandle and cells */
+ irq_map[i++] = cpu_to_be32(irqchip_phandle);
+ irq_map[i++] = cpu_to_be32(irq_nr);
+
+ if (!irq_map_stride) {
+ irq_map_stride = i;
+ }
+ irq_map += irq_map_stride;
+ }
+ }
+
+ qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map,
+ GPEX_NUM_IRQS * GPEX_NUM_IRQS *
+ irq_map_stride * sizeof(uint32_t));
+
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
+ 0x1800, 0, 0, 0x7);
+}
+
+static void openrisc_virt_pcie_init(OR1KVirtState *state,
+ hwaddr ecam_base, hwaddr ecam_size,
+ hwaddr pio_base, hwaddr pio_size,
+ hwaddr mmio_base, hwaddr mmio_size,
+ int num_cpus, OpenRISCCPU *cpus[],
+ int irq_base, int32_t pic_phandle)
+{
+ void *fdt = state->fdt;
+ char *nodename;
+ MemoryRegion *alias;
+ MemoryRegion *reg;
+ DeviceState *dev;
+ qemu_irq pcie_irq;
+ int i;
+
+ dev = qdev_new(TYPE_GPEX_HOST);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+
+ /* Map ECAM space. */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-ecam",
+ reg, 0, ecam_size);
+ memory_region_add_subregion(get_system_memory(), ecam_base, alias);
+
+ /*
+ * Map the MMIO window into system address space so as to expose
+ * the section of PCI MMIO space which starts at the same base address
+ * (ie 1:1 mapping for that part of PCI MMIO space visible through
+ * the window).
+ */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-mmio",
+ reg, mmio_base, mmio_size);
+ memory_region_add_subregion(get_system_memory(), mmio_base, alias);
+
+ /* Map IO port space. */
+ alias = g_new0(MemoryRegion, 1);
+ reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2);
+ memory_region_init_alias(alias, OBJECT(dev), "pcie-pio",
+ reg, 0, pio_size);
+ memory_region_add_subregion(get_system_memory(), pio_base, alias);
+
+ /* Connect IRQ lines. */
+ for (i = 0; i < GPEX_NUM_IRQS; i++) {
+ pcie_irq = get_per_cpu_irq(cpus, num_cpus, irq_base + i);
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pcie_irq);
+ gpex_set_irq_num(GPEX_HOST(dev), i, irq_base + i);
+ }
+
+ nodename = g_strdup_printf("/soc/pci@%" HWADDR_PRIx, ecam_base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
+ qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 3);
+ qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 2);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "pci-host-ecam-generic");
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
+ qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
+ qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
+ ecam_size / PCIE_MMCFG_SIZE_MIN - 1);
+ qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg", ecam_base, ecam_size);
+ /* pci-address(3) cpu-address(1) pci-size(2) */
+ qemu_fdt_setprop_cells(fdt, nodename, "ranges",
+ FDT_PCI_RANGE_IOPORT, 0, 0,
+ pio_base, 0, pio_size,
+ FDT_PCI_RANGE_MMIO, 0, mmio_base,
+ mmio_base, 0, mmio_size);
+
+ create_pcie_irq_map(fdt, nodename, irq_base, pic_phandle);
+ g_free(nodename);
+}
+
static void openrisc_virt_virtio_init(OR1KVirtState *state, hwaddr base,
hwaddr size, int num_cpus,
OpenRISCCPU *cpus[], int irq_pin)
@@ -340,6 +478,7 @@ static void openrisc_virt_init(MachineState *machine)
hwaddr load_addr;
int n;
unsigned int smp_cpus = machine->smp.cpus;
+ int32_t pic_phandle;
assert(smp_cpus >= 1 && smp_cpus <= VIRT_CPUS_MAX);
for (n = 0; n < smp_cpus; n++) {
@@ -359,7 +498,7 @@ static void openrisc_virt_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), 0, ram);
openrisc_create_fdt(state, virt_memmap, smp_cpus, machine->ram_size,
- machine->kernel_cmdline);
+ machine->kernel_cmdline, &pic_phandle);
if (smp_cpus > 1) {
openrisc_virt_ompic_init(state, virt_memmap[VIRT_OMPIC].base,
@@ -378,6 +517,15 @@ static void openrisc_virt_init(MachineState *machine)
virt_memmap[VIRT_RTC].size, smp_cpus, cpus,
VIRT_RTC_IRQ);
+ openrisc_virt_pcie_init(state, virt_memmap[VIRT_ECAM].base,
+ virt_memmap[VIRT_ECAM].size,
+ virt_memmap[VIRT_PIO].base,
+ virt_memmap[VIRT_PIO].size,
+ virt_memmap[VIRT_MMIO].base,
+ virt_memmap[VIRT_MMIO].size,
+ smp_cpus, cpus,
+ VIRT_PCI_IRQ_BASE, pic_phandle);
+
for (n = 0; n < VIRTIO_COUNT; n++) {
openrisc_virt_virtio_init(state, virt_memmap[VIRT_VIRTIO].base
+ n * virt_memmap[VIRT_VIRTIO].size,
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 06/11] hw/openrisc: Initialize timer time at startup
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-03 21:28 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc
The last_clk time was initialized at zero, this means when we calculate
the first delta we will calculate 0 vs current time which could cause
unnecessary hops.
Initialize last_clk to the qemu clock on initialization.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/cputimer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
index 93268815d8..4dbba3a3d4 100644
--- a/hw/openrisc/cputimer.c
+++ b/hw/openrisc/cputimer.c
@@ -140,6 +140,7 @@ void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
if (or1k_timer == NULL) {
or1k_timer = g_new0(OR1KTimerState, 1);
+ or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);
}
}
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 06/11] hw/openrisc: Initialize timer time at startup
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Stafford Horne
The last_clk time was initialized at zero, this means when we calculate
the first delta we will calculate 0 vs current time which could cause
unnecessary hops.
Initialize last_clk to the qemu clock on initialization.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/cputimer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
index 93268815d8..4dbba3a3d4 100644
--- a/hw/openrisc/cputimer.c
+++ b/hw/openrisc/cputimer.c
@@ -140,6 +140,7 @@ void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
if (or1k_timer == NULL) {
or1k_timer = g_new0(OR1KTimerState, 1);
+ or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);
}
}
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 07/11] target/openrisc: Add interrupted CPU to log
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-03 21:28 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc
When we are tracing it's helpful to know which CPU's are getting
interrupted, att that detail to the log line.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index e5724f5371..c31c6f12c4 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -83,7 +83,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
[EXCP_TRAP] = "TRAP",
};
- qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]);
+ qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n",
+ cs->cpu_index,
+ int_name[exception]);
hwaddr vect_pc = exception << 8;
if (env->cpucfgr & CPUCFGR_EVBARP) {
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 07/11] target/openrisc: Add interrupted CPU to log
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Stafford Horne
When we are tracing it's helpful to know which CPU's are getting
interrupted, att that detail to the log line.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index e5724f5371..c31c6f12c4 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -83,7 +83,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
[EXCP_TRAP] = "TRAP",
};
- qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]);
+ qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n",
+ cs->cpu_index,
+ int_name[exception]);
hwaddr vect_pc = exception << 8;
if (env->cpucfgr & CPUCFGR_EVBARP) {
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 08/11] target/openrisc: Enable MTTCG
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-03 21:28 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
configs/targets/or1k-softmmu.mak | 1 +
hw/openrisc/cputimer.c | 17 +++++++++++++++++
target/openrisc/cpu.h | 3 +++
target/openrisc/sys_helper.c | 11 +++++++++--
4 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmmu.mak
index 263e970870..432f855a30 100644
--- a/configs/targets/or1k-softmmu.mak
+++ b/configs/targets/or1k-softmmu.mak
@@ -1,3 +1,4 @@
TARGET_ARCH=openrisc
+TARGET_SUPPORTS_MTTCG=y
TARGET_BIG_ENDIAN=y
TARGET_NEED_FDT=y
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
index 4dbba3a3d4..2298eff8b9 100644
--- a/hw/openrisc/cputimer.c
+++ b/hw/openrisc/cputimer.c
@@ -43,6 +43,23 @@ uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu)
return or1k_timer->ttcr;
}
+/*
+ * Check to see if calling cpu_openrisc_count_update will
+ * actually advance the time.
+ *
+ * Used in hot spots to avoid taking expensive locks.
+ */
+bool cpu_openrisc_timer_has_advanced(OpenRISCCPU *cpu)
+{
+ uint64_t now;
+
+ if (!cpu->env.is_counting) {
+ return false;
+ }
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ return (now - or1k_timer->last_clk) >= TIMER_PERIOD;
+}
+
/* Add elapsed ticks to ttcr */
void cpu_openrisc_count_update(OpenRISCCPU *cpu)
{
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b9584f10d4..5354d681f5 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -25,6 +25,8 @@
#include "hw/core/cpu.h"
#include "qom/object.h"
+#define TCG_GUEST_DEFAULT_MO (0)
+
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
@@ -333,6 +335,7 @@ void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
/* hw/openrisc_timer.c */
void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
+bool cpu_openrisc_timer_has_advanced(OpenRISCCPU *cpu);
uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu);
void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val);
void cpu_openrisc_count_update(OpenRISCCPU *cpu);
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 48674231e7..7c0d3d6187 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -145,6 +145,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
break;
case TO_SPR(10, 0): /* TTMR */
{
+ qemu_mutex_lock_iothread();
if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
switch (rb & TTMR_M) {
case TIMER_NONE:
@@ -168,14 +169,16 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
env->ttmr = rb & ~TTMR_IP;
cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
}
-
cpu_openrisc_timer_update(cpu);
+ qemu_mutex_unlock_iothread();
}
break;
case TO_SPR(10, 1): /* TTCR */
+ qemu_mutex_lock_iothread();
cpu_openrisc_count_set(cpu, rb);
cpu_openrisc_timer_update(cpu);
+ qemu_mutex_unlock_iothread();
break;
#endif
@@ -303,7 +306,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
return env->ttmr;
case TO_SPR(10, 1): /* TTCR */
- cpu_openrisc_count_update(cpu);
+ if (cpu_openrisc_timer_has_advanced(cpu)) {
+ qemu_mutex_lock_iothread();
+ cpu_openrisc_count_update(cpu);
+ qemu_mutex_unlock_iothread();
+ }
return cpu_openrisc_count_get(cpu);
#endif
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 08/11] target/openrisc: Enable MTTCG
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Stafford Horne
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
configs/targets/or1k-softmmu.mak | 1 +
hw/openrisc/cputimer.c | 17 +++++++++++++++++
target/openrisc/cpu.h | 3 +++
target/openrisc/sys_helper.c | 11 +++++++++--
4 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmmu.mak
index 263e970870..432f855a30 100644
--- a/configs/targets/or1k-softmmu.mak
+++ b/configs/targets/or1k-softmmu.mak
@@ -1,3 +1,4 @@
TARGET_ARCH=openrisc
+TARGET_SUPPORTS_MTTCG=y
TARGET_BIG_ENDIAN=y
TARGET_NEED_FDT=y
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
index 4dbba3a3d4..2298eff8b9 100644
--- a/hw/openrisc/cputimer.c
+++ b/hw/openrisc/cputimer.c
@@ -43,6 +43,23 @@ uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu)
return or1k_timer->ttcr;
}
+/*
+ * Check to see if calling cpu_openrisc_count_update will
+ * actually advance the time.
+ *
+ * Used in hot spots to avoid taking expensive locks.
+ */
+bool cpu_openrisc_timer_has_advanced(OpenRISCCPU *cpu)
+{
+ uint64_t now;
+
+ if (!cpu->env.is_counting) {
+ return false;
+ }
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ return (now - or1k_timer->last_clk) >= TIMER_PERIOD;
+}
+
/* Add elapsed ticks to ttcr */
void cpu_openrisc_count_update(OpenRISCCPU *cpu)
{
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b9584f10d4..5354d681f5 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -25,6 +25,8 @@
#include "hw/core/cpu.h"
#include "qom/object.h"
+#define TCG_GUEST_DEFAULT_MO (0)
+
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
@@ -333,6 +335,7 @@ void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
/* hw/openrisc_timer.c */
void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
+bool cpu_openrisc_timer_has_advanced(OpenRISCCPU *cpu);
uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu);
void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val);
void cpu_openrisc_count_update(OpenRISCCPU *cpu);
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 48674231e7..7c0d3d6187 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -145,6 +145,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
break;
case TO_SPR(10, 0): /* TTMR */
{
+ qemu_mutex_lock_iothread();
if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
switch (rb & TTMR_M) {
case TIMER_NONE:
@@ -168,14 +169,16 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
env->ttmr = rb & ~TTMR_IP;
cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
}
-
cpu_openrisc_timer_update(cpu);
+ qemu_mutex_unlock_iothread();
}
break;
case TO_SPR(10, 1): /* TTCR */
+ qemu_mutex_lock_iothread();
cpu_openrisc_count_set(cpu, rb);
cpu_openrisc_timer_update(cpu);
+ qemu_mutex_unlock_iothread();
break;
#endif
@@ -303,7 +306,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
return env->ttmr;
case TO_SPR(10, 1): /* TTCR */
- cpu_openrisc_count_update(cpu);
+ if (cpu_openrisc_timer_has_advanced(cpu)) {
+ qemu_mutex_lock_iothread();
+ cpu_openrisc_count_update(cpu);
+ qemu_mutex_unlock_iothread();
+ }
return cpu_openrisc_count_get(cpu);
#endif
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 09/11] target/openrisc: Interrupt handling fixes
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-03 21:28 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc
When running SMP systems we sometimes were seeing lockups where
IPI interrupts were being raised by never handled.
This looks to be caused by 2 issues in the openrisc interrupt handling
logic.
1. After clearing an interrupt the openrisc_cpu_set_irq handler will
always clear PICSR. This is not correct as masked interrupts
should still be visible in PICSR.
2. After setting PICMR (mask register) and exposed interrupts should
cause an interrupt to be raised. This was not being done so add it.
This patch fixes both issues.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.c | 1 -
target/openrisc/sys_helper.c | 7 +++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 41d1b2a24a..cb9f35f408 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -98,7 +98,6 @@ static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
- cpu->env.picsr = 0;
}
}
#endif
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 7c0d3d6187..5336110b5e 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -139,6 +139,13 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
break;
case TO_SPR(9, 0): /* PICMR */
env->picmr = rb;
+ qemu_mutex_lock_iothread();
+ if (env->picsr & env->picmr) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+ qemu_mutex_unlock_iothread();
break;
case TO_SPR(9, 2): /* PICSR */
env->picsr &= ~rb;
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 09/11] target/openrisc: Interrupt handling fixes
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Stafford Horne
When running SMP systems we sometimes were seeing lockups where
IPI interrupts were being raised by never handled.
This looks to be caused by 2 issues in the openrisc interrupt handling
logic.
1. After clearing an interrupt the openrisc_cpu_set_irq handler will
always clear PICSR. This is not correct as masked interrupts
should still be visible in PICSR.
2. After setting PICMR (mask register) and exposed interrupts should
cause an interrupt to be raised. This was not being done so add it.
This patch fixes both issues.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.c | 1 -
target/openrisc/sys_helper.c | 7 +++++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 41d1b2a24a..cb9f35f408 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -98,7 +98,6 @@ static void openrisc_cpu_set_irq(void *opaque, int irq, int level)
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
- cpu->env.picsr = 0;
}
}
#endif
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 7c0d3d6187..5336110b5e 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -139,6 +139,13 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
break;
case TO_SPR(9, 0): /* PICMR */
env->picmr = rb;
+ qemu_mutex_lock_iothread();
+ if (env->picsr & env->picmr) {
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ } else {
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+ qemu_mutex_unlock_iothread();
break;
case TO_SPR(9, 2): /* PICSR */
env->picsr &= ~rb;
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 10/11] hw/openrisc: virt: pass random seed to fdt
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-03 21:28 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Jason A. Donenfeld, Openrisc
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.
Cc: Stafford Horne <shorne@gmail.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/virt.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
index f1d1293eeb..a301d0d769 100644
--- a/hw/openrisc/virt.c
+++ b/hw/openrisc/virt.c
@@ -8,6 +8,7 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
+#include "qemu/guest-random.h"
#include "qapi/error.h"
#include "cpu.h"
#include "exec/address-spaces.h"
@@ -130,6 +131,7 @@ static void openrisc_create_fdt(OR1KVirtState *state,
void *fdt;
int cpu;
char *nodename;
+ uint8_t rng_seed[32];
fdt = state->fdt = create_device_tree(&state->fdt_size);
if (!fdt) {
@@ -186,6 +188,10 @@ static void openrisc_create_fdt(OR1KVirtState *state,
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
+ /* Pass seed to RNG. */
+ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
+ qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
+
/* Create aliases node for use by devices. */
qemu_fdt_add_subnode(fdt, "/aliases");
}
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 10/11] hw/openrisc: virt: pass random seed to fdt
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Jason A. Donenfeld, Stafford Horne
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.
Cc: Stafford Horne <shorne@gmail.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/virt.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/openrisc/virt.c b/hw/openrisc/virt.c
index f1d1293eeb..a301d0d769 100644
--- a/hw/openrisc/virt.c
+++ b/hw/openrisc/virt.c
@@ -8,6 +8,7 @@
#include "qemu/osdep.h"
#include "qemu/error-report.h"
+#include "qemu/guest-random.h"
#include "qapi/error.h"
#include "cpu.h"
#include "exec/address-spaces.h"
@@ -130,6 +131,7 @@ static void openrisc_create_fdt(OR1KVirtState *state,
void *fdt;
int cpu;
char *nodename;
+ uint8_t rng_seed[32];
fdt = state->fdt = create_device_tree(&state->fdt_size);
if (!fdt) {
@@ -186,6 +188,10 @@ static void openrisc_create_fdt(OR1KVirtState *state,
qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
}
+ /* Pass seed to RNG. */
+ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
+ qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
+
/* Create aliases node for use by devices. */
qemu_fdt_add_subnode(fdt, "/aliases");
}
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 11/11] docs/system: openrisc: Add OpenRISC documentation
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-03 21:28 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
docs/system/openrisc/cpu-features.rst | 15 ++++++
docs/system/openrisc/emulation.rst | 17 +++++++
docs/system/openrisc/or1k-sim.rst | 43 ++++++++++++++++
docs/system/openrisc/virt.rst | 50 +++++++++++++++++++
docs/system/target-openrisc.rst | 72 +++++++++++++++++++++++++++
docs/system/targets.rst | 1 +
6 files changed, 198 insertions(+)
create mode 100644 docs/system/openrisc/cpu-features.rst
create mode 100644 docs/system/openrisc/emulation.rst
create mode 100644 docs/system/openrisc/or1k-sim.rst
create mode 100644 docs/system/openrisc/virt.rst
create mode 100644 docs/system/target-openrisc.rst
diff --git a/docs/system/openrisc/cpu-features.rst b/docs/system/openrisc/cpu-features.rst
new file mode 100644
index 0000000000..aeb65e22ff
--- /dev/null
+++ b/docs/system/openrisc/cpu-features.rst
@@ -0,0 +1,15 @@
+CPU Features
+============
+
+The QEMU emulation of the OpenRISC architecture provides following built in
+features.
+
+- Shadow GPRs
+- MMU TLB with 128 entries, 1 way
+- Power Management (PM)
+- Programmable Interrupt Controller (PIC)
+- Tick Timer
+
+These features are on by default and the presence can be confirmed by checking
+the contents of the Unit Presence Register (``UPR``) and CPU Configuration
+Register (``CPUCFGR``).
diff --git a/docs/system/openrisc/emulation.rst b/docs/system/openrisc/emulation.rst
new file mode 100644
index 0000000000..0af898ab20
--- /dev/null
+++ b/docs/system/openrisc/emulation.rst
@@ -0,0 +1,17 @@
+OpenRISC 1000 CPU architecture support
+======================================
+
+QEMU's TCG emulation includes support for the OpenRISC or1200 implementation of
+the OpenRISC 1000 cpu architecture.
+
+The or1200 cpu also has support for the following instruction subsets:
+
+- ORBIS32 (OpenRISC Basic Instruction Set)
+- ORFPX32 (OpenRISC Floating-Point eXtension)
+
+In addition to the instruction subsets the QEMU TCG emulation also has support
+for most Class II (optional) instructions.
+
+For information on all OpenRISC instructions please refer to the latest
+architecture manual available on the OpenRISC website in the
+`OpenRISC Architecture <https://openrisc.io/architecture>`_ section.
diff --git a/docs/system/openrisc/or1k-sim.rst b/docs/system/openrisc/or1k-sim.rst
new file mode 100644
index 0000000000..ef10439737
--- /dev/null
+++ b/docs/system/openrisc/or1k-sim.rst
@@ -0,0 +1,43 @@
+Or1ksim board
+=============
+
+The QEMU Or1ksim machine emulates the standard OpenRISC board simulator which is
+also the standard SoC configuration.
+
+Supported devices
+-----------------
+
+ * 16550A UART
+ * ETHOC Ethernet controller
+ * SMP (OpenRISC multicore using ompic)
+
+Boot options
+------------
+
+The Or1ksim machine can be started using the ``-kernel`` and ``-initrd`` options
+to load a Linux kernel and optional disk image.
+
+.. code-block:: bash
+
+ $ qemu-system-or1k -cpu or1220 -M or1k-sim -nographic \
+ -kernel vmlinux \
+ -initrd initramfs.cpio.gz \
+ -m 128
+
+Linux guest kernel configuration
+""""""""""""""""""""""""""""""""
+
+The 'or1ksim_defconfig' for Linux openrisc kernels includes the right
+drivers for the or1ksim machine. If you would like to run an SMP system
+choose the 'simple_smp_defconfig' config.
+
+Hardware configuration information
+""""""""""""""""""""""""""""""""""
+
+The ``or1k-sim`` board automatically generates a device tree blob ("dtb")
+which it passes to the guest. This provides information about the
+addresses, interrupt lines and other configuration of the various devices
+in the system.
+
+The location of the DTB will be passed in register ``r3`` to the guest operating
+system.
diff --git a/docs/system/openrisc/virt.rst b/docs/system/openrisc/virt.rst
new file mode 100644
index 0000000000..2fe61ac942
--- /dev/null
+++ b/docs/system/openrisc/virt.rst
@@ -0,0 +1,50 @@
+'virt' generic virtual platform
+===============================
+
+The ``virt`` board is a platform which does not correspond to any
+real hardware; it is designed for use in virtual machines.
+It is the recommended board type if you simply want to run
+a guest such as Linux and do not care about reproducing the
+idiosyncrasies and limitations of a particular bit of real-world
+hardware.
+
+Supported devices
+-----------------
+
+ * PCI/PCIe devices
+ * 8 virtio-mmio transport devices
+ * 16550A UART
+ * Goldfish RTC
+ * SiFive Test device for poweroff and reboot
+ * SMP (OpenRISC multicore using ompic)
+
+Boot options
+------------
+
+The virt machine can be started using the ``-kernel`` and ``-initrd`` options
+to load a Linux kernel and optional disk image. For example:
+
+.. code-block:: bash
+
+ $ qemu-system-or1k -cpu or1220 -M or1k-sim -nographic \
+ -device virtio-net-device,netdev=user -netdev user,id=user,net=10.9.0.1/24,host=10.9.0.100 \
+ -device virtio-blk-device,drive=d0 -drive file=virt.qcow2,id=d0,if=none,format=qcow2 \
+ -kernel vmlinux \
+ -initrd initramfs.cpio.gz \
+ -m 128
+
+Linux guest kernel configuration
+""""""""""""""""""""""""""""""""
+
+The 'virt_defconfig' for Linux openrisc kernels includes the right drivers for
+the ``virt`` machine.
+
+Hardware configuration information
+""""""""""""""""""""""""""""""""""
+
+The ``virt`` board automatically generates a device tree blob ("dtb") which it
+passes to the guest. This provides information about the addresses, interrupt
+lines and other configuration of the various devices in the system.
+
+The location of the DTB will be passed in register ``r3`` to the guest operating
+system.
diff --git a/docs/system/target-openrisc.rst b/docs/system/target-openrisc.rst
new file mode 100644
index 0000000000..d22971a953
--- /dev/null
+++ b/docs/system/target-openrisc.rst
@@ -0,0 +1,72 @@
+.. _OpenRISC-System-emulator:
+
+OpenRISC System emulator
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+QEMU can emulate 32-bit OpenRISC CPUs using the ``qemu-system-or1k`` executable.
+
+OpenRISC CPUs are generally built into "system-on-chip" (SoC) designs that run
+on FPGAs. These SoCs are based on the same core architecture as the or1ksim
+(the original OpenRISC instruction level simulator) which QEMU supports. For
+this reason QEMU does not need to support many different boards to support the
+OpenRISC hardware ecosystem.
+
+The OpenRISC CPU supported by QEMU is the ``or1200``, it supports an MMU and can
+run linux.
+
+Choosing a board model
+======================
+
+For QEMU's OpenRISC system emulation, you must specify which board model you
+want to use with the ``-M`` or ``--machine`` option; the default machine is
+``or1k-sim``.
+
+If you intend to boot Linux, it is possible to have a single kernel image that
+will boot on any of the QEMU machines. To do this one would compile all required
+drivers into the kernel. This is possible because QEMU will create a device tree
+structure that describes the QEMU machine and pass a pointer to the structure to
+the kernel. The kernel can then use this to configure itself for the machine.
+
+However, typically users will have specific firmware images for a specific machine.
+
+If you already have a system image or a kernel that works on hardware and you
+want to boot with QEMU, check whether QEMU lists that machine in its ``-machine
+help`` output. If it is listed, then you can probably use that board model. If
+it is not listed, then unfortunately your image will almost certainly not boot
+on QEMU. (You might be able to extract the filesystem and use that with a
+different kernel which boots on a system that QEMU does emulate.)
+
+If you don't care about reproducing the idiosyncrasies of a particular
+bit of hardware, such as small amount of RAM, no PCI or other hard disk, etc.,
+and just want to run Linux, the best option is to use the ``virt`` board. This
+is a platform which doesn't correspond to any real hardware and is designed for
+use in virtual machines. You'll need to compile Linux with a suitable
+configuration for running on the ``virt`` board. ``virt`` supports PCI, virtio
+and large amounts of RAM.
+
+Board-specific documentation
+============================
+
+..
+ This table of contents should be kept sorted alphabetically
+ by the title text of each file, which isn't the same ordering
+ as an alphabetical sort by filename.
+
+.. toctree::
+ :maxdepth: 1
+
+ openrisc/or1k-sim
+ openrisc/virt
+
+Emulated CPU architecture support
+=================================
+
+.. toctree::
+ openrisc/emulation
+
+OpenRISC CPU features
+=====================
+
+.. toctree::
+ openrisc/cpu-features
+
diff --git a/docs/system/targets.rst b/docs/system/targets.rst
index 9dcd95dd84..224fadae71 100644
--- a/docs/system/targets.rst
+++ b/docs/system/targets.rst
@@ -21,6 +21,7 @@ Contents:
target-m68k
target-mips
target-ppc
+ target-openrisc
target-riscv
target-rx
target-s390x
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v2 11/11] docs/system: openrisc: Add OpenRISC documentation
@ 2022-07-03 21:28 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-03 21:28 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Stafford Horne
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
docs/system/openrisc/cpu-features.rst | 15 ++++++
docs/system/openrisc/emulation.rst | 17 +++++++
docs/system/openrisc/or1k-sim.rst | 43 ++++++++++++++++
docs/system/openrisc/virt.rst | 50 +++++++++++++++++++
docs/system/target-openrisc.rst | 72 +++++++++++++++++++++++++++
docs/system/targets.rst | 1 +
6 files changed, 198 insertions(+)
create mode 100644 docs/system/openrisc/cpu-features.rst
create mode 100644 docs/system/openrisc/emulation.rst
create mode 100644 docs/system/openrisc/or1k-sim.rst
create mode 100644 docs/system/openrisc/virt.rst
create mode 100644 docs/system/target-openrisc.rst
diff --git a/docs/system/openrisc/cpu-features.rst b/docs/system/openrisc/cpu-features.rst
new file mode 100644
index 0000000000..aeb65e22ff
--- /dev/null
+++ b/docs/system/openrisc/cpu-features.rst
@@ -0,0 +1,15 @@
+CPU Features
+============
+
+The QEMU emulation of the OpenRISC architecture provides following built in
+features.
+
+- Shadow GPRs
+- MMU TLB with 128 entries, 1 way
+- Power Management (PM)
+- Programmable Interrupt Controller (PIC)
+- Tick Timer
+
+These features are on by default and the presence can be confirmed by checking
+the contents of the Unit Presence Register (``UPR``) and CPU Configuration
+Register (``CPUCFGR``).
diff --git a/docs/system/openrisc/emulation.rst b/docs/system/openrisc/emulation.rst
new file mode 100644
index 0000000000..0af898ab20
--- /dev/null
+++ b/docs/system/openrisc/emulation.rst
@@ -0,0 +1,17 @@
+OpenRISC 1000 CPU architecture support
+======================================
+
+QEMU's TCG emulation includes support for the OpenRISC or1200 implementation of
+the OpenRISC 1000 cpu architecture.
+
+The or1200 cpu also has support for the following instruction subsets:
+
+- ORBIS32 (OpenRISC Basic Instruction Set)
+- ORFPX32 (OpenRISC Floating-Point eXtension)
+
+In addition to the instruction subsets the QEMU TCG emulation also has support
+for most Class II (optional) instructions.
+
+For information on all OpenRISC instructions please refer to the latest
+architecture manual available on the OpenRISC website in the
+`OpenRISC Architecture <https://openrisc.io/architecture>`_ section.
diff --git a/docs/system/openrisc/or1k-sim.rst b/docs/system/openrisc/or1k-sim.rst
new file mode 100644
index 0000000000..ef10439737
--- /dev/null
+++ b/docs/system/openrisc/or1k-sim.rst
@@ -0,0 +1,43 @@
+Or1ksim board
+=============
+
+The QEMU Or1ksim machine emulates the standard OpenRISC board simulator which is
+also the standard SoC configuration.
+
+Supported devices
+-----------------
+
+ * 16550A UART
+ * ETHOC Ethernet controller
+ * SMP (OpenRISC multicore using ompic)
+
+Boot options
+------------
+
+The Or1ksim machine can be started using the ``-kernel`` and ``-initrd`` options
+to load a Linux kernel and optional disk image.
+
+.. code-block:: bash
+
+ $ qemu-system-or1k -cpu or1220 -M or1k-sim -nographic \
+ -kernel vmlinux \
+ -initrd initramfs.cpio.gz \
+ -m 128
+
+Linux guest kernel configuration
+""""""""""""""""""""""""""""""""
+
+The 'or1ksim_defconfig' for Linux openrisc kernels includes the right
+drivers for the or1ksim machine. If you would like to run an SMP system
+choose the 'simple_smp_defconfig' config.
+
+Hardware configuration information
+""""""""""""""""""""""""""""""""""
+
+The ``or1k-sim`` board automatically generates a device tree blob ("dtb")
+which it passes to the guest. This provides information about the
+addresses, interrupt lines and other configuration of the various devices
+in the system.
+
+The location of the DTB will be passed in register ``r3`` to the guest operating
+system.
diff --git a/docs/system/openrisc/virt.rst b/docs/system/openrisc/virt.rst
new file mode 100644
index 0000000000..2fe61ac942
--- /dev/null
+++ b/docs/system/openrisc/virt.rst
@@ -0,0 +1,50 @@
+'virt' generic virtual platform
+===============================
+
+The ``virt`` board is a platform which does not correspond to any
+real hardware; it is designed for use in virtual machines.
+It is the recommended board type if you simply want to run
+a guest such as Linux and do not care about reproducing the
+idiosyncrasies and limitations of a particular bit of real-world
+hardware.
+
+Supported devices
+-----------------
+
+ * PCI/PCIe devices
+ * 8 virtio-mmio transport devices
+ * 16550A UART
+ * Goldfish RTC
+ * SiFive Test device for poweroff and reboot
+ * SMP (OpenRISC multicore using ompic)
+
+Boot options
+------------
+
+The virt machine can be started using the ``-kernel`` and ``-initrd`` options
+to load a Linux kernel and optional disk image. For example:
+
+.. code-block:: bash
+
+ $ qemu-system-or1k -cpu or1220 -M or1k-sim -nographic \
+ -device virtio-net-device,netdev=user -netdev user,id=user,net=10.9.0.1/24,host=10.9.0.100 \
+ -device virtio-blk-device,drive=d0 -drive file=virt.qcow2,id=d0,if=none,format=qcow2 \
+ -kernel vmlinux \
+ -initrd initramfs.cpio.gz \
+ -m 128
+
+Linux guest kernel configuration
+""""""""""""""""""""""""""""""""
+
+The 'virt_defconfig' for Linux openrisc kernels includes the right drivers for
+the ``virt`` machine.
+
+Hardware configuration information
+""""""""""""""""""""""""""""""""""
+
+The ``virt`` board automatically generates a device tree blob ("dtb") which it
+passes to the guest. This provides information about the addresses, interrupt
+lines and other configuration of the various devices in the system.
+
+The location of the DTB will be passed in register ``r3`` to the guest operating
+system.
diff --git a/docs/system/target-openrisc.rst b/docs/system/target-openrisc.rst
new file mode 100644
index 0000000000..d22971a953
--- /dev/null
+++ b/docs/system/target-openrisc.rst
@@ -0,0 +1,72 @@
+.. _OpenRISC-System-emulator:
+
+OpenRISC System emulator
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+QEMU can emulate 32-bit OpenRISC CPUs using the ``qemu-system-or1k`` executable.
+
+OpenRISC CPUs are generally built into "system-on-chip" (SoC) designs that run
+on FPGAs. These SoCs are based on the same core architecture as the or1ksim
+(the original OpenRISC instruction level simulator) which QEMU supports. For
+this reason QEMU does not need to support many different boards to support the
+OpenRISC hardware ecosystem.
+
+The OpenRISC CPU supported by QEMU is the ``or1200``, it supports an MMU and can
+run linux.
+
+Choosing a board model
+======================
+
+For QEMU's OpenRISC system emulation, you must specify which board model you
+want to use with the ``-M`` or ``--machine`` option; the default machine is
+``or1k-sim``.
+
+If you intend to boot Linux, it is possible to have a single kernel image that
+will boot on any of the QEMU machines. To do this one would compile all required
+drivers into the kernel. This is possible because QEMU will create a device tree
+structure that describes the QEMU machine and pass a pointer to the structure to
+the kernel. The kernel can then use this to configure itself for the machine.
+
+However, typically users will have specific firmware images for a specific machine.
+
+If you already have a system image or a kernel that works on hardware and you
+want to boot with QEMU, check whether QEMU lists that machine in its ``-machine
+help`` output. If it is listed, then you can probably use that board model. If
+it is not listed, then unfortunately your image will almost certainly not boot
+on QEMU. (You might be able to extract the filesystem and use that with a
+different kernel which boots on a system that QEMU does emulate.)
+
+If you don't care about reproducing the idiosyncrasies of a particular
+bit of hardware, such as small amount of RAM, no PCI or other hard disk, etc.,
+and just want to run Linux, the best option is to use the ``virt`` board. This
+is a platform which doesn't correspond to any real hardware and is designed for
+use in virtual machines. You'll need to compile Linux with a suitable
+configuration for running on the ``virt`` board. ``virt`` supports PCI, virtio
+and large amounts of RAM.
+
+Board-specific documentation
+============================
+
+..
+ This table of contents should be kept sorted alphabetically
+ by the title text of each file, which isn't the same ordering
+ as an alphabetical sort by filename.
+
+.. toctree::
+ :maxdepth: 1
+
+ openrisc/or1k-sim
+ openrisc/virt
+
+Emulated CPU architecture support
+=================================
+
+.. toctree::
+ openrisc/emulation
+
+OpenRISC CPU features
+=====================
+
+.. toctree::
+ openrisc/cpu-features
+
diff --git a/docs/system/targets.rst b/docs/system/targets.rst
index 9dcd95dd84..224fadae71 100644
--- a/docs/system/targets.rst
+++ b/docs/system/targets.rst
@@ -21,6 +21,7 @@ Contents:
target-m68k
target-mips
target-ppc
+ target-openrisc
target-riscv
target-rx
target-s390x
--
2.36.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-04 2:50 ` Anup Patel
-1 siblings, 0 replies; 53+ messages in thread
From: Anup Patel @ 2022-07-04 2:50 UTC (permalink / raw)
To: Stafford Horne
Cc: QEMU Development, Openrisc, Laurent Vivier, Anup Patel,
Alistair Francis, open list:Goldfish RTC
On Mon, Jul 4, 2022 at 2:59 AM Stafford Horne <shorne@gmail.com> wrote:
>
> Add an endianness property to allow configuring the RTC as either
> native, little or big endian.
>
> Cc: Laurent Vivier <lvivier@redhat.com>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> hw/rtc/goldfish_rtc.c | 46 ++++++++++++++++++++++++++++-------
> include/hw/rtc/goldfish_rtc.h | 2 ++
> 2 files changed, 39 insertions(+), 9 deletions(-)
>
> diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c
> index 35e493be31..24f6587086 100644
> --- a/hw/rtc/goldfish_rtc.c
> +++ b/hw/rtc/goldfish_rtc.c
> @@ -216,14 +216,34 @@ static int goldfish_rtc_post_load(void *opaque, int version_id)
> return 0;
> }
>
> -static const MemoryRegionOps goldfish_rtc_ops = {
> - .read = goldfish_rtc_read,
> - .write = goldfish_rtc_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> - .valid = {
> - .min_access_size = 4,
> - .max_access_size = 4
> - }
> +static const MemoryRegionOps goldfish_rtc_ops[3] = {
> + [DEVICE_NATIVE_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> + [DEVICE_LITTLE_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> + [DEVICE_BIG_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> };
>
> static const VMStateDescription goldfish_rtc_vmstate = {
> @@ -265,7 +285,8 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
> SysBusDevice *dev = SYS_BUS_DEVICE(d);
> GoldfishRTCState *s = GOLDFISH_RTC(d);
>
> - memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_rtc_ops, s,
> + memory_region_init_io(&s->iomem, OBJECT(s),
> + &goldfish_rtc_ops[s->endianness], s,
> "goldfish_rtc", 0x24);
> sysbus_init_mmio(dev, &s->iomem);
>
> @@ -274,10 +295,17 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
> s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s);
> }
>
> +static Property goldfish_rtc_properties[] = {
> + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
> + DEVICE_NATIVE_ENDIAN),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> static void goldfish_rtc_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> + device_class_set_props(dc, goldfish_rtc_properties);
> dc->realize = goldfish_rtc_realize;
> dc->reset = goldfish_rtc_reset;
> dc->vmsd = &goldfish_rtc_vmstate;
> diff --git a/include/hw/rtc/goldfish_rtc.h b/include/hw/rtc/goldfish_rtc.h
> index 79ca7daf5d..8e1aeb85e3 100644
> --- a/include/hw/rtc/goldfish_rtc.h
> +++ b/include/hw/rtc/goldfish_rtc.h
> @@ -42,6 +42,8 @@ struct GoldfishRTCState {
> uint32_t irq_pending;
> uint32_t irq_enabled;
> uint32_t time_high;
> +
> + uint8_t endianness;
> };
>
> #endif
> --
> 2.36.1
>
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
@ 2022-07-04 2:50 ` Anup Patel
0 siblings, 0 replies; 53+ messages in thread
From: Anup Patel @ 2022-07-04 2:50 UTC (permalink / raw)
To: Stafford Horne
Cc: Laurent Vivier, open list:Goldfish RTC, Anup Patel,
QEMU Development, Openrisc, Alistair Francis
On Mon, Jul 4, 2022 at 2:59 AM Stafford Horne <shorne@gmail.com> wrote:
>
> Add an endianness property to allow configuring the RTC as either
> native, little or big endian.
>
> Cc: Laurent Vivier <lvivier@redhat.com>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> hw/rtc/goldfish_rtc.c | 46 ++++++++++++++++++++++++++++-------
> include/hw/rtc/goldfish_rtc.h | 2 ++
> 2 files changed, 39 insertions(+), 9 deletions(-)
>
> diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c
> index 35e493be31..24f6587086 100644
> --- a/hw/rtc/goldfish_rtc.c
> +++ b/hw/rtc/goldfish_rtc.c
> @@ -216,14 +216,34 @@ static int goldfish_rtc_post_load(void *opaque, int version_id)
> return 0;
> }
>
> -static const MemoryRegionOps goldfish_rtc_ops = {
> - .read = goldfish_rtc_read,
> - .write = goldfish_rtc_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> - .valid = {
> - .min_access_size = 4,
> - .max_access_size = 4
> - }
> +static const MemoryRegionOps goldfish_rtc_ops[3] = {
> + [DEVICE_NATIVE_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> + [DEVICE_LITTLE_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> + [DEVICE_BIG_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> };
>
> static const VMStateDescription goldfish_rtc_vmstate = {
> @@ -265,7 +285,8 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
> SysBusDevice *dev = SYS_BUS_DEVICE(d);
> GoldfishRTCState *s = GOLDFISH_RTC(d);
>
> - memory_region_init_io(&s->iomem, OBJECT(s), &goldfish_rtc_ops, s,
> + memory_region_init_io(&s->iomem, OBJECT(s),
> + &goldfish_rtc_ops[s->endianness], s,
> "goldfish_rtc", 0x24);
> sysbus_init_mmio(dev, &s->iomem);
>
> @@ -274,10 +295,17 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp)
> s->timer = timer_new_ns(rtc_clock, goldfish_rtc_interrupt, s);
> }
>
> +static Property goldfish_rtc_properties[] = {
> + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
> + DEVICE_NATIVE_ENDIAN),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> static void goldfish_rtc_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> + device_class_set_props(dc, goldfish_rtc_properties);
> dc->realize = goldfish_rtc_realize;
> dc->reset = goldfish_rtc_reset;
> dc->vmsd = &goldfish_rtc_vmstate;
> diff --git a/include/hw/rtc/goldfish_rtc.h b/include/hw/rtc/goldfish_rtc.h
> index 79ca7daf5d..8e1aeb85e3 100644
> --- a/include/hw/rtc/goldfish_rtc.h
> +++ b/include/hw/rtc/goldfish_rtc.h
> @@ -42,6 +42,8 @@ struct GoldfishRTCState {
> uint32_t irq_pending;
> uint32_t irq_enabled;
> uint32_t time_high;
> +
> + uint8_t endianness;
> };
>
> #endif
> --
> 2.36.1
>
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-04 9:59 ` Richard Henderson
-1 siblings, 0 replies; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 9:59 UTC (permalink / raw)
To: Stafford Horne, QEMU Development
Cc: Laurent Vivier, open list:Goldfish RTC, Anup Patel, Openrisc,
Alistair Francis
On 7/4/22 02:58, Stafford Horne wrote:
> -static const MemoryRegionOps goldfish_rtc_ops = {
> - .read = goldfish_rtc_read,
> - .write = goldfish_rtc_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> - .valid = {
> - .min_access_size = 4,
> - .max_access_size = 4
> - }
> +static const MemoryRegionOps goldfish_rtc_ops[3] = {
> + [DEVICE_NATIVE_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> + [DEVICE_LITTLE_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> + [DEVICE_BIG_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> };
You don't need 3 copies, only big and little.
> +static Property goldfish_rtc_properties[] = {
> + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
> + DEVICE_NATIVE_ENDIAN),
> + DEFINE_PROP_END_OF_LIST(),
> +};
... and I think the clear desire for default is little-endian. I would make the property
be bool, and add a comment that this is only for m68k compatibility, so don't use it in
new code.
r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
@ 2022-07-04 9:59 ` Richard Henderson
0 siblings, 0 replies; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 9:59 UTC (permalink / raw)
To: Stafford Horne, QEMU Development
Cc: Openrisc, Laurent Vivier, Anup Patel, Alistair Francis,
open list:Goldfish RTC
On 7/4/22 02:58, Stafford Horne wrote:
> -static const MemoryRegionOps goldfish_rtc_ops = {
> - .read = goldfish_rtc_read,
> - .write = goldfish_rtc_write,
> - .endianness = DEVICE_NATIVE_ENDIAN,
> - .valid = {
> - .min_access_size = 4,
> - .max_access_size = 4
> - }
> +static const MemoryRegionOps goldfish_rtc_ops[3] = {
> + [DEVICE_NATIVE_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> + [DEVICE_LITTLE_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> + [DEVICE_BIG_ENDIAN] = {
> + .read = goldfish_rtc_read,
> + .write = goldfish_rtc_write,
> + .endianness = DEVICE_BIG_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4
> + }
> + },
> };
You don't need 3 copies, only big and little.
> +static Property goldfish_rtc_properties[] = {
> + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
> + DEVICE_NATIVE_ENDIAN),
> + DEFINE_PROP_END_OF_LIST(),
> +};
... and I think the clear desire for default is little-endian. I would make the property
be bool, and add a comment that this is only for m68k compatibility, so don't use it in
new code.
r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 02/11] target/openrisc: Fix memory reading in debugger
2022-07-03 21:28 ` Stafford Horne
(?)
@ 2022-07-04 10:01 ` Richard Henderson
-1 siblings, 0 replies; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 10:01 UTC (permalink / raw)
To: Stafford Horne, QEMU Development; +Cc: Openrisc
On 7/4/22 02:58, Stafford Horne wrote:
> In commit f0655423ca ("target/openrisc: Reorg tlb lookup") data and
> instruction TLB reads were combined. This, broke debugger reads where
> we first tried to map using the data tlb then fall back to the
> instruction tlb.
>
> This patch replicates this logic by first requesting a PAGE_READ
> protection mapping then falling back to PAGE_EXEC.
>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 06/11] hw/openrisc: Initialize timer time at startup
2022-07-03 21:28 ` Stafford Horne
(?)
@ 2022-07-04 10:03 ` Richard Henderson
2022-07-04 20:32 ` Stafford Horne
-1 siblings, 1 reply; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 10:03 UTC (permalink / raw)
To: Stafford Horne, QEMU Development; +Cc: Openrisc
On 7/4/22 02:58, Stafford Horne wrote:
> The last_clk time was initialized at zero, this means when we calculate
> the first delta we will calculate 0 vs current time which could cause
> unnecessary hops.
>
> Initialize last_clk to the qemu clock on initialization.
>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> hw/openrisc/cputimer.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
> index 93268815d8..4dbba3a3d4 100644
> --- a/hw/openrisc/cputimer.c
> +++ b/hw/openrisc/cputimer.c
> @@ -140,6 +140,7 @@ void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
>
> if (or1k_timer == NULL) {
> or1k_timer = g_new0(OR1KTimerState, 1);
> + or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);
> }
> }
Init doesn't seem right. Should be in reset?
r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 07/11] target/openrisc: Add interrupted CPU to log
2022-07-03 21:28 ` Stafford Horne
(?)
@ 2022-07-04 10:04 ` Richard Henderson
2022-07-04 20:26 ` Stafford Horne
-1 siblings, 1 reply; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 10:04 UTC (permalink / raw)
To: Stafford Horne, QEMU Development; +Cc: Openrisc
On 7/4/22 02:58, Stafford Horne wrote:
> When we are tracing it's helpful to know which CPU's are getting
> interrupted, att that detail to the log line.
"at".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> target/openrisc/interrupt.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
> index e5724f5371..c31c6f12c4 100644
> --- a/target/openrisc/interrupt.c
> +++ b/target/openrisc/interrupt.c
> @@ -83,7 +83,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
> [EXCP_TRAP] = "TRAP",
> };
>
> - qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]);
> + qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n",
> + cs->cpu_index,
> + int_name[exception]);
>
> hwaddr vect_pc = exception << 8;
> if (env->cpucfgr & CPUCFGR_EVBARP) {
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 08/11] target/openrisc: Enable MTTCG
2022-07-03 21:28 ` Stafford Horne
(?)
@ 2022-07-04 10:07 ` Richard Henderson
2022-07-04 20:31 ` Stafford Horne
-1 siblings, 1 reply; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 10:07 UTC (permalink / raw)
To: Stafford Horne, QEMU Development; +Cc: Openrisc
On 7/4/22 02:58, Stafford Horne wrote:
> case TO_SPR(10, 1): /* TTCR */
> - cpu_openrisc_count_update(cpu);
> + if (cpu_openrisc_timer_has_advanced(cpu)) {
> + qemu_mutex_lock_iothread();
> + cpu_openrisc_count_update(cpu);
> + qemu_mutex_unlock_iothread();
> + }
Lock around the whole if, I think. Otherwise looks good.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
2022-07-04 9:59 ` Richard Henderson
@ 2022-07-04 10:16 ` Laurent Vivier
-1 siblings, 0 replies; 53+ messages in thread
From: Laurent Vivier @ 2022-07-04 10:16 UTC (permalink / raw)
To: Richard Henderson, Stafford Horne, QEMU Development
Cc: Openrisc, Anup Patel, Alistair Francis, open list:Goldfish RTC
On 04/07/2022 11:59, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
>> -static const MemoryRegionOps goldfish_rtc_ops = {
>> - .read = goldfish_rtc_read,
>> - .write = goldfish_rtc_write,
>> - .endianness = DEVICE_NATIVE_ENDIAN,
>> - .valid = {
>> - .min_access_size = 4,
>> - .max_access_size = 4
>> - }
>> +static const MemoryRegionOps goldfish_rtc_ops[3] = {
>> + [DEVICE_NATIVE_ENDIAN] = {
>> + .read = goldfish_rtc_read,
>> + .write = goldfish_rtc_write,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> + .valid = {
>> + .min_access_size = 4,
>> + .max_access_size = 4
>> + }
>> + },
>> + [DEVICE_LITTLE_ENDIAN] = {
>> + .read = goldfish_rtc_read,
>> + .write = goldfish_rtc_write,
>> + .endianness = DEVICE_LITTLE_ENDIAN,
>> + .valid = {
>> + .min_access_size = 4,
>> + .max_access_size = 4
>> + }
>> + },
>> + [DEVICE_BIG_ENDIAN] = {
>> + .read = goldfish_rtc_read,
>> + .write = goldfish_rtc_write,
>> + .endianness = DEVICE_BIG_ENDIAN,
>> + .valid = {
>> + .min_access_size = 4,
>> + .max_access_size = 4
>> + }
>> + },
>> };
>
> You don't need 3 copies, only big and little.
>
>> +static Property goldfish_rtc_properties[] = {
>> + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
>> + DEVICE_NATIVE_ENDIAN),
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>
> ... and I think the clear desire for default is little-endian. I would make the property
> be bool, and add a comment that this is only for m68k compatibility, so don't use it in
> new code.
m68k doesn't really need this.
kernel with the m68k virt machine and goldfish device supports "native" mode so I think
it's not needed to add another layer of complexity for it.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
@ 2022-07-04 10:16 ` Laurent Vivier
0 siblings, 0 replies; 53+ messages in thread
From: Laurent Vivier @ 2022-07-04 10:16 UTC (permalink / raw)
To: Richard Henderson, Stafford Horne, QEMU Development
Cc: open list:Goldfish RTC, Anup Patel, Openrisc, Alistair Francis
On 04/07/2022 11:59, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
>> -static const MemoryRegionOps goldfish_rtc_ops = {
>> - .read = goldfish_rtc_read,
>> - .write = goldfish_rtc_write,
>> - .endianness = DEVICE_NATIVE_ENDIAN,
>> - .valid = {
>> - .min_access_size = 4,
>> - .max_access_size = 4
>> - }
>> +static const MemoryRegionOps goldfish_rtc_ops[3] = {
>> + [DEVICE_NATIVE_ENDIAN] = {
>> + .read = goldfish_rtc_read,
>> + .write = goldfish_rtc_write,
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> + .valid = {
>> + .min_access_size = 4,
>> + .max_access_size = 4
>> + }
>> + },
>> + [DEVICE_LITTLE_ENDIAN] = {
>> + .read = goldfish_rtc_read,
>> + .write = goldfish_rtc_write,
>> + .endianness = DEVICE_LITTLE_ENDIAN,
>> + .valid = {
>> + .min_access_size = 4,
>> + .max_access_size = 4
>> + }
>> + },
>> + [DEVICE_BIG_ENDIAN] = {
>> + .read = goldfish_rtc_read,
>> + .write = goldfish_rtc_write,
>> + .endianness = DEVICE_BIG_ENDIAN,
>> + .valid = {
>> + .min_access_size = 4,
>> + .max_access_size = 4
>> + }
>> + },
>> };
>
> You don't need 3 copies, only big and little.
>
>> +static Property goldfish_rtc_properties[] = {
>> + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
>> + DEVICE_NATIVE_ENDIAN),
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>
> ... and I think the clear desire for default is little-endian. I would make the property
> be bool, and add a comment that this is only for m68k compatibility, so don't use it in
> new code.
m68k doesn't really need this.
kernel with the m68k virt machine and goldfish device supports "native" mode so I think
it's not needed to add another layer of complexity for it.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 09/11] target/openrisc: Interrupt handling fixes
2022-07-03 21:28 ` Stafford Horne
(?)
@ 2022-07-04 10:20 ` Richard Henderson
-1 siblings, 0 replies; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 10:20 UTC (permalink / raw)
To: Stafford Horne, QEMU Development; +Cc: Openrisc
On 7/4/22 02:58, Stafford Horne wrote:
> When running SMP systems we sometimes were seeing lockups where
> IPI interrupts were being raised by never handled.
>
> This looks to be caused by 2 issues in the openrisc interrupt handling
> logic.
>
> 1. After clearing an interrupt the openrisc_cpu_set_irq handler will
> always clear PICSR. This is not correct as masked interrupts
> should still be visible in PICSR.
> 2. After setting PICMR (mask register) and exposed interrupts should
> cause an interrupt to be raised. This was not being done so add it.
>
> This patch fixes both issues.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
2022-07-04 10:16 ` Laurent Vivier
@ 2022-07-04 10:21 ` Richard Henderson
-1 siblings, 0 replies; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 10:21 UTC (permalink / raw)
To: Laurent Vivier, Stafford Horne, QEMU Development
Cc: open list:Goldfish RTC, Anup Patel, Openrisc, Alistair Francis
On 7/4/22 15:46, Laurent Vivier wrote:
> On 04/07/2022 11:59, Richard Henderson wrote:
>> On 7/4/22 02:58, Stafford Horne wrote:
>>> -static const MemoryRegionOps goldfish_rtc_ops = {
>>> - .read = goldfish_rtc_read,
>>> - .write = goldfish_rtc_write,
>>> - .endianness = DEVICE_NATIVE_ENDIAN,
>>> - .valid = {
>>> - .min_access_size = 4,
>>> - .max_access_size = 4
>>> - }
>>> +static const MemoryRegionOps goldfish_rtc_ops[3] = {
>>> + [DEVICE_NATIVE_ENDIAN] = {
>>> + .read = goldfish_rtc_read,
>>> + .write = goldfish_rtc_write,
>>> + .endianness = DEVICE_NATIVE_ENDIAN,
>>> + .valid = {
>>> + .min_access_size = 4,
>>> + .max_access_size = 4
>>> + }
>>> + },
>>> + [DEVICE_LITTLE_ENDIAN] = {
>>> + .read = goldfish_rtc_read,
>>> + .write = goldfish_rtc_write,
>>> + .endianness = DEVICE_LITTLE_ENDIAN,
>>> + .valid = {
>>> + .min_access_size = 4,
>>> + .max_access_size = 4
>>> + }
>>> + },
>>> + [DEVICE_BIG_ENDIAN] = {
>>> + .read = goldfish_rtc_read,
>>> + .write = goldfish_rtc_write,
>>> + .endianness = DEVICE_BIG_ENDIAN,
>>> + .valid = {
>>> + .min_access_size = 4,
>>> + .max_access_size = 4
>>> + }
>>> + },
>>> };
>>
>> You don't need 3 copies, only big and little.
>>
>>> +static Property goldfish_rtc_properties[] = {
>>> + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
>>> + DEVICE_NATIVE_ENDIAN),
>>> + DEFINE_PROP_END_OF_LIST(),
>>> +};
>>
>> ... and I think the clear desire for default is little-endian. I would make the
>> property be bool, and add a comment that this is only for m68k compatibility, so don't
>> use it in new code.
>
> m68k doesn't really need this.
>
> kernel with the m68k virt machine and goldfish device supports "native" mode so I think
> it's not needed to add another layer of complexity for it.
"Another level"? I'm talking about removing "native", and only having "big" and "little",
which is less complexity.
r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
@ 2022-07-04 10:21 ` Richard Henderson
0 siblings, 0 replies; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 10:21 UTC (permalink / raw)
To: Laurent Vivier, Stafford Horne, QEMU Development
Cc: Openrisc, Anup Patel, Alistair Francis, open list:Goldfish RTC
On 7/4/22 15:46, Laurent Vivier wrote:
> On 04/07/2022 11:59, Richard Henderson wrote:
>> On 7/4/22 02:58, Stafford Horne wrote:
>>> -static const MemoryRegionOps goldfish_rtc_ops = {
>>> - .read = goldfish_rtc_read,
>>> - .write = goldfish_rtc_write,
>>> - .endianness = DEVICE_NATIVE_ENDIAN,
>>> - .valid = {
>>> - .min_access_size = 4,
>>> - .max_access_size = 4
>>> - }
>>> +static const MemoryRegionOps goldfish_rtc_ops[3] = {
>>> + [DEVICE_NATIVE_ENDIAN] = {
>>> + .read = goldfish_rtc_read,
>>> + .write = goldfish_rtc_write,
>>> + .endianness = DEVICE_NATIVE_ENDIAN,
>>> + .valid = {
>>> + .min_access_size = 4,
>>> + .max_access_size = 4
>>> + }
>>> + },
>>> + [DEVICE_LITTLE_ENDIAN] = {
>>> + .read = goldfish_rtc_read,
>>> + .write = goldfish_rtc_write,
>>> + .endianness = DEVICE_LITTLE_ENDIAN,
>>> + .valid = {
>>> + .min_access_size = 4,
>>> + .max_access_size = 4
>>> + }
>>> + },
>>> + [DEVICE_BIG_ENDIAN] = {
>>> + .read = goldfish_rtc_read,
>>> + .write = goldfish_rtc_write,
>>> + .endianness = DEVICE_BIG_ENDIAN,
>>> + .valid = {
>>> + .min_access_size = 4,
>>> + .max_access_size = 4
>>> + }
>>> + },
>>> };
>>
>> You don't need 3 copies, only big and little.
>>
>>> +static Property goldfish_rtc_properties[] = {
>>> + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
>>> + DEVICE_NATIVE_ENDIAN),
>>> + DEFINE_PROP_END_OF_LIST(),
>>> +};
>>
>> ... and I think the clear desire for default is little-endian. I would make the
>> property be bool, and add a comment that this is only for m68k compatibility, so don't
>> use it in new code.
>
> m68k doesn't really need this.
>
> kernel with the m68k virt machine and goldfish device supports "native" mode so I think
> it's not needed to add another layer of complexity for it.
"Another level"? I'm talking about removing "native", and only having "big" and "little",
which is less complexity.
r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 10/11] hw/openrisc: virt: pass random seed to fdt
2022-07-03 21:28 ` Stafford Horne
@ 2022-07-04 10:22 ` Richard Henderson
-1 siblings, 0 replies; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 10:22 UTC (permalink / raw)
To: Stafford Horne, QEMU Development; +Cc: Jason A. Donenfeld, Openrisc
On 7/4/22 02:58, Stafford Horne wrote:
> From: "Jason A. Donenfeld" <Jason@zx2c4.com>
>
> If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
> initialize early. Set this using the usual guest random number
> generation function. This is confirmed to successfully initialize the
> RNG on Linux 5.19-rc2.
>
> Cc: Stafford Horne <shorne@gmail.com>
> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
You could remove yourself from cc now that you've signed it. :-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 10/11] hw/openrisc: virt: pass random seed to fdt
@ 2022-07-04 10:22 ` Richard Henderson
0 siblings, 0 replies; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 10:22 UTC (permalink / raw)
To: Stafford Horne, QEMU Development; +Cc: Openrisc, Jason A. Donenfeld
On 7/4/22 02:58, Stafford Horne wrote:
> From: "Jason A. Donenfeld" <Jason@zx2c4.com>
>
> If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
> initialize early. Set this using the usual guest random number
> generation function. This is confirmed to successfully initialize the
> RNG on Linux 5.19-rc2.
>
> Cc: Stafford Horne <shorne@gmail.com>
> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
You could remove yourself from cc now that you've signed it. :-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
2022-07-04 10:21 ` Richard Henderson
@ 2022-07-04 10:23 ` Laurent Vivier
-1 siblings, 0 replies; 53+ messages in thread
From: Laurent Vivier @ 2022-07-04 10:23 UTC (permalink / raw)
To: Richard Henderson, Stafford Horne, QEMU Development
Cc: Openrisc, Anup Patel, Alistair Francis, open list:Goldfish RTC
On 04/07/2022 12:21, Richard Henderson wrote:
> On 7/4/22 15:46, Laurent Vivier wrote:
>> On 04/07/2022 11:59, Richard Henderson wrote:
>>> On 7/4/22 02:58, Stafford Horne wrote:
>>>> -static const MemoryRegionOps goldfish_rtc_ops = {
>>>> - .read = goldfish_rtc_read,
>>>> - .write = goldfish_rtc_write,
>>>> - .endianness = DEVICE_NATIVE_ENDIAN,
>>>> - .valid = {
>>>> - .min_access_size = 4,
>>>> - .max_access_size = 4
>>>> - }
>>>> +static const MemoryRegionOps goldfish_rtc_ops[3] = {
>>>> + [DEVICE_NATIVE_ENDIAN] = {
>>>> + .read = goldfish_rtc_read,
>>>> + .write = goldfish_rtc_write,
>>>> + .endianness = DEVICE_NATIVE_ENDIAN,
>>>> + .valid = {
>>>> + .min_access_size = 4,
>>>> + .max_access_size = 4
>>>> + }
>>>> + },
>>>> + [DEVICE_LITTLE_ENDIAN] = {
>>>> + .read = goldfish_rtc_read,
>>>> + .write = goldfish_rtc_write,
>>>> + .endianness = DEVICE_LITTLE_ENDIAN,
>>>> + .valid = {
>>>> + .min_access_size = 4,
>>>> + .max_access_size = 4
>>>> + }
>>>> + },
>>>> + [DEVICE_BIG_ENDIAN] = {
>>>> + .read = goldfish_rtc_read,
>>>> + .write = goldfish_rtc_write,
>>>> + .endianness = DEVICE_BIG_ENDIAN,
>>>> + .valid = {
>>>> + .min_access_size = 4,
>>>> + .max_access_size = 4
>>>> + }
>>>> + },
>>>> };
>>>
>>> You don't need 3 copies, only big and little.
>>>
>>>> +static Property goldfish_rtc_properties[] = {
>>>> + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
>>>> + DEVICE_NATIVE_ENDIAN),
>>>> + DEFINE_PROP_END_OF_LIST(),
>>>> +};
>>>
>>> ... and I think the clear desire for default is little-endian. I would make the
>>> property be bool, and add a comment that this is only for m68k compatibility, so don't
>>> use it in new code.
>>
>> m68k doesn't really need this.
>>
>> kernel with the m68k virt machine and goldfish device supports "native" mode so I think
>> it's not needed to add another layer of complexity for it.
>
> "Another level"? I'm talking about removing "native", and only having "big" and "little",
> which is less complexity.
"Less complexity" is to keep only native. I'm not against the change, I'm just saying it's
not needed by m68k.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
@ 2022-07-04 10:23 ` Laurent Vivier
0 siblings, 0 replies; 53+ messages in thread
From: Laurent Vivier @ 2022-07-04 10:23 UTC (permalink / raw)
To: Richard Henderson, Stafford Horne, QEMU Development
Cc: open list:Goldfish RTC, Anup Patel, Openrisc, Alistair Francis
On 04/07/2022 12:21, Richard Henderson wrote:
> On 7/4/22 15:46, Laurent Vivier wrote:
>> On 04/07/2022 11:59, Richard Henderson wrote:
>>> On 7/4/22 02:58, Stafford Horne wrote:
>>>> -static const MemoryRegionOps goldfish_rtc_ops = {
>>>> - .read = goldfish_rtc_read,
>>>> - .write = goldfish_rtc_write,
>>>> - .endianness = DEVICE_NATIVE_ENDIAN,
>>>> - .valid = {
>>>> - .min_access_size = 4,
>>>> - .max_access_size = 4
>>>> - }
>>>> +static const MemoryRegionOps goldfish_rtc_ops[3] = {
>>>> + [DEVICE_NATIVE_ENDIAN] = {
>>>> + .read = goldfish_rtc_read,
>>>> + .write = goldfish_rtc_write,
>>>> + .endianness = DEVICE_NATIVE_ENDIAN,
>>>> + .valid = {
>>>> + .min_access_size = 4,
>>>> + .max_access_size = 4
>>>> + }
>>>> + },
>>>> + [DEVICE_LITTLE_ENDIAN] = {
>>>> + .read = goldfish_rtc_read,
>>>> + .write = goldfish_rtc_write,
>>>> + .endianness = DEVICE_LITTLE_ENDIAN,
>>>> + .valid = {
>>>> + .min_access_size = 4,
>>>> + .max_access_size = 4
>>>> + }
>>>> + },
>>>> + [DEVICE_BIG_ENDIAN] = {
>>>> + .read = goldfish_rtc_read,
>>>> + .write = goldfish_rtc_write,
>>>> + .endianness = DEVICE_BIG_ENDIAN,
>>>> + .valid = {
>>>> + .min_access_size = 4,
>>>> + .max_access_size = 4
>>>> + }
>>>> + },
>>>> };
>>>
>>> You don't need 3 copies, only big and little.
>>>
>>>> +static Property goldfish_rtc_properties[] = {
>>>> + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
>>>> + DEVICE_NATIVE_ENDIAN),
>>>> + DEFINE_PROP_END_OF_LIST(),
>>>> +};
>>>
>>> ... and I think the clear desire for default is little-endian. I would make the
>>> property be bool, and add a comment that this is only for m68k compatibility, so don't
>>> use it in new code.
>>
>> m68k doesn't really need this.
>>
>> kernel with the m68k virt machine and goldfish device supports "native" mode so I think
>> it's not needed to add another layer of complexity for it.
>
> "Another level"? I'm talking about removing "native", and only having "big" and "little",
> which is less complexity.
"Less complexity" is to keep only native. I'm not against the change, I'm just saying it's
not needed by m68k.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 11/11] docs/system: openrisc: Add OpenRISC documentation
2022-07-03 21:28 ` Stafford Horne
(?)
@ 2022-07-04 10:25 ` Richard Henderson
-1 siblings, 0 replies; 53+ messages in thread
From: Richard Henderson @ 2022-07-04 10:25 UTC (permalink / raw)
To: Stafford Horne, QEMU Development; +Cc: Openrisc
On 7/4/22 02:58, Stafford Horne wrote:
> Signed-off-by: Stafford Horne<shorne@gmail.com>
> ---
> docs/system/openrisc/cpu-features.rst | 15 ++++++
> docs/system/openrisc/emulation.rst | 17 +++++++
> docs/system/openrisc/or1k-sim.rst | 43 ++++++++++++++++
> docs/system/openrisc/virt.rst | 50 +++++++++++++++++++
> docs/system/target-openrisc.rst | 72 +++++++++++++++++++++++++++
> docs/system/targets.rst | 1 +
> 6 files changed, 198 insertions(+)
> create mode 100644 docs/system/openrisc/cpu-features.rst
> create mode 100644 docs/system/openrisc/emulation.rst
> create mode 100644 docs/system/openrisc/or1k-sim.rst
> create mode 100644 docs/system/openrisc/virt.rst
> create mode 100644 docs/system/target-openrisc.rst
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 07/11] target/openrisc: Add interrupted CPU to log
2022-07-04 10:04 ` Richard Henderson
@ 2022-07-04 20:26 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-04 20:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: Openrisc, QEMU Development
On Mon, Jul 04, 2022 at 03:34:52PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > When we are tracing it's helpful to know which CPU's are getting
> > interrupted, att that detail to the log line.
>
> "at".
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Actually it should be "add", thanks I fixed it.
-Stafford
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 07/11] target/openrisc: Add interrupted CPU to log
@ 2022-07-04 20:26 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-04 20:26 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Development, Openrisc
On Mon, Jul 04, 2022 at 03:34:52PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > When we are tracing it's helpful to know which CPU's are getting
> > interrupted, att that detail to the log line.
>
> "at".
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Actually it should be "add", thanks I fixed it.
-Stafford
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 08/11] target/openrisc: Enable MTTCG
2022-07-04 10:07 ` Richard Henderson
@ 2022-07-04 20:31 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-04 20:31 UTC (permalink / raw)
To: Richard Henderson; +Cc: Openrisc, QEMU Development
On Mon, Jul 04, 2022 at 03:37:04PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > case TO_SPR(10, 1): /* TTCR */
> > - cpu_openrisc_count_update(cpu);
> > + if (cpu_openrisc_timer_has_advanced(cpu)) {
> > + qemu_mutex_lock_iothread();
> > + cpu_openrisc_count_update(cpu);
> > + qemu_mutex_unlock_iothread();
> > + }
>
> Lock around the whole if, I think. Otherwise looks good.
Well, actually the cpu_openrisc_timer_has_advanced read is done once outside the
lock as an optimization to avoid taking the lock when it is not needed. i.e. if
we have 4 cores that all try to update the clock at the same time in theory only
one will have to take the lock and update the shared timer.
But I do see that could be flawed as after it takes the lock the timer could
have been updated by then. Ill move it inside and see if there is any
perfromance hit / increase in the sync-profile.
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 08/11] target/openrisc: Enable MTTCG
@ 2022-07-04 20:31 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-04 20:31 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Development, Openrisc
On Mon, Jul 04, 2022 at 03:37:04PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > case TO_SPR(10, 1): /* TTCR */
> > - cpu_openrisc_count_update(cpu);
> > + if (cpu_openrisc_timer_has_advanced(cpu)) {
> > + qemu_mutex_lock_iothread();
> > + cpu_openrisc_count_update(cpu);
> > + qemu_mutex_unlock_iothread();
> > + }
>
> Lock around the whole if, I think. Otherwise looks good.
Well, actually the cpu_openrisc_timer_has_advanced read is done once outside the
lock as an optimization to avoid taking the lock when it is not needed. i.e. if
we have 4 cores that all try to update the clock at the same time in theory only
one will have to take the lock and update the shared timer.
But I do see that could be flawed as after it takes the lock the timer could
have been updated by then. Ill move it inside and see if there is any
perfromance hit / increase in the sync-profile.
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 06/11] hw/openrisc: Initialize timer time at startupi
2022-07-04 10:03 ` Richard Henderson
@ 2022-07-04 20:32 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-04 20:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: Openrisc, QEMU Development
On Mon, Jul 04, 2022 at 03:33:26PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > The last_clk time was initialized at zero, this means when we calculate
> > the first delta we will calculate 0 vs current time which could cause
> > unnecessary hops.
> >
> > Initialize last_clk to the qemu clock on initialization.
> >
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > ---
> > hw/openrisc/cputimer.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
> > index 93268815d8..4dbba3a3d4 100644
> > --- a/hw/openrisc/cputimer.c
> > +++ b/hw/openrisc/cputimer.c
> > @@ -140,6 +140,7 @@ void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
> > if (or1k_timer == NULL) {
> > or1k_timer = g_new0(OR1KTimerState, 1);
> > + or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> > vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);
> > }
> > }
>
> Init doesn't seem right. Should be in reset?
Good point, I think reset would be better.
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 06/11] hw/openrisc: Initialize timer time at startupi
@ 2022-07-04 20:32 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-04 20:32 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Development, Openrisc
On Mon, Jul 04, 2022 at 03:33:26PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > The last_clk time was initialized at zero, this means when we calculate
> > the first delta we will calculate 0 vs current time which could cause
> > unnecessary hops.
> >
> > Initialize last_clk to the qemu clock on initialization.
> >
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > ---
> > hw/openrisc/cputimer.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
> > index 93268815d8..4dbba3a3d4 100644
> > --- a/hw/openrisc/cputimer.c
> > +++ b/hw/openrisc/cputimer.c
> > @@ -140,6 +140,7 @@ void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
> > if (or1k_timer == NULL) {
> > or1k_timer = g_new0(OR1KTimerState, 1);
> > + or1k_timer->last_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
> > vmstate_register(NULL, 0, &vmstate_or1k_timer, or1k_timer);
> > }
> > }
>
> Init doesn't seem right. Should be in reset?
Good point, I think reset would be better.
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
2022-07-04 9:59 ` Richard Henderson
@ 2022-07-04 20:32 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-04 20:32 UTC (permalink / raw)
To: Richard Henderson
Cc: Laurent Vivier, open list:Goldfish RTC, Anup Patel,
QEMU Development, Openrisc, Alistair Francis
On Mon, Jul 04, 2022 at 03:29:57PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > -static const MemoryRegionOps goldfish_rtc_ops = {
> > - .read = goldfish_rtc_read,
> > - .write = goldfish_rtc_write,
> > - .endianness = DEVICE_NATIVE_ENDIAN,
> > - .valid = {
> > - .min_access_size = 4,
> > - .max_access_size = 4
> > - }
> > +static const MemoryRegionOps goldfish_rtc_ops[3] = {
> > + [DEVICE_NATIVE_ENDIAN] = {
> > + .read = goldfish_rtc_read,
> > + .write = goldfish_rtc_write,
> > + .endianness = DEVICE_NATIVE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 4,
> > + .max_access_size = 4
> > + }
> > + },
> > + [DEVICE_LITTLE_ENDIAN] = {
> > + .read = goldfish_rtc_read,
> > + .write = goldfish_rtc_write,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 4,
> > + .max_access_size = 4
> > + }
> > + },
> > + [DEVICE_BIG_ENDIAN] = {
> > + .read = goldfish_rtc_read,
> > + .write = goldfish_rtc_write,
> > + .endianness = DEVICE_BIG_ENDIAN,
> > + .valid = {
> > + .min_access_size = 4,
> > + .max_access_size = 4
> > + }
> > + },
> > };
>
> You don't need 3 copies, only big and little.
>
> > +static Property goldfish_rtc_properties[] = {
> > + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
> > + DEVICE_NATIVE_ENDIAN),
> > + DEFINE_PROP_END_OF_LIST(),
> > +};
>
> ... and I think the clear desire for default is little-endian. I would make
> the property be bool, and add a comment that this is only for m68k
> compatibility, so don't use it in new code.
Yeah, that makes sense.
-Stafford
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
@ 2022-07-04 20:32 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-04 20:32 UTC (permalink / raw)
To: Richard Henderson
Cc: QEMU Development, Openrisc, Laurent Vivier, Anup Patel,
Alistair Francis, open list:Goldfish RTC
On Mon, Jul 04, 2022 at 03:29:57PM +0530, Richard Henderson wrote:
> On 7/4/22 02:58, Stafford Horne wrote:
> > -static const MemoryRegionOps goldfish_rtc_ops = {
> > - .read = goldfish_rtc_read,
> > - .write = goldfish_rtc_write,
> > - .endianness = DEVICE_NATIVE_ENDIAN,
> > - .valid = {
> > - .min_access_size = 4,
> > - .max_access_size = 4
> > - }
> > +static const MemoryRegionOps goldfish_rtc_ops[3] = {
> > + [DEVICE_NATIVE_ENDIAN] = {
> > + .read = goldfish_rtc_read,
> > + .write = goldfish_rtc_write,
> > + .endianness = DEVICE_NATIVE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 4,
> > + .max_access_size = 4
> > + }
> > + },
> > + [DEVICE_LITTLE_ENDIAN] = {
> > + .read = goldfish_rtc_read,
> > + .write = goldfish_rtc_write,
> > + .endianness = DEVICE_LITTLE_ENDIAN,
> > + .valid = {
> > + .min_access_size = 4,
> > + .max_access_size = 4
> > + }
> > + },
> > + [DEVICE_BIG_ENDIAN] = {
> > + .read = goldfish_rtc_read,
> > + .write = goldfish_rtc_write,
> > + .endianness = DEVICE_BIG_ENDIAN,
> > + .valid = {
> > + .min_access_size = 4,
> > + .max_access_size = 4
> > + }
> > + },
> > };
>
> You don't need 3 copies, only big and little.
>
> > +static Property goldfish_rtc_properties[] = {
> > + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
> > + DEVICE_NATIVE_ENDIAN),
> > + DEFINE_PROP_END_OF_LIST(),
> > +};
>
> ... and I think the clear desire for default is little-endian. I would make
> the property be bool, and add a comment that this is only for m68k
> compatibility, so don't use it in new code.
Yeah, that makes sense.
-Stafford
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
2022-07-04 10:23 ` Laurent Vivier
@ 2022-07-04 20:40 ` Stafford Horne
-1 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-04 20:40 UTC (permalink / raw)
To: Laurent Vivier
Cc: open list:Goldfish RTC, Anup Patel, Richard Henderson,
QEMU Development, Openrisc, Alistair Francis
On Mon, Jul 04, 2022 at 12:23:23PM +0200, Laurent Vivier wrote:
> On 04/07/2022 12:21, Richard Henderson wrote:
> > On 7/4/22 15:46, Laurent Vivier wrote:
> > > On 04/07/2022 11:59, Richard Henderson wrote:
> > > > On 7/4/22 02:58, Stafford Horne wrote:
> > > > > -static const MemoryRegionOps goldfish_rtc_ops = {
> > > > > - .read = goldfish_rtc_read,
> > > > > - .write = goldfish_rtc_write,
> > > > > - .endianness = DEVICE_NATIVE_ENDIAN,
> > > > > - .valid = {
> > > > > - .min_access_size = 4,
> > > > > - .max_access_size = 4
> > > > > - }
> > > > > +static const MemoryRegionOps goldfish_rtc_ops[3] = {
> > > > > + [DEVICE_NATIVE_ENDIAN] = {
> > > > > + .read = goldfish_rtc_read,
> > > > > + .write = goldfish_rtc_write,
> > > > > + .endianness = DEVICE_NATIVE_ENDIAN,
> > > > > + .valid = {
> > > > > + .min_access_size = 4,
> > > > > + .max_access_size = 4
> > > > > + }
> > > > > + },
> > > > > + [DEVICE_LITTLE_ENDIAN] = {
> > > > > + .read = goldfish_rtc_read,
> > > > > + .write = goldfish_rtc_write,
> > > > > + .endianness = DEVICE_LITTLE_ENDIAN,
> > > > > + .valid = {
> > > > > + .min_access_size = 4,
> > > > > + .max_access_size = 4
> > > > > + }
> > > > > + },
> > > > > + [DEVICE_BIG_ENDIAN] = {
> > > > > + .read = goldfish_rtc_read,
> > > > > + .write = goldfish_rtc_write,
> > > > > + .endianness = DEVICE_BIG_ENDIAN,
> > > > > + .valid = {
> > > > > + .min_access_size = 4,
> > > > > + .max_access_size = 4
> > > > > + }
> > > > > + },
> > > > > };
> > > >
> > > > You don't need 3 copies, only big and little.
> > > >
> > > > > +static Property goldfish_rtc_properties[] = {
> > > > > + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
> > > > > + DEVICE_NATIVE_ENDIAN),
> > > > > + DEFINE_PROP_END_OF_LIST(),
> > > > > +};
> > > >
> > > > ... and I think the clear desire for default is little-endian.
> > > > I would make the property be bool, and add a comment that this
> > > > is only for m68k compatibility, so don't use it in new code.
> > >
> > > m68k doesn't really need this.
> > >
> > > kernel with the m68k virt machine and goldfish device supports
> > > "native" mode so I think it's not needed to add another layer of
> > > complexity for it.
> >
> > "Another level"? I'm talking about removing "native", and only having
> > "big" and "little", which is less complexity.
>
> "Less complexity" is to keep only native. I'm not against the change, I'm
> just saying it's not needed by m68k.
Hi Laurent,
I would agree if we only had m68k. But I am making this change so that OpenRISC
(another big-endian architecture) could use this. In the OpenRISC case we want
to use this as little-endian so no kernel updates would be needed.
So in the end we will have the following qemu platforms:
riscv{LE}--------------->goldfish_rtc{LE}
mips-longsoon3{LE}------>goldfish_rtc{LE}
openrisc{BE}------------>goldfish_rtc{LE} (LE to BE conversion done in driver)
m68k{BE}---------------->goldfish_rtc{BE} (only big-endian user)
-Stafford
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
@ 2022-07-04 20:40 ` Stafford Horne
0 siblings, 0 replies; 53+ messages in thread
From: Stafford Horne @ 2022-07-04 20:40 UTC (permalink / raw)
To: Laurent Vivier
Cc: Richard Henderson, QEMU Development, Openrisc, Anup Patel,
Alistair Francis, open list:Goldfish RTC
On Mon, Jul 04, 2022 at 12:23:23PM +0200, Laurent Vivier wrote:
> On 04/07/2022 12:21, Richard Henderson wrote:
> > On 7/4/22 15:46, Laurent Vivier wrote:
> > > On 04/07/2022 11:59, Richard Henderson wrote:
> > > > On 7/4/22 02:58, Stafford Horne wrote:
> > > > > -static const MemoryRegionOps goldfish_rtc_ops = {
> > > > > - .read = goldfish_rtc_read,
> > > > > - .write = goldfish_rtc_write,
> > > > > - .endianness = DEVICE_NATIVE_ENDIAN,
> > > > > - .valid = {
> > > > > - .min_access_size = 4,
> > > > > - .max_access_size = 4
> > > > > - }
> > > > > +static const MemoryRegionOps goldfish_rtc_ops[3] = {
> > > > > + [DEVICE_NATIVE_ENDIAN] = {
> > > > > + .read = goldfish_rtc_read,
> > > > > + .write = goldfish_rtc_write,
> > > > > + .endianness = DEVICE_NATIVE_ENDIAN,
> > > > > + .valid = {
> > > > > + .min_access_size = 4,
> > > > > + .max_access_size = 4
> > > > > + }
> > > > > + },
> > > > > + [DEVICE_LITTLE_ENDIAN] = {
> > > > > + .read = goldfish_rtc_read,
> > > > > + .write = goldfish_rtc_write,
> > > > > + .endianness = DEVICE_LITTLE_ENDIAN,
> > > > > + .valid = {
> > > > > + .min_access_size = 4,
> > > > > + .max_access_size = 4
> > > > > + }
> > > > > + },
> > > > > + [DEVICE_BIG_ENDIAN] = {
> > > > > + .read = goldfish_rtc_read,
> > > > > + .write = goldfish_rtc_write,
> > > > > + .endianness = DEVICE_BIG_ENDIAN,
> > > > > + .valid = {
> > > > > + .min_access_size = 4,
> > > > > + .max_access_size = 4
> > > > > + }
> > > > > + },
> > > > > };
> > > >
> > > > You don't need 3 copies, only big and little.
> > > >
> > > > > +static Property goldfish_rtc_properties[] = {
> > > > > + DEFINE_PROP_UINT8("endianness", GoldfishRTCState, endianness,
> > > > > + DEVICE_NATIVE_ENDIAN),
> > > > > + DEFINE_PROP_END_OF_LIST(),
> > > > > +};
> > > >
> > > > ... and I think the clear desire for default is little-endian.
> > > > I would make the property be bool, and add a comment that this
> > > > is only for m68k compatibility, so don't use it in new code.
> > >
> > > m68k doesn't really need this.
> > >
> > > kernel with the m68k virt machine and goldfish device supports
> > > "native" mode so I think it's not needed to add another layer of
> > > complexity for it.
> >
> > "Another level"? I'm talking about removing "native", and only having
> > "big" and "little", which is less complexity.
>
> "Less complexity" is to keep only native. I'm not against the change, I'm
> just saying it's not needed by m68k.
Hi Laurent,
I would agree if we only had m68k. But I am making this change so that OpenRISC
(another big-endian architecture) could use this. In the OpenRISC case we want
to use this as little-endian so no kernel updates would be needed.
So in the end we will have the following qemu platforms:
riscv{LE}--------------->goldfish_rtc{LE}
mips-longsoon3{LE}------>goldfish_rtc{LE}
openrisc{BE}------------>goldfish_rtc{LE} (LE to BE conversion done in driver)
m68k{BE}---------------->goldfish_rtc{BE} (only big-endian user)
-Stafford
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
2022-07-04 20:40 ` Stafford Horne
(?)
@ 2022-07-05 0:53 ` Jason A. Donenfeld
-1 siblings, 0 replies; 53+ messages in thread
From: Jason A. Donenfeld @ 2022-07-05 0:53 UTC (permalink / raw)
To: Stafford Horne
Cc: Laurent Vivier, open list:Goldfish RTC, Anup Patel,
Richard Henderson, QEMU Development, Openrisc, Alistair Francis
On Tue, Jul 05, 2022 at 05:40:31AM +0900, Stafford Horne wrote:
> riscv{LE}--------------->goldfish_rtc{LE}
> mips-longsoon3{LE}------>goldfish_rtc{LE}
> openrisc{BE}------------>goldfish_rtc{LE} (LE to BE conversion done in driver)
> m68k{BE}---------------->goldfish_rtc{BE} (only big-endian user)
I wish the powers that be would lighten up a little bit and let us
change m68k to be LE, and then we could avoid all this...
Just a last grumble, I guess.
Jason
^ permalink raw reply [flat|nested] 53+ messages in thread
end of thread, other threads:[~2022-07-05 0:55 UTC | newest]
Thread overview: 53+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-03 21:28 [PATCH v2 00/11] OpenRISC Virtual Machine Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-03 21:28 ` [PATCH v2 01/11] hw/openrisc: Split re-usable boot time apis out to boot.c Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-03 21:28 ` [PATCH v2 02/11] target/openrisc: Fix memory reading in debugger Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-04 10:01 ` Richard Henderson
2022-07-03 21:28 ` [PATCH v2 03/11] goldfish_rtc: Add endianness property Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-04 2:50 ` Anup Patel
2022-07-04 2:50 ` Anup Patel
2022-07-04 9:59 ` Richard Henderson
2022-07-04 9:59 ` Richard Henderson
2022-07-04 10:16 ` Laurent Vivier
2022-07-04 10:16 ` Laurent Vivier
2022-07-04 10:21 ` Richard Henderson
2022-07-04 10:21 ` Richard Henderson
2022-07-04 10:23 ` Laurent Vivier
2022-07-04 10:23 ` Laurent Vivier
2022-07-04 20:40 ` Stafford Horne
2022-07-04 20:40 ` Stafford Horne
2022-07-05 0:53 ` Jason A. Donenfeld
2022-07-04 20:32 ` Stafford Horne
2022-07-04 20:32 ` Stafford Horne
2022-07-03 21:28 ` [PATCH v2 04/11] hw/openrisc: Add the OpenRISC virtual machine Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-03 21:28 ` [PATCH v2 05/11] hw/openrisc: Add PCI bus support to virt Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-03 21:28 ` [PATCH v2 06/11] hw/openrisc: Initialize timer time at startup Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-04 10:03 ` Richard Henderson
2022-07-04 20:32 ` [PATCH v2 06/11] hw/openrisc: Initialize timer time at startupi Stafford Horne
2022-07-04 20:32 ` Stafford Horne
2022-07-03 21:28 ` [PATCH v2 07/11] target/openrisc: Add interrupted CPU to log Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-04 10:04 ` Richard Henderson
2022-07-04 20:26 ` Stafford Horne
2022-07-04 20:26 ` Stafford Horne
2022-07-03 21:28 ` [PATCH v2 08/11] target/openrisc: Enable MTTCG Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-04 10:07 ` Richard Henderson
2022-07-04 20:31 ` Stafford Horne
2022-07-04 20:31 ` Stafford Horne
2022-07-03 21:28 ` [PATCH v2 09/11] target/openrisc: Interrupt handling fixes Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-04 10:20 ` Richard Henderson
2022-07-03 21:28 ` [PATCH v2 10/11] hw/openrisc: virt: pass random seed to fdt Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-04 10:22 ` Richard Henderson
2022-07-04 10:22 ` Richard Henderson
2022-07-03 21:28 ` [PATCH v2 11/11] docs/system: openrisc: Add OpenRISC documentation Stafford Horne
2022-07-03 21:28 ` Stafford Horne
2022-07-04 10:25 ` Richard Henderson
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