* [PATCH v5 1/4] spi: dw: Fix IP-core versions macro
2022-07-06 4:20 [PATCH v5 0/4] Add support for Intel Thunder Bay SPI controller nandhini.srikandan
@ 2022-07-06 4:20 ` nandhini.srikandan
2022-07-06 11:58 ` Mark Brown
2022-07-07 13:29 ` Serge Semin
2022-07-06 4:20 ` [PATCH v5 2/4] dt-bindings: spi: Add bindings for Intel Thunder Bay SoC nandhini.srikandan
` (2 subsequent siblings)
3 siblings, 2 replies; 13+ messages in thread
From: nandhini.srikandan @ 2022-07-06 4:20 UTC (permalink / raw)
To: fancer.lancer, broonie, robh+dt, linux-spi, linux-kernel
Cc: devicetree, mgross, kris.pan, kenchappa.demakkanavar,
furong.zhou, mallikarjunappa.sangannavar, mahesh.r.vaidya,
nandhini.srikandan, rashmi.a
From: Nandhini Srikandan <nandhini.srikandan@intel.com>
Fixes: 2cc8d9227bbb ("spi: dw: Introduce Synopsys IP-core versions interface")
Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
---
drivers/spi/spi-dw.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index d5ee5130601e..79d853f6d192 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -23,7 +23,7 @@
((_dws)->ip == DW_ ## _ip ## _ID)
#define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \
- (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ver)
+ (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
#define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==)
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v5 1/4] spi: dw: Fix IP-core versions macro
2022-07-06 4:20 ` [PATCH v5 1/4] spi: dw: Fix IP-core versions macro nandhini.srikandan
@ 2022-07-06 11:58 ` Mark Brown
2022-07-06 14:56 ` Srikandan, Nandhini
2022-07-07 13:29 ` Serge Semin
1 sibling, 1 reply; 13+ messages in thread
From: Mark Brown @ 2022-07-06 11:58 UTC (permalink / raw)
To: nandhini.srikandan
Cc: fancer.lancer, robh+dt, linux-spi, linux-kernel, devicetree,
mgross, kris.pan, kenchappa.demakkanavar, furong.zhou,
mallikarjunappa.sangannavar, mahesh.r.vaidya, rashmi.a
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On Wed, Jul 06, 2022 at 12:20:36PM +0800, nandhini.srikandan@intel.com wrote:
> From: Nandhini Srikandan <nandhini.srikandan@intel.com>
>
> Fixes: 2cc8d9227bbb ("spi: dw: Introduce Synopsys IP-core versions interface")
> Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
What is the problem and how does this patch fix it?
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^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH v5 1/4] spi: dw: Fix IP-core versions macro
2022-07-06 11:58 ` Mark Brown
@ 2022-07-06 14:56 ` Srikandan, Nandhini
2022-07-06 14:59 ` Mark Brown
0 siblings, 1 reply; 13+ messages in thread
From: Srikandan, Nandhini @ 2022-07-06 14:56 UTC (permalink / raw)
To: Mark Brown
Cc: fancer.lancer, robh+dt, linux-spi, linux-kernel, devicetree,
mgross, Pan, Kris, Demakkanavar, Kenchappa, Zhou, Furong,
Sangannavar, Mallikarjunappa, Vaidya, Mahesh R, A, Rashmi
> -----Original Message-----
> From: Mark Brown <broonie@kernel.org>
> Sent: Wednesday, July 6, 2022 5:28 PM
> To: Srikandan, Nandhini <nandhini.srikandan@intel.com>
> Cc: fancer.lancer@gmail.com; robh+dt@kernel.org; linux-
> spi@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; mgross@linux.intel.com; Pan, Kris
> <kris.pan@intel.com>; Demakkanavar, Kenchappa
> <kenchappa.demakkanavar@intel.com>; Zhou, Furong
> <furong.zhou@intel.com>; Sangannavar, Mallikarjunappa
> <mallikarjunappa.sangannavar@intel.com>; Vaidya, Mahesh R
> <mahesh.r.vaidya@intel.com>; A, Rashmi <rashmi.a@intel.com>
> Subject: Re: [PATCH v5 1/4] spi: dw: Fix IP-core versions macro
>
> On Wed, Jul 06, 2022 at 12:20:36PM +0800, nandhini.srikandan@intel.com
> wrote:
> > From: Nandhini Srikandan <nandhini.srikandan@intel.com>
> >
> > Fixes: 2cc8d9227bbb ("spi: dw: Introduce Synopsys IP-core versions
> interface")
> > Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
>
> What is the problem and how does this patch fix it?
The macro was introduced by Serge Semin in the patch set (2cc8d9227bbb) but it was unused.
It is used by one of the patches in the current patchset and without the fix it leads to compilation error. I had included this in v4 and Serge Semin had asked me to add the "Fixes: 2cc8d9227bbb" tag and keep it at the top of the series. So, I have kept it as first patch in this patchset series.
- Nandhini
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 1/4] spi: dw: Fix IP-core versions macro
2022-07-06 14:56 ` Srikandan, Nandhini
@ 2022-07-06 14:59 ` Mark Brown
0 siblings, 0 replies; 13+ messages in thread
From: Mark Brown @ 2022-07-06 14:59 UTC (permalink / raw)
To: Srikandan, Nandhini
Cc: fancer.lancer, robh+dt, linux-spi, linux-kernel, devicetree,
mgross, Pan, Kris, Demakkanavar, Kenchappa, Zhou, Furong,
Sangannavar, Mallikarjunappa, Vaidya, Mahesh R, A, Rashmi
[-- Attachment #1: Type: text/plain, Size: 1010 bytes --]
On Wed, Jul 06, 2022 at 02:56:30PM +0000, Srikandan, Nandhini wrote:
> > wrote:
> > > From: Nandhini Srikandan <nandhini.srikandan@intel.com>
> > >
> > > Fixes: 2cc8d9227bbb ("spi: dw: Introduce Synopsys IP-core versions
> > interface")
> > > Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
> > What is the problem and how does this patch fix it?
> The macro was introduced by Serge Semin in the patch set (2cc8d9227bbb) but it was unused.
> It is used by one of the patches in the current patchset and without the fix it leads to compilation error. I had included this in v4 and Serge Semin had asked me to add the "Fixes: 2cc8d9227bbb" tag and keep it at the top of the series. So, I have kept it as first patch in this patchset series.
This is information that ought to be in the changelog.
Please fix your mail client to word wrap within paragraphs at something
substantially less than 80 columns. Doing this makes your messages much
easier to read and reply to.
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 1/4] spi: dw: Fix IP-core versions macro
2022-07-06 4:20 ` [PATCH v5 1/4] spi: dw: Fix IP-core versions macro nandhini.srikandan
2022-07-06 11:58 ` Mark Brown
@ 2022-07-07 13:29 ` Serge Semin
1 sibling, 0 replies; 13+ messages in thread
From: Serge Semin @ 2022-07-07 13:29 UTC (permalink / raw)
To: nandhini.srikandan
Cc: broonie, robh+dt, linux-spi, linux-kernel, devicetree, mgross,
kris.pan, kenchappa.demakkanavar, furong.zhou,
mallikarjunappa.sangannavar, mahesh.r.vaidya, rashmi.a
Hi Nandhini
On Wed, Jul 06, 2022 at 12:20:36PM +0800, nandhini.srikandan@intel.com wrote:
> From: Nandhini Srikandan <nandhini.srikandan@intel.com>
>
> Fixes: 2cc8d9227bbb ("spi: dw: Introduce Synopsys IP-core versions interface")
> Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
As Mark already noted each patch is supposed to have a changelog [1].
Please add a detailed explanation of the problem above the tags
block [1].
[1] "Patch formatting and changelogs" Documentation/process/5.Posting.rst
-Sergey
> ---
> drivers/spi/spi-dw.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index d5ee5130601e..79d853f6d192 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -23,7 +23,7 @@
> ((_dws)->ip == DW_ ## _ip ## _ID)
>
> #define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \
> - (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ver)
> + (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
>
> #define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==)
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 2/4] dt-bindings: spi: Add bindings for Intel Thunder Bay SoC
2022-07-06 4:20 [PATCH v5 0/4] Add support for Intel Thunder Bay SPI controller nandhini.srikandan
2022-07-06 4:20 ` [PATCH v5 1/4] spi: dw: Fix IP-core versions macro nandhini.srikandan
@ 2022-07-06 4:20 ` nandhini.srikandan
2022-07-06 14:48 ` Rob Herring
2022-07-07 13:22 ` Serge Semin
2022-07-06 4:20 ` [PATCH v5 3/4] spi: dw: Add support for master mode selection for DWC SSI controller nandhini.srikandan
2022-07-06 4:20 ` [PATCH v5 4/4] spi: dw: Add support for Intel Thunder Bay SPI controller nandhini.srikandan
3 siblings, 2 replies; 13+ messages in thread
From: nandhini.srikandan @ 2022-07-06 4:20 UTC (permalink / raw)
To: fancer.lancer, broonie, robh+dt, linux-spi, linux-kernel
Cc: devicetree, mgross, kris.pan, kenchappa.demakkanavar,
furong.zhou, mallikarjunappa.sangannavar, mahesh.r.vaidya,
nandhini.srikandan, rashmi.a
From: Nandhini Srikandan <nandhini.srikandan@intel.com>
Add documentation for SPI controller in Intel Thunder Bay SoC.
Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
index d7e08b03e204..5ecd996ebf33 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -61,6 +61,8 @@ properties:
- const: snps,dw-apb-ssi
- description: Intel Keem Bay SPI Controller
const: intel,keembay-ssi
+ - description: Intel Thunder Bay SPI Controller
+ const: intel,thunderbay-ssi
- description: Baikal-T1 SPI Controller
const: baikal,bt1-ssi
- description: Baikal-T1 System Boot SPI Controller
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v5 2/4] dt-bindings: spi: Add bindings for Intel Thunder Bay SoC
2022-07-06 4:20 ` [PATCH v5 2/4] dt-bindings: spi: Add bindings for Intel Thunder Bay SoC nandhini.srikandan
@ 2022-07-06 14:48 ` Rob Herring
2022-07-07 13:22 ` Serge Semin
1 sibling, 0 replies; 13+ messages in thread
From: Rob Herring @ 2022-07-06 14:48 UTC (permalink / raw)
To: nandhini.srikandan
Cc: mahesh.r.vaidya, kenchappa.demakkanavar, robh+dt, furong.zhou,
broonie, fancer.lancer, mgross, mallikarjunappa.sangannavar,
rashmi.a, devicetree, kris.pan, linux-spi, linux-kernel
On Wed, 06 Jul 2022 12:20:37 +0800, nandhini.srikandan@intel.com wrote:
> From: Nandhini Srikandan <nandhini.srikandan@intel.com>
>
> Add documentation for SPI controller in Intel Thunder Bay SoC.
>
> Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
> ---
> Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH v5 2/4] dt-bindings: spi: Add bindings for Intel Thunder Bay SoC
2022-07-06 4:20 ` [PATCH v5 2/4] dt-bindings: spi: Add bindings for Intel Thunder Bay SoC nandhini.srikandan
2022-07-06 14:48 ` Rob Herring
@ 2022-07-07 13:22 ` Serge Semin
1 sibling, 0 replies; 13+ messages in thread
From: Serge Semin @ 2022-07-07 13:22 UTC (permalink / raw)
To: nandhini.srikandan
Cc: broonie, robh+dt, linux-spi, linux-kernel, devicetree, mgross,
kris.pan, kenchappa.demakkanavar, furong.zhou,
mallikarjunappa.sangannavar, mahesh.r.vaidya, rashmi.a
On Wed, Jul 06, 2022 at 12:20:37PM +0800, nandhini.srikandan@intel.com wrote:
> From: Nandhini Srikandan <nandhini.srikandan@intel.com>
>
> Add documentation for SPI controller in Intel Thunder Bay SoC.
>
> Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
> ---
> Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
-Sergey
>
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> index d7e08b03e204..5ecd996ebf33 100644
> --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -61,6 +61,8 @@ properties:
> - const: snps,dw-apb-ssi
> - description: Intel Keem Bay SPI Controller
> const: intel,keembay-ssi
> + - description: Intel Thunder Bay SPI Controller
> + const: intel,thunderbay-ssi
> - description: Baikal-T1 SPI Controller
> const: baikal,bt1-ssi
> - description: Baikal-T1 System Boot SPI Controller
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 3/4] spi: dw: Add support for master mode selection for DWC SSI controller
2022-07-06 4:20 [PATCH v5 0/4] Add support for Intel Thunder Bay SPI controller nandhini.srikandan
2022-07-06 4:20 ` [PATCH v5 1/4] spi: dw: Fix IP-core versions macro nandhini.srikandan
2022-07-06 4:20 ` [PATCH v5 2/4] dt-bindings: spi: Add bindings for Intel Thunder Bay SoC nandhini.srikandan
@ 2022-07-06 4:20 ` nandhini.srikandan
2022-07-07 13:32 ` Serge Semin
2022-07-06 4:20 ` [PATCH v5 4/4] spi: dw: Add support for Intel Thunder Bay SPI controller nandhini.srikandan
3 siblings, 1 reply; 13+ messages in thread
From: nandhini.srikandan @ 2022-07-06 4:20 UTC (permalink / raw)
To: fancer.lancer, broonie, robh+dt, linux-spi, linux-kernel
Cc: devicetree, mgross, kris.pan, kenchappa.demakkanavar,
furong.zhou, mallikarjunappa.sangannavar, mahesh.r.vaidya,
nandhini.srikandan, rashmi.a
From: Nandhini Srikandan <nandhini.srikandan@intel.com>
Add support to select the controller mode as master mode by setting
Bit 31 of CTRLR0 register. This feature is supported for controller
versions above v1.02.
Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
---
drivers/spi/spi-dw-core.c | 5 +++--
drivers/spi/spi-dw.h | 8 +-------
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index ecea471ff42c..41ae21e1b879 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -307,8 +307,9 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi)
if (spi->mode & SPI_LOOP)
cr0 |= DW_HSSI_CTRLR0_SRL;
- if (dws->caps & DW_SPI_CAP_KEEMBAY_MST)
- cr0 |= DW_HSSI_CTRLR0_KEEMBAY_MST;
+ /* CTRLR0[31] MST */
+ if (dw_spi_ver_is_ge(dws, HSSI, 102A))
+ cr0 |= DW_HSSI_CTRLR0_MST;
}
return cr0;
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 79d853f6d192..8b8f924ac410 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -94,13 +94,7 @@
#define DW_HSSI_CTRLR0_SCPOL BIT(9)
#define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
#define DW_HSSI_CTRLR0_SRL BIT(13)
-
-/*
- * For Keem Bay, CTRLR0[31] is used to select controller mode.
- * 0: SSI is slave
- * 1: SSI is master
- */
-#define DW_HSSI_CTRLR0_KEEMBAY_MST BIT(31)
+#define DW_HSSI_CTRLR0_MST BIT(31)
/* Bit fields in CTRLR1 */
#define DW_SPI_NDF_MASK GENMASK(15, 0)
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v5 3/4] spi: dw: Add support for master mode selection for DWC SSI controller
2022-07-06 4:20 ` [PATCH v5 3/4] spi: dw: Add support for master mode selection for DWC SSI controller nandhini.srikandan
@ 2022-07-07 13:32 ` Serge Semin
0 siblings, 0 replies; 13+ messages in thread
From: Serge Semin @ 2022-07-07 13:32 UTC (permalink / raw)
To: nandhini.srikandan
Cc: broonie, robh+dt, linux-spi, linux-kernel, devicetree, mgross,
kris.pan, kenchappa.demakkanavar, furong.zhou,
mallikarjunappa.sangannavar, mahesh.r.vaidya, rashmi.a
On Wed, Jul 06, 2022 at 12:20:38PM +0800, nandhini.srikandan@intel.com wrote:
> From: Nandhini Srikandan <nandhini.srikandan@intel.com>
>
> Add support to select the controller mode as master mode by setting
> Bit 31 of CTRLR0 register. This feature is supported for controller
> versions above v1.02.
>
> Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
-Sergey
> ---
> drivers/spi/spi-dw-core.c | 5 +++--
> drivers/spi/spi-dw.h | 8 +-------
> 2 files changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
> index ecea471ff42c..41ae21e1b879 100644
> --- a/drivers/spi/spi-dw-core.c
> +++ b/drivers/spi/spi-dw-core.c
> @@ -307,8 +307,9 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi)
> if (spi->mode & SPI_LOOP)
> cr0 |= DW_HSSI_CTRLR0_SRL;
>
> - if (dws->caps & DW_SPI_CAP_KEEMBAY_MST)
> - cr0 |= DW_HSSI_CTRLR0_KEEMBAY_MST;
> + /* CTRLR0[31] MST */
> + if (dw_spi_ver_is_ge(dws, HSSI, 102A))
> + cr0 |= DW_HSSI_CTRLR0_MST;
> }
>
> return cr0;
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index 79d853f6d192..8b8f924ac410 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -94,13 +94,7 @@
> #define DW_HSSI_CTRLR0_SCPOL BIT(9)
> #define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
> #define DW_HSSI_CTRLR0_SRL BIT(13)
> -
> -/*
> - * For Keem Bay, CTRLR0[31] is used to select controller mode.
> - * 0: SSI is slave
> - * 1: SSI is master
> - */
> -#define DW_HSSI_CTRLR0_KEEMBAY_MST BIT(31)
> +#define DW_HSSI_CTRLR0_MST BIT(31)
>
> /* Bit fields in CTRLR1 */
> #define DW_SPI_NDF_MASK GENMASK(15, 0)
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 4/4] spi: dw: Add support for Intel Thunder Bay SPI controller
2022-07-06 4:20 [PATCH v5 0/4] Add support for Intel Thunder Bay SPI controller nandhini.srikandan
` (2 preceding siblings ...)
2022-07-06 4:20 ` [PATCH v5 3/4] spi: dw: Add support for master mode selection for DWC SSI controller nandhini.srikandan
@ 2022-07-06 4:20 ` nandhini.srikandan
2022-07-07 13:34 ` Serge Semin
3 siblings, 1 reply; 13+ messages in thread
From: nandhini.srikandan @ 2022-07-06 4:20 UTC (permalink / raw)
To: fancer.lancer, broonie, robh+dt, linux-spi, linux-kernel
Cc: devicetree, mgross, kris.pan, kenchappa.demakkanavar,
furong.zhou, mallikarjunappa.sangannavar, mahesh.r.vaidya,
nandhini.srikandan, rashmi.a
From: Nandhini Srikandan <nandhini.srikandan@intel.com>
Add support for Intel Thunder Bay SPI controller, which uses DesignWare
DWC_ssi core and also add common init function for both Keem Bay and
Thunder Bay.
Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
---
drivers/spi/spi-dw-mmio.c | 8 ++++----
drivers/spi/spi-dw.h | 3 +--
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 5101c4c6017b..26c40ea6dd12 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -214,11 +214,10 @@ static int dw_spi_hssi_init(struct platform_device *pdev,
return 0;
}
-static int dw_spi_keembay_init(struct platform_device *pdev,
- struct dw_spi_mmio *dwsmmio)
+static int dw_spi_intel_init(struct platform_device *pdev,
+ struct dw_spi_mmio *dwsmmio)
{
dwsmmio->dws.ip = DW_HSSI_ID;
- dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST;
return 0;
}
@@ -349,7 +348,8 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
{ .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
- { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
+ { .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
+ { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
{ /* end of table */}
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 8b8f924ac410..9e8eb2b52d5c 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -31,8 +31,7 @@
/* DW SPI controller capabilities */
#define DW_SPI_CAP_CS_OVERRIDE BIT(0)
-#define DW_SPI_CAP_KEEMBAY_MST BIT(1)
-#define DW_SPI_CAP_DFS32 BIT(2)
+#define DW_SPI_CAP_DFS32 BIT(1)
/* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
#define DW_SPI_CTRLR0 0x00
--
2.17.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH v5 4/4] spi: dw: Add support for Intel Thunder Bay SPI controller
2022-07-06 4:20 ` [PATCH v5 4/4] spi: dw: Add support for Intel Thunder Bay SPI controller nandhini.srikandan
@ 2022-07-07 13:34 ` Serge Semin
0 siblings, 0 replies; 13+ messages in thread
From: Serge Semin @ 2022-07-07 13:34 UTC (permalink / raw)
To: nandhini.srikandan
Cc: broonie, robh+dt, linux-spi, linux-kernel, devicetree, mgross,
kris.pan, kenchappa.demakkanavar, furong.zhou,
mallikarjunappa.sangannavar, mahesh.r.vaidya, rashmi.a
On Wed, Jul 06, 2022 at 12:20:39PM +0800, nandhini.srikandan@intel.com wrote:
> From: Nandhini Srikandan <nandhini.srikandan@intel.com>
>
> Add support for Intel Thunder Bay SPI controller, which uses DesignWare
> DWC_ssi core and also add common init function for both Keem Bay and
> Thunder Bay.
>
> Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
-Sergey
> ---
> drivers/spi/spi-dw-mmio.c | 8 ++++----
> drivers/spi/spi-dw.h | 3 +--
> 2 files changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
> index 5101c4c6017b..26c40ea6dd12 100644
> --- a/drivers/spi/spi-dw-mmio.c
> +++ b/drivers/spi/spi-dw-mmio.c
> @@ -214,11 +214,10 @@ static int dw_spi_hssi_init(struct platform_device *pdev,
> return 0;
> }
>
> -static int dw_spi_keembay_init(struct platform_device *pdev,
> - struct dw_spi_mmio *dwsmmio)
> +static int dw_spi_intel_init(struct platform_device *pdev,
> + struct dw_spi_mmio *dwsmmio)
> {
> dwsmmio->dws.ip = DW_HSSI_ID;
> - dwsmmio->dws.caps = DW_SPI_CAP_KEEMBAY_MST;
>
> return 0;
> }
> @@ -349,7 +348,8 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
> { .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
> { .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
> { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
> - { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
> + { .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
> + { .compatible = "intel,thunderbay-ssi", .data = dw_spi_intel_init},
> { .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
> { .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
> { /* end of table */}
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index 8b8f924ac410..9e8eb2b52d5c 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -31,8 +31,7 @@
>
> /* DW SPI controller capabilities */
> #define DW_SPI_CAP_CS_OVERRIDE BIT(0)
> -#define DW_SPI_CAP_KEEMBAY_MST BIT(1)
> -#define DW_SPI_CAP_DFS32 BIT(2)
> +#define DW_SPI_CAP_DFS32 BIT(1)
>
> /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
> #define DW_SPI_CTRLR0 0x00
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 13+ messages in thread