* [PATCH v12 0/2] iommu/mediatek: TTBR up to 35bit support
@ 2022-06-30 9:29 ` yf.wang--- via iommu
0 siblings, 0 replies; 23+ messages in thread
From: yf.wang @ 2022-06-30 9:29 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek
This patchset adds MediaTek TTBR up to 35bit support for single normal zone.
Changes in v12:
- Update [PATCH 1/2]: remove GENMASK(31, 7)
- Update [PATCH 2/2]: remove MMU_PT_ADDR_MASK definition.
Changes in v11:
https://lore.kernel.org/linux-mediatek/20220630062508.23512-1-yf.wang@mediatek.com/
- According to Yong's suggestion in [PATCH v10] to update patch
- [PATCH 1/2]: Because keep ttbr u32, so the special logic of encoded PA
bits[34:32] to ttbr lower bits will apply to all the MediaTek cases,
not only for the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT, so remove
quirk check.
- [PATCH 2/2]: Because no need calculate the special ttbr, so remove ttbr
from mtk_iommu_domain and remove MMU_PT_ADDR_MASK calculate.
Changes in v10:
https://lore.kernel.org/linux-mediatek/20220616120713.12728-1-yf.wang@mediatek.com/
- According to Robin's suggestion in [PATCH v9] to update patch
- Recovery ttbr to u32, encoded PA bits[34:32] to ttbr lower bits.
- Remove PATCH: Rename MTK_IOMMU_TLB_ADDR to MTK_IOMMU_ADDR.
Changes in v9:
https://lore.kernel.org/linux-mediatek/20220615161224.6923-1-yf.wang@mediatek.com/
- According to Will's suggestion in [PATCH v8 1/3] update [PATCH 1/3]
- Rename function to_iopte_mtk to to_mtk_iopte.
- Modify gfp_l1 and slab_flag and add comment explaining.
- Add checking that the address is within 35 bits use cfg->oas.
- PATCH 1/3 & PATCH 2/3 no change.
Changes in v8:
https://lore.kernel.org/linux-mediatek/20220611102656.10954-1-yf.wang@mediatek.com/
- Add and update patch
- Add [2/3] patch update MTK_IOMMU_ADDR to calculate the special ttbr.
- Save the special ttbr to mtk_iommu_domain avoid calculate it again.
Changes in v7:
https://lore.kernel.org/linux-mediatek/20220530080432.29123-1-yf.wang@mediatek.com/
- Update patch and commit message
- Extend arm_v7s_cfg.ttbr to u64.
- Move the special ttbr logical into mtk_iommu.c.
- Update commit message for single normal zone.
Changes in v6:
- Update patch: gfp_l1 = GFP_KERNEL | __GFP_ZERO;
- Update commit message for single normal zone.
Changes in v5:
- Only update message-ID.
Changes in v4:
- Fix build test WARNING: use GENMASK_ULL replace GENMASK.
Changes in v3:
- Add version changes description, there is No new code change in V3.
Changes in v2:
- Update patch and commit message
- Add Level 1 pgtable PA up to 35bit.
- This is new feature, remove stable@vger.kernel.org
- Update commit message.
Ning Li (2):
iommu/io-pgtable-arm-v7s: Add a quirk to allow pgtable PA up to 35bit
iommu/mediatek: Allow page table PA up to 35bit
drivers/iommu/io-pgtable-arm-v7s.c | 75 ++++++++++++++++++++++--------
drivers/iommu/mtk_iommu.c | 13 +++--
include/linux/io-pgtable.h | 15 ++++--
3 files changed, 73 insertions(+), 30 deletions(-)
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v12 0/2] iommu/mediatek: TTBR up to 35bit support
@ 2022-06-30 9:29 ` yf.wang--- via iommu
0 siblings, 0 replies; 23+ messages in thread
From: yf.wang--- via iommu @ 2022-06-30 9:29 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, linux-kernel, Libo Kang, iommu, linux-mediatek,
Ning Li, linux-arm-kernel
This patchset adds MediaTek TTBR up to 35bit support for single normal zone.
Changes in v12:
- Update [PATCH 1/2]: remove GENMASK(31, 7)
- Update [PATCH 2/2]: remove MMU_PT_ADDR_MASK definition.
Changes in v11:
https://lore.kernel.org/linux-mediatek/20220630062508.23512-1-yf.wang@mediatek.com/
- According to Yong's suggestion in [PATCH v10] to update patch
- [PATCH 1/2]: Because keep ttbr u32, so the special logic of encoded PA
bits[34:32] to ttbr lower bits will apply to all the MediaTek cases,
not only for the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT, so remove
quirk check.
- [PATCH 2/2]: Because no need calculate the special ttbr, so remove ttbr
from mtk_iommu_domain and remove MMU_PT_ADDR_MASK calculate.
Changes in v10:
https://lore.kernel.org/linux-mediatek/20220616120713.12728-1-yf.wang@mediatek.com/
- According to Robin's suggestion in [PATCH v9] to update patch
- Recovery ttbr to u32, encoded PA bits[34:32] to ttbr lower bits.
- Remove PATCH: Rename MTK_IOMMU_TLB_ADDR to MTK_IOMMU_ADDR.
Changes in v9:
https://lore.kernel.org/linux-mediatek/20220615161224.6923-1-yf.wang@mediatek.com/
- According to Will's suggestion in [PATCH v8 1/3] update [PATCH 1/3]
- Rename function to_iopte_mtk to to_mtk_iopte.
- Modify gfp_l1 and slab_flag and add comment explaining.
- Add checking that the address is within 35 bits use cfg->oas.
- PATCH 1/3 & PATCH 2/3 no change.
Changes in v8:
https://lore.kernel.org/linux-mediatek/20220611102656.10954-1-yf.wang@mediatek.com/
- Add and update patch
- Add [2/3] patch update MTK_IOMMU_ADDR to calculate the special ttbr.
- Save the special ttbr to mtk_iommu_domain avoid calculate it again.
Changes in v7:
https://lore.kernel.org/linux-mediatek/20220530080432.29123-1-yf.wang@mediatek.com/
- Update patch and commit message
- Extend arm_v7s_cfg.ttbr to u64.
- Move the special ttbr logical into mtk_iommu.c.
- Update commit message for single normal zone.
Changes in v6:
- Update patch: gfp_l1 = GFP_KERNEL | __GFP_ZERO;
- Update commit message for single normal zone.
Changes in v5:
- Only update message-ID.
Changes in v4:
- Fix build test WARNING: use GENMASK_ULL replace GENMASK.
Changes in v3:
- Add version changes description, there is No new code change in V3.
Changes in v2:
- Update patch and commit message
- Add Level 1 pgtable PA up to 35bit.
- This is new feature, remove stable@vger.kernel.org
- Update commit message.
Ning Li (2):
iommu/io-pgtable-arm-v7s: Add a quirk to allow pgtable PA up to 35bit
iommu/mediatek: Allow page table PA up to 35bit
drivers/iommu/io-pgtable-arm-v7s.c | 75 ++++++++++++++++++++++--------
drivers/iommu/mtk_iommu.c | 13 +++--
include/linux/io-pgtable.h | 15 ++++--
3 files changed, 73 insertions(+), 30 deletions(-)
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v12 0/2] iommu/mediatek: TTBR up to 35bit support
@ 2022-06-30 9:29 ` yf.wang--- via iommu
0 siblings, 0 replies; 23+ messages in thread
From: yf.wang @ 2022-06-30 9:29 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek
This patchset adds MediaTek TTBR up to 35bit support for single normal zone.
Changes in v12:
- Update [PATCH 1/2]: remove GENMASK(31, 7)
- Update [PATCH 2/2]: remove MMU_PT_ADDR_MASK definition.
Changes in v11:
https://lore.kernel.org/linux-mediatek/20220630062508.23512-1-yf.wang@mediatek.com/
- According to Yong's suggestion in [PATCH v10] to update patch
- [PATCH 1/2]: Because keep ttbr u32, so the special logic of encoded PA
bits[34:32] to ttbr lower bits will apply to all the MediaTek cases,
not only for the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT, so remove
quirk check.
- [PATCH 2/2]: Because no need calculate the special ttbr, so remove ttbr
from mtk_iommu_domain and remove MMU_PT_ADDR_MASK calculate.
Changes in v10:
https://lore.kernel.org/linux-mediatek/20220616120713.12728-1-yf.wang@mediatek.com/
- According to Robin's suggestion in [PATCH v9] to update patch
- Recovery ttbr to u32, encoded PA bits[34:32] to ttbr lower bits.
- Remove PATCH: Rename MTK_IOMMU_TLB_ADDR to MTK_IOMMU_ADDR.
Changes in v9:
https://lore.kernel.org/linux-mediatek/20220615161224.6923-1-yf.wang@mediatek.com/
- According to Will's suggestion in [PATCH v8 1/3] update [PATCH 1/3]
- Rename function to_iopte_mtk to to_mtk_iopte.
- Modify gfp_l1 and slab_flag and add comment explaining.
- Add checking that the address is within 35 bits use cfg->oas.
- PATCH 1/3 & PATCH 2/3 no change.
Changes in v8:
https://lore.kernel.org/linux-mediatek/20220611102656.10954-1-yf.wang@mediatek.com/
- Add and update patch
- Add [2/3] patch update MTK_IOMMU_ADDR to calculate the special ttbr.
- Save the special ttbr to mtk_iommu_domain avoid calculate it again.
Changes in v7:
https://lore.kernel.org/linux-mediatek/20220530080432.29123-1-yf.wang@mediatek.com/
- Update patch and commit message
- Extend arm_v7s_cfg.ttbr to u64.
- Move the special ttbr logical into mtk_iommu.c.
- Update commit message for single normal zone.
Changes in v6:
- Update patch: gfp_l1 = GFP_KERNEL | __GFP_ZERO;
- Update commit message for single normal zone.
Changes in v5:
- Only update message-ID.
Changes in v4:
- Fix build test WARNING: use GENMASK_ULL replace GENMASK.
Changes in v3:
- Add version changes description, there is No new code change in V3.
Changes in v2:
- Update patch and commit message
- Add Level 1 pgtable PA up to 35bit.
- This is new feature, remove stable@vger.kernel.org
- Update commit message.
Ning Li (2):
iommu/io-pgtable-arm-v7s: Add a quirk to allow pgtable PA up to 35bit
iommu/mediatek: Allow page table PA up to 35bit
drivers/iommu/io-pgtable-arm-v7s.c | 75 ++++++++++++++++++++++--------
drivers/iommu/mtk_iommu.c | 13 +++--
include/linux/io-pgtable.h | 15 ++++--
3 files changed, 73 insertions(+), 30 deletions(-)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v12 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to allow pgtable PA up to 35bit
2022-06-30 9:29 ` yf.wang--- via iommu
(?)
@ 2022-06-30 9:29 ` yf.wang--- via iommu
-1 siblings, 0 replies; 23+ messages in thread
From: yf.wang @ 2022-06-30 9:29 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek, Yunfei Wang, Isaac J. Manjarres,
Georgi Djakov, Sven Peter
From: Yunfei Wang <yf.wang@mediatek.com>
Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA and
cause pgtable PA size larger than 32bit.
Since Mediatek IOMMU hardware support at most 35bit PA in pgtable,
so add a quirk to allow the PA of pgtables support up to bit35.
Signed-off-by: Ning Li <ning.li@mediatek.com>
Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 75 ++++++++++++++++++++++--------
include/linux/io-pgtable.h | 15 ++++--
2 files changed, 66 insertions(+), 24 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index be066c1503d3..ba3115fd0f86 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -182,14 +182,8 @@ static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg)
(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT);
}
-static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
- struct io_pgtable_cfg *cfg)
+static arm_v7s_iopte to_mtk_iopte(phys_addr_t paddr, arm_v7s_iopte pte)
{
- arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
-
- if (!arm_v7s_is_mtk_enabled(cfg))
- return pte;
-
if (paddr & BIT_ULL(32))
pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
if (paddr & BIT_ULL(33))
@@ -199,6 +193,17 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
return pte;
}
+static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
+ struct io_pgtable_cfg *cfg)
+{
+ arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
+
+ if (arm_v7s_is_mtk_enabled(cfg))
+ return to_mtk_iopte(paddr, pte);
+
+ return pte;
+}
+
static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl,
struct io_pgtable_cfg *cfg)
{
@@ -240,10 +245,17 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
dma_addr_t dma;
size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
void *table = NULL;
+ gfp_t gfp_l1;
+
+ /*
+ * ARM_MTK_TTBR_EXT extend the translation table base support larger
+ * memory address.
+ */
+ gfp_l1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
+ GFP_KERNEL : ARM_V7S_TABLE_GFP_DMA;
if (lvl == 1)
- table = (void *)__get_free_pages(
- __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA, get_order(size));
+ table = (void *)__get_free_pages(gfp_l1 | __GFP_ZERO, get_order(size));
else if (lvl == 2)
table = kmem_cache_zalloc(data->l2_tables, gfp);
@@ -251,7 +263,8 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
return NULL;
phys = virt_to_phys(table);
- if (phys != (arm_v7s_iopte)phys) {
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
+ phys >= (1ULL << cfg->oas) : phys != (arm_v7s_iopte)phys) {
/* Doesn't fit in PTE */
dev_err(dev, "Page table does not fit in PTE: %pa", &phys);
goto out_free;
@@ -457,9 +470,14 @@ static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table,
arm_v7s_iopte curr,
struct io_pgtable_cfg *cfg)
{
+ phys_addr_t phys = virt_to_phys(table);
arm_v7s_iopte old, new;
- new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE;
+ new = phys | ARM_V7S_PTE_TYPE_TABLE;
+
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)
+ new = to_mtk_iopte(phys, new);
+
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
new |= ARM_V7S_ATTR_NS_TABLE;
@@ -779,6 +797,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
void *cookie)
{
struct arm_v7s_io_pgtable *data;
+ slab_flags_t slab_flag;
+ phys_addr_t paddr;
if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
return NULL;
@@ -788,7 +808,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
IO_PGTABLE_QUIRK_NO_PERMS |
- IO_PGTABLE_QUIRK_ARM_MTK_EXT))
+ IO_PGTABLE_QUIRK_ARM_MTK_EXT |
+ IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT))
return NULL;
/* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
@@ -796,15 +817,27 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
!(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
return NULL;
+ if ((cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) &&
+ !arm_v7s_is_mtk_enabled(cfg))
+ return NULL;
+
data = kmalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return NULL;
spin_lock_init(&data->split_lock);
+
+ /*
+ * ARM_MTK_TTBR_EXT extend the translation table base support larger
+ * memory address.
+ */
+ slab_flag = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
+ 0 : ARM_V7S_TABLE_SLAB_FLAGS;
+
data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
ARM_V7S_TABLE_SIZE(2, cfg),
ARM_V7S_TABLE_SIZE(2, cfg),
- ARM_V7S_TABLE_SLAB_FLAGS, NULL);
+ slab_flag, NULL);
if (!data->l2_tables)
goto out_free_data;
@@ -850,12 +883,16 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
wmb();
/* TTBR */
- cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S |
- (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
- ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
- ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
- (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
- ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
+ paddr = virt_to_phys(data->pgd);
+ if (arm_v7s_is_mtk_enabled(cfg))
+ cfg->arm_v7s_cfg.ttbr = paddr | upper_32_bits(paddr);
+ else
+ cfg->arm_v7s_cfg.ttbr = paddr | ARM_V7S_TTBR_S |
+ (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
+ ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
+ ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
+ (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
+ ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
return &data->iop;
out_free_data:
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
index 86af6f0a00a2..ca98aeadcc80 100644
--- a/include/linux/io-pgtable.h
+++ b/include/linux/io-pgtable.h
@@ -74,17 +74,22 @@ struct io_pgtable_cfg {
* to support up to 35 bits PA where the bit32, bit33 and bit34 are
* encoded in the bit9, bit4 and bit5 of the PTE respectively.
*
+ * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs
+ * extend the translation table base support up to 35 bits PA, the
+ * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT.
+ *
* IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
* for use in the upper half of a split address space.
*
* IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
* attributes set in the TCR for a non-coherent page-table walker.
*/
- #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
- #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
- #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
- #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
- #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
+ #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
+ #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
+ #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
+ #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4)
+ #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
+ #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
unsigned long quirks;
unsigned long pgsize_bitmap;
unsigned int ias;
--
2.18.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v12 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to allow pgtable PA up to 35bit
@ 2022-06-30 9:29 ` yf.wang--- via iommu
0 siblings, 0 replies; 23+ messages in thread
From: yf.wang--- via iommu @ 2022-06-30 9:29 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: Isaac J. Manjarres, wsd_upstream, linux-kernel, Libo Kang,
Yunfei Wang, iommu, linux-mediatek, Ning Li, linux-arm-kernel
From: Yunfei Wang <yf.wang@mediatek.com>
Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA and
cause pgtable PA size larger than 32bit.
Since Mediatek IOMMU hardware support at most 35bit PA in pgtable,
so add a quirk to allow the PA of pgtables support up to bit35.
Signed-off-by: Ning Li <ning.li@mediatek.com>
Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 75 ++++++++++++++++++++++--------
include/linux/io-pgtable.h | 15 ++++--
2 files changed, 66 insertions(+), 24 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index be066c1503d3..ba3115fd0f86 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -182,14 +182,8 @@ static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg)
(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT);
}
-static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
- struct io_pgtable_cfg *cfg)
+static arm_v7s_iopte to_mtk_iopte(phys_addr_t paddr, arm_v7s_iopte pte)
{
- arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
-
- if (!arm_v7s_is_mtk_enabled(cfg))
- return pte;
-
if (paddr & BIT_ULL(32))
pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
if (paddr & BIT_ULL(33))
@@ -199,6 +193,17 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
return pte;
}
+static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
+ struct io_pgtable_cfg *cfg)
+{
+ arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
+
+ if (arm_v7s_is_mtk_enabled(cfg))
+ return to_mtk_iopte(paddr, pte);
+
+ return pte;
+}
+
static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl,
struct io_pgtable_cfg *cfg)
{
@@ -240,10 +245,17 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
dma_addr_t dma;
size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
void *table = NULL;
+ gfp_t gfp_l1;
+
+ /*
+ * ARM_MTK_TTBR_EXT extend the translation table base support larger
+ * memory address.
+ */
+ gfp_l1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
+ GFP_KERNEL : ARM_V7S_TABLE_GFP_DMA;
if (lvl == 1)
- table = (void *)__get_free_pages(
- __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA, get_order(size));
+ table = (void *)__get_free_pages(gfp_l1 | __GFP_ZERO, get_order(size));
else if (lvl == 2)
table = kmem_cache_zalloc(data->l2_tables, gfp);
@@ -251,7 +263,8 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
return NULL;
phys = virt_to_phys(table);
- if (phys != (arm_v7s_iopte)phys) {
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
+ phys >= (1ULL << cfg->oas) : phys != (arm_v7s_iopte)phys) {
/* Doesn't fit in PTE */
dev_err(dev, "Page table does not fit in PTE: %pa", &phys);
goto out_free;
@@ -457,9 +470,14 @@ static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table,
arm_v7s_iopte curr,
struct io_pgtable_cfg *cfg)
{
+ phys_addr_t phys = virt_to_phys(table);
arm_v7s_iopte old, new;
- new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE;
+ new = phys | ARM_V7S_PTE_TYPE_TABLE;
+
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)
+ new = to_mtk_iopte(phys, new);
+
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
new |= ARM_V7S_ATTR_NS_TABLE;
@@ -779,6 +797,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
void *cookie)
{
struct arm_v7s_io_pgtable *data;
+ slab_flags_t slab_flag;
+ phys_addr_t paddr;
if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
return NULL;
@@ -788,7 +808,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
IO_PGTABLE_QUIRK_NO_PERMS |
- IO_PGTABLE_QUIRK_ARM_MTK_EXT))
+ IO_PGTABLE_QUIRK_ARM_MTK_EXT |
+ IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT))
return NULL;
/* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
@@ -796,15 +817,27 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
!(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
return NULL;
+ if ((cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) &&
+ !arm_v7s_is_mtk_enabled(cfg))
+ return NULL;
+
data = kmalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return NULL;
spin_lock_init(&data->split_lock);
+
+ /*
+ * ARM_MTK_TTBR_EXT extend the translation table base support larger
+ * memory address.
+ */
+ slab_flag = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
+ 0 : ARM_V7S_TABLE_SLAB_FLAGS;
+
data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
ARM_V7S_TABLE_SIZE(2, cfg),
ARM_V7S_TABLE_SIZE(2, cfg),
- ARM_V7S_TABLE_SLAB_FLAGS, NULL);
+ slab_flag, NULL);
if (!data->l2_tables)
goto out_free_data;
@@ -850,12 +883,16 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
wmb();
/* TTBR */
- cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S |
- (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
- ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
- ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
- (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
- ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
+ paddr = virt_to_phys(data->pgd);
+ if (arm_v7s_is_mtk_enabled(cfg))
+ cfg->arm_v7s_cfg.ttbr = paddr | upper_32_bits(paddr);
+ else
+ cfg->arm_v7s_cfg.ttbr = paddr | ARM_V7S_TTBR_S |
+ (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
+ ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
+ ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
+ (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
+ ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
return &data->iop;
out_free_data:
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
index 86af6f0a00a2..ca98aeadcc80 100644
--- a/include/linux/io-pgtable.h
+++ b/include/linux/io-pgtable.h
@@ -74,17 +74,22 @@ struct io_pgtable_cfg {
* to support up to 35 bits PA where the bit32, bit33 and bit34 are
* encoded in the bit9, bit4 and bit5 of the PTE respectively.
*
+ * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs
+ * extend the translation table base support up to 35 bits PA, the
+ * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT.
+ *
* IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
* for use in the upper half of a split address space.
*
* IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
* attributes set in the TCR for a non-coherent page-table walker.
*/
- #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
- #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
- #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
- #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
- #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
+ #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
+ #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
+ #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
+ #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4)
+ #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
+ #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
unsigned long quirks;
unsigned long pgsize_bitmap;
unsigned int ias;
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v12 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to allow pgtable PA up to 35bit
@ 2022-06-30 9:29 ` yf.wang--- via iommu
0 siblings, 0 replies; 23+ messages in thread
From: yf.wang @ 2022-06-30 9:29 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek, Yunfei Wang, Isaac J. Manjarres,
Georgi Djakov, Sven Peter
From: Yunfei Wang <yf.wang@mediatek.com>
Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA and
cause pgtable PA size larger than 32bit.
Since Mediatek IOMMU hardware support at most 35bit PA in pgtable,
so add a quirk to allow the PA of pgtables support up to bit35.
Signed-off-by: Ning Li <ning.li@mediatek.com>
Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
---
drivers/iommu/io-pgtable-arm-v7s.c | 75 ++++++++++++++++++++++--------
include/linux/io-pgtable.h | 15 ++++--
2 files changed, 66 insertions(+), 24 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index be066c1503d3..ba3115fd0f86 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -182,14 +182,8 @@ static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg)
(cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT);
}
-static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
- struct io_pgtable_cfg *cfg)
+static arm_v7s_iopte to_mtk_iopte(phys_addr_t paddr, arm_v7s_iopte pte)
{
- arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
-
- if (!arm_v7s_is_mtk_enabled(cfg))
- return pte;
-
if (paddr & BIT_ULL(32))
pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
if (paddr & BIT_ULL(33))
@@ -199,6 +193,17 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
return pte;
}
+static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
+ struct io_pgtable_cfg *cfg)
+{
+ arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
+
+ if (arm_v7s_is_mtk_enabled(cfg))
+ return to_mtk_iopte(paddr, pte);
+
+ return pte;
+}
+
static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl,
struct io_pgtable_cfg *cfg)
{
@@ -240,10 +245,17 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
dma_addr_t dma;
size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
void *table = NULL;
+ gfp_t gfp_l1;
+
+ /*
+ * ARM_MTK_TTBR_EXT extend the translation table base support larger
+ * memory address.
+ */
+ gfp_l1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
+ GFP_KERNEL : ARM_V7S_TABLE_GFP_DMA;
if (lvl == 1)
- table = (void *)__get_free_pages(
- __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA, get_order(size));
+ table = (void *)__get_free_pages(gfp_l1 | __GFP_ZERO, get_order(size));
else if (lvl == 2)
table = kmem_cache_zalloc(data->l2_tables, gfp);
@@ -251,7 +263,8 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
return NULL;
phys = virt_to_phys(table);
- if (phys != (arm_v7s_iopte)phys) {
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
+ phys >= (1ULL << cfg->oas) : phys != (arm_v7s_iopte)phys) {
/* Doesn't fit in PTE */
dev_err(dev, "Page table does not fit in PTE: %pa", &phys);
goto out_free;
@@ -457,9 +470,14 @@ static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table,
arm_v7s_iopte curr,
struct io_pgtable_cfg *cfg)
{
+ phys_addr_t phys = virt_to_phys(table);
arm_v7s_iopte old, new;
- new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE;
+ new = phys | ARM_V7S_PTE_TYPE_TABLE;
+
+ if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)
+ new = to_mtk_iopte(phys, new);
+
if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
new |= ARM_V7S_ATTR_NS_TABLE;
@@ -779,6 +797,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
void *cookie)
{
struct arm_v7s_io_pgtable *data;
+ slab_flags_t slab_flag;
+ phys_addr_t paddr;
if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
return NULL;
@@ -788,7 +808,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
IO_PGTABLE_QUIRK_NO_PERMS |
- IO_PGTABLE_QUIRK_ARM_MTK_EXT))
+ IO_PGTABLE_QUIRK_ARM_MTK_EXT |
+ IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT))
return NULL;
/* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
@@ -796,15 +817,27 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
!(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
return NULL;
+ if ((cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) &&
+ !arm_v7s_is_mtk_enabled(cfg))
+ return NULL;
+
data = kmalloc(sizeof(*data), GFP_KERNEL);
if (!data)
return NULL;
spin_lock_init(&data->split_lock);
+
+ /*
+ * ARM_MTK_TTBR_EXT extend the translation table base support larger
+ * memory address.
+ */
+ slab_flag = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
+ 0 : ARM_V7S_TABLE_SLAB_FLAGS;
+
data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
ARM_V7S_TABLE_SIZE(2, cfg),
ARM_V7S_TABLE_SIZE(2, cfg),
- ARM_V7S_TABLE_SLAB_FLAGS, NULL);
+ slab_flag, NULL);
if (!data->l2_tables)
goto out_free_data;
@@ -850,12 +883,16 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
wmb();
/* TTBR */
- cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S |
- (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
- ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
- ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
- (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
- ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
+ paddr = virt_to_phys(data->pgd);
+ if (arm_v7s_is_mtk_enabled(cfg))
+ cfg->arm_v7s_cfg.ttbr = paddr | upper_32_bits(paddr);
+ else
+ cfg->arm_v7s_cfg.ttbr = paddr | ARM_V7S_TTBR_S |
+ (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
+ ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
+ ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
+ (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
+ ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
return &data->iop;
out_free_data:
diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
index 86af6f0a00a2..ca98aeadcc80 100644
--- a/include/linux/io-pgtable.h
+++ b/include/linux/io-pgtable.h
@@ -74,17 +74,22 @@ struct io_pgtable_cfg {
* to support up to 35 bits PA where the bit32, bit33 and bit34 are
* encoded in the bit9, bit4 and bit5 of the PTE respectively.
*
+ * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs
+ * extend the translation table base support up to 35 bits PA, the
+ * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT.
+ *
* IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
* for use in the upper half of a split address space.
*
* IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
* attributes set in the TCR for a non-coherent page-table walker.
*/
- #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
- #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
- #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
- #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
- #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
+ #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
+ #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
+ #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
+ #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4)
+ #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
+ #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
unsigned long quirks;
unsigned long pgsize_bitmap;
unsigned int ias;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit
2022-06-30 9:29 ` yf.wang--- via iommu
(?)
@ 2022-06-30 9:29 ` yf.wang--- via iommu
-1 siblings, 0 replies; 23+ messages in thread
From: yf.wang @ 2022-06-30 9:29 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek, Yunfei Wang, Yong Wu
From: Yunfei Wang <yf.wang@mediatek.com>
Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So add
the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level 2
pgtable support at most 35bit PA.
Signed-off-by: Ning Li <ning.li@mediatek.com>
Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index bb9dd92c9898..3b9f4bdb15b7 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -34,7 +34,6 @@
#include <dt-bindings/memory/mtk-memory-port.h>
#define REG_MMU_PT_BASE_ADDR 0x000
-#define MMU_PT_ADDR_MASK GENMASK(31, 7)
#define REG_MMU_INVALIDATE 0x020
#define F_ALL_INVLD 0x2
@@ -138,6 +137,7 @@
/* PM and clock always on. e.g. infra iommu */
#define PM_CLK_AO BIT(15)
#define IFA_IOMMU_PCIE_SUPPORT BIT(16)
+#define PGTABLE_PA_35_EN BIT(17)
#define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
((((pdata)->flags) & (mask)) == (_x))
@@ -596,6 +596,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
.iommu_dev = data->dev,
};
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
+ dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
+
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
dom->cfg.oas = data->enable_4GB ? 33 : 32;
else
@@ -684,8 +687,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
goto err_unlock;
}
bank->m4u_dom = dom;
- writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
- bank->base + REG_MMU_PT_BASE_ADDR);
+ writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
pm_runtime_put(m4udev);
}
@@ -1366,8 +1368,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
- writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
- base + REG_MMU_PT_BASE_ADDR);
+ writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
} while (++i < data->plat_data->banks_num);
/*
@@ -1401,7 +1402,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
static const struct mtk_iommu_plat_data mt6779_data = {
.m4u_plat = M4U_MT6779,
.flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
- MTK_IOMMU_TYPE_MM,
+ MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
.banks_num = 1,
.banks_enable = {true},
--
2.18.0
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit
@ 2022-06-30 9:29 ` yf.wang--- via iommu
0 siblings, 0 replies; 23+ messages in thread
From: yf.wang--- via iommu @ 2022-06-30 9:29 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, linux-kernel, Libo Kang, Yunfei Wang, iommu,
linux-mediatek, Ning Li, linux-arm-kernel
From: Yunfei Wang <yf.wang@mediatek.com>
Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So add
the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level 2
pgtable support at most 35bit PA.
Signed-off-by: Ning Li <ning.li@mediatek.com>
Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index bb9dd92c9898..3b9f4bdb15b7 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -34,7 +34,6 @@
#include <dt-bindings/memory/mtk-memory-port.h>
#define REG_MMU_PT_BASE_ADDR 0x000
-#define MMU_PT_ADDR_MASK GENMASK(31, 7)
#define REG_MMU_INVALIDATE 0x020
#define F_ALL_INVLD 0x2
@@ -138,6 +137,7 @@
/* PM and clock always on. e.g. infra iommu */
#define PM_CLK_AO BIT(15)
#define IFA_IOMMU_PCIE_SUPPORT BIT(16)
+#define PGTABLE_PA_35_EN BIT(17)
#define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
((((pdata)->flags) & (mask)) == (_x))
@@ -596,6 +596,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
.iommu_dev = data->dev,
};
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
+ dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
+
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
dom->cfg.oas = data->enable_4GB ? 33 : 32;
else
@@ -684,8 +687,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
goto err_unlock;
}
bank->m4u_dom = dom;
- writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
- bank->base + REG_MMU_PT_BASE_ADDR);
+ writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
pm_runtime_put(m4udev);
}
@@ -1366,8 +1368,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
- writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
- base + REG_MMU_PT_BASE_ADDR);
+ writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
} while (++i < data->plat_data->banks_num);
/*
@@ -1401,7 +1402,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
static const struct mtk_iommu_plat_data mt6779_data = {
.m4u_plat = M4U_MT6779,
.flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
- MTK_IOMMU_TYPE_MM,
+ MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
.banks_num = 1,
.banks_enable = {true},
--
2.18.0
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit
@ 2022-06-30 9:29 ` yf.wang--- via iommu
0 siblings, 0 replies; 23+ messages in thread
From: yf.wang @ 2022-06-30 9:29 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek, Yunfei Wang, Yong Wu
From: Yunfei Wang <yf.wang@mediatek.com>
Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So add
the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level 2
pgtable support at most 35bit PA.
Signed-off-by: Ning Li <ning.li@mediatek.com>
Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index bb9dd92c9898..3b9f4bdb15b7 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -34,7 +34,6 @@
#include <dt-bindings/memory/mtk-memory-port.h>
#define REG_MMU_PT_BASE_ADDR 0x000
-#define MMU_PT_ADDR_MASK GENMASK(31, 7)
#define REG_MMU_INVALIDATE 0x020
#define F_ALL_INVLD 0x2
@@ -138,6 +137,7 @@
/* PM and clock always on. e.g. infra iommu */
#define PM_CLK_AO BIT(15)
#define IFA_IOMMU_PCIE_SUPPORT BIT(16)
+#define PGTABLE_PA_35_EN BIT(17)
#define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
((((pdata)->flags) & (mask)) == (_x))
@@ -596,6 +596,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
.iommu_dev = data->dev,
};
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
+ dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
+
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
dom->cfg.oas = data->enable_4GB ? 33 : 32;
else
@@ -684,8 +687,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
goto err_unlock;
}
bank->m4u_dom = dom;
- writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
- bank->base + REG_MMU_PT_BASE_ADDR);
+ writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
pm_runtime_put(m4udev);
}
@@ -1366,8 +1368,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
- writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
- base + REG_MMU_PT_BASE_ADDR);
+ writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
} while (++i < data->plat_data->banks_num);
/*
@@ -1401,7 +1402,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
static const struct mtk_iommu_plat_data mt6779_data = {
.m4u_plat = M4U_MT6779,
.flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
- MTK_IOMMU_TYPE_MM,
+ MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
.banks_num = 1,
.banks_enable = {true},
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v12 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to allow pgtable PA up to 35bit
2022-06-30 9:29 ` yf.wang--- via iommu
(?)
@ 2022-06-30 15:26 ` Robin Murphy
-1 siblings, 0 replies; 23+ messages in thread
From: Robin Murphy @ 2022-06-30 15:26 UTC (permalink / raw)
To: yf.wang, Will Deacon, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek, Isaac J. Manjarres, Georgi Djakov,
Sven Peter
On 2022-06-30 10:29, yf.wang@mediatek.com wrote:
> From: Yunfei Wang <yf.wang@mediatek.com>
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA and
> cause pgtable PA size larger than 32bit.
>
> Since Mediatek IOMMU hardware support at most 35bit PA in pgtable,
> so add a quirk to allow the PA of pgtables support up to bit35.
This looks about as clean as it's likely to get now, thanks for persevering.
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Ning Li <ning.li@mediatek.com>
> Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 75 ++++++++++++++++++++++--------
> include/linux/io-pgtable.h | 15 ++++--
> 2 files changed, 66 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index be066c1503d3..ba3115fd0f86 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -182,14 +182,8 @@ static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg)
> (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT);
> }
>
> -static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
> - struct io_pgtable_cfg *cfg)
> +static arm_v7s_iopte to_mtk_iopte(phys_addr_t paddr, arm_v7s_iopte pte)
> {
> - arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
> -
> - if (!arm_v7s_is_mtk_enabled(cfg))
> - return pte;
> -
> if (paddr & BIT_ULL(32))
> pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> if (paddr & BIT_ULL(33))
> @@ -199,6 +193,17 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
> return pte;
> }
>
> +static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
> + struct io_pgtable_cfg *cfg)
> +{
> + arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
> +
> + if (arm_v7s_is_mtk_enabled(cfg))
> + return to_mtk_iopte(paddr, pte);
> +
> + return pte;
> +}
> +
> static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl,
> struct io_pgtable_cfg *cfg)
> {
> @@ -240,10 +245,17 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
> dma_addr_t dma;
> size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
> void *table = NULL;
> + gfp_t gfp_l1;
> +
> + /*
> + * ARM_MTK_TTBR_EXT extend the translation table base support larger
> + * memory address.
> + */
> + gfp_l1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
> + GFP_KERNEL : ARM_V7S_TABLE_GFP_DMA;
>
> if (lvl == 1)
> - table = (void *)__get_free_pages(
> - __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA, get_order(size));
> + table = (void *)__get_free_pages(gfp_l1 | __GFP_ZERO, get_order(size));
> else if (lvl == 2)
> table = kmem_cache_zalloc(data->l2_tables, gfp);
>
> @@ -251,7 +263,8 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
> return NULL;
>
> phys = virt_to_phys(table);
> - if (phys != (arm_v7s_iopte)phys) {
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
> + phys >= (1ULL << cfg->oas) : phys != (arm_v7s_iopte)phys) {
> /* Doesn't fit in PTE */
> dev_err(dev, "Page table does not fit in PTE: %pa", &phys);
> goto out_free;
> @@ -457,9 +470,14 @@ static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table,
> arm_v7s_iopte curr,
> struct io_pgtable_cfg *cfg)
> {
> + phys_addr_t phys = virt_to_phys(table);
> arm_v7s_iopte old, new;
>
> - new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE;
> + new = phys | ARM_V7S_PTE_TYPE_TABLE;
> +
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)
> + new = to_mtk_iopte(phys, new);
> +
> if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
> new |= ARM_V7S_ATTR_NS_TABLE;
>
> @@ -779,6 +797,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> void *cookie)
> {
> struct arm_v7s_io_pgtable *data;
> + slab_flags_t slab_flag;
> + phys_addr_t paddr;
>
> if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
> return NULL;
> @@ -788,7 +808,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
>
> if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
> IO_PGTABLE_QUIRK_NO_PERMS |
> - IO_PGTABLE_QUIRK_ARM_MTK_EXT))
> + IO_PGTABLE_QUIRK_ARM_MTK_EXT |
> + IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT))
> return NULL;
>
> /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
> @@ -796,15 +817,27 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
> return NULL;
>
> + if ((cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) &&
> + !arm_v7s_is_mtk_enabled(cfg))
> + return NULL;
> +
> data = kmalloc(sizeof(*data), GFP_KERNEL);
> if (!data)
> return NULL;
>
> spin_lock_init(&data->split_lock);
> +
> + /*
> + * ARM_MTK_TTBR_EXT extend the translation table base support larger
> + * memory address.
> + */
> + slab_flag = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
> + 0 : ARM_V7S_TABLE_SLAB_FLAGS;
> +
> data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
> ARM_V7S_TABLE_SIZE(2, cfg),
> ARM_V7S_TABLE_SIZE(2, cfg),
> - ARM_V7S_TABLE_SLAB_FLAGS, NULL);
> + slab_flag, NULL);
> if (!data->l2_tables)
> goto out_free_data;
>
> @@ -850,12 +883,16 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> wmb();
>
> /* TTBR */
> - cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S |
> - (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
> - ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
> - ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
> - (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
> - ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
> + paddr = virt_to_phys(data->pgd);
> + if (arm_v7s_is_mtk_enabled(cfg))
> + cfg->arm_v7s_cfg.ttbr = paddr | upper_32_bits(paddr);
> + else
> + cfg->arm_v7s_cfg.ttbr = paddr | ARM_V7S_TTBR_S |
> + (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
> + ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
> + ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
> + (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
> + ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
> return &data->iop;
>
> out_free_data:
> diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
> index 86af6f0a00a2..ca98aeadcc80 100644
> --- a/include/linux/io-pgtable.h
> +++ b/include/linux/io-pgtable.h
> @@ -74,17 +74,22 @@ struct io_pgtable_cfg {
> * to support up to 35 bits PA where the bit32, bit33 and bit34 are
> * encoded in the bit9, bit4 and bit5 of the PTE respectively.
> *
> + * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs
> + * extend the translation table base support up to 35 bits PA, the
> + * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT.
> + *
> * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
> * for use in the upper half of a split address space.
> *
> * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
> * attributes set in the TCR for a non-coherent page-table walker.
> */
> - #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
> - #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
> - #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
> - #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
> - #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
> + #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
> + #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
> + #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
> + #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4)
> + #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
> + #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
> unsigned long quirks;
> unsigned long pgsize_bitmap;
> unsigned int ias;
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to allow pgtable PA up to 35bit
@ 2022-06-30 15:26 ` Robin Murphy
0 siblings, 0 replies; 23+ messages in thread
From: Robin Murphy @ 2022-06-30 15:26 UTC (permalink / raw)
To: yf.wang, Will Deacon, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: Isaac J. Manjarres, wsd_upstream, linux-kernel, Libo Kang, iommu,
linux-mediatek, Ning Li, linux-arm-kernel
On 2022-06-30 10:29, yf.wang@mediatek.com wrote:
> From: Yunfei Wang <yf.wang@mediatek.com>
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA and
> cause pgtable PA size larger than 32bit.
>
> Since Mediatek IOMMU hardware support at most 35bit PA in pgtable,
> so add a quirk to allow the PA of pgtables support up to bit35.
This looks about as clean as it's likely to get now, thanks for persevering.
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Ning Li <ning.li@mediatek.com>
> Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 75 ++++++++++++++++++++++--------
> include/linux/io-pgtable.h | 15 ++++--
> 2 files changed, 66 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index be066c1503d3..ba3115fd0f86 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -182,14 +182,8 @@ static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg)
> (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT);
> }
>
> -static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
> - struct io_pgtable_cfg *cfg)
> +static arm_v7s_iopte to_mtk_iopte(phys_addr_t paddr, arm_v7s_iopte pte)
> {
> - arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
> -
> - if (!arm_v7s_is_mtk_enabled(cfg))
> - return pte;
> -
> if (paddr & BIT_ULL(32))
> pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> if (paddr & BIT_ULL(33))
> @@ -199,6 +193,17 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
> return pte;
> }
>
> +static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
> + struct io_pgtable_cfg *cfg)
> +{
> + arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
> +
> + if (arm_v7s_is_mtk_enabled(cfg))
> + return to_mtk_iopte(paddr, pte);
> +
> + return pte;
> +}
> +
> static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl,
> struct io_pgtable_cfg *cfg)
> {
> @@ -240,10 +245,17 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
> dma_addr_t dma;
> size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
> void *table = NULL;
> + gfp_t gfp_l1;
> +
> + /*
> + * ARM_MTK_TTBR_EXT extend the translation table base support larger
> + * memory address.
> + */
> + gfp_l1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
> + GFP_KERNEL : ARM_V7S_TABLE_GFP_DMA;
>
> if (lvl == 1)
> - table = (void *)__get_free_pages(
> - __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA, get_order(size));
> + table = (void *)__get_free_pages(gfp_l1 | __GFP_ZERO, get_order(size));
> else if (lvl == 2)
> table = kmem_cache_zalloc(data->l2_tables, gfp);
>
> @@ -251,7 +263,8 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
> return NULL;
>
> phys = virt_to_phys(table);
> - if (phys != (arm_v7s_iopte)phys) {
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
> + phys >= (1ULL << cfg->oas) : phys != (arm_v7s_iopte)phys) {
> /* Doesn't fit in PTE */
> dev_err(dev, "Page table does not fit in PTE: %pa", &phys);
> goto out_free;
> @@ -457,9 +470,14 @@ static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table,
> arm_v7s_iopte curr,
> struct io_pgtable_cfg *cfg)
> {
> + phys_addr_t phys = virt_to_phys(table);
> arm_v7s_iopte old, new;
>
> - new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE;
> + new = phys | ARM_V7S_PTE_TYPE_TABLE;
> +
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)
> + new = to_mtk_iopte(phys, new);
> +
> if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
> new |= ARM_V7S_ATTR_NS_TABLE;
>
> @@ -779,6 +797,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> void *cookie)
> {
> struct arm_v7s_io_pgtable *data;
> + slab_flags_t slab_flag;
> + phys_addr_t paddr;
>
> if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
> return NULL;
> @@ -788,7 +808,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
>
> if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
> IO_PGTABLE_QUIRK_NO_PERMS |
> - IO_PGTABLE_QUIRK_ARM_MTK_EXT))
> + IO_PGTABLE_QUIRK_ARM_MTK_EXT |
> + IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT))
> return NULL;
>
> /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
> @@ -796,15 +817,27 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
> return NULL;
>
> + if ((cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) &&
> + !arm_v7s_is_mtk_enabled(cfg))
> + return NULL;
> +
> data = kmalloc(sizeof(*data), GFP_KERNEL);
> if (!data)
> return NULL;
>
> spin_lock_init(&data->split_lock);
> +
> + /*
> + * ARM_MTK_TTBR_EXT extend the translation table base support larger
> + * memory address.
> + */
> + slab_flag = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
> + 0 : ARM_V7S_TABLE_SLAB_FLAGS;
> +
> data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
> ARM_V7S_TABLE_SIZE(2, cfg),
> ARM_V7S_TABLE_SIZE(2, cfg),
> - ARM_V7S_TABLE_SLAB_FLAGS, NULL);
> + slab_flag, NULL);
> if (!data->l2_tables)
> goto out_free_data;
>
> @@ -850,12 +883,16 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> wmb();
>
> /* TTBR */
> - cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S |
> - (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
> - ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
> - ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
> - (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
> - ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
> + paddr = virt_to_phys(data->pgd);
> + if (arm_v7s_is_mtk_enabled(cfg))
> + cfg->arm_v7s_cfg.ttbr = paddr | upper_32_bits(paddr);
> + else
> + cfg->arm_v7s_cfg.ttbr = paddr | ARM_V7S_TTBR_S |
> + (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
> + ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
> + ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
> + (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
> + ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
> return &data->iop;
>
> out_free_data:
> diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
> index 86af6f0a00a2..ca98aeadcc80 100644
> --- a/include/linux/io-pgtable.h
> +++ b/include/linux/io-pgtable.h
> @@ -74,17 +74,22 @@ struct io_pgtable_cfg {
> * to support up to 35 bits PA where the bit32, bit33 and bit34 are
> * encoded in the bit9, bit4 and bit5 of the PTE respectively.
> *
> + * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs
> + * extend the translation table base support up to 35 bits PA, the
> + * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT.
> + *
> * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
> * for use in the upper half of a split address space.
> *
> * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
> * attributes set in the TCR for a non-coherent page-table walker.
> */
> - #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
> - #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
> - #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
> - #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
> - #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
> + #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
> + #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
> + #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
> + #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4)
> + #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
> + #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
> unsigned long quirks;
> unsigned long pgsize_bitmap;
> unsigned int ias;
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to allow pgtable PA up to 35bit
@ 2022-06-30 15:26 ` Robin Murphy
0 siblings, 0 replies; 23+ messages in thread
From: Robin Murphy @ 2022-06-30 15:26 UTC (permalink / raw)
To: yf.wang, Will Deacon, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek, Isaac J. Manjarres, Georgi Djakov,
Sven Peter
On 2022-06-30 10:29, yf.wang@mediatek.com wrote:
> From: Yunfei Wang <yf.wang@mediatek.com>
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA and
> cause pgtable PA size larger than 32bit.
>
> Since Mediatek IOMMU hardware support at most 35bit PA in pgtable,
> so add a quirk to allow the PA of pgtables support up to bit35.
This looks about as clean as it's likely to get now, thanks for persevering.
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Ning Li <ning.li@mediatek.com>
> Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
> ---
> drivers/iommu/io-pgtable-arm-v7s.c | 75 ++++++++++++++++++++++--------
> include/linux/io-pgtable.h | 15 ++++--
> 2 files changed, 66 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
> index be066c1503d3..ba3115fd0f86 100644
> --- a/drivers/iommu/io-pgtable-arm-v7s.c
> +++ b/drivers/iommu/io-pgtable-arm-v7s.c
> @@ -182,14 +182,8 @@ static bool arm_v7s_is_mtk_enabled(struct io_pgtable_cfg *cfg)
> (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_EXT);
> }
>
> -static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
> - struct io_pgtable_cfg *cfg)
> +static arm_v7s_iopte to_mtk_iopte(phys_addr_t paddr, arm_v7s_iopte pte)
> {
> - arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
> -
> - if (!arm_v7s_is_mtk_enabled(cfg))
> - return pte;
> -
> if (paddr & BIT_ULL(32))
> pte |= ARM_V7S_ATTR_MTK_PA_BIT32;
> if (paddr & BIT_ULL(33))
> @@ -199,6 +193,17 @@ static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
> return pte;
> }
>
> +static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
> + struct io_pgtable_cfg *cfg)
> +{
> + arm_v7s_iopte pte = paddr & ARM_V7S_LVL_MASK(lvl);
> +
> + if (arm_v7s_is_mtk_enabled(cfg))
> + return to_mtk_iopte(paddr, pte);
> +
> + return pte;
> +}
> +
> static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl,
> struct io_pgtable_cfg *cfg)
> {
> @@ -240,10 +245,17 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
> dma_addr_t dma;
> size_t size = ARM_V7S_TABLE_SIZE(lvl, cfg);
> void *table = NULL;
> + gfp_t gfp_l1;
> +
> + /*
> + * ARM_MTK_TTBR_EXT extend the translation table base support larger
> + * memory address.
> + */
> + gfp_l1 = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
> + GFP_KERNEL : ARM_V7S_TABLE_GFP_DMA;
>
> if (lvl == 1)
> - table = (void *)__get_free_pages(
> - __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA, get_order(size));
> + table = (void *)__get_free_pages(gfp_l1 | __GFP_ZERO, get_order(size));
> else if (lvl == 2)
> table = kmem_cache_zalloc(data->l2_tables, gfp);
>
> @@ -251,7 +263,8 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
> return NULL;
>
> phys = virt_to_phys(table);
> - if (phys != (arm_v7s_iopte)phys) {
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
> + phys >= (1ULL << cfg->oas) : phys != (arm_v7s_iopte)phys) {
> /* Doesn't fit in PTE */
> dev_err(dev, "Page table does not fit in PTE: %pa", &phys);
> goto out_free;
> @@ -457,9 +470,14 @@ static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table,
> arm_v7s_iopte curr,
> struct io_pgtable_cfg *cfg)
> {
> + phys_addr_t phys = virt_to_phys(table);
> arm_v7s_iopte old, new;
>
> - new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE;
> + new = phys | ARM_V7S_PTE_TYPE_TABLE;
> +
> + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT)
> + new = to_mtk_iopte(phys, new);
> +
> if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
> new |= ARM_V7S_ATTR_NS_TABLE;
>
> @@ -779,6 +797,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> void *cookie)
> {
> struct arm_v7s_io_pgtable *data;
> + slab_flags_t slab_flag;
> + phys_addr_t paddr;
>
> if (cfg->ias > (arm_v7s_is_mtk_enabled(cfg) ? 34 : ARM_V7S_ADDR_BITS))
> return NULL;
> @@ -788,7 +808,8 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
>
> if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS |
> IO_PGTABLE_QUIRK_NO_PERMS |
> - IO_PGTABLE_QUIRK_ARM_MTK_EXT))
> + IO_PGTABLE_QUIRK_ARM_MTK_EXT |
> + IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT))
> return NULL;
>
> /* If ARM_MTK_4GB is enabled, the NO_PERMS is also expected. */
> @@ -796,15 +817,27 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> !(cfg->quirks & IO_PGTABLE_QUIRK_NO_PERMS))
> return NULL;
>
> + if ((cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT) &&
> + !arm_v7s_is_mtk_enabled(cfg))
> + return NULL;
> +
> data = kmalloc(sizeof(*data), GFP_KERNEL);
> if (!data)
> return NULL;
>
> spin_lock_init(&data->split_lock);
> +
> + /*
> + * ARM_MTK_TTBR_EXT extend the translation table base support larger
> + * memory address.
> + */
> + slab_flag = cfg->quirks & IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT ?
> + 0 : ARM_V7S_TABLE_SLAB_FLAGS;
> +
> data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
> ARM_V7S_TABLE_SIZE(2, cfg),
> ARM_V7S_TABLE_SIZE(2, cfg),
> - ARM_V7S_TABLE_SLAB_FLAGS, NULL);
> + slab_flag, NULL);
> if (!data->l2_tables)
> goto out_free_data;
>
> @@ -850,12 +883,16 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
> wmb();
>
> /* TTBR */
> - cfg->arm_v7s_cfg.ttbr = virt_to_phys(data->pgd) | ARM_V7S_TTBR_S |
> - (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
> - ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
> - ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
> - (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
> - ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
> + paddr = virt_to_phys(data->pgd);
> + if (arm_v7s_is_mtk_enabled(cfg))
> + cfg->arm_v7s_cfg.ttbr = paddr | upper_32_bits(paddr);
> + else
> + cfg->arm_v7s_cfg.ttbr = paddr | ARM_V7S_TTBR_S |
> + (cfg->coherent_walk ? (ARM_V7S_TTBR_NOS |
> + ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_WBWA) |
> + ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_WBWA)) :
> + (ARM_V7S_TTBR_IRGN_ATTR(ARM_V7S_RGN_NC) |
> + ARM_V7S_TTBR_ORGN_ATTR(ARM_V7S_RGN_NC)));
> return &data->iop;
>
> out_free_data:
> diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
> index 86af6f0a00a2..ca98aeadcc80 100644
> --- a/include/linux/io-pgtable.h
> +++ b/include/linux/io-pgtable.h
> @@ -74,17 +74,22 @@ struct io_pgtable_cfg {
> * to support up to 35 bits PA where the bit32, bit33 and bit34 are
> * encoded in the bit9, bit4 and bit5 of the PTE respectively.
> *
> + * IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT: (ARM v7s format) MediaTek IOMMUs
> + * extend the translation table base support up to 35 bits PA, the
> + * encoding format is same with IO_PGTABLE_QUIRK_ARM_MTK_EXT.
> + *
> * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table
> * for use in the upper half of a split address space.
> *
> * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the outer-cacheability
> * attributes set in the TCR for a non-coherent page-table walker.
> */
> - #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
> - #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
> - #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
> - #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
> - #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
> + #define IO_PGTABLE_QUIRK_ARM_NS BIT(0)
> + #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1)
> + #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3)
> + #define IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT BIT(4)
> + #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5)
> + #define IO_PGTABLE_QUIRK_ARM_OUTER_WBWA BIT(6)
> unsigned long quirks;
> unsigned long pgsize_bitmap;
> unsigned int ias;
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit
2022-06-30 9:29 ` yf.wang--- via iommu
(?)
@ 2022-06-30 15:27 ` Robin Murphy
-1 siblings, 0 replies; 23+ messages in thread
From: Robin Murphy @ 2022-06-30 15:27 UTC (permalink / raw)
To: yf.wang, Will Deacon, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek
On 2022-06-30 10:29, yf.wang@mediatek.com wrote:
> From: Yunfei Wang <yf.wang@mediatek.com>
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So add
> the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level 2
> pgtable support at most 35bit PA.
FWIW,
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Ning Li <ning.li@mediatek.com>
> Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index bb9dd92c9898..3b9f4bdb15b7 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -34,7 +34,6 @@
> #include <dt-bindings/memory/mtk-memory-port.h>
>
> #define REG_MMU_PT_BASE_ADDR 0x000
> -#define MMU_PT_ADDR_MASK GENMASK(31, 7)
>
> #define REG_MMU_INVALIDATE 0x020
> #define F_ALL_INVLD 0x2
> @@ -138,6 +137,7 @@
> /* PM and clock always on. e.g. infra iommu */
> #define PM_CLK_AO BIT(15)
> #define IFA_IOMMU_PCIE_SUPPORT BIT(16)
> +#define PGTABLE_PA_35_EN BIT(17)
>
> #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
> ((((pdata)->flags) & (mask)) == (_x))
> @@ -596,6 +596,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
> .iommu_dev = data->dev,
> };
>
> + if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
> + dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
> +
> if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
> dom->cfg.oas = data->enable_4GB ? 33 : 32;
> else
> @@ -684,8 +687,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
> goto err_unlock;
> }
> bank->m4u_dom = dom;
> - writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
> - bank->base + REG_MMU_PT_BASE_ADDR);
> + writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
>
> pm_runtime_put(m4udev);
> }
> @@ -1366,8 +1368,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
> writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
> writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
> writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
> - writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
> - base + REG_MMU_PT_BASE_ADDR);
> + writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
> } while (++i < data->plat_data->banks_num);
>
> /*
> @@ -1401,7 +1402,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> static const struct mtk_iommu_plat_data mt6779_data = {
> .m4u_plat = M4U_MT6779,
> .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
> - MTK_IOMMU_TYPE_MM,
> + MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> .banks_num = 1,
> .banks_enable = {true},
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit
@ 2022-06-30 15:27 ` Robin Murphy
0 siblings, 0 replies; 23+ messages in thread
From: Robin Murphy @ 2022-06-30 15:27 UTC (permalink / raw)
To: yf.wang, Will Deacon, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, linux-kernel, Libo Kang, iommu, linux-mediatek,
Ning Li, linux-arm-kernel
On 2022-06-30 10:29, yf.wang@mediatek.com wrote:
> From: Yunfei Wang <yf.wang@mediatek.com>
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So add
> the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level 2
> pgtable support at most 35bit PA.
FWIW,
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Ning Li <ning.li@mediatek.com>
> Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index bb9dd92c9898..3b9f4bdb15b7 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -34,7 +34,6 @@
> #include <dt-bindings/memory/mtk-memory-port.h>
>
> #define REG_MMU_PT_BASE_ADDR 0x000
> -#define MMU_PT_ADDR_MASK GENMASK(31, 7)
>
> #define REG_MMU_INVALIDATE 0x020
> #define F_ALL_INVLD 0x2
> @@ -138,6 +137,7 @@
> /* PM and clock always on. e.g. infra iommu */
> #define PM_CLK_AO BIT(15)
> #define IFA_IOMMU_PCIE_SUPPORT BIT(16)
> +#define PGTABLE_PA_35_EN BIT(17)
>
> #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
> ((((pdata)->flags) & (mask)) == (_x))
> @@ -596,6 +596,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
> .iommu_dev = data->dev,
> };
>
> + if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
> + dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
> +
> if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
> dom->cfg.oas = data->enable_4GB ? 33 : 32;
> else
> @@ -684,8 +687,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
> goto err_unlock;
> }
> bank->m4u_dom = dom;
> - writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
> - bank->base + REG_MMU_PT_BASE_ADDR);
> + writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
>
> pm_runtime_put(m4udev);
> }
> @@ -1366,8 +1368,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
> writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
> writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
> writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
> - writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
> - base + REG_MMU_PT_BASE_ADDR);
> + writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
> } while (++i < data->plat_data->banks_num);
>
> /*
> @@ -1401,7 +1402,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> static const struct mtk_iommu_plat_data mt6779_data = {
> .m4u_plat = M4U_MT6779,
> .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
> - MTK_IOMMU_TYPE_MM,
> + MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> .banks_num = 1,
> .banks_enable = {true},
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit
@ 2022-06-30 15:27 ` Robin Murphy
0 siblings, 0 replies; 23+ messages in thread
From: Robin Murphy @ 2022-06-30 15:27 UTC (permalink / raw)
To: yf.wang, Will Deacon, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek
On 2022-06-30 10:29, yf.wang@mediatek.com wrote:
> From: Yunfei Wang <yf.wang@mediatek.com>
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So add
> the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level 2
> pgtable support at most 35bit PA.
FWIW,
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
> Signed-off-by: Ning Li <ning.li@mediatek.com>
> Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
> ---
> drivers/iommu/mtk_iommu.c | 13 +++++++------
> 1 file changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index bb9dd92c9898..3b9f4bdb15b7 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -34,7 +34,6 @@
> #include <dt-bindings/memory/mtk-memory-port.h>
>
> #define REG_MMU_PT_BASE_ADDR 0x000
> -#define MMU_PT_ADDR_MASK GENMASK(31, 7)
>
> #define REG_MMU_INVALIDATE 0x020
> #define F_ALL_INVLD 0x2
> @@ -138,6 +137,7 @@
> /* PM and clock always on. e.g. infra iommu */
> #define PM_CLK_AO BIT(15)
> #define IFA_IOMMU_PCIE_SUPPORT BIT(16)
> +#define PGTABLE_PA_35_EN BIT(17)
>
> #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
> ((((pdata)->flags) & (mask)) == (_x))
> @@ -596,6 +596,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_domain *dom,
> .iommu_dev = data->dev,
> };
>
> + if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
> + dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
> +
> if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
> dom->cfg.oas = data->enable_4GB ? 33 : 32;
> else
> @@ -684,8 +687,7 @@ static int mtk_iommu_attach_device(struct iommu_domain *domain,
> goto err_unlock;
> }
> bank->m4u_dom = dom;
> - writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
> - bank->base + REG_MMU_PT_BASE_ADDR);
> + writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR);
>
> pm_runtime_put(m4udev);
> }
> @@ -1366,8 +1368,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct device *dev)
> writel_relaxed(reg->int_control[i], base + REG_MMU_INT_CONTROL0);
> writel_relaxed(reg->int_main_control[i], base + REG_MMU_INT_MAIN_CONTROL);
> writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
> - writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
> - base + REG_MMU_PT_BASE_ADDR);
> + writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR);
> } while (++i < data->plat_data->banks_num);
>
> /*
> @@ -1401,7 +1402,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
> static const struct mtk_iommu_plat_data mt6779_data = {
> .m4u_plat = M4U_MT6779,
> .flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
> - MTK_IOMMU_TYPE_MM,
> + MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
> .inv_sel_reg = REG_MMU_INV_SEL_GEN2,
> .banks_num = 1,
> .banks_enable = {true},
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit
2022-06-30 9:29 ` yf.wang--- via iommu
(?)
@ 2022-07-05 1:38 ` Yong Wu
-1 siblings, 0 replies; 23+ messages in thread
From: Yong Wu via iommu @ 2022-07-05 1:38 UTC (permalink / raw)
To: yf.wang, Will Deacon, Robin Murphy, Joerg Roedel, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, linux-kernel, Libo Kang, iommu, linux-mediatek,
Ning Li, linux-arm-kernel
On Thu, 2022-06-30 at 17:29 +0800, yf.wang@mediatek.com wrote:
> From: Yunfei Wang <yf.wang@mediatek.com>
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So
> add
> the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level
> 2
> pgtable support at most 35bit PA.
>
> Signed-off-by: Ning Li <ning.li@mediatek.com>
> Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
Reviewed-by: Yong Wu <yong.wu@mediatek.com>
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit
@ 2022-07-05 1:38 ` Yong Wu
0 siblings, 0 replies; 23+ messages in thread
From: Yong Wu @ 2022-07-05 1:38 UTC (permalink / raw)
To: yf.wang, Will Deacon, Robin Murphy, Joerg Roedel, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek
On Thu, 2022-06-30 at 17:29 +0800, yf.wang@mediatek.com wrote:
> From: Yunfei Wang <yf.wang@mediatek.com>
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So
> add
> the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level
> 2
> pgtable support at most 35bit PA.
>
> Signed-off-by: Ning Li <ning.li@mediatek.com>
> Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
Reviewed-by: Yong Wu <yong.wu@mediatek.com>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit
@ 2022-07-05 1:38 ` Yong Wu
0 siblings, 0 replies; 23+ messages in thread
From: Yong Wu @ 2022-07-05 1:38 UTC (permalink / raw)
To: yf.wang, Will Deacon, Robin Murphy, Joerg Roedel, Miles Chen,
Matthias Brugger
Cc: wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek
On Thu, 2022-06-30 at 17:29 +0800, yf.wang@mediatek.com wrote:
> From: Yunfei Wang <yf.wang@mediatek.com>
>
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So
> add
> the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level
> 2
> pgtable support at most 35bit PA.
>
> Signed-off-by: Ning Li <ning.li@mediatek.com>
> Signed-off-by: Yunfei Wang <yf.wang@mediatek.com>
Reviewed-by: Yong Wu <yong.wu@mediatek.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 0/2] iommu/mediatek: TTBR up to 35bit support
2022-06-30 9:29 ` yf.wang--- via iommu
(?)
@ 2022-07-06 11:50 ` Will Deacon
-1 siblings, 0 replies; 23+ messages in thread
From: Will Deacon @ 2022-07-06 11:50 UTC (permalink / raw)
To: yf.wang
Cc: Robin Murphy, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger, wsd_upstream, Libo Kang, Ning Li,
linux-arm-kernel, iommu, linux-kernel, linux-mediatek
On Thu, Jun 30, 2022 at 05:29:24PM +0800, yf.wang@mediatek.com wrote:
> This patchset adds MediaTek TTBR up to 35bit support for single normal zone.
>
> Changes in v12:
> - Update [PATCH 1/2]: remove GENMASK(31, 7)
> - Update [PATCH 2/2]: remove MMU_PT_ADDR_MASK definition.
For both patches:
Acked-by: Will Deacon <will@kernel.org>
Joerg -- please can you pick these up for 5.20?
Thanks,
Will
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 0/2] iommu/mediatek: TTBR up to 35bit support
@ 2022-07-06 11:50 ` Will Deacon
0 siblings, 0 replies; 23+ messages in thread
From: Will Deacon @ 2022-07-06 11:50 UTC (permalink / raw)
To: yf.wang
Cc: linux-arm-kernel, wsd_upstream, iommu, Libo Kang, linux-kernel,
Miles Chen, linux-mediatek, Ning Li, Matthias Brugger,
Robin Murphy
On Thu, Jun 30, 2022 at 05:29:24PM +0800, yf.wang@mediatek.com wrote:
> This patchset adds MediaTek TTBR up to 35bit support for single normal zone.
>
> Changes in v12:
> - Update [PATCH 1/2]: remove GENMASK(31, 7)
> - Update [PATCH 2/2]: remove MMU_PT_ADDR_MASK definition.
For both patches:
Acked-by: Will Deacon <will@kernel.org>
Joerg -- please can you pick these up for 5.20?
Thanks,
Will
_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 0/2] iommu/mediatek: TTBR up to 35bit support
@ 2022-07-06 11:50 ` Will Deacon
0 siblings, 0 replies; 23+ messages in thread
From: Will Deacon @ 2022-07-06 11:50 UTC (permalink / raw)
To: yf.wang
Cc: Robin Murphy, Joerg Roedel, Yong Wu, Miles Chen,
Matthias Brugger, wsd_upstream, Libo Kang, Ning Li,
linux-arm-kernel, iommu, linux-kernel, linux-mediatek
On Thu, Jun 30, 2022 at 05:29:24PM +0800, yf.wang@mediatek.com wrote:
> This patchset adds MediaTek TTBR up to 35bit support for single normal zone.
>
> Changes in v12:
> - Update [PATCH 1/2]: remove GENMASK(31, 7)
> - Update [PATCH 2/2]: remove MMU_PT_ADDR_MASK definition.
For both patches:
Acked-by: Will Deacon <will@kernel.org>
Joerg -- please can you pick these up for 5.20?
Thanks,
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 0/2] iommu/mediatek: TTBR up to 35bit support
2022-07-06 11:50 ` Will Deacon
@ 2022-07-07 7:43 ` Joerg Roedel
-1 siblings, 0 replies; 23+ messages in thread
From: Joerg Roedel @ 2022-07-07 7:43 UTC (permalink / raw)
To: Will Deacon
Cc: yf.wang, Robin Murphy, Yong Wu, Miles Chen, Matthias Brugger,
wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek
On Wed, Jul 06, 2022 at 12:50:31PM +0100, Will Deacon wrote:
> On Thu, Jun 30, 2022 at 05:29:24PM +0800, yf.wang@mediatek.com wrote:
> > This patchset adds MediaTek TTBR up to 35bit support for single normal zone.
> >
> > Changes in v12:
> > - Update [PATCH 1/2]: remove GENMASK(31, 7)
> > - Update [PATCH 2/2]: remove MMU_PT_ADDR_MASK definition.
>
> For both patches:
>
> Acked-by: Will Deacon <will@kernel.org>
>
> Joerg -- please can you pick these up for 5.20?
Applied to arm/mediatek, thanks.
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v12 0/2] iommu/mediatek: TTBR up to 35bit support
@ 2022-07-07 7:43 ` Joerg Roedel
0 siblings, 0 replies; 23+ messages in thread
From: Joerg Roedel @ 2022-07-07 7:43 UTC (permalink / raw)
To: Will Deacon
Cc: yf.wang, Robin Murphy, Yong Wu, Miles Chen, Matthias Brugger,
wsd_upstream, Libo Kang, Ning Li, linux-arm-kernel, iommu,
linux-kernel, linux-mediatek
On Wed, Jul 06, 2022 at 12:50:31PM +0100, Will Deacon wrote:
> On Thu, Jun 30, 2022 at 05:29:24PM +0800, yf.wang@mediatek.com wrote:
> > This patchset adds MediaTek TTBR up to 35bit support for single normal zone.
> >
> > Changes in v12:
> > - Update [PATCH 1/2]: remove GENMASK(31, 7)
> > - Update [PATCH 2/2]: remove MMU_PT_ADDR_MASK definition.
>
> For both patches:
>
> Acked-by: Will Deacon <will@kernel.org>
>
> Joerg -- please can you pick these up for 5.20?
Applied to arm/mediatek, thanks.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2022-07-07 7:44 UTC | newest]
Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-30 9:29 [PATCH v12 0/2] iommu/mediatek: TTBR up to 35bit support yf.wang
2022-06-30 9:29 ` yf.wang
2022-06-30 9:29 ` yf.wang--- via iommu
2022-06-30 9:29 ` [PATCH v12 1/2] iommu/io-pgtable-arm-v7s: Add a quirk to allow pgtable PA up to 35bit yf.wang
2022-06-30 9:29 ` yf.wang
2022-06-30 9:29 ` yf.wang--- via iommu
2022-06-30 15:26 ` Robin Murphy
2022-06-30 15:26 ` Robin Murphy
2022-06-30 15:26 ` Robin Murphy
2022-06-30 9:29 ` [PATCH v12 2/2] iommu/mediatek: Allow page table " yf.wang
2022-06-30 9:29 ` yf.wang
2022-06-30 9:29 ` yf.wang--- via iommu
2022-06-30 15:27 ` Robin Murphy
2022-06-30 15:27 ` Robin Murphy
2022-06-30 15:27 ` Robin Murphy
2022-07-05 1:38 ` Yong Wu via iommu
2022-07-05 1:38 ` Yong Wu
2022-07-05 1:38 ` Yong Wu
2022-07-06 11:50 ` [PATCH v12 0/2] iommu/mediatek: TTBR up to 35bit support Will Deacon
2022-07-06 11:50 ` Will Deacon
2022-07-06 11:50 ` Will Deacon
2022-07-07 7:43 ` Joerg Roedel
2022-07-07 7:43 ` Joerg Roedel
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