[PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[shenwei.wang]

The LPUART hardware doesn't zero out the parity bit on the received
characters. This behavior won't impact the use cases of CS8 because
the parity bit is the 9th bit which is not currently used by software.
But the parity bit for CS7 must be zeroed out by software in order to
get the correct raw data.

Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
---
changes in v1
- fix the code indent and whitespace issue;

 drivers/tty/serial/fsl_lpuart.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
index 8fe0494d4057b..a8f59fb27c825 100644
--- a/drivers/tty/serial/fsl_lpuart.c
+++ b/drivers/tty/serial/fsl_lpuart.c
@@ -274,6 +274,8 @@ struct lpuart_port {
 	int			rx_dma_rng_buf_len;
 	unsigned int		dma_tx_nents;
 	wait_queue_head_t	dma_wait;
+	bool			is_cs7; /* Set to true when character size is 7 */
+					/* and the parity is enabled		*/
 };

 struct lpuart_soc_data {
@@ -1022,6 +1024,9 @@ static void lpuart32_rxint(struct lpuart_port *sport)
 				flg = TTY_OVERRUN;
 		}

+		if (sport->is_cs7)
+			rx &= 0x7F;
+
 		if (tty_insert_flip_char(port, rx, flg) == 0)
 			sport->port.icount.buf_overrun++;
 	}
@@ -1107,6 +1112,17 @@ static void lpuart_handle_sysrq(struct lpuart_port *sport)
 	}
 }

+static inline int lpuart_tty_insert_flip_string(struct tty_port *port,
+	unsigned char *chars, size_t size, bool is_cs7)
+{
+	int i;
+
+	if (is_cs7)
+		for (i = 0; i < size; i++)
+			chars[i] &= 0x7F;
+	return tty_insert_flip_string(port, chars, size);
+}
+
 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
 {
 	struct tty_port *port = &sport->port.state->port;
@@ -1217,7 +1233,8 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
 	if (ring->head < ring->tail) {
 		count = sport->rx_sgl.length - ring->tail;

-		copied = tty_insert_flip_string(port, ring->buf + ring->tail, count);
+		copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
+					count, sport->is_cs7);
 		if (copied != count)
 			sport->port.icount.buf_overrun++;
 		ring->tail = 0;
@@ -1227,7 +1244,8 @@ static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
 	/* Finally we read data from tail to head */
 	if (ring->tail < ring->head) {
 		count = ring->head - ring->tail;
-		copied = tty_insert_flip_string(port, ring->buf + ring->tail, count);
+		copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
+					count, sport->is_cs7);
 		if (copied != count)
 			sport->port.icount.buf_overrun++;
 		/* Wrap ring->head if needed */
@@ -2066,6 +2084,7 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
 	ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
 	bd = lpuart32_read(&sport->port, UARTBAUD);
 	modem = lpuart32_read(&sport->port, UARTMODIR);
+	sport->is_cs7 = false;
 	/*
 	 * only support CS8 and CS7, and for CS7 must enable PE.
 	 * supported mode:
@@ -2184,6 +2203,9 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
 	lpuart32_write(&sport->port, ctrl, UARTCTRL);
 	/* restore control register */

+	if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
+		sport->is_cs7 = true;
+
 	if (old && sport->lpuart_dma_rx_use) {
 		if (!lpuart_start_rx_dma(sport))
 			rx_dma_timer_init(sport);
--
2.25.1

Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[Greg KH]

On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> The LPUART hardware doesn't zero out the parity bit on the received
> characters. This behavior won't impact the use cases of CS8 because
> the parity bit is the 9th bit which is not currently used by software.
> But the parity bit for CS7 must be zeroed out by software in order to
> get the correct raw data.
> 
> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> ---
> changes in v1
> - fix the code indent and whitespace issue;

Normal patches start numbering at v1 :)

>  drivers/tty/serial/fsl_lpuart.c | 26 ++++++++++++++++++++++++--
>  1 file changed, 24 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c
> index 8fe0494d4057b..a8f59fb27c825 100644
> --- a/drivers/tty/serial/fsl_lpuart.c
> +++ b/drivers/tty/serial/fsl_lpuart.c
> @@ -274,6 +274,8 @@ struct lpuart_port {
>  	int			rx_dma_rng_buf_len;
>  	unsigned int		dma_tx_nents;
>  	wait_queue_head_t	dma_wait;
> +	bool			is_cs7; /* Set to true when character size is 7 */
> +					/* and the parity is enabled		*/
>  };
> 
>  struct lpuart_soc_data {
> @@ -1022,6 +1024,9 @@ static void lpuart32_rxint(struct lpuart_port *sport)
>  				flg = TTY_OVERRUN;
>  		}
> 
> +		if (sport->is_cs7)
> +			rx &= 0x7F;
> +
>  		if (tty_insert_flip_char(port, rx, flg) == 0)
>  			sport->port.icount.buf_overrun++;
>  	}
> @@ -1107,6 +1112,17 @@ static void lpuart_handle_sysrq(struct lpuart_port *sport)
>  	}
>  }
> 
> +static inline int lpuart_tty_insert_flip_string(struct tty_port *port,
> +	unsigned char *chars, size_t size, bool is_cs7)

Why inline?  Don't do that unless it is measurable with and without it,
good compilers will guess this correctly.

thanks,

greg k-h

Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[Greg KH]

On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> The LPUART hardware doesn't zero out the parity bit on the received
> characters. This behavior won't impact the use cases of CS8 because
> the parity bit is the 9th bit which is not currently used by software.
> But the parity bit for CS7 must be zeroed out by software in order to
> get the correct raw data.
> 
> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>

What commit id does this fix?

Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[Greg KH]

On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> The LPUART hardware doesn't zero out the parity bit on the received
> characters. This behavior won't impact the use cases of CS8 because
> the parity bit is the 9th bit which is not currently used by software.
> But the parity bit for CS7 must be zeroed out by software in order to
> get the correct raw data.
> 
> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>

Also, please fix your email client so that your name shows up in the
 From: line.

thanks,

greg k-h

RE: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[Shenwei Wang]

> -----Original Message-----
> From: Greg KH <gregkh@linuxfoundation.org>
> Sent: Thursday, July 14, 2022 9:31 AM
> To: Shenwei Wang <shenwei.wang@nxp.com>
> Cc: linux-serial@vger.kernel.org
> Subject: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7
> mode
> 
> Caution: EXT Email
> 
> On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> > The LPUART hardware doesn't zero out the parity bit on the received
> > characters. This behavior won't impact the use cases of CS8 because
> > the parity bit is the 9th bit which is not currently used by software.
> > But the parity bit for CS7 must be zeroed out by software in order to
> > get the correct raw data.
> >
> > Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> > ---
> > changes in v1
> > - fix the code indent and whitespace issue;
> 
> Normal patches start numbering at v1 :)
> 
> >  drivers/tty/serial/fsl_lpuart.c | 26 ++++++++++++++++++++++++--
> >  1 file changed, 24 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/tty/serial/fsl_lpuart.c
> > b/drivers/tty/serial/fsl_lpuart.c index 8fe0494d4057b..a8f59fb27c825
> > 100644
> > --- a/drivers/tty/serial/fsl_lpuart.c
> > +++ b/drivers/tty/serial/fsl_lpuart.c
> > @@ -274,6 +274,8 @@ struct lpuart_port {
> >       int                     rx_dma_rng_buf_len;
> >       unsigned int            dma_tx_nents;
> >       wait_queue_head_t       dma_wait;
> > +     bool                    is_cs7; /* Set to true when character size is 7 */
> > +                                     /* and the parity is enabled            */
> >  };
> >
> >  struct lpuart_soc_data {
> > @@ -1022,6 +1024,9 @@ static void lpuart32_rxint(struct lpuart_port *sport)
> >                               flg = TTY_OVERRUN;
> >               }
> >
> > +             if (sport->is_cs7)
> > +                     rx &= 0x7F;
> > +
> >               if (tty_insert_flip_char(port, rx, flg) == 0)
> >                       sport->port.icount.buf_overrun++;
> >       }
> > @@ -1107,6 +1112,17 @@ static void lpuart_handle_sysrq(struct lpuart_port
> *sport)
> >       }
> >  }
> >
> > +static inline int lpuart_tty_insert_flip_string(struct tty_port *port,
> > +     unsigned char *chars, size_t size, bool is_cs7)
> 
> Why inline?  Don't do that unless it is measurable with and without it, good
> compilers will guess this correctly.

Agree. The inline is not necessary here. Will fix it in next version.

Thanks,
Shenwei

> thanks,
> 
> greg k-h

RE: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[Shenwei Wang]

> -----Original Message-----
> From: Greg KH <gregkh@linuxfoundation.org>
> Sent: Thursday, July 14, 2022 9:31 AM
> To: Shenwei Wang <shenwei.wang@nxp.com>
> Cc: linux-serial@vger.kernel.org
> Subject: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7
> mode
> 
> Caution: EXT Email
> 
> On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> > The LPUART hardware doesn't zero out the parity bit on the received
> > characters. This behavior won't impact the use cases of CS8 because
> > the parity bit is the 9th bit which is not currently used by software.
> > But the parity bit for CS7 must be zeroed out by software in order to
> > get the correct raw data.
> >
> > Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> 
> What commit id does this fix?

The issue should have been there since the driver was written. As the CS7 mode was rarely used, we didn't notice the problem in the driver before.

Thanks,
Shenwei

Re: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[Greg KH]

On Thu, Jul 14, 2022 at 03:11:35PM +0000, Shenwei Wang wrote:
> 
> 
> > -----Original Message-----
> > From: Greg KH <gregkh@linuxfoundation.org>
> > Sent: Thursday, July 14, 2022 9:31 AM
> > To: Shenwei Wang <shenwei.wang@nxp.com>
> > Cc: linux-serial@vger.kernel.org
> > Subject: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7
> > mode
> > 
> > Caution: EXT Email
> > 
> > On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> > > The LPUART hardware doesn't zero out the parity bit on the received
> > > characters. This behavior won't impact the use cases of CS8 because
> > > the parity bit is the 9th bit which is not currently used by software.
> > > But the parity bit for CS7 must be zeroed out by software in order to
> > > get the correct raw data.
> > >
> > > Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> > 
> > What commit id does this fix?
> 
> The issue should have been there since the driver was written. As the CS7 mode was rarely used, we didn't notice the problem in the driver before.

So should this be backported to older stable kernels?

thanks,

greg k-h

RE: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[Shenwei Wang]

> -----Original Message-----
> From: Greg KH <gregkh@linuxfoundation.org>
> Sent: Thursday, July 14, 2022 10:24 AM
> To: Shenwei Wang <shenwei.wang@nxp.com>
> Cc: linux-serial@vger.kernel.org
> Subject: Re: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7
> mode
> 
> Caution: EXT Email
> 
> On Thu, Jul 14, 2022 at 03:11:35PM +0000, Shenwei Wang wrote:
> >
> >
> > > -----Original Message-----
> > > From: Greg KH <gregkh@linuxfoundation.org>
> > > Sent: Thursday, July 14, 2022 9:31 AM
> > > To: Shenwei Wang <shenwei.wang@nxp.com>
> > > Cc: linux-serial@vger.kernel.org
> > > Subject: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out
> > > parity bit in CS7 mode
> > >
> > > Caution: EXT Email
> > >
> > > On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> > > > The LPUART hardware doesn't zero out the parity bit on the
> > > > received characters. This behavior won't impact the use cases of
> > > > CS8 because the parity bit is the 9th bit which is not currently used by
> software.
> > > > But the parity bit for CS7 must be zeroed out by software in order
> > > > to get the correct raw data.
> > > >
> > > > Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> > >
> > > What commit id does this fix?
> >
> > The issue should have been there since the driver was written. As the CS7
> mode was rarely used, we didn't notice the problem in the driver before.
> 
> So should this be backported to older stable kernels?
> 

Yes, that would be great.

Thanks,
Shenwei

Re: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[Greg KH]

On Thu, Jul 14, 2022 at 03:26:30PM +0000, Shenwei Wang wrote:
> 
> 
> > -----Original Message-----
> > From: Greg KH <gregkh@linuxfoundation.org>
> > Sent: Thursday, July 14, 2022 10:24 AM
> > To: Shenwei Wang <shenwei.wang@nxp.com>
> > Cc: linux-serial@vger.kernel.org
> > Subject: Re: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7
> > mode
> > 
> > Caution: EXT Email
> > 
> > On Thu, Jul 14, 2022 at 03:11:35PM +0000, Shenwei Wang wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Greg KH <gregkh@linuxfoundation.org>
> > > > Sent: Thursday, July 14, 2022 9:31 AM
> > > > To: Shenwei Wang <shenwei.wang@nxp.com>
> > > > Cc: linux-serial@vger.kernel.org
> > > > Subject: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out
> > > > parity bit in CS7 mode
> > > >
> > > > Caution: EXT Email
> > > >
> > > > On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> > > > > The LPUART hardware doesn't zero out the parity bit on the
> > > > > received characters. This behavior won't impact the use cases of
> > > > > CS8 because the parity bit is the 9th bit which is not currently used by
> > software.
> > > > > But the parity bit for CS7 must be zeroed out by software in order
> > > > > to get the correct raw data.
> > > > >
> > > > > Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> > > >
> > > > What commit id does this fix?
> > >
> > > The issue should have been there since the driver was written. As the CS7
> > mode was rarely used, we didn't notice the problem in the driver before.
> > 
> > So should this be backported to older stable kernels?
> > 
> 
> Yes, that would be great.

Great, properly label it as such when you resend this.

thanks,

greg k-h

RE: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[Shenwei Wang]

> -----Original Message-----
> From: Greg KH <gregkh@linuxfoundation.org>
> Sent: Thursday, July 14, 2022 10:31 AM
> To: Shenwei Wang <shenwei.wang@nxp.com>
> Cc: linux-serial@vger.kernel.org
> Subject: Re: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7
> mode
> 
> Caution: EXT Email
> 
> On Thu, Jul 14, 2022 at 03:26:30PM +0000, Shenwei Wang wrote:
> >
> >
> > > -----Original Message-----
> > > From: Greg KH <gregkh@linuxfoundation.org>
> > > Sent: Thursday, July 14, 2022 10:24 AM
> > > To: Shenwei Wang <shenwei.wang@nxp.com>
> > > Cc: linux-serial@vger.kernel.org
> > > Subject: Re: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out
> > > parity bit in CS7 mode
> > >
> > > Caution: EXT Email
> > >
> > > On Thu, Jul 14, 2022 at 03:11:35PM +0000, Shenwei Wang wrote:
> > > >
> > > >
> > > > > -----Original Message-----
> > > > > From: Greg KH <gregkh@linuxfoundation.org>
> > > > > Sent: Thursday, July 14, 2022 9:31 AM
> > > > > To: Shenwei Wang <shenwei.wang@nxp.com>
> > > > > Cc: linux-serial@vger.kernel.org
> > > > > Subject: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out
> > > > > parity bit in CS7 mode
> > > > >
> > > > > Caution: EXT Email
> > > > >
> > > > > On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> > > > > > The LPUART hardware doesn't zero out the parity bit on the
> > > > > > received characters. This behavior won't impact the use cases
> > > > > > of
> > > > > > CS8 because the parity bit is the 9th bit which is not
> > > > > > currently used by
> > > software.
> > > > > > But the parity bit for CS7 must be zeroed out by software in
> > > > > > order to get the correct raw data.
> > > > > >
> > > > > > Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> > > > >
> > > > > What commit id does this fix?
> > > >
> > > > The issue should have been there since the driver was written. As
> > > > the CS7
> > > mode was rarely used, we didn't notice the problem in the driver before.
> > >
> > > So should this be backported to older stable kernels?
> > >
> >
> > Yes, that would be great.
> 
> Great, properly label it as such when you resend this.

This is my first time to handle this kind of label. Can you let me know how to label it for older stable kernels?

Thanks,
Shenwei

> 
> thanks,
> 
> greg k-h

Re: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode

[Greg KH]

On Thu, Jul 14, 2022 at 03:50:24PM +0000, Shenwei Wang wrote:
> 
> 
> > -----Original Message-----
> > From: Greg KH <gregkh@linuxfoundation.org>
> > Sent: Thursday, July 14, 2022 10:31 AM
> > To: Shenwei Wang <shenwei.wang@nxp.com>
> > Cc: linux-serial@vger.kernel.org
> > Subject: Re: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out parity bit in CS7
> > mode
> > 
> > Caution: EXT Email
> > 
> > On Thu, Jul 14, 2022 at 03:26:30PM +0000, Shenwei Wang wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Greg KH <gregkh@linuxfoundation.org>
> > > > Sent: Thursday, July 14, 2022 10:24 AM
> > > > To: Shenwei Wang <shenwei.wang@nxp.com>
> > > > Cc: linux-serial@vger.kernel.org
> > > > Subject: Re: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out
> > > > parity bit in CS7 mode
> > > >
> > > > Caution: EXT Email
> > > >
> > > > On Thu, Jul 14, 2022 at 03:11:35PM +0000, Shenwei Wang wrote:
> > > > >
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Greg KH <gregkh@linuxfoundation.org>
> > > > > > Sent: Thursday, July 14, 2022 9:31 AM
> > > > > > To: Shenwei Wang <shenwei.wang@nxp.com>
> > > > > > Cc: linux-serial@vger.kernel.org
> > > > > > Subject: [EXT] Re: [PATCH V1 1/1] serial: fsl_lpuart: zero out
> > > > > > parity bit in CS7 mode
> > > > > >
> > > > > > Caution: EXT Email
> > > > > >
> > > > > > On Fri, Jul 08, 2022 at 02:58:00PM -0500, shenwei.wang@nxp.com wrote:
> > > > > > > The LPUART hardware doesn't zero out the parity bit on the
> > > > > > > received characters. This behavior won't impact the use cases
> > > > > > > of
> > > > > > > CS8 because the parity bit is the 9th bit which is not
> > > > > > > currently used by
> > > > software.
> > > > > > > But the parity bit for CS7 must be zeroed out by software in
> > > > > > > order to get the correct raw data.
> > > > > > >
> > > > > > > Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> > > > > >
> > > > > > What commit id does this fix?
> > > > >
> > > > > The issue should have been there since the driver was written. As
> > > > > the CS7
> > > > mode was rarely used, we didn't notice the problem in the driver before.
> > > >
> > > > So should this be backported to older stable kernels?
> > > >
> > >
> > > Yes, that would be great.
> > 
> > Great, properly label it as such when you resend this.
> 
> This is my first time to handle this kind of label. Can you let me know how to label it for older stable kernels?

Please read:
    https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html

It should explain it fully, if not, please let me know.

thanks,

greg k-h