* [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff
@ 2022-07-15 20:20 Ville Syrjala
2022-07-15 20:20 ` [Intel-gfx] [PATCH 01/12] drm/i915: Unify VBT version number comments Ville Syrjala
` (13 more replies)
0 siblings, 14 replies; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Bunch of VBT work:
- cleanup of version number comments
- document more bits
- rename a few misnamed things
- warn if any port wants to use the VBT vswing tables
- parse the new DP lane count limit
Ville Syrjälä (12):
drm/i915: Unify VBT version number comments
drm/i915: Add some more VBT version number comments
drm/i915: Properly define the DP redriver VBT bits
drm/i915: Define VBT eDP/DP max lane count bits
drm/i915: Add the VBT LTTPR transparent vs. non-transparent bits
drm/i915: Define VBT max HDMI FRL rate bits
drm/i915: Document the sets of bits in the driver features block
drm/i915: Define more VBT driver features block bits
drm/i915: Define all possible VBT device handles
drm/i915: Rename some VBT bits
drm/i915: WARN if a port should use VBT provided vswing tables
drm/i915: Parse DP/eDP max lane count from VBT
drivers/gpu/drm/i915/display/intel_bios.c | 20 ++
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 13 +-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 333 ++++++++++--------
4 files changed, 222 insertions(+), 145 deletions(-)
--
2.35.1
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 01/12] drm/i915: Unify VBT version number comments
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-07-19 10:25 ` Rodrigo Vivi
2022-07-15 20:20 ` [Intel-gfx] [PATCH 02/12] drm/i915: Add some more " Ville Syrjala
` (12 subsequent siblings)
13 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use a more standard form for the VT version number comments.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 206 ++++++++++--------
1 file changed, 110 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 509b0a419c20..ba328d130991 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -75,6 +75,20 @@ struct bdb_header {
u16 bdb_size;
} __packed;
+/*
+ * BDB version number dependencies are documented as:
+ *
+ * <start>+
+ * indicates the field was introduced in version <start>
+ * and is still valid
+ *
+ * <start>-<end>
+ * indicates the field was introduced in version <start>
+ * and obsoleted in version <end>+1.
+ *
+ * ??? indicates the specific version number is unknown
+ */
+
/*
* There are several types of BIOS data blocks (BDBs), each block has
* an ID and size in the first 3 bytes (ID in first, size in next 2).
@@ -144,12 +158,12 @@ struct bdb_general_features {
/* bits 3 */
u8 disable_smooth_vision:1;
u8 single_dvi:1;
- u8 rotate_180:1; /* 181 */
+ u8 rotate_180:1; /* 181+ */
u8 fdi_rx_polarity_inverted:1;
- u8 vbios_extended_mode:1; /* 160 */
- u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */
- u8 panel_best_fit_timing:1; /* 160 */
- u8 ignore_strap_state:1; /* 160 */
+ u8 vbios_extended_mode:1; /* 160+ */
+ u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160+ */
+ u8 panel_best_fit_timing:1; /* 160+ */
+ u8 ignore_strap_state:1; /* 160+ */
/* bits 4 */
u8 legacy_monitor_detect;
@@ -164,11 +178,11 @@ struct bdb_general_features {
u8 rsvd11:2; /* finish byte */
/* bits 6 */
- u8 tc_hpd_retry_timeout:7; /* 242 */
+ u8 tc_hpd_retry_timeout:7; /* 242+ */
u8 rsvd12:1;
/* bits 7 */
- u8 afc_startup_config:2;/* 249 */
+ u8 afc_startup_config:2; /* 249+ */
u8 rsvd13:6;
} __packed;
@@ -275,27 +289,27 @@ struct bdb_general_features {
#define DVO_PORT_DPC 8
#define DVO_PORT_DPD 9
#define DVO_PORT_DPA 10
-#define DVO_PORT_DPE 11 /* 193 */
-#define DVO_PORT_HDMIE 12 /* 193 */
+#define DVO_PORT_DPE 11 /* 193+ */
+#define DVO_PORT_HDMIE 12 /* 193+ */
#define DVO_PORT_DPF 13 /* N/A */
#define DVO_PORT_HDMIF 14 /* N/A */
-#define DVO_PORT_DPG 15 /* 217 */
-#define DVO_PORT_HDMIG 16 /* 217 */
-#define DVO_PORT_DPH 17 /* 217 */
-#define DVO_PORT_HDMIH 18 /* 217 */
-#define DVO_PORT_DPI 19 /* 217 */
-#define DVO_PORT_HDMII 20 /* 217 */
-#define DVO_PORT_MIPIA 21 /* 171 */
-#define DVO_PORT_MIPIB 22 /* 171 */
-#define DVO_PORT_MIPIC 23 /* 171 */
-#define DVO_PORT_MIPID 24 /* 171 */
+#define DVO_PORT_DPG 15 /* 217+ */
+#define DVO_PORT_HDMIG 16 /* 217+ */
+#define DVO_PORT_DPH 17 /* 217+ */
+#define DVO_PORT_HDMIH 18 /* 217+ */
+#define DVO_PORT_DPI 19 /* 217+ */
+#define DVO_PORT_HDMII 20 /* 217+ */
+#define DVO_PORT_MIPIA 21 /* 171+ */
+#define DVO_PORT_MIPIB 22 /* 171+ */
+#define DVO_PORT_MIPIC 23 /* 171+ */
+#define DVO_PORT_MIPID 24 /* 171+ */
-#define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */
-#define HDMI_MAX_DATA_RATE_297 1 /* 204 */
-#define HDMI_MAX_DATA_RATE_165 2 /* 204 */
-#define HDMI_MAX_DATA_RATE_594 3 /* 249 */
-#define HDMI_MAX_DATA_RATE_340 4 /* 249 */
-#define HDMI_MAX_DATA_RATE_300 5 /* 249 */
+#define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204+ */
+#define HDMI_MAX_DATA_RATE_297 1 /* 204+ */
+#define HDMI_MAX_DATA_RATE_165 2 /* 204+ */
+#define HDMI_MAX_DATA_RATE_594 3 /* 249+ */
+#define HDMI_MAX_DATA_RATE_340 4 /* 249+ */
+#define HDMI_MAX_DATA_RATE_300 5 /* 249+ */
#define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33
@@ -379,19 +393,19 @@ struct child_device_config {
u8 device_id[10]; /* ascii string */
struct {
u8 i2c_speed;
- u8 dp_onboard_redriver; /* 158 */
- u8 dp_ondock_redriver; /* 158 */
- u8 hdmi_level_shifter_value:5; /* 169 */
- u8 hdmi_max_data_rate:3; /* 204 */
- u16 dtd_buf_ptr; /* 161 */
- u8 edidless_efp:1; /* 161 */
- u8 compression_enable:1; /* 198 */
- u8 compression_method_cps:1; /* 198 */
- u8 ganged_edp:1; /* 202 */
+ u8 dp_onboard_redriver; /* 158+ */
+ u8 dp_ondock_redriver; /* 158+ */
+ u8 hdmi_level_shifter_value:5; /* 158+ */
+ u8 hdmi_max_data_rate:3; /* 204+ */
+ u16 dtd_buf_ptr; /* 161+ */
+ u8 edidless_efp:1; /* 161+ */
+ u8 compression_enable:1; /* 198+ */
+ u8 compression_method_cps:1; /* 198+ */
+ u8 ganged_edp:1; /* 202+ */
u8 reserved0:4;
- u8 compression_structure_index:4; /* 198 */
+ u8 compression_structure_index:4; /* 198+ */
u8 reserved1:4;
- u8 slave_port; /* 202 */
+ u8 slave_port; /* 202+ */
u8 reserved2;
} __packed;
} __packed;
@@ -412,16 +426,16 @@ struct child_device_config {
u8 ddc2_pin;
} __packed;
struct {
- u8 efp_routed:1; /* 158 */
- u8 lane_reversal:1; /* 184 */
- u8 lspcon:1; /* 192 */
- u8 iboost:1; /* 196 */
- u8 hpd_invert:1; /* 196 */
- u8 use_vbt_vswing:1; /* 218 */
+ u8 efp_routed:1; /* 158+ */
+ u8 lane_reversal:1; /* 184+ */
+ u8 lspcon:1; /* 192+ */
+ u8 iboost:1; /* 196+ */
+ u8 hpd_invert:1; /* 196+ */
+ u8 use_vbt_vswing:1; /* 218+ */
u8 flag_reserved:2;
- u8 hdmi_support:1; /* 158 */
- u8 dp_support:1; /* 158 */
- u8 tmds_support:1; /* 158 */
+ u8 hdmi_support:1; /* 158+ */
+ u8 dp_support:1; /* 158+ */
+ u8 tmds_support:1; /* 158+ */
u8 support_reserved:5;
u8 aux_channel;
u8 dongle_detect;
@@ -429,7 +443,7 @@ struct child_device_config {
} __packed;
u8 pipe_cap:2;
- u8 sdvo_stall:1; /* 158 */
+ u8 sdvo_stall:1; /* 158+ */
u8 hpd_status:2;
u8 integrated_encoder:1;
u8 capabilities_reserved:2;
@@ -437,21 +451,21 @@ struct child_device_config {
union {
u8 dvo2_wiring;
- u8 mipi_bridge_type; /* 171 */
+ u8 mipi_bridge_type; /* 171+ */
} __packed;
u16 extended_type;
u8 dvo_function;
- u8 dp_usb_type_c:1; /* 195 */
- u8 tbt:1; /* 209 */
- u8 flags2_reserved:2; /* 195 */
- u8 dp_port_trace_length:4; /* 209 */
- u8 dp_gpio_index; /* 195 */
- u16 dp_gpio_pin_num; /* 195 */
- u8 dp_iboost_level:4; /* 196 */
- u8 hdmi_iboost_level:4; /* 196 */
- u8 dp_max_link_rate:3; /* 216/230 GLK+ */
- u8 dp_max_link_rate_reserved:5; /* 216/230 */
+ u8 dp_usb_type_c:1; /* 195+ */
+ u8 tbt:1; /* 209+ */
+ u8 flags2_reserved:2; /* 195+ */
+ u8 dp_port_trace_length:4; /* 209+ */
+ u8 dp_gpio_index; /* 195+ */
+ u16 dp_gpio_pin_num; /* 195+ */
+ u8 dp_iboost_level:4; /* 196+ */
+ u8 hdmi_iboost_level:4; /* 196+ */
+ u8 dp_max_link_rate:3; /* 216+ */
+ u8 dp_max_link_rate_reserved:5; /* 216+ */
} __packed;
struct bdb_general_definitions {
@@ -690,18 +704,18 @@ struct bdb_edp {
u32 sdrrs_msa_timing_delay;
/* ith bit indicates enabled/disabled for (i+1)th panel */
- u16 edp_s3d_feature; /* 162 */
- u16 edp_t3_optimization; /* 165 */
- u64 edp_vswing_preemph; /* 173 */
- u16 fast_link_training; /* 182 */
- u16 dpcd_600h_write_required; /* 185 */
- struct edp_pwm_delays pwm_delays[16]; /* 186 */
- u16 full_link_params_provided; /* 199 */
- struct edp_full_link_params full_link_params[16]; /* 199 */
- u16 apical_enable; /* 203 */
- struct edp_apical_params apical_params[16]; /* 203 */
- u16 edp_fast_link_training_rate[16]; /* 224 */
- u16 edp_max_port_link_rate[16]; /* 244 */
+ u16 edp_s3d_feature; /* 162+ */
+ u16 edp_t3_optimization; /* 165+ */
+ u64 edp_vswing_preemph; /* 173+ */
+ u16 fast_link_training; /* 182+ */
+ u16 dpcd_600h_write_required; /* 185+ */
+ struct edp_pwm_delays pwm_delays[16]; /* 186+ */
+ u16 full_link_params_provided; /* 199+ */
+ struct edp_full_link_params full_link_params[16]; /* 199+ */
+ u16 apical_enable; /* 203+ */
+ struct edp_apical_params apical_params[16]; /* 203+ */
+ u16 edp_fast_link_training_rate[16]; /* 224+ */
+ u16 edp_max_port_link_rate[16]; /* 244+ */
} __packed;
/*
@@ -710,7 +724,7 @@ struct bdb_edp {
struct bdb_lvds_options {
u8 panel_type;
- u8 panel_type2; /* 212 */
+ u8 panel_type2; /* 212+ */
/* LVDS capabilities, stored in a dword */
u8 pfit_mode:2;
u8 pfit_text_mode_enhanced:1;
@@ -733,9 +747,9 @@ struct bdb_lvds_options {
/* LVDS backlight control type bits stored here */
u32 blt_control_type_bits;
- u16 lcdvcc_s0_enable; /* 200 */
- u32 rotation; /* 228 */
- u32 position; /* 240 */
+ u16 lcdvcc_s0_enable; /* 200+ */
+ u32 rotation; /* 228+ */
+ u32 position; /* 240+ */
} __packed;
/*
@@ -756,7 +770,7 @@ struct lvds_lfp_data_ptr {
struct bdb_lvds_lfp_data_ptrs {
u8 lvds_entries;
struct lvds_lfp_data_ptr ptr[16];
- struct lvds_lfp_data_ptr_table panel_name; /* 156-163? */
+ struct lvds_lfp_data_ptr_table panel_name; /* (156-163?)+ */
} __packed;
/*
@@ -808,20 +822,20 @@ struct lvds_lfp_panel_name {
} __packed;
struct lvds_lfp_black_border {
- u8 top; /* 227 */
- u8 bottom; /* 227 */
- u8 left; /* 238 */
- u8 right; /* 238 */
+ u8 top; /* 227+ */
+ u8 bottom; /* 227+ */
+ u8 left; /* 238+ */
+ u8 right; /* 238+ */
} __packed;
struct bdb_lvds_lfp_data_tail {
- struct lvds_lfp_panel_name panel_name[16]; /* 156-163? */
- u16 scaling_enable; /* 187 */
- u8 seamless_drrs_min_refresh_rate[16]; /* 188 */
- u8 pixel_overlap_count[16]; /* 208 */
- struct lvds_lfp_black_border black_border[16]; /* 227 */
- u16 dual_lfp_port_sync_enable; /* 231 */
- u16 gpu_dithering_for_banding_artifacts; /* 245 */
+ struct lvds_lfp_panel_name panel_name[16]; /* (156-163?)+ */
+ u16 scaling_enable; /* 187+ */
+ u8 seamless_drrs_min_refresh_rate[16]; /* 188+ */
+ u8 pixel_overlap_count[16]; /* 208+ */
+ struct lvds_lfp_black_border black_border[16]; /* 227+ */
+ u16 dual_lfp_port_sync_enable; /* 231+ */
+ u16 gpu_dithering_for_banding_artifacts; /* 245+ */
} __packed;
/*
@@ -836,7 +850,7 @@ struct lfp_backlight_data_entry {
u8 active_low_pwm:1;
u8 obsolete1:5;
u16 pwm_freq_hz;
- u8 min_brightness; /* Obsolete from 234+ */
+ u8 min_brightness; /* ???-233 */
u8 obsolete2;
u8 obsolete3;
} __packed;
@@ -859,7 +873,7 @@ struct lfp_brightness_level {
struct bdb_lfp_backlight_data {
u8 entry_size;
struct lfp_backlight_data_entry data[16];
- u8 level[16]; /* Obsolete from 234+ */
+ u8 level[16]; /* ???-233 */
struct lfp_backlight_control_method backlight_control[16];
struct lfp_brightness_level brightness_level[16]; /* 234+ */
struct lfp_brightness_level brightness_min_level[16]; /* 234+ */
@@ -908,11 +922,11 @@ struct bdb_lfp_power {
u16 adb;
u16 lace_enabled_status;
struct aggressiveness_profile_entry aggressiveness[16];
- u16 hobl; /* 232+ */
- u16 vrr_feature_enabled; /* 233+ */
- u16 elp; /* 247+ */
- u16 opst; /* 247+ */
- struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247+ */
+ u16 hobl; /* 232+ */
+ u16 vrr_feature_enabled; /* 233+ */
+ u16 elp; /* 247+ */
+ u16 opst; /* 247+ */
+ struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247+ */
} __packed;
/*
@@ -922,10 +936,10 @@ struct bdb_lfp_power {
#define MAX_MIPI_CONFIGURATIONS 6
struct bdb_mipi_config {
- struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175 */
- struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177 */
- struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS]; /* 186 */
- u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190 */
+ struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175+ */
+ struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177+ */
+ struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS]; /* 186+ */
+ u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190+ */
} __packed;
/*
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 02/12] drm/i915: Add some more VBT version number comments
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
2022-07-15 20:20 ` [Intel-gfx] [PATCH 01/12] drm/i915: Unify VBT version number comments Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-09-02 15:00 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 03/12] drm/i915: Properly define the DP redriver VBT bits Ville Syrjala
` (11 subsequent siblings)
13 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Document the VBT version dependency of several other fields.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 76 +++++++++----------
1 file changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index ba328d130991..e997b8bcc6b8 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -502,25 +502,25 @@ struct bdb_general_definitions {
struct psr_table {
/* Feature bits */
- u8 full_link:1;
- u8 require_aux_to_wakeup:1;
+ u8 full_link:1; /* 165+ */
+ u8 require_aux_to_wakeup:1; /* 165+ */
u8 feature_bits_rsvd:6;
/* Wait times */
- u8 idle_frames:4;
- u8 lines_to_wait:3;
+ u8 idle_frames:4; /* 165+ */
+ u8 lines_to_wait:3; /* 165+ */
u8 wait_times_rsvd:1;
/* TP wake up time in multiple of 100 */
- u16 tp1_wakeup_time;
- u16 tp2_tp3_wakeup_time;
+ u16 tp1_wakeup_time; /* 165+ */
+ u16 tp2_tp3_wakeup_time; /* 165+ */
} __packed;
struct bdb_psr {
struct psr_table psr_table[16];
/* PSR2 TP2/TP3 wakeup time for 16 panels */
- u32 psr2_tp2_tp3_wakeup_time;
+ u32 psr2_tp2_tp3_wakeup_time; /* 226+ */
} __packed;
/*
@@ -562,28 +562,28 @@ struct bdb_driver_features {
u16 tv_hotplug:1;
u16 hdmi_config:2;
- u8 static_display:1;
+ u8 static_display:1; /* 163+ */
u8 reserved2:7;
+
u16 legacy_crt_max_x;
u16 legacy_crt_max_y;
u8 legacy_crt_max_refresh;
u8 hdmi_termination;
- u8 custom_vbt_version;
- /* Driver features data block */
- u16 rmpm_enabled:1;
- u16 s2ddt_enabled:1;
- u16 dpst_enabled:1;
- u16 bltclt_enabled:1;
- u16 adb_enabled:1;
- u16 drrs_enabled:1;
- u16 grs_enabled:1;
- u16 gpmt_enabled:1;
- u16 tbt_enabled:1;
- u16 psr_enabled:1;
- u16 ips_enabled:1;
+ u8 custom_vbt_version; /* 165+ */
+ u16 rmpm_enabled:1; /* 165+ */
+ u16 s2ddt_enabled:1; /* 165+ */
+ u16 dpst_enabled:1; /* 165-227 */
+ u16 bltclt_enabled:1; /* 165+ */
+ u16 adb_enabled:1; /* 165-227 */
+ u16 drrs_enabled:1; /* 165-227 */
+ u16 grs_enabled:1; /* 165+ */
+ u16 gpmt_enabled:1; /* 165+ */
+ u16 tbt_enabled:1; /* 165+ */
+ u16 psr_enabled:1; /* 165-227 */
+ u16 ips_enabled:1; /* 165+ */
u16 reserved3:1;
- u16 dmrrs_enabled:1;
+ u16 dmrrs_enabled:1; /* 174-227 */
u16 reserved4:2;
u16 pc_feature_valid:1;
} __packed;
@@ -671,7 +671,7 @@ struct bdb_sdvo_panel_dtds {
struct edp_fast_link_params {
- u8 rate:4;
+ u8 rate:4; /* ???-223 */
u8 lanes:4;
u8 preemphasis:4;
u8 vswing:4;
@@ -731,7 +731,7 @@ struct bdb_lvds_options {
u8 pfit_gfx_mode_enhanced:1;
u8 pfit_ratio_auto:1;
u8 pixel_dither:1;
- u8 lvds_edid:1;
+ u8 lvds_edid:1; /* ???-240 */
u8 rsvd2:1;
u8 rsvd4;
/* LVDS Panel channel bits stored here */
@@ -745,7 +745,7 @@ struct bdb_lvds_options {
/* LVDS panel type bits stored here */
u32 dps_panel_type_bits;
/* LVDS backlight control type bits stored here */
- u32 blt_control_type_bits;
+ u32 blt_control_type_bits; /* ???-240 */
u16 lcdvcc_s0_enable; /* 200+ */
u32 rotation; /* 228+ */
@@ -888,8 +888,8 @@ struct lfp_power_features {
u8 reserved1:1;
u8 power_conservation_pref:3;
u8 reserved2:1;
- u8 lace_enabled_status:1;
- u8 lace_support:1;
+ u8 lace_enabled_status:1; /* 210+ */
+ u8 lace_support:1; /* 210+ */
u8 als_enable:1;
} __packed;
@@ -909,19 +909,19 @@ struct aggressiveness_profile2_entry {
} __packed;
struct bdb_lfp_power {
- struct lfp_power_features features;
+ struct lfp_power_features features; /* ???-227 */
struct als_data_entry als[5];
- u8 lace_aggressiveness_profile:3;
+ u8 lace_aggressiveness_profile:3; /* 210-227 */
u8 reserved1:5;
- u16 dpst;
- u16 psr;
- u16 drrs;
- u16 lace_support;
- u16 adt;
- u16 dmrrs;
- u16 adb;
- u16 lace_enabled_status;
- struct aggressiveness_profile_entry aggressiveness[16];
+ u16 dpst; /* 228+ */
+ u16 psr; /* 228+ */
+ u16 drrs; /* 228+ */
+ u16 lace_support; /* 228+ */
+ u16 adt; /* 228+ */
+ u16 dmrrs; /* 228+ */
+ u16 adb; /* 228+ */
+ u16 lace_enabled_status; /* 228+ */
+ struct aggressiveness_profile_entry aggressiveness[16]; /* 228+ */
u16 hobl; /* 232+ */
u16 vrr_feature_enabled; /* 233+ */
u16 elp; /* 247+ */
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 03/12] drm/i915: Properly define the DP redriver VBT bits
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
2022-07-15 20:20 ` [Intel-gfx] [PATCH 01/12] drm/i915: Unify VBT version number comments Ville Syrjala
2022-07-15 20:20 ` [Intel-gfx] [PATCH 02/12] drm/i915: Add some more " Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-09-02 14:45 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 04/12] drm/i915: Define VBT eDP/DP max lane count bits Ville Syrjala
` (10 subsequent siblings)
13 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Split the DP redriver bytes into bitfields.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 16 +++++++++++-----
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index e997b8bcc6b8..a88c5ef51cd8 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -393,8 +393,14 @@ struct child_device_config {
u8 device_id[10]; /* ascii string */
struct {
u8 i2c_speed;
- u8 dp_onboard_redriver; /* 158+ */
- u8 dp_ondock_redriver; /* 158+ */
+ u8 dp_onboard_redriver_preemph:3; /* 158+ */
+ u8 dp_onboard_redriver_vswing:3; /* 158+ */
+ u8 dp_onboard_redriver_present:1; /* 158+ */
+ u8 reserved0:1;
+ u8 dp_ondock_redriver_preemph:3; /* 158+ */
+ u8 dp_ondock_redriver_vswing:3; /* 158+ */
+ u8 dp_ondock_redriver_present:1; /* 158+ */
+ u8 reserved1:1;
u8 hdmi_level_shifter_value:5; /* 158+ */
u8 hdmi_max_data_rate:3; /* 204+ */
u16 dtd_buf_ptr; /* 161+ */
@@ -402,11 +408,11 @@ struct child_device_config {
u8 compression_enable:1; /* 198+ */
u8 compression_method_cps:1; /* 198+ */
u8 ganged_edp:1; /* 202+ */
- u8 reserved0:4;
+ u8 reserved2:4;
u8 compression_structure_index:4; /* 198+ */
- u8 reserved1:4;
+ u8 reserved3:4;
u8 slave_port; /* 202+ */
- u8 reserved2;
+ u8 reserved4;
} __packed;
} __packed;
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 04/12] drm/i915: Define VBT eDP/DP max lane count bits
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
` (2 preceding siblings ...)
2022-07-15 20:20 ` [Intel-gfx] [PATCH 03/12] drm/i915: Properly define the DP redriver VBT bits Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-09-02 14:36 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 05/12] drm/i915: Add the VBT LTTPR transparent vs. non-transparent bits Ville Syrjala
` (9 subsequent siblings)
13 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Since version 244 the VBT can llimt the eDP/DP max lane count.
Add the bits.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index a88c5ef51cd8..d583bb085913 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -438,7 +438,7 @@ struct child_device_config {
u8 iboost:1; /* 196+ */
u8 hpd_invert:1; /* 196+ */
u8 use_vbt_vswing:1; /* 218+ */
- u8 flag_reserved:2;
+ u8 dp_max_lane_count:2; /* 244+ */
u8 hdmi_support:1; /* 158+ */
u8 dp_support:1; /* 158+ */
u8 tmds_support:1; /* 158+ */
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 05/12] drm/i915: Add the VBT LTTPR transparent vs. non-transparent bits
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
` (3 preceding siblings ...)
2022-07-15 20:20 ` [Intel-gfx] [PATCH 04/12] drm/i915: Define VBT eDP/DP max lane count bits Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-09-02 14:47 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 06/12] drm/i915: Define VBT max HDMI FRL rate bits Ville Syrjala
` (8 subsequent siblings)
13 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
VBT gained a bit to indicate whether LTTPRs should use transparent
or non-transparent mode. Dunno if we should actually look at this...
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index d583bb085913..b15e29509fac 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -408,7 +408,8 @@ struct child_device_config {
u8 compression_enable:1; /* 198+ */
u8 compression_method_cps:1; /* 198+ */
u8 ganged_edp:1; /* 202+ */
- u8 reserved2:4;
+ u8 lttpr_non_transparent:1; /* 235+ */
+ u8 reserved2:3;
u8 compression_structure_index:4; /* 198+ */
u8 reserved3:4;
u8 slave_port; /* 202+ */
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 06/12] drm/i915: Define VBT max HDMI FRL rate bits
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
` (4 preceding siblings ...)
2022-07-15 20:20 ` [Intel-gfx] [PATCH 05/12] drm/i915: Add the VBT LTTPR transparent vs. non-transparent bits Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-09-02 14:48 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 07/12] drm/i915: Document the sets of bits in the driver features block Ville Syrjala
` (7 subsequent siblings)
13 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The VBT gained some bits to inidicate the max FRL rate for
HDMI 2.1, define them.
These just outright replaced the slave_port bits for ganged eDP.
Apparently that feature was never actually used so someone decided
that reusing the bits is fine. Although the actual ganged eDP
enable bit was still left defined elsewhere for some reason.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index b15e29509fac..8bdb533b5304 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -412,8 +412,10 @@ struct child_device_config {
u8 reserved2:3;
u8 compression_structure_index:4; /* 198+ */
u8 reserved3:4;
- u8 slave_port; /* 202+ */
- u8 reserved4;
+ u8 hdmi_max_frl_rate:4; /* 237+ */
+ u8 hdmi_max_frl_rate_valid:1; /* 237+ */
+ u8 reserved4:3; /* 237+ */
+ u8 reserved5;
} __packed;
} __packed;
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 07/12] drm/i915: Document the sets of bits in the driver features block
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
` (5 preceding siblings ...)
2022-07-15 20:20 ` [Intel-gfx] [PATCH 06/12] drm/i915: Define VBT max HDMI FRL rate bits Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-09-02 14:05 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 08/12] drm/i915: Define more VBT driver features block bits Ville Syrjala
` (6 subsequent siblings)
13 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a few comment documenting the sets of bits in the driver
features block. Might make it a bit easier to check against
the spec.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 8bdb533b5304..c04937aa75b2 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -542,6 +542,7 @@ struct bdb_psr {
#define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3
struct bdb_driver_features {
+ /* Driver bits */
u8 boot_dev_algorithm:1;
u8 block_display_switch:1;
u8 allow_display_switch:1;
@@ -556,6 +557,7 @@ struct bdb_driver_features {
u8 boot_mode_bpp;
u8 boot_mode_refresh;
+ /* Extended Driver Bits 1 */
u16 enable_lfp_primary:1;
u16 selective_mode_pruning:1;
u16 dual_frequency:1;
@@ -571,6 +573,7 @@ struct bdb_driver_features {
u16 tv_hotplug:1;
u16 hdmi_config:2;
+ /* Driver Flags 1 */
u8 static_display:1; /* 163+ */
u8 reserved2:7;
@@ -578,8 +581,12 @@ struct bdb_driver_features {
u16 legacy_crt_max_y;
u8 legacy_crt_max_refresh;
+ /* Extended Driver Bits 2 */
u8 hdmi_termination;
+
u8 custom_vbt_version; /* 165+ */
+
+ /* Driver Feature Flags */
u16 rmpm_enabled:1; /* 165+ */
u16 s2ddt_enabled:1; /* 165+ */
u16 dpst_enabled:1; /* 165-227 */
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 08/12] drm/i915: Define more VBT driver features block bits
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
` (6 preceding siblings ...)
2022-07-15 20:20 ` [Intel-gfx] [PATCH 07/12] drm/i915: Document the sets of bits in the driver features block Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-09-02 14:09 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 09/12] drm/i915: Define all possible VBT device handles Ville Syrjala
` (5 subsequent siblings)
13 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Define some additoonal bits in the driver features VBT block.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index c04937aa75b2..2feba1e69a6d 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -575,14 +575,19 @@ struct bdb_driver_features {
/* Driver Flags 1 */
u8 static_display:1; /* 163+ */
- u8 reserved2:7;
+ u8 embedded_platform:1; /* 163+ */
+ u8 display_subsystem_enable:1; /* 163+ */
+ u8 reserved0:5;
u16 legacy_crt_max_x;
u16 legacy_crt_max_y;
u8 legacy_crt_max_refresh;
/* Extended Driver Bits 2 */
- u8 hdmi_termination;
+ u8 hdmi_termination:1;
+ u8 cea861d_hdmi_support:1;
+ u8 self_refresh_enable:1;
+ u8 reserved1:5;
u8 custom_vbt_version; /* 165+ */
@@ -598,9 +603,10 @@ struct bdb_driver_features {
u16 tbt_enabled:1; /* 165+ */
u16 psr_enabled:1; /* 165-227 */
u16 ips_enabled:1; /* 165+ */
- u16 reserved3:1;
+ u16 dpfs_enabled:1; /* 165+ */
u16 dmrrs_enabled:1; /* 174-227 */
- u16 reserved4:2;
+ u16 adt_enabled:1; /* ???-228 */
+ u16 hpd_wake:1; /* 201-240 */
u16 pc_feature_valid:1;
} __packed;
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 09/12] drm/i915: Define all possible VBT device handles
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
` (7 preceding siblings ...)
2022-07-15 20:20 ` [Intel-gfx] [PATCH 08/12] drm/i915: Define more VBT driver features block bits Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-09-02 14:13 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 10/12] drm/i915: Rename some VBT bits Ville Syrjala
` (4 subsequent siblings)
13 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We already have LFP1 and LFP2 device handles define. Just
add all the rest as well.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 2feba1e69a6d..f56c869e106f 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -197,6 +197,15 @@ struct bdb_general_features {
#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
/* Device handle */
+#define DEVICE_HANDLE_CRT 0x0001
+#define DEVICE_HANDLE_EFP1 0x0004
+#define DEVICE_HANDLE_EFP2 0x0040
+#define DEVICE_HANDLE_EFP3 0x0020
+#define DEVICE_HANDLE_EFP4 0x0010 /* 194+ */
+#define DEVICE_HANDLE_EFP5 0x0002 /* 215+ */
+#define DEVICE_HANDLE_EFP6 0x0001 /* 217+ */
+#define DEVICE_HANDLE_EFP7 0x0100 /* 217+ */
+#define DEVICE_HANDLE_EFP8 0x0200 /* 217+ */
#define DEVICE_HANDLE_LFP1 0x0008
#define DEVICE_HANDLE_LFP2 0x0080
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 10/12] drm/i915: Rename some VBT bits
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
` (8 preceding siblings ...)
2022-07-15 20:20 ` [Intel-gfx] [PATCH 09/12] drm/i915: Define all possible VBT device handles Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-09-02 14:15 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 11/12] drm/i915: WARN if a port should use VBT provided vswing tables Ville Syrjala
` (3 subsequent siblings)
13 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The allow vs. block display switch bits are named rather
inconsistently. Fix it up.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index f56c869e106f..62183c6bdc10 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -553,8 +553,8 @@ struct bdb_psr {
struct bdb_driver_features {
/* Driver bits */
u8 boot_dev_algorithm:1;
- u8 block_display_switch:1;
- u8 allow_display_switch:1;
+ u8 allow_display_switch_dvd:1;
+ u8 allow_display_switch_dos:1;
u8 hotplug_dvo:1;
u8 dual_view_zoom:1;
u8 int15h_hook:1;
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 11/12] drm/i915: WARN if a port should use VBT provided vswing tables
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
` (9 preceding siblings ...)
2022-07-15 20:20 ` [Intel-gfx] [PATCH 10/12] drm/i915: Rename some VBT bits Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-07-19 10:31 ` Rodrigo Vivi
2022-09-02 14:01 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 12/12] drm/i915: Parse DP/eDP max lane count from VBT Ville Syrjala
` (2 subsequent siblings)
13 siblings, 2 replies; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We don't parse the VBT vswing/preemphassis tables at all currently.
Let's WARN if a port wants to use them so we get a heads up that
whether we really need to implement this stuff or not. My
current stash contains no VBTs with this bit set.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 51dde5bfd956..cd86b65055ef 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2661,6 +2661,10 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
return;
}
+ drm_WARN(&i915->drm, child->use_vbt_vswing,
+ "Port %c asks to use VBT vswing/preemph tables\n",
+ port_name(port));
+
if (i915->vbt.ports[port]) {
drm_dbg_kms(&i915->drm,
"More than one child device for port %c in VBT, using the first.\n",
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] [PATCH 12/12] drm/i915: Parse DP/eDP max lane count from VBT
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
` (10 preceding siblings ...)
2022-07-15 20:20 ` [Intel-gfx] [PATCH 11/12] drm/i915: WARN if a port should use VBT provided vswing tables Ville Syrjala
@ 2022-07-15 20:20 ` Ville Syrjala
2022-07-19 10:39 ` Rodrigo Vivi
2022-07-16 18:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: More VBT stuff Patchwork
2022-07-16 21:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjala @ 2022-07-15 20:20 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Limit the DP lane count based on the new VBT DP/eDP max
lane count field.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/display/intel_bios.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++++++-
3 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index cd86b65055ef..d8063c329b3a 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2489,6 +2489,14 @@ static int _intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *de
return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate);
}
+static int _intel_bios_dp_max_lane_count(const struct intel_bios_encoder_data *devdata)
+{
+ if (!devdata || devdata->i915->vbt.version < 244)
+ return 0;
+
+ return devdata->child.dp_max_lane_count + 1;
+}
+
static void sanitize_device_type(struct intel_bios_encoder_data *devdata,
enum port port)
{
@@ -3674,6 +3682,14 @@ int intel_bios_dp_max_link_rate(struct intel_encoder *encoder)
return _intel_bios_dp_max_link_rate(devdata);
}
+int intel_bios_dp_max_lane_count(struct intel_encoder *encoder)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
+
+ return _intel_bios_dp_max_lane_count(devdata);
+}
+
int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index e47582b0de0a..e375405a7828 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -258,6 +258,7 @@ bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
int intel_bios_max_tmds_clock(struct intel_encoder *encoder);
int intel_bios_hdmi_level_shift(struct intel_encoder *encoder);
int intel_bios_dp_max_link_rate(struct intel_encoder *encoder);
+int intel_bios_dp_max_lane_count(struct intel_encoder *encoder);
int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder);
bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, enum port port);
bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 32292c0be2bd..0370c4c105dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -286,11 +286,22 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
}
+static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
+{
+ int vbt_max_lanes = intel_bios_dp_max_lane_count(&dig_port->base);
+ int max_lanes = dig_port->max_lanes;
+
+ if (vbt_max_lanes)
+ max_lanes = min(max_lanes, vbt_max_lanes);
+
+ return max_lanes;
+}
+
/* Theoretical max between source and sink */
static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
{
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- int source_max = dig_port->max_lanes;
+ int source_max = intel_dp_max_source_lane_count(dig_port);
int sink_max = intel_dp->max_sink_lane_count;
int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
--
2.35.1
^ permalink raw reply related [flat|nested] 32+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: More VBT stuff
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
` (11 preceding siblings ...)
2022-07-15 20:20 ` [Intel-gfx] [PATCH 12/12] drm/i915: Parse DP/eDP max lane count from VBT Ville Syrjala
@ 2022-07-16 18:13 ` Patchwork
2022-07-16 21:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-07-16 18:13 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 10909 bytes --]
== Series Details ==
Series: drm/i915: More VBT stuff
URL : https://patchwork.freedesktop.org/series/106399/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11900 -> Patchwork_106399v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/index.html
Participating hosts (43 -> 41)
------------------------------
Additional (2): fi-rkl-11600 bat-jsl-3
Missing (4): fi-hsw-4770 fi-bxt-dsi fi-icl-u2 fi-cfl-guc
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_106399v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3:
- {bat-dg2-9}: [DMESG-WARN][1] ([i915#5763]) -> [FAIL][2] +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-dp-3.html
Known issues
------------
Here are the changes found in Patchwork_106399v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@gem_lmem_swapping@basic.html
* igt@gem_tiled_pread_basic:
- fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#3282])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600: NOTRUN -> [SKIP][6] ([i915#3012])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510: [PASS][7] -> [DMESG-FAIL][8] ([i915#4528])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/fi-pnv-d510/igt@i915_selftest@live@requests.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-pnv-d510/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-rkl-11600: NOTRUN -> [INCOMPLETE][9] ([i915#5982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-snb-2600: NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-snb-2600/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-rkl-11600: NOTRUN -> [SKIP][11] ([fdo#111827]) +7 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- fi-rkl-11600: NOTRUN -> [SKIP][12] ([i915#4103])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-rkl-11600: NOTRUN -> [SKIP][13] ([fdo#109285] / [i915#4098])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_page_flip:
- fi-rkl-11600: NOTRUN -> [SKIP][14] ([i915#1072]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@kms_psr@primary_page_flip.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-rkl-11600: NOTRUN -> [SKIP][15] ([i915#3555] / [i915#4098])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-read:
- fi-rkl-11600: NOTRUN -> [SKIP][16] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-userptr:
- fi-rkl-11600: NOTRUN -> [SKIP][17] ([fdo#109295] / [i915#3301] / [i915#3708])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-rkl-11600/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-pnv-d510: NOTRUN -> [FAIL][18] ([fdo#109271] / [i915#2403] / [i915#4312])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-pnv-d510/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-adlm-1}: [DMESG-WARN][19] ([i915#2867]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@client:
- {bat-dg2-9}: [DMESG-WARN][21] ([i915#5763]) -> [PASS][22] +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/bat-dg2-9/igt@i915_selftest@live@client.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/bat-dg2-9/igt@i915_selftest@live@client.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [DMESG-FAIL][23] ([i915#4494] / [i915#4957]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
- fi-snb-2600: [INCOMPLETE][25] ([i915#3921]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@hugepages:
- {bat-rpls-1}: [DMESG-WARN][27] ([i915#5278]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/bat-rpls-1/igt@i915_selftest@live@hugepages.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/bat-rpls-1/igt@i915_selftest@live@hugepages.html
* igt@i915_selftest@live@reset:
- {bat-rpls-1}: [DMESG-FAIL][29] ([i915#4983]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/bat-rpls-1/igt@i915_selftest@live@reset.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/bat-rpls-1/igt@i915_selftest@live@reset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
[i915#6297]: https://gitlab.freedesktop.org/drm/intel/issues/6297
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
Build changes
-------------
* Linux: CI_DRM_11900 -> Patchwork_106399v1
CI-20190529: 20190529
CI_DRM_11900: 5218ea24682b8edb1d629323dce5c88a44e225b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6585: 1b15ce5ec4cb6693daa9dff042e32f675ba8af76 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_106399v1: 5218ea24682b8edb1d629323dce5c88a44e225b0 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
7b84a56ef69b drm/i915: Parse DP/eDP max lane count from VBT
4d73142f950f drm/i915: WARN if a port should use VBT provided vswing tables
838297f73186 drm/i915: Rename some VBT bits
0994c64ed75c drm/i915: Define all possible VBT device handles
c9af7f7edfc2 drm/i915: Define more VBT driver features block bits
f1a14545870e drm/i915: Document the sets of bits in the driver features block
888001e15ca6 drm/i915: Define VBT max HDMI FRL rate bits
feeda9627a2e drm/i915: Add the VBT LTTPR transparent vs. non-transparent bits
7753f63437f0 drm/i915: Define VBT eDP/DP max lane count bits
43a576d7e1b8 drm/i915: Properly define the DP redriver VBT bits
85fc8c9af61f drm/i915: Add some more VBT version number comments
e8586cba9b1a drm/i915: Unify VBT version number comments
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/index.html
[-- Attachment #2: Type: text/html, Size: 11974 bytes --]
^ permalink raw reply [flat|nested] 32+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: More VBT stuff
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
` (12 preceding siblings ...)
2022-07-16 18:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: More VBT stuff Patchwork
@ 2022-07-16 21:50 ` Patchwork
13 siblings, 0 replies; 32+ messages in thread
From: Patchwork @ 2022-07-16 21:50 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 37321 bytes --]
== Series Details ==
Series: drm/i915: More VBT stuff
URL : https://patchwork.freedesktop.org/series/106399/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11900_full -> Patchwork_106399v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (12 -> 12)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_106399v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][1] ([i915#4991])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-apl7/igt@gem_create@create-massive.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [PASS][2] -> [FAIL][3] ([i915#6268])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-tglb7/igt@gem_ctx_exec@basic-nohangcheck.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-tglb8/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-kbl: [PASS][4] -> [DMESG-WARN][5] ([i915#180]) +9 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-kbl4/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_ctx_persistence@engines-hang@bcs0:
- shard-skl: NOTRUN -> [SKIP][6] ([fdo#109271]) +80 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl10/igt@gem_ctx_persistence@engines-hang@bcs0.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#4525])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb3/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-glk2/igt@gem_exec_fair@basic-pace@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-glk5/igt@gem_exec_fair@basic-pace@rcs0.html
- shard-iclb: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-iclb6/igt@gem_exec_fair@basic-pace@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb2/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb2/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl10/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@verify:
- shard-apl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +2 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-apl6/igt@gem_lmem_swapping@verify.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: NOTRUN -> [FAIL][19] ([i915#454])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_suspend@fence-restore-untiled:
- shard-skl: [PASS][20] -> [INCOMPLETE][21] ([i915#4817] / [i915#4939])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-skl4/igt@i915_suspend@fence-restore-untiled.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl7/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3886]) +3 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@kms_ccs@pipe-c-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#3886]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-apl4/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3886]) +5 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl9/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-hpd-for-each-pipe:
- shard-kbl: NOTRUN -> [SKIP][25] ([fdo#109271] / [fdo#111827]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@kms_chamelium@dp-hpd-for-each-pipe.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +12 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-apl7/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
- shard-skl: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +5 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl9/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html
* igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1:
- shard-skl: [PASS][28] -> [INCOMPLETE][29] ([i915#4939])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-skl7/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl10/igt@kms_cursor_crc@cursor-suspend@pipe-b-edp-1.html
* igt@kms_cursor_edge_walk@top-edge@pipe-a-hdmi-a-1-256x256:
- shard-glk: [PASS][30] -> [DMESG-FAIL][31] ([i915#118])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-glk9/igt@kms_cursor_edge_walk@top-edge@pipe-a-hdmi-a-1-256x256.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-glk8/igt@kms_cursor_edge_walk@top-edge@pipe-a-hdmi-a-1-256x256.html
* igt@kms_cursor_legacy@flip-vs-cursor@toggle:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#2346]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl5/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][34] -> [FAIL][35] ([i915#79])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [PASS][36] -> [FAIL][37] ([i915#2122])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl5/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
- shard-glk: [PASS][38] -> [FAIL][39] ([i915#79])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl: NOTRUN -> [DMESG-WARN][40] ([i915#180]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-apl6/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#2672]) +5 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][42] ([i915#3555]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
- shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271]) +148 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-apl7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render.html
* igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1:
- shard-kbl: [PASS][44] -> [FAIL][45] ([i915#1188]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-kbl4/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl6/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][46] ([i915#265])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][47] ([fdo#108145] / [i915#265])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][48] ([fdo#108145] / [i915#265])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-apl4/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][49] -> [FAIL][50] ([fdo#108145] / [i915#265]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][51] -> [SKIP][52] ([i915#5176]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-iclb5/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-a-edp-1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-kbl: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#658])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-skl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#658]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl10/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][55] -> [SKIP][56] ([fdo#109441]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb5/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#2437])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-apl7/igt@kms_writeback@writeback-check-output.html
* igt@prime_nv_pcopy@test2:
- shard-kbl: NOTRUN -> [SKIP][58] ([fdo#109271]) +33 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@prime_nv_pcopy@test2.html
* igt@sysfs_clients@busy:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2994]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-apl4/igt@sysfs_clients@busy.html
* igt@sysfs_clients@pidname:
- shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#2994])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl9/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [DMESG-WARN][61] ([i915#180]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-kbl7/igt@gem_eio@in-flight-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@gem_eio@in-flight-suspend.html
* igt@gem_eio@kms:
- {shard-tglu}: [INCOMPLETE][63] ([i915#5182]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-tglu-8/igt@gem_eio@kms.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-tglu-1/igt@gem_eio@kms.html
* igt@gem_eio@unwedge-stress:
- {shard-rkl}: [TIMEOUT][65] ([i915#3063]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@gem_eio@unwedge-stress.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-5/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-iclb: [SKIP][67] ([i915#4525]) -> [PASS][68] +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-iclb6/igt@gem_exec_balancer@parallel-keep-submit-fence.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb2/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_endless@dispatch@bcs0:
- shard-tglb: [INCOMPLETE][69] ([i915#3778]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-tglb5/igt@gem_exec_endless@dispatch@bcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-tglb1/igt@gem_exec_endless@dispatch@bcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][71] ([i915#2846]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-glk6/igt@gem_exec_fair@basic-deadline.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-glk9/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-tglu}: [FAIL][73] ([i915#2842]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-tglu-5/igt@gem_exec_fair@basic-none-share@rcs0.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-tglu-3/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [FAIL][75] ([i915#2842]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-gtt-cpu:
- {shard-rkl}: [SKIP][77] ([i915#3281]) -> [PASS][78] +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@gem_exec_reloc@basic-gtt-cpu.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-cpu.html
* igt@gem_mmap_gtt@coherency:
- {shard-rkl}: [SKIP][79] ([fdo#111656]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@gem_mmap_gtt@coherency.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-5/igt@gem_mmap_gtt@coherency.html
* igt@gem_readwrite@read-write:
- {shard-rkl}: [SKIP][81] ([i915#3282]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@gem_readwrite@read-write.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-5/igt@gem_readwrite@read-write.html
* igt@gen9_exec_parse@basic-rejected:
- {shard-rkl}: [SKIP][83] ([i915#2527]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-1/igt@gen9_exec_parse@basic-rejected.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-5/igt@gen9_exec_parse@basic-rejected.html
* igt@i915_hangman@engine-engine-error@bcs0:
- {shard-rkl}: [SKIP][85] ([i915#6258]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-5/igt@i915_hangman@engine-engine-error@bcs0.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-1/igt@i915_hangman@engine-engine-error@bcs0.html
* igt@i915_pm_rpm@cursor:
- {shard-rkl}: [SKIP][87] ([i915#1849]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@i915_pm_rpm@cursor.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-6/igt@i915_pm_rpm@cursor.html
* igt@i915_pm_rpm@modeset-lpsp:
- {shard-rkl}: [SKIP][89] ([i915#1397]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@i915_pm_rpm@modeset-lpsp.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp.html
* igt@i915_suspend@debugfs-reader:
- shard-apl: [DMESG-WARN][91] ([i915#180]) -> [PASS][92] +5 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-apl3/igt@i915_suspend@debugfs-reader.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-apl3/igt@i915_suspend@debugfs-reader.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][93] ([i915#72]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
- shard-glk: [FAIL][95] ([i915#2346]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled:
- {shard-rkl}: [SKIP][97] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][98] +5 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled.html
* igt@kms_fbcon_fbt@psr-suspend:
- {shard-rkl}: [SKIP][99] ([fdo#110189] / [i915#3955]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [FAIL][101] ([i915#79]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-hdmi-a1:
- shard-glk: [FAIL][103] ([i915#2122]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-glk1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-hdmi-a1.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-glk1/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-hdmi-a1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [FAIL][105] ([i915#2122]) -> [PASS][106] +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-skl2/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- {shard-rkl}: [SKIP][107] ([i915#1849] / [i915#4098]) -> [PASS][108] +13 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-kbl: [FAIL][109] ([i915#1188]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-kbl1/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl1/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- {shard-rkl}: [SKIP][111] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][112] +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- {shard-rkl}: [SKIP][113] ([i915#1849] / [i915#3558] / [i915#4070]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@kms_plane_multiple@atomic-pipe-b-tiling-none.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-6/igt@kms_plane_multiple@atomic-pipe-b-tiling-none.html
* igt@kms_psr@primary_render:
- {shard-rkl}: [SKIP][115] ([i915#1072]) -> [PASS][116] +2 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@kms_psr@primary_render.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-6/igt@kms_psr@primary_render.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][117] ([fdo#109441]) -> [PASS][118] +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- {shard-rkl}: [SKIP][119] ([i915#5461]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_vblank@pipe-a-wait-forked-busy-hang:
- {shard-rkl}: [SKIP][121] ([i915#1845] / [i915#4098]) -> [PASS][122] +14 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-6/igt@kms_vblank@pipe-a-wait-forked-busy-hang.html
* igt@perf@polling-small-buf:
- {shard-rkl}: [FAIL][123] ([i915#1722]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-rkl-2/igt@perf@polling-small-buf.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-rkl-6/igt@perf@polling-small-buf.html
- shard-skl: [FAIL][125] ([i915#1722]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-skl5/igt@perf@polling-small-buf.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl7/igt@perf@polling-small-buf.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [FAIL][127] ([i915#6117]) -> [SKIP][128] ([i915#4525])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-iclb4/igt@gem_exec_balancer@parallel-ordering.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb7/igt@gem_exec_balancer@parallel-ordering.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][129] ([i915#658]) -> [SKIP][130] ([i915#2920])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-iclb6/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: [SKIP][131] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][132] ([i915#5939])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-iclb6/igt@kms_psr2_su@page_flip-p010.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html
* igt@nouveau_crc@pipe-d-source-rg:
- shard-skl: [SKIP][133] ([fdo#109271] / [i915#1888]) -> [SKIP][134] ([fdo#109271])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-skl2/igt@nouveau_crc@pipe-d-source-rg.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl4/igt@nouveau_crc@pipe-d-source-rg.html
* igt@runner@aborted:
- shard-skl: ([FAIL][135], [FAIL][136]) ([i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][137], [FAIL][138]) ([i915#2029] / [i915#3002] / [i915#4312] / [i915#5257])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-skl10/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-skl10/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl5/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-skl6/igt@runner@aborted.html
- shard-kbl: ([FAIL][139], [FAIL][140], [FAIL][141]) ([i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-kbl1/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-kbl6/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11900/shard-kbl7/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl4/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl4/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl6/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/shard-kbl7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#160]: https://gitlab.freedesktop.org/drm/intel/issues/160
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3778]: https://gitlab.freedesktop.org/drm/intel/issues/3778
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941
[i915#4972]: https://gitlab.freedesktop.org/drm/intel/issues/4972
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5182]: https://gitlab.freedesktop.org/drm/intel/issues/5182
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6375]: https://gitlab.freedesktop.org/drm/intel/issues/6375
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11900 -> Patchwork_106399v1
CI-20190529: 20190529
CI_DRM_11900: 5218ea24682b8edb1d629323dce5c88a44e225b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6585: 1b15ce5ec4cb6693daa9dff042e32f675ba8af76 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_106399v1: 5218ea24682b8edb1d629323dce5c88a44e225b0 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106399v1/index.html
[-- Attachment #2: Type: text/html, Size: 41882 bytes --]
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 01/12] drm/i915: Unify VBT version number comments
2022-07-15 20:20 ` [Intel-gfx] [PATCH 01/12] drm/i915: Unify VBT version number comments Ville Syrjala
@ 2022-07-19 10:25 ` Rodrigo Vivi
2022-09-01 9:24 ` Ville Syrjälä
0 siblings, 1 reply; 32+ messages in thread
From: Rodrigo Vivi @ 2022-07-19 10:25 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Jul 15, 2022 at 11:20:33PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use a more standard form for the VT version number comments.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 206 ++++++++++--------
> 1 file changed, 110 insertions(+), 96 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 509b0a419c20..ba328d130991 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -75,6 +75,20 @@ struct bdb_header {
> u16 bdb_size;
> } __packed;
>
> +/*
> + * BDB version number dependencies are documented as:
> + *
> + * <start>+
> + * indicates the field was introduced in version <start>
> + * and is still valid
> + *
> + * <start>-<end>
> + * indicates the field was introduced in version <start>
> + * and obsoleted in version <end>+1.
> + *
> + * ??? indicates the specific version number is unknown
> + */
> +
> /*
> * There are several types of BIOS data blocks (BDBs), each block has
> * an ID and size in the first 3 bytes (ID in first, size in next 2).
> @@ -144,12 +158,12 @@ struct bdb_general_features {
> /* bits 3 */
> u8 disable_smooth_vision:1;
> u8 single_dvi:1;
> - u8 rotate_180:1; /* 181 */
> + u8 rotate_180:1; /* 181+ */
> u8 fdi_rx_polarity_inverted:1;
> - u8 vbios_extended_mode:1; /* 160 */
> - u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */
> - u8 panel_best_fit_timing:1; /* 160 */
> - u8 ignore_strap_state:1; /* 160 */
> + u8 vbios_extended_mode:1; /* 160+ */
> + u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160+ */
> + u8 panel_best_fit_timing:1; /* 160+ */
> + u8 ignore_strap_state:1; /* 160+ */
>
> /* bits 4 */
> u8 legacy_monitor_detect;
> @@ -164,11 +178,11 @@ struct bdb_general_features {
> u8 rsvd11:2; /* finish byte */
>
> /* bits 6 */
> - u8 tc_hpd_retry_timeout:7; /* 242 */
> + u8 tc_hpd_retry_timeout:7; /* 242+ */
> u8 rsvd12:1;
>
> /* bits 7 */
> - u8 afc_startup_config:2;/* 249 */
> + u8 afc_startup_config:2; /* 249+ */
> u8 rsvd13:6;
> } __packed;
>
> @@ -275,27 +289,27 @@ struct bdb_general_features {
> #define DVO_PORT_DPC 8
> #define DVO_PORT_DPD 9
> #define DVO_PORT_DPA 10
> -#define DVO_PORT_DPE 11 /* 193 */
> -#define DVO_PORT_HDMIE 12 /* 193 */
> +#define DVO_PORT_DPE 11 /* 193+ */
> +#define DVO_PORT_HDMIE 12 /* 193+ */
> #define DVO_PORT_DPF 13 /* N/A */
> #define DVO_PORT_HDMIF 14 /* N/A */
> -#define DVO_PORT_DPG 15 /* 217 */
> -#define DVO_PORT_HDMIG 16 /* 217 */
> -#define DVO_PORT_DPH 17 /* 217 */
> -#define DVO_PORT_HDMIH 18 /* 217 */
> -#define DVO_PORT_DPI 19 /* 217 */
> -#define DVO_PORT_HDMII 20 /* 217 */
> -#define DVO_PORT_MIPIA 21 /* 171 */
> -#define DVO_PORT_MIPIB 22 /* 171 */
> -#define DVO_PORT_MIPIC 23 /* 171 */
> -#define DVO_PORT_MIPID 24 /* 171 */
> +#define DVO_PORT_DPG 15 /* 217+ */
> +#define DVO_PORT_HDMIG 16 /* 217+ */
> +#define DVO_PORT_DPH 17 /* 217+ */
> +#define DVO_PORT_HDMIH 18 /* 217+ */
> +#define DVO_PORT_DPI 19 /* 217+ */
> +#define DVO_PORT_HDMII 20 /* 217+ */
> +#define DVO_PORT_MIPIA 21 /* 171+ */
> +#define DVO_PORT_MIPIB 22 /* 171+ */
> +#define DVO_PORT_MIPIC 23 /* 171+ */
> +#define DVO_PORT_MIPID 24 /* 171+ */
>
> -#define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */
> -#define HDMI_MAX_DATA_RATE_297 1 /* 204 */
> -#define HDMI_MAX_DATA_RATE_165 2 /* 204 */
> -#define HDMI_MAX_DATA_RATE_594 3 /* 249 */
> -#define HDMI_MAX_DATA_RATE_340 4 /* 249 */
> -#define HDMI_MAX_DATA_RATE_300 5 /* 249 */
> +#define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204+ */
> +#define HDMI_MAX_DATA_RATE_297 1 /* 204+ */
> +#define HDMI_MAX_DATA_RATE_165 2 /* 204+ */
> +#define HDMI_MAX_DATA_RATE_594 3 /* 249+ */
> +#define HDMI_MAX_DATA_RATE_340 4 /* 249+ */
> +#define HDMI_MAX_DATA_RATE_300 5 /* 249+ */
>
> #define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33
>
> @@ -379,19 +393,19 @@ struct child_device_config {
> u8 device_id[10]; /* ascii string */
> struct {
> u8 i2c_speed;
> - u8 dp_onboard_redriver; /* 158 */
> - u8 dp_ondock_redriver; /* 158 */
> - u8 hdmi_level_shifter_value:5; /* 169 */
> - u8 hdmi_max_data_rate:3; /* 204 */
> - u16 dtd_buf_ptr; /* 161 */
> - u8 edidless_efp:1; /* 161 */
> - u8 compression_enable:1; /* 198 */
> - u8 compression_method_cps:1; /* 198 */
> - u8 ganged_edp:1; /* 202 */
> + u8 dp_onboard_redriver; /* 158+ */
> + u8 dp_ondock_redriver; /* 158+ */
> + u8 hdmi_level_shifter_value:5; /* 158+ */
> + u8 hdmi_max_data_rate:3; /* 204+ */
> + u16 dtd_buf_ptr; /* 161+ */
> + u8 edidless_efp:1; /* 161+ */
> + u8 compression_enable:1; /* 198+ */
> + u8 compression_method_cps:1; /* 198+ */
> + u8 ganged_edp:1; /* 202+ */
> u8 reserved0:4;
> - u8 compression_structure_index:4; /* 198 */
> + u8 compression_structure_index:4; /* 198+ */
> u8 reserved1:4;
> - u8 slave_port; /* 202 */
> + u8 slave_port; /* 202+ */
> u8 reserved2;
> } __packed;
> } __packed;
> @@ -412,16 +426,16 @@ struct child_device_config {
> u8 ddc2_pin;
> } __packed;
> struct {
> - u8 efp_routed:1; /* 158 */
> - u8 lane_reversal:1; /* 184 */
> - u8 lspcon:1; /* 192 */
> - u8 iboost:1; /* 196 */
> - u8 hpd_invert:1; /* 196 */
> - u8 use_vbt_vswing:1; /* 218 */
> + u8 efp_routed:1; /* 158+ */
> + u8 lane_reversal:1; /* 184+ */
> + u8 lspcon:1; /* 192+ */
> + u8 iboost:1; /* 196+ */
> + u8 hpd_invert:1; /* 196+ */
> + u8 use_vbt_vswing:1; /* 218+ */
> u8 flag_reserved:2;
> - u8 hdmi_support:1; /* 158 */
> - u8 dp_support:1; /* 158 */
> - u8 tmds_support:1; /* 158 */
> + u8 hdmi_support:1; /* 158+ */
> + u8 dp_support:1; /* 158+ */
> + u8 tmds_support:1; /* 158+ */
> u8 support_reserved:5;
> u8 aux_channel;
> u8 dongle_detect;
> @@ -429,7 +443,7 @@ struct child_device_config {
> } __packed;
>
> u8 pipe_cap:2;
> - u8 sdvo_stall:1; /* 158 */
> + u8 sdvo_stall:1; /* 158+ */
> u8 hpd_status:2;
> u8 integrated_encoder:1;
> u8 capabilities_reserved:2;
> @@ -437,21 +451,21 @@ struct child_device_config {
>
> union {
> u8 dvo2_wiring;
> - u8 mipi_bridge_type; /* 171 */
> + u8 mipi_bridge_type; /* 171+ */
> } __packed;
>
> u16 extended_type;
> u8 dvo_function;
> - u8 dp_usb_type_c:1; /* 195 */
> - u8 tbt:1; /* 209 */
> - u8 flags2_reserved:2; /* 195 */
> - u8 dp_port_trace_length:4; /* 209 */
> - u8 dp_gpio_index; /* 195 */
> - u16 dp_gpio_pin_num; /* 195 */
> - u8 dp_iboost_level:4; /* 196 */
> - u8 hdmi_iboost_level:4; /* 196 */
> - u8 dp_max_link_rate:3; /* 216/230 GLK+ */
> - u8 dp_max_link_rate_reserved:5; /* 216/230 */
any idea about this 230 and the GLK mention?
but anyway the 216+ includes the 230, so it looks okay.
for everything else I just relied on what was already in the code
and didn't check the VBT itself, but feel free to use:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> + u8 dp_usb_type_c:1; /* 195+ */
> + u8 tbt:1; /* 209+ */
> + u8 flags2_reserved:2; /* 195+ */
> + u8 dp_port_trace_length:4; /* 209+ */
> + u8 dp_gpio_index; /* 195+ */
> + u16 dp_gpio_pin_num; /* 195+ */
> + u8 dp_iboost_level:4; /* 196+ */
> + u8 hdmi_iboost_level:4; /* 196+ */
> + u8 dp_max_link_rate:3; /* 216+ */
> + u8 dp_max_link_rate_reserved:5; /* 216+ */
> } __packed;
>
> struct bdb_general_definitions {
> @@ -690,18 +704,18 @@ struct bdb_edp {
> u32 sdrrs_msa_timing_delay;
>
> /* ith bit indicates enabled/disabled for (i+1)th panel */
> - u16 edp_s3d_feature; /* 162 */
> - u16 edp_t3_optimization; /* 165 */
> - u64 edp_vswing_preemph; /* 173 */
> - u16 fast_link_training; /* 182 */
> - u16 dpcd_600h_write_required; /* 185 */
> - struct edp_pwm_delays pwm_delays[16]; /* 186 */
> - u16 full_link_params_provided; /* 199 */
> - struct edp_full_link_params full_link_params[16]; /* 199 */
> - u16 apical_enable; /* 203 */
> - struct edp_apical_params apical_params[16]; /* 203 */
> - u16 edp_fast_link_training_rate[16]; /* 224 */
> - u16 edp_max_port_link_rate[16]; /* 244 */
> + u16 edp_s3d_feature; /* 162+ */
> + u16 edp_t3_optimization; /* 165+ */
> + u64 edp_vswing_preemph; /* 173+ */
> + u16 fast_link_training; /* 182+ */
> + u16 dpcd_600h_write_required; /* 185+ */
> + struct edp_pwm_delays pwm_delays[16]; /* 186+ */
> + u16 full_link_params_provided; /* 199+ */
> + struct edp_full_link_params full_link_params[16]; /* 199+ */
> + u16 apical_enable; /* 203+ */
> + struct edp_apical_params apical_params[16]; /* 203+ */
> + u16 edp_fast_link_training_rate[16]; /* 224+ */
> + u16 edp_max_port_link_rate[16]; /* 244+ */
> } __packed;
>
> /*
> @@ -710,7 +724,7 @@ struct bdb_edp {
>
> struct bdb_lvds_options {
> u8 panel_type;
> - u8 panel_type2; /* 212 */
> + u8 panel_type2; /* 212+ */
> /* LVDS capabilities, stored in a dword */
> u8 pfit_mode:2;
> u8 pfit_text_mode_enhanced:1;
> @@ -733,9 +747,9 @@ struct bdb_lvds_options {
> /* LVDS backlight control type bits stored here */
> u32 blt_control_type_bits;
>
> - u16 lcdvcc_s0_enable; /* 200 */
> - u32 rotation; /* 228 */
> - u32 position; /* 240 */
> + u16 lcdvcc_s0_enable; /* 200+ */
> + u32 rotation; /* 228+ */
> + u32 position; /* 240+ */
> } __packed;
>
> /*
> @@ -756,7 +770,7 @@ struct lvds_lfp_data_ptr {
> struct bdb_lvds_lfp_data_ptrs {
> u8 lvds_entries;
> struct lvds_lfp_data_ptr ptr[16];
> - struct lvds_lfp_data_ptr_table panel_name; /* 156-163? */
> + struct lvds_lfp_data_ptr_table panel_name; /* (156-163?)+ */
> } __packed;
>
> /*
> @@ -808,20 +822,20 @@ struct lvds_lfp_panel_name {
> } __packed;
>
> struct lvds_lfp_black_border {
> - u8 top; /* 227 */
> - u8 bottom; /* 227 */
> - u8 left; /* 238 */
> - u8 right; /* 238 */
> + u8 top; /* 227+ */
> + u8 bottom; /* 227+ */
> + u8 left; /* 238+ */
> + u8 right; /* 238+ */
> } __packed;
>
> struct bdb_lvds_lfp_data_tail {
> - struct lvds_lfp_panel_name panel_name[16]; /* 156-163? */
> - u16 scaling_enable; /* 187 */
> - u8 seamless_drrs_min_refresh_rate[16]; /* 188 */
> - u8 pixel_overlap_count[16]; /* 208 */
> - struct lvds_lfp_black_border black_border[16]; /* 227 */
> - u16 dual_lfp_port_sync_enable; /* 231 */
> - u16 gpu_dithering_for_banding_artifacts; /* 245 */
> + struct lvds_lfp_panel_name panel_name[16]; /* (156-163?)+ */
> + u16 scaling_enable; /* 187+ */
> + u8 seamless_drrs_min_refresh_rate[16]; /* 188+ */
> + u8 pixel_overlap_count[16]; /* 208+ */
> + struct lvds_lfp_black_border black_border[16]; /* 227+ */
> + u16 dual_lfp_port_sync_enable; /* 231+ */
> + u16 gpu_dithering_for_banding_artifacts; /* 245+ */
> } __packed;
>
> /*
> @@ -836,7 +850,7 @@ struct lfp_backlight_data_entry {
> u8 active_low_pwm:1;
> u8 obsolete1:5;
> u16 pwm_freq_hz;
> - u8 min_brightness; /* Obsolete from 234+ */
> + u8 min_brightness; /* ???-233 */
> u8 obsolete2;
> u8 obsolete3;
> } __packed;
> @@ -859,7 +873,7 @@ struct lfp_brightness_level {
> struct bdb_lfp_backlight_data {
> u8 entry_size;
> struct lfp_backlight_data_entry data[16];
> - u8 level[16]; /* Obsolete from 234+ */
> + u8 level[16]; /* ???-233 */
> struct lfp_backlight_control_method backlight_control[16];
> struct lfp_brightness_level brightness_level[16]; /* 234+ */
> struct lfp_brightness_level brightness_min_level[16]; /* 234+ */
> @@ -908,11 +922,11 @@ struct bdb_lfp_power {
> u16 adb;
> u16 lace_enabled_status;
> struct aggressiveness_profile_entry aggressiveness[16];
> - u16 hobl; /* 232+ */
> - u16 vrr_feature_enabled; /* 233+ */
> - u16 elp; /* 247+ */
> - u16 opst; /* 247+ */
> - struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247+ */
> + u16 hobl; /* 232+ */
> + u16 vrr_feature_enabled; /* 233+ */
> + u16 elp; /* 247+ */
> + u16 opst; /* 247+ */
> + struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247+ */
> } __packed;
>
> /*
> @@ -922,10 +936,10 @@ struct bdb_lfp_power {
> #define MAX_MIPI_CONFIGURATIONS 6
>
> struct bdb_mipi_config {
> - struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175 */
> - struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177 */
> - struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS]; /* 186 */
> - u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190 */
> + struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175+ */
> + struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177+ */
> + struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS]; /* 186+ */
> + u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190+ */
> } __packed;
>
> /*
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 11/12] drm/i915: WARN if a port should use VBT provided vswing tables
2022-07-15 20:20 ` [Intel-gfx] [PATCH 11/12] drm/i915: WARN if a port should use VBT provided vswing tables Ville Syrjala
@ 2022-07-19 10:31 ` Rodrigo Vivi
2022-09-01 9:24 ` Ville Syrjälä
2022-09-02 14:01 ` Jani Nikula
1 sibling, 1 reply; 32+ messages in thread
From: Rodrigo Vivi @ 2022-07-19 10:31 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Jul 15, 2022 at 11:20:43PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We don't parse the VBT vswing/preemphassis tables at all currently.
> Let's WARN if a port wants to use them so we get a heads up that
> whether we really need to implement this stuff or not. My
> current stash contains no VBTs with this bit set.
let's unlock a new can of worms?! :)
I believe this deserves a /* XXX: comment with the code in case
someone else finds this warns first and doesn't use the git blame
anyways
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 51dde5bfd956..cd86b65055ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2661,6 +2661,10 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
> return;
> }
>
> + drm_WARN(&i915->drm, child->use_vbt_vswing,
> + "Port %c asks to use VBT vswing/preemph tables\n",
> + port_name(port));
> +
> if (i915->vbt.ports[port]) {
> drm_dbg_kms(&i915->drm,
> "More than one child device for port %c in VBT, using the first.\n",
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 12/12] drm/i915: Parse DP/eDP max lane count from VBT
2022-07-15 20:20 ` [Intel-gfx] [PATCH 12/12] drm/i915: Parse DP/eDP max lane count from VBT Ville Syrjala
@ 2022-07-19 10:39 ` Rodrigo Vivi
2022-09-01 9:25 ` Ville Syrjälä
0 siblings, 1 reply; 32+ messages in thread
From: Rodrigo Vivi @ 2022-07-19 10:39 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Fri, Jul 15, 2022 at 11:20:44PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Limit the DP lane count based on the new VBT DP/eDP max
> lane count field.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 16 ++++++++++++++++
> drivers/gpu/drm/i915/display/intel_bios.h | 1 +
> drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++++++-
> 3 files changed, 29 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index cd86b65055ef..d8063c329b3a 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2489,6 +2489,14 @@ static int _intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *de
> return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate);
> }
>
> +static int _intel_bios_dp_max_lane_count(const struct intel_bios_encoder_data *devdata)
> +{
> + if (!devdata || devdata->i915->vbt.version < 244)
> + return 0;
> +
> + return devdata->child.dp_max_lane_count + 1;
> +}
> +
> static void sanitize_device_type(struct intel_bios_encoder_data *devdata,
> enum port port)
> {
> @@ -3674,6 +3682,14 @@ int intel_bios_dp_max_link_rate(struct intel_encoder *encoder)
> return _intel_bios_dp_max_link_rate(devdata);
> }
>
> +int intel_bios_dp_max_lane_count(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
> +
> + return _intel_bios_dp_max_lane_count(devdata);
> +}
do we really need 2 functions here since this one is small and we don't have any
bit switches and all?!
or do you plan to reuse this anywhere else later?
> +
> int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
> index e47582b0de0a..e375405a7828 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.h
> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> @@ -258,6 +258,7 @@ bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
> int intel_bios_max_tmds_clock(struct intel_encoder *encoder);
> int intel_bios_hdmi_level_shift(struct intel_encoder *encoder);
> int intel_bios_dp_max_link_rate(struct intel_encoder *encoder);
> +int intel_bios_dp_max_lane_count(struct intel_encoder *encoder);
> int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder);
> bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, enum port port);
> bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 32292c0be2bd..0370c4c105dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -286,11 +286,22 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
> return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
> }
>
> +static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
> +{
> + int vbt_max_lanes = intel_bios_dp_max_lane_count(&dig_port->base);
> + int max_lanes = dig_port->max_lanes;
> +
> + if (vbt_max_lanes)
> + max_lanes = min(max_lanes, vbt_max_lanes);
> +
> + return max_lanes;
> +}
> +
> /* Theoretical max between source and sink */
> static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> - int source_max = dig_port->max_lanes;
> + int source_max = intel_dp_max_source_lane_count(dig_port);
> int sink_max = intel_dp->max_sink_lane_count;
> int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
> int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 01/12] drm/i915: Unify VBT version number comments
2022-07-19 10:25 ` Rodrigo Vivi
@ 2022-09-01 9:24 ` Ville Syrjälä
0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2022-09-01 9:24 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Jul 19, 2022 at 06:25:20AM -0400, Rodrigo Vivi wrote:
> On Fri, Jul 15, 2022 at 11:20:33PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Use a more standard form for the VT version number comments.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_vbt_defs.h | 206 ++++++++++--------
> > 1 file changed, 110 insertions(+), 96 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > index 509b0a419c20..ba328d130991 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> > @@ -75,6 +75,20 @@ struct bdb_header {
> > u16 bdb_size;
> > } __packed;
> >
> > +/*
> > + * BDB version number dependencies are documented as:
> > + *
> > + * <start>+
> > + * indicates the field was introduced in version <start>
> > + * and is still valid
> > + *
> > + * <start>-<end>
> > + * indicates the field was introduced in version <start>
> > + * and obsoleted in version <end>+1.
> > + *
> > + * ??? indicates the specific version number is unknown
> > + */
> > +
> > /*
> > * There are several types of BIOS data blocks (BDBs), each block has
> > * an ID and size in the first 3 bytes (ID in first, size in next 2).
> > @@ -144,12 +158,12 @@ struct bdb_general_features {
> > /* bits 3 */
> > u8 disable_smooth_vision:1;
> > u8 single_dvi:1;
> > - u8 rotate_180:1; /* 181 */
> > + u8 rotate_180:1; /* 181+ */
> > u8 fdi_rx_polarity_inverted:1;
> > - u8 vbios_extended_mode:1; /* 160 */
> > - u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */
> > - u8 panel_best_fit_timing:1; /* 160 */
> > - u8 ignore_strap_state:1; /* 160 */
> > + u8 vbios_extended_mode:1; /* 160+ */
> > + u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160+ */
> > + u8 panel_best_fit_timing:1; /* 160+ */
> > + u8 ignore_strap_state:1; /* 160+ */
> >
> > /* bits 4 */
> > u8 legacy_monitor_detect;
> > @@ -164,11 +178,11 @@ struct bdb_general_features {
> > u8 rsvd11:2; /* finish byte */
> >
> > /* bits 6 */
> > - u8 tc_hpd_retry_timeout:7; /* 242 */
> > + u8 tc_hpd_retry_timeout:7; /* 242+ */
> > u8 rsvd12:1;
> >
> > /* bits 7 */
> > - u8 afc_startup_config:2;/* 249 */
> > + u8 afc_startup_config:2; /* 249+ */
> > u8 rsvd13:6;
> > } __packed;
> >
> > @@ -275,27 +289,27 @@ struct bdb_general_features {
> > #define DVO_PORT_DPC 8
> > #define DVO_PORT_DPD 9
> > #define DVO_PORT_DPA 10
> > -#define DVO_PORT_DPE 11 /* 193 */
> > -#define DVO_PORT_HDMIE 12 /* 193 */
> > +#define DVO_PORT_DPE 11 /* 193+ */
> > +#define DVO_PORT_HDMIE 12 /* 193+ */
> > #define DVO_PORT_DPF 13 /* N/A */
> > #define DVO_PORT_HDMIF 14 /* N/A */
> > -#define DVO_PORT_DPG 15 /* 217 */
> > -#define DVO_PORT_HDMIG 16 /* 217 */
> > -#define DVO_PORT_DPH 17 /* 217 */
> > -#define DVO_PORT_HDMIH 18 /* 217 */
> > -#define DVO_PORT_DPI 19 /* 217 */
> > -#define DVO_PORT_HDMII 20 /* 217 */
> > -#define DVO_PORT_MIPIA 21 /* 171 */
> > -#define DVO_PORT_MIPIB 22 /* 171 */
> > -#define DVO_PORT_MIPIC 23 /* 171 */
> > -#define DVO_PORT_MIPID 24 /* 171 */
> > +#define DVO_PORT_DPG 15 /* 217+ */
> > +#define DVO_PORT_HDMIG 16 /* 217+ */
> > +#define DVO_PORT_DPH 17 /* 217+ */
> > +#define DVO_PORT_HDMIH 18 /* 217+ */
> > +#define DVO_PORT_DPI 19 /* 217+ */
> > +#define DVO_PORT_HDMII 20 /* 217+ */
> > +#define DVO_PORT_MIPIA 21 /* 171+ */
> > +#define DVO_PORT_MIPIB 22 /* 171+ */
> > +#define DVO_PORT_MIPIC 23 /* 171+ */
> > +#define DVO_PORT_MIPID 24 /* 171+ */
> >
> > -#define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */
> > -#define HDMI_MAX_DATA_RATE_297 1 /* 204 */
> > -#define HDMI_MAX_DATA_RATE_165 2 /* 204 */
> > -#define HDMI_MAX_DATA_RATE_594 3 /* 249 */
> > -#define HDMI_MAX_DATA_RATE_340 4 /* 249 */
> > -#define HDMI_MAX_DATA_RATE_300 5 /* 249 */
> > +#define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204+ */
> > +#define HDMI_MAX_DATA_RATE_297 1 /* 204+ */
> > +#define HDMI_MAX_DATA_RATE_165 2 /* 204+ */
> > +#define HDMI_MAX_DATA_RATE_594 3 /* 249+ */
> > +#define HDMI_MAX_DATA_RATE_340 4 /* 249+ */
> > +#define HDMI_MAX_DATA_RATE_300 5 /* 249+ */
> >
> > #define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33
> >
> > @@ -379,19 +393,19 @@ struct child_device_config {
> > u8 device_id[10]; /* ascii string */
> > struct {
> > u8 i2c_speed;
> > - u8 dp_onboard_redriver; /* 158 */
> > - u8 dp_ondock_redriver; /* 158 */
> > - u8 hdmi_level_shifter_value:5; /* 169 */
> > - u8 hdmi_max_data_rate:3; /* 204 */
> > - u16 dtd_buf_ptr; /* 161 */
> > - u8 edidless_efp:1; /* 161 */
> > - u8 compression_enable:1; /* 198 */
> > - u8 compression_method_cps:1; /* 198 */
> > - u8 ganged_edp:1; /* 202 */
> > + u8 dp_onboard_redriver; /* 158+ */
> > + u8 dp_ondock_redriver; /* 158+ */
> > + u8 hdmi_level_shifter_value:5; /* 158+ */
> > + u8 hdmi_max_data_rate:3; /* 204+ */
> > + u16 dtd_buf_ptr; /* 161+ */
> > + u8 edidless_efp:1; /* 161+ */
> > + u8 compression_enable:1; /* 198+ */
> > + u8 compression_method_cps:1; /* 198+ */
> > + u8 ganged_edp:1; /* 202+ */
> > u8 reserved0:4;
> > - u8 compression_structure_index:4; /* 198 */
> > + u8 compression_structure_index:4; /* 198+ */
> > u8 reserved1:4;
> > - u8 slave_port; /* 202 */
> > + u8 slave_port; /* 202+ */
> > u8 reserved2;
> > } __packed;
> > } __packed;
> > @@ -412,16 +426,16 @@ struct child_device_config {
> > u8 ddc2_pin;
> > } __packed;
> > struct {
> > - u8 efp_routed:1; /* 158 */
> > - u8 lane_reversal:1; /* 184 */
> > - u8 lspcon:1; /* 192 */
> > - u8 iboost:1; /* 196 */
> > - u8 hpd_invert:1; /* 196 */
> > - u8 use_vbt_vswing:1; /* 218 */
> > + u8 efp_routed:1; /* 158+ */
> > + u8 lane_reversal:1; /* 184+ */
> > + u8 lspcon:1; /* 192+ */
> > + u8 iboost:1; /* 196+ */
> > + u8 hpd_invert:1; /* 196+ */
> > + u8 use_vbt_vswing:1; /* 218+ */
> > u8 flag_reserved:2;
> > - u8 hdmi_support:1; /* 158 */
> > - u8 dp_support:1; /* 158 */
> > - u8 tmds_support:1; /* 158 */
> > + u8 hdmi_support:1; /* 158+ */
> > + u8 dp_support:1; /* 158+ */
> > + u8 tmds_support:1; /* 158+ */
> > u8 support_reserved:5;
> > u8 aux_channel;
> > u8 dongle_detect;
> > @@ -429,7 +443,7 @@ struct child_device_config {
> > } __packed;
> >
> > u8 pipe_cap:2;
> > - u8 sdvo_stall:1; /* 158 */
> > + u8 sdvo_stall:1; /* 158+ */
> > u8 hpd_status:2;
> > u8 integrated_encoder:1;
> > u8 capabilities_reserved:2;
> > @@ -437,21 +451,21 @@ struct child_device_config {
> >
> > union {
> > u8 dvo2_wiring;
> > - u8 mipi_bridge_type; /* 171 */
> > + u8 mipi_bridge_type; /* 171+ */
> > } __packed;
> >
> > u16 extended_type;
> > u8 dvo_function;
> > - u8 dp_usb_type_c:1; /* 195 */
> > - u8 tbt:1; /* 209 */
> > - u8 flags2_reserved:2; /* 195 */
> > - u8 dp_port_trace_length:4; /* 209 */
> > - u8 dp_gpio_index; /* 195 */
> > - u16 dp_gpio_pin_num; /* 195 */
> > - u8 dp_iboost_level:4; /* 196 */
> > - u8 hdmi_iboost_level:4; /* 196 */
> > - u8 dp_max_link_rate:3; /* 216/230 GLK+ */
> > - u8 dp_max_link_rate_reserved:5; /* 216/230 */
>
> any idea about this 230 and the GLK mention?
Had to do some digging for this one.
So the story is that the field was introduced in 216 but
then they totally changed the meaning of the bits in 230.
See parse_bdb_216_dp_max_link_rate() vs.
parse_bdb_230_dp_max_link_rate(). But naturally the current
version of the spec totally fails to mention this. Sigh.
The GLK comment originally said CNL (it got changed during mass
rename when CNL stuff was dropped), and that was just based on
a note in the spec at the time that said the field is valid for
CNL+. Whether that actually included GLK or not is not at all
clear.
Also currently we parse this for everything so it's not super
obvious if we're accidentlaly parsing it on platforms where
it should not be used. But that should actually be fine since
the value should then be 0 which either means 8.1Gbps or
"no limit" which should not therefore impose any accidental
limit on anything.
I should probably put some of that into the commit message
for posterity...
> but anyway the 216+ includes the 230, so it looks okay.
>
> for everything else I just relied on what was already in the code
> and didn't check the VBT itself, but feel free to use:
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Thanks.
>
>
>
> > + u8 dp_usb_type_c:1; /* 195+ */
> > + u8 tbt:1; /* 209+ */
> > + u8 flags2_reserved:2; /* 195+ */
> > + u8 dp_port_trace_length:4; /* 209+ */
> > + u8 dp_gpio_index; /* 195+ */
> > + u16 dp_gpio_pin_num; /* 195+ */
> > + u8 dp_iboost_level:4; /* 196+ */
> > + u8 hdmi_iboost_level:4; /* 196+ */
> > + u8 dp_max_link_rate:3; /* 216+ */
> > + u8 dp_max_link_rate_reserved:5; /* 216+ */
> > } __packed;
> >
> > struct bdb_general_definitions {
> > @@ -690,18 +704,18 @@ struct bdb_edp {
> > u32 sdrrs_msa_timing_delay;
> >
> > /* ith bit indicates enabled/disabled for (i+1)th panel */
> > - u16 edp_s3d_feature; /* 162 */
> > - u16 edp_t3_optimization; /* 165 */
> > - u64 edp_vswing_preemph; /* 173 */
> > - u16 fast_link_training; /* 182 */
> > - u16 dpcd_600h_write_required; /* 185 */
> > - struct edp_pwm_delays pwm_delays[16]; /* 186 */
> > - u16 full_link_params_provided; /* 199 */
> > - struct edp_full_link_params full_link_params[16]; /* 199 */
> > - u16 apical_enable; /* 203 */
> > - struct edp_apical_params apical_params[16]; /* 203 */
> > - u16 edp_fast_link_training_rate[16]; /* 224 */
> > - u16 edp_max_port_link_rate[16]; /* 244 */
> > + u16 edp_s3d_feature; /* 162+ */
> > + u16 edp_t3_optimization; /* 165+ */
> > + u64 edp_vswing_preemph; /* 173+ */
> > + u16 fast_link_training; /* 182+ */
> > + u16 dpcd_600h_write_required; /* 185+ */
> > + struct edp_pwm_delays pwm_delays[16]; /* 186+ */
> > + u16 full_link_params_provided; /* 199+ */
> > + struct edp_full_link_params full_link_params[16]; /* 199+ */
> > + u16 apical_enable; /* 203+ */
> > + struct edp_apical_params apical_params[16]; /* 203+ */
> > + u16 edp_fast_link_training_rate[16]; /* 224+ */
> > + u16 edp_max_port_link_rate[16]; /* 244+ */
> > } __packed;
> >
> > /*
> > @@ -710,7 +724,7 @@ struct bdb_edp {
> >
> > struct bdb_lvds_options {
> > u8 panel_type;
> > - u8 panel_type2; /* 212 */
> > + u8 panel_type2; /* 212+ */
> > /* LVDS capabilities, stored in a dword */
> > u8 pfit_mode:2;
> > u8 pfit_text_mode_enhanced:1;
> > @@ -733,9 +747,9 @@ struct bdb_lvds_options {
> > /* LVDS backlight control type bits stored here */
> > u32 blt_control_type_bits;
> >
> > - u16 lcdvcc_s0_enable; /* 200 */
> > - u32 rotation; /* 228 */
> > - u32 position; /* 240 */
> > + u16 lcdvcc_s0_enable; /* 200+ */
> > + u32 rotation; /* 228+ */
> > + u32 position; /* 240+ */
> > } __packed;
> >
> > /*
> > @@ -756,7 +770,7 @@ struct lvds_lfp_data_ptr {
> > struct bdb_lvds_lfp_data_ptrs {
> > u8 lvds_entries;
> > struct lvds_lfp_data_ptr ptr[16];
> > - struct lvds_lfp_data_ptr_table panel_name; /* 156-163? */
> > + struct lvds_lfp_data_ptr_table panel_name; /* (156-163?)+ */
> > } __packed;
> >
> > /*
> > @@ -808,20 +822,20 @@ struct lvds_lfp_panel_name {
> > } __packed;
> >
> > struct lvds_lfp_black_border {
> > - u8 top; /* 227 */
> > - u8 bottom; /* 227 */
> > - u8 left; /* 238 */
> > - u8 right; /* 238 */
> > + u8 top; /* 227+ */
> > + u8 bottom; /* 227+ */
> > + u8 left; /* 238+ */
> > + u8 right; /* 238+ */
> > } __packed;
> >
> > struct bdb_lvds_lfp_data_tail {
> > - struct lvds_lfp_panel_name panel_name[16]; /* 156-163? */
> > - u16 scaling_enable; /* 187 */
> > - u8 seamless_drrs_min_refresh_rate[16]; /* 188 */
> > - u8 pixel_overlap_count[16]; /* 208 */
> > - struct lvds_lfp_black_border black_border[16]; /* 227 */
> > - u16 dual_lfp_port_sync_enable; /* 231 */
> > - u16 gpu_dithering_for_banding_artifacts; /* 245 */
> > + struct lvds_lfp_panel_name panel_name[16]; /* (156-163?)+ */
> > + u16 scaling_enable; /* 187+ */
> > + u8 seamless_drrs_min_refresh_rate[16]; /* 188+ */
> > + u8 pixel_overlap_count[16]; /* 208+ */
> > + struct lvds_lfp_black_border black_border[16]; /* 227+ */
> > + u16 dual_lfp_port_sync_enable; /* 231+ */
> > + u16 gpu_dithering_for_banding_artifacts; /* 245+ */
> > } __packed;
> >
> > /*
> > @@ -836,7 +850,7 @@ struct lfp_backlight_data_entry {
> > u8 active_low_pwm:1;
> > u8 obsolete1:5;
> > u16 pwm_freq_hz;
> > - u8 min_brightness; /* Obsolete from 234+ */
> > + u8 min_brightness; /* ???-233 */
> > u8 obsolete2;
> > u8 obsolete3;
> > } __packed;
> > @@ -859,7 +873,7 @@ struct lfp_brightness_level {
> > struct bdb_lfp_backlight_data {
> > u8 entry_size;
> > struct lfp_backlight_data_entry data[16];
> > - u8 level[16]; /* Obsolete from 234+ */
> > + u8 level[16]; /* ???-233 */
> > struct lfp_backlight_control_method backlight_control[16];
> > struct lfp_brightness_level brightness_level[16]; /* 234+ */
> > struct lfp_brightness_level brightness_min_level[16]; /* 234+ */
> > @@ -908,11 +922,11 @@ struct bdb_lfp_power {
> > u16 adb;
> > u16 lace_enabled_status;
> > struct aggressiveness_profile_entry aggressiveness[16];
> > - u16 hobl; /* 232+ */
> > - u16 vrr_feature_enabled; /* 233+ */
> > - u16 elp; /* 247+ */
> > - u16 opst; /* 247+ */
> > - struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247+ */
> > + u16 hobl; /* 232+ */
> > + u16 vrr_feature_enabled; /* 233+ */
> > + u16 elp; /* 247+ */
> > + u16 opst; /* 247+ */
> > + struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247+ */
> > } __packed;
> >
> > /*
> > @@ -922,10 +936,10 @@ struct bdb_lfp_power {
> > #define MAX_MIPI_CONFIGURATIONS 6
> >
> > struct bdb_mipi_config {
> > - struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175 */
> > - struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177 */
> > - struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS]; /* 186 */
> > - u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190 */
> > + struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; /* 175+ */
> > + struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; /* 177+ */
> > + struct edp_pwm_delays pwm_delays[MAX_MIPI_CONFIGURATIONS]; /* 186+ */
> > + u8 pmic_i2c_bus_number[MAX_MIPI_CONFIGURATIONS]; /* 190+ */
> > } __packed;
> >
> > /*
> > --
> > 2.35.1
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 11/12] drm/i915: WARN if a port should use VBT provided vswing tables
2022-07-19 10:31 ` Rodrigo Vivi
@ 2022-09-01 9:24 ` Ville Syrjälä
0 siblings, 0 replies; 32+ messages in thread
From: Ville Syrjälä @ 2022-09-01 9:24 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Jul 19, 2022 at 06:31:11AM -0400, Rodrigo Vivi wrote:
> On Fri, Jul 15, 2022 at 11:20:43PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We don't parse the VBT vswing/preemphassis tables at all currently.
> > Let's WARN if a port wants to use them so we get a heads up that
> > whether we really need to implement this stuff or not. My
> > current stash contains no VBTs with this bit set.
>
> let's unlock a new can of worms?! :)
>
> I believe this deserves a /* XXX: comment with the code in case
> someone else finds this warns first and doesn't use the git blame
Sure I'll stick some kind of comment there.
>
> anyways
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bios.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> > index 51dde5bfd956..cd86b65055ef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -2661,6 +2661,10 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
> > return;
> > }
> >
> > + drm_WARN(&i915->drm, child->use_vbt_vswing,
> > + "Port %c asks to use VBT vswing/preemph tables\n",
> > + port_name(port));
> > +
> > if (i915->vbt.ports[port]) {
> > drm_dbg_kms(&i915->drm,
> > "More than one child device for port %c in VBT, using the first.\n",
> > --
> > 2.35.1
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 12/12] drm/i915: Parse DP/eDP max lane count from VBT
2022-07-19 10:39 ` Rodrigo Vivi
@ 2022-09-01 9:25 ` Ville Syrjälä
2022-09-02 14:42 ` Jani Nikula
0 siblings, 1 reply; 32+ messages in thread
From: Ville Syrjälä @ 2022-09-01 9:25 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Tue, Jul 19, 2022 at 06:39:29AM -0400, Rodrigo Vivi wrote:
> On Fri, Jul 15, 2022 at 11:20:44PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Limit the DP lane count based on the new VBT DP/eDP max
> > lane count field.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bios.c | 16 ++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_bios.h | 1 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++++++-
> > 3 files changed, 29 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> > index cd86b65055ef..d8063c329b3a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> > @@ -2489,6 +2489,14 @@ static int _intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *de
> > return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate);
> > }
> >
> > +static int _intel_bios_dp_max_lane_count(const struct intel_bios_encoder_data *devdata)
> > +{
> > + if (!devdata || devdata->i915->vbt.version < 244)
> > + return 0;
> > +
> > + return devdata->child.dp_max_lane_count + 1;
> > +}
> > +
> > static void sanitize_device_type(struct intel_bios_encoder_data *devdata,
> > enum port port)
> > {
> > @@ -3674,6 +3682,14 @@ int intel_bios_dp_max_link_rate(struct intel_encoder *encoder)
> > return _intel_bios_dp_max_link_rate(devdata);
> > }
> >
> > +int intel_bios_dp_max_lane_count(struct intel_encoder *encoder)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
> > +
> > + return _intel_bios_dp_max_lane_count(devdata);
> > +}
>
> do we really need 2 functions here since this one is small and we don't have any
> bit switches and all?!
> or do you plan to reuse this anywhere else later?
This is modelled after the other similar functions. I think Jani had
some plans for cleaning up a lot of this stuff, but dunno how far we
are on that path.
>
> > +
> > int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
> > {
> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
> > index e47582b0de0a..e375405a7828 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bios.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> > @@ -258,6 +258,7 @@ bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
> > int intel_bios_max_tmds_clock(struct intel_encoder *encoder);
> > int intel_bios_hdmi_level_shift(struct intel_encoder *encoder);
> > int intel_bios_dp_max_link_rate(struct intel_encoder *encoder);
> > +int intel_bios_dp_max_lane_count(struct intel_encoder *encoder);
> > int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder);
> > bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, enum port port);
> > bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port);
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 32292c0be2bd..0370c4c105dc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -286,11 +286,22 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
> > return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
> > }
> >
> > +static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
> > +{
> > + int vbt_max_lanes = intel_bios_dp_max_lane_count(&dig_port->base);
> > + int max_lanes = dig_port->max_lanes;
> > +
> > + if (vbt_max_lanes)
> > + max_lanes = min(max_lanes, vbt_max_lanes);
> > +
> > + return max_lanes;
> > +}
> > +
> > /* Theoretical max between source and sink */
> > static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
> > {
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > - int source_max = dig_port->max_lanes;
> > + int source_max = intel_dp_max_source_lane_count(dig_port);
> > int sink_max = intel_dp->max_sink_lane_count;
> > int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
> > int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
> > --
> > 2.35.1
> >
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 11/12] drm/i915: WARN if a port should use VBT provided vswing tables
2022-07-15 20:20 ` [Intel-gfx] [PATCH 11/12] drm/i915: WARN if a port should use VBT provided vswing tables Ville Syrjala
2022-07-19 10:31 ` Rodrigo Vivi
@ 2022-09-02 14:01 ` Jani Nikula
1 sibling, 0 replies; 32+ messages in thread
From: Jani Nikula @ 2022-09-02 14:01 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 15 Jul 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We don't parse the VBT vswing/preemphassis tables at all currently.
> Let's WARN if a port wants to use them so we get a heads up that
> whether we really need to implement this stuff or not. My
> current stash contains no VBTs with this bit set.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 51dde5bfd956..cd86b65055ef 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2661,6 +2661,10 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
> return;
> }
>
> + drm_WARN(&i915->drm, child->use_vbt_vswing,
> + "Port %c asks to use VBT vswing/preemph tables\n",
> + port_name(port));
> +
I was hoping to clean parse_ddi_port() of all this kind of informative
stuff and shove it to print_ddi_port().
BR,
Jani.
> if (i915->vbt.ports[port]) {
> drm_dbg_kms(&i915->drm,
> "More than one child device for port %c in VBT, using the first.\n",
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 07/12] drm/i915: Document the sets of bits in the driver features block
2022-07-15 20:20 ` [Intel-gfx] [PATCH 07/12] drm/i915: Document the sets of bits in the driver features block Ville Syrjala
@ 2022-09-02 14:05 ` Jani Nikula
0 siblings, 0 replies; 32+ messages in thread
From: Jani Nikula @ 2022-09-02 14:05 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 15 Jul 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add a few comment documenting the sets of bits in the driver
> features block. Might make it a bit easier to check against
> the spec.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 8bdb533b5304..c04937aa75b2 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -542,6 +542,7 @@ struct bdb_psr {
> #define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3
>
> struct bdb_driver_features {
> + /* Driver bits */
> u8 boot_dev_algorithm:1;
> u8 block_display_switch:1;
> u8 allow_display_switch:1;
> @@ -556,6 +557,7 @@ struct bdb_driver_features {
> u8 boot_mode_bpp;
> u8 boot_mode_refresh;
>
> + /* Extended Driver Bits 1 */
> u16 enable_lfp_primary:1;
> u16 selective_mode_pruning:1;
> u16 dual_frequency:1;
> @@ -571,6 +573,7 @@ struct bdb_driver_features {
> u16 tv_hotplug:1;
> u16 hdmi_config:2;
>
> + /* Driver Flags 1 */
> u8 static_display:1; /* 163+ */
> u8 reserved2:7;
>
> @@ -578,8 +581,12 @@ struct bdb_driver_features {
> u16 legacy_crt_max_y;
> u8 legacy_crt_max_refresh;
>
> + /* Extended Driver Bits 2 */
> u8 hdmi_termination;
> +
> u8 custom_vbt_version; /* 165+ */
> +
> + /* Driver Feature Flags */
> u16 rmpm_enabled:1; /* 165+ */
> u16 s2ddt_enabled:1; /* 165+ */
> u16 dpst_enabled:1; /* 165-227 */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 08/12] drm/i915: Define more VBT driver features block bits
2022-07-15 20:20 ` [Intel-gfx] [PATCH 08/12] drm/i915: Define more VBT driver features block bits Ville Syrjala
@ 2022-09-02 14:09 ` Jani Nikula
0 siblings, 0 replies; 32+ messages in thread
From: Jani Nikula @ 2022-09-02 14:09 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 15 Jul 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Define some additoonal bits in the driver features VBT block.
*additional
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index c04937aa75b2..2feba1e69a6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -575,14 +575,19 @@ struct bdb_driver_features {
>
> /* Driver Flags 1 */
> u8 static_display:1; /* 163+ */
> - u8 reserved2:7;
> + u8 embedded_platform:1; /* 163+ */
> + u8 display_subsystem_enable:1; /* 163+ */
> + u8 reserved0:5;
>
> u16 legacy_crt_max_x;
> u16 legacy_crt_max_y;
> u8 legacy_crt_max_refresh;
>
> /* Extended Driver Bits 2 */
> - u8 hdmi_termination;
> + u8 hdmi_termination:1;
> + u8 cea861d_hdmi_support:1;
> + u8 self_refresh_enable:1;
> + u8 reserved1:5;
>
> u8 custom_vbt_version; /* 165+ */
>
> @@ -598,9 +603,10 @@ struct bdb_driver_features {
> u16 tbt_enabled:1; /* 165+ */
> u16 psr_enabled:1; /* 165-227 */
> u16 ips_enabled:1; /* 165+ */
> - u16 reserved3:1;
> + u16 dpfs_enabled:1; /* 165+ */
> u16 dmrrs_enabled:1; /* 174-227 */
> - u16 reserved4:2;
> + u16 adt_enabled:1; /* ???-228 */
> + u16 hpd_wake:1; /* 201-240 */
> u16 pc_feature_valid:1;
> } __packed;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 09/12] drm/i915: Define all possible VBT device handles
2022-07-15 20:20 ` [Intel-gfx] [PATCH 09/12] drm/i915: Define all possible VBT device handles Ville Syrjala
@ 2022-09-02 14:13 ` Jani Nikula
0 siblings, 0 replies; 32+ messages in thread
From: Jani Nikula @ 2022-09-02 14:13 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 15 Jul 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We already have LFP1 and LFP2 device handles define. Just
> add all the rest as well.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 2feba1e69a6d..f56c869e106f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -197,6 +197,15 @@ struct bdb_general_features {
> #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */
>
> /* Device handle */
> +#define DEVICE_HANDLE_CRT 0x0001
> +#define DEVICE_HANDLE_EFP1 0x0004
> +#define DEVICE_HANDLE_EFP2 0x0040
> +#define DEVICE_HANDLE_EFP3 0x0020
> +#define DEVICE_HANDLE_EFP4 0x0010 /* 194+ */
> +#define DEVICE_HANDLE_EFP5 0x0002 /* 215+ */
> +#define DEVICE_HANDLE_EFP6 0x0001 /* 217+ */
> +#define DEVICE_HANDLE_EFP7 0x0100 /* 217+ */
> +#define DEVICE_HANDLE_EFP8 0x0200 /* 217+ */
> #define DEVICE_HANDLE_LFP1 0x0008
> #define DEVICE_HANDLE_LFP2 0x0080
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 10/12] drm/i915: Rename some VBT bits
2022-07-15 20:20 ` [Intel-gfx] [PATCH 10/12] drm/i915: Rename some VBT bits Ville Syrjala
@ 2022-09-02 14:15 ` Jani Nikula
0 siblings, 0 replies; 32+ messages in thread
From: Jani Nikula @ 2022-09-02 14:15 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 15 Jul 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The allow vs. block display switch bits are named rather
> inconsistently. Fix it up.
WTF on the names. :D
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index f56c869e106f..62183c6bdc10 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -553,8 +553,8 @@ struct bdb_psr {
> struct bdb_driver_features {
> /* Driver bits */
> u8 boot_dev_algorithm:1;
> - u8 block_display_switch:1;
> - u8 allow_display_switch:1;
> + u8 allow_display_switch_dvd:1;
> + u8 allow_display_switch_dos:1;
> u8 hotplug_dvo:1;
> u8 dual_view_zoom:1;
> u8 int15h_hook:1;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 04/12] drm/i915: Define VBT eDP/DP max lane count bits
2022-07-15 20:20 ` [Intel-gfx] [PATCH 04/12] drm/i915: Define VBT eDP/DP max lane count bits Ville Syrjala
@ 2022-09-02 14:36 ` Jani Nikula
0 siblings, 0 replies; 32+ messages in thread
From: Jani Nikula @ 2022-09-02 14:36 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 15 Jul 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Since version 244 the VBT can llimt the eDP/DP max lane count.
> Add the bits.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index a88c5ef51cd8..d583bb085913 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -438,7 +438,7 @@ struct child_device_config {
> u8 iboost:1; /* 196+ */
> u8 hpd_invert:1; /* 196+ */
> u8 use_vbt_vswing:1; /* 218+ */
> - u8 flag_reserved:2;
> + u8 dp_max_lane_count:2; /* 244+ */
> u8 hdmi_support:1; /* 158+ */
> u8 dp_support:1; /* 158+ */
> u8 tmds_support:1; /* 158+ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 12/12] drm/i915: Parse DP/eDP max lane count from VBT
2022-09-01 9:25 ` Ville Syrjälä
@ 2022-09-02 14:42 ` Jani Nikula
0 siblings, 0 replies; 32+ messages in thread
From: Jani Nikula @ 2022-09-02 14:42 UTC (permalink / raw)
To: Ville Syrjälä, Rodrigo Vivi; +Cc: intel-gfx
On Thu, 01 Sep 2022, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Jul 19, 2022 at 06:39:29AM -0400, Rodrigo Vivi wrote:
>> On Fri, Jul 15, 2022 at 11:20:44PM +0300, Ville Syrjala wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Limit the DP lane count based on the new VBT DP/eDP max
>> > lane count field.
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > ---
>> > drivers/gpu/drm/i915/display/intel_bios.c | 16 ++++++++++++++++
>> > drivers/gpu/drm/i915/display/intel_bios.h | 1 +
>> > drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++++++-
>> > 3 files changed, 29 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>> > index cd86b65055ef..d8063c329b3a 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_bios.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>> > @@ -2489,6 +2489,14 @@ static int _intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *de
>> > return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate);
>> > }
>> >
>> > +static int _intel_bios_dp_max_lane_count(const struct intel_bios_encoder_data *devdata)
>> > +{
>> > + if (!devdata || devdata->i915->vbt.version < 244)
>> > + return 0;
>> > +
>> > + return devdata->child.dp_max_lane_count + 1;
They just won't learn that non-zero is a really crappy "default" to
set. *sigh*
>> > +}
>> > +
>> > static void sanitize_device_type(struct intel_bios_encoder_data *devdata,
>> > enum port port)
>> > {
>> > @@ -3674,6 +3682,14 @@ int intel_bios_dp_max_link_rate(struct intel_encoder *encoder)
>> > return _intel_bios_dp_max_link_rate(devdata);
>> > }
>> >
>> > +int intel_bios_dp_max_lane_count(struct intel_encoder *encoder)
>> > +{
>> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> > + const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
>> > +
>> > + return _intel_bios_dp_max_lane_count(devdata);
>> > +}
>>
>> do we really need 2 functions here since this one is small and we don't have any
>> bit switches and all?!
>> or do you plan to reuse this anywhere else later?
>
> This is modelled after the other similar functions. I think Jani had
> some plans for cleaning up a lot of this stuff, but dunno how far we
> are on that path.
A bit stalled. Eventually I'd like all encoders to have encoder->devdata
and callers would pass that instead of encoder, and we wouldn't have
this i915->vbt.ports[encoder->port]; lookup.
But the first function could be used in print_ddi_port() for printing
the info while the latter couldn't. So I kinda prefer the split.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>>
>> > +
>> > int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
>> > {
>> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
>> > index e47582b0de0a..e375405a7828 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_bios.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_bios.h
>> > @@ -258,6 +258,7 @@ bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
>> > int intel_bios_max_tmds_clock(struct intel_encoder *encoder);
>> > int intel_bios_hdmi_level_shift(struct intel_encoder *encoder);
>> > int intel_bios_dp_max_link_rate(struct intel_encoder *encoder);
>> > +int intel_bios_dp_max_lane_count(struct intel_encoder *encoder);
>> > int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder);
>> > bool intel_bios_port_supports_typec_usb(struct drm_i915_private *i915, enum port port);
>> > bool intel_bios_port_supports_tbt(struct drm_i915_private *i915, enum port port);
>> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> > index 32292c0be2bd..0370c4c105dc 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> > @@ -286,11 +286,22 @@ static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
>> > return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);
>> > }
>> >
>> > +static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
>> > +{
>> > + int vbt_max_lanes = intel_bios_dp_max_lane_count(&dig_port->base);
>> > + int max_lanes = dig_port->max_lanes;
>> > +
>> > + if (vbt_max_lanes)
>> > + max_lanes = min(max_lanes, vbt_max_lanes);
>> > +
>> > + return max_lanes;
>> > +}
>> > +
>> > /* Theoretical max between source and sink */
>> > static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
>> > {
>> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> > - int source_max = dig_port->max_lanes;
>> > + int source_max = intel_dp_max_source_lane_count(dig_port);
>> > int sink_max = intel_dp->max_sink_lane_count;
>> > int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
>> > int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
>> > --
>> > 2.35.1
>> >
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 03/12] drm/i915: Properly define the DP redriver VBT bits
2022-07-15 20:20 ` [Intel-gfx] [PATCH 03/12] drm/i915: Properly define the DP redriver VBT bits Ville Syrjala
@ 2022-09-02 14:45 ` Jani Nikula
0 siblings, 0 replies; 32+ messages in thread
From: Jani Nikula @ 2022-09-02 14:45 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 15 Jul 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Split the DP redriver bytes into bitfields.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index e997b8bcc6b8..a88c5ef51cd8 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -393,8 +393,14 @@ struct child_device_config {
> u8 device_id[10]; /* ascii string */
> struct {
> u8 i2c_speed;
> - u8 dp_onboard_redriver; /* 158+ */
> - u8 dp_ondock_redriver; /* 158+ */
> + u8 dp_onboard_redriver_preemph:3; /* 158+ */
> + u8 dp_onboard_redriver_vswing:3; /* 158+ */
> + u8 dp_onboard_redriver_present:1; /* 158+ */
> + u8 reserved0:1;
> + u8 dp_ondock_redriver_preemph:3; /* 158+ */
> + u8 dp_ondock_redriver_vswing:3; /* 158+ */
> + u8 dp_ondock_redriver_present:1; /* 158+ */
> + u8 reserved1:1;
> u8 hdmi_level_shifter_value:5; /* 158+ */
> u8 hdmi_max_data_rate:3; /* 204+ */
> u16 dtd_buf_ptr; /* 161+ */
> @@ -402,11 +408,11 @@ struct child_device_config {
> u8 compression_enable:1; /* 198+ */
> u8 compression_method_cps:1; /* 198+ */
> u8 ganged_edp:1; /* 202+ */
> - u8 reserved0:4;
> + u8 reserved2:4;
> u8 compression_structure_index:4; /* 198+ */
> - u8 reserved1:4;
> + u8 reserved3:4;
> u8 slave_port; /* 202+ */
> - u8 reserved2;
> + u8 reserved4;
> } __packed;
> } __packed;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 05/12] drm/i915: Add the VBT LTTPR transparent vs. non-transparent bits
2022-07-15 20:20 ` [Intel-gfx] [PATCH 05/12] drm/i915: Add the VBT LTTPR transparent vs. non-transparent bits Ville Syrjala
@ 2022-09-02 14:47 ` Jani Nikula
0 siblings, 0 replies; 32+ messages in thread
From: Jani Nikula @ 2022-09-02 14:47 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 15 Jul 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> VBT gained a bit to indicate whether LTTPRs should use transparent
> or non-transparent mode. Dunno if we should actually look at this...
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index d583bb085913..b15e29509fac 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -408,7 +408,8 @@ struct child_device_config {
> u8 compression_enable:1; /* 198+ */
> u8 compression_method_cps:1; /* 198+ */
> u8 ganged_edp:1; /* 202+ */
> - u8 reserved2:4;
> + u8 lttpr_non_transparent:1; /* 235+ */
> + u8 reserved2:3;
> u8 compression_structure_index:4; /* 198+ */
> u8 reserved3:4;
> u8 slave_port; /* 202+ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 06/12] drm/i915: Define VBT max HDMI FRL rate bits
2022-07-15 20:20 ` [Intel-gfx] [PATCH 06/12] drm/i915: Define VBT max HDMI FRL rate bits Ville Syrjala
@ 2022-09-02 14:48 ` Jani Nikula
0 siblings, 0 replies; 32+ messages in thread
From: Jani Nikula @ 2022-09-02 14:48 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 15 Jul 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The VBT gained some bits to inidicate the max FRL rate for
> HDMI 2.1, define them.
>
> These just outright replaced the slave_port bits for ganged eDP.
> Apparently that feature was never actually used so someone decided
> that reusing the bits is fine. Although the actual ganged eDP
> enable bit was still left defined elsewhere for some reason.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index b15e29509fac..8bdb533b5304 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -412,8 +412,10 @@ struct child_device_config {
> u8 reserved2:3;
> u8 compression_structure_index:4; /* 198+ */
> u8 reserved3:4;
> - u8 slave_port; /* 202+ */
> - u8 reserved4;
> + u8 hdmi_max_frl_rate:4; /* 237+ */
> + u8 hdmi_max_frl_rate_valid:1; /* 237+ */
> + u8 reserved4:3; /* 237+ */
> + u8 reserved5;
> } __packed;
> } __packed;
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [Intel-gfx] [PATCH 02/12] drm/i915: Add some more VBT version number comments
2022-07-15 20:20 ` [Intel-gfx] [PATCH 02/12] drm/i915: Add some more " Ville Syrjala
@ 2022-09-02 15:00 ` Jani Nikula
0 siblings, 0 replies; 32+ messages in thread
From: Jani Nikula @ 2022-09-02 15:00 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 15 Jul 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Document the VBT version dependency of several other fields.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_vbt_defs.h | 76 +++++++++----------
> 1 file changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index ba328d130991..e997b8bcc6b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -502,25 +502,25 @@ struct bdb_general_definitions {
>
> struct psr_table {
> /* Feature bits */
> - u8 full_link:1;
> - u8 require_aux_to_wakeup:1;
> + u8 full_link:1; /* 165+ */
> + u8 require_aux_to_wakeup:1; /* 165+ */
> u8 feature_bits_rsvd:6;
>
> /* Wait times */
> - u8 idle_frames:4;
> - u8 lines_to_wait:3;
> + u8 idle_frames:4; /* 165+ */
> + u8 lines_to_wait:3; /* 165+ */
> u8 wait_times_rsvd:1;
>
> /* TP wake up time in multiple of 100 */
> - u16 tp1_wakeup_time;
> - u16 tp2_tp3_wakeup_time;
> + u16 tp1_wakeup_time; /* 165+ */
> + u16 tp2_tp3_wakeup_time; /* 165+ */
> } __packed;
>
> struct bdb_psr {
> struct psr_table psr_table[16];
>
> /* PSR2 TP2/TP3 wakeup time for 16 panels */
> - u32 psr2_tp2_tp3_wakeup_time;
> + u32 psr2_tp2_tp3_wakeup_time; /* 226+ */
> } __packed;
>
> /*
> @@ -562,28 +562,28 @@ struct bdb_driver_features {
> u16 tv_hotplug:1;
> u16 hdmi_config:2;
>
> - u8 static_display:1;
> + u8 static_display:1; /* 163+ */
> u8 reserved2:7;
> +
> u16 legacy_crt_max_x;
> u16 legacy_crt_max_y;
> u8 legacy_crt_max_refresh;
>
> u8 hdmi_termination;
> - u8 custom_vbt_version;
> - /* Driver features data block */
> - u16 rmpm_enabled:1;
> - u16 s2ddt_enabled:1;
> - u16 dpst_enabled:1;
> - u16 bltclt_enabled:1;
> - u16 adb_enabled:1;
> - u16 drrs_enabled:1;
> - u16 grs_enabled:1;
> - u16 gpmt_enabled:1;
> - u16 tbt_enabled:1;
> - u16 psr_enabled:1;
> - u16 ips_enabled:1;
> + u8 custom_vbt_version; /* 165+ */
That's 155 in current bspec as well as some old doc I had.
Other than that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + u16 rmpm_enabled:1; /* 165+ */
> + u16 s2ddt_enabled:1; /* 165+ */
> + u16 dpst_enabled:1; /* 165-227 */
> + u16 bltclt_enabled:1; /* 165+ */
> + u16 adb_enabled:1; /* 165-227 */
> + u16 drrs_enabled:1; /* 165-227 */
> + u16 grs_enabled:1; /* 165+ */
> + u16 gpmt_enabled:1; /* 165+ */
> + u16 tbt_enabled:1; /* 165+ */
> + u16 psr_enabled:1; /* 165-227 */
> + u16 ips_enabled:1; /* 165+ */
> u16 reserved3:1;
> - u16 dmrrs_enabled:1;
> + u16 dmrrs_enabled:1; /* 174-227 */
> u16 reserved4:2;
> u16 pc_feature_valid:1;
> } __packed;
> @@ -671,7 +671,7 @@ struct bdb_sdvo_panel_dtds {
>
>
> struct edp_fast_link_params {
> - u8 rate:4;
> + u8 rate:4; /* ???-223 */
> u8 lanes:4;
> u8 preemphasis:4;
> u8 vswing:4;
> @@ -731,7 +731,7 @@ struct bdb_lvds_options {
> u8 pfit_gfx_mode_enhanced:1;
> u8 pfit_ratio_auto:1;
> u8 pixel_dither:1;
> - u8 lvds_edid:1;
> + u8 lvds_edid:1; /* ???-240 */
> u8 rsvd2:1;
> u8 rsvd4;
> /* LVDS Panel channel bits stored here */
> @@ -745,7 +745,7 @@ struct bdb_lvds_options {
> /* LVDS panel type bits stored here */
> u32 dps_panel_type_bits;
> /* LVDS backlight control type bits stored here */
> - u32 blt_control_type_bits;
> + u32 blt_control_type_bits; /* ???-240 */
>
> u16 lcdvcc_s0_enable; /* 200+ */
> u32 rotation; /* 228+ */
> @@ -888,8 +888,8 @@ struct lfp_power_features {
> u8 reserved1:1;
> u8 power_conservation_pref:3;
> u8 reserved2:1;
> - u8 lace_enabled_status:1;
> - u8 lace_support:1;
> + u8 lace_enabled_status:1; /* 210+ */
> + u8 lace_support:1; /* 210+ */
> u8 als_enable:1;
> } __packed;
>
> @@ -909,19 +909,19 @@ struct aggressiveness_profile2_entry {
> } __packed;
>
> struct bdb_lfp_power {
> - struct lfp_power_features features;
> + struct lfp_power_features features; /* ???-227 */
> struct als_data_entry als[5];
> - u8 lace_aggressiveness_profile:3;
> + u8 lace_aggressiveness_profile:3; /* 210-227 */
> u8 reserved1:5;
> - u16 dpst;
> - u16 psr;
> - u16 drrs;
> - u16 lace_support;
> - u16 adt;
> - u16 dmrrs;
> - u16 adb;
> - u16 lace_enabled_status;
> - struct aggressiveness_profile_entry aggressiveness[16];
> + u16 dpst; /* 228+ */
> + u16 psr; /* 228+ */
> + u16 drrs; /* 228+ */
> + u16 lace_support; /* 228+ */
> + u16 adt; /* 228+ */
> + u16 dmrrs; /* 228+ */
> + u16 adb; /* 228+ */
> + u16 lace_enabled_status; /* 228+ */
> + struct aggressiveness_profile_entry aggressiveness[16]; /* 228+ */
> u16 hobl; /* 232+ */
> u16 vrr_feature_enabled; /* 233+ */
> u16 elp; /* 247+ */
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 32+ messages in thread
end of thread, other threads:[~2022-09-02 15:01 UTC | newest]
Thread overview: 32+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-15 20:20 [Intel-gfx] [PATCH 00/12] drm/i915: More VBT stuff Ville Syrjala
2022-07-15 20:20 ` [Intel-gfx] [PATCH 01/12] drm/i915: Unify VBT version number comments Ville Syrjala
2022-07-19 10:25 ` Rodrigo Vivi
2022-09-01 9:24 ` Ville Syrjälä
2022-07-15 20:20 ` [Intel-gfx] [PATCH 02/12] drm/i915: Add some more " Ville Syrjala
2022-09-02 15:00 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 03/12] drm/i915: Properly define the DP redriver VBT bits Ville Syrjala
2022-09-02 14:45 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 04/12] drm/i915: Define VBT eDP/DP max lane count bits Ville Syrjala
2022-09-02 14:36 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 05/12] drm/i915: Add the VBT LTTPR transparent vs. non-transparent bits Ville Syrjala
2022-09-02 14:47 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 06/12] drm/i915: Define VBT max HDMI FRL rate bits Ville Syrjala
2022-09-02 14:48 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 07/12] drm/i915: Document the sets of bits in the driver features block Ville Syrjala
2022-09-02 14:05 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 08/12] drm/i915: Define more VBT driver features block bits Ville Syrjala
2022-09-02 14:09 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 09/12] drm/i915: Define all possible VBT device handles Ville Syrjala
2022-09-02 14:13 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 10/12] drm/i915: Rename some VBT bits Ville Syrjala
2022-09-02 14:15 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 11/12] drm/i915: WARN if a port should use VBT provided vswing tables Ville Syrjala
2022-07-19 10:31 ` Rodrigo Vivi
2022-09-01 9:24 ` Ville Syrjälä
2022-09-02 14:01 ` Jani Nikula
2022-07-15 20:20 ` [Intel-gfx] [PATCH 12/12] drm/i915: Parse DP/eDP max lane count from VBT Ville Syrjala
2022-07-19 10:39 ` Rodrigo Vivi
2022-09-01 9:25 ` Ville Syrjälä
2022-09-02 14:42 ` Jani Nikula
2022-07-16 18:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: More VBT stuff Patchwork
2022-07-16 21:50 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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