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From: Greg KH <gregkh@linuxfoundation.org>
To: Shenwei Wang <shenwei.wang@nxp.com>
Cc: linux-serial@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode
Date: Thu, 28 Jul 2022 10:35:05 +0200	[thread overview]
Message-ID: <YuJKObb/XQJ4woBK@kroah.com> (raw)
In-Reply-To: <20220714185858.615373-1-shenwei.wang@nxp.com>

On Thu, Jul 14, 2022 at 01:58:58PM -0500, Shenwei Wang wrote:
> The LPUART hardware doesn't zero out the parity bit on the received
> characters. This behavior won't impact the use cases of CS8 because
> the parity bit is the 9th bit which is not currently used by software.
> But the parity bit for CS7 must be zeroed out by software in order to
> get the correct raw data.
> 
> Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
> ---
> changes in v2
> - remove the "inline" keyword from the function of lpuart_tty_insert_flip_string;
> 
> changes in v1
> - fix the code indent and whitespace issue;

Please work with your email admins to fix up your systems as it is
showing this is an invalid signature when validating it:
	✗ BADSIG: DKIM/nxp.com

Soon I will just reject patches like this as you don't want people to
impersonate your domain, right?

thanks,

greg k-h

  parent reply	other threads:[~2022-07-28  8:35 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-14 18:58 [PATCH V2 1/1] serial: fsl_lpuart: zero out parity bit in CS7 mode Shenwei Wang
2022-07-19 10:25 ` Ilpo Järvinen
2022-07-19 23:33   ` [EXT] " Shenwei Wang
2022-07-28  8:35 ` Greg KH [this message]
2022-07-28 18:15   ` Shenwei Wang
2022-07-29  7:52     ` Greg KH

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