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* [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests
@ 2022-07-28  1:15 Umesh Nerlige Ramappa
  2022-07-28  1:53 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/hangman: Fix gt hang/error tests (rev2) Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 12+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-07-28  1:15 UTC (permalink / raw)
  To: igt-dev, John.C.Harrison, kamil.konieczny

gt-engine-hang and gt-engine-error tests were still using reset=2
setting so that ended up just doing an engine reset. Fix the tests so
that they actually do the gt specific reset and set the expectations
correctly.

In some rare failures, some of the background spinners show up as
innocent and keep spinning after the hang recovery. This can only happen
if the spinners did not start for some reason. Check that the spinners
actually started before submitting a hanging batch.

For engine specific hang, only one context is marked guilty, but for a
gt hang all contexts are marked guilty. Check for different expected
behavior for engine vs. gt reset.

v2:
- gt-reset resets all contexts on all engines. The execlist implementation
  of gt-engine-* tests expected that a preemptible background spinner
  running on the target engine should be marked innocent. While i915 can
  mark such a context for execlist mode, GuC scheduling does not guarantee
  that the background spinner can be marked as innocent. Since the state
  of the background spinner depends on the scheduling backend, do no
  validate the state of the background spinner for the target engine.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/i915/i915_hangman.c | 84 ++++++++++++++++++++++++---------------
 1 file changed, 53 insertions(+), 31 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index c7d69fdd..d7b173ab 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -295,9 +295,15 @@ static void context_unban(int fd, unsigned ctx)
 	gem_context_set_param(fd, &param);
 }
 
+enum reset_type {
+	GT_RESET = 1,
+	ENGINE_RESET = 2,
+};
+
 static void
 test_engine_hang(const intel_ctx_t *ctx,
-		 const struct intel_execution_engine2 *e, unsigned int flags)
+		 const struct intel_execution_engine2 *e, unsigned int flags,
+		 enum reset_type reset)
 {
 	const struct intel_execution_engine2 *other;
 	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
@@ -309,6 +315,7 @@ test_engine_hang(const intel_ctx_t *ctx,
 	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
 		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
 
+	igt_assert(reset == GT_RESET || reset == ENGINE_RESET);
 	/*
 	 * Fill all engines with background load.
 	 * This verifies that independent engines are unaffected and gives
@@ -324,7 +331,10 @@ test_engine_hang(const intel_ctx_t *ctx,
 				      .ahnd = ahndN,
 				      .ctx = local_ctx[num_ctx],
 				      .engine = other->flags,
-				      .flags = IGT_SPIN_FENCE_OUT);
+				      .flags = IGT_SPIN_FENCE_OUT |
+					       IGT_SPIN_POLL_RUN);
+		igt_spin_busywait_until_started(spin);
+
 		num_ctx++;
 
 		igt_list_move(&spin->link, &list);
@@ -344,14 +354,43 @@ test_engine_hang(const intel_ctx_t *ctx,
 	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
 	igt_spin_free(device, spin);
 
-	/* But no other engines/clients should be affected */
-	igt_list_for_each_entry_safe(spin, next, &list, link) {
+	/*
+	 * engine-engine-hang: Other engines/clients should not be affected for
+	 * engine reset, so innocent contexts complete successfully once the
+	 * spinner is ended.
+	 *
+	 * gt-engine-hang: All engines/clients are guilty and complete with a
+	 * -EIO fence status, however the background task that was submitted to
+	 * the target engine is innocent and is expected to complete
+	 * successfully.
+	 */
+	igt_list_for_each_entry_safe_reverse(spin, next, &list, link) {
+		bool innocent = reset == ENGINE_RESET;
+		int expect = innocent ? 1 : -EIO;
+
 		ahndN = spin->opts.ahnd;
-		igt_assert(sync_fence_wait(spin->out_fence, 0) == -ETIME);
-		igt_spin_end(spin);
+		if (innocent) {
+			igt_assert_eq(sync_fence_wait(spin->out_fence, 0), -ETIME);
+			igt_spin_end(spin);
+		}
 
-		igt_assert(sync_fence_wait(spin->out_fence, 500) == 0);
-		igt_assert_eq(sync_fence_status(spin->out_fence), 1);
+		if (spin->opts.engine == e->flags) {
+		/*
+		 * gt-reset resets all contexts on all engines. The execlist
+		 * implementation of gt-engine-* tests expected that a
+		 * preemptible background spinner running on the target engine
+		 * should be marked innocent. While i915 can mark such a
+		 * context for execlist mode, GuC scheduling does not guarantee
+		 * that the background spinner can be marked as innocent. Since
+		 * the state of the background spinner depends on the scheduling
+		 * backend, do no validate the state of the background spinner
+		 * for the target engine.
+		 */
+			igt_spin_end(spin);
+		} else {
+			igt_assert_eq(sync_fence_wait(spin->out_fence, 500), 0);
+			igt_assert_eq(sync_fence_status(spin->out_fence), expect);
+		}
 		igt_spin_free(device, spin);
 		put_ahnd(ahndN);
 	}
@@ -439,6 +478,10 @@ static void do_tests(const char *name, const char *prefix,
 {
 	const struct intel_execution_engine2 *e;
 	char buff[256];
+	enum reset_type reset = ENGINE_RESET;
+
+	if (!strncmp(prefix, "gt", 2))
+		reset = GT_RESET;
 
 	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
 	igt_describe(buff);
@@ -454,20 +497,9 @@ static void do_tests(const char *name, const char *prefix,
 	igt_describe(buff);
 	snprintf(buff, sizeof(buff), "%s-engine-hang", prefix);
 	igt_subtest_with_dynamic(buff) {
-                int has_gpu_reset = 0;
-		struct drm_i915_getparam gp = {
-			.param = I915_PARAM_HAS_GPU_RESET,
-			.value = &has_gpu_reset,
-		};
-
-		igt_require(gem_scheduler_has_preemption(device));
-		igt_params_set(device, "reset", "%u", -1);
-                ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
-		igt_require(has_gpu_reset > 1);
-
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_engine_hang(ctx, e, 0);
+				test_engine_hang(ctx, e, 0, reset);
 		}
 	}
 
@@ -475,19 +507,9 @@ static void do_tests(const char *name, const char *prefix,
 	igt_describe(buff);
 	snprintf(buff, sizeof(buff), "%s-engine-error", prefix);
 	igt_subtest_with_dynamic(buff) {
-		int has_gpu_reset = 0;
-		struct drm_i915_getparam gp = {
-			.param = I915_PARAM_HAS_GPU_RESET,
-			.value = &has_gpu_reset,
-		};
-
-		igt_params_set(device, "reset", "%u", -1);
-		ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
-		igt_require(has_gpu_reset > 1);
-
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
+				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS, reset);
 		}
 	}
 }
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [igt-dev] ✓ Fi.CI.BAT: success for i915/hangman: Fix gt hang/error tests (rev2)
  2022-07-28  1:15 [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests Umesh Nerlige Ramappa
@ 2022-07-28  1:53 ` Patchwork
  2022-07-28  9:21 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
  2022-07-28 14:59 ` [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests Kamil Konieczny
  2 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-07-28  1:53 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: igt-dev

[-- Attachment #1: Type: text/plain, Size: 5094 bytes --]

== Series Details ==

Series: i915/hangman: Fix gt hang/error tests (rev2)
URL   : https://patchwork.freedesktop.org/series/103845/
State : success

== Summary ==

CI Bug Log - changes from IGT_6601 -> IGTPW_7573
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/index.html

Participating hosts (41 -> 33)
------------------------------

  Missing    (8): fi-kbl-soraka bat-dg1-5 bat-adlm-1 bat-adlp-4 fi-kbl-guc bat-rplp-1 fi-blb-e6850 fi-bdw-samus 

Known issues
------------

  Here are the changes found in IGTPW_7573 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s3@smem:
    - fi-rkl-11600:       NOTRUN -> [INCOMPLETE][1] ([i915#6179])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/fi-rkl-11600/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@i915_selftest@live@gem:
    - fi-pnv-d510:        NOTRUN -> [DMESG-FAIL][2] ([i915#4528])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/fi-pnv-d510/igt@i915_selftest@live@gem.html

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-bdw-5557u:       [PASS][3] -> [INCOMPLETE][4] ([i915#146])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/fi-bdw-5557u/igt@i915_suspend@basic-s3-without-i915.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/fi-bdw-5557u/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-hsw-g3258:       NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/fi-hsw-g3258/igt@kms_chamelium@common-hpd-after-suspend.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-kbl-7567u:       [DMESG-FAIL][6] ([i915#5334]) -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/fi-kbl-7567u/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
    - fi-hsw-g3258:       [INCOMPLETE][8] ([i915#3303] / [i915#4785]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@requests:
    - fi-pnv-d510:        [DMESG-FAIL][10] ([i915#4528]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/fi-pnv-d510/igt@i915_selftest@live@requests.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/fi-pnv-d510/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@slpc:
    - {bat-dg2-9}:        [DMESG-WARN][12] ([i915#5763]) -> [PASS][13] +6 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/bat-dg2-9/igt@i915_selftest@live@slpc.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/bat-dg2-9/igt@i915_selftest@live@slpc.html

  
#### Warnings ####

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-rkl-11600:       [INCOMPLETE][14] ([i915#5982]) -> [FAIL][15] ([fdo#103375])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
  [i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
  [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
  [i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982
  [i915#6179]: https://gitlab.freedesktop.org/drm/intel/issues/6179


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6601 -> IGTPW_7573

  CI-20190529: 20190529
  CI_DRM_11946: 0e9c43d76a145712da46e935d429ce2a3eea80e8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_7573: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/index.html
  IGT_6601: db15dc4bd58d48703a3883bdcd7c12bef4bd92b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/index.html

[-- Attachment #2: Type: text/html, Size: 5772 bytes --]

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [igt-dev] ✗ Fi.CI.IGT: failure for i915/hangman: Fix gt hang/error tests (rev2)
  2022-07-28  1:15 [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests Umesh Nerlige Ramappa
  2022-07-28  1:53 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/hangman: Fix gt hang/error tests (rev2) Patchwork
@ 2022-07-28  9:21 ` Patchwork
  2022-07-28 14:59 ` [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests Kamil Konieczny
  2 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-07-28  9:21 UTC (permalink / raw)
  To: Umesh Nerlige Ramappa; +Cc: igt-dev

[-- Attachment #1: Type: text/plain, Size: 63632 bytes --]

== Series Details ==

Series: i915/hangman: Fix gt hang/error tests (rev2)
URL   : https://patchwork.freedesktop.org/series/103845/
State : failure

== Summary ==

CI Bug Log - changes from IGT_6601_full -> IGTPW_7573_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_7573_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_7573_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/index.html

Participating hosts (7 -> 10)
------------------------------

  Additional (3): shard-rkl shard-dg1 shard-tglu 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_7573_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_hangman@gt-engine-error@rcs0:
    - shard-snb:          NOTRUN -> [INCOMPLETE][1] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-snb2/igt@i915_hangman@gt-engine-error@rcs0.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_plane_lowres@tiling-none@pipe-b-hdmi-a-1:
    - {shard-dg1}:        NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-dg1-16/igt@kms_plane_lowres@tiling-none@pipe-b-hdmi-a-1.html

  * igt@kms_vblank@pipe-c-query-busy-hang:
    - {shard-dg1}:        NOTRUN -> [TIMEOUT][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-dg1-18/igt@kms_vblank@pipe-c-query-busy-hang.html

  
New tests
---------

  New tests have been introduced between IGT_6601_full and IGTPW_7573_full:

### New IGT tests (100) ###

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-linear-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-linear-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-linear-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-linear-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-linear-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-x-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-x-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-x-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-x-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-x-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-rc_ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.21] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-rc_ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-rc_ccs-cc-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-rc_ccs-cc-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-rc_ccs-cc-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.16] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-rc_ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-rc_ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-rc_ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-rc_ccs-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.25] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-rc_ccs-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-a-y-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-linear-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.16] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-linear-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-linear-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-linear-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-linear-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.16] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-x-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-x-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-x-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-x-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-x-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-rc_ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-rc_ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-rc_ccs-cc-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-rc_ccs-cc-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-rc_ccs-cc-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.16] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-rc_ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-rc_ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-rc_ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-rc_ccs-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.24] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-rc_ccs-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-b-y-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-linear-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-linear-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-linear-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-linear-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-linear-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-x-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-x-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-x-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-x-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-x-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-rc_ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-rc_ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-rc_ccs-cc-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.16] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-rc_ccs-cc-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-rc_ccs-cc-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.16] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-rc_ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-rc_ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-rc_ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-rc_ccs-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.25] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-rc_ccs-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-c-y-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-linear-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-linear-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-linear-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-linear-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-linear-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-x-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-x-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-x-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-x-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-x-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-rc_ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-rc_ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-rc_ccs-cc-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-rc_ccs-cc-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-rc_ccs-cc-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-rc_ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-rc_ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-rc_ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-rc_ccs-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.23] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-rc_ccs-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-to-y-rc_ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@hdmi-a-4-pipe-d-y-to-y-rc_ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  

Known issues
------------

  Here are the changes found in IGTPW_7573_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@engines-persistence:
    - shard-snb:          NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-snb4/igt@gem_ctx_persistence@engines-persistence.html

  * igt@gem_eio@reset-stress:
    - shard-snb:          [PASS][5] -> [TIMEOUT][6] ([i915#3427])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-snb7/igt@gem_eio@reset-stress.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-snb7/igt@gem_eio@reset-stress.html

  * igt@gem_eio@unwedge-stress:
    - shard-iclb:         [PASS][7] -> [TIMEOUT][8] ([i915#3070])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-iclb7/igt@gem_eio@unwedge-stress.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb3/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-kbl:          [PASS][9] -> [SKIP][10] ([fdo#109271]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-kbl7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl6/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs1:
    - shard-iclb:         NOTRUN -> [FAIL][11] ([i915#2842])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-tglb:         NOTRUN -> [SKIP][12] ([fdo#109283])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb7/igt@gem_exec_params@rsvd2-dirt.html
    - shard-iclb:         NOTRUN -> [SKIP][13] ([fdo#109283])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb6/igt@gem_exec_params@rsvd2-dirt.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-apl:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
    - shard-tglb:         NOTRUN -> [SKIP][15] ([i915#4613])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb3/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
    - shard-glk:          NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk9/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
    - shard-iclb:         NOTRUN -> [SKIP][17] ([i915#4613])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb2/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@random:
    - shard-kbl:          NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) +1 similar issue
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl1/igt@gem_lmem_swapping@random.html

  * igt@gem_media_vme:
    - shard-tglb:         NOTRUN -> [SKIP][19] ([i915#284])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb7/igt@gem_media_vme.html

  * igt@gem_pread@exhaustion:
    - shard-apl:          NOTRUN -> [WARN][20] ([i915#2658])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl1/igt@gem_pread@exhaustion.html
    - shard-tglb:         NOTRUN -> [WARN][21] ([i915#2658])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb3/igt@gem_pread@exhaustion.html
    - shard-glk:          NOTRUN -> [WARN][22] ([i915#2658])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk5/igt@gem_pread@exhaustion.html
    - shard-iclb:         NOTRUN -> [WARN][23] ([i915#2658])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb3/igt@gem_pread@exhaustion.html
    - shard-kbl:          NOTRUN -> [WARN][24] ([i915#2658])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl7/igt@gem_pread@exhaustion.html
    - shard-snb:          NOTRUN -> [WARN][25] ([i915#2658])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-snb6/igt@gem_pread@exhaustion.html

  * igt@gem_render_copy@yf-tiled-to-vebox-y-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][26] ([i915#768]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb5/igt@gem_render_copy@yf-tiled-to-vebox-y-tiled.html

  * igt@gem_softpin@evict-single-offset:
    - shard-kbl:          NOTRUN -> [FAIL][27] ([i915#4171])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl6/igt@gem_softpin@evict-single-offset.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][28] ([i915#3297])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb5/igt@gem_userptr_blits@dmabuf-unsync.html
    - shard-iclb:         NOTRUN -> [SKIP][29] ([i915#3297])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb4/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk:          [PASS][30] -> [DMESG-WARN][31] ([i915#5566] / [i915#716])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-glk6/igt@gen9_exec_parse@allowed-single.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk2/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-iclb:         NOTRUN -> [SKIP][32] ([i915#2856]) +2 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb2/igt@gen9_exec_parse@bb-start-far.html
    - shard-tglb:         NOTRUN -> [SKIP][33] ([i915#2527] / [i915#2856]) +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb1/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-apl:          [PASS][34] -> [SKIP][35] ([fdo#109271])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-apl7/igt@i915_pm_dc@dc9-dpms.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl2/igt@i915_pm_dc@dc9-dpms.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         NOTRUN -> [WARN][36] ([i915#2684])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html
    - shard-tglb:         NOTRUN -> [WARN][37] ([i915#2681])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb2/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
    - shard-tglb:         NOTRUN -> [SKIP][38] ([fdo#111644] / [i915#1397] / [i915#2411])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb5/igt@i915_pm_rpm@modeset-non-lpsp.html
    - shard-iclb:         NOTRUN -> [SKIP][39] ([fdo#110892])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb8/igt@i915_pm_rpm@modeset-non-lpsp.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-iclb:         NOTRUN -> [SKIP][40] ([i915#5903])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb1/igt@i915_suspend@basic-s3-without-i915.html
    - shard-tglb:         NOTRUN -> [SKIP][41] ([i915#5903])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb2/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][42] ([i915#5286]) +2 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb2/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
    - shard-iclb:         NOTRUN -> [SKIP][43] ([i915#5286]) +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb1/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
    - shard-glk:          NOTRUN -> [SKIP][44] ([fdo#109271]) +65 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk7/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
    - shard-iclb:         NOTRUN -> [SKIP][45] ([fdo#110723]) +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb7/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][46] ([fdo#111615] / [i915#3689]) +3 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb3/igt@kms_ccs@pipe-a-bad-pixel-format-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][47] ([i915#3689] / [i915#3886]) +3 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][48] ([fdo#109271] / [i915#3886]) +4 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk8/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +10 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl2/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_rc_ccs_cc:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#6095]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb5/igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc:
    - shard-tglb:         NOTRUN -> [SKIP][51] ([i915#3689] / [i915#6095])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb1/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][52] ([fdo#109278] / [i915#3886]) +4 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb6/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
    - shard-kbl:          NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#3886]) +9 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl4/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][54] ([fdo#109271]) +177 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl6/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_rc_ccs.html

  * igt@kms_ccs@pipe-d-random-ccs-data-4_tiled_dg2_rc_ccs_cc:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([i915#3689])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb1/igt@kms_ccs@pipe-d-random-ccs-data-4_tiled_dg2_rc_ccs_cc.html

  * igt@kms_chamelium@dp-crc-single:
    - shard-apl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl2/igt@kms_chamelium@dp-crc-single.html
    - shard-tglb:         NOTRUN -> [SKIP][57] ([fdo#109284] / [fdo#111827]) +3 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb2/igt@kms_chamelium@dp-crc-single.html
    - shard-glk:          NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk1/igt@kms_chamelium@dp-crc-single.html

  * igt@kms_color_chamelium@pipe-c-ctm-0-75:
    - shard-kbl:          NOTRUN -> [SKIP][59] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl1/igt@kms_color_chamelium@pipe-c-ctm-0-75.html

  * igt@kms_color_chamelium@pipe-c-degamma:
    - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109284] / [fdo#111827]) +3 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb2/igt@kms_color_chamelium@pipe-c-degamma.html
    - shard-snb:          NOTRUN -> [SKIP][61] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-snb7/igt@kms_color_chamelium@pipe-c-degamma.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-tglb:         NOTRUN -> [SKIP][62] ([i915#3116] / [i915#3299])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb5/igt@kms_content_protection@dp-mst-type-1.html
    - shard-iclb:         NOTRUN -> [SKIP][63] ([i915#3116])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb8/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@srm:
    - shard-kbl:          NOTRUN -> [TIMEOUT][64] ([i915#1319])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl7/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-sliding@pipe-a-edp-1-32x32:
    - shard-tglb:         NOTRUN -> [SKIP][65] ([i915#4462]) +7 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb7/igt@kms_cursor_crc@cursor-sliding@pipe-a-edp-1-32x32.html

  * igt@kms_cursor_crc@cursor-sliding@pipe-a-edp-1-512x512:
    - shard-iclb:         NOTRUN -> [SKIP][66] ([i915#3359]) +5 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb6/igt@kms_cursor_crc@cursor-sliding@pipe-a-edp-1-512x512.html

  * igt@kms_cursor_crc@cursor-sliding@pipe-b-edp-1-512x512:
    - shard-tglb:         NOTRUN -> [SKIP][67] ([i915#3359]) +7 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb7/igt@kms_cursor_crc@cursor-sliding@pipe-b-edp-1-512x512.html

  * igt@kms_cursor_crc@cursor-sliding@pipe-c-edp-1-32x10:
    - shard-iclb:         NOTRUN -> [SKIP][68] ([i915#4462]) +5 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb6/igt@kms_cursor_crc@cursor-sliding@pipe-c-edp-1-32x10.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1:
    - shard-apl:          [PASS][69] -> [DMESG-WARN][70] ([i915#180]) +2 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-apl3/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl8/igt@kms_cursor_crc@cursor-suspend@pipe-a-dp-1.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [PASS][71] -> [FAIL][72] ([i915#72])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb@varying-size:
    - shard-tglb:         NOTRUN -> [SKIP][73] ([fdo#109274] / [fdo#111825]) +5 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb3/igt@kms_cursor_legacy@cursorb-vs-flipb@varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor@toggle:
    - shard-iclb:         [PASS][74] -> [FAIL][75] ([i915#2346]) +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-iclb3/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor@toggle.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-tglb:         NOTRUN -> [SKIP][76] ([fdo#109274] / [fdo#111825] / [i915#3637] / [i915#3966])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb1/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-tglb:         NOTRUN -> [SKIP][77] ([fdo#109274] / [fdo#111825] / [i915#3637]) +3 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb3/igt@kms_flip@2x-flip-vs-fences-interruptible.html
    - shard-iclb:         NOTRUN -> [SKIP][78] ([fdo#109274]) +10 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb7/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1:
    - shard-kbl:          [PASS][79] -> [FAIL][80] ([i915#79])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-kbl:          [PASS][81] -> [DMESG-WARN][82] ([i915#180]) +4 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-edp1:
    - shard-iclb:         [PASS][83] -> [DMESG-WARN][84] ([i915#2867])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-iclb5/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb5/igt@kms_flip@flip-vs-suspend-interruptible@c-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-tglb:         NOTRUN -> [SKIP][85] ([i915#2672])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][86] ([i915#3555])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][87] ([i915#2672]) +10 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
    - shard-glk:          [PASS][88] -> [FAIL][89] ([i915#1888] / [i915#2546])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-glk2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk9/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
    - shard-iclb:         [PASS][90] -> [FAIL][91] ([i915#1888] / [i915#2546])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([fdo#109280] / [fdo#111825]) +11 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-tglb:         NOTRUN -> [SKIP][93] ([i915#6497]) +2 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-iclb:         NOTRUN -> [SKIP][94] ([fdo#109280]) +11 similar issues
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch@pipe-a-dp-1:
    - shard-kbl:          NOTRUN -> [FAIL][95] ([i915#1188])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl6/igt@kms_hdr@bpc-switch@pipe-a-dp-1.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][96] ([i915#265])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
    - shard-kbl:          NOTRUN -> [FAIL][97] ([i915#265])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
    - shard-kbl:          NOTRUN -> [FAIL][98] ([fdo#108145] / [i915#265])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl6/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
    - shard-tglb:         NOTRUN -> [SKIP][99] ([fdo#111615]) +4 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb5/igt@kms_plane_multiple@atomic-pipe-a-tiling-yf.html

  * igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
    - shard-apl:          NOTRUN -> [SKIP][100] ([fdo#109271]) +129 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl8/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-edp-1:
    - shard-iclb:         NOTRUN -> [SKIP][101] ([i915#5176]) +2 similar issues
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb4/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-edp-1.html

  * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-d-edp-1:
    - shard-tglb:         NOTRUN -> [SKIP][102] ([i915#5176]) +3 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb1/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-d-edp-1.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
    - shard-tglb:         NOTRUN -> [SKIP][103] ([i915#2920])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb7/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
    - shard-iclb:         NOTRUN -> [SKIP][104] ([fdo#111068] / [i915#658])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-apl:          NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#658]) +1 similar issue
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl1/igt@kms_psr2_su@page_flip-p010.html
    - shard-tglb:         NOTRUN -> [SKIP][106] ([i915#1911])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb1/igt@kms_psr2_su@page_flip-p010.html
    - shard-glk:          NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#658]) +1 similar issue
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk5/igt@kms_psr2_su@page_flip-p010.html
    - shard-iclb:         NOTRUN -> [SKIP][108] ([fdo#109642] / [fdo#111068] / [i915#658])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb3/igt@kms_psr2_su@page_flip-p010.html
    - shard-kbl:          NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#658]) +1 similar issue
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl1/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@psr2_primary_blt:
    - shard-iclb:         [PASS][110] -> [SKIP][111] ([fdo#109441]) +1 similar issue
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-iclb2/igt@kms_psr@psr2_primary_blt.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb1/igt@kms_psr@psr2_primary_blt.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-snb:          NOTRUN -> [SKIP][112] ([fdo#109271]) +138 similar issues
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-snb7/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-tglb:         NOTRUN -> [SKIP][113] ([fdo#111615] / [i915#5289])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
    - shard-kbl:          [PASS][114] -> [INCOMPLETE][115] ([i915#3614] / [i915#4939])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html

  * igt@kms_vblank@pipe-d-query-forked-hang:
    - shard-iclb:         NOTRUN -> [SKIP][116] ([fdo#109278]) +11 similar issues
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb7/igt@kms_vblank@pipe-d-query-forked-hang.html

  * igt@kms_writeback@writeback-check-output:
    - shard-kbl:          NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#2437])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl7/igt@kms_writeback@writeback-check-output.html

  * igt@nouveau_crc@pipe-b-ctx-flip-detection:
    - shard-tglb:         NOTRUN -> [SKIP][118] ([i915#2530])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb1/igt@nouveau_crc@pipe-b-ctx-flip-detection.html
    - shard-iclb:         NOTRUN -> [SKIP][119] ([i915#2530])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb2/igt@nouveau_crc@pipe-b-ctx-flip-detection.html

  * igt@prime_udl:
    - shard-tglb:         NOTRUN -> [SKIP][120] ([fdo#109291])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb1/igt@prime_udl.html
    - shard-iclb:         NOTRUN -> [SKIP][121] ([fdo#109291])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb2/igt@prime_udl.html

  * igt@sysfs_clients@pidname:
    - shard-apl:          NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#2994]) +1 similar issue
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl4/igt@sysfs_clients@pidname.html
    - shard-tglb:         NOTRUN -> [SKIP][123] ([i915#2994])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb1/igt@sysfs_clients@pidname.html
    - shard-glk:          NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#2994])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk2/igt@sysfs_clients@pidname.html
    - shard-iclb:         NOTRUN -> [SKIP][125] ([i915#2994])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb4/igt@sysfs_clients@pidname.html

  * igt@sysfs_clients@sema-10:
    - shard-kbl:          NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#2994]) +2 similar issues
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl7/igt@sysfs_clients@sema-10.html

  
#### Possible fixes ####

  * igt@gem_eio@kms:
    - shard-tglb:         [TIMEOUT][127] ([i915#3063]) -> [PASS][128] +1 similar issue
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-tglb1/igt@gem_eio@kms.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb7/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-iclb:         [SKIP][129] ([i915#4525]) -> [PASS][130] +1 similar issue
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-iclb8/igt@gem_exec_balancer@parallel-keep-submit-fence.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-tglb:         [FAIL][131] ([i915#2842]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-tglb7/igt@gem_exec_fair@basic-none-share@rcs0.html
    - shard-glk:          [FAIL][133] ([i915#2842]) -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-glk3/igt@gem_exec_fair@basic-none-share@rcs0.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk7/igt@gem_exec_fair@basic-none-share@rcs0.html
    - shard-kbl:          [FAIL][135] ([i915#2842]) -> [PASS][136]
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-kbl4/igt@gem_exec_fair@basic-none-share@rcs0.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl1/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-apl:          [FAIL][137] ([i915#2842]) -> [PASS][138] +1 similar issue
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-kbl:          [DMESG-WARN][139] ([i915#180]) -> [PASS][140] +1 similar issue
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-kbl6/igt@i915_suspend@fence-restore-untiled.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl1/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
    - shard-kbl:          [FAIL][141] ([i915#1188]) -> [PASS][142]
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-kbl4/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-kbl6/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
    - shard-apl:          [DMESG-WARN][143] ([i915#180]) -> [PASS][144] +1 similar issue
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html

  * igt@kms_plane_lowres@tiling-yf@pipe-a-hdmi-a-1:
    - shard-glk:          [DMESG-WARN][145] ([i915#118] / [i915#1888]) -> [PASS][146]
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-glk7/igt@kms_plane_lowres@tiling-yf@pipe-a-hdmi-a-1.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-glk9/igt@kms_plane_lowres@tiling-yf@pipe-a-hdmi-a-1.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [SKIP][147] ([fdo#109441]) -> [PASS][148] +1 similar issue
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html

  
#### Warnings ####

  * igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
    - shard-iclb:         [SKIP][149] ([i915#2920]) -> [SKIP][150] ([i915#658])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-iclb7/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-apl6/igt@runner@aborted.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-apl6/igt@runner@aborted.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-apl4/igt@runner@aborted.html
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-apl6/igt@runner@aborted.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-apl3/igt@runner@aborted.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6601/shard-apl8/igt@runner@aborted.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl3/igt@runner@aborted.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl3/igt@runner@aborted.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl8/igt@runner@aborted.html
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl3/igt@runner@aborted.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/shard-apl8/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
  [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
  [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
  [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
  [i915#2532]: https://gitlab.freedesktop.org/drm/intel/issues/2532
  [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
  [i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
  [i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
  [i915#3427]: https://gitlab.freedesktop.org/drm/intel/issues/3427
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3614]: https://gitlab.freedesktop.org/drm/intel/issues/3614
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
  [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
  [i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
  [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
  [i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
  [i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
  [i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4462]: https://gitlab.freedesktop.org/drm/intel/issues/4462
  [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
  [i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
  [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
  [i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
  [i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
  [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
  [i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
  [i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
  [i915#4904]: https://gitlab.freedesktop.org/drm/intel/issues/4904
  [i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
  [i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941
  [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
  [i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
  [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
  [i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6331]: https://gitlab.freedesktop.org/drm/intel/issues/6331
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
  [i915#6403]: https://gitlab.freedesktop.org/drm/intel/issues/6403
  [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6458]: https://gitlab.freedesktop.org/drm/intel/issues/6458
  [i915#6463]: https://gitlab.freedesktop.org/drm/intel/issues/6463
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6601 -> IGTPW_7573

  CI-20190529: 20190529
  CI_DRM_11946: 0e9c43d76a145712da46e935d429ce2a3eea80e8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_7573: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/index.html
  IGT_6601: db15dc4bd58d48703a3883bdcd7c12bef4bd92b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7573/index.html

[-- Attachment #2: Type: text/html, Size: 67992 bytes --]

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests
  2022-07-28  1:15 [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests Umesh Nerlige Ramappa
  2022-07-28  1:53 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/hangman: Fix gt hang/error tests (rev2) Patchwork
  2022-07-28  9:21 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-07-28 14:59 ` Kamil Konieczny
  2022-07-28 15:14   ` Umesh Nerlige Ramappa
  2 siblings, 1 reply; 12+ messages in thread
From: Kamil Konieczny @ 2022-07-28 14:59 UTC (permalink / raw)
  To: igt-dev

Hi Umesh,

On 2022-07-28 at 01:15:59 +0000, Umesh Nerlige Ramappa wrote:
> gt-engine-hang and gt-engine-error tests were still using reset=2
> setting so that ended up just doing an engine reset. Fix the tests so
> that they actually do the gt specific reset and set the expectations
> correctly.
> 
> In some rare failures, some of the background spinners show up as
> innocent and keep spinning after the hang recovery. This can only happen
> if the spinners did not start for some reason. Check that the spinners
> actually started before submitting a hanging batch.
> 
> For engine specific hang, only one context is marked guilty, but for a
> gt hang all contexts are marked guilty. Check for different expected
> behavior for engine vs. gt reset.
> 
> v2:
> - gt-reset resets all contexts on all engines. The execlist implementation
>   of gt-engine-* tests expected that a preemptible background spinner
>   running on the target engine should be marked innocent. While i915 can
>   mark such a context for execlist mode, GuC scheduling does not guarantee
>   that the background spinner can be marked as innocent. Since the state
>   of the background spinner depends on the scheduling backend, do no
>   validate the state of the background spinner for the target engine.
> 
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/i915/i915_hangman.c | 84 ++++++++++++++++++++++++---------------
>  1 file changed, 53 insertions(+), 31 deletions(-)
> 
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index c7d69fdd..d7b173ab 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -295,9 +295,15 @@ static void context_unban(int fd, unsigned ctx)
>  	gem_context_set_param(fd, &param);
>  }
>  
> +enum reset_type {
> +	GT_RESET = 1,
> +	ENGINE_RESET = 2,
> +};
> +
>  static void
>  test_engine_hang(const intel_ctx_t *ctx,
> -		 const struct intel_execution_engine2 *e, unsigned int flags)
> +		 const struct intel_execution_engine2 *e, unsigned int flags,
> +		 enum reset_type reset)
>  {
>  	const struct intel_execution_engine2 *other;
>  	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
> @@ -309,6 +315,7 @@ test_engine_hang(const intel_ctx_t *ctx,
>  	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
>  		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
>  
> +	igt_assert(reset == GT_RESET || reset == ENGINE_RESET);
>  	/*
>  	 * Fill all engines with background load.
>  	 * This verifies that independent engines are unaffected and gives
> @@ -324,7 +331,10 @@ test_engine_hang(const intel_ctx_t *ctx,
>  				      .ahnd = ahndN,
>  				      .ctx = local_ctx[num_ctx],
>  				      .engine = other->flags,
> -				      .flags = IGT_SPIN_FENCE_OUT);
> +				      .flags = IGT_SPIN_FENCE_OUT |
> +					       IGT_SPIN_POLL_RUN);
> +		igt_spin_busywait_until_started(spin);
> +
>  		num_ctx++;
>  
>  		igt_list_move(&spin->link, &list);
> @@ -344,14 +354,43 @@ test_engine_hang(const intel_ctx_t *ctx,
>  	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
>  	igt_spin_free(device, spin);
>  
> -	/* But no other engines/clients should be affected */
> -	igt_list_for_each_entry_safe(spin, next, &list, link) {
> +	/*
> +	 * engine-engine-hang: Other engines/clients should not be affected for
> +	 * engine reset, so innocent contexts complete successfully once the
> +	 * spinner is ended.
> +	 *
> +	 * gt-engine-hang: All engines/clients are guilty and complete with a
> +	 * -EIO fence status, however the background task that was submitted to
> +	 * the target engine is innocent and is expected to complete
> +	 * successfully.
> +	 */

imho we should keep test for execlist behaviour. It is not clear
why background task survives ? You stated "All ... are guilty" ?
Isn't this a race between completing and resetting GT ?

> +	igt_list_for_each_entry_safe_reverse(spin, next, &list, link) {
> +		bool innocent = reset == ENGINE_RESET;
> +		int expect = innocent ? 1 : -EIO;
> +
>  		ahndN = spin->opts.ahnd;
> -		igt_assert(sync_fence_wait(spin->out_fence, 0) == -ETIME);
> -		igt_spin_end(spin);
> +		if (innocent) {
> +			igt_assert_eq(sync_fence_wait(spin->out_fence, 0), -ETIME);
> +			igt_spin_end(spin);
> +		}
>  
> -		igt_assert(sync_fence_wait(spin->out_fence, 500) == 0);
> -		igt_assert_eq(sync_fence_status(spin->out_fence), 1);
> +		if (spin->opts.engine == e->flags) {
> +		/*
> +		 * gt-reset resets all contexts on all engines. The execlist
> +		 * implementation of gt-engine-* tests expected that a
> +		 * preemptible background spinner running on the target engine
> +		 * should be marked innocent. While i915 can mark such a
> +		 * context for execlist mode, GuC scheduling does not guarantee
> +		 * that the background spinner can be marked as innocent. Since
> +		 * the state of the background spinner depends on the scheduling
> +		 * backend, do no validate the state of the background spinner
> +		 * for the target engine.
> +		 */
> +			igt_spin_end(spin);
> +		} else {
> +			igt_assert_eq(sync_fence_wait(spin->out_fence, 500), 0);
> +			igt_assert_eq(sync_fence_status(spin->out_fence), expect);
> +		}
>  		igt_spin_free(device, spin);
>  		put_ahnd(ahndN);
>  	}
> @@ -439,6 +478,10 @@ static void do_tests(const char *name, const char *prefix,
>  {
>  	const struct intel_execution_engine2 *e;
>  	char buff[256];
> +	enum reset_type reset = ENGINE_RESET;
> +
> +	if (!strncmp(prefix, "gt", 2))
> +		reset = GT_RESET;
>  
>  	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
>  	igt_describe(buff);
> @@ -454,20 +497,9 @@ static void do_tests(const char *name, const char *prefix,
>  	igt_describe(buff);
>  	snprintf(buff, sizeof(buff), "%s-engine-hang", prefix);
>  	igt_subtest_with_dynamic(buff) {
> -                int has_gpu_reset = 0;
> -		struct drm_i915_getparam gp = {
> -			.param = I915_PARAM_HAS_GPU_RESET,
> -			.value = &has_gpu_reset,
> -		};
> -
> -		igt_require(gem_scheduler_has_preemption(device));
> -		igt_params_set(device, "reset", "%u", -1);
> -                ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
> -		igt_require(has_gpu_reset > 1);
> -
>  		for_each_ctx_engine(device, ctx, e) {
>  			igt_dynamic_f("%s", e->name)
> -				test_engine_hang(ctx, e, 0);
> +				test_engine_hang(ctx, e, 0, reset);
>  		}
>  	}
>  
> @@ -475,19 +507,9 @@ static void do_tests(const char *name, const char *prefix,
>  	igt_describe(buff);
>  	snprintf(buff, sizeof(buff), "%s-engine-error", prefix);
>  	igt_subtest_with_dynamic(buff) {
> -		int has_gpu_reset = 0;
> -		struct drm_i915_getparam gp = {
> -			.param = I915_PARAM_HAS_GPU_RESET,
> -			.value = &has_gpu_reset,
> -		};
> -
> -		igt_params_set(device, "reset", "%u", -1);
> -		ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
> -		igt_require(has_gpu_reset > 1);
> -

imho we need this code in test_engine_hang for execlist
subbmission for gt-engine-hang case.

Regards,
Kamil

>  		for_each_ctx_engine(device, ctx, e) {
>  			igt_dynamic_f("%s", e->name)
> -				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
> +				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS, reset);
>  		}
>  	}
>  }
> -- 
> 2.25.1
> 

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests
  2022-07-28 14:59 ` [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests Kamil Konieczny
@ 2022-07-28 15:14   ` Umesh Nerlige Ramappa
  2022-07-29 18:35     ` Umesh Nerlige Ramappa
  0 siblings, 1 reply; 12+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-07-28 15:14 UTC (permalink / raw)
  To: Kamil Konieczny, igt-dev

On Thu, Jul 28, 2022 at 04:59:53PM +0200, Kamil Konieczny wrote:
>Hi Umesh,
>
>On 2022-07-28 at 01:15:59 +0000, Umesh Nerlige Ramappa wrote:
>> gt-engine-hang and gt-engine-error tests were still using reset=2
>> setting so that ended up just doing an engine reset. Fix the tests so
>> that they actually do the gt specific reset and set the expectations
>> correctly.
>>
>> In some rare failures, some of the background spinners show up as
>> innocent and keep spinning after the hang recovery. This can only happen
>> if the spinners did not start for some reason. Check that the spinners
>> actually started before submitting a hanging batch.
>>
>> For engine specific hang, only one context is marked guilty, but for a
>> gt hang all contexts are marked guilty. Check for different expected
>> behavior for engine vs. gt reset.
>>
>> v2:
>> - gt-reset resets all contexts on all engines. The execlist implementation
>>   of gt-engine-* tests expected that a preemptible background spinner
>>   running on the target engine should be marked innocent. While i915 can
>>   mark such a context for execlist mode, GuC scheduling does not guarantee
>>   that the background spinner can be marked as innocent. Since the state
>>   of the background spinner depends on the scheduling backend, do no
>>   validate the state of the background spinner for the target engine.
>>
>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> ---
>>  tests/i915/i915_hangman.c | 84 ++++++++++++++++++++++++---------------
>>  1 file changed, 53 insertions(+), 31 deletions(-)
>>
>> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>> index c7d69fdd..d7b173ab 100644
>> --- a/tests/i915/i915_hangman.c
>> +++ b/tests/i915/i915_hangman.c
>> @@ -295,9 +295,15 @@ static void context_unban(int fd, unsigned ctx)
>>  	gem_context_set_param(fd, &param);
>>  }
>>
>> +enum reset_type {
>> +	GT_RESET = 1,
>> +	ENGINE_RESET = 2,
>> +};
>> +
>>  static void
>>  test_engine_hang(const intel_ctx_t *ctx,
>> -		 const struct intel_execution_engine2 *e, unsigned int flags)
>> +		 const struct intel_execution_engine2 *e, unsigned int flags,
>> +		 enum reset_type reset)
>>  {
>>  	const struct intel_execution_engine2 *other;
>>  	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
>> @@ -309,6 +315,7 @@ test_engine_hang(const intel_ctx_t *ctx,
>>  	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
>>  		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
>>
>> +	igt_assert(reset == GT_RESET || reset == ENGINE_RESET);
>>  	/*
>>  	 * Fill all engines with background load.
>>  	 * This verifies that independent engines are unaffected and gives
>> @@ -324,7 +331,10 @@ test_engine_hang(const intel_ctx_t *ctx,
>>  				      .ahnd = ahndN,
>>  				      .ctx = local_ctx[num_ctx],
>>  				      .engine = other->flags,
>> -				      .flags = IGT_SPIN_FENCE_OUT);
>> +				      .flags = IGT_SPIN_FENCE_OUT |
>> +					       IGT_SPIN_POLL_RUN);
>> +		igt_spin_busywait_until_started(spin);
>> +
>>  		num_ctx++;
>>
>>  		igt_list_move(&spin->link, &list);
>> @@ -344,14 +354,43 @@ test_engine_hang(const intel_ctx_t *ctx,
>>  	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
>>  	igt_spin_free(device, spin);
>>
>> -	/* But no other engines/clients should be affected */
>> -	igt_list_for_each_entry_safe(spin, next, &list, link) {
>> +	/*
>> +	 * engine-engine-hang: Other engines/clients should not be affected for
>> +	 * engine reset, so innocent contexts complete successfully once the
>> +	 * spinner is ended.
>> +	 *
>> +	 * gt-engine-hang: All engines/clients are guilty and complete with a
>> +	 * -EIO fence status, however the background task that was submitted to
>> +	 * the target engine is innocent and is expected to complete
>> +	 * successfully.
>> +	 */
>
>imho we should keep test for execlist behaviour. It is not clear
>why background task survives ? You stated "All ... are guilty" ?
>Isn't this a race between completing and resetting GT ?

With execlist mode, kmd has control over preempting the background task 
and saving it's state. With GuC KMD has no such control to save the 
state of select spinners.

All execlist behavior in this test is retained, except for one - the 
check for the state of the background spinner on the target engine. The 
state assumed by execlist backend cannot be guaranteed by GuC backend.

>
>> +	igt_list_for_each_entry_safe_reverse(spin, next, &list, link) {
>> +		bool innocent = reset == ENGINE_RESET;
>> +		int expect = innocent ? 1 : -EIO;
>> +
>>  		ahndN = spin->opts.ahnd;
>> -		igt_assert(sync_fence_wait(spin->out_fence, 0) == -ETIME);
>> -		igt_spin_end(spin);
>> +		if (innocent) {
>> +			igt_assert_eq(sync_fence_wait(spin->out_fence, 0), -ETIME);
>> +			igt_spin_end(spin);
>> +		}
>>
>> -		igt_assert(sync_fence_wait(spin->out_fence, 500) == 0);
>> -		igt_assert_eq(sync_fence_status(spin->out_fence), 1);
>> +		if (spin->opts.engine == e->flags) {

I think the above condition should also check for GT_RESET. I need to 
add that.

>> +		/*
>> +		 * gt-reset resets all contexts on all engines. The execlist
>> +		 * implementation of gt-engine-* tests expected that a
>> +		 * preemptible background spinner running on the target engine
>> +		 * should be marked innocent. While i915 can mark such a
>> +		 * context for execlist mode, GuC scheduling does not guarantee
>> +		 * that the background spinner can be marked as innocent. Since
>> +		 * the state of the background spinner depends on the scheduling
>> +		 * backend, do no validate the state of the background spinner
>> +		 * for the target engine.
>> +		 */

In relation to my earlier comment, this is the only place where the 
asserts are omitted. This is because of the caveat mentioned in the 
comment above.

>> +			igt_spin_end(spin);
>> +		} else {
>> +			igt_assert_eq(sync_fence_wait(spin->out_fence, 500), 0);
>> +			igt_assert_eq(sync_fence_status(spin->out_fence), expect);
>> +		}
>>  		igt_spin_free(device, spin);
>>  		put_ahnd(ahndN);
>>  	}
>> @@ -439,6 +478,10 @@ static void do_tests(const char *name, const char *prefix,
>>  {
>>  	const struct intel_execution_engine2 *e;
>>  	char buff[256];
>> +	enum reset_type reset = ENGINE_RESET;
>> +
>> +	if (!strncmp(prefix, "gt", 2))
>> +		reset = GT_RESET;
>>
>>  	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
>>  	igt_describe(buff);
>> @@ -454,20 +497,9 @@ static void do_tests(const char *name, const char *prefix,
>>  	igt_describe(buff);
>>  	snprintf(buff, sizeof(buff), "%s-engine-hang", prefix);
>>  	igt_subtest_with_dynamic(buff) {
>> -                int has_gpu_reset = 0;
>> -		struct drm_i915_getparam gp = {
>> -			.param = I915_PARAM_HAS_GPU_RESET,
>> -			.value = &has_gpu_reset,
>> -		};
>> -
>> -		igt_require(gem_scheduler_has_preemption(device));
>> -		igt_params_set(device, "reset", "%u", -1);
>> -                ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
>> -		igt_require(has_gpu_reset > 1);
>> -
>>  		for_each_ctx_engine(device, ctx, e) {
>>  			igt_dynamic_f("%s", e->name)
>> -				test_engine_hang(ctx, e, 0);
>> +				test_engine_hang(ctx, e, 0, reset);
>>  		}
>>  	}
>>
>> @@ -475,19 +507,9 @@ static void do_tests(const char *name, const char *prefix,
>>  	igt_describe(buff);
>>  	snprintf(buff, sizeof(buff), "%s-engine-error", prefix);
>>  	igt_subtest_with_dynamic(buff) {
>> -		int has_gpu_reset = 0;
>> -		struct drm_i915_getparam gp = {
>> -			.param = I915_PARAM_HAS_GPU_RESET,
>> -			.value = &has_gpu_reset,
>> -		};
>> -
>> -		igt_params_set(device, "reset", "%u", -1);
>> -		ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
>> -		igt_require(has_gpu_reset > 1);
>> -
>
>imho we need this code in test_engine_hang for execlist
>subbmission for gt-engine-hang case.

for gt-* tests, the fixture in igt_main has 

hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);

That should suffice.

Regards,
Umesh


>
>Regards,
>Kamil
>
>>  		for_each_ctx_engine(device, ctx, e) {
>>  			igt_dynamic_f("%s", e->name)
>> -				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
>> +				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS, reset);
>>  		}
>>  	}
>>  }
>> --
>> 2.25.1
>>

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests
  2022-07-28 15:14   ` Umesh Nerlige Ramappa
@ 2022-07-29 18:35     ` Umesh Nerlige Ramappa
  0 siblings, 0 replies; 12+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-07-29 18:35 UTC (permalink / raw)
  To: Kamil Konieczny, igt-dev

On Thu, Jul 28, 2022 at 08:14:44AM -0700, Umesh Nerlige Ramappa wrote:
>On Thu, Jul 28, 2022 at 04:59:53PM +0200, Kamil Konieczny wrote:
>>Hi Umesh,
>>
>>On 2022-07-28 at 01:15:59 +0000, Umesh Nerlige Ramappa wrote:
>>>gt-engine-hang and gt-engine-error tests were still using reset=2
>>>setting so that ended up just doing an engine reset. Fix the tests so
>>>that they actually do the gt specific reset and set the expectations
>>>correctly.
>>>
>>>In some rare failures, some of the background spinners show up as
>>>innocent and keep spinning after the hang recovery. This can only happen
>>>if the spinners did not start for some reason. Check that the spinners
>>>actually started before submitting a hanging batch.
>>>
>>>For engine specific hang, only one context is marked guilty, but for a
>>>gt hang all contexts are marked guilty. Check for different expected
>>>behavior for engine vs. gt reset.
>>>
>>>v2:
>>>- gt-reset resets all contexts on all engines. The execlist implementation
>>>  of gt-engine-* tests expected that a preemptible background spinner
>>>  running on the target engine should be marked innocent. While i915 can
>>>  mark such a context for execlist mode, GuC scheduling does not guarantee
>>>  that the background spinner can be marked as innocent. Since the state
>>>  of the background spinner depends on the scheduling backend, do no
>>>  validate the state of the background spinner for the target engine.
>>>
>>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>>---
>>> tests/i915/i915_hangman.c | 84 ++++++++++++++++++++++++---------------
>>> 1 file changed, 53 insertions(+), 31 deletions(-)
>>>
>>>diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>>>index c7d69fdd..d7b173ab 100644
>>>--- a/tests/i915/i915_hangman.c
>>>+++ b/tests/i915/i915_hangman.c
>>>@@ -295,9 +295,15 @@ static void context_unban(int fd, unsigned ctx)
>>> 	gem_context_set_param(fd, &param);
>>> }
>>>
>>>+enum reset_type {
>>>+	GT_RESET = 1,
>>>+	ENGINE_RESET = 2,
>>>+};
>>>+
>>> static void
>>> test_engine_hang(const intel_ctx_t *ctx,
>>>-		 const struct intel_execution_engine2 *e, unsigned int flags)
>>>+		 const struct intel_execution_engine2 *e, unsigned int flags,
>>>+		 enum reset_type reset)
>>> {
>>> 	const struct intel_execution_engine2 *other;
>>> 	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
>>>@@ -309,6 +315,7 @@ test_engine_hang(const intel_ctx_t *ctx,
>>> 	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
>>> 		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
>>>
>>>+	igt_assert(reset == GT_RESET || reset == ENGINE_RESET);
>>> 	/*
>>> 	 * Fill all engines with background load.
>>> 	 * This verifies that independent engines are unaffected and gives
>>>@@ -324,7 +331,10 @@ test_engine_hang(const intel_ctx_t *ctx,
>>> 				      .ahnd = ahndN,
>>> 				      .ctx = local_ctx[num_ctx],
>>> 				      .engine = other->flags,
>>>-				      .flags = IGT_SPIN_FENCE_OUT);
>>>+				      .flags = IGT_SPIN_FENCE_OUT |
>>>+					       IGT_SPIN_POLL_RUN);
>>>+		igt_spin_busywait_until_started(spin);
>>>+
>>> 		num_ctx++;
>>>
>>> 		igt_list_move(&spin->link, &list);
>>>@@ -344,14 +354,43 @@ test_engine_hang(const intel_ctx_t *ctx,
>>> 	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
>>> 	igt_spin_free(device, spin);
>>>
>>>-	/* But no other engines/clients should be affected */
>>>-	igt_list_for_each_entry_safe(spin, next, &list, link) {
>>>+	/*
>>>+	 * engine-engine-hang: Other engines/clients should not be affected for
>>>+	 * engine reset, so innocent contexts complete successfully once the
>>>+	 * spinner is ended.
>>>+	 *
>>>+	 * gt-engine-hang: All engines/clients are guilty and complete with a
>>>+	 * -EIO fence status, however the background task that was submitted to
>>>+	 * the target engine is innocent and is expected to complete
>>>+	 * successfully.
>>>+	 */
>>
>>imho we should keep test for execlist behaviour. It is not clear
>>why background task survives ? You stated "All ... are guilty" ?
>>Isn't this a race between completing and resetting GT ?
>
>With execlist mode, kmd has control over preempting the background 
>task and saving it's state. With GuC KMD has no such control to save 
>the state of select spinners.
>
>All execlist behavior in this test is retained, except for one - the 
>check for the state of the background spinner on the target engine. 
>The state assumed by execlist backend cannot be guaranteed by GuC 
>backend.
>
>>
>>>+	igt_list_for_each_entry_safe_reverse(spin, next, &list, link) {
>>>+		bool innocent = reset == ENGINE_RESET;
>>>+		int expect = innocent ? 1 : -EIO;
>>>+
>>> 		ahndN = spin->opts.ahnd;
>>>-		igt_assert(sync_fence_wait(spin->out_fence, 0) == -ETIME);
>>>-		igt_spin_end(spin);
>>>+		if (innocent) {
>>>+			igt_assert_eq(sync_fence_wait(spin->out_fence, 0), -ETIME);
>>>+			igt_spin_end(spin);
>>>+		}
>>>
>>>-		igt_assert(sync_fence_wait(spin->out_fence, 500) == 0);
>>>-		igt_assert_eq(sync_fence_status(spin->out_fence), 1);
>>>+		if (spin->opts.engine == e->flags) {
>
>I think the above condition should also check for GT_RESET. I need to 
>add that.
>
>>>+		/*
>>>+		 * gt-reset resets all contexts on all engines. The execlist
>>>+		 * implementation of gt-engine-* tests expected that a
>>>+		 * preemptible background spinner running on the target engine
>>>+		 * should be marked innocent. While i915 can mark such a
>>>+		 * context for execlist mode, GuC scheduling does not guarantee
>>>+		 * that the background spinner can be marked as innocent. Since
>>>+		 * the state of the background spinner depends on the scheduling
>>>+		 * backend, do no validate the state of the background spinner
>>>+		 * for the target engine.
>>>+		 */
>
>In relation to my earlier comment, this is the only place where the 
>asserts are omitted. This is because of the caveat mentioned in the 
>comment above.
>
>>>+			igt_spin_end(spin);
>>>+		} else {
>>>+			igt_assert_eq(sync_fence_wait(spin->out_fence, 500), 0);
>>>+			igt_assert_eq(sync_fence_status(spin->out_fence), expect);
>>>+		}
>>> 		igt_spin_free(device, spin);
>>> 		put_ahnd(ahndN);
>>> 	}
>>>@@ -439,6 +478,10 @@ static void do_tests(const char *name, const char *prefix,
>>> {
>>> 	const struct intel_execution_engine2 *e;
>>> 	char buff[256];
>>>+	enum reset_type reset = ENGINE_RESET;
>>>+
>>>+	if (!strncmp(prefix, "gt", 2))
>>>+		reset = GT_RESET;
>>>
>>> 	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
>>> 	igt_describe(buff);
>>>@@ -454,20 +497,9 @@ static void do_tests(const char *name, const char *prefix,
>>> 	igt_describe(buff);
>>> 	snprintf(buff, sizeof(buff), "%s-engine-hang", prefix);
>>> 	igt_subtest_with_dynamic(buff) {
>>>-                int has_gpu_reset = 0;
>>>-		struct drm_i915_getparam gp = {
>>>-			.param = I915_PARAM_HAS_GPU_RESET,
>>>-			.value = &has_gpu_reset,
>>>-		};
>>>-
>>>-		igt_require(gem_scheduler_has_preemption(device));
>>>-		igt_params_set(device, "reset", "%u", -1);
>>>-                ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
>>>-		igt_require(has_gpu_reset > 1);
>>>-
>>> 		for_each_ctx_engine(device, ctx, e) {
>>> 			igt_dynamic_f("%s", e->name)
>>>-				test_engine_hang(ctx, e, 0);
>>>+				test_engine_hang(ctx, e, 0, reset);
>>> 		}
>>> 	}
>>>
>>>@@ -475,19 +507,9 @@ static void do_tests(const char *name, const char *prefix,
>>> 	igt_describe(buff);
>>> 	snprintf(buff, sizeof(buff), "%s-engine-error", prefix);
>>> 	igt_subtest_with_dynamic(buff) {
>>>-		int has_gpu_reset = 0;
>>>-		struct drm_i915_getparam gp = {
>>>-			.param = I915_PARAM_HAS_GPU_RESET,
>>>-			.value = &has_gpu_reset,
>>>-		};
>>>-
>>>-		igt_params_set(device, "reset", "%u", -1);
>>>-		ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
>>>-		igt_require(has_gpu_reset > 1);
>>>-
>>
>>imho we need this code in test_engine_hang for execlist
>>subbmission for gt-engine-hang case.
>
>for gt-* tests, the fixture in igt_main has
>
>hang = igt_allow_hang(device, ctx->id, HANG_ALLOW_CAPTURE);
>
>That should suffice.

ok, I see what you are saying here - the checks for has_gpu_reset and 
gem_scheduler_has_preemption are still needed for the gt-* tests in 
exelist mode, although I think that code can be placed in the igt_main.  
I will try it out and post another revision.

Thanks,
Umesh

>
>Regards,
>Umesh
>
>
>>
>>Regards,
>>Kamil
>>
>>> 		for_each_ctx_engine(device, ctx, e) {
>>> 			igt_dynamic_f("%s", e->name)
>>>-				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
>>>+				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS, reset);
>>> 		}
>>> 	}
>>> }
>>>--
>>>2.25.1
>>>

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests
  2022-07-29 19:26 Nerlige Ramappa, Umesh
@ 2022-09-02 20:18 ` Kamil Konieczny
  0 siblings, 0 replies; 12+ messages in thread
From: Kamil Konieczny @ 2022-09-02 20:18 UTC (permalink / raw)
  To: igt-dev

Hi Umesh,

On 2022-07-29 at 12:26:13 -0700, Nerlige Ramappa, Umesh wrote:
> From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> 
> gt-engine-hang and gt-engine-error tests were still using reset=2
> setting so that ended up just doing an engine reset. Fix the tests so
> that they actually do the gt specific reset and set the expectations
> correctly.
> 
> In some rare failures, some of the background spinners show up as
> innocent and keep spinning after the hang recovery. This can only happen
> if the spinners did not start for some reason. Check that the spinners
> actually started before submitting a hanging batch.
> 
> For engine specific hang, only one context is marked guilty, but for a
> gt hang all contexts are marked guilty. Check for different expected
> behavior for engine vs. gt reset.
> 
> v2:
> - gt-reset resets all contexts on all engines. The execlist implementation
>   of gt-engine-* tests expected that a preemptible background spinner
>   running on the target engine should be marked innocent. While i915 can
>   mark such a context for execlist mode, GuC scheduling does not guarantee
>   that the background spinner can be marked as innocent. Since the state
>   of the background spinner depends on the scheduling backend, do no
>   validate the state of the background spinner for the target engine.
> 
> v3:
> - omit checking background spinner state only for gt-reset case
> 
> v4: (Kamil)
> - check has_gpu_reset and gem_scheduler_has_preemption for the
>   gt-engine-hang and gt-engine-error tests.

May you put version number in subject of e-mail ? Like
[PATCH i-g-t v4] i915/hangman: ...

> 
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/i915/i915_hangman.c | 75 +++++++++++++++++++++++++++++++--------
>  1 file changed, 60 insertions(+), 15 deletions(-)
> 
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index c7d69fdd..bdf47bc0 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -295,9 +295,15 @@ static void context_unban(int fd, unsigned ctx)
>  	gem_context_set_param(fd, &param);
>  }
>  
> +enum reset_type {
> +	GT_RESET = 1,
> +	ENGINE_RESET = 2,
> +};
> +
>  static void
>  test_engine_hang(const intel_ctx_t *ctx,
> -		 const struct intel_execution_engine2 *e, unsigned int flags)
> +		 const struct intel_execution_engine2 *e, unsigned int flags,
> +		 enum reset_type reset)
----------------- ^
This imho is not needed (new boolean-like param), see below.

>  {
>  	const struct intel_execution_engine2 *other;
>  	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
> @@ -309,6 +315,7 @@ test_engine_hang(const intel_ctx_t *ctx,
>  	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
>  		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
>  
> +	igt_assert(reset == GT_RESET || reset == ENGINE_RESET);

imho we should add new function test_gt_hang and assume that
engine-reset there will be off (meaning gt hang only).
That whould require to move initialization for spinners
into new helper function, but can be postponed to later step
(we could start with some code duplication).

We should first come up with clear logic for test. This is
complicated as for execlist submission there is no difference
between gt-hang or engine-hang (i195 works as if engine-hang
was in effect), so the checks should be done before calling
these test functions.

>  	/*
>  	 * Fill all engines with background load.
>  	 * This verifies that independent engines are unaffected and gives
> @@ -324,7 +331,10 @@ test_engine_hang(const intel_ctx_t *ctx,
>  				      .ahnd = ahndN,
>  				      .ctx = local_ctx[num_ctx],
>  				      .engine = other->flags,
> -				      .flags = IGT_SPIN_FENCE_OUT);
> +				      .flags = IGT_SPIN_FENCE_OUT |
> +					       IGT_SPIN_POLL_RUN);
> +		igt_spin_busywait_until_started(spin);
> +
>  		num_ctx++;
>  
>  		igt_list_move(&spin->link, &list);
> @@ -344,14 +354,44 @@ test_engine_hang(const intel_ctx_t *ctx,
>  	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
>  	igt_spin_free(device, spin);
>  
> -	/* But no other engines/clients should be affected */
> -	igt_list_for_each_entry_safe(spin, next, &list, link) {
> +	/*
> +	 * engine-engine-hang: Other engines/clients should not be affected for
> +	 * engine reset, so innocent contexts complete successfully once the
> +	 * spinner is ended.
> +	 *
> +	 * gt-engine-hang: All engines/clients are guilty and complete with a
> +	 * -EIO fence status, however the background task that was submitted to
> +	 * the target engine is innocent and is expected to complete
> +	 * successfully.
> +	 */
> +	igt_list_for_each_entry_safe_reverse(spin, next, &list, link) {
> +		bool innocent = reset == ENGINE_RESET;
> +		int expect = innocent ? 1 : -EIO;
> +
>  		ahndN = spin->opts.ahnd;
> -		igt_assert(sync_fence_wait(spin->out_fence, 0) == -ETIME);
> -		igt_spin_end(spin);
> +		if (innocent) {
> +			igt_assert_eq(sync_fence_wait(spin->out_fence, 0), -ETIME);
> +			igt_spin_end(spin);
> +		}
>  
> -		igt_assert(sync_fence_wait(spin->out_fence, 500) == 0);
> -		igt_assert_eq(sync_fence_status(spin->out_fence), 1);
> +		if (reset == GT_RESET && spin->opts.engine == e->flags) {
> +			/*
> +			 * gt-reset resets everything. The execlist
> +			 * implementation of gt-engine-* tests expect that a
> +			 * preemptible background spinner running on the target
> +			 * engine should be marked innocent. While i915 can mark
> +			 * such a context innocent for execlist mode, GuC
> +			 * scheduling does not guarantee that the background
> +			 * spinner can be marked as innocent. Since the state of
> +			 * the background spinner depends on the scheduling
> +			 * backend, do no validate the state of the background
> +			 * spinner for the target engine when doing a gt-reset.
> +			 */
> +			igt_spin_end(spin);

If the spinner is not checked it should not be created.
This comment should go to other place.

> +		} else {
> +			igt_assert_eq(sync_fence_wait(spin->out_fence, 500), 0);
> +			igt_assert_eq(sync_fence_status(spin->out_fence), expect);
> +		}
>  		igt_spin_free(device, spin);
>  		put_ahnd(ahndN);
>  	}
> @@ -439,6 +479,10 @@ static void do_tests(const char *name, const char *prefix,
>  {
>  	const struct intel_execution_engine2 *e;
>  	char buff[256];
> +	enum reset_type reset = ENGINE_RESET;
> +
> +	if (!strncmp(prefix, "gt", 2))
> +		reset = GT_RESET;
>  
>  	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
>  	igt_describe(buff);
> @@ -461,13 +505,13 @@ static void do_tests(const char *name, const char *prefix,
>  		};
>  
>  		igt_require(gem_scheduler_has_preemption(device));
> -		igt_params_set(device, "reset", "%u", -1);

		igt_params_set(device, "reset", "%u", reset);

>                  ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
> -		igt_require(has_gpu_reset > 1);
> +		igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
> +			    (reset == ENGINE_RESET && has_gpu_reset > 1));

		igt_require(reset == has_gpu_reset);

btw maybe do name change from has_gpu_reset to gpu_reset_level ?

>  
>  		for_each_ctx_engine(device, ctx, e) {
>  			igt_dynamic_f("%s", e->name)
> -				test_engine_hang(ctx, e, 0);
> +				test_engine_hang(ctx, e, 0, reset);
>  		}
>  	}
>  
> @@ -481,13 +525,14 @@ static void do_tests(const char *name, const char *prefix,
>  			.value = &has_gpu_reset,
>  		};
>  
> -		igt_params_set(device, "reset", "%u", -1);
> -		ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
> -		igt_require(has_gpu_reset > 1);
> +		igt_require(gem_scheduler_has_preemption(device));
> +                ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
> +		igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
> +			    (reset == ENGINE_RESET && has_gpu_reset > 1));

This code looks very similar to above, maybe move it to helper ?
Or even better move settings and checks before calling test_gt_hang
or test_engine_hang.

What about setting engine-reset before program exit ?

>  
>  		for_each_ctx_engine(device, ctx, e) {
>  			igt_dynamic_f("%s", e->name)
> -				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
> +				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS, reset);
>  		}
>  	}
>  }
> -- 
> 2.36.1
> 

imho we should add checks for execlist versus GuC submission
and decide what function we call so we should keep test for
old behaviour of i915.

Regards,
Kamil

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests
  2022-08-04 16:57 ` Kamil Konieczny
@ 2022-08-04 17:34   ` Umesh Nerlige Ramappa
  0 siblings, 0 replies; 12+ messages in thread
From: Umesh Nerlige Ramappa @ 2022-08-04 17:34 UTC (permalink / raw)
  To: Kamil Konieczny, igt-dev, Janusz Krzysztofik

On Thu, Aug 04, 2022 at 06:57:32PM +0200, Kamil Konieczny wrote:
>Hi Umesh,
>
>On 2022-07-29 at 12:27:41 -0700, Nerlige Ramappa, Umesh wrote:
>> From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>>
>> gt-engine-hang and gt-engine-error tests were still using reset=2
>> setting so that ended up just doing an engine reset. Fix the tests so
>> that they actually do the gt specific reset and set the expectations
>> correctly.
>>
>> In some rare failures, some of the background spinners show up as
>> innocent and keep spinning after the hang recovery. This can only happen
>> if the spinners did not start for some reason. Check that the spinners
>> actually started before submitting a hanging batch.
>
>imho this is a fix, it is worth to split into separate patch.
>
>>
>> For engine specific hang, only one context is marked guilty, but for a
>> gt hang all contexts are marked guilty. Check for different expected
>> behavior for engine vs. gt reset.
>
>This is true only for GuC submission on new platforms.
>When execlist is used, these tests are the same as engine-engine-*
>as you noted at beginning.
>
>>
>> v2:
>> - gt-reset resets all contexts on all engines. The execlist implementation
>>   of gt-engine-* tests expected that a preemptible background spinner
>>   running on the target engine should be marked innocent. While i915 can
>>   mark such a context for execlist mode, GuC scheduling does not guarantee
>>   that the background spinner can be marked as innocent. Since the state
>>   of the background spinner depends on the scheduling backend, do no
>>   validate the state of the background spinner for the target engine.
>>
>> v3:
>> - omit checking background spinner state only for gt-reset case
>>
>> v4: (Kamil)
>> - check has_gpu_reset and gem_scheduler_has_preemption for the
>>   gt-engine-hang and gt-engine-error tests.
>>
>> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
>> ---
>>  tests/i915/i915_hangman.c | 75 +++++++++++++++++++++++++++++++--------
>>  1 file changed, 60 insertions(+), 15 deletions(-)
>>
>> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
>> index c7d69fdd..bdf47bc0 100644
>> --- a/tests/i915/i915_hangman.c
>> +++ b/tests/i915/i915_hangman.c
>> @@ -295,9 +295,15 @@ static void context_unban(int fd, unsigned ctx)
>>  	gem_context_set_param(fd, &param);
>>  }
>>
>> +enum reset_type {
>> +	GT_RESET = 1,
>> +	ENGINE_RESET = 2,
>> +};
>> +
>>  static void
>>  test_engine_hang(const intel_ctx_t *ctx,
>> -		 const struct intel_execution_engine2 *e, unsigned int flags)
>> +		 const struct intel_execution_engine2 *e, unsigned int flags,
>> +		 enum reset_type reset)
>
>Using bool as param are no good, imho we should split this into
>two functions, see below after your comment on
>egine-engine-hang.
>
>>  {
>>  	const struct intel_execution_engine2 *other;
>>  	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
>> @@ -309,6 +315,7 @@ test_engine_hang(const intel_ctx_t *ctx,
>>  	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
>>  		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
>>
>> +	igt_assert(reset == GT_RESET || reset == ENGINE_RESET);
>>  	/*
>>  	 * Fill all engines with background load.
>>  	 * This verifies that independent engines are unaffected and gives
>> @@ -324,7 +331,10 @@ test_engine_hang(const intel_ctx_t *ctx,
>>  				      .ahnd = ahndN,
>>  				      .ctx = local_ctx[num_ctx],
>>  				      .engine = other->flags,
>> -				      .flags = IGT_SPIN_FENCE_OUT);
>> +				      .flags = IGT_SPIN_FENCE_OUT |
>> +					       IGT_SPIN_POLL_RUN);
>> +		igt_spin_busywait_until_started(spin);
>> +
>
>This is a fix, please split it to separate patch.
>
>>  		num_ctx++;
>>
>>  		igt_list_move(&spin->link, &list);
>> @@ -344,14 +354,44 @@ test_engine_hang(const intel_ctx_t *ctx,
>>  	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
>>  	igt_spin_free(device, spin);
>>
>> -	/* But no other engines/clients should be affected */
>> -	igt_list_for_each_entry_safe(spin, next, &list, link) {
>> +	/*
>> +	 * engine-engine-hang: Other engines/clients should not be affected for
>> +	 * engine reset, so innocent contexts complete successfully once the
>> +	 * spinner is ended.
>> +	 *
>> +	 * gt-engine-hang: All engines/clients are guilty and complete with a
>> +	 * -EIO fence status, however the background task that was submitted to
>> +	 * the target engine is innocent and is expected to complete
>> +	 * successfully.
>> +	 */
>
From this description maybe it it worth to split this function
>into two separate functions : gt_engine_hang and engine_engine_hang.
>Latter one will be old and in former one we could add different
>bahaviour. I will add Janusz to Cc for this topic.
>
>> +	igt_list_for_each_entry_safe_reverse(spin, next, &list, link) {
>
>Why do you change this into _reverse ?

Just retaining whatever was used earlier.

>
>> +		bool innocent = reset == ENGINE_RESET;
>
>When we split functionality then we can remove this check.

yes.

>
>> +		int expect = innocent ? 1 : -EIO;
>> +
>>  		ahndN = spin->opts.ahnd;
>> -		igt_assert(sync_fence_wait(spin->out_fence, 0) == -ETIME);
>> -		igt_spin_end(spin);
>> +		if (innocent) {
>> +			igt_assert_eq(sync_fence_wait(spin->out_fence, 0), -ETIME);
>> +			igt_spin_end(spin);
>> +		}
>>
>> -		igt_assert(sync_fence_wait(spin->out_fence, 500) == 0);
>> -		igt_assert_eq(sync_fence_status(spin->out_fence), 1);
>> +		if (reset == GT_RESET && spin->opts.engine == e->flags) {
>---------------------------------------  ^
>Here you will check execlist or GuC ? This shows we need to split
>functionality to avoid logic errors and further simplify our
>checks.
>
>> +			/*
>> +			 * gt-reset resets everything. The execlist
>> +			 * implementation of gt-engine-* tests expect that a
>> +			 * preemptible background spinner running on the target
>> +			 * engine should be marked innocent. While i915 can mark
>> +			 * such a context innocent for execlist mode, GuC
>> +			 * scheduling does not guarantee that the background
>> +			 * spinner can be marked as innocent. Since the state of
>> +			 * the background spinner depends on the scheduling
>> +			 * backend, do no validate the state of the background
>> +			 * spinner for the target engine when doing a gt-reset.
>> +			 */
>> +			igt_spin_end(spin);
>> +		} else {
>> +			igt_assert_eq(sync_fence_wait(spin->out_fence, 500), 0);
>> +			igt_assert_eq(sync_fence_status(spin->out_fence), expect);
>> +		}
>>  		igt_spin_free(device, spin);
>>  		put_ahnd(ahndN);
>>  	}
>> @@ -439,6 +479,10 @@ static void do_tests(const char *name, const char *prefix,
>>  {
>>  	const struct intel_execution_engine2 *e;
>>  	char buff[256];
>> +	enum reset_type reset = ENGINE_RESET;
>> +
>> +	if (!strncmp(prefix, "gt", 2))
>> +		reset = GT_RESET;
>>
>>  	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
>>  	igt_describe(buff);
>> @@ -461,13 +505,13 @@ static void do_tests(const char *name, const char *prefix,
>>  		};
>>
>>  		igt_require(gem_scheduler_has_preemption(device));
>> -		igt_params_set(device, "reset", "%u", -1);
>>                  ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
>> -		igt_require(has_gpu_reset > 1);
>> +		igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
>> +			    (reset == ENGINE_RESET && has_gpu_reset > 1));
>
>Move above checks into separate function (avoid code duplication),
>so here:
>		check_reset(reset);
>and
>check_reset(enum reset_type reset)
>{
>	...put data declarations here...
>
>	ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
>	igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
>		    (reset == ENGINE_RESET && has_gpu_reset > 1));
>}
>
>>
>>  		for_each_ctx_engine(device, ctx, e) {
>>  			igt_dynamic_f("%s", e->name)
>> -				test_engine_hang(ctx, e, 0);
>> +				test_engine_hang(ctx, e, 0, reset);
>
>It is better to make this into:
>				gt_reset ? gt_engine_hang(ctx, e, 0) : engine_engine_hang(ctx, e, 0);
>
>and before that set:
>
>	bool gt_reset = reset == GT_RESET && gem_using_guc_submission(device) &&
>				 intel_gen(intel_get_drm_devid(i915)) >= 12;
>
>imho we want to check both old execlist and new GuC behaviour.
>
>>  		}
>>  	}
>>
>> @@ -481,13 +525,14 @@ static void do_tests(const char *name, const char *prefix,
>>  			.value = &has_gpu_reset,
>>  		};
>>
>> -		igt_params_set(device, "reset", "%u", -1);
>> -		ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
>> -		igt_require(has_gpu_reset > 1);
>> +		igt_require(gem_scheduler_has_preemption(device));
>
>Why is it needed here ?

The reset mechanisms rely on periodic preemption. If preemption is not 
available, then the resets will not work, so we need to check this. This 
is also pulled from older code. Without this SNB CI fails for these 
tests. 

>
>> +                ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
>-- ^
>Use tabs, not spaces here.
>
>> +		igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
>> +			    (reset == ENGINE_RESET && has_gpu_reset > 1));
>
>Instead of above use check_reset(reset) here.
>
>>
>>  		for_each_ctx_engine(device, ctx, e) {
>>  			igt_dynamic_f("%s", e->name)
>> -				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
>> +				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS, reset);
>
>Same here, call gt_engine_hang or engine_engine_hang instead
>(see above). What happens when there are no preemption ?
>
>>  		}
>>  	}
>>  }

overall, I agree that the test would need to be refactored to separate 
out the gt/engine tests as well as execlist/guc checks. That would make 
it better to maintain. I would do that as a follow up since this test is 
still needed for BAT.

Thanks,
Umesh


>> --
>> 2.36.1
>>
>
>Regards,
>Kamil
>

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests
  2022-07-29 19:27 Nerlige Ramappa, Umesh
@ 2022-08-04 16:57 ` Kamil Konieczny
  2022-08-04 17:34   ` Umesh Nerlige Ramappa
  0 siblings, 1 reply; 12+ messages in thread
From: Kamil Konieczny @ 2022-08-04 16:57 UTC (permalink / raw)
  To: igt-dev

Hi Umesh,

On 2022-07-29 at 12:27:41 -0700, Nerlige Ramappa, Umesh wrote:
> From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> 
> gt-engine-hang and gt-engine-error tests were still using reset=2
> setting so that ended up just doing an engine reset. Fix the tests so
> that they actually do the gt specific reset and set the expectations
> correctly.
> 
> In some rare failures, some of the background spinners show up as
> innocent and keep spinning after the hang recovery. This can only happen
> if the spinners did not start for some reason. Check that the spinners
> actually started before submitting a hanging batch.

imho this is a fix, it is worth to split into separate patch.

> 
> For engine specific hang, only one context is marked guilty, but for a
> gt hang all contexts are marked guilty. Check for different expected
> behavior for engine vs. gt reset.

This is true only for GuC submission on new platforms.
When execlist is used, these tests are the same as engine-engine-*
as you noted at beginning.

> 
> v2:
> - gt-reset resets all contexts on all engines. The execlist implementation
>   of gt-engine-* tests expected that a preemptible background spinner
>   running on the target engine should be marked innocent. While i915 can
>   mark such a context for execlist mode, GuC scheduling does not guarantee
>   that the background spinner can be marked as innocent. Since the state
>   of the background spinner depends on the scheduling backend, do no
>   validate the state of the background spinner for the target engine.
> 
> v3:
> - omit checking background spinner state only for gt-reset case
> 
> v4: (Kamil)
> - check has_gpu_reset and gem_scheduler_has_preemption for the
>   gt-engine-hang and gt-engine-error tests.
> 
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  tests/i915/i915_hangman.c | 75 +++++++++++++++++++++++++++++++--------
>  1 file changed, 60 insertions(+), 15 deletions(-)
> 
> diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
> index c7d69fdd..bdf47bc0 100644
> --- a/tests/i915/i915_hangman.c
> +++ b/tests/i915/i915_hangman.c
> @@ -295,9 +295,15 @@ static void context_unban(int fd, unsigned ctx)
>  	gem_context_set_param(fd, &param);
>  }
>  
> +enum reset_type {
> +	GT_RESET = 1,
> +	ENGINE_RESET = 2,
> +};
> +
>  static void
>  test_engine_hang(const intel_ctx_t *ctx,
> -		 const struct intel_execution_engine2 *e, unsigned int flags)
> +		 const struct intel_execution_engine2 *e, unsigned int flags,
> +		 enum reset_type reset)

Using bool as param are no good, imho we should split this into
two functions, see below after your comment on
egine-engine-hang.

>  {
>  	const struct intel_execution_engine2 *other;
>  	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
> @@ -309,6 +315,7 @@ test_engine_hang(const intel_ctx_t *ctx,
>  	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
>  		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
>  
> +	igt_assert(reset == GT_RESET || reset == ENGINE_RESET);
>  	/*
>  	 * Fill all engines with background load.
>  	 * This verifies that independent engines are unaffected and gives
> @@ -324,7 +331,10 @@ test_engine_hang(const intel_ctx_t *ctx,
>  				      .ahnd = ahndN,
>  				      .ctx = local_ctx[num_ctx],
>  				      .engine = other->flags,
> -				      .flags = IGT_SPIN_FENCE_OUT);
> +				      .flags = IGT_SPIN_FENCE_OUT |
> +					       IGT_SPIN_POLL_RUN);
> +		igt_spin_busywait_until_started(spin);
> +

This is a fix, please split it to separate patch.

>  		num_ctx++;
>  
>  		igt_list_move(&spin->link, &list);
> @@ -344,14 +354,44 @@ test_engine_hang(const intel_ctx_t *ctx,
>  	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
>  	igt_spin_free(device, spin);
>  
> -	/* But no other engines/clients should be affected */
> -	igt_list_for_each_entry_safe(spin, next, &list, link) {
> +	/*
> +	 * engine-engine-hang: Other engines/clients should not be affected for
> +	 * engine reset, so innocent contexts complete successfully once the
> +	 * spinner is ended.
> +	 *
> +	 * gt-engine-hang: All engines/clients are guilty and complete with a
> +	 * -EIO fence status, however the background task that was submitted to
> +	 * the target engine is innocent and is expected to complete
> +	 * successfully.
> +	 */

From this description maybe it it worth to split this function
into two separate functions : gt_engine_hang and engine_engine_hang.
Latter one will be old and in former one we could add different
bahaviour. I will add Janusz to Cc for this topic.

> +	igt_list_for_each_entry_safe_reverse(spin, next, &list, link) {

Why do you change this into _reverse ?

> +		bool innocent = reset == ENGINE_RESET;

When we split functionality then we can remove this check.

> +		int expect = innocent ? 1 : -EIO;
> +
>  		ahndN = spin->opts.ahnd;
> -		igt_assert(sync_fence_wait(spin->out_fence, 0) == -ETIME);
> -		igt_spin_end(spin);
> +		if (innocent) {
> +			igt_assert_eq(sync_fence_wait(spin->out_fence, 0), -ETIME);
> +			igt_spin_end(spin);
> +		}
>  
> -		igt_assert(sync_fence_wait(spin->out_fence, 500) == 0);
> -		igt_assert_eq(sync_fence_status(spin->out_fence), 1);
> +		if (reset == GT_RESET && spin->opts.engine == e->flags) {
---------------------------------------  ^
Here you will check execlist or GuC ? This shows we need to split
functionality to avoid logic errors and further simplify our
checks.

> +			/*
> +			 * gt-reset resets everything. The execlist
> +			 * implementation of gt-engine-* tests expect that a
> +			 * preemptible background spinner running on the target
> +			 * engine should be marked innocent. While i915 can mark
> +			 * such a context innocent for execlist mode, GuC
> +			 * scheduling does not guarantee that the background
> +			 * spinner can be marked as innocent. Since the state of
> +			 * the background spinner depends on the scheduling
> +			 * backend, do no validate the state of the background
> +			 * spinner for the target engine when doing a gt-reset.
> +			 */
> +			igt_spin_end(spin);
> +		} else {
> +			igt_assert_eq(sync_fence_wait(spin->out_fence, 500), 0);
> +			igt_assert_eq(sync_fence_status(spin->out_fence), expect);
> +		}
>  		igt_spin_free(device, spin);
>  		put_ahnd(ahndN);
>  	}
> @@ -439,6 +479,10 @@ static void do_tests(const char *name, const char *prefix,
>  {
>  	const struct intel_execution_engine2 *e;
>  	char buff[256];
> +	enum reset_type reset = ENGINE_RESET;
> +
> +	if (!strncmp(prefix, "gt", 2))
> +		reset = GT_RESET;
>  
>  	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
>  	igt_describe(buff);
> @@ -461,13 +505,13 @@ static void do_tests(const char *name, const char *prefix,
>  		};
>  
>  		igt_require(gem_scheduler_has_preemption(device));
> -		igt_params_set(device, "reset", "%u", -1);
>                  ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
> -		igt_require(has_gpu_reset > 1);
> +		igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
> +			    (reset == ENGINE_RESET && has_gpu_reset > 1));

Move above checks into separate function (avoid code duplication),
so here:
		check_reset(reset);
and
check_reset(enum reset_type reset)
{
	...put data declarations here...

	ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
	igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
		    (reset == ENGINE_RESET && has_gpu_reset > 1));
}

>  
>  		for_each_ctx_engine(device, ctx, e) {
>  			igt_dynamic_f("%s", e->name)
> -				test_engine_hang(ctx, e, 0);
> +				test_engine_hang(ctx, e, 0, reset);

It is better to make this into:
				gt_reset ? gt_engine_hang(ctx, e, 0) : engine_engine_hang(ctx, e, 0);

and before that set:

	bool gt_reset = reset == GT_RESET && gem_using_guc_submission(device) &&
				 intel_gen(intel_get_drm_devid(i915)) >= 12;

imho we want to check both old execlist and new GuC behaviour.

>  		}
>  	}
>  
> @@ -481,13 +525,14 @@ static void do_tests(const char *name, const char *prefix,
>  			.value = &has_gpu_reset,
>  		};
>  
> -		igt_params_set(device, "reset", "%u", -1);
> -		ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
> -		igt_require(has_gpu_reset > 1);
> +		igt_require(gem_scheduler_has_preemption(device));

Why is it needed here ?

> +                ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
-- ^
Use tabs, not spaces here.

> +		igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
> +			    (reset == ENGINE_RESET && has_gpu_reset > 1));

Instead of above use check_reset(reset) here.

>  
>  		for_each_ctx_engine(device, ctx, e) {
>  			igt_dynamic_f("%s", e->name)
> -				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
> +				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS, reset);

Same here, call gt_engine_hang or engine_engine_hang instead 
(see above). What happens when there are no preemption ?

>  		}
>  	}
>  }
> -- 
> 2.36.1
> 

Regards,
Kamil

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests
@ 2022-07-29 19:27 Nerlige Ramappa, Umesh
  2022-08-04 16:57 ` Kamil Konieczny
  0 siblings, 1 reply; 12+ messages in thread
From: Nerlige Ramappa, Umesh @ 2022-07-29 19:27 UTC (permalink / raw)
  To: igt-dev, kamil.konieczny

From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

gt-engine-hang and gt-engine-error tests were still using reset=2
setting so that ended up just doing an engine reset. Fix the tests so
that they actually do the gt specific reset and set the expectations
correctly.

In some rare failures, some of the background spinners show up as
innocent and keep spinning after the hang recovery. This can only happen
if the spinners did not start for some reason. Check that the spinners
actually started before submitting a hanging batch.

For engine specific hang, only one context is marked guilty, but for a
gt hang all contexts are marked guilty. Check for different expected
behavior for engine vs. gt reset.

v2:
- gt-reset resets all contexts on all engines. The execlist implementation
  of gt-engine-* tests expected that a preemptible background spinner
  running on the target engine should be marked innocent. While i915 can
  mark such a context for execlist mode, GuC scheduling does not guarantee
  that the background spinner can be marked as innocent. Since the state
  of the background spinner depends on the scheduling backend, do no
  validate the state of the background spinner for the target engine.

v3:
- omit checking background spinner state only for gt-reset case

v4: (Kamil)
- check has_gpu_reset and gem_scheduler_has_preemption for the
  gt-engine-hang and gt-engine-error tests.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/i915/i915_hangman.c | 75 +++++++++++++++++++++++++++++++--------
 1 file changed, 60 insertions(+), 15 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index c7d69fdd..bdf47bc0 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -295,9 +295,15 @@ static void context_unban(int fd, unsigned ctx)
 	gem_context_set_param(fd, &param);
 }
 
+enum reset_type {
+	GT_RESET = 1,
+	ENGINE_RESET = 2,
+};
+
 static void
 test_engine_hang(const intel_ctx_t *ctx,
-		 const struct intel_execution_engine2 *e, unsigned int flags)
+		 const struct intel_execution_engine2 *e, unsigned int flags,
+		 enum reset_type reset)
 {
 	const struct intel_execution_engine2 *other;
 	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
@@ -309,6 +315,7 @@ test_engine_hang(const intel_ctx_t *ctx,
 	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
 		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
 
+	igt_assert(reset == GT_RESET || reset == ENGINE_RESET);
 	/*
 	 * Fill all engines with background load.
 	 * This verifies that independent engines are unaffected and gives
@@ -324,7 +331,10 @@ test_engine_hang(const intel_ctx_t *ctx,
 				      .ahnd = ahndN,
 				      .ctx = local_ctx[num_ctx],
 				      .engine = other->flags,
-				      .flags = IGT_SPIN_FENCE_OUT);
+				      .flags = IGT_SPIN_FENCE_OUT |
+					       IGT_SPIN_POLL_RUN);
+		igt_spin_busywait_until_started(spin);
+
 		num_ctx++;
 
 		igt_list_move(&spin->link, &list);
@@ -344,14 +354,44 @@ test_engine_hang(const intel_ctx_t *ctx,
 	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
 	igt_spin_free(device, spin);
 
-	/* But no other engines/clients should be affected */
-	igt_list_for_each_entry_safe(spin, next, &list, link) {
+	/*
+	 * engine-engine-hang: Other engines/clients should not be affected for
+	 * engine reset, so innocent contexts complete successfully once the
+	 * spinner is ended.
+	 *
+	 * gt-engine-hang: All engines/clients are guilty and complete with a
+	 * -EIO fence status, however the background task that was submitted to
+	 * the target engine is innocent and is expected to complete
+	 * successfully.
+	 */
+	igt_list_for_each_entry_safe_reverse(spin, next, &list, link) {
+		bool innocent = reset == ENGINE_RESET;
+		int expect = innocent ? 1 : -EIO;
+
 		ahndN = spin->opts.ahnd;
-		igt_assert(sync_fence_wait(spin->out_fence, 0) == -ETIME);
-		igt_spin_end(spin);
+		if (innocent) {
+			igt_assert_eq(sync_fence_wait(spin->out_fence, 0), -ETIME);
+			igt_spin_end(spin);
+		}
 
-		igt_assert(sync_fence_wait(spin->out_fence, 500) == 0);
-		igt_assert_eq(sync_fence_status(spin->out_fence), 1);
+		if (reset == GT_RESET && spin->opts.engine == e->flags) {
+			/*
+			 * gt-reset resets everything. The execlist
+			 * implementation of gt-engine-* tests expect that a
+			 * preemptible background spinner running on the target
+			 * engine should be marked innocent. While i915 can mark
+			 * such a context innocent for execlist mode, GuC
+			 * scheduling does not guarantee that the background
+			 * spinner can be marked as innocent. Since the state of
+			 * the background spinner depends on the scheduling
+			 * backend, do no validate the state of the background
+			 * spinner for the target engine when doing a gt-reset.
+			 */
+			igt_spin_end(spin);
+		} else {
+			igt_assert_eq(sync_fence_wait(spin->out_fence, 500), 0);
+			igt_assert_eq(sync_fence_status(spin->out_fence), expect);
+		}
 		igt_spin_free(device, spin);
 		put_ahnd(ahndN);
 	}
@@ -439,6 +479,10 @@ static void do_tests(const char *name, const char *prefix,
 {
 	const struct intel_execution_engine2 *e;
 	char buff[256];
+	enum reset_type reset = ENGINE_RESET;
+
+	if (!strncmp(prefix, "gt", 2))
+		reset = GT_RESET;
 
 	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
 	igt_describe(buff);
@@ -461,13 +505,13 @@ static void do_tests(const char *name, const char *prefix,
 		};
 
 		igt_require(gem_scheduler_has_preemption(device));
-		igt_params_set(device, "reset", "%u", -1);
                 ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
-		igt_require(has_gpu_reset > 1);
+		igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
+			    (reset == ENGINE_RESET && has_gpu_reset > 1));
 
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_engine_hang(ctx, e, 0);
+				test_engine_hang(ctx, e, 0, reset);
 		}
 	}
 
@@ -481,13 +525,14 @@ static void do_tests(const char *name, const char *prefix,
 			.value = &has_gpu_reset,
 		};
 
-		igt_params_set(device, "reset", "%u", -1);
-		ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
-		igt_require(has_gpu_reset > 1);
+		igt_require(gem_scheduler_has_preemption(device));
+                ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
+		igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
+			    (reset == ENGINE_RESET && has_gpu_reset > 1));
 
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
+				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS, reset);
 		}
 	}
 }
-- 
2.36.1

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests
@ 2022-07-29 19:26 Nerlige Ramappa, Umesh
  2022-09-02 20:18 ` Kamil Konieczny
  0 siblings, 1 reply; 12+ messages in thread
From: Nerlige Ramappa, Umesh @ 2022-07-29 19:26 UTC (permalink / raw)
  To: igt-dev, kamil.konieczny

From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

gt-engine-hang and gt-engine-error tests were still using reset=2
setting so that ended up just doing an engine reset. Fix the tests so
that they actually do the gt specific reset and set the expectations
correctly.

In some rare failures, some of the background spinners show up as
innocent and keep spinning after the hang recovery. This can only happen
if the spinners did not start for some reason. Check that the spinners
actually started before submitting a hanging batch.

For engine specific hang, only one context is marked guilty, but for a
gt hang all contexts are marked guilty. Check for different expected
behavior for engine vs. gt reset.

v2:
- gt-reset resets all contexts on all engines. The execlist implementation
  of gt-engine-* tests expected that a preemptible background spinner
  running on the target engine should be marked innocent. While i915 can
  mark such a context for execlist mode, GuC scheduling does not guarantee
  that the background spinner can be marked as innocent. Since the state
  of the background spinner depends on the scheduling backend, do no
  validate the state of the background spinner for the target engine.

v3:
- omit checking background spinner state only for gt-reset case

v4: (Kamil)
- check has_gpu_reset and gem_scheduler_has_preemption for the
  gt-engine-hang and gt-engine-error tests.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/i915/i915_hangman.c | 75 +++++++++++++++++++++++++++++++--------
 1 file changed, 60 insertions(+), 15 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index c7d69fdd..bdf47bc0 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -295,9 +295,15 @@ static void context_unban(int fd, unsigned ctx)
 	gem_context_set_param(fd, &param);
 }
 
+enum reset_type {
+	GT_RESET = 1,
+	ENGINE_RESET = 2,
+};
+
 static void
 test_engine_hang(const intel_ctx_t *ctx,
-		 const struct intel_execution_engine2 *e, unsigned int flags)
+		 const struct intel_execution_engine2 *e, unsigned int flags,
+		 enum reset_type reset)
 {
 	const struct intel_execution_engine2 *other;
 	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
@@ -309,6 +315,7 @@ test_engine_hang(const intel_ctx_t *ctx,
 	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
 		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
 
+	igt_assert(reset == GT_RESET || reset == ENGINE_RESET);
 	/*
 	 * Fill all engines with background load.
 	 * This verifies that independent engines are unaffected and gives
@@ -324,7 +331,10 @@ test_engine_hang(const intel_ctx_t *ctx,
 				      .ahnd = ahndN,
 				      .ctx = local_ctx[num_ctx],
 				      .engine = other->flags,
-				      .flags = IGT_SPIN_FENCE_OUT);
+				      .flags = IGT_SPIN_FENCE_OUT |
+					       IGT_SPIN_POLL_RUN);
+		igt_spin_busywait_until_started(spin);
+
 		num_ctx++;
 
 		igt_list_move(&spin->link, &list);
@@ -344,14 +354,44 @@ test_engine_hang(const intel_ctx_t *ctx,
 	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
 	igt_spin_free(device, spin);
 
-	/* But no other engines/clients should be affected */
-	igt_list_for_each_entry_safe(spin, next, &list, link) {
+	/*
+	 * engine-engine-hang: Other engines/clients should not be affected for
+	 * engine reset, so innocent contexts complete successfully once the
+	 * spinner is ended.
+	 *
+	 * gt-engine-hang: All engines/clients are guilty and complete with a
+	 * -EIO fence status, however the background task that was submitted to
+	 * the target engine is innocent and is expected to complete
+	 * successfully.
+	 */
+	igt_list_for_each_entry_safe_reverse(spin, next, &list, link) {
+		bool innocent = reset == ENGINE_RESET;
+		int expect = innocent ? 1 : -EIO;
+
 		ahndN = spin->opts.ahnd;
-		igt_assert(sync_fence_wait(spin->out_fence, 0) == -ETIME);
-		igt_spin_end(spin);
+		if (innocent) {
+			igt_assert_eq(sync_fence_wait(spin->out_fence, 0), -ETIME);
+			igt_spin_end(spin);
+		}
 
-		igt_assert(sync_fence_wait(spin->out_fence, 500) == 0);
-		igt_assert_eq(sync_fence_status(spin->out_fence), 1);
+		if (reset == GT_RESET && spin->opts.engine == e->flags) {
+			/*
+			 * gt-reset resets everything. The execlist
+			 * implementation of gt-engine-* tests expect that a
+			 * preemptible background spinner running on the target
+			 * engine should be marked innocent. While i915 can mark
+			 * such a context innocent for execlist mode, GuC
+			 * scheduling does not guarantee that the background
+			 * spinner can be marked as innocent. Since the state of
+			 * the background spinner depends on the scheduling
+			 * backend, do no validate the state of the background
+			 * spinner for the target engine when doing a gt-reset.
+			 */
+			igt_spin_end(spin);
+		} else {
+			igt_assert_eq(sync_fence_wait(spin->out_fence, 500), 0);
+			igt_assert_eq(sync_fence_status(spin->out_fence), expect);
+		}
 		igt_spin_free(device, spin);
 		put_ahnd(ahndN);
 	}
@@ -439,6 +479,10 @@ static void do_tests(const char *name, const char *prefix,
 {
 	const struct intel_execution_engine2 *e;
 	char buff[256];
+	enum reset_type reset = ENGINE_RESET;
+
+	if (!strncmp(prefix, "gt", 2))
+		reset = GT_RESET;
 
 	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
 	igt_describe(buff);
@@ -461,13 +505,13 @@ static void do_tests(const char *name, const char *prefix,
 		};
 
 		igt_require(gem_scheduler_has_preemption(device));
-		igt_params_set(device, "reset", "%u", -1);
                 ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
-		igt_require(has_gpu_reset > 1);
+		igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
+			    (reset == ENGINE_RESET && has_gpu_reset > 1));
 
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_engine_hang(ctx, e, 0);
+				test_engine_hang(ctx, e, 0, reset);
 		}
 	}
 
@@ -481,13 +525,14 @@ static void do_tests(const char *name, const char *prefix,
 			.value = &has_gpu_reset,
 		};
 
-		igt_params_set(device, "reset", "%u", -1);
-		ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
-		igt_require(has_gpu_reset > 1);
+		igt_require(gem_scheduler_has_preemption(device));
+                ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
+		igt_require((reset == GT_RESET && has_gpu_reset == 1) ||
+			    (reset == ENGINE_RESET && has_gpu_reset > 1));
 
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
+				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS, reset);
 		}
 	}
 }
-- 
2.36.1

^ permalink raw reply related	[flat|nested] 12+ messages in thread

* [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests
@ 2022-07-28 18:11 Nerlige Ramappa, Umesh
  0 siblings, 0 replies; 12+ messages in thread
From: Nerlige Ramappa, Umesh @ 2022-07-28 18:11 UTC (permalink / raw)
  To: igt-dev, John.C.Harrison, kamil.konieczny

From: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

gt-engine-hang and gt-engine-error tests were still using reset=2
setting so that ended up just doing an engine reset. Fix the tests so
that they actually do the gt specific reset and set the expectations
correctly.

In some rare failures, some of the background spinners show up as
innocent and keep spinning after the hang recovery. This can only happen
if the spinners did not start for some reason. Check that the spinners
actually started before submitting a hanging batch.

For engine specific hang, only one context is marked guilty, but for a
gt hang all contexts are marked guilty. Check for different expected
behavior for engine vs. gt reset.

v2:
- gt-reset resets all contexts on all engines. The execlist implementation
  of gt-engine-* tests expected that a preemptible background spinner
  running on the target engine should be marked innocent. While i915 can
  mark such a context for execlist mode, GuC scheduling does not guarantee
  that the background spinner can be marked as innocent. Since the state
  of the background spinner depends on the scheduling backend, do no
  validate the state of the background spinner for the target engine.

v3:
- omit checking background spinner state only for gt-reset case

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 tests/i915/i915_hangman.c | 85 +++++++++++++++++++++++++--------------
 1 file changed, 54 insertions(+), 31 deletions(-)

diff --git a/tests/i915/i915_hangman.c b/tests/i915/i915_hangman.c
index c7d69fdd..5b804997 100644
--- a/tests/i915/i915_hangman.c
+++ b/tests/i915/i915_hangman.c
@@ -295,9 +295,15 @@ static void context_unban(int fd, unsigned ctx)
 	gem_context_set_param(fd, &param);
 }
 
+enum reset_type {
+	GT_RESET = 1,
+	ENGINE_RESET = 2,
+};
+
 static void
 test_engine_hang(const intel_ctx_t *ctx,
-		 const struct intel_execution_engine2 *e, unsigned int flags)
+		 const struct intel_execution_engine2 *e, unsigned int flags,
+		 enum reset_type reset)
 {
 	const struct intel_execution_engine2 *other;
 	const intel_ctx_t *local_ctx[GEM_MAX_ENGINES];
@@ -309,6 +315,7 @@ test_engine_hang(const intel_ctx_t *ctx,
 	igt_skip_on(flags & IGT_SPIN_INVALID_CS &&
 		    gem_engine_has_cmdparser(device, &ctx->cfg, e->flags));
 
+	igt_assert(reset == GT_RESET || reset == ENGINE_RESET);
 	/*
 	 * Fill all engines with background load.
 	 * This verifies that independent engines are unaffected and gives
@@ -324,7 +331,10 @@ test_engine_hang(const intel_ctx_t *ctx,
 				      .ahnd = ahndN,
 				      .ctx = local_ctx[num_ctx],
 				      .engine = other->flags,
-				      .flags = IGT_SPIN_FENCE_OUT);
+				      .flags = IGT_SPIN_FENCE_OUT |
+					       IGT_SPIN_POLL_RUN);
+		igt_spin_busywait_until_started(spin);
+
 		num_ctx++;
 
 		igt_list_move(&spin->link, &list);
@@ -344,14 +354,44 @@ test_engine_hang(const intel_ctx_t *ctx,
 	igt_assert_eq(sync_fence_status(spin->out_fence), -EIO);
 	igt_spin_free(device, spin);
 
-	/* But no other engines/clients should be affected */
-	igt_list_for_each_entry_safe(spin, next, &list, link) {
+	/*
+	 * engine-engine-hang: Other engines/clients should not be affected for
+	 * engine reset, so innocent contexts complete successfully once the
+	 * spinner is ended.
+	 *
+	 * gt-engine-hang: All engines/clients are guilty and complete with a
+	 * -EIO fence status, however the background task that was submitted to
+	 * the target engine is innocent and is expected to complete
+	 * successfully.
+	 */
+	igt_list_for_each_entry_safe_reverse(spin, next, &list, link) {
+		bool innocent = reset == ENGINE_RESET;
+		int expect = innocent ? 1 : -EIO;
+
 		ahndN = spin->opts.ahnd;
-		igt_assert(sync_fence_wait(spin->out_fence, 0) == -ETIME);
-		igt_spin_end(spin);
+		if (innocent) {
+			igt_assert_eq(sync_fence_wait(spin->out_fence, 0), -ETIME);
+			igt_spin_end(spin);
+		}
 
-		igt_assert(sync_fence_wait(spin->out_fence, 500) == 0);
-		igt_assert_eq(sync_fence_status(spin->out_fence), 1);
+		if (reset == GT_RESET && spin->opts.engine == e->flags) {
+			/*
+			 * gt-reset resets everything. The execlist
+			 * implementation of gt-engine-* tests expect that a
+			 * preemptible background spinner running on the target
+			 * engine should be marked innocent. While i915 can mark
+			 * such a context innocent for execlist mode, GuC
+			 * scheduling does not guarantee that the background
+			 * spinner can be marked as innocent. Since the state of
+			 * the background spinner depends on the scheduling
+			 * backend, do no validate the state of the background
+			 * spinner for the target engine when doing a gt-reset.
+			 */
+			igt_spin_end(spin);
+		} else {
+			igt_assert_eq(sync_fence_wait(spin->out_fence, 500), 0);
+			igt_assert_eq(sync_fence_status(spin->out_fence), expect);
+		}
 		igt_spin_free(device, spin);
 		put_ahnd(ahndN);
 	}
@@ -439,6 +479,10 @@ static void do_tests(const char *name, const char *prefix,
 {
 	const struct intel_execution_engine2 *e;
 	char buff[256];
+	enum reset_type reset = ENGINE_RESET;
+
+	if (!strncmp(prefix, "gt", 2))
+		reset = GT_RESET;
 
 	snprintf(buff, sizeof(buff), "Per engine error capture (%s reset)", name);
 	igt_describe(buff);
@@ -454,20 +498,9 @@ static void do_tests(const char *name, const char *prefix,
 	igt_describe(buff);
 	snprintf(buff, sizeof(buff), "%s-engine-hang", prefix);
 	igt_subtest_with_dynamic(buff) {
-                int has_gpu_reset = 0;
-		struct drm_i915_getparam gp = {
-			.param = I915_PARAM_HAS_GPU_RESET,
-			.value = &has_gpu_reset,
-		};
-
-		igt_require(gem_scheduler_has_preemption(device));
-		igt_params_set(device, "reset", "%u", -1);
-                ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
-		igt_require(has_gpu_reset > 1);
-
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_engine_hang(ctx, e, 0);
+				test_engine_hang(ctx, e, 0, reset);
 		}
 	}
 
@@ -475,19 +508,9 @@ static void do_tests(const char *name, const char *prefix,
 	igt_describe(buff);
 	snprintf(buff, sizeof(buff), "%s-engine-error", prefix);
 	igt_subtest_with_dynamic(buff) {
-		int has_gpu_reset = 0;
-		struct drm_i915_getparam gp = {
-			.param = I915_PARAM_HAS_GPU_RESET,
-			.value = &has_gpu_reset,
-		};
-
-		igt_params_set(device, "reset", "%u", -1);
-		ioctl(device, DRM_IOCTL_I915_GETPARAM, &gp);
-		igt_require(has_gpu_reset > 1);
-
 		for_each_ctx_engine(device, ctx, e) {
 			igt_dynamic_f("%s", e->name)
-				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS);
+				test_engine_hang(ctx, e, IGT_SPIN_INVALID_CS, reset);
 		}
 	}
 }
-- 
2.25.1

^ permalink raw reply related	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2022-09-02 20:18 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-28  1:15 [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests Umesh Nerlige Ramappa
2022-07-28  1:53 ` [igt-dev] ✓ Fi.CI.BAT: success for i915/hangman: Fix gt hang/error tests (rev2) Patchwork
2022-07-28  9:21 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
2022-07-28 14:59 ` [igt-dev] [PATCH i-g-t] i915/hangman: Fix gt hang/error tests Kamil Konieczny
2022-07-28 15:14   ` Umesh Nerlige Ramappa
2022-07-29 18:35     ` Umesh Nerlige Ramappa
2022-07-28 18:11 Nerlige Ramappa, Umesh
2022-07-29 19:26 Nerlige Ramappa, Umesh
2022-09-02 20:18 ` Kamil Konieczny
2022-07-29 19:27 Nerlige Ramappa, Umesh
2022-08-04 16:57 ` Kamil Konieczny
2022-08-04 17:34   ` Umesh Nerlige Ramappa

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