* [PATCH v8 0/2] Add the iMX8MP PCIe support
@ 2022-09-20 7:38 ` Richard Zhu
0 siblings, 0 replies; 15+ messages in thread
From: Richard Zhu @ 2022-09-20 7:38 UTC (permalink / raw)
To: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
vkoul, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx
Based on the 6.0-rc1 of the pci/next branch.
This series adds the i.MX8MP PCIe support and tested on i.MX8MP
EVK board when one PCIe NVME device is used.
- i.MX8MP PCIe has reversed initial PERST bit value refer to i.MX8MQ/i.MX8MM.
Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
- Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
And share as much as possible codes with i.MX8MM PCIe PHY.
- Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
driver.
Main changes v7-->v8:
- Add the Reviewed-by tag, no other changes.
Only two patches in v8, Since the other patches had been merged by
Philipp/Shawn/Lorenzo.
Main changes v6-->v7:
- Add "Reviewed-by: Lucas Stach <l.stach@pengutronix.de>" into first three
patches.
- Use "const *char" to replace the static allocation.
Main changes v5-->v6:
- To avoid code duplication when find the gpr syscon regmap, add the
gpr compatible into the drvdata.
- Add one missing space before one curly brace in 3/7 of v5 series.
- 4/7 of v5 had been applied by Phillipp, thanks. For ease of tests, still
keep it in v6.
Main changes v4-->v5:
- Use Lucas' approach, let blk-ctrl driver do the hsio-mix resets.
- Fetch the iomuxc-gpr regmap by the different phandles.
Main changes v3-->v4:
- Regarding Phillipp's suggestions, add fix tag into the first commit.
- Add Reviewed and Tested tags.
Main changes v2-->v3:
- Fix the schema checking error in the PHY dt-binding patch.
- Inspired by Lucas, the PLL configurations might not required when
external OSC is used as PCIe referrence clock. It's true. Remove all
the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK board
with one NVME device is used.
- Drop the #4 patch of v2, since it had been applied by Rob.
Main changes v1-->v2:
- It's my fault forget including Vinod, re-send v2 after include Vinod
and linux-phy@lists.infradead.org.
- List the basements of this patch-set. The branch, codes changes and so on.
- Clean up some useless register and bit definitions in #3 patch.
[PATCH v8 1/2] dt-binding: phy: Add iMX8MP PCIe PHY binding
[PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v8 0/2] Add the iMX8MP PCIe support
@ 2022-09-20 7:38 ` Richard Zhu
0 siblings, 0 replies; 15+ messages in thread
From: Richard Zhu @ 2022-09-20 7:38 UTC (permalink / raw)
To: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
vkoul, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx
Based on the 6.0-rc1 of the pci/next branch.
This series adds the i.MX8MP PCIe support and tested on i.MX8MP
EVK board when one PCIe NVME device is used.
- i.MX8MP PCIe has reversed initial PERST bit value refer to i.MX8MQ/i.MX8MM.
Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
- Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
And share as much as possible codes with i.MX8MM PCIe PHY.
- Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
driver.
Main changes v7-->v8:
- Add the Reviewed-by tag, no other changes.
Only two patches in v8, Since the other patches had been merged by
Philipp/Shawn/Lorenzo.
Main changes v6-->v7:
- Add "Reviewed-by: Lucas Stach <l.stach@pengutronix.de>" into first three
patches.
- Use "const *char" to replace the static allocation.
Main changes v5-->v6:
- To avoid code duplication when find the gpr syscon regmap, add the
gpr compatible into the drvdata.
- Add one missing space before one curly brace in 3/7 of v5 series.
- 4/7 of v5 had been applied by Phillipp, thanks. For ease of tests, still
keep it in v6.
Main changes v4-->v5:
- Use Lucas' approach, let blk-ctrl driver do the hsio-mix resets.
- Fetch the iomuxc-gpr regmap by the different phandles.
Main changes v3-->v4:
- Regarding Phillipp's suggestions, add fix tag into the first commit.
- Add Reviewed and Tested tags.
Main changes v2-->v3:
- Fix the schema checking error in the PHY dt-binding patch.
- Inspired by Lucas, the PLL configurations might not required when
external OSC is used as PCIe referrence clock. It's true. Remove all
the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK board
with one NVME device is used.
- Drop the #4 patch of v2, since it had been applied by Rob.
Main changes v1-->v2:
- It's my fault forget including Vinod, re-send v2 after include Vinod
and linux-phy@lists.infradead.org.
- List the basements of this patch-set. The branch, codes changes and so on.
- Clean up some useless register and bit definitions in #3 patch.
[PATCH v8 1/2] dt-binding: phy: Add iMX8MP PCIe PHY binding
[PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v8 0/2] Add the iMX8MP PCIe support
@ 2022-09-20 7:38 ` Richard Zhu
0 siblings, 0 replies; 15+ messages in thread
From: Richard Zhu @ 2022-09-20 7:38 UTC (permalink / raw)
To: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
vkoul, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx
Based on the 6.0-rc1 of the pci/next branch.
This series adds the i.MX8MP PCIe support and tested on i.MX8MP
EVK board when one PCIe NVME device is used.
- i.MX8MP PCIe has reversed initial PERST bit value refer to i.MX8MQ/i.MX8MM.
Add the PHY PERST explicitly for i.MX8MP PCIe PHY.
- Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver.
And share as much as possible codes with i.MX8MM PCIe PHY.
- Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe
driver.
Main changes v7-->v8:
- Add the Reviewed-by tag, no other changes.
Only two patches in v8, Since the other patches had been merged by
Philipp/Shawn/Lorenzo.
Main changes v6-->v7:
- Add "Reviewed-by: Lucas Stach <l.stach@pengutronix.de>" into first three
patches.
- Use "const *char" to replace the static allocation.
Main changes v5-->v6:
- To avoid code duplication when find the gpr syscon regmap, add the
gpr compatible into the drvdata.
- Add one missing space before one curly brace in 3/7 of v5 series.
- 4/7 of v5 had been applied by Phillipp, thanks. For ease of tests, still
keep it in v6.
Main changes v4-->v5:
- Use Lucas' approach, let blk-ctrl driver do the hsio-mix resets.
- Fetch the iomuxc-gpr regmap by the different phandles.
Main changes v3-->v4:
- Regarding Phillipp's suggestions, add fix tag into the first commit.
- Add Reviewed and Tested tags.
Main changes v2-->v3:
- Fix the schema checking error in the PHY dt-binding patch.
- Inspired by Lucas, the PLL configurations might not required when
external OSC is used as PCIe referrence clock. It's true. Remove all
the HSIO PLL bit manipulations, and PCIe works fine on i.MX8MP EVK board
with one NVME device is used.
- Drop the #4 patch of v2, since it had been applied by Rob.
Main changes v1-->v2:
- It's my fault forget including Vinod, re-send v2 after include Vinod
and linux-phy@lists.infradead.org.
- List the basements of this patch-set. The branch, codes changes and so on.
- Clean up some useless register and bit definitions in #3 patch.
[PATCH v8 1/2] dt-binding: phy: Add iMX8MP PCIe PHY binding
[PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v8 1/2] dt-binding: phy: Add iMX8MP PCIe PHY binding
2022-09-20 7:38 ` Richard Zhu
(?)
@ 2022-09-20 7:38 ` Richard Zhu
-1 siblings, 0 replies; 15+ messages in thread
From: Richard Zhu @ 2022-09-20 7:38 UTC (permalink / raw)
To: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
vkoul, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
Add i.MX8MP PCIe PHY binding.
On iMX8MM, the initialized default value of PERST bit(BIT3) of
SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.
And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add one more PERST explicitly for i.MX8MP PCIe PHY.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index b6421eedece3..692783c7fd69 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- fsl,imx8mm-pcie-phy
+ - fsl,imx8mp-pcie-phy
reg:
maxItems: 1
@@ -28,11 +29,16 @@ properties:
- const: ref
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reset-names:
- items:
- - const: pciephy
+ oneOf:
+ - items: # for iMX8MM
+ - const: pciephy
+ - items: # for IMX8MP
+ - const: pciephy
+ - const: perst
fsl,refclk-pad-mode:
description: |
@@ -60,6 +66,10 @@ properties:
description: A boolean property indicating the CLKREQ# signal is
not supported in the board design (optional)
+ power-domains:
+ description: PCIe PHY power domain (optional).
+ maxItems: 1
+
required:
- "#phy-cells"
- compatible
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v8 1/2] dt-binding: phy: Add iMX8MP PCIe PHY binding
@ 2022-09-20 7:38 ` Richard Zhu
0 siblings, 0 replies; 15+ messages in thread
From: Richard Zhu @ 2022-09-20 7:38 UTC (permalink / raw)
To: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
vkoul, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
Add i.MX8MP PCIe PHY binding.
On iMX8MM, the initialized default value of PERST bit(BIT3) of
SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.
And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add one more PERST explicitly for i.MX8MP PCIe PHY.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index b6421eedece3..692783c7fd69 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- fsl,imx8mm-pcie-phy
+ - fsl,imx8mp-pcie-phy
reg:
maxItems: 1
@@ -28,11 +29,16 @@ properties:
- const: ref
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reset-names:
- items:
- - const: pciephy
+ oneOf:
+ - items: # for iMX8MM
+ - const: pciephy
+ - items: # for IMX8MP
+ - const: pciephy
+ - const: perst
fsl,refclk-pad-mode:
description: |
@@ -60,6 +66,10 @@ properties:
description: A boolean property indicating the CLKREQ# signal is
not supported in the board design (optional)
+ power-domains:
+ description: PCIe PHY power domain (optional).
+ maxItems: 1
+
required:
- "#phy-cells"
- compatible
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v8 1/2] dt-binding: phy: Add iMX8MP PCIe PHY binding
@ 2022-09-20 7:38 ` Richard Zhu
0 siblings, 0 replies; 15+ messages in thread
From: Richard Zhu @ 2022-09-20 7:38 UTC (permalink / raw)
To: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
vkoul, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
Add i.MX8MP PCIe PHY binding.
On iMX8MM, the initialized default value of PERST bit(BIT3) of
SRC_PCIEPHY_RCR is 1b'1.
But i.MX8MP has one inversed default value 1b'0 of PERST bit.
And the PERST bit should be kept 1b'1 after power and clocks are stable.
So add one more PERST explicitly for i.MX8MP PCIe PHY.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
index b6421eedece3..692783c7fd69 100644
--- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- fsl,imx8mm-pcie-phy
+ - fsl,imx8mp-pcie-phy
reg:
maxItems: 1
@@ -28,11 +29,16 @@ properties:
- const: ref
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reset-names:
- items:
- - const: pciephy
+ oneOf:
+ - items: # for iMX8MM
+ - const: pciephy
+ - items: # for IMX8MP
+ - const: pciephy
+ - const: perst
fsl,refclk-pad-mode:
description: |
@@ -60,6 +66,10 @@ properties:
description: A boolean property indicating the CLKREQ# signal is
not supported in the board design (optional)
+ power-domains:
+ description: PCIe PHY power domain (optional).
+ maxItems: 1
+
required:
- "#phy-cells"
- compatible
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
2022-09-20 7:38 ` Richard Zhu
(?)
@ 2022-09-20 7:38 ` Richard Zhu
-1 siblings, 0 replies; 15+ messages in thread
From: Richard Zhu @ 2022-09-20 7:38 UTC (permalink / raw)
To: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
vkoul, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
Add i.MX8MP PCIe PHY support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 144 ++++++++++++++-------
1 file changed, 97 insertions(+), 47 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index ad7d2edfc414..bef0e9d64244 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -11,6 +11,9 @@
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_device.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -31,12 +34,10 @@
#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
#define ANA_AUX_TX_LVL GENMASK(3, 0)
-#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
-#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
+#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
+#define ANA_PLL_DONE 0x3
#define PCIE_PHY_TRSV_REG5 0x414
-#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
#define PCIE_PHY_TRSV_REG6 0x418
-#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
@@ -47,16 +48,28 @@
#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
+enum imx8_pcie_phy_type {
+ IMX8MM,
+ IMX8MP,
+};
+
+struct imx8_pcie_phy_drvdata {
+ enum imx8_pcie_phy_type variant;
+ const char *gpr;
+};
+
struct imx8_pcie_phy {
void __iomem *base;
struct clk *clk;
struct phy *phy;
struct regmap *iomuxc_gpr;
struct reset_control *reset;
+ struct reset_control *perst;
u32 refclk_pad_mode;
u32 tx_deemph_gen1;
u32 tx_deemph_gen2;
bool clkreq_unused;
+ const struct imx8_pcie_phy_drvdata *drvdata;
};
static int imx8_pcie_phy_init(struct phy *phy)
@@ -68,31 +81,20 @@ static int imx8_pcie_phy_init(struct phy *phy)
reset_control_assert(imx8_phy->reset);
pad_mode = imx8_phy->refclk_pad_mode;
- /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
- imx8_phy->clkreq_unused ?
- 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN,
- IMX8MM_GPR_PCIE_AUX_EN);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_POWER_OFF, 0);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_SSC_EN, 0);
-
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_REF_CLK_SEL,
- pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
- IMX8MM_GPR_PCIE_REF_CLK_EXT :
- IMX8MM_GPR_PCIE_REF_CLK_PLL);
- usleep_range(100, 200);
-
- /* Do the PHY common block reset */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_CMN_RST,
- IMX8MM_GPR_PCIE_CMN_RST);
- usleep_range(200, 500);
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MM:
+ /* Tune PHY de-emphasis setting to pass PCIe compliance. */
+ if (imx8_phy->tx_deemph_gen1)
+ writel(imx8_phy->tx_deemph_gen1,
+ imx8_phy->base + PCIE_PHY_TRSV_REG5);
+ if (imx8_phy->tx_deemph_gen2)
+ writel(imx8_phy->tx_deemph_gen2,
+ imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ break;
+ case IMX8MP:
+ reset_control_assert(imx8_phy->perst);
+ break;
+ }
if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
@@ -120,20 +122,44 @@ static int imx8_pcie_phy_init(struct phy *phy)
imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
}
- /* Tune PHY de-emphasis setting to pass PCIe compliance. */
- if (imx8_phy->tx_deemph_gen1)
- writel(imx8_phy->tx_deemph_gen1,
- imx8_phy->base + PCIE_PHY_TRSV_REG5);
- if (imx8_phy->tx_deemph_gen2)
- writel(imx8_phy->tx_deemph_gen2,
- imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
+ imx8_phy->clkreq_unused ?
+ 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN,
+ IMX8MM_GPR_PCIE_AUX_EN);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_POWER_OFF, 0);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_SSC_EN, 0);
+
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_REF_CLK_SEL,
+ pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
+ IMX8MM_GPR_PCIE_REF_CLK_EXT :
+ IMX8MM_GPR_PCIE_REF_CLK_PLL);
+ usleep_range(100, 200);
- reset_control_deassert(imx8_phy->reset);
+ /* Do the PHY common block reset */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_CMN_RST,
+ IMX8MM_GPR_PCIE_CMN_RST);
+
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MP:
+ reset_control_deassert(imx8_phy->perst);
+ fallthrough;
+ case IMX8MM:
+ reset_control_deassert(imx8_phy->reset);
+ usleep_range(200, 500);
+ break;
+ }
/* Polling to check the phy is ready or not. */
- ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
- val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
- 10, 20000);
+ ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
+ val, val == ANA_PLL_DONE, 10, 20000);
return ret;
}
@@ -160,6 +186,25 @@ static const struct phy_ops imx8_pcie_phy_ops = {
.owner = THIS_MODULE,
};
+static const struct imx8_pcie_phy_drvdata drvdata[] = {
+ [IMX8MM] = {
+ .variant = IMX8MM,
+ .gpr = "fsl,imx8mm-iomuxc-gpr",
+ },
+
+ [IMX8MP] = {
+ .variant = IMX8MP,
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
+ },
+};
+
+static const struct of_device_id imx8_pcie_phy_of_match[] = {
+ {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
+ {.compatible = "fsl,imx8mp-pcie-phy", .data = &drvdata[IMX8MP], },
+ { },
+};
+MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
+
static int imx8_pcie_phy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
@@ -172,6 +217,8 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
if (!imx8_phy)
return -ENOMEM;
+ imx8_phy->drvdata = of_device_get_match_data(dev);
+
/* get PHY refclk pad mode */
of_property_read_u32(np, "fsl,refclk-pad-mode",
&imx8_phy->refclk_pad_mode);
@@ -197,7 +244,7 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
/* Grab GPR config register range */
imx8_phy->iomuxc_gpr =
- syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
if (IS_ERR(imx8_phy->iomuxc_gpr)) {
dev_err(dev, "unable to find iomuxc registers\n");
return PTR_ERR(imx8_phy->iomuxc_gpr);
@@ -209,6 +256,15 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR(imx8_phy->reset);
}
+ if (imx8_phy->drvdata->variant == IMX8MP) {
+ imx8_phy->perst =
+ devm_reset_control_get_exclusive(dev, "perst");
+ if (IS_ERR(imx8_phy->perst)) {
+ dev_err(dev, "Failed to get PCIE PHY PERST control\n");
+ return PTR_ERR(imx8_phy->perst);
+ }
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
imx8_phy->base = devm_ioremap_resource(dev, res);
if (IS_ERR(imx8_phy->base))
@@ -225,12 +281,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
-static const struct of_device_id imx8_pcie_phy_of_match[] = {
- {.compatible = "fsl,imx8mm-pcie-phy",},
- { },
-};
-MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
-
static struct platform_driver imx8_pcie_phy_driver = {
.probe = imx8_pcie_phy_probe,
.driver = {
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
@ 2022-09-20 7:38 ` Richard Zhu
0 siblings, 0 replies; 15+ messages in thread
From: Richard Zhu @ 2022-09-20 7:38 UTC (permalink / raw)
To: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
vkoul, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
Add i.MX8MP PCIe PHY support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 144 ++++++++++++++-------
1 file changed, 97 insertions(+), 47 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index ad7d2edfc414..bef0e9d64244 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -11,6 +11,9 @@
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_device.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -31,12 +34,10 @@
#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
#define ANA_AUX_TX_LVL GENMASK(3, 0)
-#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
-#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
+#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
+#define ANA_PLL_DONE 0x3
#define PCIE_PHY_TRSV_REG5 0x414
-#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
#define PCIE_PHY_TRSV_REG6 0x418
-#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
@@ -47,16 +48,28 @@
#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
+enum imx8_pcie_phy_type {
+ IMX8MM,
+ IMX8MP,
+};
+
+struct imx8_pcie_phy_drvdata {
+ enum imx8_pcie_phy_type variant;
+ const char *gpr;
+};
+
struct imx8_pcie_phy {
void __iomem *base;
struct clk *clk;
struct phy *phy;
struct regmap *iomuxc_gpr;
struct reset_control *reset;
+ struct reset_control *perst;
u32 refclk_pad_mode;
u32 tx_deemph_gen1;
u32 tx_deemph_gen2;
bool clkreq_unused;
+ const struct imx8_pcie_phy_drvdata *drvdata;
};
static int imx8_pcie_phy_init(struct phy *phy)
@@ -68,31 +81,20 @@ static int imx8_pcie_phy_init(struct phy *phy)
reset_control_assert(imx8_phy->reset);
pad_mode = imx8_phy->refclk_pad_mode;
- /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
- imx8_phy->clkreq_unused ?
- 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN,
- IMX8MM_GPR_PCIE_AUX_EN);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_POWER_OFF, 0);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_SSC_EN, 0);
-
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_REF_CLK_SEL,
- pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
- IMX8MM_GPR_PCIE_REF_CLK_EXT :
- IMX8MM_GPR_PCIE_REF_CLK_PLL);
- usleep_range(100, 200);
-
- /* Do the PHY common block reset */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_CMN_RST,
- IMX8MM_GPR_PCIE_CMN_RST);
- usleep_range(200, 500);
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MM:
+ /* Tune PHY de-emphasis setting to pass PCIe compliance. */
+ if (imx8_phy->tx_deemph_gen1)
+ writel(imx8_phy->tx_deemph_gen1,
+ imx8_phy->base + PCIE_PHY_TRSV_REG5);
+ if (imx8_phy->tx_deemph_gen2)
+ writel(imx8_phy->tx_deemph_gen2,
+ imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ break;
+ case IMX8MP:
+ reset_control_assert(imx8_phy->perst);
+ break;
+ }
if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
@@ -120,20 +122,44 @@ static int imx8_pcie_phy_init(struct phy *phy)
imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
}
- /* Tune PHY de-emphasis setting to pass PCIe compliance. */
- if (imx8_phy->tx_deemph_gen1)
- writel(imx8_phy->tx_deemph_gen1,
- imx8_phy->base + PCIE_PHY_TRSV_REG5);
- if (imx8_phy->tx_deemph_gen2)
- writel(imx8_phy->tx_deemph_gen2,
- imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
+ imx8_phy->clkreq_unused ?
+ 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN,
+ IMX8MM_GPR_PCIE_AUX_EN);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_POWER_OFF, 0);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_SSC_EN, 0);
+
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_REF_CLK_SEL,
+ pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
+ IMX8MM_GPR_PCIE_REF_CLK_EXT :
+ IMX8MM_GPR_PCIE_REF_CLK_PLL);
+ usleep_range(100, 200);
- reset_control_deassert(imx8_phy->reset);
+ /* Do the PHY common block reset */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_CMN_RST,
+ IMX8MM_GPR_PCIE_CMN_RST);
+
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MP:
+ reset_control_deassert(imx8_phy->perst);
+ fallthrough;
+ case IMX8MM:
+ reset_control_deassert(imx8_phy->reset);
+ usleep_range(200, 500);
+ break;
+ }
/* Polling to check the phy is ready or not. */
- ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
- val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
- 10, 20000);
+ ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
+ val, val == ANA_PLL_DONE, 10, 20000);
return ret;
}
@@ -160,6 +186,25 @@ static const struct phy_ops imx8_pcie_phy_ops = {
.owner = THIS_MODULE,
};
+static const struct imx8_pcie_phy_drvdata drvdata[] = {
+ [IMX8MM] = {
+ .variant = IMX8MM,
+ .gpr = "fsl,imx8mm-iomuxc-gpr",
+ },
+
+ [IMX8MP] = {
+ .variant = IMX8MP,
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
+ },
+};
+
+static const struct of_device_id imx8_pcie_phy_of_match[] = {
+ {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
+ {.compatible = "fsl,imx8mp-pcie-phy", .data = &drvdata[IMX8MP], },
+ { },
+};
+MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
+
static int imx8_pcie_phy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
@@ -172,6 +217,8 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
if (!imx8_phy)
return -ENOMEM;
+ imx8_phy->drvdata = of_device_get_match_data(dev);
+
/* get PHY refclk pad mode */
of_property_read_u32(np, "fsl,refclk-pad-mode",
&imx8_phy->refclk_pad_mode);
@@ -197,7 +244,7 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
/* Grab GPR config register range */
imx8_phy->iomuxc_gpr =
- syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
if (IS_ERR(imx8_phy->iomuxc_gpr)) {
dev_err(dev, "unable to find iomuxc registers\n");
return PTR_ERR(imx8_phy->iomuxc_gpr);
@@ -209,6 +256,15 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR(imx8_phy->reset);
}
+ if (imx8_phy->drvdata->variant == IMX8MP) {
+ imx8_phy->perst =
+ devm_reset_control_get_exclusive(dev, "perst");
+ if (IS_ERR(imx8_phy->perst)) {
+ dev_err(dev, "Failed to get PCIE PHY PERST control\n");
+ return PTR_ERR(imx8_phy->perst);
+ }
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
imx8_phy->base = devm_ioremap_resource(dev, res);
if (IS_ERR(imx8_phy->base))
@@ -225,12 +281,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
-static const struct of_device_id imx8_pcie_phy_of_match[] = {
- {.compatible = "fsl,imx8mm-pcie-phy",},
- { },
-};
-MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
-
static struct platform_driver imx8_pcie_phy_driver = {
.probe = imx8_pcie_phy_probe,
.driver = {
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
@ 2022-09-20 7:38 ` Richard Zhu
0 siblings, 0 replies; 15+ messages in thread
From: Richard Zhu @ 2022-09-20 7:38 UTC (permalink / raw)
To: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
vkoul, alexander.stein, marex, richard.leitner
Cc: linux-phy, devicetree, linux-pci, linux-arm-kernel, linux-kernel,
kernel, linux-imx, Richard Zhu
Add i.MX8MP PCIe PHY support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Richard Leitner <richard.leitner@skidata.com>
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 144 ++++++++++++++-------
1 file changed, 97 insertions(+), 47 deletions(-)
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index ad7d2edfc414..bef0e9d64244 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -11,6 +11,9 @@
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/of_device.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -31,12 +34,10 @@
#define IMX8MM_PCIE_PHY_CMN_REG065 0x194
#define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
#define ANA_AUX_TX_LVL GENMASK(3, 0)
-#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
-#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
+#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
+#define ANA_PLL_DONE 0x3
#define PCIE_PHY_TRSV_REG5 0x414
-#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
#define PCIE_PHY_TRSV_REG6 0x418
-#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
@@ -47,16 +48,28 @@
#define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
+enum imx8_pcie_phy_type {
+ IMX8MM,
+ IMX8MP,
+};
+
+struct imx8_pcie_phy_drvdata {
+ enum imx8_pcie_phy_type variant;
+ const char *gpr;
+};
+
struct imx8_pcie_phy {
void __iomem *base;
struct clk *clk;
struct phy *phy;
struct regmap *iomuxc_gpr;
struct reset_control *reset;
+ struct reset_control *perst;
u32 refclk_pad_mode;
u32 tx_deemph_gen1;
u32 tx_deemph_gen2;
bool clkreq_unused;
+ const struct imx8_pcie_phy_drvdata *drvdata;
};
static int imx8_pcie_phy_init(struct phy *phy)
@@ -68,31 +81,20 @@ static int imx8_pcie_phy_init(struct phy *phy)
reset_control_assert(imx8_phy->reset);
pad_mode = imx8_phy->refclk_pad_mode;
- /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
- imx8_phy->clkreq_unused ?
- 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_AUX_EN,
- IMX8MM_GPR_PCIE_AUX_EN);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_POWER_OFF, 0);
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_SSC_EN, 0);
-
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_REF_CLK_SEL,
- pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
- IMX8MM_GPR_PCIE_REF_CLK_EXT :
- IMX8MM_GPR_PCIE_REF_CLK_PLL);
- usleep_range(100, 200);
-
- /* Do the PHY common block reset */
- regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
- IMX8MM_GPR_PCIE_CMN_RST,
- IMX8MM_GPR_PCIE_CMN_RST);
- usleep_range(200, 500);
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MM:
+ /* Tune PHY de-emphasis setting to pass PCIe compliance. */
+ if (imx8_phy->tx_deemph_gen1)
+ writel(imx8_phy->tx_deemph_gen1,
+ imx8_phy->base + PCIE_PHY_TRSV_REG5);
+ if (imx8_phy->tx_deemph_gen2)
+ writel(imx8_phy->tx_deemph_gen2,
+ imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ break;
+ case IMX8MP:
+ reset_control_assert(imx8_phy->perst);
+ break;
+ }
if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
@@ -120,20 +122,44 @@ static int imx8_pcie_phy_init(struct phy *phy)
imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
}
- /* Tune PHY de-emphasis setting to pass PCIe compliance. */
- if (imx8_phy->tx_deemph_gen1)
- writel(imx8_phy->tx_deemph_gen1,
- imx8_phy->base + PCIE_PHY_TRSV_REG5);
- if (imx8_phy->tx_deemph_gen2)
- writel(imx8_phy->tx_deemph_gen2,
- imx8_phy->base + PCIE_PHY_TRSV_REG6);
+ /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
+ imx8_phy->clkreq_unused ?
+ 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_AUX_EN,
+ IMX8MM_GPR_PCIE_AUX_EN);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_POWER_OFF, 0);
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_SSC_EN, 0);
+
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_REF_CLK_SEL,
+ pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
+ IMX8MM_GPR_PCIE_REF_CLK_EXT :
+ IMX8MM_GPR_PCIE_REF_CLK_PLL);
+ usleep_range(100, 200);
- reset_control_deassert(imx8_phy->reset);
+ /* Do the PHY common block reset */
+ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
+ IMX8MM_GPR_PCIE_CMN_RST,
+ IMX8MM_GPR_PCIE_CMN_RST);
+
+ switch (imx8_phy->drvdata->variant) {
+ case IMX8MP:
+ reset_control_deassert(imx8_phy->perst);
+ fallthrough;
+ case IMX8MM:
+ reset_control_deassert(imx8_phy->reset);
+ usleep_range(200, 500);
+ break;
+ }
/* Polling to check the phy is ready or not. */
- ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
- val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
- 10, 20000);
+ ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
+ val, val == ANA_PLL_DONE, 10, 20000);
return ret;
}
@@ -160,6 +186,25 @@ static const struct phy_ops imx8_pcie_phy_ops = {
.owner = THIS_MODULE,
};
+static const struct imx8_pcie_phy_drvdata drvdata[] = {
+ [IMX8MM] = {
+ .variant = IMX8MM,
+ .gpr = "fsl,imx8mm-iomuxc-gpr",
+ },
+
+ [IMX8MP] = {
+ .variant = IMX8MP,
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
+ },
+};
+
+static const struct of_device_id imx8_pcie_phy_of_match[] = {
+ {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
+ {.compatible = "fsl,imx8mp-pcie-phy", .data = &drvdata[IMX8MP], },
+ { },
+};
+MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
+
static int imx8_pcie_phy_probe(struct platform_device *pdev)
{
struct phy_provider *phy_provider;
@@ -172,6 +217,8 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
if (!imx8_phy)
return -ENOMEM;
+ imx8_phy->drvdata = of_device_get_match_data(dev);
+
/* get PHY refclk pad mode */
of_property_read_u32(np, "fsl,refclk-pad-mode",
&imx8_phy->refclk_pad_mode);
@@ -197,7 +244,7 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
/* Grab GPR config register range */
imx8_phy->iomuxc_gpr =
- syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
if (IS_ERR(imx8_phy->iomuxc_gpr)) {
dev_err(dev, "unable to find iomuxc registers\n");
return PTR_ERR(imx8_phy->iomuxc_gpr);
@@ -209,6 +256,15 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR(imx8_phy->reset);
}
+ if (imx8_phy->drvdata->variant == IMX8MP) {
+ imx8_phy->perst =
+ devm_reset_control_get_exclusive(dev, "perst");
+ if (IS_ERR(imx8_phy->perst)) {
+ dev_err(dev, "Failed to get PCIE PHY PERST control\n");
+ return PTR_ERR(imx8_phy->perst);
+ }
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
imx8_phy->base = devm_ioremap_resource(dev, res);
if (IS_ERR(imx8_phy->base))
@@ -225,12 +281,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
-static const struct of_device_id imx8_pcie_phy_of_match[] = {
- {.compatible = "fsl,imx8mm-pcie-phy",},
- { },
-};
-MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
-
static struct platform_driver imx8_pcie_phy_driver = {
.probe = imx8_pcie_phy_probe,
.driver = {
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
2022-09-20 7:38 ` Richard Zhu
(?)
@ 2022-09-24 7:32 ` Vinod Koul
-1 siblings, 0 replies; 15+ messages in thread
From: Vinod Koul @ 2022-09-24 7:32 UTC (permalink / raw)
To: Richard Zhu
Cc: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
alexander.stein, marex, richard.leitner, linux-phy, devicetree,
linux-pci, linux-arm-kernel, linux-kernel, kernel, linux-imx
On 20-09-22, 15:38, Richard Zhu wrote:
> Add i.MX8MP PCIe PHY support.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 144 ++++++++++++++-------
> 1 file changed, 97 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> index ad7d2edfc414..bef0e9d64244 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> @@ -11,6 +11,9 @@
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> #include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_device.h>
why do you need all these headers..?
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> @@ -31,12 +34,10 @@
> #define IMX8MM_PCIE_PHY_CMN_REG065 0x194
> #define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
> #define ANA_AUX_TX_LVL GENMASK(3, 0)
> -#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
> -#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
> +#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
why this change?
> +#define ANA_PLL_DONE 0x3
> #define PCIE_PHY_TRSV_REG5 0x414
> -#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
> #define PCIE_PHY_TRSV_REG6 0x418
> -#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
>
> #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
> #define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
> @@ -47,16 +48,28 @@
> #define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
> #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
>
> +enum imx8_pcie_phy_type {
> + IMX8MM,
> + IMX8MP,
> +};
> +
> +struct imx8_pcie_phy_drvdata {
> + enum imx8_pcie_phy_type variant;
> + const char *gpr;
> +};
> +
> struct imx8_pcie_phy {
> void __iomem *base;
> struct clk *clk;
> struct phy *phy;
> struct regmap *iomuxc_gpr;
> struct reset_control *reset;
> + struct reset_control *perst;
> u32 refclk_pad_mode;
> u32 tx_deemph_gen1;
> u32 tx_deemph_gen2;
> bool clkreq_unused;
> + const struct imx8_pcie_phy_drvdata *drvdata;
> };
>
> static int imx8_pcie_phy_init(struct phy *phy)
> @@ -68,31 +81,20 @@ static int imx8_pcie_phy_init(struct phy *phy)
> reset_control_assert(imx8_phy->reset);
>
> pad_mode = imx8_phy->refclk_pad_mode;
> - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> - imx8_phy->clkreq_unused ?
> - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_AUX_EN,
> - IMX8MM_GPR_PCIE_AUX_EN);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_POWER_OFF, 0);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_SSC_EN, 0);
> -
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_REF_CLK_SEL,
> - pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> - IMX8MM_GPR_PCIE_REF_CLK_EXT :
> - IMX8MM_GPR_PCIE_REF_CLK_PLL);
> - usleep_range(100, 200);
> -
> - /* Do the PHY common block reset */
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_CMN_RST,
> - IMX8MM_GPR_PCIE_CMN_RST);
> - usleep_range(200, 500);
> + switch (imx8_phy->drvdata->variant) {
> + case IMX8MM:
> + /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> + if (imx8_phy->tx_deemph_gen1)
> + writel(imx8_phy->tx_deemph_gen1,
> + imx8_phy->base + PCIE_PHY_TRSV_REG5);
> + if (imx8_phy->tx_deemph_gen2)
> + writel(imx8_phy->tx_deemph_gen2,
> + imx8_phy->base + PCIE_PHY_TRSV_REG6);
> + break;
> + case IMX8MP:
> + reset_control_assert(imx8_phy->perst);
> + break;
> + }
>
> if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
> @@ -120,20 +122,44 @@ static int imx8_pcie_phy_init(struct phy *phy)
> imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
> }
>
> - /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> - if (imx8_phy->tx_deemph_gen1)
> - writel(imx8_phy->tx_deemph_gen1,
> - imx8_phy->base + PCIE_PHY_TRSV_REG5);
> - if (imx8_phy->tx_deemph_gen2)
> - writel(imx8_phy->tx_deemph_gen2,
> - imx8_phy->base + PCIE_PHY_TRSV_REG6);
> + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> + imx8_phy->clkreq_unused ?
> + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_AUX_EN,
> + IMX8MM_GPR_PCIE_AUX_EN);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_POWER_OFF, 0);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_SSC_EN, 0);
> +
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_REF_CLK_SEL,
> + pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> + IMX8MM_GPR_PCIE_REF_CLK_EXT :
> + IMX8MM_GPR_PCIE_REF_CLK_PLL);
Lets do code reorg in a separate patch and then add support for new SOC,
that is more reviewable that this big pile of changes
> + usleep_range(100, 200);
>
> - reset_control_deassert(imx8_phy->reset);
> + /* Do the PHY common block reset */
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_CMN_RST,
> + IMX8MM_GPR_PCIE_CMN_RST);
> +
> + switch (imx8_phy->drvdata->variant) {
> + case IMX8MP:
> + reset_control_deassert(imx8_phy->perst);
> + fallthrough;
> + case IMX8MM:
> + reset_control_deassert(imx8_phy->reset);
> + usleep_range(200, 500);
> + break;
> + }
>
> /* Polling to check the phy is ready or not. */
> - ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
> - val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
> - 10, 20000);
> + ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
> + val, val == ANA_PLL_DONE, 10, 20000);
> return ret;
> }
>
> @@ -160,6 +186,25 @@ static const struct phy_ops imx8_pcie_phy_ops = {
> .owner = THIS_MODULE,
> };
>
> +static const struct imx8_pcie_phy_drvdata drvdata[] = {
> + [IMX8MM] = {
> + .variant = IMX8MM,
> + .gpr = "fsl,imx8mm-iomuxc-gpr",
> + },
> +
> + [IMX8MP] = {
> + .variant = IMX8MP,
> + .gpr = "fsl,imx8mp-iomuxc-gpr",
> + },
> +};
> +
> +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> + {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
> + {.compatible = "fsl,imx8mp-pcie-phy", .data = &drvdata[IMX8MP], },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> +
> static int imx8_pcie_phy_probe(struct platform_device *pdev)
> {
> struct phy_provider *phy_provider;
> @@ -172,6 +217,8 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> if (!imx8_phy)
> return -ENOMEM;
>
> + imx8_phy->drvdata = of_device_get_match_data(dev);
> +
> /* get PHY refclk pad mode */
> of_property_read_u32(np, "fsl,refclk-pad-mode",
> &imx8_phy->refclk_pad_mode);
> @@ -197,7 +244,7 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
>
> /* Grab GPR config register range */
> imx8_phy->iomuxc_gpr =
> - syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> + syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
> if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> dev_err(dev, "unable to find iomuxc registers\n");
> return PTR_ERR(imx8_phy->iomuxc_gpr);
> @@ -209,6 +256,15 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> return PTR_ERR(imx8_phy->reset);
> }
>
> + if (imx8_phy->drvdata->variant == IMX8MP) {
> + imx8_phy->perst =
> + devm_reset_control_get_exclusive(dev, "perst");
> + if (IS_ERR(imx8_phy->perst)) {
> + dev_err(dev, "Failed to get PCIE PHY PERST control\n");
> + return PTR_ERR(imx8_phy->perst);
> + }
> + }
> +
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> imx8_phy->base = devm_ioremap_resource(dev, res);
> if (IS_ERR(imx8_phy->base))
> @@ -225,12 +281,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> return PTR_ERR_OR_ZERO(phy_provider);
> }
>
> -static const struct of_device_id imx8_pcie_phy_of_match[] = {
> - {.compatible = "fsl,imx8mm-pcie-phy",},
> - { },
> -};
> -MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> -
> static struct platform_driver imx8_pcie_phy_driver = {
> .probe = imx8_pcie_phy_probe,
> .driver = {
> --
> 2.25.1
--
~Vinod
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
@ 2022-09-24 7:32 ` Vinod Koul
0 siblings, 0 replies; 15+ messages in thread
From: Vinod Koul @ 2022-09-24 7:32 UTC (permalink / raw)
To: Richard Zhu
Cc: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
alexander.stein, marex, richard.leitner, linux-phy, devicetree,
linux-pci, linux-arm-kernel, linux-kernel, kernel, linux-imx
On 20-09-22, 15:38, Richard Zhu wrote:
> Add i.MX8MP PCIe PHY support.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 144 ++++++++++++++-------
> 1 file changed, 97 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> index ad7d2edfc414..bef0e9d64244 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> @@ -11,6 +11,9 @@
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> #include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_device.h>
why do you need all these headers..?
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> @@ -31,12 +34,10 @@
> #define IMX8MM_PCIE_PHY_CMN_REG065 0x194
> #define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
> #define ANA_AUX_TX_LVL GENMASK(3, 0)
> -#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
> -#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
> +#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
why this change?
> +#define ANA_PLL_DONE 0x3
> #define PCIE_PHY_TRSV_REG5 0x414
> -#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
> #define PCIE_PHY_TRSV_REG6 0x418
> -#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
>
> #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
> #define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
> @@ -47,16 +48,28 @@
> #define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
> #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
>
> +enum imx8_pcie_phy_type {
> + IMX8MM,
> + IMX8MP,
> +};
> +
> +struct imx8_pcie_phy_drvdata {
> + enum imx8_pcie_phy_type variant;
> + const char *gpr;
> +};
> +
> struct imx8_pcie_phy {
> void __iomem *base;
> struct clk *clk;
> struct phy *phy;
> struct regmap *iomuxc_gpr;
> struct reset_control *reset;
> + struct reset_control *perst;
> u32 refclk_pad_mode;
> u32 tx_deemph_gen1;
> u32 tx_deemph_gen2;
> bool clkreq_unused;
> + const struct imx8_pcie_phy_drvdata *drvdata;
> };
>
> static int imx8_pcie_phy_init(struct phy *phy)
> @@ -68,31 +81,20 @@ static int imx8_pcie_phy_init(struct phy *phy)
> reset_control_assert(imx8_phy->reset);
>
> pad_mode = imx8_phy->refclk_pad_mode;
> - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> - imx8_phy->clkreq_unused ?
> - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_AUX_EN,
> - IMX8MM_GPR_PCIE_AUX_EN);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_POWER_OFF, 0);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_SSC_EN, 0);
> -
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_REF_CLK_SEL,
> - pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> - IMX8MM_GPR_PCIE_REF_CLK_EXT :
> - IMX8MM_GPR_PCIE_REF_CLK_PLL);
> - usleep_range(100, 200);
> -
> - /* Do the PHY common block reset */
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_CMN_RST,
> - IMX8MM_GPR_PCIE_CMN_RST);
> - usleep_range(200, 500);
> + switch (imx8_phy->drvdata->variant) {
> + case IMX8MM:
> + /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> + if (imx8_phy->tx_deemph_gen1)
> + writel(imx8_phy->tx_deemph_gen1,
> + imx8_phy->base + PCIE_PHY_TRSV_REG5);
> + if (imx8_phy->tx_deemph_gen2)
> + writel(imx8_phy->tx_deemph_gen2,
> + imx8_phy->base + PCIE_PHY_TRSV_REG6);
> + break;
> + case IMX8MP:
> + reset_control_assert(imx8_phy->perst);
> + break;
> + }
>
> if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
> @@ -120,20 +122,44 @@ static int imx8_pcie_phy_init(struct phy *phy)
> imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
> }
>
> - /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> - if (imx8_phy->tx_deemph_gen1)
> - writel(imx8_phy->tx_deemph_gen1,
> - imx8_phy->base + PCIE_PHY_TRSV_REG5);
> - if (imx8_phy->tx_deemph_gen2)
> - writel(imx8_phy->tx_deemph_gen2,
> - imx8_phy->base + PCIE_PHY_TRSV_REG6);
> + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> + imx8_phy->clkreq_unused ?
> + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_AUX_EN,
> + IMX8MM_GPR_PCIE_AUX_EN);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_POWER_OFF, 0);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_SSC_EN, 0);
> +
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_REF_CLK_SEL,
> + pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> + IMX8MM_GPR_PCIE_REF_CLK_EXT :
> + IMX8MM_GPR_PCIE_REF_CLK_PLL);
Lets do code reorg in a separate patch and then add support for new SOC,
that is more reviewable that this big pile of changes
> + usleep_range(100, 200);
>
> - reset_control_deassert(imx8_phy->reset);
> + /* Do the PHY common block reset */
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_CMN_RST,
> + IMX8MM_GPR_PCIE_CMN_RST);
> +
> + switch (imx8_phy->drvdata->variant) {
> + case IMX8MP:
> + reset_control_deassert(imx8_phy->perst);
> + fallthrough;
> + case IMX8MM:
> + reset_control_deassert(imx8_phy->reset);
> + usleep_range(200, 500);
> + break;
> + }
>
> /* Polling to check the phy is ready or not. */
> - ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
> - val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
> - 10, 20000);
> + ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
> + val, val == ANA_PLL_DONE, 10, 20000);
> return ret;
> }
>
> @@ -160,6 +186,25 @@ static const struct phy_ops imx8_pcie_phy_ops = {
> .owner = THIS_MODULE,
> };
>
> +static const struct imx8_pcie_phy_drvdata drvdata[] = {
> + [IMX8MM] = {
> + .variant = IMX8MM,
> + .gpr = "fsl,imx8mm-iomuxc-gpr",
> + },
> +
> + [IMX8MP] = {
> + .variant = IMX8MP,
> + .gpr = "fsl,imx8mp-iomuxc-gpr",
> + },
> +};
> +
> +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> + {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
> + {.compatible = "fsl,imx8mp-pcie-phy", .data = &drvdata[IMX8MP], },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> +
> static int imx8_pcie_phy_probe(struct platform_device *pdev)
> {
> struct phy_provider *phy_provider;
> @@ -172,6 +217,8 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> if (!imx8_phy)
> return -ENOMEM;
>
> + imx8_phy->drvdata = of_device_get_match_data(dev);
> +
> /* get PHY refclk pad mode */
> of_property_read_u32(np, "fsl,refclk-pad-mode",
> &imx8_phy->refclk_pad_mode);
> @@ -197,7 +244,7 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
>
> /* Grab GPR config register range */
> imx8_phy->iomuxc_gpr =
> - syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> + syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
> if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> dev_err(dev, "unable to find iomuxc registers\n");
> return PTR_ERR(imx8_phy->iomuxc_gpr);
> @@ -209,6 +256,15 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> return PTR_ERR(imx8_phy->reset);
> }
>
> + if (imx8_phy->drvdata->variant == IMX8MP) {
> + imx8_phy->perst =
> + devm_reset_control_get_exclusive(dev, "perst");
> + if (IS_ERR(imx8_phy->perst)) {
> + dev_err(dev, "Failed to get PCIE PHY PERST control\n");
> + return PTR_ERR(imx8_phy->perst);
> + }
> + }
> +
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> imx8_phy->base = devm_ioremap_resource(dev, res);
> if (IS_ERR(imx8_phy->base))
> @@ -225,12 +281,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> return PTR_ERR_OR_ZERO(phy_provider);
> }
>
> -static const struct of_device_id imx8_pcie_phy_of_match[] = {
> - {.compatible = "fsl,imx8mm-pcie-phy",},
> - { },
> -};
> -MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> -
> static struct platform_driver imx8_pcie_phy_driver = {
> .probe = imx8_pcie_phy_probe,
> .driver = {
> --
> 2.25.1
--
~Vinod
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
@ 2022-09-24 7:32 ` Vinod Koul
0 siblings, 0 replies; 15+ messages in thread
From: Vinod Koul @ 2022-09-24 7:32 UTC (permalink / raw)
To: Richard Zhu
Cc: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
alexander.stein, marex, richard.leitner, linux-phy, devicetree,
linux-pci, linux-arm-kernel, linux-kernel, kernel, linux-imx
On 20-09-22, 15:38, Richard Zhu wrote:
> Add i.MX8MP PCIe PHY support.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 144 ++++++++++++++-------
> 1 file changed, 97 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> index ad7d2edfc414..bef0e9d64244 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> @@ -11,6 +11,9 @@
> #include <linux/mfd/syscon.h>
> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> #include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/of_device.h>
why do you need all these headers..?
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> @@ -31,12 +34,10 @@
> #define IMX8MM_PCIE_PHY_CMN_REG065 0x194
> #define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
> #define ANA_AUX_TX_LVL GENMASK(3, 0)
> -#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
> -#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
> +#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
why this change?
> +#define ANA_PLL_DONE 0x3
> #define PCIE_PHY_TRSV_REG5 0x414
> -#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
> #define PCIE_PHY_TRSV_REG6 0x418
> -#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
>
> #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
> #define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
> @@ -47,16 +48,28 @@
> #define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
> #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
>
> +enum imx8_pcie_phy_type {
> + IMX8MM,
> + IMX8MP,
> +};
> +
> +struct imx8_pcie_phy_drvdata {
> + enum imx8_pcie_phy_type variant;
> + const char *gpr;
> +};
> +
> struct imx8_pcie_phy {
> void __iomem *base;
> struct clk *clk;
> struct phy *phy;
> struct regmap *iomuxc_gpr;
> struct reset_control *reset;
> + struct reset_control *perst;
> u32 refclk_pad_mode;
> u32 tx_deemph_gen1;
> u32 tx_deemph_gen2;
> bool clkreq_unused;
> + const struct imx8_pcie_phy_drvdata *drvdata;
> };
>
> static int imx8_pcie_phy_init(struct phy *phy)
> @@ -68,31 +81,20 @@ static int imx8_pcie_phy_init(struct phy *phy)
> reset_control_assert(imx8_phy->reset);
>
> pad_mode = imx8_phy->refclk_pad_mode;
> - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> - imx8_phy->clkreq_unused ?
> - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_AUX_EN,
> - IMX8MM_GPR_PCIE_AUX_EN);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_POWER_OFF, 0);
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_SSC_EN, 0);
> -
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_REF_CLK_SEL,
> - pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> - IMX8MM_GPR_PCIE_REF_CLK_EXT :
> - IMX8MM_GPR_PCIE_REF_CLK_PLL);
> - usleep_range(100, 200);
> -
> - /* Do the PHY common block reset */
> - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> - IMX8MM_GPR_PCIE_CMN_RST,
> - IMX8MM_GPR_PCIE_CMN_RST);
> - usleep_range(200, 500);
> + switch (imx8_phy->drvdata->variant) {
> + case IMX8MM:
> + /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> + if (imx8_phy->tx_deemph_gen1)
> + writel(imx8_phy->tx_deemph_gen1,
> + imx8_phy->base + PCIE_PHY_TRSV_REG5);
> + if (imx8_phy->tx_deemph_gen2)
> + writel(imx8_phy->tx_deemph_gen2,
> + imx8_phy->base + PCIE_PHY_TRSV_REG6);
> + break;
> + case IMX8MP:
> + reset_control_assert(imx8_phy->perst);
> + break;
> + }
>
> if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
> @@ -120,20 +122,44 @@ static int imx8_pcie_phy_init(struct phy *phy)
> imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
> }
>
> - /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> - if (imx8_phy->tx_deemph_gen1)
> - writel(imx8_phy->tx_deemph_gen1,
> - imx8_phy->base + PCIE_PHY_TRSV_REG5);
> - if (imx8_phy->tx_deemph_gen2)
> - writel(imx8_phy->tx_deemph_gen2,
> - imx8_phy->base + PCIE_PHY_TRSV_REG6);
> + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> + imx8_phy->clkreq_unused ?
> + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_AUX_EN,
> + IMX8MM_GPR_PCIE_AUX_EN);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_POWER_OFF, 0);
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_SSC_EN, 0);
> +
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_REF_CLK_SEL,
> + pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> + IMX8MM_GPR_PCIE_REF_CLK_EXT :
> + IMX8MM_GPR_PCIE_REF_CLK_PLL);
Lets do code reorg in a separate patch and then add support for new SOC,
that is more reviewable that this big pile of changes
> + usleep_range(100, 200);
>
> - reset_control_deassert(imx8_phy->reset);
> + /* Do the PHY common block reset */
> + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> + IMX8MM_GPR_PCIE_CMN_RST,
> + IMX8MM_GPR_PCIE_CMN_RST);
> +
> + switch (imx8_phy->drvdata->variant) {
> + case IMX8MP:
> + reset_control_deassert(imx8_phy->perst);
> + fallthrough;
> + case IMX8MM:
> + reset_control_deassert(imx8_phy->reset);
> + usleep_range(200, 500);
> + break;
> + }
>
> /* Polling to check the phy is ready or not. */
> - ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75,
> - val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
> - 10, 20000);
> + ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
> + val, val == ANA_PLL_DONE, 10, 20000);
> return ret;
> }
>
> @@ -160,6 +186,25 @@ static const struct phy_ops imx8_pcie_phy_ops = {
> .owner = THIS_MODULE,
> };
>
> +static const struct imx8_pcie_phy_drvdata drvdata[] = {
> + [IMX8MM] = {
> + .variant = IMX8MM,
> + .gpr = "fsl,imx8mm-iomuxc-gpr",
> + },
> +
> + [IMX8MP] = {
> + .variant = IMX8MP,
> + .gpr = "fsl,imx8mp-iomuxc-gpr",
> + },
> +};
> +
> +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> + {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
> + {.compatible = "fsl,imx8mp-pcie-phy", .data = &drvdata[IMX8MP], },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> +
> static int imx8_pcie_phy_probe(struct platform_device *pdev)
> {
> struct phy_provider *phy_provider;
> @@ -172,6 +217,8 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> if (!imx8_phy)
> return -ENOMEM;
>
> + imx8_phy->drvdata = of_device_get_match_data(dev);
> +
> /* get PHY refclk pad mode */
> of_property_read_u32(np, "fsl,refclk-pad-mode",
> &imx8_phy->refclk_pad_mode);
> @@ -197,7 +244,7 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
>
> /* Grab GPR config register range */
> imx8_phy->iomuxc_gpr =
> - syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> + syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
> if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> dev_err(dev, "unable to find iomuxc registers\n");
> return PTR_ERR(imx8_phy->iomuxc_gpr);
> @@ -209,6 +256,15 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> return PTR_ERR(imx8_phy->reset);
> }
>
> + if (imx8_phy->drvdata->variant == IMX8MP) {
> + imx8_phy->perst =
> + devm_reset_control_get_exclusive(dev, "perst");
> + if (IS_ERR(imx8_phy->perst)) {
> + dev_err(dev, "Failed to get PCIE PHY PERST control\n");
> + return PTR_ERR(imx8_phy->perst);
> + }
> + }
> +
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> imx8_phy->base = devm_ioremap_resource(dev, res);
> if (IS_ERR(imx8_phy->base))
> @@ -225,12 +281,6 @@ static int imx8_pcie_phy_probe(struct platform_device *pdev)
> return PTR_ERR_OR_ZERO(phy_provider);
> }
>
> -static const struct of_device_id imx8_pcie_phy_of_match[] = {
> - {.compatible = "fsl,imx8mm-pcie-phy",},
> - { },
> -};
> -MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> -
> static struct platform_driver imx8_pcie_phy_driver = {
> .probe = imx8_pcie_phy_probe,
> .driver = {
> --
> 2.25.1
--
~Vinod
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
2022-09-24 7:32 ` Vinod Koul
(?)
@ 2022-09-26 5:11 ` Hongxing Zhu
-1 siblings, 0 replies; 15+ messages in thread
From: Hongxing Zhu @ 2022-09-26 5:11 UTC (permalink / raw)
To: Vinod Koul
Cc: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
alexander.stein, marex, richard.leitner, linux-phy, devicetree,
linux-pci, linux-arm-kernel, linux-kernel, kernel, dl-linux-imx
Hi Vinod:
> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: 2022年9月24日 15:33
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: p.zabel@pengutronix.de; l.stach@pengutronix.de; bhelgaas@google.com;
> lorenzo.pieralisi@arm.com; robh@kernel.org; shawnguo@kernel.org;
> alexander.stein@ew.tq-group.com; marex@denx.de; richard.leitner@linux.dev;
> linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe
> PHY support
>
> On 20-09-22, 15:38, Richard Zhu wrote:
> > Add i.MX8MP PCIe PHY support.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Tested-by: Marek Vasut <marex@denx.de>
> > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 144
> > ++++++++++++++-------
> > 1 file changed, 97 insertions(+), 47 deletions(-)
> >
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > index ad7d2edfc414..bef0e9d64244 100644
> > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > @@ -11,6 +11,9 @@
> > #include <linux/mfd/syscon.h>
> > #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> > #include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_device.h>
>
> why do you need all these headers..?
Thanks for your review comments.
Sorry, forget to clean up them from the v1 series.
Only #include <linux/of_device.h> is needed.
>
> > #include <linux/phy/phy.h>
> > #include <linux/platform_device.h>
> > #include <linux/regmap.h>
> > @@ -31,12 +34,10 @@
> > #define IMX8MM_PCIE_PHY_CMN_REG065 0x194
> > #define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
> > #define ANA_AUX_TX_LVL GENMASK(3, 0)
> > -#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
> > -#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
> > +#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
>
> why this change?
To keep align with the format of the other PHY CMN registers.
Change the "IMX8MM_PCIE_PHY_CMN_REG75" to
"IMX8MM_PCIE_PHY_CMN_REG075".
Would encapsulate them into one standalone patch later.
>
> > +#define ANA_PLL_DONE 0x3
> > #define PCIE_PHY_TRSV_REG5 0x414
> > -#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
> > #define PCIE_PHY_TRSV_REG6 0x418
> > -#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
> >
> > #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
> > #define IMX8MM_GPR_PCIE_REF_CLK_PLL
> FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
> > @@ -47,16 +48,28 @@
> > #define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
> > #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
> >
> > +enum imx8_pcie_phy_type {
> > + IMX8MM,
> > + IMX8MP,
> > +};
> > +
> > +struct imx8_pcie_phy_drvdata {
> > + enum imx8_pcie_phy_type variant;
> > + const char *gpr;
> > +};
> > +
> > struct imx8_pcie_phy {
> > void __iomem *base;
> > struct clk *clk;
> > struct phy *phy;
> > struct regmap *iomuxc_gpr;
> > struct reset_control *reset;
> > + struct reset_control *perst;
> > u32 refclk_pad_mode;
> > u32 tx_deemph_gen1;
> > u32 tx_deemph_gen2;
> > bool clkreq_unused;
> > + const struct imx8_pcie_phy_drvdata *drvdata;
> > };
> >
> > static int imx8_pcie_phy_init(struct phy *phy) @@ -68,31 +81,20 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> > reset_control_assert(imx8_phy->reset);
> >
> > pad_mode = imx8_phy->refclk_pad_mode;
> > - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > - imx8_phy->clkreq_unused ?
> > - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_AUX_EN,
> > - IMX8MM_GPR_PCIE_AUX_EN);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_SSC_EN, 0);
> > -
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > - pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > - IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > - IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > - usleep_range(100, 200);
> > -
> > - /* Do the PHY common block reset */
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_CMN_RST,
> > - IMX8MM_GPR_PCIE_CMN_RST);
> > - usleep_range(200, 500);
> > + switch (imx8_phy->drvdata->variant) {
> > + case IMX8MM:
> > + /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > + if (imx8_phy->tx_deemph_gen1)
> > + writel(imx8_phy->tx_deemph_gen1,
> > + imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > + if (imx8_phy->tx_deemph_gen2)
> > + writel(imx8_phy->tx_deemph_gen2,
> > + imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > + break;
> > + case IMX8MP:
> > + reset_control_assert(imx8_phy->perst);
> > + break;
> > + }
> >
> > if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> > pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { @@ -120,20
> +122,44 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> > imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
> > }
> >
> > - /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > - if (imx8_phy->tx_deemph_gen1)
> > - writel(imx8_phy->tx_deemph_gen1,
> > - imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > - if (imx8_phy->tx_deemph_gen2)
> > - writel(imx8_phy->tx_deemph_gen2,
> > - imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > + imx8_phy->clkreq_unused ?
> > + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_AUX_EN,
> > + IMX8MM_GPR_PCIE_AUX_EN);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_SSC_EN, 0);
> > +
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > + pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > + IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > + IMX8MM_GPR_PCIE_REF_CLK_PLL);
>
> Lets do code reorg in a separate patch and then add support for new SOC, that
> is more reviewable that this big pile of changes
Okay, would spilt them into two patches.
Thanks.
Richard Zhu
Best Regards
>
> > + usleep_range(100, 200);
> >
> > - reset_control_deassert(imx8_phy->reset);
> > + /* Do the PHY common block reset */
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_CMN_RST,
> > + IMX8MM_GPR_PCIE_CMN_RST);
> > +
> > + switch (imx8_phy->drvdata->variant) {
> > + case IMX8MP:
> > + reset_control_deassert(imx8_phy->perst);
> > + fallthrough;
> > + case IMX8MM:
> > + reset_control_deassert(imx8_phy->reset);
> > + usleep_range(200, 500);
> > + break;
> > + }
> >
> > /* Polling to check the phy is ready or not. */
> > - ret = readl_poll_timeout(imx8_phy->base +
> IMX8MM_PCIE_PHY_CMN_REG75,
> > - val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
> > - 10, 20000);
> > + ret = readl_poll_timeout(imx8_phy->base +
> IMX8MM_PCIE_PHY_CMN_REG075,
> > + val, val == ANA_PLL_DONE, 10, 20000);
> > return ret;
> > }
> >
> > @@ -160,6 +186,25 @@ static const struct phy_ops imx8_pcie_phy_ops = {
> > .owner = THIS_MODULE,
> > };
> >
> > +static const struct imx8_pcie_phy_drvdata drvdata[] = {
> > + [IMX8MM] = {
> > + .variant = IMX8MM,
> > + .gpr = "fsl,imx8mm-iomuxc-gpr",
> > + },
> > +
> > + [IMX8MP] = {
> > + .variant = IMX8MP,
> > + .gpr = "fsl,imx8mp-iomuxc-gpr",
> > + },
> > +};
> > +
> > +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > + {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
> > + {.compatible = "fsl,imx8mp-pcie-phy", .data = &drvdata[IMX8MP], },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > +
> > static int imx8_pcie_phy_probe(struct platform_device *pdev) {
> > struct phy_provider *phy_provider;
> > @@ -172,6 +217,8 @@ static int imx8_pcie_phy_probe(struct
> platform_device *pdev)
> > if (!imx8_phy)
> > return -ENOMEM;
> >
> > + imx8_phy->drvdata = of_device_get_match_data(dev);
> > +
> > /* get PHY refclk pad mode */
> > of_property_read_u32(np, "fsl,refclk-pad-mode",
> > &imx8_phy->refclk_pad_mode);
> > @@ -197,7 +244,7 @@ static int imx8_pcie_phy_probe(struct
> > platform_device *pdev)
> >
> > /* Grab GPR config register range */
> > imx8_phy->iomuxc_gpr =
> > - syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> > + syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
> > if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> > dev_err(dev, "unable to find iomuxc registers\n");
> > return PTR_ERR(imx8_phy->iomuxc_gpr); @@ -209,6 +256,15 @@
> static
> > int imx8_pcie_phy_probe(struct platform_device *pdev)
> > return PTR_ERR(imx8_phy->reset);
> > }
> >
> > + if (imx8_phy->drvdata->variant == IMX8MP) {
> > + imx8_phy->perst =
> > + devm_reset_control_get_exclusive(dev, "perst");
> > + if (IS_ERR(imx8_phy->perst)) {
> > + dev_err(dev, "Failed to get PCIE PHY PERST control\n");
> > + return PTR_ERR(imx8_phy->perst);
> > + }
> > + }
> > +
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > imx8_phy->base = devm_ioremap_resource(dev, res);
> > if (IS_ERR(imx8_phy->base))
> > @@ -225,12 +281,6 @@ static int imx8_pcie_phy_probe(struct
> platform_device *pdev)
> > return PTR_ERR_OR_ZERO(phy_provider); }
> >
> > -static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > - {.compatible = "fsl,imx8mm-pcie-phy",},
> > - { },
> > -};
> > -MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > -
> > static struct platform_driver imx8_pcie_phy_driver = {
> > .probe = imx8_pcie_phy_probe,
> > .driver = {
> > --
> > 2.25.1
>
> --
> ~Vinod
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
@ 2022-09-26 5:11 ` Hongxing Zhu
0 siblings, 0 replies; 15+ messages in thread
From: Hongxing Zhu @ 2022-09-26 5:11 UTC (permalink / raw)
To: Vinod Koul
Cc: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
alexander.stein, marex, richard.leitner, linux-phy, devicetree,
linux-pci, linux-arm-kernel, linux-kernel, kernel, dl-linux-imx
Hi Vinod:
> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: 2022年9月24日 15:33
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: p.zabel@pengutronix.de; l.stach@pengutronix.de; bhelgaas@google.com;
> lorenzo.pieralisi@arm.com; robh@kernel.org; shawnguo@kernel.org;
> alexander.stein@ew.tq-group.com; marex@denx.de; richard.leitner@linux.dev;
> linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe
> PHY support
>
> On 20-09-22, 15:38, Richard Zhu wrote:
> > Add i.MX8MP PCIe PHY support.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Tested-by: Marek Vasut <marex@denx.de>
> > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 144
> > ++++++++++++++-------
> > 1 file changed, 97 insertions(+), 47 deletions(-)
> >
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > index ad7d2edfc414..bef0e9d64244 100644
> > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > @@ -11,6 +11,9 @@
> > #include <linux/mfd/syscon.h>
> > #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> > #include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_device.h>
>
> why do you need all these headers..?
Thanks for your review comments.
Sorry, forget to clean up them from the v1 series.
Only #include <linux/of_device.h> is needed.
>
> > #include <linux/phy/phy.h>
> > #include <linux/platform_device.h>
> > #include <linux/regmap.h>
> > @@ -31,12 +34,10 @@
> > #define IMX8MM_PCIE_PHY_CMN_REG065 0x194
> > #define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
> > #define ANA_AUX_TX_LVL GENMASK(3, 0)
> > -#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
> > -#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
> > +#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
>
> why this change?
To keep align with the format of the other PHY CMN registers.
Change the "IMX8MM_PCIE_PHY_CMN_REG75" to
"IMX8MM_PCIE_PHY_CMN_REG075".
Would encapsulate them into one standalone patch later.
>
> > +#define ANA_PLL_DONE 0x3
> > #define PCIE_PHY_TRSV_REG5 0x414
> > -#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
> > #define PCIE_PHY_TRSV_REG6 0x418
> > -#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
> >
> > #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
> > #define IMX8MM_GPR_PCIE_REF_CLK_PLL
> FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
> > @@ -47,16 +48,28 @@
> > #define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
> > #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
> >
> > +enum imx8_pcie_phy_type {
> > + IMX8MM,
> > + IMX8MP,
> > +};
> > +
> > +struct imx8_pcie_phy_drvdata {
> > + enum imx8_pcie_phy_type variant;
> > + const char *gpr;
> > +};
> > +
> > struct imx8_pcie_phy {
> > void __iomem *base;
> > struct clk *clk;
> > struct phy *phy;
> > struct regmap *iomuxc_gpr;
> > struct reset_control *reset;
> > + struct reset_control *perst;
> > u32 refclk_pad_mode;
> > u32 tx_deemph_gen1;
> > u32 tx_deemph_gen2;
> > bool clkreq_unused;
> > + const struct imx8_pcie_phy_drvdata *drvdata;
> > };
> >
> > static int imx8_pcie_phy_init(struct phy *phy) @@ -68,31 +81,20 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> > reset_control_assert(imx8_phy->reset);
> >
> > pad_mode = imx8_phy->refclk_pad_mode;
> > - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > - imx8_phy->clkreq_unused ?
> > - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_AUX_EN,
> > - IMX8MM_GPR_PCIE_AUX_EN);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_SSC_EN, 0);
> > -
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > - pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > - IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > - IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > - usleep_range(100, 200);
> > -
> > - /* Do the PHY common block reset */
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_CMN_RST,
> > - IMX8MM_GPR_PCIE_CMN_RST);
> > - usleep_range(200, 500);
> > + switch (imx8_phy->drvdata->variant) {
> > + case IMX8MM:
> > + /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > + if (imx8_phy->tx_deemph_gen1)
> > + writel(imx8_phy->tx_deemph_gen1,
> > + imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > + if (imx8_phy->tx_deemph_gen2)
> > + writel(imx8_phy->tx_deemph_gen2,
> > + imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > + break;
> > + case IMX8MP:
> > + reset_control_assert(imx8_phy->perst);
> > + break;
> > + }
> >
> > if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> > pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { @@ -120,20
> +122,44 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> > imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
> > }
> >
> > - /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > - if (imx8_phy->tx_deemph_gen1)
> > - writel(imx8_phy->tx_deemph_gen1,
> > - imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > - if (imx8_phy->tx_deemph_gen2)
> > - writel(imx8_phy->tx_deemph_gen2,
> > - imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > + imx8_phy->clkreq_unused ?
> > + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_AUX_EN,
> > + IMX8MM_GPR_PCIE_AUX_EN);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_SSC_EN, 0);
> > +
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > + pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > + IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > + IMX8MM_GPR_PCIE_REF_CLK_PLL);
>
> Lets do code reorg in a separate patch and then add support for new SOC, that
> is more reviewable that this big pile of changes
Okay, would spilt them into two patches.
Thanks.
Richard Zhu
Best Regards
>
> > + usleep_range(100, 200);
> >
> > - reset_control_deassert(imx8_phy->reset);
> > + /* Do the PHY common block reset */
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_CMN_RST,
> > + IMX8MM_GPR_PCIE_CMN_RST);
> > +
> > + switch (imx8_phy->drvdata->variant) {
> > + case IMX8MP:
> > + reset_control_deassert(imx8_phy->perst);
> > + fallthrough;
> > + case IMX8MM:
> > + reset_control_deassert(imx8_phy->reset);
> > + usleep_range(200, 500);
> > + break;
> > + }
> >
> > /* Polling to check the phy is ready or not. */
> > - ret = readl_poll_timeout(imx8_phy->base +
> IMX8MM_PCIE_PHY_CMN_REG75,
> > - val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
> > - 10, 20000);
> > + ret = readl_poll_timeout(imx8_phy->base +
> IMX8MM_PCIE_PHY_CMN_REG075,
> > + val, val == ANA_PLL_DONE, 10, 20000);
> > return ret;
> > }
> >
> > @@ -160,6 +186,25 @@ static const struct phy_ops imx8_pcie_phy_ops = {
> > .owner = THIS_MODULE,
> > };
> >
> > +static const struct imx8_pcie_phy_drvdata drvdata[] = {
> > + [IMX8MM] = {
> > + .variant = IMX8MM,
> > + .gpr = "fsl,imx8mm-iomuxc-gpr",
> > + },
> > +
> > + [IMX8MP] = {
> > + .variant = IMX8MP,
> > + .gpr = "fsl,imx8mp-iomuxc-gpr",
> > + },
> > +};
> > +
> > +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > + {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
> > + {.compatible = "fsl,imx8mp-pcie-phy", .data = &drvdata[IMX8MP], },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > +
> > static int imx8_pcie_phy_probe(struct platform_device *pdev) {
> > struct phy_provider *phy_provider;
> > @@ -172,6 +217,8 @@ static int imx8_pcie_phy_probe(struct
> platform_device *pdev)
> > if (!imx8_phy)
> > return -ENOMEM;
> >
> > + imx8_phy->drvdata = of_device_get_match_data(dev);
> > +
> > /* get PHY refclk pad mode */
> > of_property_read_u32(np, "fsl,refclk-pad-mode",
> > &imx8_phy->refclk_pad_mode);
> > @@ -197,7 +244,7 @@ static int imx8_pcie_phy_probe(struct
> > platform_device *pdev)
> >
> > /* Grab GPR config register range */
> > imx8_phy->iomuxc_gpr =
> > - syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> > + syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
> > if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> > dev_err(dev, "unable to find iomuxc registers\n");
> > return PTR_ERR(imx8_phy->iomuxc_gpr); @@ -209,6 +256,15 @@
> static
> > int imx8_pcie_phy_probe(struct platform_device *pdev)
> > return PTR_ERR(imx8_phy->reset);
> > }
> >
> > + if (imx8_phy->drvdata->variant == IMX8MP) {
> > + imx8_phy->perst =
> > + devm_reset_control_get_exclusive(dev, "perst");
> > + if (IS_ERR(imx8_phy->perst)) {
> > + dev_err(dev, "Failed to get PCIE PHY PERST control\n");
> > + return PTR_ERR(imx8_phy->perst);
> > + }
> > + }
> > +
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > imx8_phy->base = devm_ioremap_resource(dev, res);
> > if (IS_ERR(imx8_phy->base))
> > @@ -225,12 +281,6 @@ static int imx8_pcie_phy_probe(struct
> platform_device *pdev)
> > return PTR_ERR_OR_ZERO(phy_provider); }
> >
> > -static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > - {.compatible = "fsl,imx8mm-pcie-phy",},
> > - { },
> > -};
> > -MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > -
> > static struct platform_driver imx8_pcie_phy_driver = {
> > .probe = imx8_pcie_phy_probe,
> > .driver = {
> > --
> > 2.25.1
>
> --
> ~Vinod
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply [flat|nested] 15+ messages in thread
* RE: [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support
@ 2022-09-26 5:11 ` Hongxing Zhu
0 siblings, 0 replies; 15+ messages in thread
From: Hongxing Zhu @ 2022-09-26 5:11 UTC (permalink / raw)
To: Vinod Koul
Cc: p.zabel, l.stach, bhelgaas, lorenzo.pieralisi, robh, shawnguo,
alexander.stein, marex, richard.leitner, linux-phy, devicetree,
linux-pci, linux-arm-kernel, linux-kernel, kernel, dl-linux-imx
Hi Vinod:
> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: 2022年9月24日 15:33
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: p.zabel@pengutronix.de; l.stach@pengutronix.de; bhelgaas@google.com;
> lorenzo.pieralisi@arm.com; robh@kernel.org; shawnguo@kernel.org;
> alexander.stein@ew.tq-group.com; marex@denx.de; richard.leitner@linux.dev;
> linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe
> PHY support
>
> On 20-09-22, 15:38, Richard Zhu wrote:
> > Add i.MX8MP PCIe PHY support.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Tested-by: Marek Vasut <marex@denx.de>
> > Tested-by: Richard Leitner <richard.leitner@skidata.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 144
> > ++++++++++++++-------
> > 1 file changed, 97 insertions(+), 47 deletions(-)
> >
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > index ad7d2edfc414..bef0e9d64244 100644
> > --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
> > @@ -11,6 +11,9 @@
> > #include <linux/mfd/syscon.h>
> > #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
> > #include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_device.h>
>
> why do you need all these headers..?
Thanks for your review comments.
Sorry, forget to clean up them from the v1 series.
Only #include <linux/of_device.h> is needed.
>
> > #include <linux/phy/phy.h>
> > #include <linux/platform_device.h>
> > #include <linux/regmap.h>
> > @@ -31,12 +34,10 @@
> > #define IMX8MM_PCIE_PHY_CMN_REG065 0x194
> > #define ANA_AUX_RX_TERM (BIT(7) | BIT(4))
> > #define ANA_AUX_TX_LVL GENMASK(3, 0)
> > -#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4
> > -#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3
> > +#define IMX8MM_PCIE_PHY_CMN_REG075 0x1D4
>
> why this change?
To keep align with the format of the other PHY CMN registers.
Change the "IMX8MM_PCIE_PHY_CMN_REG75" to
"IMX8MM_PCIE_PHY_CMN_REG075".
Would encapsulate them into one standalone patch later.
>
> > +#define ANA_PLL_DONE 0x3
> > #define PCIE_PHY_TRSV_REG5 0x414
> > -#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D
> > #define PCIE_PHY_TRSV_REG6 0x418
> > -#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF
> >
> > #define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24)
> > #define IMX8MM_GPR_PCIE_REF_CLK_PLL
> FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
> > @@ -47,16 +48,28 @@
> > #define IMX8MM_GPR_PCIE_SSC_EN BIT(16)
> > #define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9)
> >
> > +enum imx8_pcie_phy_type {
> > + IMX8MM,
> > + IMX8MP,
> > +};
> > +
> > +struct imx8_pcie_phy_drvdata {
> > + enum imx8_pcie_phy_type variant;
> > + const char *gpr;
> > +};
> > +
> > struct imx8_pcie_phy {
> > void __iomem *base;
> > struct clk *clk;
> > struct phy *phy;
> > struct regmap *iomuxc_gpr;
> > struct reset_control *reset;
> > + struct reset_control *perst;
> > u32 refclk_pad_mode;
> > u32 tx_deemph_gen1;
> > u32 tx_deemph_gen2;
> > bool clkreq_unused;
> > + const struct imx8_pcie_phy_drvdata *drvdata;
> > };
> >
> > static int imx8_pcie_phy_init(struct phy *phy) @@ -68,31 +81,20 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> > reset_control_assert(imx8_phy->reset);
> >
> > pad_mode = imx8_phy->refclk_pad_mode;
> > - /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > - imx8_phy->clkreq_unused ?
> > - 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_AUX_EN,
> > - IMX8MM_GPR_PCIE_AUX_EN);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_SSC_EN, 0);
> > -
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > - pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > - IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > - IMX8MM_GPR_PCIE_REF_CLK_PLL);
> > - usleep_range(100, 200);
> > -
> > - /* Do the PHY common block reset */
> > - regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > - IMX8MM_GPR_PCIE_CMN_RST,
> > - IMX8MM_GPR_PCIE_CMN_RST);
> > - usleep_range(200, 500);
> > + switch (imx8_phy->drvdata->variant) {
> > + case IMX8MM:
> > + /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > + if (imx8_phy->tx_deemph_gen1)
> > + writel(imx8_phy->tx_deemph_gen1,
> > + imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > + if (imx8_phy->tx_deemph_gen2)
> > + writel(imx8_phy->tx_deemph_gen2,
> > + imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > + break;
> > + case IMX8MP:
> > + reset_control_assert(imx8_phy->perst);
> > + break;
> > + }
> >
> > if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
> > pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) { @@ -120,20
> +122,44 @@
> > static int imx8_pcie_phy_init(struct phy *phy)
> > imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
> > }
> >
> > - /* Tune PHY de-emphasis setting to pass PCIe compliance. */
> > - if (imx8_phy->tx_deemph_gen1)
> > - writel(imx8_phy->tx_deemph_gen1,
> > - imx8_phy->base + PCIE_PHY_TRSV_REG5);
> > - if (imx8_phy->tx_deemph_gen2)
> > - writel(imx8_phy->tx_deemph_gen2,
> > - imx8_phy->base + PCIE_PHY_TRSV_REG6);
> > + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
> > + imx8_phy->clkreq_unused ?
> > + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_AUX_EN,
> > + IMX8MM_GPR_PCIE_AUX_EN);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_POWER_OFF, 0);
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_SSC_EN, 0);
> > +
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_REF_CLK_SEL,
> > + pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
> > + IMX8MM_GPR_PCIE_REF_CLK_EXT :
> > + IMX8MM_GPR_PCIE_REF_CLK_PLL);
>
> Lets do code reorg in a separate patch and then add support for new SOC, that
> is more reviewable that this big pile of changes
Okay, would spilt them into two patches.
Thanks.
Richard Zhu
Best Regards
>
> > + usleep_range(100, 200);
> >
> > - reset_control_deassert(imx8_phy->reset);
> > + /* Do the PHY common block reset */
> > + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
> > + IMX8MM_GPR_PCIE_CMN_RST,
> > + IMX8MM_GPR_PCIE_CMN_RST);
> > +
> > + switch (imx8_phy->drvdata->variant) {
> > + case IMX8MP:
> > + reset_control_deassert(imx8_phy->perst);
> > + fallthrough;
> > + case IMX8MM:
> > + reset_control_deassert(imx8_phy->reset);
> > + usleep_range(200, 500);
> > + break;
> > + }
> >
> > /* Polling to check the phy is ready or not. */
> > - ret = readl_poll_timeout(imx8_phy->base +
> IMX8MM_PCIE_PHY_CMN_REG75,
> > - val, val == PCIE_PHY_CMN_REG75_PLL_DONE,
> > - 10, 20000);
> > + ret = readl_poll_timeout(imx8_phy->base +
> IMX8MM_PCIE_PHY_CMN_REG075,
> > + val, val == ANA_PLL_DONE, 10, 20000);
> > return ret;
> > }
> >
> > @@ -160,6 +186,25 @@ static const struct phy_ops imx8_pcie_phy_ops = {
> > .owner = THIS_MODULE,
> > };
> >
> > +static const struct imx8_pcie_phy_drvdata drvdata[] = {
> > + [IMX8MM] = {
> > + .variant = IMX8MM,
> > + .gpr = "fsl,imx8mm-iomuxc-gpr",
> > + },
> > +
> > + [IMX8MP] = {
> > + .variant = IMX8MP,
> > + .gpr = "fsl,imx8mp-iomuxc-gpr",
> > + },
> > +};
> > +
> > +static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > + {.compatible = "fsl,imx8mm-pcie-phy", .data = &drvdata[IMX8MM], },
> > + {.compatible = "fsl,imx8mp-pcie-phy", .data = &drvdata[IMX8MP], },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > +
> > static int imx8_pcie_phy_probe(struct platform_device *pdev) {
> > struct phy_provider *phy_provider;
> > @@ -172,6 +217,8 @@ static int imx8_pcie_phy_probe(struct
> platform_device *pdev)
> > if (!imx8_phy)
> > return -ENOMEM;
> >
> > + imx8_phy->drvdata = of_device_get_match_data(dev);
> > +
> > /* get PHY refclk pad mode */
> > of_property_read_u32(np, "fsl,refclk-pad-mode",
> > &imx8_phy->refclk_pad_mode);
> > @@ -197,7 +244,7 @@ static int imx8_pcie_phy_probe(struct
> > platform_device *pdev)
> >
> > /* Grab GPR config register range */
> > imx8_phy->iomuxc_gpr =
> > - syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
> > + syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
> > if (IS_ERR(imx8_phy->iomuxc_gpr)) {
> > dev_err(dev, "unable to find iomuxc registers\n");
> > return PTR_ERR(imx8_phy->iomuxc_gpr); @@ -209,6 +256,15 @@
> static
> > int imx8_pcie_phy_probe(struct platform_device *pdev)
> > return PTR_ERR(imx8_phy->reset);
> > }
> >
> > + if (imx8_phy->drvdata->variant == IMX8MP) {
> > + imx8_phy->perst =
> > + devm_reset_control_get_exclusive(dev, "perst");
> > + if (IS_ERR(imx8_phy->perst)) {
> > + dev_err(dev, "Failed to get PCIE PHY PERST control\n");
> > + return PTR_ERR(imx8_phy->perst);
> > + }
> > + }
> > +
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > imx8_phy->base = devm_ioremap_resource(dev, res);
> > if (IS_ERR(imx8_phy->base))
> > @@ -225,12 +281,6 @@ static int imx8_pcie_phy_probe(struct
> platform_device *pdev)
> > return PTR_ERR_OR_ZERO(phy_provider); }
> >
> > -static const struct of_device_id imx8_pcie_phy_of_match[] = {
> > - {.compatible = "fsl,imx8mm-pcie-phy",},
> > - { },
> > -};
> > -MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
> > -
> > static struct platform_driver imx8_pcie_phy_driver = {
> > .probe = imx8_pcie_phy_probe,
> > .driver = {
> > --
> > 2.25.1
>
> --
> ~Vinod
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2022-09-26 5:12 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-20 7:38 [PATCH v8 0/2] Add the iMX8MP PCIe support Richard Zhu
2022-09-20 7:38 ` Richard Zhu
2022-09-20 7:38 ` Richard Zhu
2022-09-20 7:38 ` [PATCH v8 1/2] dt-binding: phy: Add iMX8MP PCIe PHY binding Richard Zhu
2022-09-20 7:38 ` Richard Zhu
2022-09-20 7:38 ` Richard Zhu
2022-09-20 7:38 ` [PATCH v8 2/2] phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support Richard Zhu
2022-09-20 7:38 ` Richard Zhu
2022-09-20 7:38 ` Richard Zhu
2022-09-24 7:32 ` Vinod Koul
2022-09-24 7:32 ` Vinod Koul
2022-09-24 7:32 ` Vinod Koul
2022-09-26 5:11 ` Hongxing Zhu
2022-09-26 5:11 ` Hongxing Zhu
2022-09-26 5:11 ` Hongxing Zhu
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.