* [Intel-gfx] [PATCH 00/12] Explicit MCR handling and MTL steering
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Steering of multicast/replicated registers becomes a bit more
complicated on Meteor Lake. Whereas previously the control register we
used to manage the steering was only used by our driver[*], software's
control of steering has now been consolidated with the controls for
various other hardware/firmware agents into a single register. We can
no longer utilize pre-programmed implicit steering since other firmware
agents may change the steering target and not restore it afterward;
we'll need to explicitly steer all types of MCR registers (including the
GSLICE/COMPUTE/DSS ranges that have been handled implicitly in the
past). Furthermore, since multiple agents will now be sharing a single
steering control register, races are possible. To address this, the
hardware adds a new MCR semaphore register which is supposed to be used
to temporarily lock the steering while performing MCR operations.
It's going to become important for us to handle accesses of multicast
registers very explicitly going forward. This series provides some prep
work for that by updating our register definitions to clearly define
registers as either MCR or non-MCR and ensure that we're using the
intel_gt_mcr_*() functions rather than intel_uncore_*() when operating
on MCR registers. By declaring MCR registers as a new C type (i.e., not
an i915_reg_t) we can have the compiler help us find any mistakes where
non-MCR functions are used on MCR registers and vice-versa.
This series also includes the general MCR steering tables and logic, but
does not yet introduce the support for the semaphore register that will
be used to coordinate steering updates with other agents; we'll provide
that support in a separate series once this preparation work has landed.
[*] This is a bit of an oversimplification; there are some hardware and
software debug tools that use the same MCR_SELECTOR register that i915
does and which could potentially re-steer MCR accesses behind our back.
E.g., simply using IGT's "intel_reg" tool to write the MCR_SELECTOR
register at the wrong time could interfere with driver operation. But
given that these debug facilities require root privileges to run and are
only used by people intentionally debugging the driver or hardware, we
can ignore such races for real-world usage.
Matt Roper (12):
drm/i915/gen8: Create separate reg definitions for new MCR registers
drm/i915/xehp: Create separate reg definitions for new MCR registers
drm/i915/gt: Drop a few unused register definitions
drm/i915/gt: Correct prefix on a few registers
drm/i915/xehp: Check for faults on primary GAM
drm/i915: Define MCR registers explicitly
drm/i915/gt: Always use MCR functions on multicast registers
drm/i915/guc: Handle save/restore of MCR registers explicitly
drm/i915/gt: Add MCR-specific workaround initializers
drm/i915: Define multicast registers as a new type
drm/i915/mtl: Add multicast steering for render GT
drm/i915/mtl: Add multicast steering for media GT
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 40 +-
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 149 ++++--
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 14 +-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 157 +++---
drivers/gpu/drm/i915/gt/intel_gt_types.h | 9 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 44 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 12 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 470 +++++++++++-------
.../gpu/drm/i915/gt/intel_workarounds_types.h | 9 +-
.../gpu/drm/i915/gt/selftest_workarounds.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 60 ++-
.../gpu/drm/i915/gt/uc/intel_guc_capture.c | 8 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 12 +-
drivers/gpu/drm/i915/gvt/handlers.c | 19 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 16 +-
drivers/gpu/drm/i915/i915_pci.c | 1 +
drivers/gpu/drm/i915/i915_reg_defs.h | 22 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 12 +-
drivers/gpu/drm/i915/intel_pm.c | 20 +-
22 files changed, 700 insertions(+), 386 deletions(-)
--
2.37.3
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 01/12] drm/i915/gen8: Create separate reg definitions for new MCR registers
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Gen8 was the first time our hardware had multicast registers (or at
least the first time the multicast nature was exposed and MMIO accesses
could be steered). There are some registers that transitioned from
singleton behavior to multicast during the gen7 -> gen8 transition;
let's duplicate the register definitions for those registers in
preparation for upcoming patches that will handle MCR registers in a
special manner.
The registers adjusted are:
* MISCCPCTL
* SAMPLER_INSTDONE
* ROW_INSTDONE
* ROW_CHICKEN2
* HALF_SLICE_CHICKEN1
* HALF_SLICE_CHICKEN3
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 11 +++++++++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 +++++++++----------
.../gpu/drm/i915/gt/uc/intel_guc_capture.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 10 ++++-----
9 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2ddcad497fa3..c408bac3c533 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1559,11 +1559,11 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
for_each_ss_steering(iter, engine->gt, slice, subslice) {
instdone->sampler[slice][subslice] =
intel_gt_mcr_read(engine->gt,
- GEN7_SAMPLER_INSTDONE,
+ GEN8_SAMPLER_INSTDONE,
slice, subslice);
instdone->row[slice][subslice] =
intel_gt_mcr_read(engine->gt,
- GEN7_ROW_INSTDONE,
+ GEN8_ROW_INSTDONE,
slice, subslice);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 1cbb7226400b..e5a1ea255640 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -647,6 +647,9 @@
#define GEN7_MISCCPCTL _MMIO(0x9424)
#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
+
+#define GEN8_MISCCPCTL _MMIO(0x9424)
+#define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
@@ -1068,18 +1071,22 @@
#define GEN12_GAM_DONE _MMIO(0xcf68)
#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
+#define GEN8_HALF_SLICE_CHICKEN1 _MMIO(0xe100)
#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
+#define GEN8_SAMPLER_INSTDONE _MMIO(0xe160)
#define GEN7_ROW_INSTDONE _MMIO(0xe164)
+#define GEN8_ROW_INSTDONE _MMIO(0xe164)
#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
#define GEN8_ST_PO_DISABLE (1 << 13)
-#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
+#define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
+#define GEN8_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
@@ -1132,6 +1139,8 @@
#define DISABLE_EARLY_EOT REG_BIT(1)
#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
+
+#define GEN8_ROW_CHICKEN2 _MMIO(0xe4f4)
#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6d2003d598e6..e382cb4c6971 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -295,10 +295,10 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
* Also see the related UCGTCL1 write in bdw_init_clock_gating()
* to disable EUTC clock gating.
*/
- wa_masked_en(wal, GEN7_ROW_CHICKEN2,
+ wa_masked_en(wal, GEN8_ROW_CHICKEN2,
DOP_CLOCK_GATING_DISABLE);
- wa_masked_en(wal, HALF_SLICE_CHICKEN3,
+ wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
wa_masked_en(wal, HDC_CHICKEN0,
@@ -386,7 +386,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
IS_KABYLAKE(i915) ||
IS_COFFEELAKE(i915) ||
IS_COMETLAKE(i915))
- wa_masked_en(wal, HALF_SLICE_CHICKEN3,
+ wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
@@ -490,7 +490,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaDisableSbeCacheDispatchPortSharing:kbl */
- wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
+ wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
@@ -514,7 +514,7 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaDisableSbeCacheDispatchPortSharing:cfl */
- wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
+ wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
@@ -2107,7 +2107,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14013392000:dg2_g11 */
- wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
+ wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
/* Wa_16011620976:dg2_g11 */
wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
@@ -2156,7 +2156,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
DISABLE_128B_EVICTION_COMMAND_UDW);
/* Wa_22012856258:dg2 */
- wa_masked_en(wal, GEN7_ROW_CHICKEN2,
+ wa_masked_en(wal, GEN8_ROW_CHICKEN2,
GEN12_DISABLE_READ_SUPPRESSION);
/*
@@ -2253,7 +2253,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
- wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+ wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
/*
* Wa_1407928979:tgl A*
@@ -2282,7 +2282,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
- wa_masked_en(wal, GEN7_ROW_CHICKEN2,
+ wa_masked_en(wal, GEN8_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
/*
@@ -2449,7 +2449,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_HASWELL(i915)) {
/* WaSampleCChickenBitEnable:hsw */
wa_masked_en(wal,
- HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
+ HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
wa_masked_dis(wal,
CACHE_MODE_0_GEN7,
@@ -2747,7 +2747,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
/* Wa_14010449647:xehpsdv */
- wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
+ wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
/* Wa_18011725039:xehpsdv */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 8f1165146013..9495a7928bc8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -244,8 +244,8 @@ struct __ext_steer_reg {
};
static const struct __ext_steer_reg xe_extregs[] = {
- {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE},
- {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE}
+ {"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE},
+ {"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE}
};
static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index a0372735cddb..9229243992c2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -35,7 +35,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
if (GRAPHICS_VER(uncore->i915) == 9) {
/* DOP Clock Gating Enable for GuC clocks */
- intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
+ intel_uncore_rmw(uncore, GEN8_MISCCPCTL,
0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
/* allows for 5us (in 10ns units) before GT can go to RC6 */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index daac2050d77d..700cc9688f47 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2257,7 +2257,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
/* display */
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 1c6e941c9666..ac58460fb305 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -111,7 +111,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
{RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
{RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
- {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
+ {RCS0, HSW_HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
{RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
{RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
{RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 8279dc580a3e..638b77d64bf4 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -102,7 +102,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x2438));
MMIO_D(_MMIO(0x243c));
MMIO_D(_MMIO(0x7018));
- MMIO_D(HALF_SLICE_CHICKEN3);
+ MMIO_D(HSW_HALF_SLICE_CHICKEN3);
MMIO_D(GEN7_HALF_SLICE_CHICKEN1);
/* display */
MMIO_F(_MMIO(0x60220), 0x20);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8f86f56e7ca4..1aa77b18fd3c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4325,8 +4325,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
u32 val;
/* WaTempDisableDOPClkGating:bdw */
- misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
- intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+ misccpctl = intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL);
+ intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);
val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
val &= ~L3_PRIO_CREDITS_MASK;
@@ -4340,7 +4340,7 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
*/
intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
udelay(1);
- intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
+ intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl);
}
static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -4500,8 +4500,8 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
gen9_init_clock_gating(dev_priv);
/* WaDisableDopClockGating:skl */
- intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
- ~GEN7_DOP_CLOCK_GATE_ENABLE);
+ intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL) &
+ ~GEN8_DOP_CLOCK_GATE_ENABLE);
/* WAC6entrylatency:skl */
intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH 01/12] drm/i915/gen8: Create separate reg definitions for new MCR registers
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Gen8 was the first time our hardware had multicast registers (or at
least the first time the multicast nature was exposed and MMIO accesses
could be steered). There are some registers that transitioned from
singleton behavior to multicast during the gen7 -> gen8 transition;
let's duplicate the register definitions for those registers in
preparation for upcoming patches that will handle MCR registers in a
special manner.
The registers adjusted are:
* MISCCPCTL
* SAMPLER_INSTDONE
* ROW_INSTDONE
* ROW_CHICKEN2
* HALF_SLICE_CHICKEN1
* HALF_SLICE_CHICKEN3
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 11 +++++++++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 +++++++++----------
.../gpu/drm/i915/gt/uc/intel_guc_capture.c | 4 ++--
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 10 ++++-----
9 files changed, 34 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 2ddcad497fa3..c408bac3c533 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1559,11 +1559,11 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
for_each_ss_steering(iter, engine->gt, slice, subslice) {
instdone->sampler[slice][subslice] =
intel_gt_mcr_read(engine->gt,
- GEN7_SAMPLER_INSTDONE,
+ GEN8_SAMPLER_INSTDONE,
slice, subslice);
instdone->row[slice][subslice] =
intel_gt_mcr_read(engine->gt,
- GEN7_ROW_INSTDONE,
+ GEN8_ROW_INSTDONE,
slice, subslice);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 1cbb7226400b..e5a1ea255640 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -647,6 +647,9 @@
#define GEN7_MISCCPCTL _MMIO(0x9424)
#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
+
+#define GEN8_MISCCPCTL _MMIO(0x9424)
+#define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
#define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
@@ -1068,18 +1071,22 @@
#define GEN12_GAM_DONE _MMIO(0xcf68)
#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
+#define GEN8_HALF_SLICE_CHICKEN1 _MMIO(0xe100)
#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
+#define GEN8_SAMPLER_INSTDONE _MMIO(0xe160)
#define GEN7_ROW_INSTDONE _MMIO(0xe164)
+#define GEN8_ROW_INSTDONE _MMIO(0xe164)
#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
#define GEN8_ST_PO_DISABLE (1 << 13)
-#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
+#define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
+#define GEN8_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
@@ -1132,6 +1139,8 @@
#define DISABLE_EARLY_EOT REG_BIT(1)
#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
+
+#define GEN8_ROW_CHICKEN2 _MMIO(0xe4f4)
#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 6d2003d598e6..e382cb4c6971 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -295,10 +295,10 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
* Also see the related UCGTCL1 write in bdw_init_clock_gating()
* to disable EUTC clock gating.
*/
- wa_masked_en(wal, GEN7_ROW_CHICKEN2,
+ wa_masked_en(wal, GEN8_ROW_CHICKEN2,
DOP_CLOCK_GATING_DISABLE);
- wa_masked_en(wal, HALF_SLICE_CHICKEN3,
+ wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
wa_masked_en(wal, HDC_CHICKEN0,
@@ -386,7 +386,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
IS_KABYLAKE(i915) ||
IS_COFFEELAKE(i915) ||
IS_COMETLAKE(i915))
- wa_masked_en(wal, HALF_SLICE_CHICKEN3,
+ wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
@@ -490,7 +490,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaDisableSbeCacheDispatchPortSharing:kbl */
- wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
+ wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
@@ -514,7 +514,7 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaDisableSbeCacheDispatchPortSharing:cfl */
- wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
+ wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
@@ -2107,7 +2107,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14013392000:dg2_g11 */
- wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
+ wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
/* Wa_16011620976:dg2_g11 */
wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
@@ -2156,7 +2156,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
DISABLE_128B_EVICTION_COMMAND_UDW);
/* Wa_22012856258:dg2 */
- wa_masked_en(wal, GEN7_ROW_CHICKEN2,
+ wa_masked_en(wal, GEN8_ROW_CHICKEN2,
GEN12_DISABLE_READ_SUPPRESSION);
/*
@@ -2253,7 +2253,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
- wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+ wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
/*
* Wa_1407928979:tgl A*
@@ -2282,7 +2282,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
- wa_masked_en(wal, GEN7_ROW_CHICKEN2,
+ wa_masked_en(wal, GEN8_ROW_CHICKEN2,
GEN12_PUSH_CONST_DEREF_HOLD_DIS);
/*
@@ -2449,7 +2449,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_HASWELL(i915)) {
/* WaSampleCChickenBitEnable:hsw */
wa_masked_en(wal,
- HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
+ HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
wa_masked_dis(wal,
CACHE_MODE_0_GEN7,
@@ -2747,7 +2747,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
/* Wa_14010449647:xehpsdv */
- wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
+ wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
/* Wa_18011725039:xehpsdv */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 8f1165146013..9495a7928bc8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -244,8 +244,8 @@ struct __ext_steer_reg {
};
static const struct __ext_steer_reg xe_extregs[] = {
- {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE},
- {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE}
+ {"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE},
+ {"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE}
};
static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index a0372735cddb..9229243992c2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -35,7 +35,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
if (GRAPHICS_VER(uncore->i915) == 9) {
/* DOP Clock Gating Enable for GuC clocks */
- intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
+ intel_uncore_rmw(uncore, GEN8_MISCCPCTL,
0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
/* allows for 5us (in 10ns units) before GT can go to RC6 */
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index daac2050d77d..700cc9688f47 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2257,7 +2257,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
/* display */
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index 1c6e941c9666..ac58460fb305 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -111,7 +111,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
{RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
{RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
- {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
+ {RCS0, HSW_HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
{RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
{RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
{RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 8279dc580a3e..638b77d64bf4 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -102,7 +102,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x2438));
MMIO_D(_MMIO(0x243c));
MMIO_D(_MMIO(0x7018));
- MMIO_D(HALF_SLICE_CHICKEN3);
+ MMIO_D(HSW_HALF_SLICE_CHICKEN3);
MMIO_D(GEN7_HALF_SLICE_CHICKEN1);
/* display */
MMIO_F(_MMIO(0x60220), 0x20);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8f86f56e7ca4..1aa77b18fd3c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4325,8 +4325,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
u32 val;
/* WaTempDisableDOPClkGating:bdw */
- misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
- intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+ misccpctl = intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL);
+ intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);
val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
val &= ~L3_PRIO_CREDITS_MASK;
@@ -4340,7 +4340,7 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
*/
intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
udelay(1);
- intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
+ intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl);
}
static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -4500,8 +4500,8 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
gen9_init_clock_gating(dev_priv);
/* WaDisableDopClockGating:skl */
- intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
- ~GEN7_DOP_CLOCK_GATE_ENABLE);
+ intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL) &
+ ~GEN8_DOP_CLOCK_GATE_ENABLE);
/* WAC6entrylatency:skl */
intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH 01/12] drm/i915/gen8: Create separate reg definitions for new MCR registers
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-26 6:15 ` Balasubramani Vivekanandan
-1 siblings, 0 replies; 40+ messages in thread
From: Balasubramani Vivekanandan @ 2022-09-26 6:15 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 19.09.2022 15:32, Matt Roper wrote:
> Gen8 was the first time our hardware had multicast registers (or at
> least the first time the multicast nature was exposed and MMIO accesses
> could be steered). There are some registers that transitioned from
> singleton behavior to multicast during the gen7 -> gen8 transition;
> let's duplicate the register definitions for those registers in
> preparation for upcoming patches that will handle MCR registers in a
> special manner.
>
> The registers adjusted are:
> * MISCCPCTL
> * SAMPLER_INSTDONE
> * ROW_INSTDONE
> * ROW_CHICKEN2
> * HALF_SLICE_CHICKEN1
> * HALF_SLICE_CHICKEN3
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 11 +++++++++-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 +++++++++----------
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 4 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++-----
> 9 files changed, 34 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 2ddcad497fa3..c408bac3c533 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1559,11 +1559,11 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> for_each_ss_steering(iter, engine->gt, slice, subslice) {
> instdone->sampler[slice][subslice] =
> intel_gt_mcr_read(engine->gt,
> - GEN7_SAMPLER_INSTDONE,
> + GEN8_SAMPLER_INSTDONE,
> slice, subslice);
> instdone->row[slice][subslice] =
> intel_gt_mcr_read(engine->gt,
> - GEN7_ROW_INSTDONE,
> + GEN8_ROW_INSTDONE,
> slice, subslice);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 1cbb7226400b..e5a1ea255640 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -647,6 +647,9 @@
>
> #define GEN7_MISCCPCTL _MMIO(0x9424)
> #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
> +
> +#define GEN8_MISCCPCTL _MMIO(0x9424)
> +#define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
> #define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
> #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
> #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
> @@ -1068,18 +1071,22 @@
> #define GEN12_GAM_DONE _MMIO(0xcf68)
>
> #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
> +#define GEN8_HALF_SLICE_CHICKEN1 _MMIO(0xe100)
> #define GEN7_MAX_PS_THREAD_DEP (8 << 12)
> #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
> #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
> #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
>
> #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
> +#define GEN8_SAMPLER_INSTDONE _MMIO(0xe160)
> #define GEN7_ROW_INSTDONE _MMIO(0xe164)
> +#define GEN8_ROW_INSTDONE _MMIO(0xe164)
>
> #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
> #define GEN8_ST_PO_DISABLE (1 << 13)
>
> -#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> +#define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> +#define GEN8_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> #define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
> #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
> #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
> @@ -1132,6 +1139,8 @@
> #define DISABLE_EARLY_EOT REG_BIT(1)
>
> #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
> +
> +#define GEN8_ROW_CHICKEN2 _MMIO(0xe4f4)
> #define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
> #define GEN12_DISABLE_EARLY_READ REG_BIT(14)
> #define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 6d2003d598e6..e382cb4c6971 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -295,10 +295,10 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
> * Also see the related UCGTCL1 write in bdw_init_clock_gating()
> * to disable EUTC clock gating.
> */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> DOP_CLOCK_GATING_DISABLE);
>
> - wa_masked_en(wal, HALF_SLICE_CHICKEN3,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> wa_masked_en(wal, HDC_CHICKEN0,
> @@ -386,7 +386,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
> IS_KABYLAKE(i915) ||
> IS_COFFEELAKE(i915) ||
> IS_COMETLAKE(i915))
> - wa_masked_en(wal, HALF_SLICE_CHICKEN3,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
> @@ -490,7 +490,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
>
> /* WaDisableSbeCacheDispatchPortSharing:kbl */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> }
>
> @@ -514,7 +514,7 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
>
> /* WaDisableSbeCacheDispatchPortSharing:cfl */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> }
>
> @@ -2107,7 +2107,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> /* Wa_14013392000:dg2_g11 */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
>
> /* Wa_16011620976:dg2_g11 */
> wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
> @@ -2156,7 +2156,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> DISABLE_128B_EVICTION_COMMAND_UDW);
>
> /* Wa_22012856258:dg2 */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> GEN12_DISABLE_READ_SUPPRESSION);
>
> /*
> @@ -2253,7 +2253,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
>
> /*
> * Wa_1407928979:tgl A*
> @@ -2282,7 +2282,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> GEN12_PUSH_CONST_DEREF_HOLD_DIS);
>
> /*
> @@ -2449,7 +2449,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> if (IS_HASWELL(i915)) {
> /* WaSampleCChickenBitEnable:hsw */
> wa_masked_en(wal,
> - HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
> + HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
>
> wa_masked_dis(wal,
> CACHE_MODE_0_GEN7,
> @@ -2747,7 +2747,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
>
> /* Wa_14010449647:xehpsdv */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
>
> /* Wa_18011725039:xehpsdv */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index 8f1165146013..9495a7928bc8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -244,8 +244,8 @@ struct __ext_steer_reg {
> };
>
> static const struct __ext_steer_reg xe_extregs[] = {
> - {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE},
> - {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE}
> + {"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE},
> + {"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE}
> };
>
> static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index a0372735cddb..9229243992c2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -35,7 +35,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
>
> if (GRAPHICS_VER(uncore->i915) == 9) {
> /* DOP Clock Gating Enable for GuC clocks */
> - intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
> + intel_uncore_rmw(uncore, GEN8_MISCCPCTL,
> 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
>
> /* allows for 5us (in 10ns units) before GT can go to RC6 */
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index daac2050d77d..700cc9688f47 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2257,7 +2257,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>
> /* display */
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index 1c6e941c9666..ac58460fb305 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -111,7 +111,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
> {RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
> {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
> {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
> - {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
> + {RCS0, HSW_HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
Since it is for Gen9 and above, can we use GEN8_HALF_SLICE_CHICKEN3
register name here?
Rest looks good.
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Regards,
Bala
> {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
> {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
> {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 8279dc580a3e..638b77d64bf4 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -102,7 +102,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
> MMIO_D(_MMIO(0x2438));
> MMIO_D(_MMIO(0x243c));
> MMIO_D(_MMIO(0x7018));
> - MMIO_D(HALF_SLICE_CHICKEN3);
> + MMIO_D(HSW_HALF_SLICE_CHICKEN3);
> MMIO_D(GEN7_HALF_SLICE_CHICKEN1);
> /* display */
> MMIO_F(_MMIO(0x60220), 0x20);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8f86f56e7ca4..1aa77b18fd3c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4325,8 +4325,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> u32 val;
>
> /* WaTempDisableDOPClkGating:bdw */
> - misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> + misccpctl = intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);
>
> val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
> val &= ~L3_PRIO_CREDITS_MASK;
> @@ -4340,7 +4340,7 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> */
> intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
> udelay(1);
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl);
> }
>
> static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -4500,8 +4500,8 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
> gen9_init_clock_gating(dev_priv);
>
> /* WaDisableDopClockGating:skl */
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
> - ~GEN7_DOP_CLOCK_GATE_ENABLE);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL) &
> + ~GEN8_DOP_CLOCK_GATE_ENABLE);
>
> /* WAC6entrylatency:skl */
> intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
> --
> 2.37.3
>
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 01/12] drm/i915/gen8: Create separate reg definitions for new MCR registers
@ 2022-09-26 6:15 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 40+ messages in thread
From: Balasubramani Vivekanandan @ 2022-09-26 6:15 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 19.09.2022 15:32, Matt Roper wrote:
> Gen8 was the first time our hardware had multicast registers (or at
> least the first time the multicast nature was exposed and MMIO accesses
> could be steered). There are some registers that transitioned from
> singleton behavior to multicast during the gen7 -> gen8 transition;
> let's duplicate the register definitions for those registers in
> preparation for upcoming patches that will handle MCR registers in a
> special manner.
>
> The registers adjusted are:
> * MISCCPCTL
> * SAMPLER_INSTDONE
> * ROW_INSTDONE
> * ROW_CHICKEN2
> * HALF_SLICE_CHICKEN1
> * HALF_SLICE_CHICKEN3
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 11 +++++++++-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 +++++++++----------
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 4 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++-----
> 9 files changed, 34 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 2ddcad497fa3..c408bac3c533 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1559,11 +1559,11 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> for_each_ss_steering(iter, engine->gt, slice, subslice) {
> instdone->sampler[slice][subslice] =
> intel_gt_mcr_read(engine->gt,
> - GEN7_SAMPLER_INSTDONE,
> + GEN8_SAMPLER_INSTDONE,
> slice, subslice);
> instdone->row[slice][subslice] =
> intel_gt_mcr_read(engine->gt,
> - GEN7_ROW_INSTDONE,
> + GEN8_ROW_INSTDONE,
> slice, subslice);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 1cbb7226400b..e5a1ea255640 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -647,6 +647,9 @@
>
> #define GEN7_MISCCPCTL _MMIO(0x9424)
> #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
> +
> +#define GEN8_MISCCPCTL _MMIO(0x9424)
> +#define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
> #define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
> #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
> #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
> @@ -1068,18 +1071,22 @@
> #define GEN12_GAM_DONE _MMIO(0xcf68)
>
> #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
> +#define GEN8_HALF_SLICE_CHICKEN1 _MMIO(0xe100)
> #define GEN7_MAX_PS_THREAD_DEP (8 << 12)
> #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
> #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
> #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
>
> #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
> +#define GEN8_SAMPLER_INSTDONE _MMIO(0xe160)
> #define GEN7_ROW_INSTDONE _MMIO(0xe164)
> +#define GEN8_ROW_INSTDONE _MMIO(0xe164)
>
> #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
> #define GEN8_ST_PO_DISABLE (1 << 13)
>
> -#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> +#define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> +#define GEN8_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> #define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
> #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
> #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
> @@ -1132,6 +1139,8 @@
> #define DISABLE_EARLY_EOT REG_BIT(1)
>
> #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
> +
> +#define GEN8_ROW_CHICKEN2 _MMIO(0xe4f4)
> #define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
> #define GEN12_DISABLE_EARLY_READ REG_BIT(14)
> #define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 6d2003d598e6..e382cb4c6971 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -295,10 +295,10 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
> * Also see the related UCGTCL1 write in bdw_init_clock_gating()
> * to disable EUTC clock gating.
> */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> DOP_CLOCK_GATING_DISABLE);
>
> - wa_masked_en(wal, HALF_SLICE_CHICKEN3,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> wa_masked_en(wal, HDC_CHICKEN0,
> @@ -386,7 +386,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
> IS_KABYLAKE(i915) ||
> IS_COFFEELAKE(i915) ||
> IS_COMETLAKE(i915))
> - wa_masked_en(wal, HALF_SLICE_CHICKEN3,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
> @@ -490,7 +490,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
>
> /* WaDisableSbeCacheDispatchPortSharing:kbl */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> }
>
> @@ -514,7 +514,7 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
>
> /* WaDisableSbeCacheDispatchPortSharing:cfl */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> }
>
> @@ -2107,7 +2107,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> /* Wa_14013392000:dg2_g11 */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
>
> /* Wa_16011620976:dg2_g11 */
> wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
> @@ -2156,7 +2156,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> DISABLE_128B_EVICTION_COMMAND_UDW);
>
> /* Wa_22012856258:dg2 */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> GEN12_DISABLE_READ_SUPPRESSION);
>
> /*
> @@ -2253,7 +2253,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
>
> /*
> * Wa_1407928979:tgl A*
> @@ -2282,7 +2282,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> GEN12_PUSH_CONST_DEREF_HOLD_DIS);
>
> /*
> @@ -2449,7 +2449,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> if (IS_HASWELL(i915)) {
> /* WaSampleCChickenBitEnable:hsw */
> wa_masked_en(wal,
> - HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
> + HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
>
> wa_masked_dis(wal,
> CACHE_MODE_0_GEN7,
> @@ -2747,7 +2747,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
>
> /* Wa_14010449647:xehpsdv */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
>
> /* Wa_18011725039:xehpsdv */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index 8f1165146013..9495a7928bc8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -244,8 +244,8 @@ struct __ext_steer_reg {
> };
>
> static const struct __ext_steer_reg xe_extregs[] = {
> - {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE},
> - {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE}
> + {"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE},
> + {"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE}
> };
>
> static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index a0372735cddb..9229243992c2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -35,7 +35,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
>
> if (GRAPHICS_VER(uncore->i915) == 9) {
> /* DOP Clock Gating Enable for GuC clocks */
> - intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
> + intel_uncore_rmw(uncore, GEN8_MISCCPCTL,
> 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
>
> /* allows for 5us (in 10ns units) before GT can go to RC6 */
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index daac2050d77d..700cc9688f47 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2257,7 +2257,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>
> /* display */
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index 1c6e941c9666..ac58460fb305 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -111,7 +111,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
> {RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
> {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
> {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
> - {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
> + {RCS0, HSW_HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
Since it is for Gen9 and above, can we use GEN8_HALF_SLICE_CHICKEN3
register name here?
Rest looks good.
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Regards,
Bala
> {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
> {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
> {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 8279dc580a3e..638b77d64bf4 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -102,7 +102,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
> MMIO_D(_MMIO(0x2438));
> MMIO_D(_MMIO(0x243c));
> MMIO_D(_MMIO(0x7018));
> - MMIO_D(HALF_SLICE_CHICKEN3);
> + MMIO_D(HSW_HALF_SLICE_CHICKEN3);
> MMIO_D(GEN7_HALF_SLICE_CHICKEN1);
> /* display */
> MMIO_F(_MMIO(0x60220), 0x20);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8f86f56e7ca4..1aa77b18fd3c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4325,8 +4325,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> u32 val;
>
> /* WaTempDisableDOPClkGating:bdw */
> - misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> + misccpctl = intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);
>
> val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
> val &= ~L3_PRIO_CREDITS_MASK;
> @@ -4340,7 +4340,7 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> */
> intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
> udelay(1);
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl);
> }
>
> static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -4500,8 +4500,8 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
> gen9_init_clock_gating(dev_priv);
>
> /* WaDisableDopClockGating:skl */
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
> - ~GEN7_DOP_CLOCK_GATE_ENABLE);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL) &
> + ~GEN8_DOP_CLOCK_GATE_ENABLE);
>
> /* WAC6entrylatency:skl */
> intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
> --
> 2.37.3
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH 01/12] drm/i915/gen8: Create separate reg definitions for new MCR registers
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-28 8:25 ` Balasubramani Vivekanandan
-1 siblings, 0 replies; 40+ messages in thread
From: Balasubramani Vivekanandan @ 2022-09-28 8:25 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 19.09.2022 15:32, Matt Roper wrote:
> Gen8 was the first time our hardware had multicast registers (or at
> least the first time the multicast nature was exposed and MMIO accesses
> could be steered). There are some registers that transitioned from
> singleton behavior to multicast during the gen7 -> gen8 transition;
> let's duplicate the register definitions for those registers in
> preparation for upcoming patches that will handle MCR registers in a
> special manner.
>
> The registers adjusted are:
> * MISCCPCTL
> * SAMPLER_INSTDONE
> * ROW_INSTDONE
> * ROW_CHICKEN2
> * HALF_SLICE_CHICKEN1
> * HALF_SLICE_CHICKEN3
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 11 +++++++++-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 +++++++++----------
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 4 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++-----
> 9 files changed, 34 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 2ddcad497fa3..c408bac3c533 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1559,11 +1559,11 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> for_each_ss_steering(iter, engine->gt, slice, subslice) {
> instdone->sampler[slice][subslice] =
> intel_gt_mcr_read(engine->gt,
> - GEN7_SAMPLER_INSTDONE,
> + GEN8_SAMPLER_INSTDONE,
> slice, subslice);
> instdone->row[slice][subslice] =
> intel_gt_mcr_read(engine->gt,
> - GEN7_ROW_INSTDONE,
> + GEN8_ROW_INSTDONE,
> slice, subslice);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 1cbb7226400b..e5a1ea255640 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -647,6 +647,9 @@
>
> #define GEN7_MISCCPCTL _MMIO(0x9424)
> #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
> +
> +#define GEN8_MISCCPCTL _MMIO(0x9424)
> +#define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
When I went through the driver to check if is there any instance where
platforms above Gen7 still using Gen7 registers, I found the following
two functions still using GEN7_MISCCPCTL. Can you check?
* dg2_gt_workarounds_init
* pvc_gt_workarounds_init
Regards,
Bala
> #define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
> #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
> #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
> @@ -1068,18 +1071,22 @@
> #define GEN12_GAM_DONE _MMIO(0xcf68)
>
> #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
> +#define GEN8_HALF_SLICE_CHICKEN1 _MMIO(0xe100)
> #define GEN7_MAX_PS_THREAD_DEP (8 << 12)
> #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
> #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
> #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
>
> #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
> +#define GEN8_SAMPLER_INSTDONE _MMIO(0xe160)
> #define GEN7_ROW_INSTDONE _MMIO(0xe164)
> +#define GEN8_ROW_INSTDONE _MMIO(0xe164)
>
> #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
> #define GEN8_ST_PO_DISABLE (1 << 13)
>
> -#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> +#define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> +#define GEN8_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> #define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
> #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
> #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
> @@ -1132,6 +1139,8 @@
> #define DISABLE_EARLY_EOT REG_BIT(1)
>
> #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
> +
> +#define GEN8_ROW_CHICKEN2 _MMIO(0xe4f4)
> #define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
> #define GEN12_DISABLE_EARLY_READ REG_BIT(14)
> #define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 6d2003d598e6..e382cb4c6971 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -295,10 +295,10 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
> * Also see the related UCGTCL1 write in bdw_init_clock_gating()
> * to disable EUTC clock gating.
> */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> DOP_CLOCK_GATING_DISABLE);
>
> - wa_masked_en(wal, HALF_SLICE_CHICKEN3,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> wa_masked_en(wal, HDC_CHICKEN0,
> @@ -386,7 +386,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
> IS_KABYLAKE(i915) ||
> IS_COFFEELAKE(i915) ||
> IS_COMETLAKE(i915))
> - wa_masked_en(wal, HALF_SLICE_CHICKEN3,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
> @@ -490,7 +490,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
>
> /* WaDisableSbeCacheDispatchPortSharing:kbl */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> }
>
> @@ -514,7 +514,7 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
>
> /* WaDisableSbeCacheDispatchPortSharing:cfl */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> }
>
> @@ -2107,7 +2107,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> /* Wa_14013392000:dg2_g11 */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
>
> /* Wa_16011620976:dg2_g11 */
> wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
> @@ -2156,7 +2156,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> DISABLE_128B_EVICTION_COMMAND_UDW);
>
> /* Wa_22012856258:dg2 */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> GEN12_DISABLE_READ_SUPPRESSION);
>
> /*
> @@ -2253,7 +2253,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
>
> /*
> * Wa_1407928979:tgl A*
> @@ -2282,7 +2282,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> GEN12_PUSH_CONST_DEREF_HOLD_DIS);
>
> /*
> @@ -2449,7 +2449,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> if (IS_HASWELL(i915)) {
> /* WaSampleCChickenBitEnable:hsw */
> wa_masked_en(wal,
> - HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
> + HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
>
> wa_masked_dis(wal,
> CACHE_MODE_0_GEN7,
> @@ -2747,7 +2747,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
>
> /* Wa_14010449647:xehpsdv */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
>
> /* Wa_18011725039:xehpsdv */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index 8f1165146013..9495a7928bc8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -244,8 +244,8 @@ struct __ext_steer_reg {
> };
>
> static const struct __ext_steer_reg xe_extregs[] = {
> - {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE},
> - {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE}
> + {"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE},
> + {"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE}
> };
>
> static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index a0372735cddb..9229243992c2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -35,7 +35,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
>
> if (GRAPHICS_VER(uncore->i915) == 9) {
> /* DOP Clock Gating Enable for GuC clocks */
> - intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
> + intel_uncore_rmw(uncore, GEN8_MISCCPCTL,
> 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
>
> /* allows for 5us (in 10ns units) before GT can go to RC6 */
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index daac2050d77d..700cc9688f47 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2257,7 +2257,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>
> /* display */
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index 1c6e941c9666..ac58460fb305 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -111,7 +111,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
> {RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
> {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
> {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
> - {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
> + {RCS0, HSW_HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
> {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
> {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
> {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 8279dc580a3e..638b77d64bf4 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -102,7 +102,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
> MMIO_D(_MMIO(0x2438));
> MMIO_D(_MMIO(0x243c));
> MMIO_D(_MMIO(0x7018));
> - MMIO_D(HALF_SLICE_CHICKEN3);
> + MMIO_D(HSW_HALF_SLICE_CHICKEN3);
> MMIO_D(GEN7_HALF_SLICE_CHICKEN1);
> /* display */
> MMIO_F(_MMIO(0x60220), 0x20);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8f86f56e7ca4..1aa77b18fd3c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4325,8 +4325,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> u32 val;
>
> /* WaTempDisableDOPClkGating:bdw */
> - misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> + misccpctl = intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);
>
> val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
> val &= ~L3_PRIO_CREDITS_MASK;
> @@ -4340,7 +4340,7 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> */
> intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
> udelay(1);
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl);
> }
>
> static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -4500,8 +4500,8 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
> gen9_init_clock_gating(dev_priv);
>
> /* WaDisableDopClockGating:skl */
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
> - ~GEN7_DOP_CLOCK_GATE_ENABLE);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL) &
> + ~GEN8_DOP_CLOCK_GATE_ENABLE);
>
> /* WAC6entrylatency:skl */
> intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
> --
> 2.37.3
>
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 01/12] drm/i915/gen8: Create separate reg definitions for new MCR registers
@ 2022-09-28 8:25 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 40+ messages in thread
From: Balasubramani Vivekanandan @ 2022-09-28 8:25 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 19.09.2022 15:32, Matt Roper wrote:
> Gen8 was the first time our hardware had multicast registers (or at
> least the first time the multicast nature was exposed and MMIO accesses
> could be steered). There are some registers that transitioned from
> singleton behavior to multicast during the gen7 -> gen8 transition;
> let's duplicate the register definitions for those registers in
> preparation for upcoming patches that will handle MCR registers in a
> special manner.
>
> The registers adjusted are:
> * MISCCPCTL
> * SAMPLER_INSTDONE
> * ROW_INSTDONE
> * ROW_CHICKEN2
> * HALF_SLICE_CHICKEN1
> * HALF_SLICE_CHICKEN3
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 11 +++++++++-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 22 +++++++++----------
> .../gpu/drm/i915/gt/uc/intel_guc_capture.c | 4 ++--
> drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/gvt/mmio_context.c | 2 +-
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 10 ++++-----
> 9 files changed, 34 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 2ddcad497fa3..c408bac3c533 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1559,11 +1559,11 @@ void intel_engine_get_instdone(const struct intel_engine_cs *engine,
> for_each_ss_steering(iter, engine->gt, slice, subslice) {
> instdone->sampler[slice][subslice] =
> intel_gt_mcr_read(engine->gt,
> - GEN7_SAMPLER_INSTDONE,
> + GEN8_SAMPLER_INSTDONE,
> slice, subslice);
> instdone->row[slice][subslice] =
> intel_gt_mcr_read(engine->gt,
> - GEN7_ROW_INSTDONE,
> + GEN8_ROW_INSTDONE,
> slice, subslice);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 1cbb7226400b..e5a1ea255640 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -647,6 +647,9 @@
>
> #define GEN7_MISCCPCTL _MMIO(0x9424)
> #define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
> +
> +#define GEN8_MISCCPCTL _MMIO(0x9424)
> +#define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
When I went through the driver to check if is there any instance where
platforms above Gen7 still using Gen7 registers, I found the following
two functions still using GEN7_MISCCPCTL. Can you check?
* dg2_gt_workarounds_init
* pvc_gt_workarounds_init
Regards,
Bala
> #define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
> #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
> #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4)
> @@ -1068,18 +1071,22 @@
> #define GEN12_GAM_DONE _MMIO(0xcf68)
>
> #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
> +#define GEN8_HALF_SLICE_CHICKEN1 _MMIO(0xe100)
> #define GEN7_MAX_PS_THREAD_DEP (8 << 12)
> #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
> #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
> #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
>
> #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
> +#define GEN8_SAMPLER_INSTDONE _MMIO(0xe160)
> #define GEN7_ROW_INSTDONE _MMIO(0xe164)
> +#define GEN8_ROW_INSTDONE _MMIO(0xe164)
>
> #define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
> #define GEN8_ST_PO_DISABLE (1 << 13)
>
> -#define HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> +#define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> +#define GEN8_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
> #define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
> #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
> #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
> @@ -1132,6 +1139,8 @@
> #define DISABLE_EARLY_EOT REG_BIT(1)
>
> #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
> +
> +#define GEN8_ROW_CHICKEN2 _MMIO(0xe4f4)
> #define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
> #define GEN12_DISABLE_EARLY_READ REG_BIT(14)
> #define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 6d2003d598e6..e382cb4c6971 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -295,10 +295,10 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
> * Also see the related UCGTCL1 write in bdw_init_clock_gating()
> * to disable EUTC clock gating.
> */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> DOP_CLOCK_GATING_DISABLE);
>
> - wa_masked_en(wal, HALF_SLICE_CHICKEN3,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> wa_masked_en(wal, HDC_CHICKEN0,
> @@ -386,7 +386,7 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
> IS_KABYLAKE(i915) ||
> IS_COFFEELAKE(i915) ||
> IS_COMETLAKE(i915))
> - wa_masked_en(wal, HALF_SLICE_CHICKEN3,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
> @@ -490,7 +490,7 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
>
> /* WaDisableSbeCacheDispatchPortSharing:kbl */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> }
>
> @@ -514,7 +514,7 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
> GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
>
> /* WaDisableSbeCacheDispatchPortSharing:cfl */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> }
>
> @@ -2107,7 +2107,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>
> if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
> /* Wa_14013392000:dg2_g11 */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
>
> /* Wa_16011620976:dg2_g11 */
> wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
> @@ -2156,7 +2156,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> DISABLE_128B_EVICTION_COMMAND_UDW);
>
> /* Wa_22012856258:dg2 */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> GEN12_DISABLE_READ_SUPPRESSION);
>
> /*
> @@ -2253,7 +2253,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
>
> /*
> * Wa_1407928979:tgl A*
> @@ -2282,7 +2282,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
> IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
> /* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
> - wa_masked_en(wal, GEN7_ROW_CHICKEN2,
> + wa_masked_en(wal, GEN8_ROW_CHICKEN2,
> GEN12_PUSH_CONST_DEREF_HOLD_DIS);
>
> /*
> @@ -2449,7 +2449,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
> if (IS_HASWELL(i915)) {
> /* WaSampleCChickenBitEnable:hsw */
> wa_masked_en(wal,
> - HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
> + HSW_HALF_SLICE_CHICKEN3, HSW_SAMPLE_C_PERFORMANCE);
>
> wa_masked_dis(wal,
> CACHE_MODE_0_GEN7,
> @@ -2747,7 +2747,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
> wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
>
> /* Wa_14010449647:xehpsdv */
> - wa_masked_en(wal, GEN7_HALF_SLICE_CHICKEN1,
> + wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
> GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
>
> /* Wa_18011725039:xehpsdv */
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index 8f1165146013..9495a7928bc8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -244,8 +244,8 @@ struct __ext_steer_reg {
> };
>
> static const struct __ext_steer_reg xe_extregs[] = {
> - {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE},
> - {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE}
> + {"GEN8_SAMPLER_INSTDONE", GEN8_SAMPLER_INSTDONE},
> + {"GEN8_ROW_INSTDONE", GEN8_ROW_INSTDONE}
> };
>
> static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index a0372735cddb..9229243992c2 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -35,7 +35,7 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
>
> if (GRAPHICS_VER(uncore->i915) == 9) {
> /* DOP Clock Gating Enable for GuC clocks */
> - intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
> + intel_uncore_rmw(uncore, GEN8_MISCCPCTL,
> 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
>
> /* allows for 5us (in 10ns units) before GT can go to RC6 */
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index daac2050d77d..700cc9688f47 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2257,7 +2257,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> - MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> + MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
> MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>
> /* display */
> diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
> index 1c6e941c9666..ac58460fb305 100644
> --- a/drivers/gpu/drm/i915/gvt/mmio_context.c
> +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
> @@ -111,7 +111,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
> {RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
> {RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
> {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
> - {RCS0, HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
> + {RCS0, HSW_HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
> {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
> {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
> {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index 8279dc580a3e..638b77d64bf4 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -102,7 +102,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
> MMIO_D(_MMIO(0x2438));
> MMIO_D(_MMIO(0x243c));
> MMIO_D(_MMIO(0x7018));
> - MMIO_D(HALF_SLICE_CHICKEN3);
> + MMIO_D(HSW_HALF_SLICE_CHICKEN3);
> MMIO_D(GEN7_HALF_SLICE_CHICKEN1);
> /* display */
> MMIO_F(_MMIO(0x60220), 0x20);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8f86f56e7ca4..1aa77b18fd3c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4325,8 +4325,8 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> u32 val;
>
> /* WaTempDisableDOPClkGating:bdw */
> - misccpctl = intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL);
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
> + misccpctl = intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);
>
> val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
> val &= ~L3_PRIO_CREDITS_MASK;
> @@ -4340,7 +4340,7 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> */
> intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
> udelay(1);
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl);
> }
>
> static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> @@ -4500,8 +4500,8 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
> gen9_init_clock_gating(dev_priv);
>
> /* WaDisableDopClockGating:skl */
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN7_MISCCPCTL) &
> - ~GEN7_DOP_CLOCK_GATE_ENABLE);
> + intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL) &
> + ~GEN8_DOP_CLOCK_GATE_ENABLE);
>
> /* WAC6entrylatency:skl */
> intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
> --
> 2.37.3
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 02/12] drm/i915/xehp: Create separate reg definitions for new MCR registers
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Starting in Xe_HP, several registers our driver works with have been
converted from singleton registers into replicated registers with
multicast behavior. Although the registers are still located at the
same MMIO offsets as on previous platforms, let's duplicate the register
definitions in preparation for upcoming patches that will handle
multicast registers in a special manner.
The registers that are now replicated on Xe_HP are:
* PAT_INDEX (mslice replication)
* FF_MODE2 (gslice replication)
* COMMON_SLICE_CHICKEN3 (gslice replication)
* SLICE_COMMON_ECO_CHICKEN1 (gslice replication)
* SLICE_UNIT_LEVEL_CLKGATE (gslice replication)
* LNCFCMOCS (lncf replication)
Bspec: 66534
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 ++++++++-----
drivers/gpu/drm/i915/gt/intel_gtt.c | 29 ++++++++++++++-------
drivers/gpu/drm/i915/gt/intel_mocs.c | 5 +++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 ++++++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 +++--
5 files changed, 52 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index e5a1ea255640..559e3473f14c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -329,6 +329,7 @@
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
+#define XEHP_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
#define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)
#define XEHP_TILE_LMEM_RANGE_SHIFT 8
@@ -387,7 +388,8 @@
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
-#define FF_MODE2 _MMIO(0x6604)
+#define GEN12_FF_MODE2 _MMIO(0x6604)
+#define XEHP_FF_MODE2 _MMIO(0x6604)
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
@@ -442,6 +444,7 @@
#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
@@ -455,10 +458,9 @@
#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
-#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
-
-#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
+#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
@@ -703,7 +705,8 @@
#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
#define LTCDD_CLKGATE_DIS REG_BIT(10)
-#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
+#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
+#define XEHP_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
#define RCCUNIT_CLKGATE_DIS (1 << 7)
#define MSCUNIT_CLKGATE_DIS (1 << 10)
@@ -718,7 +721,7 @@
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
-#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
+#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
#define GWUNIT_CLKGATE_DIS REG_BIT(16)
@@ -943,7 +946,8 @@
/* MOCS (Memory Object Control State) registers */
#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
-#define GEN9_LNCFCMOCS_REG_COUNT 32
+#define XEHP_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
+#define LNCFCMOCS_REG_COUNT 32
#define GEN7_L3CNTLREG3 _MMIO(0xb024)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index b67831833c9a..601d89b4feb1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -479,15 +479,26 @@ void gtt_write_workarounds(struct intel_gt *gt)
static void tgl_setup_private_ppat(struct intel_uncore *uncore)
{
- /* TGL doesn't support LLC or AGE settings */
- intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
+ if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50)) {
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
+ } else {
+ /* TGL doesn't support LLC or AGE settings */
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
+ }
}
static void icl_setup_private_ppat(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c6ebe2781076..06643701bf24 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -608,7 +608,10 @@ static void init_l3cc_table(struct intel_uncore *uncore,
u32 l3cc;
for_each_l3cc(l3cc, table, i)
- intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
+ if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50))
+ intel_uncore_write_fw(uncore, XEHP_LNCFCMOCS(i), l3cc);
+ else
+ intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
}
void intel_mocs_init_engine(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e382cb4c6971..eff5f4f85374 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -572,7 +572,7 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
wa_add(wal,
- FF_MODE2,
+ XEHP_FF_MODE2,
FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_TDS_TIMER_128,
0, false);
@@ -599,7 +599,7 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
* verification is ignored.
*/
wa_add(wal,
- FF_MODE2,
+ GEN12_FF_MODE2,
FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_TDS_TIMER_128,
0, false);
@@ -637,7 +637,7 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
* to Wa_1608008084.
*/
wa_add(wal,
- FF_MODE2,
+ GEN12_FF_MODE2,
FF_MODE2_GS_TIMER_MASK,
FF_MODE2_GS_TIMER_224,
0, false);
@@ -670,7 +670,7 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
/* Wa_14010469329:dg2_g10 */
- wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
+ wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
/*
@@ -678,12 +678,12 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
* Wa_22010613112:dg2_g10
* Wa_14010698770:dg2_g10
*/
- wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
+ wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
}
/* Wa_16013271637:dg2 */
- wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
+ wa_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
/* Wa_14014947963:dg2 */
@@ -1255,14 +1255,14 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_1406680159:icl,ehl */
wa_write_or(wal,
- SUBSLICE_UNIT_LEVEL_CLKGATE,
+ GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
GWUNIT_CLKGATE_DIS);
/* Wa_1607087056:icl,ehl,jsl */
if (IS_ICELAKE(i915) ||
IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
wa_write_or(wal,
- SLICE_UNIT_LEVEL_CLKGATE,
+ GEN11_SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
/*
@@ -1322,7 +1322,7 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_1607087056:tgl also know as BUG:1409180338 */
if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
wa_write_or(wal,
- SLICE_UNIT_LEVEL_CLKGATE,
+ GEN11_SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
/* Wa_1408615072:tgl[a0] */
@@ -1341,7 +1341,7 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_1607087056:dg1 */
if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
wa_write_or(wal,
- SLICE_UNIT_LEVEL_CLKGATE,
+ GEN11_SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
/* Wa_1409420604:dg1 */
@@ -1445,7 +1445,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
CG3DDISCFEG_CLKGATE_DIS);
/* Wa_14011006942:dg2 */
- wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE,
+ wa_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
DSS_ROUTER_CLKGATE_DIS);
}
@@ -1457,7 +1457,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
/* Wa_14011371254:dg2_g10 */
- wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
+ wa_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
/* Wa_14011431319:dg2_g10 */
wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 74cbe8eaf531..7d9f4f57ca95 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -372,8 +372,11 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
false);
/* add in local MOCS registers */
- for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++)
- ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
+ for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ ret |= GUC_MMIO_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
+ else
+ ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
return ret ? -1 : 0;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH 02/12] drm/i915/xehp: Create separate reg definitions for new MCR registers
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Starting in Xe_HP, several registers our driver works with have been
converted from singleton registers into replicated registers with
multicast behavior. Although the registers are still located at the
same MMIO offsets as on previous platforms, let's duplicate the register
definitions in preparation for upcoming patches that will handle
multicast registers in a special manner.
The registers that are now replicated on Xe_HP are:
* PAT_INDEX (mslice replication)
* FF_MODE2 (gslice replication)
* COMMON_SLICE_CHICKEN3 (gslice replication)
* SLICE_COMMON_ECO_CHICKEN1 (gslice replication)
* SLICE_UNIT_LEVEL_CLKGATE (gslice replication)
* LNCFCMOCS (lncf replication)
Bspec: 66534
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 ++++++++-----
drivers/gpu/drm/i915/gt/intel_gtt.c | 29 ++++++++++++++-------
drivers/gpu/drm/i915/gt/intel_mocs.c | 5 +++-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 ++++++++---------
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 +++--
5 files changed, 52 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index e5a1ea255640..559e3473f14c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -329,6 +329,7 @@
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
+#define XEHP_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
#define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)
#define XEHP_TILE_LMEM_RANGE_SHIFT 8
@@ -387,7 +388,8 @@
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
-#define FF_MODE2 _MMIO(0x6604)
+#define GEN12_FF_MODE2 _MMIO(0x6604)
+#define XEHP_FF_MODE2 _MMIO(0x6604)
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
@@ -442,6 +444,7 @@
#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
@@ -455,10 +458,9 @@
#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
-#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
-
-#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
+#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
#define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
@@ -703,7 +705,8 @@
#define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
#define LTCDD_CLKGATE_DIS REG_BIT(10)
-#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
+#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
+#define XEHP_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
#define RCCUNIT_CLKGATE_DIS (1 << 7)
#define MSCUNIT_CLKGATE_DIS (1 << 10)
@@ -718,7 +721,7 @@
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
-#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
+#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
#define GWUNIT_CLKGATE_DIS REG_BIT(16)
@@ -943,7 +946,8 @@
/* MOCS (Memory Object Control State) registers */
#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
-#define GEN9_LNCFCMOCS_REG_COUNT 32
+#define XEHP_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
+#define LNCFCMOCS_REG_COUNT 32
#define GEN7_L3CNTLREG3 _MMIO(0xb024)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index b67831833c9a..601d89b4feb1 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -479,15 +479,26 @@ void gtt_write_workarounds(struct intel_gt *gt)
static void tgl_setup_private_ppat(struct intel_uncore *uncore)
{
- /* TGL doesn't support LLC or AGE settings */
- intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
+ if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50)) {
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
+ } else {
+ /* TGL doesn't support LLC or AGE settings */
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
+ intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
+ }
}
static void icl_setup_private_ppat(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index c6ebe2781076..06643701bf24 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -608,7 +608,10 @@ static void init_l3cc_table(struct intel_uncore *uncore,
u32 l3cc;
for_each_l3cc(l3cc, table, i)
- intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
+ if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50))
+ intel_uncore_write_fw(uncore, XEHP_LNCFCMOCS(i), l3cc);
+ else
+ intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
}
void intel_mocs_init_engine(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index e382cb4c6971..eff5f4f85374 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -572,7 +572,7 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
wa_add(wal,
- FF_MODE2,
+ XEHP_FF_MODE2,
FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_TDS_TIMER_128,
0, false);
@@ -599,7 +599,7 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
* verification is ignored.
*/
wa_add(wal,
- FF_MODE2,
+ GEN12_FF_MODE2,
FF_MODE2_TDS_TIMER_MASK,
FF_MODE2_TDS_TIMER_128,
0, false);
@@ -637,7 +637,7 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
* to Wa_1608008084.
*/
wa_add(wal,
- FF_MODE2,
+ GEN12_FF_MODE2,
FF_MODE2_GS_TIMER_MASK,
FF_MODE2_GS_TIMER_224,
0, false);
@@ -670,7 +670,7 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
/* Wa_14010469329:dg2_g10 */
- wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
+ wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
/*
@@ -678,12 +678,12 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
* Wa_22010613112:dg2_g10
* Wa_14010698770:dg2_g10
*/
- wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
+ wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
}
/* Wa_16013271637:dg2 */
- wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
+ wa_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
/* Wa_14014947963:dg2 */
@@ -1255,14 +1255,14 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_1406680159:icl,ehl */
wa_write_or(wal,
- SUBSLICE_UNIT_LEVEL_CLKGATE,
+ GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
GWUNIT_CLKGATE_DIS);
/* Wa_1607087056:icl,ehl,jsl */
if (IS_ICELAKE(i915) ||
IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
wa_write_or(wal,
- SLICE_UNIT_LEVEL_CLKGATE,
+ GEN11_SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
/*
@@ -1322,7 +1322,7 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_1607087056:tgl also know as BUG:1409180338 */
if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
wa_write_or(wal,
- SLICE_UNIT_LEVEL_CLKGATE,
+ GEN11_SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
/* Wa_1408615072:tgl[a0] */
@@ -1341,7 +1341,7 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_1607087056:dg1 */
if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
wa_write_or(wal,
- SLICE_UNIT_LEVEL_CLKGATE,
+ GEN11_SLICE_UNIT_LEVEL_CLKGATE,
L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
/* Wa_1409420604:dg1 */
@@ -1445,7 +1445,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
CG3DDISCFEG_CLKGATE_DIS);
/* Wa_14011006942:dg2 */
- wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE,
+ wa_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
DSS_ROUTER_CLKGATE_DIS);
}
@@ -1457,7 +1457,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
/* Wa_14011371254:dg2_g10 */
- wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
+ wa_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
/* Wa_14011431319:dg2_g10 */
wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 74cbe8eaf531..7d9f4f57ca95 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -372,8 +372,11 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
false);
/* add in local MOCS registers */
- for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++)
- ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
+ for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
+ if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
+ ret |= GUC_MMIO_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
+ else
+ ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
return ret ? -1 : 0;
}
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [PATCH 02/12] drm/i915/xehp: Create separate reg definitions for new MCR registers
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-28 9:50 ` Balasubramani Vivekanandan
-1 siblings, 0 replies; 40+ messages in thread
From: Balasubramani Vivekanandan @ 2022-09-28 9:50 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 19.09.2022 15:32, Matt Roper wrote:
> Starting in Xe_HP, several registers our driver works with have been
> converted from singleton registers into replicated registers with
> multicast behavior. Although the registers are still located at the
> same MMIO offsets as on previous platforms, let's duplicate the register
> definitions in preparation for upcoming patches that will handle
> multicast registers in a special manner.
>
> The registers that are now replicated on Xe_HP are:
> * PAT_INDEX (mslice replication)
> * FF_MODE2 (gslice replication)
> * COMMON_SLICE_CHICKEN3 (gslice replication)
> * SLICE_COMMON_ECO_CHICKEN1 (gslice replication)
> * SLICE_UNIT_LEVEL_CLKGATE (gslice replication)
> * LNCFCMOCS (lncf replication)
>
> Bspec: 66534
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 ++++++++-----
> drivers/gpu/drm/i915/gt/intel_gtt.c | 29 ++++++++++++++-------
> drivers/gpu/drm/i915/gt/intel_mocs.c | 5 +++-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 ++++++++---------
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 +++--
> 5 files changed, 52 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index e5a1ea255640..559e3473f14c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -329,6 +329,7 @@
> #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
>
> #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
> +#define XEHP_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
>
> #define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)
> #define XEHP_TILE_LMEM_RANGE_SHIFT 8
> @@ -387,7 +388,8 @@
> #define DIS_OVER_FETCH_CACHE REG_BIT(1)
> #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
>
> -#define FF_MODE2 _MMIO(0x6604)
> +#define GEN12_FF_MODE2 _MMIO(0x6604)
> +#define XEHP_FF_MODE2 _MMIO(0x6604)
> #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
> #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
> #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
> @@ -442,6 +444,7 @@
> #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
>
> #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> +#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
> #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
> #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
> @@ -455,10 +458,9 @@
> #define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
>
> #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> -#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
> -
> -#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> +#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
> +#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
>
> #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
> #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> @@ -703,7 +705,8 @@
> #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
> #define LTCDD_CLKGATE_DIS REG_BIT(10)
>
> -#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> +#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> +#define XEHP_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> #define SARBUNIT_CLKGATE_DIS (1 << 5)
> #define RCCUNIT_CLKGATE_DIS (1 << 7)
> #define MSCUNIT_CLKGATE_DIS (1 << 10)
> @@ -718,7 +721,7 @@
> #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
> #define PSDUNIT_CLKGATE_DIS REG_BIT(5)
>
> -#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
> +#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
> #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
> #define GWUNIT_CLKGATE_DIS REG_BIT(16)
>
> @@ -943,7 +946,8 @@
>
> /* MOCS (Memory Object Control State) registers */
> #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
GEN9_LNCFCMOCS is used in few functions in file selftest_mocs.c. This
patch has untouched those instances. Is it by intention to handle it
part of a separate series? If the plan is to handle it later sometime
can we create a ticket to keep track of it?
Regards,
Bala
> -#define GEN9_LNCFCMOCS_REG_COUNT 32
> +#define XEHP_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
> +#define LNCFCMOCS_REG_COUNT 32
>
> #define GEN7_L3CNTLREG3 _MMIO(0xb024)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index b67831833c9a..601d89b4feb1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -479,15 +479,26 @@ void gtt_write_workarounds(struct intel_gt *gt)
>
> static void tgl_setup_private_ppat(struct intel_uncore *uncore)
> {
> - /* TGL doesn't support LLC or AGE settings */
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
> + if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50)) {
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
> + } else {
> + /* TGL doesn't support LLC or AGE settings */
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
> + }
> }
>
> static void icl_setup_private_ppat(struct intel_uncore *uncore)
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index c6ebe2781076..06643701bf24 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -608,7 +608,10 @@ static void init_l3cc_table(struct intel_uncore *uncore,
> u32 l3cc;
>
> for_each_l3cc(l3cc, table, i)
> - intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
> + if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50))
> + intel_uncore_write_fw(uncore, XEHP_LNCFCMOCS(i), l3cc);
> + else
> + intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
> }
>
> void intel_mocs_init_engine(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e382cb4c6971..eff5f4f85374 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -572,7 +572,7 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
> REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
> wa_add(wal,
> - FF_MODE2,
> + XEHP_FF_MODE2,
> FF_MODE2_TDS_TIMER_MASK,
> FF_MODE2_TDS_TIMER_128,
> 0, false);
> @@ -599,7 +599,7 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> * verification is ignored.
> */
> wa_add(wal,
> - FF_MODE2,
> + GEN12_FF_MODE2,
> FF_MODE2_TDS_TIMER_MASK,
> FF_MODE2_TDS_TIMER_128,
> 0, false);
> @@ -637,7 +637,7 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
> * to Wa_1608008084.
> */
> wa_add(wal,
> - FF_MODE2,
> + GEN12_FF_MODE2,
> FF_MODE2_GS_TIMER_MASK,
> FF_MODE2_GS_TIMER_224,
> 0, false);
> @@ -670,7 +670,7 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>
> if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
> /* Wa_14010469329:dg2_g10 */
> - wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> + wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
> XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
>
> /*
> @@ -678,12 +678,12 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> * Wa_22010613112:dg2_g10
> * Wa_14010698770:dg2_g10
> */
> - wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> + wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
> GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> }
>
> /* Wa_16013271637:dg2 */
> - wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
> + wa_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
> MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
>
> /* Wa_14014947963:dg2 */
> @@ -1255,14 +1255,14 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>
> /* Wa_1406680159:icl,ehl */
> wa_write_or(wal,
> - SUBSLICE_UNIT_LEVEL_CLKGATE,
> + GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
> GWUNIT_CLKGATE_DIS);
>
> /* Wa_1607087056:icl,ehl,jsl */
> if (IS_ICELAKE(i915) ||
> IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> wa_write_or(wal,
> - SLICE_UNIT_LEVEL_CLKGATE,
> + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>
> /*
> @@ -1322,7 +1322,7 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> /* Wa_1607087056:tgl also know as BUG:1409180338 */
> if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> wa_write_or(wal,
> - SLICE_UNIT_LEVEL_CLKGATE,
> + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>
> /* Wa_1408615072:tgl[a0] */
> @@ -1341,7 +1341,7 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> /* Wa_1607087056:dg1 */
> if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> wa_write_or(wal,
> - SLICE_UNIT_LEVEL_CLKGATE,
> + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>
> /* Wa_1409420604:dg1 */
> @@ -1445,7 +1445,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> CG3DDISCFEG_CLKGATE_DIS);
>
> /* Wa_14011006942:dg2 */
> - wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE,
> + wa_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
> DSS_ROUTER_CLKGATE_DIS);
> }
>
> @@ -1457,7 +1457,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
>
> /* Wa_14011371254:dg2_g10 */
> - wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
> + wa_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
>
> /* Wa_14011431319:dg2_g10 */
> wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 74cbe8eaf531..7d9f4f57ca95 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -372,8 +372,11 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
> false);
>
> /* add in local MOCS registers */
> - for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++)
> - ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
> + for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + ret |= GUC_MMIO_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
> + else
> + ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
>
> return ret ? -1 : 0;
> }
> --
> 2.37.3
>
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 02/12] drm/i915/xehp: Create separate reg definitions for new MCR registers
@ 2022-09-28 9:50 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 40+ messages in thread
From: Balasubramani Vivekanandan @ 2022-09-28 9:50 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 19.09.2022 15:32, Matt Roper wrote:
> Starting in Xe_HP, several registers our driver works with have been
> converted from singleton registers into replicated registers with
> multicast behavior. Although the registers are still located at the
> same MMIO offsets as on previous platforms, let's duplicate the register
> definitions in preparation for upcoming patches that will handle
> multicast registers in a special manner.
>
> The registers that are now replicated on Xe_HP are:
> * PAT_INDEX (mslice replication)
> * FF_MODE2 (gslice replication)
> * COMMON_SLICE_CHICKEN3 (gslice replication)
> * SLICE_COMMON_ECO_CHICKEN1 (gslice replication)
> * SLICE_UNIT_LEVEL_CLKGATE (gslice replication)
> * LNCFCMOCS (lncf replication)
>
> Bspec: 66534
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 ++++++++-----
> drivers/gpu/drm/i915/gt/intel_gtt.c | 29 ++++++++++++++-------
> drivers/gpu/drm/i915/gt/intel_mocs.c | 5 +++-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 ++++++++---------
> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 +++--
> 5 files changed, 52 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index e5a1ea255640..559e3473f14c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -329,6 +329,7 @@
> #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
>
> #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
> +#define XEHP_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
>
> #define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)
> #define XEHP_TILE_LMEM_RANGE_SHIFT 8
> @@ -387,7 +388,8 @@
> #define DIS_OVER_FETCH_CACHE REG_BIT(1)
> #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
>
> -#define FF_MODE2 _MMIO(0x6604)
> +#define GEN12_FF_MODE2 _MMIO(0x6604)
> +#define XEHP_FF_MODE2 _MMIO(0x6604)
> #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
> #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
> #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
> @@ -442,6 +444,7 @@
> #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
>
> #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> +#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
> #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
> #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
> @@ -455,10 +458,9 @@
> #define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
>
> #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> -#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
> -
> -#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> +#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
> +#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
>
> #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
> #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> @@ -703,7 +705,8 @@
> #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
> #define LTCDD_CLKGATE_DIS REG_BIT(10)
>
> -#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> +#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> +#define XEHP_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> #define SARBUNIT_CLKGATE_DIS (1 << 5)
> #define RCCUNIT_CLKGATE_DIS (1 << 7)
> #define MSCUNIT_CLKGATE_DIS (1 << 10)
> @@ -718,7 +721,7 @@
> #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
> #define PSDUNIT_CLKGATE_DIS REG_BIT(5)
>
> -#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
> +#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
> #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
> #define GWUNIT_CLKGATE_DIS REG_BIT(16)
>
> @@ -943,7 +946,8 @@
>
> /* MOCS (Memory Object Control State) registers */
> #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
GEN9_LNCFCMOCS is used in few functions in file selftest_mocs.c. This
patch has untouched those instances. Is it by intention to handle it
part of a separate series? If the plan is to handle it later sometime
can we create a ticket to keep track of it?
Regards,
Bala
> -#define GEN9_LNCFCMOCS_REG_COUNT 32
> +#define XEHP_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
> +#define LNCFCMOCS_REG_COUNT 32
>
> #define GEN7_L3CNTLREG3 _MMIO(0xb024)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index b67831833c9a..601d89b4feb1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -479,15 +479,26 @@ void gtt_write_workarounds(struct intel_gt *gt)
>
> static void tgl_setup_private_ppat(struct intel_uncore *uncore)
> {
> - /* TGL doesn't support LLC or AGE settings */
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
> - intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
> + if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50)) {
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
> + } else {
> + /* TGL doesn't support LLC or AGE settings */
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
> + intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
> + }
> }
>
> static void icl_setup_private_ppat(struct intel_uncore *uncore)
> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> index c6ebe2781076..06643701bf24 100644
> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> @@ -608,7 +608,10 @@ static void init_l3cc_table(struct intel_uncore *uncore,
> u32 l3cc;
>
> for_each_l3cc(l3cc, table, i)
> - intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
> + if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50))
> + intel_uncore_write_fw(uncore, XEHP_LNCFCMOCS(i), l3cc);
> + else
> + intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
> }
>
> void intel_mocs_init_engine(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index e382cb4c6971..eff5f4f85374 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -572,7 +572,7 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
> REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
> wa_add(wal,
> - FF_MODE2,
> + XEHP_FF_MODE2,
> FF_MODE2_TDS_TIMER_MASK,
> FF_MODE2_TDS_TIMER_128,
> 0, false);
> @@ -599,7 +599,7 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> * verification is ignored.
> */
> wa_add(wal,
> - FF_MODE2,
> + GEN12_FF_MODE2,
> FF_MODE2_TDS_TIMER_MASK,
> FF_MODE2_TDS_TIMER_128,
> 0, false);
> @@ -637,7 +637,7 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
> * to Wa_1608008084.
> */
> wa_add(wal,
> - FF_MODE2,
> + GEN12_FF_MODE2,
> FF_MODE2_GS_TIMER_MASK,
> FF_MODE2_GS_TIMER_224,
> 0, false);
> @@ -670,7 +670,7 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>
> if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
> /* Wa_14010469329:dg2_g10 */
> - wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> + wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
> XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
>
> /*
> @@ -678,12 +678,12 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> * Wa_22010613112:dg2_g10
> * Wa_14010698770:dg2_g10
> */
> - wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> + wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
> GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> }
>
> /* Wa_16013271637:dg2 */
> - wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
> + wa_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
> MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
>
> /* Wa_14014947963:dg2 */
> @@ -1255,14 +1255,14 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
>
> /* Wa_1406680159:icl,ehl */
> wa_write_or(wal,
> - SUBSLICE_UNIT_LEVEL_CLKGATE,
> + GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
> GWUNIT_CLKGATE_DIS);
>
> /* Wa_1607087056:icl,ehl,jsl */
> if (IS_ICELAKE(i915) ||
> IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> wa_write_or(wal,
> - SLICE_UNIT_LEVEL_CLKGATE,
> + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>
> /*
> @@ -1322,7 +1322,7 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> /* Wa_1607087056:tgl also know as BUG:1409180338 */
> if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> wa_write_or(wal,
> - SLICE_UNIT_LEVEL_CLKGATE,
> + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>
> /* Wa_1408615072:tgl[a0] */
> @@ -1341,7 +1341,7 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> /* Wa_1607087056:dg1 */
> if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> wa_write_or(wal,
> - SLICE_UNIT_LEVEL_CLKGATE,
> + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
>
> /* Wa_1409420604:dg1 */
> @@ -1445,7 +1445,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> CG3DDISCFEG_CLKGATE_DIS);
>
> /* Wa_14011006942:dg2 */
> - wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE,
> + wa_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
> DSS_ROUTER_CLKGATE_DIS);
> }
>
> @@ -1457,7 +1457,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
>
> /* Wa_14011371254:dg2_g10 */
> - wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
> + wa_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
>
> /* Wa_14011431319:dg2_g10 */
> wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> index 74cbe8eaf531..7d9f4f57ca95 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> @@ -372,8 +372,11 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
> false);
>
> /* add in local MOCS registers */
> - for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++)
> - ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
> + for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
> + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> + ret |= GUC_MMIO_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
> + else
> + ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
>
> return ret ? -1 : 0;
> }
> --
> 2.37.3
>
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 02/12] drm/i915/xehp: Create separate reg definitions for new MCR registers
2022-09-28 9:50 ` [Intel-gfx] " Balasubramani Vivekanandan
@ 2022-09-30 21:54 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-30 21:54 UTC (permalink / raw)
To: Balasubramani Vivekanandan; +Cc: intel-gfx, dri-devel
On Wed, Sep 28, 2022 at 03:20:52PM +0530, Balasubramani Vivekanandan wrote:
> On 19.09.2022 15:32, Matt Roper wrote:
> > Starting in Xe_HP, several registers our driver works with have been
> > converted from singleton registers into replicated registers with
> > multicast behavior. Although the registers are still located at the
> > same MMIO offsets as on previous platforms, let's duplicate the register
> > definitions in preparation for upcoming patches that will handle
> > multicast registers in a special manner.
> >
> > The registers that are now replicated on Xe_HP are:
> > * PAT_INDEX (mslice replication)
> > * FF_MODE2 (gslice replication)
> > * COMMON_SLICE_CHICKEN3 (gslice replication)
> > * SLICE_COMMON_ECO_CHICKEN1 (gslice replication)
> > * SLICE_UNIT_LEVEL_CLKGATE (gslice replication)
> > * LNCFCMOCS (lncf replication)
> >
> > Bspec: 66534
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 ++++++++-----
> > drivers/gpu/drm/i915/gt/intel_gtt.c | 29 ++++++++++++++-------
> > drivers/gpu/drm/i915/gt/intel_mocs.c | 5 +++-
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 ++++++++---------
> > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 +++--
> > 5 files changed, 52 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index e5a1ea255640..559e3473f14c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -329,6 +329,7 @@
> > #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
> >
> > #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
> > +#define XEHP_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
> >
> > #define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)
> > #define XEHP_TILE_LMEM_RANGE_SHIFT 8
> > @@ -387,7 +388,8 @@
> > #define DIS_OVER_FETCH_CACHE REG_BIT(1)
> > #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
> >
> > -#define FF_MODE2 _MMIO(0x6604)
> > +#define GEN12_FF_MODE2 _MMIO(0x6604)
> > +#define XEHP_FF_MODE2 _MMIO(0x6604)
> > #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
> > #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
> > #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
> > @@ -442,6 +444,7 @@
> > #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
> >
> > #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> > +#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> > #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
> > #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
> > #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
> > @@ -455,10 +458,9 @@
> > #define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
> >
> > #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> > -#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
> > -
> > -#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> > +#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> > #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
> > +#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
> >
> > #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
> > #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> > @@ -703,7 +705,8 @@
> > #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
> > #define LTCDD_CLKGATE_DIS REG_BIT(10)
> >
> > -#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> > +#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> > +#define XEHP_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> > #define SARBUNIT_CLKGATE_DIS (1 << 5)
> > #define RCCUNIT_CLKGATE_DIS (1 << 7)
> > #define MSCUNIT_CLKGATE_DIS (1 << 10)
> > @@ -718,7 +721,7 @@
> > #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
> > #define PSDUNIT_CLKGATE_DIS REG_BIT(5)
> >
> > -#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
> > +#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
> > #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
> > #define GWUNIT_CLKGATE_DIS REG_BIT(16)
> >
> > @@ -943,7 +946,8 @@
> >
> > /* MOCS (Memory Object Control State) registers */
> > #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
>
> GEN9_LNCFCMOCS is used in few functions in file selftest_mocs.c. This
> patch has untouched those instances. Is it by intention to handle it
> part of a separate series? If the plan is to handle it later sometime
> can we create a ticket to keep track of it?
Both of the instances there are just looking up the offset of the
register (which is the same for both the MCR and non-MCR version of the
register) and aren't doing any CPU reads/writes directly where the
multicast nature of the register would come into play. So I think it's
okay to keep using the GEN9_ version there to keep things simple. But
I'll add a note about it to the commit message.
Matt
>
> Regards,
> Bala
>
> > -#define GEN9_LNCFCMOCS_REG_COUNT 32
> > +#define XEHP_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
> > +#define LNCFCMOCS_REG_COUNT 32
> >
> > #define GEN7_L3CNTLREG3 _MMIO(0xb024)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > index b67831833c9a..601d89b4feb1 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > @@ -479,15 +479,26 @@ void gtt_write_workarounds(struct intel_gt *gt)
> >
> > static void tgl_setup_private_ppat(struct intel_uncore *uncore)
> > {
> > - /* TGL doesn't support LLC or AGE settings */
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
> > + if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50)) {
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
> > + } else {
> > + /* TGL doesn't support LLC or AGE settings */
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
> > + }
> > }
> >
> > static void icl_setup_private_ppat(struct intel_uncore *uncore)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > index c6ebe2781076..06643701bf24 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > @@ -608,7 +608,10 @@ static void init_l3cc_table(struct intel_uncore *uncore,
> > u32 l3cc;
> >
> > for_each_l3cc(l3cc, table, i)
> > - intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
> > + if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50))
> > + intel_uncore_write_fw(uncore, XEHP_LNCFCMOCS(i), l3cc);
> > + else
> > + intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
> > }
> >
> > void intel_mocs_init_engine(struct intel_engine_cs *engine)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index e382cb4c6971..eff5f4f85374 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -572,7 +572,7 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> > wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
> > REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
> > wa_add(wal,
> > - FF_MODE2,
> > + XEHP_FF_MODE2,
> > FF_MODE2_TDS_TIMER_MASK,
> > FF_MODE2_TDS_TIMER_128,
> > 0, false);
> > @@ -599,7 +599,7 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> > * verification is ignored.
> > */
> > wa_add(wal,
> > - FF_MODE2,
> > + GEN12_FF_MODE2,
> > FF_MODE2_TDS_TIMER_MASK,
> > FF_MODE2_TDS_TIMER_128,
> > 0, false);
> > @@ -637,7 +637,7 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
> > * to Wa_1608008084.
> > */
> > wa_add(wal,
> > - FF_MODE2,
> > + GEN12_FF_MODE2,
> > FF_MODE2_GS_TIMER_MASK,
> > FF_MODE2_GS_TIMER_224,
> > 0, false);
> > @@ -670,7 +670,7 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> >
> > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
> > /* Wa_14010469329:dg2_g10 */
> > - wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> > + wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
> > XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
> >
> > /*
> > @@ -678,12 +678,12 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> > * Wa_22010613112:dg2_g10
> > * Wa_14010698770:dg2_g10
> > */
> > - wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> > + wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
> > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > }
> >
> > /* Wa_16013271637:dg2 */
> > - wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
> > + wa_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
> > MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
> >
> > /* Wa_14014947963:dg2 */
> > @@ -1255,14 +1255,14 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> >
> > /* Wa_1406680159:icl,ehl */
> > wa_write_or(wal,
> > - SUBSLICE_UNIT_LEVEL_CLKGATE,
> > + GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
> > GWUNIT_CLKGATE_DIS);
> >
> > /* Wa_1607087056:icl,ehl,jsl */
> > if (IS_ICELAKE(i915) ||
> > IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > wa_write_or(wal,
> > - SLICE_UNIT_LEVEL_CLKGATE,
> > + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> >
> > /*
> > @@ -1322,7 +1322,7 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > /* Wa_1607087056:tgl also know as BUG:1409180338 */
> > if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > wa_write_or(wal,
> > - SLICE_UNIT_LEVEL_CLKGATE,
> > + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> >
> > /* Wa_1408615072:tgl[a0] */
> > @@ -1341,7 +1341,7 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > /* Wa_1607087056:dg1 */
> > if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > wa_write_or(wal,
> > - SLICE_UNIT_LEVEL_CLKGATE,
> > + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> >
> > /* Wa_1409420604:dg1 */
> > @@ -1445,7 +1445,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > CG3DDISCFEG_CLKGATE_DIS);
> >
> > /* Wa_14011006942:dg2 */
> > - wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE,
> > + wa_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
> > DSS_ROUTER_CLKGATE_DIS);
> > }
> >
> > @@ -1457,7 +1457,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
> >
> > /* Wa_14011371254:dg2_g10 */
> > - wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
> > + wa_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
> >
> > /* Wa_14011431319:dg2_g10 */
> > wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > index 74cbe8eaf531..7d9f4f57ca95 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > @@ -372,8 +372,11 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
> > false);
> >
> > /* add in local MOCS registers */
> > - for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++)
> > - ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
> > + for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
> > + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> > + ret |= GUC_MMIO_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
> > + else
> > + ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
> >
> > return ret ? -1 : 0;
> > }
> > --
> > 2.37.3
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH 02/12] drm/i915/xehp: Create separate reg definitions for new MCR registers
@ 2022-09-30 21:54 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-30 21:54 UTC (permalink / raw)
To: Balasubramani Vivekanandan; +Cc: intel-gfx, dri-devel
On Wed, Sep 28, 2022 at 03:20:52PM +0530, Balasubramani Vivekanandan wrote:
> On 19.09.2022 15:32, Matt Roper wrote:
> > Starting in Xe_HP, several registers our driver works with have been
> > converted from singleton registers into replicated registers with
> > multicast behavior. Although the registers are still located at the
> > same MMIO offsets as on previous platforms, let's duplicate the register
> > definitions in preparation for upcoming patches that will handle
> > multicast registers in a special manner.
> >
> > The registers that are now replicated on Xe_HP are:
> > * PAT_INDEX (mslice replication)
> > * FF_MODE2 (gslice replication)
> > * COMMON_SLICE_CHICKEN3 (gslice replication)
> > * SLICE_COMMON_ECO_CHICKEN1 (gslice replication)
> > * SLICE_UNIT_LEVEL_CLKGATE (gslice replication)
> > * LNCFCMOCS (lncf replication)
> >
> > Bspec: 66534
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 18 ++++++++-----
> > drivers/gpu/drm/i915/gt/intel_gtt.c | 29 ++++++++++++++-------
> > drivers/gpu/drm/i915/gt/intel_mocs.c | 5 +++-
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 24 ++++++++---------
> > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 7 +++--
> > 5 files changed, 52 insertions(+), 31 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > index e5a1ea255640..559e3473f14c 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> > @@ -329,6 +329,7 @@
> > #define GEN7_TLB_RD_ADDR _MMIO(0x4700)
> >
> > #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
> > +#define XEHP_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
> >
> > #define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)
> > #define XEHP_TILE_LMEM_RANGE_SHIFT 8
> > @@ -387,7 +388,8 @@
> > #define DIS_OVER_FETCH_CACHE REG_BIT(1)
> > #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
> >
> > -#define FF_MODE2 _MMIO(0x6604)
> > +#define GEN12_FF_MODE2 _MMIO(0x6604)
> > +#define XEHP_FF_MODE2 _MMIO(0x6604)
> > #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
> > #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
> > #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
> > @@ -442,6 +444,7 @@
> > #define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
> >
> > #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> > +#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
> > #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
> > #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
> > #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
> > @@ -455,10 +458,9 @@
> > #define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
> >
> > #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> > -#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
> > -
> > -#define SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> > +#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> > #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
> > +#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
> >
> > #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4)
> > #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \
> > @@ -703,7 +705,8 @@
> > #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16)
> > #define LTCDD_CLKGATE_DIS REG_BIT(10)
> >
> > -#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> > +#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> > +#define XEHP_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> > #define SARBUNIT_CLKGATE_DIS (1 << 5)
> > #define RCCUNIT_CLKGATE_DIS (1 << 7)
> > #define MSCUNIT_CLKGATE_DIS (1 << 10)
> > @@ -718,7 +721,7 @@
> > #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
> > #define PSDUNIT_CLKGATE_DIS REG_BIT(5)
> >
> > -#define SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
> > +#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
> > #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
> > #define GWUNIT_CLKGATE_DIS REG_BIT(16)
> >
> > @@ -943,7 +946,8 @@
> >
> > /* MOCS (Memory Object Control State) registers */
> > #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
>
> GEN9_LNCFCMOCS is used in few functions in file selftest_mocs.c. This
> patch has untouched those instances. Is it by intention to handle it
> part of a separate series? If the plan is to handle it later sometime
> can we create a ticket to keep track of it?
Both of the instances there are just looking up the offset of the
register (which is the same for both the MCR and non-MCR version of the
register) and aren't doing any CPU reads/writes directly where the
multicast nature of the register would come into play. So I think it's
okay to keep using the GEN9_ version there to keep things simple. But
I'll add a note about it to the commit message.
Matt
>
> Regards,
> Bala
>
> > -#define GEN9_LNCFCMOCS_REG_COUNT 32
> > +#define XEHP_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
> > +#define LNCFCMOCS_REG_COUNT 32
> >
> > #define GEN7_L3CNTLREG3 _MMIO(0xb024)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > index b67831833c9a..601d89b4feb1 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > @@ -479,15 +479,26 @@ void gtt_write_workarounds(struct intel_gt *gt)
> >
> > static void tgl_setup_private_ppat(struct intel_uncore *uncore)
> > {
> > - /* TGL doesn't support LLC or AGE settings */
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
> > - intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
> > + if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50)) {
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
> > + } else {
> > + /* TGL doesn't support LLC or AGE settings */
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
> > + intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
> > + }
> > }
> >
> > static void icl_setup_private_ppat(struct intel_uncore *uncore)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > index c6ebe2781076..06643701bf24 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
> > @@ -608,7 +608,10 @@ static void init_l3cc_table(struct intel_uncore *uncore,
> > u32 l3cc;
> >
> > for_each_l3cc(l3cc, table, i)
> > - intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
> > + if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50))
> > + intel_uncore_write_fw(uncore, XEHP_LNCFCMOCS(i), l3cc);
> > + else
> > + intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
> > }
> >
> > void intel_mocs_init_engine(struct intel_engine_cs *engine)
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index e382cb4c6971..eff5f4f85374 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -572,7 +572,7 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> > wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
> > REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
> > wa_add(wal,
> > - FF_MODE2,
> > + XEHP_FF_MODE2,
> > FF_MODE2_TDS_TIMER_MASK,
> > FF_MODE2_TDS_TIMER_128,
> > 0, false);
> > @@ -599,7 +599,7 @@ static void gen12_ctx_gt_tuning_init(struct intel_engine_cs *engine,
> > * verification is ignored.
> > */
> > wa_add(wal,
> > - FF_MODE2,
> > + GEN12_FF_MODE2,
> > FF_MODE2_TDS_TIMER_MASK,
> > FF_MODE2_TDS_TIMER_128,
> > 0, false);
> > @@ -637,7 +637,7 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
> > * to Wa_1608008084.
> > */
> > wa_add(wal,
> > - FF_MODE2,
> > + GEN12_FF_MODE2,
> > FF_MODE2_GS_TIMER_MASK,
> > FF_MODE2_GS_TIMER_224,
> > 0, false);
> > @@ -670,7 +670,7 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> >
> > if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
> > /* Wa_14010469329:dg2_g10 */
> > - wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> > + wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
> > XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
> >
> > /*
> > @@ -678,12 +678,12 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
> > * Wa_22010613112:dg2_g10
> > * Wa_14010698770:dg2_g10
> > */
> > - wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3,
> > + wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
> > GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
> > }
> >
> > /* Wa_16013271637:dg2 */
> > - wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
> > + wa_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
> > MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
> >
> > /* Wa_14014947963:dg2 */
> > @@ -1255,14 +1255,14 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> >
> > /* Wa_1406680159:icl,ehl */
> > wa_write_or(wal,
> > - SUBSLICE_UNIT_LEVEL_CLKGATE,
> > + GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
> > GWUNIT_CLKGATE_DIS);
> >
> > /* Wa_1607087056:icl,ehl,jsl */
> > if (IS_ICELAKE(i915) ||
> > IS_JSL_EHL_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > wa_write_or(wal,
> > - SLICE_UNIT_LEVEL_CLKGATE,
> > + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> >
> > /*
> > @@ -1322,7 +1322,7 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > /* Wa_1607087056:tgl also know as BUG:1409180338 */
> > if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > wa_write_or(wal,
> > - SLICE_UNIT_LEVEL_CLKGATE,
> > + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> >
> > /* Wa_1408615072:tgl[a0] */
> > @@ -1341,7 +1341,7 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > /* Wa_1607087056:dg1 */
> > if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> > wa_write_or(wal,
> > - SLICE_UNIT_LEVEL_CLKGATE,
> > + GEN11_SLICE_UNIT_LEVEL_CLKGATE,
> > L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);
> >
> > /* Wa_1409420604:dg1 */
> > @@ -1445,7 +1445,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > CG3DDISCFEG_CLKGATE_DIS);
> >
> > /* Wa_14011006942:dg2 */
> > - wa_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE,
> > + wa_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
> > DSS_ROUTER_CLKGATE_DIS);
> > }
> >
> > @@ -1457,7 +1457,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
> > wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
> >
> > /* Wa_14011371254:dg2_g10 */
> > - wa_write_or(wal, SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
> > + wa_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
> >
> > /* Wa_14011431319:dg2_g10 */
> > wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
> > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > index 74cbe8eaf531..7d9f4f57ca95 100644
> > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
> > @@ -372,8 +372,11 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
> > false);
> >
> > /* add in local MOCS registers */
> > - for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++)
> > - ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
> > + for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
> > + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
> > + ret |= GUC_MMIO_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
> > + else
> > + ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
> >
> > return ret ? -1 : 0;
> > }
> > --
> > 2.37.3
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 03/12] drm/i915/gt: Drop a few unused register definitions
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Let's drop a few register definitions that are unused anywhere in the
driver today. Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 559e3473f14c..53bedbd5ba0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -450,13 +450,6 @@
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
-/* GEN9 chicken */
-#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
-#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
-
-#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
-#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
-
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
@@ -963,11 +956,6 @@
#define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)
#define GEN7_L3LOG_SIZE 0x80
-#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
-#define PMFLUSHDONE_LNICRSDROP (1 << 20)
-#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
-#define PMFLUSHDONE_LNEBLK (1 << 22)
-
#define XEHP_L3NODEARBCFG _MMIO(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19)
@@ -982,9 +970,6 @@
#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
-#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xb114)
-#define GEN11_I2M_WRITE_DISABLE (1 << 28)
-
#define GEN8_L3SQCREG4 _MMIO(0xb118)
#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
@@ -1179,8 +1164,6 @@
#define SARB_CHICKEN1 _MMIO(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)
-#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
-
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 03/12] drm/i915/gt: Drop a few unused register definitions
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Let's drop a few register definitions that are unused anywhere in the
driver today. Since the referenced offsets are part of what is now
considered a multicast register region, the current definitions would
not be correct for use on any future platform.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 559e3473f14c..53bedbd5ba0c 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -450,13 +450,6 @@
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
-/* GEN9 chicken */
-#define SLICE_ECO_CHICKEN0 _MMIO(0x7308)
-#define PIXEL_MASK_CAMMING_DISABLE (1 << 14)
-
-#define GEN9_SLICE_COMMON_ECO_CHICKEN0 _MMIO(0x7308)
-#define DISABLE_PIXEL_MASK_CAMMING (1 << 14)
-
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
@@ -963,11 +956,6 @@
#define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)
#define GEN7_L3LOG_SIZE 0x80
-#define GEN10_SCRATCH_LNCF2 _MMIO(0xb0a0)
-#define PMFLUSHDONE_LNICRSDROP (1 << 20)
-#define PMFLUSH_GAPL3UNBLOCK (1 << 21)
-#define PMFLUSHDONE_LNEBLK (1 << 22)
-
#define XEHP_L3NODEARBCFG _MMIO(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19)
@@ -982,9 +970,6 @@
#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
-#define GEN10_L3_CHICKEN_MODE_REGISTER _MMIO(0xb114)
-#define GEN11_I2M_WRITE_DISABLE (1 << 28)
-
#define GEN8_L3SQCREG4 _MMIO(0xb118)
#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
@@ -1179,8 +1164,6 @@
#define SARB_CHICKEN1 _MMIO(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)
-#define GEN7_HALF_SLICE_CHICKEN1_GT2 _MMIO(0xf100)
-
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
#define DOP_CLOCK_GATING_DISABLE (1 << 0)
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 04/12] drm/i915/gt: Correct prefix on a few registers
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
We have a few registers that have existed for several hardware
generations, but are only used by the driver on Xe_HP and beyond. In
cases where the Xe_HP version of the register is now replicated and uses
multicast behavior, but earlier generations were singleton, let's change
the register prefix to "XEHP_" to help clarify that we're using the
newer multicast form of the register.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++++----
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++-----
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 53bedbd5ba0c..cf87a1b36a21 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -482,7 +482,7 @@
#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
-#define GEN12_SQCM _MMIO(0x8724)
+#define XEHP_SQCM _MMIO(0x8724)
#define EN_32B_ACCESS REG_BIT(30)
#define HSW_IDICR _MMIO(0x9008)
@@ -985,7 +985,7 @@
#define GEN11_SCRATCH2 _MMIO(0xb140)
#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
-#define GEN11_L3SQCREG5 _MMIO(0xb158)
+#define XEHP_L3SQCREG5 _MMIO(0xb158)
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
#define MLTICTXCTL _MMIO(0xb170)
@@ -1041,7 +1041,7 @@
#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
#define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04)
-#define GEN12_MERT_MOD_CTRL _MMIO(0xcf28)
+#define XEHP_MERT_MOD_CTRL _MMIO(0xcf28)
#define RENDER_MOD_CTRL _MMIO(0xcf2c)
#define COMP_MOD_CTRL _MMIO(0xcf30)
#define VDBX_MOD_CTRL _MMIO(0xcf34)
@@ -1143,7 +1143,7 @@
#define EU_PERF_CNTL1 _MMIO(0xe558)
#define EU_PERF_CNTL5 _MMIO(0xe55c)
-#define GEN12_HDC_CHICKEN0 _MMIO(0xe5f0)
+#define XEHP_HDC_CHICKEN0 _MMIO(0xe5f0)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define ICL_HDC_MODE _MMIO(0xe5f4)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index eff5f4f85374..3d48189021ad 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -569,7 +569,7 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
- wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
+ wa_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
wa_add(wal,
XEHP_FF_MODE2,
@@ -1504,7 +1504,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
* recommended tuning settings documented in the bspec's
* performance guide section.
*/
- wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS);
+ wa_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
/* Wa_14015795083 */
wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
@@ -2163,7 +2163,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* Wa_22010960976:dg2
* Wa_14013347512:dg2
*/
- wa_masked_dis(wal, GEN12_HDC_CHICKEN0,
+ wa_masked_dis(wal, XEHP_HDC_CHICKEN0,
LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
}
@@ -2216,7 +2216,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012362059:dg2 */
- wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
}
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) ||
@@ -2757,7 +2757,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
}
/* Wa_14012362059:xehpsdv */
- wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
/* Wa_14014368820:xehpsdv */
wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH 04/12] drm/i915/gt: Correct prefix on a few registers
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
We have a few registers that have existed for several hardware
generations, but are only used by the driver on Xe_HP and beyond. In
cases where the Xe_HP version of the register is now replicated and uses
multicast behavior, but earlier generations were singleton, let's change
the register prefix to "XEHP_" to help clarify that we're using the
newer multicast form of the register.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++++----
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 +++++-----
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 53bedbd5ba0c..cf87a1b36a21 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -482,7 +482,7 @@
#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
-#define GEN12_SQCM _MMIO(0x8724)
+#define XEHP_SQCM _MMIO(0x8724)
#define EN_32B_ACCESS REG_BIT(30)
#define HSW_IDICR _MMIO(0x9008)
@@ -985,7 +985,7 @@
#define GEN11_SCRATCH2 _MMIO(0xb140)
#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
-#define GEN11_L3SQCREG5 _MMIO(0xb158)
+#define XEHP_L3SQCREG5 _MMIO(0xb158)
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
#define MLTICTXCTL _MMIO(0xb170)
@@ -1041,7 +1041,7 @@
#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
#define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04)
-#define GEN12_MERT_MOD_CTRL _MMIO(0xcf28)
+#define XEHP_MERT_MOD_CTRL _MMIO(0xcf28)
#define RENDER_MOD_CTRL _MMIO(0xcf2c)
#define COMP_MOD_CTRL _MMIO(0xcf30)
#define VDBX_MOD_CTRL _MMIO(0xcf34)
@@ -1143,7 +1143,7 @@
#define EU_PERF_CNTL1 _MMIO(0xe558)
#define EU_PERF_CNTL5 _MMIO(0xe55c)
-#define GEN12_HDC_CHICKEN0 _MMIO(0xe5f0)
+#define XEHP_HDC_CHICKEN0 _MMIO(0xe5f0)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define ICL_HDC_MODE _MMIO(0xe5f4)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index eff5f4f85374..3d48189021ad 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -569,7 +569,7 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
- wa_write_clr_set(wal, GEN11_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
+ wa_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
wa_add(wal,
XEHP_FF_MODE2,
@@ -1504,7 +1504,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
* recommended tuning settings documented in the bspec's
* performance guide section.
*/
- wa_write_or(wal, GEN12_SQCM, EN_32B_ACCESS);
+ wa_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
/* Wa_14015795083 */
wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
@@ -2163,7 +2163,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* Wa_22010960976:dg2
* Wa_14013347512:dg2
*/
- wa_masked_dis(wal, GEN12_HDC_CHICKEN0,
+ wa_masked_dis(wal, XEHP_HDC_CHICKEN0,
LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
}
@@ -2216,7 +2216,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012362059:dg2 */
- wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
}
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) ||
@@ -2757,7 +2757,7 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
}
/* Wa_14012362059:xehpsdv */
- wa_write_or(wal, GEN12_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
/* Wa_14014368820:xehpsdv */
wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 05/12] drm/i915/xehp: Check for faults on primary GAM
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
On Xe_HP the fault registers are now in a multicast register range.
However as part of the GAM these registers follow special rules and we
need only read from the "primary" GAM's instance to get the information
we need. So a single intel_gt_mcr_read_any() (which will automatically
steer to the primary GAM) is sufficient; we don't need to loop over each
instance of the MCR register.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 40 ++++++++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5ddae95d4886..1cb7dd40ec47 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -304,6 +304,42 @@ static void gen6_check_faults(struct intel_gt *gt)
}
}
+static void xehp_check_faults(struct intel_gt *gt)
+{
+ u32 fault;
+
+ /*
+ * Although the fault register now lives in an MCR register range,
+ * the GAM registers are special and we only truly need to read
+ * the "primary" GAM instance rather than handling each instance
+ * individually. intel_gt_mcr_read_any() will automatically steer
+ * toward the primary instance.
+ */
+ fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
+ if (fault & RING_FAULT_VALID) {
+ u32 fault_data0, fault_data1;
+ u64 fault_addr;
+
+ fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0);
+ fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1);
+
+ fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
+ ((u64)fault_data0 << 12);
+
+ drm_dbg(>->i915->drm, "Unexpected fault\n"
+ "\tAddr: 0x%08x_%08x\n"
+ "\tAddress space: %s\n"
+ "\tEngine ID: %d\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+ GEN8_RING_FAULT_ENGINE_ID(fault),
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
+ }
+}
+
static void gen8_check_faults(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
@@ -350,7 +386,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
/* From GEN8 onwards we only have one 'All Engine Fault Register' */
- if (GRAPHICS_VER(i915) >= 8)
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ xehp_check_faults(gt);
+ else if (GRAPHICS_VER(i915) >= 8)
gen8_check_faults(gt);
else if (GRAPHICS_VER(i915) >= 6)
gen6_check_faults(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index cf87a1b36a21..dff38b0c4430 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1024,11 +1024,14 @@
#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
+#define XEHP_FAULT_TLB_DATA0 _MMIO(0xceb8)
#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
+#define XEHP_FAULT_TLB_DATA1 _MMIO(0xcebc)
#define FAULT_VA_HIGH_BITS (0xf << 0)
#define FAULT_GTT_SEL (1 << 4)
#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
+#define XEHP_RING_FAULT_REG _MMIO(0xcec4)
#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
#define RING_FAULT_GTTSEL_MASK (1 << 11)
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH 05/12] drm/i915/xehp: Check for faults on primary GAM
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
On Xe_HP the fault registers are now in a multicast register range.
However as part of the GAM these registers follow special rules and we
need only read from the "primary" GAM's instance to get the information
we need. So a single intel_gt_mcr_read_any() (which will automatically
steer to the primary GAM) is sufficient; we don't need to loop over each
instance of the MCR register.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 40 ++++++++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
2 files changed, 42 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5ddae95d4886..1cb7dd40ec47 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -304,6 +304,42 @@ static void gen6_check_faults(struct intel_gt *gt)
}
}
+static void xehp_check_faults(struct intel_gt *gt)
+{
+ u32 fault;
+
+ /*
+ * Although the fault register now lives in an MCR register range,
+ * the GAM registers are special and we only truly need to read
+ * the "primary" GAM instance rather than handling each instance
+ * individually. intel_gt_mcr_read_any() will automatically steer
+ * toward the primary instance.
+ */
+ fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
+ if (fault & RING_FAULT_VALID) {
+ u32 fault_data0, fault_data1;
+ u64 fault_addr;
+
+ fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0);
+ fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1);
+
+ fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
+ ((u64)fault_data0 << 12);
+
+ drm_dbg(>->i915->drm, "Unexpected fault\n"
+ "\tAddr: 0x%08x_%08x\n"
+ "\tAddress space: %s\n"
+ "\tEngine ID: %d\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+ GEN8_RING_FAULT_ENGINE_ID(fault),
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
+ }
+}
+
static void gen8_check_faults(struct intel_gt *gt)
{
struct intel_uncore *uncore = gt->uncore;
@@ -350,7 +386,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
struct drm_i915_private *i915 = gt->i915;
/* From GEN8 onwards we only have one 'All Engine Fault Register' */
- if (GRAPHICS_VER(i915) >= 8)
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
+ xehp_check_faults(gt);
+ else if (GRAPHICS_VER(i915) >= 8)
gen8_check_faults(gt);
else if (GRAPHICS_VER(i915) >= 6)
gen6_check_faults(gt);
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index cf87a1b36a21..dff38b0c4430 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1024,11 +1024,14 @@
#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
+#define XEHP_FAULT_TLB_DATA0 _MMIO(0xceb8)
#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
+#define XEHP_FAULT_TLB_DATA1 _MMIO(0xcebc)
#define FAULT_VA_HIGH_BITS (0xf << 0)
#define FAULT_GTT_SEL (1 << 4)
#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
+#define XEHP_RING_FAULT_REG _MMIO(0xcec4)
#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
#define RING_FAULT_GTTSEL_MASK (1 << 11)
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [PATCH 05/12] drm/i915/xehp: Check for faults on primary GAM
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
(?)
@ 2022-09-26 12:28 ` Balasubramani Vivekanandan
-1 siblings, 0 replies; 40+ messages in thread
From: Balasubramani Vivekanandan @ 2022-09-26 12:28 UTC (permalink / raw)
To: Matt Roper, intel-gfx; +Cc: dri-devel
On 19.09.2022 15:32, Matt Roper wrote:
> On Xe_HP the fault registers are now in a multicast register range.
> However as part of the GAM these registers follow special rules and we
> need only read from the "primary" GAM's instance to get the information
> we need. So a single intel_gt_mcr_read_any() (which will automatically
> steer to the primary GAM) is sufficient; we don't need to loop over each
> instance of the MCR register.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 40 ++++++++++++++++++++++++-
> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 ++
> 2 files changed, 42 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 5ddae95d4886..1cb7dd40ec47 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -304,6 +304,42 @@ static void gen6_check_faults(struct intel_gt *gt)
> }
> }
>
> +static void xehp_check_faults(struct intel_gt *gt)
> +{
> + u32 fault;
> +
> + /*
> + * Although the fault register now lives in an MCR register range,
> + * the GAM registers are special and we only truly need to read
> + * the "primary" GAM instance rather than handling each instance
> + * individually. intel_gt_mcr_read_any() will automatically steer
> + * toward the primary instance.
> + */
> + fault = intel_gt_mcr_read_any(gt, XEHP_RING_FAULT_REG);
> + if (fault & RING_FAULT_VALID) {
> + u32 fault_data0, fault_data1;
> + u64 fault_addr;
> +
> + fault_data0 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA0);
> + fault_data1 = intel_gt_mcr_read_any(gt, XEHP_FAULT_TLB_DATA1);
> +
> + fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
> + ((u64)fault_data0 << 12);
> +
> + drm_dbg(>->i915->drm, "Unexpected fault\n"
> + "\tAddr: 0x%08x_%08x\n"
> + "\tAddress space: %s\n"
> + "\tEngine ID: %d\n"
> + "\tSource ID: %d\n"
> + "\tType: %d\n",
> + upper_32_bits(fault_addr), lower_32_bits(fault_addr),
> + fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
> + GEN8_RING_FAULT_ENGINE_ID(fault),
> + RING_FAULT_SRCID(fault),
> + RING_FAULT_FAULT_TYPE(fault));
> + }
> +}
> +
> static void gen8_check_faults(struct intel_gt *gt)
> {
> struct intel_uncore *uncore = gt->uncore;
> @@ -350,7 +386,9 @@ void intel_gt_check_and_clear_faults(struct intel_gt *gt)
> struct drm_i915_private *i915 = gt->i915;
>
> /* From GEN8 onwards we only have one 'All Engine Fault Register' */
> - if (GRAPHICS_VER(i915) >= 8)
> + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
> + xehp_check_faults(gt);
> + else if (GRAPHICS_VER(i915) >= 8)
> gen8_check_faults(gt);
> else if (GRAPHICS_VER(i915) >= 6)
> gen6_check_faults(gt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index cf87a1b36a21..dff38b0c4430 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -1024,11 +1024,14 @@
> #define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
>
> #define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
> +#define XEHP_FAULT_TLB_DATA0 _MMIO(0xceb8)
> #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
> +#define XEHP_FAULT_TLB_DATA1 _MMIO(0xcebc)
> #define FAULT_VA_HIGH_BITS (0xf << 0)
> #define FAULT_GTT_SEL (1 << 4)
>
> #define GEN12_RING_FAULT_REG _MMIO(0xcec4)
> +#define XEHP_RING_FAULT_REG _MMIO(0xcec4)
The fault registers GEN12_FAULT_TLB_DATA0, GEN12_FAULT_TLB_DATA1,
GEN12_RING_FAULT_REG are used in few other places in the driver for
platforms including Xe_HP. Don't we need to take care of them?
Regards,
Bala
> #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
> #define RING_FAULT_GTTSEL_MASK (1 << 11)
> #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
> --
> 2.37.3
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH 06/12] drm/i915: Define MCR registers explicitly
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Rather than using the same _MMIO() macro to define MCR registers as
singleton registers, let's use a new MCR_REG() macro to make it clear
that these registers are special and should be handled accordingly. For
now MCR_REG() will still generate an i915_reg_t with the given offset,
but we'll change that in future patches.
Bspec: 66673, 66696, 66534, 67609
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 124 ++++++++++++------------
1 file changed, 63 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index dff38b0c4430..f96cf08cd31e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -8,6 +8,8 @@
#include "i915_reg_defs.h"
+#define MCR_REG(offset) _MMIO(offset)
+
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
@@ -329,12 +331,12 @@
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
-#define XEHP_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
+#define XEHP_PAT_INDEX(index) MCR_REG(0x4800 + (index) * 4)
-#define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)
+#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
#define XEHP_TILE_LMEM_RANGE_SHIFT 8
-#define XEHP_FLAT_CCS_BASE_ADDR _MMIO(0x4910)
+#define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
#define XEHP_CCS_BASE_SHIFT 8
#define GAMTARBMODE _MMIO(0x4a08)
@@ -384,18 +386,18 @@
#define CHICKEN_RASTER_2 _MMIO(0x6208)
#define TBIMR_FAST_CLIP REG_BIT(5)
-#define VFLSKPD _MMIO(0x62a8)
+#define VFLSKPD MCR_REG(0x62a8)
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
#define GEN12_FF_MODE2 _MMIO(0x6604)
-#define XEHP_FF_MODE2 _MMIO(0x6604)
+#define XEHP_FF_MODE2 MCR_REG(0x6604)
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
-#define XEHPG_INSTDONE_GEOM_SVG _MMIO(0x666c)
+#define XEHPG_INSTDONE_GEOM_SVG MCR_REG(0x666c)
#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
#define RC_OP_FLUSH_ENABLE (1 << 0)
@@ -444,14 +446,14 @@
#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
-#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
-#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
@@ -482,7 +484,7 @@
#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
-#define XEHP_SQCM _MMIO(0x8724)
+#define XEHP_SQCM MCR_REG(0x8724)
#define EN_32B_ACCESS REG_BIT(30)
#define HSW_IDICR _MMIO(0x9008)
@@ -643,7 +645,7 @@
#define GEN7_MISCCPCTL _MMIO(0x9424)
#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
-#define GEN8_MISCCPCTL _MMIO(0x9424)
+#define GEN8_MISCCPCTL MCR_REG(0x9424)
#define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
@@ -699,7 +701,7 @@
#define LTCDD_CLKGATE_DIS REG_BIT(10)
#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
-#define XEHP_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
+#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
#define RCCUNIT_CLKGATE_DIS (1 << 7)
#define MSCUNIT_CLKGATE_DIS (1 << 10)
@@ -707,27 +709,27 @@
#define L3_CLKGATE_DIS REG_BIT(16)
#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
-#define SCCGCTL94DC _MMIO(0x94dc)
+#define SCCGCTL94DC MCR_REG(0x94dc)
#define CG3DDISURB REG_BIT(14)
#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
-#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
+#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
#define GWUNIT_CLKGATE_DIS REG_BIT(16)
-#define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528)
+#define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528)
#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
-#define SSMCGCTL9530 _MMIO(0x9530)
+#define SSMCGCTL9530 MCR_REG(0x9530)
#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
-#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
#define DFR_DISABLE (1 << 9)
-#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
+#define INF_UNIT_LEVEL_CLKGATE MCR_REG(0x9560)
#define CGPSF_CLKGATE_DIS (1 << 3)
#define MICRO_BP0_0 _MMIO(0x9800)
@@ -939,7 +941,7 @@
/* MOCS (Memory Object Control State) registers */
#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
-#define XEHP_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
+#define XEHP_LNCFCMOCS(i) MCR_REG(0xb020 + (i) * 4) /* L3 Cache Control */
#define LNCFCMOCS_REG_COUNT 32
#define GEN7_L3CNTLREG3 _MMIO(0xb024)
@@ -956,10 +958,10 @@
#define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)
#define GEN7_L3LOG_SIZE 0x80
-#define XEHP_L3NODEARBCFG _MMIO(0xb0b4)
+#define XEHP_L3NODEARBCFG MCR_REG(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19)
-#define GEN8_L3SQCREG1 _MMIO(0xb100)
+#define GEN8_L3SQCREG1 MCR_REG(0xb100)
/*
* Note that on CHV the following has an off-by-one error wrt. to BSpec.
* Using the formula in BSpec leads to a hang, while the formula here works
@@ -970,28 +972,28 @@
#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
-#define GEN8_L3SQCREG4 _MMIO(0xb118)
+#define GEN8_L3SQCREG4 MCR_REG(0xb118)
#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
-#define GEN9_SCRATCH1 _MMIO(0xb11c)
+#define GEN9_SCRATCH1 MCR_REG(0xb11c)
#define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
-#define BDW_SCRATCH1 _MMIO(0xb11c)
+#define BDW_SCRATCH1 MCR_REG(0xb11c)
#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
-#define GEN11_SCRATCH2 _MMIO(0xb140)
+#define GEN11_SCRATCH2 MCR_REG(0xb140)
#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
-#define XEHP_L3SQCREG5 _MMIO(0xb158)
+#define XEHP_L3SQCREG5 MCR_REG(0xb158)
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
-#define MLTICTXCTL _MMIO(0xb170)
+#define MLTICTXCTL MCR_REG(0xb170)
#define TDONRENDER REG_BIT(2)
-#define XEHP_L3SCQREG7 _MMIO(0xb188)
+#define XEHP_L3SCQREG7 MCR_REG(0xb188)
#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
#define XEHPC_L3SCRUB _MMIO(0xb18c)
@@ -999,7 +1001,7 @@
#define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
#define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
-#define L3SQCREG1_CCS0 _MMIO(0xb200)
+#define L3SQCREG1_CCS0 MCR_REG(0xb200)
#define FLUSHALLNONCOH REG_BIT(5)
#define GEN11_GLBLINVL _MMIO(0xb404)
@@ -1024,14 +1026,14 @@
#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
-#define XEHP_FAULT_TLB_DATA0 _MMIO(0xceb8)
+#define XEHP_FAULT_TLB_DATA0 MCR_REG(0xceb8)
#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
-#define XEHP_FAULT_TLB_DATA1 _MMIO(0xcebc)
+#define XEHP_FAULT_TLB_DATA1 MCR_REG(0xcebc)
#define FAULT_VA_HIGH_BITS (0xf << 0)
#define FAULT_GTT_SEL (1 << 4)
#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
-#define XEHP_RING_FAULT_REG _MMIO(0xcec4)
+#define XEHP_RING_FAULT_REG MCR_REG(0xcec4)
#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
#define RING_FAULT_GTTSEL_MASK (1 << 11)
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
@@ -1044,11 +1046,11 @@
#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
#define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04)
-#define XEHP_MERT_MOD_CTRL _MMIO(0xcf28)
-#define RENDER_MOD_CTRL _MMIO(0xcf2c)
-#define COMP_MOD_CTRL _MMIO(0xcf30)
-#define VDBX_MOD_CTRL _MMIO(0xcf34)
-#define VEBX_MOD_CTRL _MMIO(0xcf38)
+#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28)
+#define RENDER_MOD_CTRL MCR_REG(0xcf2c)
+#define COMP_MOD_CTRL MCR_REG(0xcf30)
+#define VDBX_MOD_CTRL MCR_REG(0xcf34)
+#define VEBX_MOD_CTRL MCR_REG(0xcf38)
#define FORCE_MISS_FTLB REG_BIT(3)
#define GEN12_GAMSTLB_CTRL _MMIO(0xcf4c)
@@ -1063,52 +1065,52 @@
#define GEN12_GAM_DONE _MMIO(0xcf68)
#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
-#define GEN8_HALF_SLICE_CHICKEN1 _MMIO(0xe100)
+#define GEN8_HALF_SLICE_CHICKEN1 MCR_REG(0xe100)
#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
-#define GEN8_SAMPLER_INSTDONE _MMIO(0xe160)
+#define GEN8_SAMPLER_INSTDONE MCR_REG(0xe160)
#define GEN7_ROW_INSTDONE _MMIO(0xe164)
-#define GEN8_ROW_INSTDONE _MMIO(0xe164)
+#define GEN8_ROW_INSTDONE MCR_REG(0xe164)
-#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
+#define HALF_SLICE_CHICKEN2 MCR_REG(0xe180)
#define GEN8_ST_PO_DISABLE (1 << 13)
#define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
-#define GEN8_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
+#define GEN8_HALF_SLICE_CHICKEN3 MCR_REG(0xe184)
#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
-#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
+#define GEN9_HALF_SLICE_CHICKEN5 MCR_REG(0xe188)
#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
-#define GEN10_SAMPLER_MODE _MMIO(0xe18c)
+#define GEN10_SAMPLER_MODE MCR_REG(0xe18c)
#define ENABLE_SMALLPL REG_BIT(15)
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
-#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
+#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR REG_BIT(8)
#define GEN9_ENABLE_YV12_BUGFIX REG_BIT(4)
#define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2)
-#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
+#define GEN10_CACHE_MODE_SS MCR_REG(0xe420)
#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
#define DISABLE_ECC REG_BIT(5)
#define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
-#define EU_PERF_CNTL0 _MMIO(0xe458)
-#define EU_PERF_CNTL4 _MMIO(0xe45c)
+#define EU_PERF_CNTL0 MCR_REG(0xe458)
+#define EU_PERF_CNTL4 MCR_REG(0xe45c)
-#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
+#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
@@ -1120,7 +1122,7 @@
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
-#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
+#define GEN8_ROW_CHICKEN MCR_REG(0xe4f0)
#define FLOW_CONTROL_ENABLE REG_BIT(15)
#define UGM_BACKUP_MODE REG_BIT(13)
#define MDQ_ARBITRATION_MODE REG_BIT(12)
@@ -1132,39 +1134,39 @@
#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
-#define GEN8_ROW_CHICKEN2 _MMIO(0xe4f4)
+#define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4)
#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
-#define RT_CTRL _MMIO(0xe530)
+#define RT_CTRL MCR_REG(0xe530)
#define DIS_NULL_QUERY REG_BIT(10)
#define STACKID_CTRL REG_GENMASK(6, 5)
#define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2)
-#define EU_PERF_CNTL1 _MMIO(0xe558)
-#define EU_PERF_CNTL5 _MMIO(0xe55c)
+#define EU_PERF_CNTL1 MCR_REG(0xe558)
+#define EU_PERF_CNTL5 MCR_REG(0xe55c)
-#define XEHP_HDC_CHICKEN0 _MMIO(0xe5f0)
+#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
-#define ICL_HDC_MODE _MMIO(0xe5f4)
+#define ICL_HDC_MODE MCR_REG(0xe5f4)
-#define EU_PERF_CNTL2 _MMIO(0xe658)
-#define EU_PERF_CNTL6 _MMIO(0xe65c)
-#define EU_PERF_CNTL3 _MMIO(0xe758)
+#define EU_PERF_CNTL2 MCR_REG(0xe658)
+#define EU_PERF_CNTL6 MCR_REG(0xe65c)
+#define EU_PERF_CNTL3 MCR_REG(0xe758)
-#define LSC_CHICKEN_BIT_0 _MMIO(0xe7c8)
+#define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8)
#define DISABLE_D8_D16_COASLESCE REG_BIT(30)
#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
-#define LSC_CHICKEN_BIT_0_UDW _MMIO(0xe7c8 + 4)
+#define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4)
#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
-#define SARB_CHICKEN1 _MMIO(0xe90c)
+#define SARB_CHICKEN1 MCR_REG(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH 06/12] drm/i915: Define MCR registers explicitly
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Rather than using the same _MMIO() macro to define MCR registers as
singleton registers, let's use a new MCR_REG() macro to make it clear
that these registers are special and should be handled accordingly. For
now MCR_REG() will still generate an i915_reg_t with the given offset,
but we'll change that in future patches.
Bspec: 66673, 66696, 66534, 67609
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 124 ++++++++++++------------
1 file changed, 63 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index dff38b0c4430..f96cf08cd31e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -8,6 +8,8 @@
#include "i915_reg_defs.h"
+#define MCR_REG(offset) _MMIO(offset)
+
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
#define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3
@@ -329,12 +331,12 @@
#define GEN7_TLB_RD_ADDR _MMIO(0x4700)
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
-#define XEHP_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)
+#define XEHP_PAT_INDEX(index) MCR_REG(0x4800 + (index) * 4)
-#define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)
+#define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900)
#define XEHP_TILE_LMEM_RANGE_SHIFT 8
-#define XEHP_FLAT_CCS_BASE_ADDR _MMIO(0x4910)
+#define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910)
#define XEHP_CCS_BASE_SHIFT 8
#define GAMTARBMODE _MMIO(0x4a08)
@@ -384,18 +386,18 @@
#define CHICKEN_RASTER_2 _MMIO(0x6208)
#define TBIMR_FAST_CLIP REG_BIT(5)
-#define VFLSKPD _MMIO(0x62a8)
+#define VFLSKPD MCR_REG(0x62a8)
#define DIS_OVER_FETCH_CACHE REG_BIT(1)
#define DIS_MULT_MISS_RD_SQUASH REG_BIT(0)
#define GEN12_FF_MODE2 _MMIO(0x6604)
-#define XEHP_FF_MODE2 _MMIO(0x6604)
+#define XEHP_FF_MODE2 MCR_REG(0x6604)
#define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24)
#define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
-#define XEHPG_INSTDONE_GEOM_SVG _MMIO(0x666c)
+#define XEHPG_INSTDONE_GEOM_SVG MCR_REG(0x666c)
#define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */
#define RC_OP_FLUSH_ENABLE (1 << 0)
@@ -444,14 +446,14 @@
#define GEN8_HDC_CHICKEN1 _MMIO(0x7304)
#define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
-#define XEHP_COMMON_SLICE_CHICKEN3 _MMIO(0x7304)
+#define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304)
#define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12)
#define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12)
#define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11)
#define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9)
#define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
-#define XEHP_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
+#define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c)
#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
#define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
@@ -482,7 +484,7 @@
#define GEN8_RC6_CTX_INFO _MMIO(0x8504)
-#define XEHP_SQCM _MMIO(0x8724)
+#define XEHP_SQCM MCR_REG(0x8724)
#define EN_32B_ACCESS REG_BIT(30)
#define HSW_IDICR _MMIO(0x9008)
@@ -643,7 +645,7 @@
#define GEN7_MISCCPCTL _MMIO(0x9424)
#define GEN7_DOP_CLOCK_GATE_ENABLE (1 << 0)
-#define GEN8_MISCCPCTL _MMIO(0x9424)
+#define GEN8_MISCCPCTL MCR_REG(0x9424)
#define GEN8_DOP_CLOCK_GATE_ENABLE REG_BIT(0)
#define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1)
#define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2)
@@ -699,7 +701,7 @@
#define LTCDD_CLKGATE_DIS REG_BIT(10)
#define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
-#define XEHP_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
+#define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4)
#define SARBUNIT_CLKGATE_DIS (1 << 5)
#define RCCUNIT_CLKGATE_DIS (1 << 7)
#define MSCUNIT_CLKGATE_DIS (1 << 10)
@@ -707,27 +709,27 @@
#define L3_CLKGATE_DIS REG_BIT(16)
#define L3_CR2X_CLKGATE_DIS REG_BIT(17)
-#define SCCGCTL94DC _MMIO(0x94dc)
+#define SCCGCTL94DC MCR_REG(0x94dc)
#define CG3DDISURB REG_BIT(14)
#define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4)
#define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19)
#define PSDUNIT_CLKGATE_DIS REG_BIT(5)
-#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9524)
+#define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524)
#define DSS_ROUTER_CLKGATE_DIS REG_BIT(28)
#define GWUNIT_CLKGATE_DIS REG_BIT(16)
-#define SUBSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x9528)
+#define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528)
#define CPSSUNIT_CLKGATE_DIS REG_BIT(9)
-#define SSMCGCTL9530 _MMIO(0x9530)
+#define SSMCGCTL9530 MCR_REG(0x9530)
#define RTFUNIT_CLKGATE_DIS REG_BIT(18)
-#define GEN10_DFR_RATIO_EN_AND_CHICKEN _MMIO(0x9550)
+#define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550)
#define DFR_DISABLE (1 << 9)
-#define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560)
+#define INF_UNIT_LEVEL_CLKGATE MCR_REG(0x9560)
#define CGPSF_CLKGATE_DIS (1 << 3)
#define MICRO_BP0_0 _MMIO(0x9800)
@@ -939,7 +941,7 @@
/* MOCS (Memory Object Control State) registers */
#define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
-#define XEHP_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */
+#define XEHP_LNCFCMOCS(i) MCR_REG(0xb020 + (i) * 4) /* L3 Cache Control */
#define LNCFCMOCS_REG_COUNT 32
#define GEN7_L3CNTLREG3 _MMIO(0xb024)
@@ -956,10 +958,10 @@
#define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4)
#define GEN7_L3LOG_SIZE 0x80
-#define XEHP_L3NODEARBCFG _MMIO(0xb0b4)
+#define XEHP_L3NODEARBCFG MCR_REG(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19)
-#define GEN8_L3SQCREG1 _MMIO(0xb100)
+#define GEN8_L3SQCREG1 MCR_REG(0xb100)
/*
* Note that on CHV the following has an off-by-one error wrt. to BSpec.
* Using the formula in BSpec leads to a hang, while the formula here works
@@ -970,28 +972,28 @@
#define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14)
#define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14))
-#define GEN8_L3SQCREG4 _MMIO(0xb118)
+#define GEN8_L3SQCREG4 MCR_REG(0xb118)
#define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6)
#define GEN8_LQSC_RO_PERF_DIS (1 << 27)
#define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21)
#define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22)
-#define GEN9_SCRATCH1 _MMIO(0xb11c)
+#define GEN9_SCRATCH1 MCR_REG(0xb11c)
#define EVICTION_PERF_FIX_ENABLE REG_BIT(8)
-#define BDW_SCRATCH1 _MMIO(0xb11c)
+#define BDW_SCRATCH1 MCR_REG(0xb11c)
#define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2)
-#define GEN11_SCRATCH2 _MMIO(0xb140)
+#define GEN11_SCRATCH2 MCR_REG(0xb140)
#define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19)
-#define XEHP_L3SQCREG5 _MMIO(0xb158)
+#define XEHP_L3SQCREG5 MCR_REG(0xb158)
#define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0)
-#define MLTICTXCTL _MMIO(0xb170)
+#define MLTICTXCTL MCR_REG(0xb170)
#define TDONRENDER REG_BIT(2)
-#define XEHP_L3SCQREG7 _MMIO(0xb188)
+#define XEHP_L3SCQREG7 MCR_REG(0xb188)
#define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3)
#define XEHPC_L3SCRUB _MMIO(0xb18c)
@@ -999,7 +1001,7 @@
#define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0)
#define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6)
-#define L3SQCREG1_CCS0 _MMIO(0xb200)
+#define L3SQCREG1_CCS0 MCR_REG(0xb200)
#define FLUSHALLNONCOH REG_BIT(5)
#define GEN11_GLBLINVL _MMIO(0xb404)
@@ -1024,14 +1026,14 @@
#define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4)
#define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8)
-#define XEHP_FAULT_TLB_DATA0 _MMIO(0xceb8)
+#define XEHP_FAULT_TLB_DATA0 MCR_REG(0xceb8)
#define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc)
-#define XEHP_FAULT_TLB_DATA1 _MMIO(0xcebc)
+#define XEHP_FAULT_TLB_DATA1 MCR_REG(0xcebc)
#define FAULT_VA_HIGH_BITS (0xf << 0)
#define FAULT_GTT_SEL (1 << 4)
#define GEN12_RING_FAULT_REG _MMIO(0xcec4)
-#define XEHP_RING_FAULT_REG _MMIO(0xcec4)
+#define XEHP_RING_FAULT_REG MCR_REG(0xcec4)
#define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7)
#define RING_FAULT_GTTSEL_MASK (1 << 11)
#define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff)
@@ -1044,11 +1046,11 @@
#define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4)
#define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04)
-#define XEHP_MERT_MOD_CTRL _MMIO(0xcf28)
-#define RENDER_MOD_CTRL _MMIO(0xcf2c)
-#define COMP_MOD_CTRL _MMIO(0xcf30)
-#define VDBX_MOD_CTRL _MMIO(0xcf34)
-#define VEBX_MOD_CTRL _MMIO(0xcf38)
+#define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28)
+#define RENDER_MOD_CTRL MCR_REG(0xcf2c)
+#define COMP_MOD_CTRL MCR_REG(0xcf30)
+#define VDBX_MOD_CTRL MCR_REG(0xcf34)
+#define VEBX_MOD_CTRL MCR_REG(0xcf38)
#define FORCE_MISS_FTLB REG_BIT(3)
#define GEN12_GAMSTLB_CTRL _MMIO(0xcf4c)
@@ -1063,52 +1065,52 @@
#define GEN12_GAM_DONE _MMIO(0xcf68)
#define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */
-#define GEN8_HALF_SLICE_CHICKEN1 _MMIO(0xe100)
+#define GEN8_HALF_SLICE_CHICKEN1 MCR_REG(0xe100)
#define GEN7_MAX_PS_THREAD_DEP (8 << 12)
#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10)
#define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4)
#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3)
#define GEN7_SAMPLER_INSTDONE _MMIO(0xe160)
-#define GEN8_SAMPLER_INSTDONE _MMIO(0xe160)
+#define GEN8_SAMPLER_INSTDONE MCR_REG(0xe160)
#define GEN7_ROW_INSTDONE _MMIO(0xe164)
-#define GEN8_ROW_INSTDONE _MMIO(0xe164)
+#define GEN8_ROW_INSTDONE MCR_REG(0xe164)
-#define HALF_SLICE_CHICKEN2 _MMIO(0xe180)
+#define HALF_SLICE_CHICKEN2 MCR_REG(0xe180)
#define GEN8_ST_PO_DISABLE (1 << 13)
#define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
-#define GEN8_HALF_SLICE_CHICKEN3 _MMIO(0xe184)
+#define GEN8_HALF_SLICE_CHICKEN3 MCR_REG(0xe184)
#define HSW_SAMPLE_C_PERFORMANCE (1 << 9)
#define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8)
#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5)
#define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1)
-#define GEN9_HALF_SLICE_CHICKEN5 _MMIO(0xe188)
+#define GEN9_HALF_SLICE_CHICKEN5 MCR_REG(0xe188)
#define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5)
#define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3)
-#define GEN10_SAMPLER_MODE _MMIO(0xe18c)
+#define GEN10_SAMPLER_MODE MCR_REG(0xe18c)
#define ENABLE_SMALLPL REG_BIT(15)
#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9)
#define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5)
-#define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194)
+#define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194)
#define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15)
#define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR REG_BIT(8)
#define GEN9_ENABLE_YV12_BUGFIX REG_BIT(4)
#define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2)
-#define GEN10_CACHE_MODE_SS _MMIO(0xe420)
+#define GEN10_CACHE_MODE_SS MCR_REG(0xe420)
#define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10)
#define DISABLE_ECC REG_BIT(5)
#define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
-#define EU_PERF_CNTL0 _MMIO(0xe458)
-#define EU_PERF_CNTL4 _MMIO(0xe45c)
+#define EU_PERF_CNTL0 MCR_REG(0xe458)
+#define EU_PERF_CNTL4 MCR_REG(0xe45c)
-#define GEN9_ROW_CHICKEN4 _MMIO(0xe48c)
+#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
#define XEHP_DIS_BBL_SYSPIPE REG_BIT(11)
#define GEN12_DISABLE_TDL_PUSH REG_BIT(9)
@@ -1120,7 +1122,7 @@
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
-#define GEN8_ROW_CHICKEN _MMIO(0xe4f0)
+#define GEN8_ROW_CHICKEN MCR_REG(0xe4f0)
#define FLOW_CONTROL_ENABLE REG_BIT(15)
#define UGM_BACKUP_MODE REG_BIT(13)
#define MDQ_ARBITRATION_MODE REG_BIT(12)
@@ -1132,39 +1134,39 @@
#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
-#define GEN8_ROW_CHICKEN2 _MMIO(0xe4f4)
+#define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4)
#define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15)
#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
#define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12)
#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
-#define RT_CTRL _MMIO(0xe530)
+#define RT_CTRL MCR_REG(0xe530)
#define DIS_NULL_QUERY REG_BIT(10)
#define STACKID_CTRL REG_GENMASK(6, 5)
#define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2)
-#define EU_PERF_CNTL1 _MMIO(0xe558)
-#define EU_PERF_CNTL5 _MMIO(0xe55c)
+#define EU_PERF_CNTL1 MCR_REG(0xe558)
+#define EU_PERF_CNTL5 MCR_REG(0xe55c)
-#define XEHP_HDC_CHICKEN0 _MMIO(0xe5f0)
+#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
-#define ICL_HDC_MODE _MMIO(0xe5f4)
+#define ICL_HDC_MODE MCR_REG(0xe5f4)
-#define EU_PERF_CNTL2 _MMIO(0xe658)
-#define EU_PERF_CNTL6 _MMIO(0xe65c)
-#define EU_PERF_CNTL3 _MMIO(0xe758)
+#define EU_PERF_CNTL2 MCR_REG(0xe658)
+#define EU_PERF_CNTL6 MCR_REG(0xe65c)
+#define EU_PERF_CNTL3 MCR_REG(0xe758)
-#define LSC_CHICKEN_BIT_0 _MMIO(0xe7c8)
+#define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8)
#define DISABLE_D8_D16_COASLESCE REG_BIT(30)
#define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15)
-#define LSC_CHICKEN_BIT_0_UDW _MMIO(0xe7c8 + 4)
+#define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4)
#define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32)
#define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32)
#define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32)
#define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32)
#define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32)
-#define SARB_CHICKEN1 _MMIO(0xe90c)
+#define SARB_CHICKEN1 MCR_REG(0xe90c)
#define COMP_CKN_IN REG_GENMASK(30, 29)
#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 07/12] drm/i915/gt: Always use MCR functions on multicast registers
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Rather than relying on the implicit behavior of intel_uncore_*()
functions, let's always use the intel_gt_mcr_*() functions to operate on
multicast/replicated registers.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 49 ++++++++++++-----------
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 13 +++---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 12 ++++--
drivers/gpu/drm/i915/intel_pm.c | 20 +++++----
6 files changed, 55 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 30cf5c3369d9..e2620f41d8b2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -986,7 +986,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
- setup_private_pat(ggtt->vm.gt->uncore);
+ setup_private_pat(ggtt->vm.gt);
return ggtt_probe_common(ggtt, size);
}
@@ -1302,7 +1302,7 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
wbinvd_on_all_cpus();
if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
- setup_private_pat(ggtt->vm.gt->uncore);
+ setup_private_pat(ggtt->vm.gt);
intel_ggtt_restore_fences(ggtt);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 601d89b4feb1..6f61c8da0b61 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -15,6 +15,7 @@
#include "i915_trace.h"
#include "i915_utils.h"
#include "intel_gt.h"
+#include "intel_gt_mcr.h"
#include "intel_gt_regs.h"
#include "intel_gtt.h"
@@ -477,27 +478,27 @@ void gtt_write_workarounds(struct intel_gt *gt)
}
}
-static void tgl_setup_private_ppat(struct intel_uncore *uncore)
+static void tgl_setup_private_ppat(struct intel_gt *gt)
{
- if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50)) {
- intel_uncore_write(uncore, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
} else {
/* TGL doesn't support LLC or AGE settings */
- intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
}
}
@@ -593,20 +594,20 @@ static void chv_setup_private_ppat(struct intel_uncore *uncore)
intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
}
-void setup_private_pat(struct intel_uncore *uncore)
+void setup_private_pat(struct intel_gt *gt)
{
- struct drm_i915_private *i915 = uncore->i915;
+ struct drm_i915_private *i915 = gt->i915;
GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
if (GRAPHICS_VER(i915) >= 12)
- tgl_setup_private_ppat(uncore);
+ tgl_setup_private_ppat(gt);
else if (GRAPHICS_VER(i915) >= 11)
- icl_setup_private_ppat(uncore);
+ icl_setup_private_ppat(gt->uncore);
else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
- chv_setup_private_ppat(uncore);
+ chv_setup_private_ppat(gt->uncore);
else
- bdw_setup_private_ppat(uncore);
+ bdw_setup_private_ppat(gt->uncore);
}
struct i915_vma *
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index c0ca53cba9f0..5236c60f2a68 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -667,7 +667,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
void gtt_write_workarounds(struct intel_gt *gt);
-void setup_private_pat(struct intel_uncore *uncore);
+void setup_private_pat(struct intel_gt *gt);
int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
struct i915_vm_pt_stash *stash,
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 06643701bf24..89ef1e06bf1d 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -7,6 +7,7 @@
#include "intel_engine.h"
#include "intel_gt.h"
+#include "intel_gt_mcr.h"
#include "intel_gt_regs.h"
#include "intel_mocs.h"
#include "intel_ring.h"
@@ -601,17 +602,17 @@ static u32 l3cc_combine(u16 low, u16 high)
0; \
i++)
-static void init_l3cc_table(struct intel_uncore *uncore,
+static void init_l3cc_table(struct intel_gt *gt,
const struct drm_i915_mocs_table *table)
{
unsigned int i;
u32 l3cc;
for_each_l3cc(l3cc, table, i)
- if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50))
- intel_uncore_write_fw(uncore, XEHP_LNCFCMOCS(i), l3cc);
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
+ intel_gt_mcr_multicast_write_fw(gt, XEHP_LNCFCMOCS(i), l3cc);
else
- intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
+ intel_uncore_write_fw(gt->uncore, GEN9_LNCFCMOCS(i), l3cc);
}
void intel_mocs_init_engine(struct intel_engine_cs *engine)
@@ -631,7 +632,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
init_mocs_table(engine, &table);
if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
- init_l3cc_table(engine->uncore, &table);
+ init_l3cc_table(engine->gt, &table);
}
static u32 global_mocs_offset(void)
@@ -667,7 +668,7 @@ void intel_mocs_init(struct intel_gt *gt)
* memory transactions including guc transactions
*/
if (flags & HAS_RENDER_L3CC)
- init_l3cc_table(gt->uncore, &table);
+ init_l3cc_table(gt, &table);
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 9229243992c2..5b86b2e286e0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -10,12 +10,15 @@
*/
#include "gt/intel_gt.h"
+#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
#include "intel_guc_fw.h"
#include "i915_drv.h"
-static void guc_prepare_xfer(struct intel_uncore *uncore)
+static void guc_prepare_xfer(struct intel_gt *gt)
{
+ struct intel_uncore *uncore = gt->uncore;
+
u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
@@ -35,8 +38,9 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
if (GRAPHICS_VER(uncore->i915) == 9) {
/* DOP Clock Gating Enable for GuC clocks */
- intel_uncore_rmw(uncore, GEN8_MISCCPCTL,
- 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
+ intel_gt_mcr_multicast_write(gt, GEN8_MISCCPCTL,
+ GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
+ intel_gt_mcr_read_any(gt, GEN8_MISCCPCTL));
/* allows for 5us (in 10ns units) before GT can go to RC6 */
intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
@@ -168,7 +172,7 @@ int intel_guc_fw_upload(struct intel_guc *guc)
struct intel_uncore *uncore = gt->uncore;
int ret;
- guc_prepare_xfer(uncore);
+ guc_prepare_xfer(gt);
/*
* Note that GuC needs the CSS header plus uKernel code to be copied
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1aa77b18fd3c..fd1286d1908c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -30,6 +30,8 @@
#include "display/skl_watermark.h"
#include "gt/intel_engine_regs.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
#include "i915_drv.h"
@@ -4325,22 +4327,23 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
u32 val;
/* WaTempDisableDOPClkGating:bdw */
- misccpctl = intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL);
- intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);
+ misccpctl = intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_MISCCPCTL);
+ intel_gt_mcr_multicast_write(to_gt(dev_priv), GEN8_MISCCPCTL,
+ misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);
- val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
+ val = intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_L3SQCREG1);
val &= ~L3_PRIO_CREDITS_MASK;
val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
- intel_uncore_write(&dev_priv->uncore, GEN8_L3SQCREG1, val);
+ intel_gt_mcr_multicast_write(to_gt(dev_priv), GEN8_L3SQCREG1, val);
/*
* Wait at least 100 clocks before re-enabling clock gating.
* See the definition of L3SQCREG1 in BSpec.
*/
- intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
+ intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_L3SQCREG1);
udelay(1);
- intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl);
+ intel_gt_mcr_multicast_write(to_gt(dev_priv), GEN8_MISCCPCTL, misccpctl);
}
static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -4500,8 +4503,9 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
gen9_init_clock_gating(dev_priv);
/* WaDisableDopClockGating:skl */
- intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL) &
- ~GEN8_DOP_CLOCK_GATE_ENABLE);
+ intel_gt_mcr_multicast_write(to_gt(dev_priv), GEN8_MISCCPCTL,
+ intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_MISCCPCTL) &
+ ~GEN8_DOP_CLOCK_GATE_ENABLE);
/* WAC6entrylatency:skl */
intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH 07/12] drm/i915/gt: Always use MCR functions on multicast registers
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Rather than relying on the implicit behavior of intel_uncore_*()
functions, let's always use the intel_gt_mcr_*() functions to operate on
multicast/replicated registers.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 49 ++++++++++++-----------
drivers/gpu/drm/i915/gt/intel_gtt.h | 2 +-
drivers/gpu/drm/i915/gt/intel_mocs.c | 13 +++---
drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c | 12 ++++--
drivers/gpu/drm/i915/intel_pm.c | 20 +++++----
6 files changed, 55 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 30cf5c3369d9..e2620f41d8b2 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -986,7 +986,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
- setup_private_pat(ggtt->vm.gt->uncore);
+ setup_private_pat(ggtt->vm.gt);
return ggtt_probe_common(ggtt, size);
}
@@ -1302,7 +1302,7 @@ void i915_ggtt_resume(struct i915_ggtt *ggtt)
wbinvd_on_all_cpus();
if (GRAPHICS_VER(ggtt->vm.i915) >= 8)
- setup_private_pat(ggtt->vm.gt->uncore);
+ setup_private_pat(ggtt->vm.gt);
intel_ggtt_restore_fences(ggtt);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 601d89b4feb1..6f61c8da0b61 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -15,6 +15,7 @@
#include "i915_trace.h"
#include "i915_utils.h"
#include "intel_gt.h"
+#include "intel_gt_mcr.h"
#include "intel_gt_regs.h"
#include "intel_gtt.h"
@@ -477,27 +478,27 @@ void gtt_write_workarounds(struct intel_gt *gt)
}
}
-static void tgl_setup_private_ppat(struct intel_uncore *uncore)
+static void tgl_setup_private_ppat(struct intel_gt *gt)
{
- if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50)) {
- intel_uncore_write(uncore, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
- intel_uncore_write(uncore, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(0), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(1), GEN8_PPAT_WC);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(2), GEN8_PPAT_WT);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(3), GEN8_PPAT_UC);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(4), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(5), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(6), GEN8_PPAT_WB);
+ intel_gt_mcr_multicast_write(gt, XEHP_PAT_INDEX(7), GEN8_PPAT_WB);
} else {
/* TGL doesn't support LLC or AGE settings */
- intel_uncore_write(uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
- intel_uncore_write(uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(0), GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(1), GEN8_PPAT_WC);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(2), GEN8_PPAT_WT);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(3), GEN8_PPAT_UC);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(4), GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(5), GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(6), GEN8_PPAT_WB);
+ intel_uncore_write(gt->uncore, GEN12_PAT_INDEX(7), GEN8_PPAT_WB);
}
}
@@ -593,20 +594,20 @@ static void chv_setup_private_ppat(struct intel_uncore *uncore)
intel_uncore_write(uncore, GEN8_PRIVATE_PAT_HI, upper_32_bits(pat));
}
-void setup_private_pat(struct intel_uncore *uncore)
+void setup_private_pat(struct intel_gt *gt)
{
- struct drm_i915_private *i915 = uncore->i915;
+ struct drm_i915_private *i915 = gt->i915;
GEM_BUG_ON(GRAPHICS_VER(i915) < 8);
if (GRAPHICS_VER(i915) >= 12)
- tgl_setup_private_ppat(uncore);
+ tgl_setup_private_ppat(gt);
else if (GRAPHICS_VER(i915) >= 11)
- icl_setup_private_ppat(uncore);
+ icl_setup_private_ppat(gt->uncore);
else if (IS_CHERRYVIEW(i915) || IS_GEN9_LP(i915))
- chv_setup_private_ppat(uncore);
+ chv_setup_private_ppat(gt->uncore);
else
- bdw_setup_private_ppat(uncore);
+ bdw_setup_private_ppat(gt->uncore);
}
struct i915_vma *
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index c0ca53cba9f0..5236c60f2a68 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -667,7 +667,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
void gtt_write_workarounds(struct intel_gt *gt);
-void setup_private_pat(struct intel_uncore *uncore);
+void setup_private_pat(struct intel_gt *gt);
int i915_vm_alloc_pt_stash(struct i915_address_space *vm,
struct i915_vm_pt_stash *stash,
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 06643701bf24..89ef1e06bf1d 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -7,6 +7,7 @@
#include "intel_engine.h"
#include "intel_gt.h"
+#include "intel_gt_mcr.h"
#include "intel_gt_regs.h"
#include "intel_mocs.h"
#include "intel_ring.h"
@@ -601,17 +602,17 @@ static u32 l3cc_combine(u16 low, u16 high)
0; \
i++)
-static void init_l3cc_table(struct intel_uncore *uncore,
+static void init_l3cc_table(struct intel_gt *gt,
const struct drm_i915_mocs_table *table)
{
unsigned int i;
u32 l3cc;
for_each_l3cc(l3cc, table, i)
- if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 50))
- intel_uncore_write_fw(uncore, XEHP_LNCFCMOCS(i), l3cc);
+ if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50))
+ intel_gt_mcr_multicast_write_fw(gt, XEHP_LNCFCMOCS(i), l3cc);
else
- intel_uncore_write_fw(uncore, GEN9_LNCFCMOCS(i), l3cc);
+ intel_uncore_write_fw(gt->uncore, GEN9_LNCFCMOCS(i), l3cc);
}
void intel_mocs_init_engine(struct intel_engine_cs *engine)
@@ -631,7 +632,7 @@ void intel_mocs_init_engine(struct intel_engine_cs *engine)
init_mocs_table(engine, &table);
if (flags & HAS_RENDER_L3CC && engine->class == RENDER_CLASS)
- init_l3cc_table(engine->uncore, &table);
+ init_l3cc_table(engine->gt, &table);
}
static u32 global_mocs_offset(void)
@@ -667,7 +668,7 @@ void intel_mocs_init(struct intel_gt *gt)
* memory transactions including guc transactions
*/
if (flags & HAS_RENDER_L3CC)
- init_l3cc_table(gt->uncore, &table);
+ init_l3cc_table(gt, &table);
}
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 9229243992c2..5b86b2e286e0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -10,12 +10,15 @@
*/
#include "gt/intel_gt.h"
+#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
#include "intel_guc_fw.h"
#include "i915_drv.h"
-static void guc_prepare_xfer(struct intel_uncore *uncore)
+static void guc_prepare_xfer(struct intel_gt *gt)
{
+ struct intel_uncore *uncore = gt->uncore;
+
u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC |
GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA |
GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA |
@@ -35,8 +38,9 @@ static void guc_prepare_xfer(struct intel_uncore *uncore)
if (GRAPHICS_VER(uncore->i915) == 9) {
/* DOP Clock Gating Enable for GuC clocks */
- intel_uncore_rmw(uncore, GEN8_MISCCPCTL,
- 0, GEN8_DOP_CLOCK_GATE_GUC_ENABLE);
+ intel_gt_mcr_multicast_write(gt, GEN8_MISCCPCTL,
+ GEN8_DOP_CLOCK_GATE_GUC_ENABLE |
+ intel_gt_mcr_read_any(gt, GEN8_MISCCPCTL));
/* allows for 5us (in 10ns units) before GT can go to RC6 */
intel_uncore_write(uncore, GUC_ARAT_C6DIS, 0x1FF);
@@ -168,7 +172,7 @@ int intel_guc_fw_upload(struct intel_guc *guc)
struct intel_uncore *uncore = gt->uncore;
int ret;
- guc_prepare_xfer(uncore);
+ guc_prepare_xfer(gt);
/*
* Note that GuC needs the CSS header plus uKernel code to be copied
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1aa77b18fd3c..fd1286d1908c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -30,6 +30,8 @@
#include "display/skl_watermark.h"
#include "gt/intel_engine_regs.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_gt_mcr.h"
#include "gt/intel_gt_regs.h"
#include "i915_drv.h"
@@ -4325,22 +4327,23 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
u32 val;
/* WaTempDisableDOPClkGating:bdw */
- misccpctl = intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL);
- intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);
+ misccpctl = intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_MISCCPCTL);
+ intel_gt_mcr_multicast_write(to_gt(dev_priv), GEN8_MISCCPCTL,
+ misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);
- val = intel_uncore_read(&dev_priv->uncore, GEN8_L3SQCREG1);
+ val = intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_L3SQCREG1);
val &= ~L3_PRIO_CREDITS_MASK;
val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
- intel_uncore_write(&dev_priv->uncore, GEN8_L3SQCREG1, val);
+ intel_gt_mcr_multicast_write(to_gt(dev_priv), GEN8_L3SQCREG1, val);
/*
* Wait at least 100 clocks before re-enabling clock gating.
* See the definition of L3SQCREG1 in BSpec.
*/
- intel_uncore_posting_read(&dev_priv->uncore, GEN8_L3SQCREG1);
+ intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_L3SQCREG1);
udelay(1);
- intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl);
+ intel_gt_mcr_multicast_write(to_gt(dev_priv), GEN8_MISCCPCTL, misccpctl);
}
static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -4500,8 +4503,9 @@ static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
gen9_init_clock_gating(dev_priv);
/* WaDisableDopClockGating:skl */
- intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL) &
- ~GEN8_DOP_CLOCK_GATE_ENABLE);
+ intel_gt_mcr_multicast_write(to_gt(dev_priv), GEN8_MISCCPCTL,
+ intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_MISCCPCTL) &
+ ~GEN8_DOP_CLOCK_GATE_ENABLE);
/* WAC6entrylatency:skl */
intel_uncore_write(&dev_priv->uncore, FBC_LLC_READ_CTRL, intel_uncore_read(&dev_priv->uncore, FBC_LLC_READ_CTRL) |
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 08/12] drm/i915/guc: Handle save/restore of MCR registers explicitly
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
MCR registers can be placed on the GuC's save/restore list, but at the
moment they are always handled in a multicast manner (i.e., the GuC
reads one instance to save the value and then does a multicast write to
restore that single value to all instances). In the future the GuC will
probably give us an alternate interface to do unicast per-instance
save/restore operations, so we should be very clear about which
registers on the list are MCR registers (and in the future which
save/restore behavior we want for them).
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 55 +++++++++++++---------
1 file changed, 34 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 7d9f4f57ca95..b5d3e3ef1787 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -277,24 +277,16 @@ __mmio_reg_add(struct temp_regset *regset, struct guc_mmio_reg *reg)
return slot;
}
-#define GUC_REGSET_STEERING(group, instance) ( \
- FIELD_PREP(GUC_REGSET_STEERING_GROUP, (group)) | \
- FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, (instance)) | \
- GUC_REGSET_NEEDS_STEERING \
-)
-
static long __must_check guc_mmio_reg_add(struct intel_gt *gt,
struct temp_regset *regset,
- i915_reg_t reg, u32 flags)
+ u32 offset, u32 flags)
{
u32 count = regset->storage_used - (regset->registers - regset->storage);
- u32 offset = i915_mmio_reg_offset(reg);
struct guc_mmio_reg entry = {
.offset = offset,
.flags = flags,
};
struct guc_mmio_reg *slot;
- u8 group, inst;
/*
* The mmio list is built using separate lists within the driver.
@@ -306,17 +298,6 @@ static long __must_check guc_mmio_reg_add(struct intel_gt *gt,
sizeof(entry), guc_mmio_reg_cmp))
return 0;
- /*
- * The GuC doesn't have a default steering, so we need to explicitly
- * steer all registers that need steering. However, we do not keep track
- * of all the steering ranges, only of those that have a chance of using
- * a non-default steering from the i915 pov. Instead of adding such
- * tracking, it is easier to just program the default steering for all
- * regs that don't need a non-default one.
- */
- intel_gt_mcr_get_nonterminated_steering(gt, reg, &group, &inst);
- entry.flags |= GUC_REGSET_STEERING(group, inst);
-
slot = __mmio_reg_add(regset, &entry);
if (IS_ERR(slot))
return PTR_ERR(slot);
@@ -334,6 +315,38 @@ static long __must_check guc_mmio_reg_add(struct intel_gt *gt,
#define GUC_MMIO_REG_ADD(gt, regset, reg, masked) \
guc_mmio_reg_add(gt, \
+ regset, \
+ i915_mmio_reg_offset(reg), \
+ (masked) ? GUC_REGSET_MASKED : 0)
+
+#define GUC_REGSET_STEERING(group, instance) ( \
+ FIELD_PREP(GUC_REGSET_STEERING_GROUP, (group)) | \
+ FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, (instance)) | \
+ GUC_REGSET_NEEDS_STEERING \
+)
+
+static long __must_check guc_mcr_reg_add(struct intel_gt *gt,
+ struct temp_regset *regset,
+ i915_reg_t reg, u32 flags)
+{
+ u8 group, inst;
+
+ /*
+ * The GuC doesn't have a default steering, so we need to explicitly
+ * steer all registers that need steering. However, we do not keep track
+ * of all the steering ranges, only of those that have a chance of using
+ * a non-default steering from the i915 pov. Instead of adding such
+ * tracking, it is easier to just program the default steering for all
+ * regs that don't need a non-default one.
+ */
+ intel_gt_mcr_get_nonterminated_steering(gt, reg, &group, &inst);
+ flags |= GUC_REGSET_STEERING(group, inst);
+
+ return guc_mmio_reg_add(gt, regset, i915_mmio_reg_offset(reg), flags);
+}
+
+#define GUC_MCR_REG_ADD(gt, regset, reg, masked) \
+ guc_mcr_reg_add(gt, \
regset, \
(reg), \
(masked) ? GUC_REGSET_MASKED : 0)
@@ -374,7 +387,7 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
/* add in local MOCS registers */
for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
- ret |= GUC_MMIO_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
+ ret |= GUC_MCR_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
else
ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH 08/12] drm/i915/guc: Handle save/restore of MCR registers explicitly
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
MCR registers can be placed on the GuC's save/restore list, but at the
moment they are always handled in a multicast manner (i.e., the GuC
reads one instance to save the value and then does a multicast write to
restore that single value to all instances). In the future the GuC will
probably give us an alternate interface to do unicast per-instance
save/restore operations, so we should be very clear about which
registers on the list are MCR registers (and in the future which
save/restore behavior we want for them).
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 55 +++++++++++++---------
1 file changed, 34 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 7d9f4f57ca95..b5d3e3ef1787 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -277,24 +277,16 @@ __mmio_reg_add(struct temp_regset *regset, struct guc_mmio_reg *reg)
return slot;
}
-#define GUC_REGSET_STEERING(group, instance) ( \
- FIELD_PREP(GUC_REGSET_STEERING_GROUP, (group)) | \
- FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, (instance)) | \
- GUC_REGSET_NEEDS_STEERING \
-)
-
static long __must_check guc_mmio_reg_add(struct intel_gt *gt,
struct temp_regset *regset,
- i915_reg_t reg, u32 flags)
+ u32 offset, u32 flags)
{
u32 count = regset->storage_used - (regset->registers - regset->storage);
- u32 offset = i915_mmio_reg_offset(reg);
struct guc_mmio_reg entry = {
.offset = offset,
.flags = flags,
};
struct guc_mmio_reg *slot;
- u8 group, inst;
/*
* The mmio list is built using separate lists within the driver.
@@ -306,17 +298,6 @@ static long __must_check guc_mmio_reg_add(struct intel_gt *gt,
sizeof(entry), guc_mmio_reg_cmp))
return 0;
- /*
- * The GuC doesn't have a default steering, so we need to explicitly
- * steer all registers that need steering. However, we do not keep track
- * of all the steering ranges, only of those that have a chance of using
- * a non-default steering from the i915 pov. Instead of adding such
- * tracking, it is easier to just program the default steering for all
- * regs that don't need a non-default one.
- */
- intel_gt_mcr_get_nonterminated_steering(gt, reg, &group, &inst);
- entry.flags |= GUC_REGSET_STEERING(group, inst);
-
slot = __mmio_reg_add(regset, &entry);
if (IS_ERR(slot))
return PTR_ERR(slot);
@@ -334,6 +315,38 @@ static long __must_check guc_mmio_reg_add(struct intel_gt *gt,
#define GUC_MMIO_REG_ADD(gt, regset, reg, masked) \
guc_mmio_reg_add(gt, \
+ regset, \
+ i915_mmio_reg_offset(reg), \
+ (masked) ? GUC_REGSET_MASKED : 0)
+
+#define GUC_REGSET_STEERING(group, instance) ( \
+ FIELD_PREP(GUC_REGSET_STEERING_GROUP, (group)) | \
+ FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, (instance)) | \
+ GUC_REGSET_NEEDS_STEERING \
+)
+
+static long __must_check guc_mcr_reg_add(struct intel_gt *gt,
+ struct temp_regset *regset,
+ i915_reg_t reg, u32 flags)
+{
+ u8 group, inst;
+
+ /*
+ * The GuC doesn't have a default steering, so we need to explicitly
+ * steer all registers that need steering. However, we do not keep track
+ * of all the steering ranges, only of those that have a chance of using
+ * a non-default steering from the i915 pov. Instead of adding such
+ * tracking, it is easier to just program the default steering for all
+ * regs that don't need a non-default one.
+ */
+ intel_gt_mcr_get_nonterminated_steering(gt, reg, &group, &inst);
+ flags |= GUC_REGSET_STEERING(group, inst);
+
+ return guc_mmio_reg_add(gt, regset, i915_mmio_reg_offset(reg), flags);
+}
+
+#define GUC_MCR_REG_ADD(gt, regset, reg, masked) \
+ guc_mcr_reg_add(gt, \
regset, \
(reg), \
(masked) ? GUC_REGSET_MASKED : 0)
@@ -374,7 +387,7 @@ static int guc_mmio_regset_init(struct temp_regset *regset,
/* add in local MOCS registers */
for (i = 0; i < LNCFCMOCS_REG_COUNT; i++)
if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
- ret |= GUC_MMIO_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
+ ret |= GUC_MCR_REG_ADD(gt, regset, XEHP_LNCFCMOCS(i), false);
else
ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false);
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 09/12] drm/i915/gt: Add MCR-specific workaround initializers
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Let's be more explicit about which of our workarounds are updating MCR
registers.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 424 +++++++++++-------
.../gpu/drm/i915/gt/intel_workarounds_types.h | 4 +-
2 files changed, 259 insertions(+), 169 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3d48189021ad..f98213b7c61d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -166,12 +166,33 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
_wa_add(wal, &wa);
}
+static void wa_mcr_add(struct i915_wa_list *wal, i915_reg_t reg,
+ u32 clear, u32 set, u32 read_mask, bool masked_reg)
+{
+ struct i915_wa wa = {
+ .reg = reg,
+ .clr = clear,
+ .set = set,
+ .read = read_mask,
+ .masked_reg = masked_reg,
+ .is_mcr = 1,
+ };
+
+ _wa_add(wal, &wa);
+}
+
static void
wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
{
wa_add(wal, reg, clear, set, clear, false);
}
+static void
+wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
+{
+ wa_mcr_add(wal, reg, clear, set, clear, false);
+}
+
static void
wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
{
@@ -184,12 +205,24 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
wa_write_clr_set(wal, reg, set, set);
}
+static void
+wa_mcr_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
+{
+ wa_mcr_write_clr_set(wal, reg, set, set);
+}
+
static void
wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
{
wa_write_clr_set(wal, reg, clr, 0);
}
+static void
+wa_mcr_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
+{
+ wa_mcr_write_clr_set(wal, reg, clr, 0);
+}
+
/*
* WA operations on "masked register". A masked register has the upper 16 bits
* documented as "masked" in b-spec. Its purpose is to allow writing to just a
@@ -207,12 +240,24 @@ wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
}
+static void
+wa_mcr_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+ wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
+}
+
static void
wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
}
+static void
+wa_mcr_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+ wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
+}
+
static void
wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
u32 mask, u32 val)
@@ -220,6 +265,13 @@ wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
}
+static void
+wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
+ u32 mask, u32 val)
+{
+ wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
+}
+
static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
@@ -241,7 +293,7 @@ static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE);
/* WaDisablePartialInstShootdown:bdw,chv */
- wa_masked_en(wal, GEN8_ROW_CHICKEN,
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
/* Use Force Non-Coherent whenever executing a 3D context. This is a
@@ -288,18 +340,18 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
gen8_ctx_workarounds_init(engine, wal);
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
- wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
/* WaDisableDopClockGating:bdw
*
* Also see the related UCGTCL1 write in bdw_init_clock_gating()
* to disable EUTC clock gating.
*/
- wa_masked_en(wal, GEN8_ROW_CHICKEN2,
- DOP_CLOCK_GATING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
+ DOP_CLOCK_GATING_DISABLE);
- wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
- GEN8_SAMPLER_POWER_BYPASS_DIS);
+ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
+ GEN8_SAMPLER_POWER_BYPASS_DIS);
wa_masked_en(wal, HDC_CHICKEN0,
/* WaForceContextSaveRestoreNonCoherent:bdw */
@@ -314,7 +366,7 @@ static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
gen8_ctx_workarounds_init(engine, wal);
/* WaDisableThreadStallDopClockGating:chv */
- wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
/* Improve HiZ throughput on CHV. */
wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
@@ -333,21 +385,21 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
*/
wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
GEN9_PBE_COMPRESSED_HASH_SELECTION);
- wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
- GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
+ wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
+ GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
}
/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
- wa_masked_en(wal, GEN8_ROW_CHICKEN,
- FLOW_CONTROL_ENABLE |
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
+ FLOW_CONTROL_ENABLE |
+ PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
- wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
- GEN9_ENABLE_YV12_BUGFIX |
- GEN9_ENABLE_GPGPU_PREEMPTION);
+ wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
+ GEN9_ENABLE_YV12_BUGFIX |
+ GEN9_ENABLE_GPGPU_PREEMPTION);
/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
/* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
@@ -356,8 +408,8 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
- wa_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5,
- GEN9_CCS_TLB_PREFETCH_ENABLE);
+ wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5,
+ GEN9_CCS_TLB_PREFETCH_ENABLE);
/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
wa_masked_en(wal, HDC_CHICKEN0,
@@ -386,11 +438,11 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
IS_KABYLAKE(i915) ||
IS_COFFEELAKE(i915) ||
IS_COMETLAKE(i915))
- wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
- GEN8_SAMPLER_POWER_BYPASS_DIS);
+ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
+ GEN8_SAMPLER_POWER_BYPASS_DIS);
/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
- wa_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
+ wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
/*
* Supporting preemption with fine-granularity requires changes in the
@@ -469,8 +521,8 @@ static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
gen9_ctx_workarounds_init(engine, wal);
/* WaDisableThreadStallDopClockGating:bxt */
- wa_masked_en(wal, GEN8_ROW_CHICKEN,
- STALL_DOP_GATING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
+ STALL_DOP_GATING_DISABLE);
/* WaToEnableHwFixForPushConstHWBug:bxt */
wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
@@ -490,8 +542,8 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaDisableSbeCacheDispatchPortSharing:kbl */
- wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
- GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
+ GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
@@ -514,8 +566,8 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaDisableSbeCacheDispatchPortSharing:cfl */
- wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
- GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
+ GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
@@ -534,13 +586,13 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
* (the register is whitelisted in hardware now, so UMDs can opt in
* for coherency if they have a good reason).
*/
- wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
+ wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
/* WaEnableFloatBlendOptimization:icl */
- wa_add(wal, GEN10_CACHE_MODE_SS, 0,
- _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
- 0 /* write-only, so skip validation */,
- true);
+ wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
+ _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
+ 0 /* write-only, so skip validation */,
+ true);
/* WaDisableGPGPUMidThreadPreemption:icl */
wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
@@ -548,8 +600,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
/* allow headerless messages for preemptible GPGPU context */
- wa_masked_en(wal, GEN10_SAMPLER_MODE,
- GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
+ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
+ GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
/* Wa_1604278689:icl,ehl */
wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
@@ -558,7 +610,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
0xFFFFFFFF);
/* Wa_1406306137:icl,ehl */
- wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
+ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
}
/*
@@ -569,13 +621,13 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
- wa_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
- REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
- wa_add(wal,
- XEHP_FF_MODE2,
- FF_MODE2_TDS_TIMER_MASK,
- FF_MODE2_TDS_TIMER_128,
- 0, false);
+ wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
+ REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
+ wa_mcr_add(wal,
+ XEHP_FF_MODE2,
+ FF_MODE2_TDS_TIMER_MASK,
+ FF_MODE2_TDS_TIMER_128,
+ 0, false);
}
/*
@@ -664,27 +716,27 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
/* Wa_16011186671:dg2_g11 */
if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
- wa_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH);
- wa_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE);
+ wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH);
+ wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE);
}
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
/* Wa_14010469329:dg2_g10 */
- wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
- XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
+ wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
+ XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
/*
* Wa_22010465075:dg2_g10
* Wa_22010613112:dg2_g10
* Wa_14010698770:dg2_g10
*/
- wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
- GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+ wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
+ GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
}
/* Wa_16013271637:dg2 */
- wa_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
- MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
+ wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
+ MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
/* Wa_14014947963:dg2 */
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
@@ -1254,9 +1306,9 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
PSDUNIT_CLKGATE_DIS);
/* Wa_1406680159:icl,ehl */
- wa_write_or(wal,
- GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
- GWUNIT_CLKGATE_DIS);
+ wa_mcr_write_or(wal,
+ GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
+ GWUNIT_CLKGATE_DIS);
/* Wa_1607087056:icl,ehl,jsl */
if (IS_ICELAKE(i915) ||
@@ -1269,7 +1321,7 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
* This is not a documented workaround, but rather an optimization
* to reduce sampler power.
*/
- wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
+ wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
}
/*
@@ -1303,7 +1355,7 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_14011060649(gt, wal);
/* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
- wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
+ wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
}
static void
@@ -1315,9 +1367,9 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_1409420604:tgl */
if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
- wa_write_or(wal,
- SUBSLICE_UNIT_LEVEL_CLKGATE2,
- CPSSUNIT_CLKGATE_DIS);
+ wa_mcr_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
/* Wa_1607087056:tgl also know as BUG:1409180338 */
if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
@@ -1346,9 +1398,9 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_1409420604:dg1 */
if (IS_DG1(i915))
- wa_write_or(wal,
- SUBSLICE_UNIT_LEVEL_CLKGATE2,
- CPSSUNIT_CLKGATE_DIS);
+ wa_mcr_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
/* Wa_1408615072:dg1 */
/* Empirical testing shows this register is unaffected by engine reset. */
@@ -1365,7 +1417,7 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
xehp_init_mcr(gt, wal);
/* Wa_1409757795:xehpsdv */
- wa_write_or(wal, SCCGCTL94DC, CG3DDISURB);
+ wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB);
/* Wa_16011155590:xehpsdv */
if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
@@ -1445,8 +1497,8 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
CG3DDISCFEG_CLKGATE_DIS);
/* Wa_14011006942:dg2 */
- wa_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
- DSS_ROUTER_CLKGATE_DIS);
+ wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
+ DSS_ROUTER_CLKGATE_DIS);
}
if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) {
@@ -1457,7 +1509,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
/* Wa_14011371254:dg2_g10 */
- wa_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
+ wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
/* Wa_14011431319:dg2_g10 */
wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
@@ -1493,18 +1545,18 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
GAMEDIA_CLKGATE_DIS);
/* Wa_14011028019:dg2_g10 */
- wa_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS);
+ wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS);
}
/* Wa_14014830051:dg2 */
- wa_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
+ wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
/*
* The following are not actually "workarounds" but rather
* recommended tuning settings documented in the bspec's
* performance guide section.
*/
- wa_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
+ wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
/* Wa_14015795083 */
wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
@@ -1628,14 +1680,25 @@ wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal)
u32 val, old = 0;
/* open-coded rmw due to steering */
- old = wa->clr ? intel_gt_mcr_read_any_fw(gt, wa->reg) : 0;
+ if (wa->clr)
+ old = wa->is_mcr ?
+ intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_uncore_read_fw(uncore, wa->reg);
val = (old & ~wa->clr) | wa->set;
- if (val != old || !wa->clr)
- intel_uncore_write_fw(uncore, wa->reg, val);
+ if (val != old || !wa->clr) {
+ if (wa->is_mcr)
+ intel_gt_mcr_multicast_write_fw(gt, wa->reg, val);
+ else
+ intel_uncore_write_fw(uncore, wa->reg, val);
+ }
+
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
+ u32 val = wa->is_mcr ?
+ intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_uncore_read_fw(uncore, wa->reg);
- if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
- wa_verify(wa, intel_gt_mcr_read_any_fw(gt, wa->reg),
- wal->name, "application");
+ wa_verify(wa, val, wal->name, "application");
+ }
}
intel_uncore_forcewake_put__locked(uncore, fw);
@@ -1664,8 +1727,9 @@ static bool wa_list_verify(struct intel_gt *gt,
intel_uncore_forcewake_get__locked(uncore, fw);
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- ok &= wa_verify(wa,
- intel_gt_mcr_read_any_fw(gt, wa->reg),
+ ok &= wa_verify(wa, wa->is_mcr ?
+ intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_uncore_read_fw(uncore, wa->reg),
wal->name, from);
intel_uncore_forcewake_put__locked(uncore, fw);
@@ -1711,12 +1775,36 @@ whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
_wa_add(wal, &wa);
}
+static void
+whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
+{
+ struct i915_wa wa = {
+ .reg = reg,
+ .is_mcr = 1,
+ };
+
+ if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
+ return;
+
+ if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
+ return;
+
+ wa.reg.reg |= flags;
+ _wa_add(wal, &wa);
+}
+
static void
whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
{
whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
}
+static void
+whitelist_mcr_reg(struct i915_wa_list *wal, i915_reg_t reg)
+{
+ whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
+}
+
static void gen9_whitelist_build(struct i915_wa_list *w)
{
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
@@ -1742,7 +1830,7 @@ static void skl_whitelist_build(struct intel_engine_cs *engine)
gen9_whitelist_build(w);
/* WaDisableLSQCROPERFforOCL:skl */
- whitelist_reg(w, GEN8_L3SQCREG4);
+ whitelist_mcr_reg(w, GEN8_L3SQCREG4);
}
static void bxt_whitelist_build(struct intel_engine_cs *engine)
@@ -1763,7 +1851,7 @@ static void kbl_whitelist_build(struct intel_engine_cs *engine)
gen9_whitelist_build(w);
/* WaDisableLSQCROPERFforOCL:kbl */
- whitelist_reg(w, GEN8_L3SQCREG4);
+ whitelist_mcr_reg(w, GEN8_L3SQCREG4);
}
static void glk_whitelist_build(struct intel_engine_cs *engine)
@@ -1828,10 +1916,10 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
switch (engine->class) {
case RENDER_CLASS:
/* WaAllowUMDToModifyHalfSliceChicken7:icl */
- whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+ whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7);
/* WaAllowUMDToModifySamplerMode:icl */
- whitelist_reg(w, GEN10_SAMPLER_MODE);
+ whitelist_mcr_reg(w, GEN10_SAMPLER_MODE);
/* WaEnableStateCacheRedirectToCS:icl */
whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
@@ -2107,24 +2195,24 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14013392000:dg2_g11 */
- wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
/* Wa_16011620976:dg2_g11 */
- wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
/* Wa_1509727124:dg2 */
- wa_masked_en(wal, GEN10_SAMPLER_MODE,
- SC_DISABLE_POWER_OPTIMIZATION_EBB);
+ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
+ SC_DISABLE_POWER_OPTIMIZATION_EBB);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012419201:dg2 */
- wa_masked_en(wal, GEN9_ROW_CHICKEN4,
- GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX);
+ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4,
+ GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
@@ -2133,13 +2221,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* Wa_22012826095:dg2
* Wa_22013059131:dg2
*/
- wa_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
- MAXREQS_PER_BANK,
- REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
+ wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
+ MAXREQS_PER_BANK,
+ REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
/* Wa_22013059131:dg2 */
- wa_write_or(wal, LSC_CHICKEN_BIT_0,
- FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
+ FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
}
/* Wa_1308578152:dg2_g10 when first gslice is fused off */
@@ -2152,19 +2240,19 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
/* Wa_22013037850:dg2 */
- wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
- DISABLE_128B_EVICTION_COMMAND_UDW);
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
+ DISABLE_128B_EVICTION_COMMAND_UDW);
/* Wa_22012856258:dg2 */
- wa_masked_en(wal, GEN8_ROW_CHICKEN2,
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
GEN12_DISABLE_READ_SUPPRESSION);
/*
* Wa_22010960976:dg2
* Wa_14013347512:dg2
*/
- wa_masked_dis(wal, XEHP_HDC_CHICKEN0,
- LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
+ wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0,
+ LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
@@ -2172,7 +2260,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* Wa_1608949956:dg2_g10
* Wa_14010198302:dg2_g10
*/
- wa_masked_en(wal, GEN8_ROW_CHICKEN,
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE);
/*
@@ -2181,31 +2269,31 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping,
* so ignoring verification.
*/
- wa_add(wal, LSC_CHICKEN_BIT_0_UDW, 0,
- FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE,
- 0, false);
+ wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0,
+ FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE,
+ 0, false);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
/* Wa_22010430635:dg2 */
- wa_masked_en(wal,
- GEN9_ROW_CHICKEN4,
- GEN12_DISABLE_GRF_CLEAR);
+ wa_mcr_masked_en(wal,
+ GEN9_ROW_CHICKEN4,
+ GEN12_DISABLE_GRF_CLEAR);
/* Wa_14010648519:dg2 */
- wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
+ wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
}
/* Wa_14013202645:dg2 */
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0))
- wa_write_or(wal, RT_CTRL, DIS_NULL_QUERY);
+ wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY);
/* Wa_22012532006:dg2 */
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) ||
IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
- wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
- DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
+ wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
+ DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
/* Wa_14010680813:dg2_g10 */
@@ -2216,17 +2304,17 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012362059:dg2 */
- wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
}
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) ||
IS_DG2_G10(i915)) {
/* Wa_22014600077:dg2 */
- wa_add(wal, GEN10_CACHE_MODE_SS, 0,
- _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),
- 0 /* Wa_14012342262 :write-only reg, so skip
- verification */,
- true);
+ wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
+ _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),
+ 0 /* Wa_14012342262 :write-only reg, so skip
+ verification */,
+ true);
}
if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
@@ -2253,7 +2341,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
- wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
/*
* Wa_1407928979:tgl A*
@@ -2282,14 +2370,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
- wa_masked_en(wal, GEN8_ROW_CHICKEN2,
- GEN12_PUSH_CONST_DEREF_HOLD_DIS);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
+ GEN12_PUSH_CONST_DEREF_HOLD_DIS);
/*
* Wa_1409085225:tgl
* Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p
*/
- wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
+ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
}
if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
@@ -2313,9 +2401,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) ||
IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
/* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */
- wa_masked_en(wal,
- GEN10_SAMPLER_MODE,
- ENABLE_SMALLPL);
+ wa_mcr_masked_en(wal,
+ GEN10_SAMPLER_MODE,
+ ENABLE_SMALLPL);
}
if (GRAPHICS_VER(i915) == 11) {
@@ -2349,9 +2437,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* Wa_1405733216:icl
* Formerly known as WaDisableCleanEvicts
*/
- wa_write_or(wal,
- GEN8_L3SQCREG4,
- GEN11_LQSC_CLEAN_EVICT_DISABLE);
+ wa_mcr_write_or(wal,
+ GEN8_L3SQCREG4,
+ GEN11_LQSC_CLEAN_EVICT_DISABLE);
/* Wa_1606682166:icl */
wa_write_or(wal,
@@ -2359,10 +2447,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN7_DISABLE_SAMPLER_PREFETCH);
/* Wa_1409178092:icl */
- wa_write_clr_set(wal,
- GEN11_SCRATCH2,
- GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
- 0);
+ wa_mcr_write_clr_set(wal,
+ GEN11_SCRATCH2,
+ GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
+ 0);
/* WaEnable32PlaneMode:icl */
wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,
@@ -2420,30 +2508,30 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
- wa_write_or(wal,
- BDW_SCRATCH1,
- GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
+ wa_mcr_write_or(wal,
+ BDW_SCRATCH1,
+ GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
/* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
if (IS_GEN9_LP(i915))
- wa_write_clr_set(wal,
- GEN8_L3SQCREG1,
- L3_PRIO_CREDITS_MASK,
- L3_GENERAL_PRIO_CREDITS(62) |
- L3_HIGH_PRIO_CREDITS(2));
+ wa_mcr_write_clr_set(wal,
+ GEN8_L3SQCREG1,
+ L3_PRIO_CREDITS_MASK,
+ L3_GENERAL_PRIO_CREDITS(62) |
+ L3_HIGH_PRIO_CREDITS(2));
/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
- wa_write_or(wal,
- GEN8_L3SQCREG4,
- GEN8_LQSC_FLUSH_COHERENT_LINES);
+ wa_mcr_write_or(wal,
+ GEN8_L3SQCREG4,
+ GEN8_LQSC_FLUSH_COHERENT_LINES);
/* Disable atomics in L3 to prevent unrecoverable hangs */
wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1,
GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0);
- wa_write_clr_set(wal, GEN8_L3SQCREG4,
- GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
- wa_write_clr_set(wal, GEN9_SCRATCH1,
- EVICTION_PERF_FIX_ENABLE, 0);
+ wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4,
+ GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+ wa_mcr_write_clr_set(wal, GEN9_SCRATCH1,
+ EVICTION_PERF_FIX_ENABLE, 0);
}
if (IS_HASWELL(i915)) {
@@ -2657,7 +2745,7 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) {
/* Wa_14014999345:pvc */
- wa_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC);
+ wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC);
}
}
@@ -2683,8 +2771,8 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
}
if (IS_DG2(i915)) {
- wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
- wa_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
+ wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+ wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
/*
* This is also listed as Wa_22012654132 for certain DG2
@@ -2695,10 +2783,10 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
* back for verification on DG2 (due to Wa_14012342262), so
* we need to explicitly skip the readback.
*/
- wa_add(wal, GEN10_CACHE_MODE_SS, 0,
- _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
- 0 /* write-only, so skip validation */,
- true);
+ wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
+ _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
+ 0 /* write-only, so skip validation */,
+ true);
}
/*
@@ -2707,8 +2795,8 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
* platforms.
*/
if (INTEL_INFO(i915)->tuning_thread_rr_after_dep)
- wa_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
- THREAD_EX_ARB_MODE_RR_AFTER_DEP);
+ wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
+ THREAD_EX_ARB_MODE_RR_AFTER_DEP);
}
/*
@@ -2734,30 +2822,30 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
if (IS_XEHPSDV(i915)) {
/* Wa_1409954639 */
- wa_masked_en(wal,
- GEN8_ROW_CHICKEN,
- SYSTOLIC_DOP_CLOCK_GATING_DIS);
+ wa_mcr_masked_en(wal,
+ GEN8_ROW_CHICKEN,
+ SYSTOLIC_DOP_CLOCK_GATING_DIS);
/* Wa_1607196519 */
- wa_masked_en(wal,
- GEN9_ROW_CHICKEN4,
- GEN12_DISABLE_GRF_CLEAR);
+ wa_mcr_masked_en(wal,
+ GEN9_ROW_CHICKEN4,
+ GEN12_DISABLE_GRF_CLEAR);
/* Wa_14010670810:xehpsdv */
- wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
+ wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
/* Wa_14010449647:xehpsdv */
- wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
- GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
+ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
+ GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
/* Wa_18011725039:xehpsdv */
if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
- wa_masked_dis(wal, MLTICTXCTL, TDONRENDER);
- wa_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
+ wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER);
+ wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
}
/* Wa_14012362059:xehpsdv */
- wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
/* Wa_14014368820:xehpsdv */
wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
@@ -2766,19 +2854,19 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) {
/* Wa_14015227452:dg2,pvc */
- wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
+ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
/* Wa_22014226127:dg2,pvc */
- wa_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
/* Wa_16015675438:dg2,pvc */
wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
/* Wa_18018781329:dg2,pvc */
- wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
index 8a4b6de4e754..f05b37e56fa9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
@@ -15,7 +15,9 @@ struct i915_wa {
u32 clr;
u32 set;
u32 read;
- bool masked_reg;
+
+ u32 masked_reg:1;
+ u32 is_mcr:1;
};
struct i915_wa_list {
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH 09/12] drm/i915/gt: Add MCR-specific workaround initializers
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Let's be more explicit about which of our workarounds are updating MCR
registers.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 424 +++++++++++-------
.../gpu/drm/i915/gt/intel_workarounds_types.h | 4 +-
2 files changed, 259 insertions(+), 169 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3d48189021ad..f98213b7c61d 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -166,12 +166,33 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
_wa_add(wal, &wa);
}
+static void wa_mcr_add(struct i915_wa_list *wal, i915_reg_t reg,
+ u32 clear, u32 set, u32 read_mask, bool masked_reg)
+{
+ struct i915_wa wa = {
+ .reg = reg,
+ .clr = clear,
+ .set = set,
+ .read = read_mask,
+ .masked_reg = masked_reg,
+ .is_mcr = 1,
+ };
+
+ _wa_add(wal, &wa);
+}
+
static void
wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
{
wa_add(wal, reg, clear, set, clear, false);
}
+static void
+wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
+{
+ wa_mcr_add(wal, reg, clear, set, clear, false);
+}
+
static void
wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
{
@@ -184,12 +205,24 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
wa_write_clr_set(wal, reg, set, set);
}
+static void
+wa_mcr_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
+{
+ wa_mcr_write_clr_set(wal, reg, set, set);
+}
+
static void
wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
{
wa_write_clr_set(wal, reg, clr, 0);
}
+static void
+wa_mcr_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
+{
+ wa_mcr_write_clr_set(wal, reg, clr, 0);
+}
+
/*
* WA operations on "masked register". A masked register has the upper 16 bits
* documented as "masked" in b-spec. Its purpose is to allow writing to just a
@@ -207,12 +240,24 @@ wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
}
+static void
+wa_mcr_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+ wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
+}
+
static void
wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
{
wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
}
+static void
+wa_mcr_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+ wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
+}
+
static void
wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
u32 mask, u32 val)
@@ -220,6 +265,13 @@ wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
}
+static void
+wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
+ u32 mask, u32 val)
+{
+ wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
+}
+
static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
@@ -241,7 +293,7 @@ static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE);
/* WaDisablePartialInstShootdown:bdw,chv */
- wa_masked_en(wal, GEN8_ROW_CHICKEN,
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
/* Use Force Non-Coherent whenever executing a 3D context. This is a
@@ -288,18 +340,18 @@ static void bdw_ctx_workarounds_init(struct intel_engine_cs *engine,
gen8_ctx_workarounds_init(engine, wal);
/* WaDisableThreadStallDopClockGating:bdw (pre-production) */
- wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
/* WaDisableDopClockGating:bdw
*
* Also see the related UCGTCL1 write in bdw_init_clock_gating()
* to disable EUTC clock gating.
*/
- wa_masked_en(wal, GEN8_ROW_CHICKEN2,
- DOP_CLOCK_GATING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
+ DOP_CLOCK_GATING_DISABLE);
- wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
- GEN8_SAMPLER_POWER_BYPASS_DIS);
+ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
+ GEN8_SAMPLER_POWER_BYPASS_DIS);
wa_masked_en(wal, HDC_CHICKEN0,
/* WaForceContextSaveRestoreNonCoherent:bdw */
@@ -314,7 +366,7 @@ static void chv_ctx_workarounds_init(struct intel_engine_cs *engine,
gen8_ctx_workarounds_init(engine, wal);
/* WaDisableThreadStallDopClockGating:chv */
- wa_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
/* Improve HiZ throughput on CHV. */
wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
@@ -333,21 +385,21 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
*/
wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
GEN9_PBE_COMPRESSED_HASH_SELECTION);
- wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
- GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
+ wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
+ GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
}
/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
/* WaDisablePartialInstShootdown:skl,bxt,kbl,glk,cfl */
- wa_masked_en(wal, GEN8_ROW_CHICKEN,
- FLOW_CONTROL_ENABLE |
- PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
+ FLOW_CONTROL_ENABLE |
+ PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
- wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
- GEN9_ENABLE_YV12_BUGFIX |
- GEN9_ENABLE_GPGPU_PREEMPTION);
+ wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
+ GEN9_ENABLE_YV12_BUGFIX |
+ GEN9_ENABLE_GPGPU_PREEMPTION);
/* Wa4x4STCOptimizationDisable:skl,bxt,kbl,glk,cfl */
/* WaDisablePartialResolveInVc:skl,bxt,kbl,cfl */
@@ -356,8 +408,8 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE);
/* WaCcsTlbPrefetchDisable:skl,bxt,kbl,glk,cfl */
- wa_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5,
- GEN9_CCS_TLB_PREFETCH_ENABLE);
+ wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5,
+ GEN9_CCS_TLB_PREFETCH_ENABLE);
/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
wa_masked_en(wal, HDC_CHICKEN0,
@@ -386,11 +438,11 @@ static void gen9_ctx_workarounds_init(struct intel_engine_cs *engine,
IS_KABYLAKE(i915) ||
IS_COFFEELAKE(i915) ||
IS_COMETLAKE(i915))
- wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
- GEN8_SAMPLER_POWER_BYPASS_DIS);
+ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3,
+ GEN8_SAMPLER_POWER_BYPASS_DIS);
/* WaDisableSTUnitPowerOptimization:skl,bxt,kbl,glk,cfl */
- wa_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
+ wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
/*
* Supporting preemption with fine-granularity requires changes in the
@@ -469,8 +521,8 @@ static void bxt_ctx_workarounds_init(struct intel_engine_cs *engine,
gen9_ctx_workarounds_init(engine, wal);
/* WaDisableThreadStallDopClockGating:bxt */
- wa_masked_en(wal, GEN8_ROW_CHICKEN,
- STALL_DOP_GATING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
+ STALL_DOP_GATING_DISABLE);
/* WaToEnableHwFixForPushConstHWBug:bxt */
wa_masked_en(wal, COMMON_SLICE_CHICKEN2,
@@ -490,8 +542,8 @@ static void kbl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaDisableSbeCacheDispatchPortSharing:kbl */
- wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
- GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
+ GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
static void glk_ctx_workarounds_init(struct intel_engine_cs *engine,
@@ -514,8 +566,8 @@ static void cfl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaDisableSbeCacheDispatchPortSharing:cfl */
- wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
- GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
+ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
+ GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
}
static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
@@ -534,13 +586,13 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
* (the register is whitelisted in hardware now, so UMDs can opt in
* for coherency if they have a good reason).
*/
- wa_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
+ wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT);
/* WaEnableFloatBlendOptimization:icl */
- wa_add(wal, GEN10_CACHE_MODE_SS, 0,
- _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
- 0 /* write-only, so skip validation */,
- true);
+ wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
+ _MASKED_BIT_ENABLE(FLOAT_BLEND_OPTIMIZATION_ENABLE),
+ 0 /* write-only, so skip validation */,
+ true);
/* WaDisableGPGPUMidThreadPreemption:icl */
wa_masked_field_set(wal, GEN8_CS_CHICKEN1,
@@ -548,8 +600,8 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
/* allow headerless messages for preemptible GPGPU context */
- wa_masked_en(wal, GEN10_SAMPLER_MODE,
- GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
+ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
+ GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
/* Wa_1604278689:icl,ehl */
wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
@@ -558,7 +610,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
0xFFFFFFFF);
/* Wa_1406306137:icl,ehl */
- wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
+ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
}
/*
@@ -569,13 +621,13 @@ static void dg2_ctx_gt_tuning_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
wa_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP);
- wa_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
- REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
- wa_add(wal,
- XEHP_FF_MODE2,
- FF_MODE2_TDS_TIMER_MASK,
- FF_MODE2_TDS_TIMER_128,
- 0, false);
+ wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
+ REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f));
+ wa_mcr_add(wal,
+ XEHP_FF_MODE2,
+ FF_MODE2_TDS_TIMER_MASK,
+ FF_MODE2_TDS_TIMER_128,
+ 0, false);
}
/*
@@ -664,27 +716,27 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
/* Wa_16011186671:dg2_g11 */
if (IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
- wa_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH);
- wa_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE);
+ wa_mcr_masked_dis(wal, VFLSKPD, DIS_MULT_MISS_RD_SQUASH);
+ wa_mcr_masked_en(wal, VFLSKPD, DIS_OVER_FETCH_CACHE);
}
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
/* Wa_14010469329:dg2_g10 */
- wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
- XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
+ wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
+ XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE);
/*
* Wa_22010465075:dg2_g10
* Wa_22010613112:dg2_g10
* Wa_14010698770:dg2_g10
*/
- wa_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
- GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
+ wa_mcr_masked_en(wal, XEHP_COMMON_SLICE_CHICKEN3,
+ GEN12_DISABLE_CPS_AWARE_COLOR_PIPE);
}
/* Wa_16013271637:dg2 */
- wa_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
- MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
+ wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1,
+ MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
/* Wa_14014947963:dg2 */
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
@@ -1254,9 +1306,9 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
PSDUNIT_CLKGATE_DIS);
/* Wa_1406680159:icl,ehl */
- wa_write_or(wal,
- GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
- GWUNIT_CLKGATE_DIS);
+ wa_mcr_write_or(wal,
+ GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
+ GWUNIT_CLKGATE_DIS);
/* Wa_1607087056:icl,ehl,jsl */
if (IS_ICELAKE(i915) ||
@@ -1269,7 +1321,7 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
* This is not a documented workaround, but rather an optimization
* to reduce sampler power.
*/
- wa_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
+ wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
}
/*
@@ -1303,7 +1355,7 @@ gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_14011060649(gt, wal);
/* Wa_14011059788:tgl,rkl,adl-s,dg1,adl-p */
- wa_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
+ wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE);
}
static void
@@ -1315,9 +1367,9 @@ tgl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_1409420604:tgl */
if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
- wa_write_or(wal,
- SUBSLICE_UNIT_LEVEL_CLKGATE2,
- CPSSUNIT_CLKGATE_DIS);
+ wa_mcr_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
/* Wa_1607087056:tgl also know as BUG:1409180338 */
if (IS_TGL_UY_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
@@ -1346,9 +1398,9 @@ dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
/* Wa_1409420604:dg1 */
if (IS_DG1(i915))
- wa_write_or(wal,
- SUBSLICE_UNIT_LEVEL_CLKGATE2,
- CPSSUNIT_CLKGATE_DIS);
+ wa_mcr_write_or(wal,
+ SUBSLICE_UNIT_LEVEL_CLKGATE2,
+ CPSSUNIT_CLKGATE_DIS);
/* Wa_1408615072:dg1 */
/* Empirical testing shows this register is unaffected by engine reset. */
@@ -1365,7 +1417,7 @@ xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
xehp_init_mcr(gt, wal);
/* Wa_1409757795:xehpsdv */
- wa_write_or(wal, SCCGCTL94DC, CG3DDISURB);
+ wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB);
/* Wa_16011155590:xehpsdv */
if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
@@ -1445,8 +1497,8 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
CG3DDISCFEG_CLKGATE_DIS);
/* Wa_14011006942:dg2 */
- wa_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
- DSS_ROUTER_CLKGATE_DIS);
+ wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE,
+ DSS_ROUTER_CLKGATE_DIS);
}
if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0)) {
@@ -1457,7 +1509,7 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_write_or(wal, UNSLCGCTL9444, LTCDD_CLKGATE_DIS);
/* Wa_14011371254:dg2_g10 */
- wa_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
+ wa_mcr_write_or(wal, XEHP_SLICE_UNIT_LEVEL_CLKGATE, NODEDSS_CLKGATE_DIS);
/* Wa_14011431319:dg2_g10 */
wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS |
@@ -1493,18 +1545,18 @@ dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
GAMEDIA_CLKGATE_DIS);
/* Wa_14011028019:dg2_g10 */
- wa_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS);
+ wa_mcr_write_or(wal, SSMCGCTL9530, RTFUNIT_CLKGATE_DIS);
}
/* Wa_14014830051:dg2 */
- wa_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
+ wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN);
/*
* The following are not actually "workarounds" but rather
* recommended tuning settings documented in the bspec's
* performance guide section.
*/
- wa_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
+ wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
/* Wa_14015795083 */
wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
@@ -1628,14 +1680,25 @@ wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal)
u32 val, old = 0;
/* open-coded rmw due to steering */
- old = wa->clr ? intel_gt_mcr_read_any_fw(gt, wa->reg) : 0;
+ if (wa->clr)
+ old = wa->is_mcr ?
+ intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_uncore_read_fw(uncore, wa->reg);
val = (old & ~wa->clr) | wa->set;
- if (val != old || !wa->clr)
- intel_uncore_write_fw(uncore, wa->reg, val);
+ if (val != old || !wa->clr) {
+ if (wa->is_mcr)
+ intel_gt_mcr_multicast_write_fw(gt, wa->reg, val);
+ else
+ intel_uncore_write_fw(uncore, wa->reg, val);
+ }
+
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
+ u32 val = wa->is_mcr ?
+ intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_uncore_read_fw(uncore, wa->reg);
- if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
- wa_verify(wa, intel_gt_mcr_read_any_fw(gt, wa->reg),
- wal->name, "application");
+ wa_verify(wa, val, wal->name, "application");
+ }
}
intel_uncore_forcewake_put__locked(uncore, fw);
@@ -1664,8 +1727,9 @@ static bool wa_list_verify(struct intel_gt *gt,
intel_uncore_forcewake_get__locked(uncore, fw);
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- ok &= wa_verify(wa,
- intel_gt_mcr_read_any_fw(gt, wa->reg),
+ ok &= wa_verify(wa, wa->is_mcr ?
+ intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_uncore_read_fw(uncore, wa->reg),
wal->name, from);
intel_uncore_forcewake_put__locked(uncore, fw);
@@ -1711,12 +1775,36 @@ whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
_wa_add(wal, &wa);
}
+static void
+whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
+{
+ struct i915_wa wa = {
+ .reg = reg,
+ .is_mcr = 1,
+ };
+
+ if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS))
+ return;
+
+ if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
+ return;
+
+ wa.reg.reg |= flags;
+ _wa_add(wal, &wa);
+}
+
static void
whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
{
whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
}
+static void
+whitelist_mcr_reg(struct i915_wa_list *wal, i915_reg_t reg)
+{
+ whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
+}
+
static void gen9_whitelist_build(struct i915_wa_list *w)
{
/* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt,glk,cfl */
@@ -1742,7 +1830,7 @@ static void skl_whitelist_build(struct intel_engine_cs *engine)
gen9_whitelist_build(w);
/* WaDisableLSQCROPERFforOCL:skl */
- whitelist_reg(w, GEN8_L3SQCREG4);
+ whitelist_mcr_reg(w, GEN8_L3SQCREG4);
}
static void bxt_whitelist_build(struct intel_engine_cs *engine)
@@ -1763,7 +1851,7 @@ static void kbl_whitelist_build(struct intel_engine_cs *engine)
gen9_whitelist_build(w);
/* WaDisableLSQCROPERFforOCL:kbl */
- whitelist_reg(w, GEN8_L3SQCREG4);
+ whitelist_mcr_reg(w, GEN8_L3SQCREG4);
}
static void glk_whitelist_build(struct intel_engine_cs *engine)
@@ -1828,10 +1916,10 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
switch (engine->class) {
case RENDER_CLASS:
/* WaAllowUMDToModifyHalfSliceChicken7:icl */
- whitelist_reg(w, GEN9_HALF_SLICE_CHICKEN7);
+ whitelist_mcr_reg(w, GEN9_HALF_SLICE_CHICKEN7);
/* WaAllowUMDToModifySamplerMode:icl */
- whitelist_reg(w, GEN10_SAMPLER_MODE);
+ whitelist_mcr_reg(w, GEN10_SAMPLER_MODE);
/* WaEnableStateCacheRedirectToCS:icl */
whitelist_reg(w, GEN9_SLICE_COMMON_ECO_CHICKEN1);
@@ -2107,24 +2195,24 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14013392000:dg2_g11 */
- wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_ENABLE_LARGE_GRF_MODE);
/* Wa_16011620976:dg2_g11 */
- wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
/* Wa_1509727124:dg2 */
- wa_masked_en(wal, GEN10_SAMPLER_MODE,
- SC_DISABLE_POWER_OPTIMIZATION_EBB);
+ wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE,
+ SC_DISABLE_POWER_OPTIMIZATION_EBB);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012419201:dg2 */
- wa_masked_en(wal, GEN9_ROW_CHICKEN4,
- GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX);
+ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4,
+ GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
@@ -2133,13 +2221,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* Wa_22012826095:dg2
* Wa_22013059131:dg2
*/
- wa_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
- MAXREQS_PER_BANK,
- REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
+ wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW,
+ MAXREQS_PER_BANK,
+ REG_FIELD_PREP(MAXREQS_PER_BANK, 2));
/* Wa_22013059131:dg2 */
- wa_write_or(wal, LSC_CHICKEN_BIT_0,
- FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0,
+ FORCE_1_SUB_MESSAGE_PER_FRAGMENT);
}
/* Wa_1308578152:dg2_g10 when first gslice is fused off */
@@ -2152,19 +2240,19 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
/* Wa_22013037850:dg2 */
- wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
- DISABLE_128B_EVICTION_COMMAND_UDW);
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
+ DISABLE_128B_EVICTION_COMMAND_UDW);
/* Wa_22012856258:dg2 */
- wa_masked_en(wal, GEN8_ROW_CHICKEN2,
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
GEN12_DISABLE_READ_SUPPRESSION);
/*
* Wa_22010960976:dg2
* Wa_14013347512:dg2
*/
- wa_masked_dis(wal, XEHP_HDC_CHICKEN0,
- LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
+ wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0,
+ LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
@@ -2172,7 +2260,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* Wa_1608949956:dg2_g10
* Wa_14010198302:dg2_g10
*/
- wa_masked_en(wal, GEN8_ROW_CHICKEN,
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE);
/*
@@ -2181,31 +2269,31 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* LSC_CHICKEN_BIT_0 always reads back as 0 is this stepping,
* so ignoring verification.
*/
- wa_add(wal, LSC_CHICKEN_BIT_0_UDW, 0,
- FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE,
- 0, false);
+ wa_mcr_add(wal, LSC_CHICKEN_BIT_0_UDW, 0,
+ FORCE_SLM_FENCE_SCOPE_TO_TILE | FORCE_UGM_FENCE_SCOPE_TO_TILE,
+ 0, false);
}
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0)) {
/* Wa_22010430635:dg2 */
- wa_masked_en(wal,
- GEN9_ROW_CHICKEN4,
- GEN12_DISABLE_GRF_CLEAR);
+ wa_mcr_masked_en(wal,
+ GEN9_ROW_CHICKEN4,
+ GEN12_DISABLE_GRF_CLEAR);
/* Wa_14010648519:dg2 */
- wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
+ wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
}
/* Wa_14013202645:dg2 */
if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_C0) ||
IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0))
- wa_write_or(wal, RT_CTRL, DIS_NULL_QUERY);
+ wa_mcr_write_or(wal, RT_CTRL, DIS_NULL_QUERY);
/* Wa_22012532006:dg2 */
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_C0) ||
IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0))
- wa_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
- DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
+ wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7,
+ DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA);
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0)) {
/* Wa_14010680813:dg2_g10 */
@@ -2216,17 +2304,17 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_A0, STEP_B0) ||
IS_DG2_GRAPHICS_STEP(engine->i915, G11, STEP_A0, STEP_B0)) {
/* Wa_14012362059:dg2 */
- wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
}
if (IS_DG2_GRAPHICS_STEP(i915, G11, STEP_B0, STEP_FOREVER) ||
IS_DG2_G10(i915)) {
/* Wa_22014600077:dg2 */
- wa_add(wal, GEN10_CACHE_MODE_SS, 0,
- _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),
- 0 /* Wa_14012342262 :write-only reg, so skip
- verification */,
- true);
+ wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
+ _MASKED_BIT_ENABLE(ENABLE_EU_COUNT_FOR_TDL_FLUSH),
+ 0 /* Wa_14012342262 :write-only reg, so skip
+ verification */,
+ true);
}
if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
@@ -2253,7 +2341,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_ALDERLAKE_P(i915) || IS_ALDERLAKE_S(i915) || IS_DG1(i915) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1606931601:tgl,rkl,dg1,adl-s,adl-p */
- wa_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ);
/*
* Wa_1407928979:tgl A*
@@ -2282,14 +2370,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915)) {
/* Wa_1409804808:tgl,rkl,dg1[a0],adl-s,adl-p */
- wa_masked_en(wal, GEN8_ROW_CHICKEN2,
- GEN12_PUSH_CONST_DEREF_HOLD_DIS);
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
+ GEN12_PUSH_CONST_DEREF_HOLD_DIS);
/*
* Wa_1409085225:tgl
* Wa_14010229206:tgl,rkl,dg1[a0],adl-s,adl-p
*/
- wa_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
+ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH);
}
if (IS_DG1_GRAPHICS_STEP(i915, STEP_A0, STEP_B0) ||
@@ -2313,9 +2401,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || IS_TIGERLAKE(i915) ||
IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
/* Wa_1406941453:tgl,rkl,dg1,adl-s,adl-p */
- wa_masked_en(wal,
- GEN10_SAMPLER_MODE,
- ENABLE_SMALLPL);
+ wa_mcr_masked_en(wal,
+ GEN10_SAMPLER_MODE,
+ ENABLE_SMALLPL);
}
if (GRAPHICS_VER(i915) == 11) {
@@ -2349,9 +2437,9 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* Wa_1405733216:icl
* Formerly known as WaDisableCleanEvicts
*/
- wa_write_or(wal,
- GEN8_L3SQCREG4,
- GEN11_LQSC_CLEAN_EVICT_DISABLE);
+ wa_mcr_write_or(wal,
+ GEN8_L3SQCREG4,
+ GEN11_LQSC_CLEAN_EVICT_DISABLE);
/* Wa_1606682166:icl */
wa_write_or(wal,
@@ -2359,10 +2447,10 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN7_DISABLE_SAMPLER_PREFETCH);
/* Wa_1409178092:icl */
- wa_write_clr_set(wal,
- GEN11_SCRATCH2,
- GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
- 0);
+ wa_mcr_write_clr_set(wal,
+ GEN11_SCRATCH2,
+ GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE,
+ 0);
/* WaEnable32PlaneMode:icl */
wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,
@@ -2420,30 +2508,30 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE);
/* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl,glk,cfl */
- wa_write_or(wal,
- BDW_SCRATCH1,
- GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
+ wa_mcr_write_or(wal,
+ BDW_SCRATCH1,
+ GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
/* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */
if (IS_GEN9_LP(i915))
- wa_write_clr_set(wal,
- GEN8_L3SQCREG1,
- L3_PRIO_CREDITS_MASK,
- L3_GENERAL_PRIO_CREDITS(62) |
- L3_HIGH_PRIO_CREDITS(2));
+ wa_mcr_write_clr_set(wal,
+ GEN8_L3SQCREG1,
+ L3_PRIO_CREDITS_MASK,
+ L3_GENERAL_PRIO_CREDITS(62) |
+ L3_HIGH_PRIO_CREDITS(2));
/* WaOCLCoherentLineFlush:skl,bxt,kbl,cfl */
- wa_write_or(wal,
- GEN8_L3SQCREG4,
- GEN8_LQSC_FLUSH_COHERENT_LINES);
+ wa_mcr_write_or(wal,
+ GEN8_L3SQCREG4,
+ GEN8_LQSC_FLUSH_COHERENT_LINES);
/* Disable atomics in L3 to prevent unrecoverable hangs */
wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1,
GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE, 0);
- wa_write_clr_set(wal, GEN8_L3SQCREG4,
- GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
- wa_write_clr_set(wal, GEN9_SCRATCH1,
- EVICTION_PERF_FIX_ENABLE, 0);
+ wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4,
+ GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE, 0);
+ wa_mcr_write_clr_set(wal, GEN9_SCRATCH1,
+ EVICTION_PERF_FIX_ENABLE, 0);
}
if (IS_HASWELL(i915)) {
@@ -2657,7 +2745,7 @@ ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
{
if (IS_PVC_CT_STEP(engine->i915, STEP_A0, STEP_C0)) {
/* Wa_14014999345:pvc */
- wa_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC);
+ wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC);
}
}
@@ -2683,8 +2771,8 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
}
if (IS_DG2(i915)) {
- wa_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
- wa_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
+ wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+ wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
/*
* This is also listed as Wa_22012654132 for certain DG2
@@ -2695,10 +2783,10 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
* back for verification on DG2 (due to Wa_14012342262), so
* we need to explicitly skip the readback.
*/
- wa_add(wal, GEN10_CACHE_MODE_SS, 0,
- _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
- 0 /* write-only, so skip validation */,
- true);
+ wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,
+ _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC),
+ 0 /* write-only, so skip validation */,
+ true);
}
/*
@@ -2707,8 +2795,8 @@ add_render_compute_tuning_settings(struct drm_i915_private *i915,
* platforms.
*/
if (INTEL_INFO(i915)->tuning_thread_rr_after_dep)
- wa_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
- THREAD_EX_ARB_MODE_RR_AFTER_DEP);
+ wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE,
+ THREAD_EX_ARB_MODE_RR_AFTER_DEP);
}
/*
@@ -2734,30 +2822,30 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
if (IS_XEHPSDV(i915)) {
/* Wa_1409954639 */
- wa_masked_en(wal,
- GEN8_ROW_CHICKEN,
- SYSTOLIC_DOP_CLOCK_GATING_DIS);
+ wa_mcr_masked_en(wal,
+ GEN8_ROW_CHICKEN,
+ SYSTOLIC_DOP_CLOCK_GATING_DIS);
/* Wa_1607196519 */
- wa_masked_en(wal,
- GEN9_ROW_CHICKEN4,
- GEN12_DISABLE_GRF_CLEAR);
+ wa_mcr_masked_en(wal,
+ GEN9_ROW_CHICKEN4,
+ GEN12_DISABLE_GRF_CLEAR);
/* Wa_14010670810:xehpsdv */
- wa_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
+ wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE);
/* Wa_14010449647:xehpsdv */
- wa_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
- GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
+ wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1,
+ GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE);
/* Wa_18011725039:xehpsdv */
if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A1, STEP_B0)) {
- wa_masked_dis(wal, MLTICTXCTL, TDONRENDER);
- wa_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
+ wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER);
+ wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH);
}
/* Wa_14012362059:xehpsdv */
- wa_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB);
/* Wa_14014368820:xehpsdv */
wa_write_or(wal, GEN12_GAMCNTRL_CTRL, INVALIDATION_BROADCAST_MODE_DIS |
@@ -2766,19 +2854,19 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li
if (IS_DG2(i915) || IS_PONTEVECCHIO(i915)) {
/* Wa_14015227452:dg2,pvc */
- wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
+ wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE);
/* Wa_22014226127:dg2,pvc */
- wa_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE);
/* Wa_16015675438:dg2,pvc */
wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE);
/* Wa_18018781329:dg2,pvc */
- wa_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
- wa_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VDBX_MOD_CTRL, FORCE_MISS_FTLB);
+ wa_mcr_write_or(wal, VEBX_MOD_CTRL, FORCE_MISS_FTLB);
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
index 8a4b6de4e754..f05b37e56fa9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
@@ -15,7 +15,9 @@ struct i915_wa {
u32 clr;
u32 set;
u32 read;
- bool masked_reg;
+
+ u32 masked_reg:1;
+ u32 is_mcr:1;
};
struct i915_wa_list {
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 10/12] drm/i915: Define multicast registers as a new type
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Rather than treating multicast registers as 'i915_reg_t' let's define
them as a completely new type. This will allow the compiler to help us
make sure we're using multicast-aware functions to operate on multicast
registers.
This plan does break down a bit in places where we're just maintaining
heterogeneous lists of registers (e.g., various MMIO whitelists used by
perf, GVT, etc.) rather than performing reads/writes. We only really
care about the offset in those cases, so for now we can "cast" the
registers as non-MCR, leaving us with a list of i915_reg_t's, but we may
want to look for better ways to store mixed collections of i915_reg_t
and i915_mcr_reg_t in the future.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 49 ++++++++++++-------
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 14 +++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 27 +++++++---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++++++------
.../gpu/drm/i915/gt/intel_workarounds_types.h | 5 +-
.../gpu/drm/i915/gt/selftest_workarounds.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_capture.c | 4 +-
drivers/gpu/drm/i915/gvt/handlers.c | 17 ++++---
drivers/gpu/drm/i915/gvt/mmio_context.c | 14 +++---
drivers/gpu/drm/i915/i915_reg_defs.h | 22 +++------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 10 ++--
12 files changed, 112 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index e79405a45312..8f9009af3673 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -134,6 +134,19 @@ void intel_gt_mcr_init(struct intel_gt *gt)
}
}
+/*
+ * Although the rest of the driver should use MCR-specific functions to
+ * read/write MCR registers, we still use the regular intel_uncore_* functions
+ * internally to implement those, so we need a way for the functions in this
+ * file to "cast" an i915_mcr_reg_t into an i915_reg_t.
+ */
+static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr)
+{
+ i915_reg_t r = { .reg = mcr.reg };
+
+ return r;
+}
+
/*
* rw_with_mcr_steering_fw - Access a register with specific MCR steering
* @uncore: pointer to struct intel_uncore
@@ -148,7 +161,7 @@ void intel_gt_mcr_init(struct intel_gt *gt)
* Caller needs to make sure the relevant forcewake wells are up.
*/
static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
- i915_reg_t reg, u8 rw_flag,
+ i915_mcr_reg_t reg, u8 rw_flag,
int group, int instance, u32 value)
{
u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;
@@ -185,9 +198,9 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
if (rw_flag == FW_REG_READ)
- val = intel_uncore_read_fw(uncore, reg);
+ val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg));
else
- intel_uncore_write_fw(uncore, reg, value);
+ intel_uncore_write_fw(uncore, mcr_reg_cast(reg), value);
mcr &= ~mcr_mask;
mcr |= old_mcr & mcr_mask;
@@ -198,14 +211,14 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
}
static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
- i915_reg_t reg, u8 rw_flag,
+ i915_mcr_reg_t reg, u8 rw_flag,
int group, int instance,
u32 value)
{
enum forcewake_domains fw_domains;
u32 val;
- fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
+ fw_domains = intel_uncore_forcewake_for_reg(uncore, mcr_reg_cast(reg),
rw_flag);
fw_domains |= intel_uncore_forcewake_for_reg(uncore,
GEN8_MCR_SELECTOR,
@@ -233,7 +246,7 @@ static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
* group/instance.
*/
u32 intel_gt_mcr_read(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
int group, int instance)
{
return rw_with_mcr_steering(gt->uncore, reg, FW_REG_READ, group, instance, 0);
@@ -250,7 +263,7 @@ u32 intel_gt_mcr_read(struct intel_gt *gt,
* Write an MCR register in unicast mode after steering toward a specific
* group/instance.
*/
-void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_reg_t reg, u32 value,
+void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value,
int group, int instance)
{
rw_with_mcr_steering(gt->uncore, reg, FW_REG_WRITE, group, instance, value);
@@ -265,9 +278,9 @@ void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_reg_t reg, u32 value,
* Write an MCR register in multicast mode to update all instances.
*/
void intel_gt_mcr_multicast_write(struct intel_gt *gt,
- i915_reg_t reg, u32 value)
+ i915_mcr_reg_t reg, u32 value)
{
- intel_uncore_write(gt->uncore, reg, value);
+ intel_uncore_write(gt->uncore, mcr_reg_cast(reg), value);
}
/**
@@ -281,9 +294,9 @@ void intel_gt_mcr_multicast_write(struct intel_gt *gt,
* domains; use intel_gt_mcr_multicast_write() in cases where forcewake should
* be obtained automatically.
*/
-void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 value)
+void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)
{
- intel_uncore_write_fw(gt->uncore, reg, value);
+ intel_uncore_write_fw(gt->uncore, mcr_reg_cast(reg), value);
}
/*
@@ -301,10 +314,10 @@ void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 va
* for @type steering too.
*/
static bool reg_needs_read_steering(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
enum intel_steering_type type)
{
- const u32 offset = i915_mmio_reg_offset(reg);
+ const u32 offset = i915_mmio_reg_offset(mcr_reg_cast(reg));
const struct intel_mmio_range *entry;
if (likely(!gt->steering_table[type]))
@@ -380,7 +393,7 @@ static void get_nonterminated_steering(struct intel_gt *gt,
* steering.
*/
void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
u8 *group, u8 *instance)
{
int type;
@@ -409,7 +422,7 @@ void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
*
* Returns the value from a non-terminated instance of @reg.
*/
-u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg)
+u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg)
{
int type;
u8 group, instance;
@@ -423,7 +436,7 @@ u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg)
}
}
- return intel_uncore_read_fw(gt->uncore, reg);
+ return intel_uncore_read_fw(gt->uncore, mcr_reg_cast(reg));
}
/**
@@ -436,7 +449,7 @@ u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg)
*
* Returns the value from a non-terminated instance of @reg.
*/
-u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg)
+u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg)
{
int type;
u8 group, instance;
@@ -450,7 +463,7 @@ u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg)
}
}
- return intel_uncore_read(gt->uncore, reg);
+ return intel_uncore_read(gt->uncore, mcr_reg_cast(reg));
}
static void report_steering_type(struct drm_printer *p,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
index 77a8b11c287d..907e751fa9f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
@@ -11,21 +11,21 @@
void intel_gt_mcr_init(struct intel_gt *gt);
u32 intel_gt_mcr_read(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
int group, int instance);
-u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg);
-u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg);
+u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg);
+u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg);
void intel_gt_mcr_unicast_write(struct intel_gt *gt,
- i915_reg_t reg, u32 value,
+ i915_mcr_reg_t reg, u32 value,
int group, int instance);
void intel_gt_mcr_multicast_write(struct intel_gt *gt,
- i915_reg_t reg, u32 value);
+ i915_mcr_reg_t reg, u32 value);
void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt,
- i915_reg_t reg, u32 value);
+ i915_mcr_reg_t reg, u32 value);
void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
u8 *group, u8 *instance);
void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f96cf08cd31e..4b5692d84858 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -8,7 +8,18 @@
#include "i915_reg_defs.h"
-#define MCR_REG(offset) _MMIO(offset)
+#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
+
+/*
+ * The perf control registers are technically multicast registers, but the
+ * driver never needs to read/write them directly; we only use them to build
+ * lists of registers (where they're mixed in with other non-MCR registers)
+ * and then operate on the offset directly. For now we'll just define them
+ * as non-multicast so we can place them on the same list, but we may want
+ * to try to come up with a better way to handle heterogeneous lists of
+ * registers in the future.
+ */
+#define PERF_REG(offset) _MMIO(offset)
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
@@ -1107,8 +1118,8 @@
#define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
-#define EU_PERF_CNTL0 MCR_REG(0xe458)
-#define EU_PERF_CNTL4 MCR_REG(0xe45c)
+#define EU_PERF_CNTL0 PERF_REG(0xe458)
+#define EU_PERF_CNTL4 PERF_REG(0xe45c)
#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
@@ -1145,16 +1156,16 @@
#define STACKID_CTRL REG_GENMASK(6, 5)
#define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2)
-#define EU_PERF_CNTL1 MCR_REG(0xe558)
-#define EU_PERF_CNTL5 MCR_REG(0xe55c)
+#define EU_PERF_CNTL1 PERF_REG(0xe558)
+#define EU_PERF_CNTL5 PERF_REG(0xe55c)
#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define ICL_HDC_MODE MCR_REG(0xe5f4)
-#define EU_PERF_CNTL2 MCR_REG(0xe658)
-#define EU_PERF_CNTL6 MCR_REG(0xe65c)
-#define EU_PERF_CNTL3 MCR_REG(0xe758)
+#define EU_PERF_CNTL2 PERF_REG(0xe658)
+#define EU_PERF_CNTL6 PERF_REG(0xe65c)
+#define EU_PERF_CNTL3 PERF_REG(0xe758)
#define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8)
#define DISABLE_D8_D16_COASLESCE REG_BIT(30)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f98213b7c61d..0f18872a7995 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -166,11 +166,11 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
_wa_add(wal, &wa);
}
-static void wa_mcr_add(struct i915_wa_list *wal, i915_reg_t reg,
+static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg,
u32 clear, u32 set, u32 read_mask, bool masked_reg)
{
struct i915_wa wa = {
- .reg = reg,
+ .mcr_reg = reg,
.clr = clear,
.set = set,
.read = read_mask,
@@ -188,7 +188,7 @@ wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
}
static void
-wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
+wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set)
{
wa_mcr_add(wal, reg, clear, set, clear, false);
}
@@ -206,7 +206,7 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
}
static void
-wa_mcr_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
+wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
{
wa_mcr_write_clr_set(wal, reg, set, set);
}
@@ -218,7 +218,7 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
}
static void
-wa_mcr_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
+wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr)
{
wa_mcr_write_clr_set(wal, reg, clr, 0);
}
@@ -241,7 +241,7 @@ wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
}
static void
-wa_mcr_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
{
wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
}
@@ -253,7 +253,7 @@ wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
}
static void
-wa_mcr_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
{
wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
}
@@ -266,7 +266,7 @@ wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
}
static void
-wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
+wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg,
u32 mask, u32 val)
{
wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
@@ -1682,19 +1682,19 @@ wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal)
/* open-coded rmw due to steering */
if (wa->clr)
old = wa->is_mcr ?
- intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
intel_uncore_read_fw(uncore, wa->reg);
val = (old & ~wa->clr) | wa->set;
if (val != old || !wa->clr) {
if (wa->is_mcr)
- intel_gt_mcr_multicast_write_fw(gt, wa->reg, val);
+ intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val);
else
intel_uncore_write_fw(uncore, wa->reg, val);
}
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
u32 val = wa->is_mcr ?
- intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
intel_uncore_read_fw(uncore, wa->reg);
wa_verify(wa, val, wal->name, "application");
@@ -1728,7 +1728,7 @@ static bool wa_list_verify(struct intel_gt *gt,
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
ok &= wa_verify(wa, wa->is_mcr ?
- intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
intel_uncore_read_fw(uncore, wa->reg),
wal->name, from);
@@ -1776,10 +1776,10 @@ whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
}
static void
-whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
+whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags)
{
struct i915_wa wa = {
- .reg = reg,
+ .mcr_reg = reg,
.is_mcr = 1,
};
@@ -1789,7 +1789,7 @@ whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
return;
- wa.reg.reg |= flags;
+ wa.mcr_reg.reg |= flags;
_wa_add(wal, &wa);
}
@@ -1800,7 +1800,7 @@ whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
}
static void
-whitelist_mcr_reg(struct i915_wa_list *wal, i915_reg_t reg)
+whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg)
{
whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
index f05b37e56fa9..7c8b01d00043 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
@@ -11,7 +11,10 @@
#include "i915_reg_defs.h"
struct i915_wa {
- i915_reg_t reg;
+ union {
+ i915_reg_t reg;
+ i915_mcr_reg_t mcr_reg;
+ };
u32 clr;
u32 set;
u32 read;
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 67a9aab801dd..21b1edc052f8 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -991,7 +991,7 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
/* Alas, we must pardon some whitelists. Mistakes already made */
static const struct regmask pardon[] = {
{ GEN9_CTX_PREEMPT_REG, 9 },
- { GEN8_L3SQCREG4, 9 },
+ { _MMIO(0xb118), 9 }, /* GEN8_L3SQCREG4 */
};
return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index b5d3e3ef1787..31eee994e91c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -327,7 +327,7 @@ static long __must_check guc_mmio_reg_add(struct intel_gt *gt,
static long __must_check guc_mcr_reg_add(struct intel_gt *gt,
struct temp_regset *regset,
- i915_reg_t reg, u32 flags)
+ i915_mcr_reg_t reg, u32 flags)
{
u8 group, inst;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 9495a7928bc8..d5c03e7a7843 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -240,7 +240,7 @@ static void guc_capture_free_extlists(struct __guc_mmio_reg_descr_group *reglist
struct __ext_steer_reg {
const char *name;
- i915_reg_t reg;
+ i915_mcr_reg_t reg;
};
static const struct __ext_steer_reg xe_extregs[] = {
@@ -252,7 +252,7 @@ static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
const struct __ext_steer_reg *extlist,
int slice_id, int subslice_id)
{
- ext->reg = extlist->reg;
+ ext->reg = _MMIO(i915_mmio_reg_offset(extlist->reg));
ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id);
ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id);
ext->regname = extlist->name;
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 700cc9688f47..a52c4645cdbe 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -734,7 +734,7 @@ static i915_reg_t force_nonpriv_white_list[] = {
_MMIO(0x770c),
_MMIO(0x83a8),
_MMIO(0xb110),
- GEN8_L3SQCREG4,//_MMIO(0xb118)
+ _MMIO(0xb118),
_MMIO(0xe100),
_MMIO(0xe18c),
_MMIO(0xe48c),
@@ -2140,6 +2140,9 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
#define MMIO_DFH(reg, d, f, r, w) \
MMIO_F(reg, 4, f, 0, 0, d, r, w)
+#define MMIO_DFH_MCR(reg, d, f, r, w) \
+ MMIO_F(_MMIO(i915_mmio_reg_offset(reg)), 4, f, 0, 0, d, r, w)
+
#define MMIO_GM(reg, d, r, w) \
MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
@@ -2529,15 +2532,15 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt)
MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
+ MMIO_DFH_MCR(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
NULL, NULL);
MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH_MCR(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
@@ -2550,7 +2553,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt)
MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH_MCR(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
@@ -2699,7 +2702,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
- MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH_MCR(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
NULL, NULL);
@@ -2769,7 +2772,7 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
bxt_port_tx_dw3_read, NULL);
MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
- MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH_MCR(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index ac58460fb305..b5b51e4f28da 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -44,6 +44,8 @@
#define GEN9_MOCS_SIZE 64
+#define MCR_CAST(mcr) _MMIO(i915_mcr_reg_offset(mcr))
+
/* Raw offset is appened to each line for convenience. */
static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
@@ -106,15 +108,15 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
{RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
{RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
{RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
- {RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
- {RCS0, GEN9_SCRATCH1, 0, false}, /* 0xb11c */
+ {RCS0, _MMIO(0xb118), 0, false}, /* GEN8_L3SQCREG4 */
+ {RCS0, _MMIO(0xb11c), 0, false}, /* GEN9_SCRATCH1 */
{RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
- {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
+ {RCS0, _MMIO(0xe180), 0xffff, true}, /* HALF_SLICE_CHICKEN2 */
{RCS0, HSW_HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
- {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
- {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
- {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
+ {RCS0, _MMIO(0xe188), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN5 */
+ {RCS0, _MMIO(0xe194), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN7 */
+ {RCS0, _MMIO(0xe4f0), 0xffff, true}, /* GEN8_ROW_CHICKEN */
{RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */
{RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */
{RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index 8f486f77609f..e823869b9afd 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -104,22 +104,16 @@ typedef struct {
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
-#define INVALID_MMIO_REG _MMIO(0)
-
-static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
-{
- return reg.reg;
-}
+typedef struct {
+ u32 reg;
+} i915_mcr_reg_t;
-static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
-{
- return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
-}
+#define INVALID_MMIO_REG _MMIO(0)
-static inline bool i915_mmio_reg_valid(i915_reg_t reg)
-{
- return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
-}
+/* These macros can be used on either i915_reg_t or i915_mcr_reg_t */
+#define i915_mmio_reg_offset(r) (r.reg)
+#define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))
+#define i915_mmio_reg_valid(r) (!i915_mmio_reg_equal(r, INVALID_MMIO_REG))
#define VLV_DISPLAY_BASE 0x180000
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 638b77d64bf4..8c1515f5c04c 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -816,10 +816,10 @@ static int iterate_bdw_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(GEN8_EU_DISABLE1);
MMIO_D(GEN8_EU_DISABLE2);
MMIO_D(_MMIO(0xfdc));
- MMIO_D(GEN8_ROW_CHICKEN);
+ MMIO_D(_MMIO(0xe4f0)); /* GEN8_ROW_CHICKEN */
MMIO_D(GEN7_ROW_CHICKEN2);
MMIO_D(GEN8_UCGCTL6);
- MMIO_D(GEN8_L3SQCREG4);
+ MMIO_D(_MMIO(0xb118)); /* GEN8_L3SQCREG4 */
MMIO_D(GEN9_SCRATCH_LNCF1);
MMIO_F(_MMIO(0x24d0), 48);
MMIO_D(_MMIO(0x44484));
@@ -831,7 +831,7 @@ static int iterate_bdw_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x65f10));
MMIO_D(_MMIO(0xe194));
MMIO_D(_MMIO(0xe188));
- MMIO_D(HALF_SLICE_CHICKEN2);
+ MMIO_D(_MMIO(0xe180)); /* HALF_SLICE_CHICKEN2 */
MMIO_D(_MMIO(0x2580));
MMIO_D(_MMIO(0xe220));
MMIO_D(_MMIO(0xe230));
@@ -1025,7 +1025,7 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(DMC_SSP_BASE);
MMIO_D(DMC_HTP_SKL);
MMIO_D(DMC_LAST_WRITE);
- MMIO_D(BDW_SCRATCH1);
+ MMIO_D(_MMIO(0xb11c)); /* BDW_SCRATCH1 */
MMIO_D(SKL_DFSM);
MMIO_D(DISPIO_CR_TX_BMU_CR0);
MMIO_F(GEN9_GFX_MOCS(0), 0x7f8);
@@ -1228,7 +1228,7 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(GEN8_PUSHBUS_ENABLE);
MMIO_D(GEN8_PUSHBUS_SHIFT);
MMIO_D(GEN6_GFXPAUSE);
- MMIO_D(GEN8_L3SQCREG1);
+ MMIO_D(_MMIO(0xb100)); /* GEN8_L3SQCREG1 */
MMIO_D(GEN8_L3CNTLREG);
MMIO_D(_MMIO(0x20D8));
MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40);
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH 10/12] drm/i915: Define multicast registers as a new type
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Rather than treating multicast registers as 'i915_reg_t' let's define
them as a completely new type. This will allow the compiler to help us
make sure we're using multicast-aware functions to operate on multicast
registers.
This plan does break down a bit in places where we're just maintaining
heterogeneous lists of registers (e.g., various MMIO whitelists used by
perf, GVT, etc.) rather than performing reads/writes. We only really
care about the offset in those cases, so for now we can "cast" the
registers as non-MCR, leaving us with a list of i915_reg_t's, but we may
want to look for better ways to store mixed collections of i915_reg_t
and i915_mcr_reg_t in the future.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 49 ++++++++++++-------
drivers/gpu/drm/i915/gt/intel_gt_mcr.h | 14 +++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 27 +++++++---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++++++------
.../gpu/drm/i915/gt/intel_workarounds_types.h | 5 +-
.../gpu/drm/i915/gt/selftest_workarounds.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 +-
.../gpu/drm/i915/gt/uc/intel_guc_capture.c | 4 +-
drivers/gpu/drm/i915/gvt/handlers.c | 17 ++++---
drivers/gpu/drm/i915/gvt/mmio_context.c | 14 +++---
drivers/gpu/drm/i915/i915_reg_defs.h | 22 +++------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 10 ++--
12 files changed, 112 insertions(+), 86 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index e79405a45312..8f9009af3673 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -134,6 +134,19 @@ void intel_gt_mcr_init(struct intel_gt *gt)
}
}
+/*
+ * Although the rest of the driver should use MCR-specific functions to
+ * read/write MCR registers, we still use the regular intel_uncore_* functions
+ * internally to implement those, so we need a way for the functions in this
+ * file to "cast" an i915_mcr_reg_t into an i915_reg_t.
+ */
+static i915_reg_t mcr_reg_cast(const i915_mcr_reg_t mcr)
+{
+ i915_reg_t r = { .reg = mcr.reg };
+
+ return r;
+}
+
/*
* rw_with_mcr_steering_fw - Access a register with specific MCR steering
* @uncore: pointer to struct intel_uncore
@@ -148,7 +161,7 @@ void intel_gt_mcr_init(struct intel_gt *gt)
* Caller needs to make sure the relevant forcewake wells are up.
*/
static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
- i915_reg_t reg, u8 rw_flag,
+ i915_mcr_reg_t reg, u8 rw_flag,
int group, int instance, u32 value)
{
u32 mcr_mask, mcr_ss, mcr, old_mcr, val = 0;
@@ -185,9 +198,9 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
if (rw_flag == FW_REG_READ)
- val = intel_uncore_read_fw(uncore, reg);
+ val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg));
else
- intel_uncore_write_fw(uncore, reg, value);
+ intel_uncore_write_fw(uncore, mcr_reg_cast(reg), value);
mcr &= ~mcr_mask;
mcr |= old_mcr & mcr_mask;
@@ -198,14 +211,14 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
}
static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
- i915_reg_t reg, u8 rw_flag,
+ i915_mcr_reg_t reg, u8 rw_flag,
int group, int instance,
u32 value)
{
enum forcewake_domains fw_domains;
u32 val;
- fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
+ fw_domains = intel_uncore_forcewake_for_reg(uncore, mcr_reg_cast(reg),
rw_flag);
fw_domains |= intel_uncore_forcewake_for_reg(uncore,
GEN8_MCR_SELECTOR,
@@ -233,7 +246,7 @@ static u32 rw_with_mcr_steering(struct intel_uncore *uncore,
* group/instance.
*/
u32 intel_gt_mcr_read(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
int group, int instance)
{
return rw_with_mcr_steering(gt->uncore, reg, FW_REG_READ, group, instance, 0);
@@ -250,7 +263,7 @@ u32 intel_gt_mcr_read(struct intel_gt *gt,
* Write an MCR register in unicast mode after steering toward a specific
* group/instance.
*/
-void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_reg_t reg, u32 value,
+void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value,
int group, int instance)
{
rw_with_mcr_steering(gt->uncore, reg, FW_REG_WRITE, group, instance, value);
@@ -265,9 +278,9 @@ void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_reg_t reg, u32 value,
* Write an MCR register in multicast mode to update all instances.
*/
void intel_gt_mcr_multicast_write(struct intel_gt *gt,
- i915_reg_t reg, u32 value)
+ i915_mcr_reg_t reg, u32 value)
{
- intel_uncore_write(gt->uncore, reg, value);
+ intel_uncore_write(gt->uncore, mcr_reg_cast(reg), value);
}
/**
@@ -281,9 +294,9 @@ void intel_gt_mcr_multicast_write(struct intel_gt *gt,
* domains; use intel_gt_mcr_multicast_write() in cases where forcewake should
* be obtained automatically.
*/
-void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 value)
+void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value)
{
- intel_uncore_write_fw(gt->uncore, reg, value);
+ intel_uncore_write_fw(gt->uncore, mcr_reg_cast(reg), value);
}
/*
@@ -301,10 +314,10 @@ void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_reg_t reg, u32 va
* for @type steering too.
*/
static bool reg_needs_read_steering(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
enum intel_steering_type type)
{
- const u32 offset = i915_mmio_reg_offset(reg);
+ const u32 offset = i915_mmio_reg_offset(mcr_reg_cast(reg));
const struct intel_mmio_range *entry;
if (likely(!gt->steering_table[type]))
@@ -380,7 +393,7 @@ static void get_nonterminated_steering(struct intel_gt *gt,
* steering.
*/
void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
u8 *group, u8 *instance)
{
int type;
@@ -409,7 +422,7 @@ void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
*
* Returns the value from a non-terminated instance of @reg.
*/
-u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg)
+u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg)
{
int type;
u8 group, instance;
@@ -423,7 +436,7 @@ u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg)
}
}
- return intel_uncore_read_fw(gt->uncore, reg);
+ return intel_uncore_read_fw(gt->uncore, mcr_reg_cast(reg));
}
/**
@@ -436,7 +449,7 @@ u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg)
*
* Returns the value from a non-terminated instance of @reg.
*/
-u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg)
+u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg)
{
int type;
u8 group, instance;
@@ -450,7 +463,7 @@ u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg)
}
}
- return intel_uncore_read(gt->uncore, reg);
+ return intel_uncore_read(gt->uncore, mcr_reg_cast(reg));
}
static void report_steering_type(struct drm_printer *p,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
index 77a8b11c287d..907e751fa9f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.h
@@ -11,21 +11,21 @@
void intel_gt_mcr_init(struct intel_gt *gt);
u32 intel_gt_mcr_read(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
int group, int instance);
-u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_reg_t reg);
-u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_reg_t reg);
+u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg);
+u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg);
void intel_gt_mcr_unicast_write(struct intel_gt *gt,
- i915_reg_t reg, u32 value,
+ i915_mcr_reg_t reg, u32 value,
int group, int instance);
void intel_gt_mcr_multicast_write(struct intel_gt *gt,
- i915_reg_t reg, u32 value);
+ i915_mcr_reg_t reg, u32 value);
void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt,
- i915_reg_t reg, u32 value);
+ i915_mcr_reg_t reg, u32 value);
void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt,
- i915_reg_t reg,
+ i915_mcr_reg_t reg,
u8 *group, u8 *instance);
void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt,
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f96cf08cd31e..4b5692d84858 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -8,7 +8,18 @@
#include "i915_reg_defs.h"
-#define MCR_REG(offset) _MMIO(offset)
+#define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) })
+
+/*
+ * The perf control registers are technically multicast registers, but the
+ * driver never needs to read/write them directly; we only use them to build
+ * lists of registers (where they're mixed in with other non-MCR registers)
+ * and then operate on the offset directly. For now we'll just define them
+ * as non-multicast so we can place them on the same list, but we may want
+ * to try to come up with a better way to handle heterogeneous lists of
+ * registers in the future.
+ */
+#define PERF_REG(offset) _MMIO(offset)
/* RPM unit config (Gen8+) */
#define RPM_CONFIG0 _MMIO(0xd00)
@@ -1107,8 +1118,8 @@
#define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4)
#define ENABLE_PREFETCH_INTO_IC REG_BIT(3)
-#define EU_PERF_CNTL0 MCR_REG(0xe458)
-#define EU_PERF_CNTL4 MCR_REG(0xe45c)
+#define EU_PERF_CNTL0 PERF_REG(0xe458)
+#define EU_PERF_CNTL4 PERF_REG(0xe45c)
#define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c)
#define GEN12_DISABLE_GRF_CLEAR REG_BIT(13)
@@ -1145,16 +1156,16 @@
#define STACKID_CTRL REG_GENMASK(6, 5)
#define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2)
-#define EU_PERF_CNTL1 MCR_REG(0xe558)
-#define EU_PERF_CNTL5 MCR_REG(0xe55c)
+#define EU_PERF_CNTL1 PERF_REG(0xe558)
+#define EU_PERF_CNTL5 PERF_REG(0xe55c)
#define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0)
#define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11)
#define ICL_HDC_MODE MCR_REG(0xe5f4)
-#define EU_PERF_CNTL2 MCR_REG(0xe658)
-#define EU_PERF_CNTL6 MCR_REG(0xe65c)
-#define EU_PERF_CNTL3 MCR_REG(0xe758)
+#define EU_PERF_CNTL2 PERF_REG(0xe658)
+#define EU_PERF_CNTL6 PERF_REG(0xe65c)
+#define EU_PERF_CNTL3 PERF_REG(0xe758)
#define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8)
#define DISABLE_D8_D16_COASLESCE REG_BIT(30)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index f98213b7c61d..0f18872a7995 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -166,11 +166,11 @@ static void wa_add(struct i915_wa_list *wal, i915_reg_t reg,
_wa_add(wal, &wa);
}
-static void wa_mcr_add(struct i915_wa_list *wal, i915_reg_t reg,
+static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg,
u32 clear, u32 set, u32 read_mask, bool masked_reg)
{
struct i915_wa wa = {
- .reg = reg,
+ .mcr_reg = reg,
.clr = clear,
.set = set,
.read = read_mask,
@@ -188,7 +188,7 @@ wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
}
static void
-wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set)
+wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set)
{
wa_mcr_add(wal, reg, clear, set, clear, false);
}
@@ -206,7 +206,7 @@ wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
}
static void
-wa_mcr_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set)
+wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set)
{
wa_mcr_write_clr_set(wal, reg, set, set);
}
@@ -218,7 +218,7 @@ wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
}
static void
-wa_mcr_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr)
+wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr)
{
wa_mcr_write_clr_set(wal, reg, clr, 0);
}
@@ -241,7 +241,7 @@ wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
}
static void
-wa_mcr_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
{
wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true);
}
@@ -253,7 +253,7 @@ wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
}
static void
-wa_mcr_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val)
{
wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true);
}
@@ -266,7 +266,7 @@ wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
}
static void
-wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg,
+wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg,
u32 mask, u32 val)
{
wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true);
@@ -1682,19 +1682,19 @@ wa_list_apply(struct intel_gt *gt, const struct i915_wa_list *wal)
/* open-coded rmw due to steering */
if (wa->clr)
old = wa->is_mcr ?
- intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
intel_uncore_read_fw(uncore, wa->reg);
val = (old & ~wa->clr) | wa->set;
if (val != old || !wa->clr) {
if (wa->is_mcr)
- intel_gt_mcr_multicast_write_fw(gt, wa->reg, val);
+ intel_gt_mcr_multicast_write_fw(gt, wa->mcr_reg, val);
else
intel_uncore_write_fw(uncore, wa->reg, val);
}
if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
u32 val = wa->is_mcr ?
- intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
intel_uncore_read_fw(uncore, wa->reg);
wa_verify(wa, val, wal->name, "application");
@@ -1728,7 +1728,7 @@ static bool wa_list_verify(struct intel_gt *gt,
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
ok &= wa_verify(wa, wa->is_mcr ?
- intel_gt_mcr_read_any_fw(gt, wa->reg) :
+ intel_gt_mcr_read_any_fw(gt, wa->mcr_reg) :
intel_uncore_read_fw(uncore, wa->reg),
wal->name, from);
@@ -1776,10 +1776,10 @@ whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
}
static void
-whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
+whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags)
{
struct i915_wa wa = {
- .reg = reg,
+ .mcr_reg = reg,
.is_mcr = 1,
};
@@ -1789,7 +1789,7 @@ whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags)
if (GEM_DEBUG_WARN_ON(!is_nonpriv_flags_valid(flags)))
return;
- wa.reg.reg |= flags;
+ wa.mcr_reg.reg |= flags;
_wa_add(wal, &wa);
}
@@ -1800,7 +1800,7 @@ whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg)
}
static void
-whitelist_mcr_reg(struct i915_wa_list *wal, i915_reg_t reg)
+whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg)
{
whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
index f05b37e56fa9..7c8b01d00043 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds_types.h
@@ -11,7 +11,10 @@
#include "i915_reg_defs.h"
struct i915_wa {
- i915_reg_t reg;
+ union {
+ i915_reg_t reg;
+ i915_mcr_reg_t mcr_reg;
+ };
u32 clr;
u32 set;
u32 read;
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
index 67a9aab801dd..21b1edc052f8 100644
--- a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
@@ -991,7 +991,7 @@ static bool pardon_reg(struct drm_i915_private *i915, i915_reg_t reg)
/* Alas, we must pardon some whitelists. Mistakes already made */
static const struct regmask pardon[] = {
{ GEN9_CTX_PREEMPT_REG, 9 },
- { GEN8_L3SQCREG4, 9 },
+ { _MMIO(0xb118), 9 }, /* GEN8_L3SQCREG4 */
};
return find_reg(i915, reg, pardon, ARRAY_SIZE(pardon));
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index b5d3e3ef1787..31eee994e91c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -327,7 +327,7 @@ static long __must_check guc_mmio_reg_add(struct intel_gt *gt,
static long __must_check guc_mcr_reg_add(struct intel_gt *gt,
struct temp_regset *regset,
- i915_reg_t reg, u32 flags)
+ i915_mcr_reg_t reg, u32 flags)
{
u8 group, inst;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 9495a7928bc8..d5c03e7a7843 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -240,7 +240,7 @@ static void guc_capture_free_extlists(struct __guc_mmio_reg_descr_group *reglist
struct __ext_steer_reg {
const char *name;
- i915_reg_t reg;
+ i915_mcr_reg_t reg;
};
static const struct __ext_steer_reg xe_extregs[] = {
@@ -252,7 +252,7 @@ static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
const struct __ext_steer_reg *extlist,
int slice_id, int subslice_id)
{
- ext->reg = extlist->reg;
+ ext->reg = _MMIO(i915_mmio_reg_offset(extlist->reg));
ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id);
ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id);
ext->regname = extlist->name;
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 700cc9688f47..a52c4645cdbe 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -734,7 +734,7 @@ static i915_reg_t force_nonpriv_white_list[] = {
_MMIO(0x770c),
_MMIO(0x83a8),
_MMIO(0xb110),
- GEN8_L3SQCREG4,//_MMIO(0xb118)
+ _MMIO(0xb118),
_MMIO(0xe100),
_MMIO(0xe18c),
_MMIO(0xe48c),
@@ -2140,6 +2140,9 @@ static int csfe_chicken1_mmio_write(struct intel_vgpu *vgpu,
#define MMIO_DFH(reg, d, f, r, w) \
MMIO_F(reg, 4, f, 0, 0, d, r, w)
+#define MMIO_DFH_MCR(reg, d, f, r, w) \
+ MMIO_F(_MMIO(i915_mmio_reg_offset(reg)), 4, f, 0, 0, d, r, w)
+
#define MMIO_GM(reg, d, r, w) \
MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
@@ -2529,15 +2532,15 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt)
MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
- NULL, NULL);
+ MMIO_DFH_MCR(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
+ NULL, NULL);
MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
NULL, NULL);
MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH_MCR(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);
@@ -2550,7 +2553,7 @@ static int init_bdw_mmio_info(struct intel_gvt *gvt)
MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
- MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH_MCR(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);
@@ -2699,7 +2702,7 @@ static int init_skl_mmio_info(struct intel_gvt *gvt)
MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL);
MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL);
- MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH_MCR(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS,
NULL, NULL);
@@ -2769,7 +2772,7 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
bxt_port_tx_dw3_read, NULL);
MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
- MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
+ MMIO_DFH_MCR(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);
MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);
MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS,
diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c
index ac58460fb305..b5b51e4f28da 100644
--- a/drivers/gpu/drm/i915/gvt/mmio_context.c
+++ b/drivers/gpu/drm/i915/gvt/mmio_context.c
@@ -44,6 +44,8 @@
#define GEN9_MOCS_SIZE 64
+#define MCR_CAST(mcr) _MMIO(i915_mcr_reg_offset(mcr))
+
/* Raw offset is appened to each line for convenience. */
static struct engine_mmio gen8_engine_mmio_list[] __cacheline_aligned = {
{RCS0, RING_MODE_GEN7(RENDER_RING_BASE), 0xffff, false}, /* 0x229c */
@@ -106,15 +108,15 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = {
{RCS0, GEN8_CS_CHICKEN1, 0xffff, true}, /* 0x2580 */
{RCS0, COMMON_SLICE_CHICKEN2, 0xffff, true}, /* 0x7014 */
{RCS0, GEN9_CS_DEBUG_MODE1, 0xffff, false}, /* 0x20ec */
- {RCS0, GEN8_L3SQCREG4, 0, false}, /* 0xb118 */
- {RCS0, GEN9_SCRATCH1, 0, false}, /* 0xb11c */
+ {RCS0, _MMIO(0xb118), 0, false}, /* GEN8_L3SQCREG4 */
+ {RCS0, _MMIO(0xb11c), 0, false}, /* GEN9_SCRATCH1 */
{RCS0, GEN9_SCRATCH_LNCF1, 0, false}, /* 0xb008 */
{RCS0, GEN7_HALF_SLICE_CHICKEN1, 0xffff, true}, /* 0xe100 */
- {RCS0, HALF_SLICE_CHICKEN2, 0xffff, true}, /* 0xe180 */
+ {RCS0, _MMIO(0xe180), 0xffff, true}, /* HALF_SLICE_CHICKEN2 */
{RCS0, HSW_HALF_SLICE_CHICKEN3, 0xffff, true}, /* 0xe184 */
- {RCS0, GEN9_HALF_SLICE_CHICKEN5, 0xffff, true}, /* 0xe188 */
- {RCS0, GEN9_HALF_SLICE_CHICKEN7, 0xffff, true}, /* 0xe194 */
- {RCS0, GEN8_ROW_CHICKEN, 0xffff, true}, /* 0xe4f0 */
+ {RCS0, _MMIO(0xe188), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN5 */
+ {RCS0, _MMIO(0xe194), 0xffff, true}, /* GEN9_HALF_SLICE_CHICKEN7 */
+ {RCS0, _MMIO(0xe4f0), 0xffff, true}, /* GEN8_ROW_CHICKEN */
{RCS0, TRVATTL3PTRDW(0), 0, true}, /* 0x4de0 */
{RCS0, TRVATTL3PTRDW(1), 0, true}, /* 0x4de4 */
{RCS0, TRNULLDETCT, 0, true}, /* 0x4de8 */
diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h
index 8f486f77609f..e823869b9afd 100644
--- a/drivers/gpu/drm/i915/i915_reg_defs.h
+++ b/drivers/gpu/drm/i915/i915_reg_defs.h
@@ -104,22 +104,16 @@ typedef struct {
#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
-#define INVALID_MMIO_REG _MMIO(0)
-
-static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
-{
- return reg.reg;
-}
+typedef struct {
+ u32 reg;
+} i915_mcr_reg_t;
-static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
-{
- return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
-}
+#define INVALID_MMIO_REG _MMIO(0)
-static inline bool i915_mmio_reg_valid(i915_reg_t reg)
-{
- return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
-}
+/* These macros can be used on either i915_reg_t or i915_mcr_reg_t */
+#define i915_mmio_reg_offset(r) (r.reg)
+#define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))
+#define i915_mmio_reg_valid(r) (!i915_mmio_reg_equal(r, INVALID_MMIO_REG))
#define VLV_DISPLAY_BASE 0x180000
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 638b77d64bf4..8c1515f5c04c 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -816,10 +816,10 @@ static int iterate_bdw_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(GEN8_EU_DISABLE1);
MMIO_D(GEN8_EU_DISABLE2);
MMIO_D(_MMIO(0xfdc));
- MMIO_D(GEN8_ROW_CHICKEN);
+ MMIO_D(_MMIO(0xe4f0)); /* GEN8_ROW_CHICKEN */
MMIO_D(GEN7_ROW_CHICKEN2);
MMIO_D(GEN8_UCGCTL6);
- MMIO_D(GEN8_L3SQCREG4);
+ MMIO_D(_MMIO(0xb118)); /* GEN8_L3SQCREG4 */
MMIO_D(GEN9_SCRATCH_LNCF1);
MMIO_F(_MMIO(0x24d0), 48);
MMIO_D(_MMIO(0x44484));
@@ -831,7 +831,7 @@ static int iterate_bdw_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(_MMIO(0x65f10));
MMIO_D(_MMIO(0xe194));
MMIO_D(_MMIO(0xe188));
- MMIO_D(HALF_SLICE_CHICKEN2);
+ MMIO_D(_MMIO(0xe180)); /* HALF_SLICE_CHICKEN2 */
MMIO_D(_MMIO(0x2580));
MMIO_D(_MMIO(0xe220));
MMIO_D(_MMIO(0xe230));
@@ -1025,7 +1025,7 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(DMC_SSP_BASE);
MMIO_D(DMC_HTP_SKL);
MMIO_D(DMC_LAST_WRITE);
- MMIO_D(BDW_SCRATCH1);
+ MMIO_D(_MMIO(0xb11c)); /* BDW_SCRATCH1 */
MMIO_D(SKL_DFSM);
MMIO_D(DISPIO_CR_TX_BMU_CR0);
MMIO_F(GEN9_GFX_MOCS(0), 0x7f8);
@@ -1228,7 +1228,7 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(GEN8_PUSHBUS_ENABLE);
MMIO_D(GEN8_PUSHBUS_SHIFT);
MMIO_D(GEN6_GFXPAUSE);
- MMIO_D(GEN8_L3SQCREG1);
+ MMIO_D(_MMIO(0xb100)); /* GEN8_L3SQCREG1 */
MMIO_D(GEN8_L3CNTLREG);
MMIO_D(_MMIO(0x20D8));
MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40);
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 11/12] drm/i915/mtl: Add multicast steering for render GT
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel, Radhakrishna Sripada
MTL once again changes the multicast register types and steering
details. Key changes from past platforms:
* The number of instances of some MCR types (NODE, OAAL2, and GAM) vary
according to the MTL subplatform and cannot be read from fuse
registers.
* The MCR steering register (and its bitfields) has changed.
Unlike past platforms, we will be explicitly steering all types of MCR
accesses, including those for "SLICE" and "DSS" ranges; we no longer
rely on implicit steering. On previous platforms, various
hardware/firmware agents that needed to access registers typically had
their own steering control registers, allowing them to perform multicast
steering without clobbering the CPU/kernel steering. Starting with MTL,
more of these agents now share a single steering register (0xFD4) and it
is no longer safe for us to assume that the value will remain unchanged
from how we initialized it during startup. There is also a slight
chance of race conditions between the driver and a hardware/firmware
agent, so the hardware provides a semaphore register that can be used to
coordinate access to the steering register. Support for the semaphore
register will be introduced in a future patch.
Bspec: 67788, 67112
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 85 ++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 8 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 ++++-
drivers/gpu/drm/i915/i915_pci.c | 1 +
5 files changed, 102 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 8f9009af3673..05f41f1cc88d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -40,6 +40,7 @@ static const char * const intel_steering_types[] = {
"L3BANK",
"MSLICE",
"LNCF",
+ "DSS",
"INSTANCE 0",
};
@@ -89,9 +90,40 @@ static const struct intel_mmio_range pvc_instance0_steering_table[] = {
{},
};
+static const struct intel_mmio_range mtl3d_instance0_steering_table[] = {
+ { 0x000B00, 0x000BFF }, /* SQIDI */
+ { 0x001000, 0x001FFF }, /* SQIDI */
+ { 0x004000, 0x0048FF }, /* GAM */
+ { 0x008700, 0x0087FF }, /* SQIDI */
+ { 0x00B000, 0x00B0FF }, /* NODE */
+ { 0x00C800, 0x00CFFF }, /* GAM */
+ { 0x00D880, 0x00D8FF }, /* NODE */
+ { 0x00DD00, 0x00DDFF }, /* OAAL2 */
+ {},
+};
+
+static const struct intel_mmio_range mtl3d_l3bank_steering_table[] = {
+ { 0x00B100, 0x00B3FF },
+ {},
+};
+
+/* DSS steering is used for SLICE ranges as well */
+static const struct intel_mmio_range mtl3d_dss_steering_table[] = {
+ { 0x005200, 0x0052FF }, /* SLICE */
+ { 0x005500, 0x007FFF }, /* SLICE */
+ { 0x008140, 0x00815F }, /* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
+ { 0x0094D0, 0x00955F }, /* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
+ { 0x009680, 0x0096FF }, /* DSS */
+ { 0x00D800, 0x00D87F }, /* SLICE */
+ { 0x00DC00, 0x00DCFF }, /* SLICE */
+ { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
+};
+
void intel_gt_mcr_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ unsigned long fuse;
+ int i;
/*
* An mslice is unavailable only if both the meml3 for the slice is
@@ -109,7 +141,22 @@ void intel_gt_mcr_init(struct intel_gt *gt)
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
- if (IS_PONTEVECCHIO(i915)) {
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70) &&
+ gt->type == GT_PRIMARY) {
+ fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
+ intel_uncore_read(gt->uncore, XEHP_FUSE4));
+
+ /*
+ * Despite the register field being named "exclude mask" the
+ * bits actually represent enabled banks (two banks per bit).
+ */
+ for_each_set_bit(i, &fuse, 3)
+ gt->info.l3bank_mask |= (0x3 << 2*i);
+
+ gt->steering_table[INSTANCE0] = mtl3d_instance0_steering_table;
+ gt->steering_table[L3BANK] = mtl3d_l3bank_steering_table;
+ gt->steering_table[DSS] = mtl3d_dss_steering_table;
+ } else if (IS_PONTEVECCHIO(i915)) {
gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
} else if (IS_DG2(i915)) {
gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
@@ -168,7 +215,12 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
lockdep_assert_held(&uncore->lock);
- if (GRAPHICS_VER(uncore->i915) >= 11) {
+ if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70)) {
+ /* No need to save old steering reg value */
+ intel_uncore_write_fw(uncore, MTL_MCR_SELECTOR,
+ REG_FIELD_PREP(MTL_MCR_GROUPID, group) |
+ REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance));
+ } else if (GRAPHICS_VER(uncore->i915) >= 11) {
mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
mcr_ss = GEN11_MCR_SLICE(group) | GEN11_MCR_SUBSLICE(instance);
@@ -186,26 +238,30 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
*/
if (rw_flag == FW_REG_WRITE)
mcr_mask |= GEN11_MCR_MULTICAST;
+
+ old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
+
+ mcr &= ~mcr_mask;
+ mcr |= mcr_ss;
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
} else {
mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
mcr_ss = GEN8_MCR_SLICE(group) | GEN8_MCR_SUBSLICE(instance);
- }
- old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
+ old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
- mcr &= ~mcr_mask;
- mcr |= mcr_ss;
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+ mcr &= ~mcr_mask;
+ mcr |= mcr_ss;
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+ }
if (rw_flag == FW_REG_READ)
val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg));
else
intel_uncore_write_fw(uncore, mcr_reg_cast(reg), value);
- mcr &= ~mcr_mask;
- mcr |= old_mcr & mcr_mask;
-
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+ if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 70))
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
return val;
}
@@ -345,6 +401,8 @@ static void get_nonterminated_steering(struct intel_gt *gt,
enum intel_steering_type type,
u8 *group, u8 *instance)
{
+ u32 dss;
+
switch (type) {
case L3BANK:
*group = 0; /* unused */
@@ -364,6 +422,11 @@ static void get_nonterminated_steering(struct intel_gt *gt,
*group = __ffs(gt->info.mslice_mask) << 1;
*instance = 0; /* unused */
break;
+ case DSS:
+ dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0);
+ *group = dss / GEN_DSS_PER_GSLICE;
+ *instance = dss % GEN_DSS_PER_GSLICE;
+ break;
case INSTANCE0:
/*
* There are a lot of MCR types for which instance (0, 0)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4b5692d84858..6363b4038556 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -56,6 +56,7 @@
#define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc)
#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
+#define MTL_MCR_SELECTOR _MMIO(0xfd4)
#define SF_MCR_SELECTOR _MMIO(0xfd8)
#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
@@ -67,6 +68,8 @@
#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
+#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
+#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
#define IPEIR_I965 _MMIO(0x2064)
#define IPEHR_I965 _MMIO(0x2068)
@@ -527,6 +530,8 @@
#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
/* Fuse readout registers for GT */
+#define XEHP_FUSE4 _MMIO(0x9114)
+#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
#define GEN10_L3BANK_PAIR_COUNT 4
#define GEN10_L3BANK_MASK 0x0F
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index f19c2de77ff6..2a0441410ec7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -59,6 +59,7 @@ enum intel_steering_type {
L3BANK,
MSLICE,
LNCF,
+ DSS,
/*
* On some platforms there are multiple types of MCR registers that
@@ -254,8 +255,6 @@ struct intel_gt {
intel_engine_mask_t engine_mask;
- u32 l3bank_mask;
-
u8 num_engines;
/* General presence of SFC units */
@@ -267,7 +266,10 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
- unsigned long mslice_mask;
+ union {
+ unsigned long mslice_mask;
+ unsigned long l3bank_mask;
+ };
/** @hwconfig: hardware configuration data */
struct intel_hwconfig hwconfig;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0f18872a7995..2562ad83966b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1571,12 +1571,28 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
}
+static void
+mtl_3d_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
+{
+ /*
+ * Unlike older platforms, we no longer setup implicit steering here;
+ * all MCR accesses are explicitly steered.
+ */
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ struct drm_printer p = drm_debug_printer("MCR Steering:");
+
+ intel_gt_mcr_report_steering(&p, gt, false);
+ }
+}
+
static void
gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = gt->i915;
- if (IS_PONTEVECCHIO(i915))
+ if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
+ mtl_3d_gt_workarounds_init(gt, wal);
+ else if (IS_PONTEVECCHIO(i915))
pvc_gt_workarounds_init(gt, wal);
else if (IS_DG2(i915))
dg2_gt_workarounds_init(gt, wal);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 77e7df21f539..3af94d8289df 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1143,6 +1143,7 @@ static const struct intel_device_info mtl_info = {
.display.has_modular_fia = 1,
.extra_gt_list = xelpmp_extra_gt,
.has_flat_ccs = 0,
+ .has_mslice_steering = 0,
.has_snoop = 1,
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH 11/12] drm/i915/mtl: Add multicast steering for render GT
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
MTL once again changes the multicast register types and steering
details. Key changes from past platforms:
* The number of instances of some MCR types (NODE, OAAL2, and GAM) vary
according to the MTL subplatform and cannot be read from fuse
registers.
* The MCR steering register (and its bitfields) has changed.
Unlike past platforms, we will be explicitly steering all types of MCR
accesses, including those for "SLICE" and "DSS" ranges; we no longer
rely on implicit steering. On previous platforms, various
hardware/firmware agents that needed to access registers typically had
their own steering control registers, allowing them to perform multicast
steering without clobbering the CPU/kernel steering. Starting with MTL,
more of these agents now share a single steering register (0xFD4) and it
is no longer safe for us to assume that the value will remain unchanged
from how we initialized it during startup. There is also a slight
chance of race conditions between the driver and a hardware/firmware
agent, so the hardware provides a semaphore register that can be used to
coordinate access to the steering register. Support for the semaphore
register will be introduced in a future patch.
Bspec: 67788, 67112
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 85 ++++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 8 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 ++++-
drivers/gpu/drm/i915/i915_pci.c | 1 +
5 files changed, 102 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 8f9009af3673..05f41f1cc88d 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -40,6 +40,7 @@ static const char * const intel_steering_types[] = {
"L3BANK",
"MSLICE",
"LNCF",
+ "DSS",
"INSTANCE 0",
};
@@ -89,9 +90,40 @@ static const struct intel_mmio_range pvc_instance0_steering_table[] = {
{},
};
+static const struct intel_mmio_range mtl3d_instance0_steering_table[] = {
+ { 0x000B00, 0x000BFF }, /* SQIDI */
+ { 0x001000, 0x001FFF }, /* SQIDI */
+ { 0x004000, 0x0048FF }, /* GAM */
+ { 0x008700, 0x0087FF }, /* SQIDI */
+ { 0x00B000, 0x00B0FF }, /* NODE */
+ { 0x00C800, 0x00CFFF }, /* GAM */
+ { 0x00D880, 0x00D8FF }, /* NODE */
+ { 0x00DD00, 0x00DDFF }, /* OAAL2 */
+ {},
+};
+
+static const struct intel_mmio_range mtl3d_l3bank_steering_table[] = {
+ { 0x00B100, 0x00B3FF },
+ {},
+};
+
+/* DSS steering is used for SLICE ranges as well */
+static const struct intel_mmio_range mtl3d_dss_steering_table[] = {
+ { 0x005200, 0x0052FF }, /* SLICE */
+ { 0x005500, 0x007FFF }, /* SLICE */
+ { 0x008140, 0x00815F }, /* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
+ { 0x0094D0, 0x00955F }, /* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
+ { 0x009680, 0x0096FF }, /* DSS */
+ { 0x00D800, 0x00D87F }, /* SLICE */
+ { 0x00DC00, 0x00DCFF }, /* SLICE */
+ { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
+};
+
void intel_gt_mcr_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
+ unsigned long fuse;
+ int i;
/*
* An mslice is unavailable only if both the meml3 for the slice is
@@ -109,7 +141,22 @@ void intel_gt_mcr_init(struct intel_gt *gt)
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
- if (IS_PONTEVECCHIO(i915)) {
+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70) &&
+ gt->type == GT_PRIMARY) {
+ fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
+ intel_uncore_read(gt->uncore, XEHP_FUSE4));
+
+ /*
+ * Despite the register field being named "exclude mask" the
+ * bits actually represent enabled banks (two banks per bit).
+ */
+ for_each_set_bit(i, &fuse, 3)
+ gt->info.l3bank_mask |= (0x3 << 2*i);
+
+ gt->steering_table[INSTANCE0] = mtl3d_instance0_steering_table;
+ gt->steering_table[L3BANK] = mtl3d_l3bank_steering_table;
+ gt->steering_table[DSS] = mtl3d_dss_steering_table;
+ } else if (IS_PONTEVECCHIO(i915)) {
gt->steering_table[INSTANCE0] = pvc_instance0_steering_table;
} else if (IS_DG2(i915)) {
gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
@@ -168,7 +215,12 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
lockdep_assert_held(&uncore->lock);
- if (GRAPHICS_VER(uncore->i915) >= 11) {
+ if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 70)) {
+ /* No need to save old steering reg value */
+ intel_uncore_write_fw(uncore, MTL_MCR_SELECTOR,
+ REG_FIELD_PREP(MTL_MCR_GROUPID, group) |
+ REG_FIELD_PREP(MTL_MCR_INSTANCEID, instance));
+ } else if (GRAPHICS_VER(uncore->i915) >= 11) {
mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
mcr_ss = GEN11_MCR_SLICE(group) | GEN11_MCR_SUBSLICE(instance);
@@ -186,26 +238,30 @@ static u32 rw_with_mcr_steering_fw(struct intel_uncore *uncore,
*/
if (rw_flag == FW_REG_WRITE)
mcr_mask |= GEN11_MCR_MULTICAST;
+
+ old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
+
+ mcr &= ~mcr_mask;
+ mcr |= mcr_ss;
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
} else {
mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
mcr_ss = GEN8_MCR_SLICE(group) | GEN8_MCR_SUBSLICE(instance);
- }
- old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
+ old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
- mcr &= ~mcr_mask;
- mcr |= mcr_ss;
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+ mcr &= ~mcr_mask;
+ mcr |= mcr_ss;
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+ }
if (rw_flag == FW_REG_READ)
val = intel_uncore_read_fw(uncore, mcr_reg_cast(reg));
else
intel_uncore_write_fw(uncore, mcr_reg_cast(reg), value);
- mcr &= ~mcr_mask;
- mcr |= old_mcr & mcr_mask;
-
- intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
+ if (GRAPHICS_VER_FULL(uncore->i915) < IP_VER(12, 70))
+ intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
return val;
}
@@ -345,6 +401,8 @@ static void get_nonterminated_steering(struct intel_gt *gt,
enum intel_steering_type type,
u8 *group, u8 *instance)
{
+ u32 dss;
+
switch (type) {
case L3BANK:
*group = 0; /* unused */
@@ -364,6 +422,11 @@ static void get_nonterminated_steering(struct intel_gt *gt,
*group = __ffs(gt->info.mslice_mask) << 1;
*instance = 0; /* unused */
break;
+ case DSS:
+ dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0);
+ *group = dss / GEN_DSS_PER_GSLICE;
+ *instance = dss % GEN_DSS_PER_GSLICE;
+ break;
case INSTANCE0:
/*
* There are a lot of MCR types for which instance (0, 0)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 4b5692d84858..6363b4038556 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -56,6 +56,7 @@
#define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc)
#define MCFG_MCR_SELECTOR _MMIO(0xfd0)
+#define MTL_MCR_SELECTOR _MMIO(0xfd4)
#define SF_MCR_SELECTOR _MMIO(0xfd8)
#define GEN8_MCR_SELECTOR _MMIO(0xfdc)
#define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26)
@@ -67,6 +68,8 @@
#define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf)
#define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24)
#define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7)
+#define MTL_MCR_GROUPID REG_GENMASK(11, 8)
+#define MTL_MCR_INSTANCEID REG_GENMASK(3, 0)
#define IPEIR_I965 _MMIO(0x2064)
#define IPEHR_I965 _MMIO(0x2068)
@@ -527,6 +530,8 @@
#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
/* Fuse readout registers for GT */
+#define XEHP_FUSE4 _MMIO(0x9114)
+#define GT_L3_EXC_MASK REG_GENMASK(6, 4)
#define GEN10_MIRROR_FUSE3 _MMIO(0x9118)
#define GEN10_L3BANK_PAIR_COUNT 4
#define GEN10_L3BANK_MASK 0x0F
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index f19c2de77ff6..2a0441410ec7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -59,6 +59,7 @@ enum intel_steering_type {
L3BANK,
MSLICE,
LNCF,
+ DSS,
/*
* On some platforms there are multiple types of MCR registers that
@@ -254,8 +255,6 @@ struct intel_gt {
intel_engine_mask_t engine_mask;
- u32 l3bank_mask;
-
u8 num_engines;
/* General presence of SFC units */
@@ -267,7 +266,10 @@ struct intel_gt {
/* Slice/subslice/EU info */
struct sseu_dev_info sseu;
- unsigned long mslice_mask;
+ union {
+ unsigned long mslice_mask;
+ unsigned long l3bank_mask;
+ };
/** @hwconfig: hardware configuration data */
struct intel_hwconfig hwconfig;
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0f18872a7995..2562ad83966b 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1571,12 +1571,28 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE);
}
+static void
+mtl_3d_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
+{
+ /*
+ * Unlike older platforms, we no longer setup implicit steering here;
+ * all MCR accesses are explicitly steered.
+ */
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ struct drm_printer p = drm_debug_printer("MCR Steering:");
+
+ intel_gt_mcr_report_steering(&p, gt, false);
+ }
+}
+
static void
gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = gt->i915;
- if (IS_PONTEVECCHIO(i915))
+ if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
+ mtl_3d_gt_workarounds_init(gt, wal);
+ else if (IS_PONTEVECCHIO(i915))
pvc_gt_workarounds_init(gt, wal);
else if (IS_DG2(i915))
dg2_gt_workarounds_init(gt, wal);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 77e7df21f539..3af94d8289df 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1143,6 +1143,7 @@ static const struct intel_device_info mtl_info = {
.display.has_modular_fia = 1,
.extra_gt_list = xelpmp_extra_gt,
.has_flat_ccs = 0,
+ .has_mslice_steering = 0,
.has_snoop = 1,
.__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
.__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH 12/12] drm/i915/mtl: Add multicast steering for media GT
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
@ 2022-09-19 22:32 ` Matt Roper
-1 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
MTL's media GT only has a single type of steering ("OAADDRM") which
selects between media slice 0 and media slice 1. We'll always steer to
media slice 0 unless it is fused off (which is the case when VD0, VE0,
and SFC0 are all reported as unavailable).
Bspec: 67789
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 19 +++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++++++++++++-
3 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 05f41f1cc88d..04f75c1e0f4e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -41,6 +41,7 @@ static const char * const intel_steering_types[] = {
"MSLICE",
"LNCF",
"DSS",
+ "OADDRM",
"INSTANCE 0",
};
@@ -119,6 +120,12 @@ static const struct intel_mmio_range mtl3d_dss_steering_table[] = {
{ 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
};
+static const struct intel_mmio_range xelpmp_oaddrm_steering_table[] = {
+ { 0x393200, 0x39323F },
+ { 0x393400, 0x3934FF },
+};
+
+
void intel_gt_mcr_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -141,8 +148,9 @@ void intel_gt_mcr_init(struct intel_gt *gt)
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70) &&
- gt->type == GT_PRIMARY) {
+ if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
+ gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
+ } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
intel_uncore_read(gt->uncore, XEHP_FUSE4));
@@ -435,6 +443,13 @@ static void get_nonterminated_steering(struct intel_gt *gt,
*group = 0;
*instance = 0;
break;
+ case OADDRM:
+ if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) & BIT(0))
+ *group = 0;
+ else
+ *group = 1;
+ *instance = 0;
+ break;
default:
MISSING_CASE(type);
*group = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 2a0441410ec7..5fa59a66dba2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -60,6 +60,7 @@ enum intel_steering_type {
MSLICE,
LNCF,
DSS,
+ OADDRM,
/*
* On some platforms there are multiple types of MCR registers that
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2562ad83966b..9227391fc144 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1585,12 +1585,28 @@ mtl_3d_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
}
}
+static void
+mtl_media_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
+{
+ /*
+ * Unlike older platforms, we no longer setup implicit steering here;
+ * all MCR accesses are explicitly steered.
+ */
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ struct drm_printer p = drm_debug_printer("MCR Steering:");
+
+ intel_gt_mcr_report_steering(&p, gt, false);
+ }
+}
+
static void
gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = gt->i915;
- if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
+ if (IS_METEORLAKE(i915) && gt->type == GT_MEDIA)
+ mtl_media_gt_workarounds_init(gt, wal);
+ else if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
mtl_3d_gt_workarounds_init(gt, wal);
else if (IS_PONTEVECCHIO(i915))
pvc_gt_workarounds_init(gt, wal);
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH 12/12] drm/i915/mtl: Add multicast steering for media GT
@ 2022-09-19 22:32 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-19 22:32 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
MTL's media GT only has a single type of steering ("OAADDRM") which
selects between media slice 0 and media slice 1. We'll always steer to
media slice 0 unless it is fused off (which is the case when VD0, VE0,
and SFC0 are all reported as unavailable).
Bspec: 67789
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 19 +++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 18 +++++++++++++++++-
3 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
index 05f41f1cc88d..04f75c1e0f4e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c
@@ -41,6 +41,7 @@ static const char * const intel_steering_types[] = {
"MSLICE",
"LNCF",
"DSS",
+ "OADDRM",
"INSTANCE 0",
};
@@ -119,6 +120,12 @@ static const struct intel_mmio_range mtl3d_dss_steering_table[] = {
{ 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
};
+static const struct intel_mmio_range xelpmp_oaddrm_steering_table[] = {
+ { 0x393200, 0x39323F },
+ { 0x393400, 0x3934FF },
+};
+
+
void intel_gt_mcr_init(struct intel_gt *gt)
{
struct drm_i915_private *i915 = gt->i915;
@@ -141,8 +148,9 @@ void intel_gt_mcr_init(struct intel_gt *gt)
drm_warn(&i915->drm, "mslice mask all zero!\n");
}
- if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70) &&
- gt->type == GT_PRIMARY) {
+ if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) {
+ gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table;
+ } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) {
fuse = REG_FIELD_GET(GT_L3_EXC_MASK,
intel_uncore_read(gt->uncore, XEHP_FUSE4));
@@ -435,6 +443,13 @@ static void get_nonterminated_steering(struct intel_gt *gt,
*group = 0;
*instance = 0;
break;
+ case OADDRM:
+ if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) & BIT(0))
+ *group = 0;
+ else
+ *group = 1;
+ *instance = 0;
+ break;
default:
MISSING_CASE(type);
*group = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 2a0441410ec7..5fa59a66dba2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -60,6 +60,7 @@ enum intel_steering_type {
MSLICE,
LNCF,
DSS,
+ OADDRM,
/*
* On some platforms there are multiple types of MCR registers that
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 2562ad83966b..9227391fc144 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1585,12 +1585,28 @@ mtl_3d_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
}
}
+static void
+mtl_media_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
+{
+ /*
+ * Unlike older platforms, we no longer setup implicit steering here;
+ * all MCR accesses are explicitly steered.
+ */
+ if (drm_debug_enabled(DRM_UT_DRIVER)) {
+ struct drm_printer p = drm_debug_printer("MCR Steering:");
+
+ intel_gt_mcr_report_steering(&p, gt, false);
+ }
+}
+
static void
gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal)
{
struct drm_i915_private *i915 = gt->i915;
- if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
+ if (IS_METEORLAKE(i915) && gt->type == GT_MEDIA)
+ mtl_media_gt_workarounds_init(gt, wal);
+ else if (IS_METEORLAKE(i915) && gt->type == GT_PRIMARY)
mtl_3d_gt_workarounds_init(gt, wal);
else if (IS_PONTEVECCHIO(i915))
pvc_gt_workarounds_init(gt, wal);
--
2.37.3
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Explicit MCR handling and MTL steering
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
` (12 preceding siblings ...)
(?)
@ 2022-09-20 0:46 ` Patchwork
-1 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2022-09-20 0:46 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Explicit MCR handling and MTL steering
URL : https://patchwork.freedesktop.org/series/108755/
State : warning
== Summary ==
Error: dim checkpatch failed
b8fad010a955 drm/i915/gen8: Create separate reg definitions for new MCR registers
-:266: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#266: FILE: drivers/gpu/drm/i915/intel_pm.c:4329:
+ intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, misccpctl & ~GEN8_DOP_CLOCK_GATE_ENABLE);
-:285: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#285: FILE: drivers/gpu/drm/i915/intel_pm.c:4503:
+ intel_uncore_write(&dev_priv->uncore, GEN8_MISCCPCTL, intel_uncore_read(&dev_priv->uncore, GEN8_MISCCPCTL) &
total: 0 errors, 2 warnings, 0 checks, 207 lines checked
f2021d24f2ef drm/i915/xehp: Create separate reg definitions for new MCR registers
eadc4174dc1e drm/i915/gt: Drop a few unused register definitions
fa7d3af0dfed drm/i915/gt: Correct prefix on a few registers
8cad69165b35 drm/i915/xehp: Check for faults on primary GAM
268e98c61eca drm/i915: Define MCR registers explicitly
-:149: WARNING:LONG_LINE_COMMENT: line length of 102 exceeds 100 columns
#149: FILE: drivers/gpu/drm/i915/gt/intel_gt_regs.h:944:
+#define XEHP_LNCFCMOCS(i) MCR_REG(0xb020 + (i) * 4) /* L3 Cache Control */
total: 0 errors, 1 warnings, 0 checks, 336 lines checked
ca16a86aaa43 drm/i915/gt: Always use MCR functions on multicast registers
512f53fa7952 drm/i915/guc: Handle save/restore of MCR registers explicitly
a503a645efa4 drm/i915/gt: Add MCR-specific workaround initializers
-:119: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#119: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:297:
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
-:622: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#622: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:2248:
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2,
GEN12_DISABLE_READ_SUPPRESSION);
-:641: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#641: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:2264:
+ wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN,
MDQ_ARBITRATION_MODE | UGM_BACKUP_MODE);
-:705: WARNING:BLOCK_COMMENT_STYLE: Block comments use * on subsequent lines
#705: FILE: drivers/gpu/drm/i915/gt/intel_workarounds.c:2316:
+ 0 /* Wa_14012342262 :write-only reg, so skip
+ verification */,
total: 0 errors, 1 warnings, 3 checks, 883 lines checked
b70ee2ae2afa drm/i915: Define multicast registers as a new type
-:590: WARNING:NEW_TYPEDEFS: do not add new typedefs
#590: FILE: drivers/gpu/drm/i915/i915_reg_defs.h:107:
+typedef struct {
total: 0 errors, 1 warnings, 0 checks, 538 lines checked
b2d91bc03cfd drm/i915/mtl: Add multicast steering for render GT
-:99: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#99: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:154:
+ gt->info.l3bank_mask |= (0x3 << 2*i);
^
-:127: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#127: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:242:
+ old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
-:138: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#138: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:251:
+ old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
total: 0 errors, 0 warnings, 3 checks, 226 lines checked
6fff7a4c5772 drm/i915/mtl: Add multicast steering for media GT
-:35: CHECK:LINE_SPACING: Please don't use multiple blank lines
#35: FILE: drivers/gpu/drm/i915/gt/intel_gt_mcr.c:128:
+
+
total: 0 errors, 0 warnings, 1 checks, 79 lines checked
^ permalink raw reply [flat|nested] 40+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Explicit MCR handling and MTL steering
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
` (13 preceding siblings ...)
(?)
@ 2022-09-20 0:46 ` Patchwork
-1 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2022-09-20 0:46 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: Explicit MCR handling and MTL steering
URL : https://patchwork.freedesktop.org/series/108755/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 40+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for Explicit MCR handling and MTL steering
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
` (14 preceding siblings ...)
(?)
@ 2022-09-20 1:10 ` Patchwork
-1 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2022-09-20 1:10 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7890 bytes --]
== Series Details ==
Series: Explicit MCR handling and MTL steering
URL : https://patchwork.freedesktop.org/series/108755/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12158 -> Patchwork_108755v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/index.html
Participating hosts (42 -> 39)
------------------------------
Missing (3): fi-ctg-p8600 bat-jsl-3 bat-dg1-5
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108755v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@execlists:
- {fi-jsl-1}: [PASS][1] -> [DMESG-WARN][2] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-jsl-1/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-jsl-1/igt@i915_selftest@live@execlists.html
- {fi-ehl-2}: [PASS][3] -> [DMESG-WARN][4] +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-ehl-2/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-ehl-2/igt@i915_selftest@live@execlists.html
Known issues
------------
Here are the changes found in Patchwork_108755v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- fi-pnv-d510: [PASS][5] -> [INCOMPLETE][6] ([i915#6863])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-pnv-d510/igt@debugfs_test@read_all_entries.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-pnv-d510/igt@debugfs_test@read_all_entries.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-bxt-dsi: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-bxt-dsi/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-ivb-3770: [PASS][9] -> [INCOMPLETE][10] ([i915#3303] / [i915#5370])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-ivb-3770/igt@i915_selftest@live@hangcheck.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-ivb-3770/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@runner@aborted:
- fi-ivb-3770: NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#4312])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-ivb-3770/igt@runner@aborted.html
- fi-pnv-d510: NOTRUN -> [FAIL][13] ([i915#2403] / [i915#4312])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-pnv-d510/igt@runner@aborted.html
#### Possible fixes ####
* igt@fbdev@eof:
- {fi-tgl-mst}: [SKIP][14] ([i915#2582]) -> [PASS][15] +4 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-tgl-mst/igt@fbdev@eof.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-tgl-mst/igt@fbdev@eof.html
* igt@gem_ctx_create@basic-files:
- {fi-tgl-mst}: [DMESG-WARN][16] -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-tgl-mst/igt@gem_ctx_create@basic-files.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-tgl-mst/igt@gem_ctx_create@basic-files.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][18] ([i915#4785]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@slpc:
- {bat-rpls-1}: [DMESG-FAIL][20] ([i915#6367]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/bat-rpls-1/igt@i915_selftest@live@slpc.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/bat-rpls-1/igt@i915_selftest@live@slpc.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
- fi-bsw-kefka: [FAIL][22] ([i915#6298]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5370]: https://gitlab.freedesktop.org/drm/intel/issues/5370
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6434]: https://gitlab.freedesktop.org/drm/intel/issues/6434
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6863]: https://gitlab.freedesktop.org/drm/intel/issues/6863
Build changes
-------------
* Linux: CI_DRM_12158 -> Patchwork_108755v1
CI-20190529: 20190529
CI_DRM_12158: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108755v1: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
463b3c599e98 drm/i915/mtl: Add multicast steering for media GT
6f56cf555c63 drm/i915/mtl: Add multicast steering for render GT
b759c9ab0708 drm/i915: Define multicast registers as a new type
c57a8322cb00 drm/i915/gt: Add MCR-specific workaround initializers
a13c2e492bd0 drm/i915/guc: Handle save/restore of MCR registers explicitly
aa4fde1c62a3 drm/i915/gt: Always use MCR functions on multicast registers
55c84188f031 drm/i915: Define MCR registers explicitly
b26968e4ae10 drm/i915/xehp: Check for faults on primary GAM
4b507f90eacd drm/i915/gt: Correct prefix on a few registers
185a163f8488 drm/i915/gt: Drop a few unused register definitions
576e12e43a6d drm/i915/xehp: Create separate reg definitions for new MCR registers
823366116269 drm/i915/gen8: Create separate reg definitions for new MCR registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/index.html
[-- Attachment #2: Type: text/html, Size: 8543 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for Explicit MCR handling and MTL steering
2022-09-19 22:32 ` [Intel-gfx] " Matt Roper
` (15 preceding siblings ...)
(?)
@ 2022-09-20 10:18 ` Patchwork
2022-09-20 22:37 ` Matt Roper
-1 siblings, 1 reply; 40+ messages in thread
From: Patchwork @ 2022-09-20 10:18 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 34500 bytes --]
== Series Details ==
Series: Explicit MCR handling and MTL steering
URL : https://patchwork.freedesktop.org/series/108755/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_12158_full -> Patchwork_108755v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_108755v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_108755v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_108755v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_suspend@debugfs-reader:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb3/igt@i915_suspend@debugfs-reader.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb1/igt@i915_suspend@debugfs-reader.html
#### Warnings ####
* igt@runner@aborted:
- shard-skl: ([FAIL][3], [FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26], [FAIL][27]) ([i915#6599]) -> ([FAIL][28], [FAIL][29], [FAIL][30], [FAIL][31], [FAIL][32], [FAIL][33], [FAIL][34], [FAIL][35], [FAIL][36], [FAIL][37], [FAIL][38], [FAIL][39], [FAIL][40], [FAIL][41], [FAIL][42], [FAIL][43], [FAIL][44], [FAIL][45], [FAIL][46], [FAIL][47], [FAIL][48], [FAIL][49], [FAIL][50], [FAIL][51], [FAIL][52])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl10/igt@runner@aborted.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl7/igt@runner@aborted.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl10/igt@runner@aborted.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl4/igt@runner@aborted.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl6/igt@runner@aborted.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl7/igt@runner@aborted.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl4/igt@runner@aborted.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl6/igt@runner@aborted.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl10/igt@runner@aborted.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl10/igt@runner@aborted.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl6/igt@runner@aborted.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl7/igt@runner@aborted.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl4/igt@runner@aborted.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl10/igt@runner@aborted.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl7/igt@runner@aborted.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl1/igt@runner@aborted.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl6/igt@runner@aborted.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl1/igt@runner@aborted.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl1/igt@runner@aborted.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl1/igt@runner@aborted.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl9/igt@runner@aborted.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl4/igt@runner@aborted.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl9/igt@runner@aborted.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl9/igt@runner@aborted.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl9/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_108755v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-apl: ([PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77]) -> ([PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [FAIL][101], [PASS][102]) ([i915#4386])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl2/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl2/boot.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl2/boot.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl2/boot.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/boot.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/boot.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/boot.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/boot.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/boot.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/boot.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/boot.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/boot.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/boot.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/boot.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl7/boot.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl7/boot.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl7/boot.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/boot.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/boot.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/boot.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/boot.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/boot.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/boot.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/boot.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl2/boot.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/boot.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl2/boot.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/boot.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/boot.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/boot.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/boot.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/boot.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/boot.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/boot.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/boot.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/boot.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/boot.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/boot.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/boot.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl2/boot.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl1/boot.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl1/boot.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl1/boot.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl1/boot.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl2/boot.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel:
- shard-iclb: [PASS][103] -> [SKIP][104] ([i915#4525])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb1/igt@gem_exec_balancer@parallel.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb5/igt@gem_exec_balancer@parallel.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-glk: [PASS][105] -> [FAIL][106] ([i915#2842])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk9/igt@gem_exec_fair@basic-none@vecs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk1/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [PASS][107] -> [FAIL][108] ([i915#2842])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglb: [PASS][109] -> [FAIL][110] ([i915#2842])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-uc-set-default:
- shard-apl: [PASS][111] -> [DMESG-FAIL][112] ([i915#6864])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/igt@gem_exec_flush@basic-uc-set-default.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/igt@gem_exec_flush@basic-uc-set-default.html
* igt@gem_softpin@evict-single-offset:
- shard-tglb: [PASS][113] -> [FAIL][114] ([i915#4171])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb3/igt@gem_softpin@evict-single-offset.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb1/igt@gem_softpin@evict-single-offset.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][115] ([i915#4991])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@gem_userptr_blits@input-checking.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-apl: NOTRUN -> [SKIP][116] ([fdo#109271]) +57 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@i915_pm_rps@engine-order:
- shard-apl: [PASS][117] -> [FAIL][118] ([i915#6537])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/igt@i915_pm_rps@engine-order.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/igt@i915_pm_rps@engine-order.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#3886]) +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color_chamelium@ctm-red-to-blue:
- shard-apl: NOTRUN -> [SKIP][120] ([fdo#109271] / [fdo#111827]) +2 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@kms_color_chamelium@ctm-red-to-blue.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-glk: [PASS][121] -> [FAIL][122] ([i915#2346])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][123] ([fdo#109271])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk6/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][124] -> [FAIL][125] ([i915#4767])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-apl: [PASS][126] -> [DMESG-WARN][127] ([i915#180]) +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][128] ([i915#2672]) +5 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-iclb: NOTRUN -> [SKIP][129] ([i915#2587] / [i915#2672]) +2 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2:
- shard-glk: [PASS][130] -> [DMESG-WARN][131] ([i915#118] / [i915#1888])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
- shard-iclb: [PASS][132] -> [SKIP][133] ([i915#5176]) +2 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb1/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
- shard-iclb: [PASS][134] -> [SKIP][135] ([i915#5235]) +2 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb6/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
- shard-apl: NOTRUN -> [SKIP][136] ([fdo#109271] / [i915#658])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr@psr2_sprite_plane_onoff:
- shard-iclb: [PASS][137] -> [SKIP][138] ([fdo#109441]) +2 similar issues
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb1/igt@kms_psr@psr2_sprite_plane_onoff.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#533])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@kms_vblank@pipe-d-wait-idle.html
* igt@perf@stress-open-close:
- shard-glk: [PASS][140] -> [INCOMPLETE][141] ([i915#5213])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@perf@stress-open-close.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@perf@stress-open-close.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][142] ([i915#658]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb1/igt@feature_discovery@psr2.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglb: [FAIL][144] ([i915#6268]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb3/igt@gem_ctx_exec@basic-nohangcheck.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb1/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [SKIP][146] ([i915#4525]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb6/igt@gem_exec_balancer@parallel-bb-first.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][148] ([i915#2842]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_workarounds@suspend-resume:
- shard-apl: [DMESG-WARN][150] ([i915#180]) -> [PASS][151] +1 similar issue
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/igt@gem_workarounds@suspend-resume.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@gem_workarounds@suspend-resume.html
* igt@i915_pm_dc@dc5-psr:
- shard-iclb: [FAIL][152] ([i915#3989]) -> [PASS][153]
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb8/igt@i915_pm_dc@dc5-psr.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb3/igt@i915_pm_dc@dc5-psr.html
* igt@i915_selftest@live@hangcheck:
- shard-tglb: [DMESG-WARN][154] ([i915#5591]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb5/igt@i915_selftest@live@hangcheck.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb3/igt@i915_selftest@live@hangcheck.html
* igt@kms_frontbuffer_tracking@fbc-badstride:
- shard-snb: [SKIP][156] ([fdo#109271]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-snb4/igt@kms_frontbuffer_tracking@fbc-badstride.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-snb2/igt@kms_frontbuffer_tracking@fbc-badstride.html
* igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1:
- shard-glk: [FAIL][158] ([i915#1888]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][160] ([fdo#109441]) -> [PASS][161] +2 similar issues
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_vblank@pipe-b-accuracy-idle:
- shard-glk: [FAIL][162] ([i915#43]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@kms_vblank@pipe-b-accuracy-idle.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@kms_vblank@pipe-b-accuracy-idle.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-iclb: [FAIL][164] ([i915#2684]) -> [WARN][165] ([i915#2684])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-iclb: [SKIP][166] ([i915#2920]) -> [SKIP][167] ([i915#658])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [SKIP][168] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][169] ([i915#5939])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
* igt@runner@aborted:
- shard-apl: ([FAIL][170], [FAIL][171], [FAIL][172], [FAIL][173]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177], [FAIL][178], [FAIL][179]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/igt@runner@aborted.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/igt@runner@aborted.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/igt@runner@aborted.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/igt@runner@aborted.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl1/igt@runner@aborted.html
- shard-tglb: ([FAIL][180], [FAIL][181]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][182], [FAIL][183]) ([i915#3002] / [i915#4312] / [i915#5257])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb8/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb1/igt@runner@aborted.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb8/igt@runner@aborted.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb7/igt@runner@aborted.html
- shard-glk: ([FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][188], [FAIL][189], [FAIL][190], [FAIL][191], [FAIL][192]) ([i915#3002] / [i915#4312] / [i915#5257])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@runner@aborted.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/igt@runner@aborted.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/igt@runner@aborted.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk1/igt@runner@aborted.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk2/igt@runner@aborted.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk8/igt@runner@aborted.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk2/igt@runner@aborted.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@runner@aborted.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@runner@aborted.html
- shard-iclb: ([FAIL][193], [FAIL][194]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][195], [FAIL][196]) ([i915#3002] / [i915#4312] / [i915#5257])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb7/igt@runner@aborted.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb5/igt@runner@aborted.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb4/igt@runner@aborted.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb6/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
[i915#6864]: https://gitlab.freedesktop.org/drm/intel/issues/6864
Build changes
-------------
* Linux: CI_DRM_12158 -> Patchwork_108755v1
CI-20190529: 20190529
CI_DRM_12158: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_108755v1: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/index.html
[-- Attachment #2: Type: text/html, Size: 37048 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Explicit MCR handling and MTL steering
2022-09-20 10:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-09-20 22:37 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2022-09-20 22:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Vudum, Lakshminarayana
On Tue, Sep 20, 2022 at 10:18:20AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: Explicit MCR handling and MTL steering
> URL : https://patchwork.freedesktop.org/series/108755/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_12158_full -> Patchwork_108755v1_full
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_108755v1_full absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_108755v1_full, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
>
>
> Participating hosts (10 -> 10)
> ------------------------------
>
> No changes in participating hosts
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_108755v1_full:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_suspend@debugfs-reader:
> - shard-tglb: [PASS][1] -> [INCOMPLETE][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb3/igt@i915_suspend@debugfs-reader.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb1/igt@i915_suspend@debugfs-reader.html
Looks like the system simply never came back from suspend; no errors in
dmesg. Does not appear related to this series.
Matt
>
>
> #### Warnings ####
>
> * igt@runner@aborted:
> - shard-skl: ([FAIL][3], [FAIL][4], [FAIL][5], [FAIL][6], [FAIL][7], [FAIL][8], [FAIL][9], [FAIL][10], [FAIL][11], [FAIL][12], [FAIL][13], [FAIL][14], [FAIL][15], [FAIL][16], [FAIL][17], [FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26], [FAIL][27]) ([i915#6599]) -> ([FAIL][28], [FAIL][29], [FAIL][30], [FAIL][31], [FAIL][32], [FAIL][33], [FAIL][34], [FAIL][35], [FAIL][36], [FAIL][37], [FAIL][38], [FAIL][39], [FAIL][40], [FAIL][41], [FAIL][42], [FAIL][43], [FAIL][44], [FAIL][45], [FAIL][46], [FAIL][47], [FAIL][48], [FAIL][49], [FAIL][50], [FAIL][51], [FAIL][52])
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl1/igt@runner@aborted.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl10/igt@runner@aborted.html
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl6/igt@runner@aborted.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl4/igt@runner@aborted.html
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl7/igt@runner@aborted.html
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-skl9/igt@runner@aborted.html
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl10/igt@runner@aborted.html
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl7/igt@runner@aborted.html
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl10/igt@runner@aborted.html
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl4/igt@runner@aborted.html
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl6/igt@runner@aborted.html
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl7/igt@runner@aborted.html
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl4/igt@runner@aborted.html
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl6/igt@runner@aborted.html
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl10/igt@runner@aborted.html
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl10/igt@runner@aborted.html
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl6/igt@runner@aborted.html
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl7/igt@runner@aborted.html
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl4/igt@runner@aborted.html
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl10/igt@runner@aborted.html
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl7/igt@runner@aborted.html
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl1/igt@runner@aborted.html
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl6/igt@runner@aborted.html
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl1/igt@runner@aborted.html
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl1/igt@runner@aborted.html
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl1/igt@runner@aborted.html
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl9/igt@runner@aborted.html
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl4/igt@runner@aborted.html
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl9/igt@runner@aborted.html
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl9/igt@runner@aborted.html
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-skl9/igt@runner@aborted.html
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_108755v1_full that come from known issues:
>
> ### CI changes ###
>
> #### Issues hit ####
>
> * boot:
> - shard-apl: ([PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [PASS][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71], [PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77]) -> ([PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93], [PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [FAIL][101], [PASS][102]) ([i915#4386])
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/boot.html
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/boot.html
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/boot.html
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/boot.html
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl2/boot.html
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl2/boot.html
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl2/boot.html
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl2/boot.html
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/boot.html
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/boot.html
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/boot.html
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/boot.html
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/boot.html
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/boot.html
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/boot.html
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/boot.html
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/boot.html
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/boot.html
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl7/boot.html
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl7/boot.html
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl7/boot.html
> [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/boot.html
> [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/boot.html
> [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/boot.html
> [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/boot.html
> [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/boot.html
> [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/boot.html
> [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/boot.html
> [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl2/boot.html
> [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/boot.html
> [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl2/boot.html
> [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/boot.html
> [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/boot.html
> [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/boot.html
> [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/boot.html
> [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/boot.html
> [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/boot.html
> [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/boot.html
> [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/boot.html
> [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/boot.html
> [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/boot.html
> [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/boot.html
> [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/boot.html
> [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl2/boot.html
> [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl1/boot.html
> [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl1/boot.html
> [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl1/boot.html
> [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl1/boot.html
> [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl2/boot.html
> [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/boot.html
>
>
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_exec_balancer@parallel:
> - shard-iclb: [PASS][103] -> [SKIP][104] ([i915#4525])
> [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb1/igt@gem_exec_balancer@parallel.html
> [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb5/igt@gem_exec_balancer@parallel.html
>
> * igt@gem_exec_fair@basic-none@vecs0:
> - shard-glk: [PASS][105] -> [FAIL][106] ([i915#2842])
> [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk9/igt@gem_exec_fair@basic-none@vecs0.html
> [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk1/igt@gem_exec_fair@basic-none@vecs0.html
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - shard-apl: [PASS][107] -> [FAIL][108] ([i915#2842])
> [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/igt@gem_exec_fair@basic-pace-share@rcs0.html
> - shard-tglb: [PASS][109] -> [FAIL][110] ([i915#2842])
> [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb5/igt@gem_exec_fair@basic-pace-share@rcs0.html
>
> * igt@gem_exec_flush@basic-uc-set-default:
> - shard-apl: [PASS][111] -> [DMESG-FAIL][112] ([i915#6864])
> [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/igt@gem_exec_flush@basic-uc-set-default.html
> [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/igt@gem_exec_flush@basic-uc-set-default.html
>
> * igt@gem_softpin@evict-single-offset:
> - shard-tglb: [PASS][113] -> [FAIL][114] ([i915#4171])
> [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb3/igt@gem_softpin@evict-single-offset.html
> [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb1/igt@gem_softpin@evict-single-offset.html
>
> * igt@gem_userptr_blits@input-checking:
> - shard-apl: NOTRUN -> [DMESG-WARN][115] ([i915#4991])
> [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@gem_userptr_blits@input-checking.html
>
> * igt@gen7_exec_parse@oacontrol-tracking:
> - shard-apl: NOTRUN -> [SKIP][116] ([fdo#109271]) +57 similar issues
> [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@gen7_exec_parse@oacontrol-tracking.html
>
> * igt@i915_pm_rps@engine-order:
> - shard-apl: [PASS][117] -> [FAIL][118] ([i915#6537])
> [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/igt@i915_pm_rps@engine-order.html
> [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/igt@i915_pm_rps@engine-order.html
>
> * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
> - shard-apl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#3886]) +1 similar issue
> [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
>
> * igt@kms_color_chamelium@ctm-red-to-blue:
> - shard-apl: NOTRUN -> [SKIP][120] ([fdo#109271] / [fdo#111827]) +2 similar issues
> [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@kms_color_chamelium@ctm-red-to-blue.html
>
> * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
> - shard-glk: [PASS][121] -> [FAIL][122] ([i915#2346])
> [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
> [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
>
> * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
> - shard-glk: NOTRUN -> [SKIP][123] ([fdo#109271])
> [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk6/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
>
> * igt@kms_fbcon_fbt@fbc-suspend:
> - shard-apl: [PASS][124] -> [FAIL][125] ([i915#4767])
> [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
> [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
>
> * igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
> - shard-apl: [PASS][126] -> [DMESG-WARN][127] ([i915#180]) +1 similar issue
> [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
> [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
>
> * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode:
> - shard-iclb: NOTRUN -> [SKIP][128] ([i915#2672]) +5 similar issues
> [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-default-mode.html
>
> * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
> - shard-iclb: NOTRUN -> [SKIP][129] ([i915#2587] / [i915#2672]) +2 similar issues
> [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html
>
> * igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2:
> - shard-glk: [PASS][130] -> [DMESG-WARN][131] ([i915#118] / [i915#1888])
> [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2.html
> [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@kms_plane_lowres@tiling-y@pipe-a-hdmi-a-2.html
>
> * igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1:
> - shard-iclb: [PASS][132] -> [SKIP][133] ([i915#5176]) +2 similar issues
> [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb1/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
> [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1.html
>
> * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
> - shard-iclb: [PASS][134] -> [SKIP][135] ([i915#5235]) +2 similar issues
> [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb6/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
> [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
>
> * igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf:
> - shard-apl: NOTRUN -> [SKIP][136] ([fdo#109271] / [i915#658])
> [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf.html
>
> * igt@kms_psr@psr2_sprite_plane_onoff:
> - shard-iclb: [PASS][137] -> [SKIP][138] ([fdo#109441]) +2 similar issues
> [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb2/igt@kms_psr@psr2_sprite_plane_onoff.html
> [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb1/igt@kms_psr@psr2_sprite_plane_onoff.html
>
> * igt@kms_vblank@pipe-d-wait-idle:
> - shard-apl: NOTRUN -> [SKIP][139] ([fdo#109271] / [i915#533])
> [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@kms_vblank@pipe-d-wait-idle.html
>
> * igt@perf@stress-open-close:
> - shard-glk: [PASS][140] -> [INCOMPLETE][141] ([i915#5213])
> [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@perf@stress-open-close.html
> [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@perf@stress-open-close.html
>
>
> #### Possible fixes ####
>
> * igt@feature_discovery@psr2:
> - shard-iclb: [SKIP][142] ([i915#658]) -> [PASS][143]
> [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb1/igt@feature_discovery@psr2.html
> [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@feature_discovery@psr2.html
>
> * igt@gem_ctx_exec@basic-nohangcheck:
> - shard-tglb: [FAIL][144] ([i915#6268]) -> [PASS][145]
> [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb3/igt@gem_ctx_exec@basic-nohangcheck.html
> [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb1/igt@gem_ctx_exec@basic-nohangcheck.html
>
> * igt@gem_exec_balancer@parallel-bb-first:
> - shard-iclb: [SKIP][146] ([i915#4525]) -> [PASS][147]
> [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb6/igt@gem_exec_balancer@parallel-bb-first.html
> [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@gem_exec_balancer@parallel-bb-first.html
>
> * igt@gem_exec_fair@basic-pace-share@rcs0:
> - shard-glk: [FAIL][148] ([i915#2842]) -> [PASS][149]
> [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
> [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
>
> * igt@gem_workarounds@suspend-resume:
> - shard-apl: [DMESG-WARN][150] ([i915#180]) -> [PASS][151] +1 similar issue
> [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/igt@gem_workarounds@suspend-resume.html
> [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@gem_workarounds@suspend-resume.html
>
> * igt@i915_pm_dc@dc5-psr:
> - shard-iclb: [FAIL][152] ([i915#3989]) -> [PASS][153]
> [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb8/igt@i915_pm_dc@dc5-psr.html
> [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb3/igt@i915_pm_dc@dc5-psr.html
>
> * igt@i915_selftest@live@hangcheck:
> - shard-tglb: [DMESG-WARN][154] ([i915#5591]) -> [PASS][155]
> [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb5/igt@i915_selftest@live@hangcheck.html
> [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb3/igt@i915_selftest@live@hangcheck.html
>
> * igt@kms_frontbuffer_tracking@fbc-badstride:
> - shard-snb: [SKIP][156] ([fdo#109271]) -> [PASS][157]
> [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-snb4/igt@kms_frontbuffer_tracking@fbc-badstride.html
> [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-snb2/igt@kms_frontbuffer_tracking@fbc-badstride.html
>
> * igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1:
> - shard-glk: [FAIL][158] ([i915#1888]) -> [PASS][159]
> [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1.html
> [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@kms_plane_lowres@tiling-y@pipe-c-hdmi-a-1.html
>
> * igt@kms_psr@psr2_cursor_blt:
> - shard-iclb: [SKIP][160] ([fdo#109441]) -> [PASS][161] +2 similar issues
> [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html
> [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
>
> * igt@kms_vblank@pipe-b-accuracy-idle:
> - shard-glk: [FAIL][162] ([i915#43]) -> [PASS][163]
> [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@kms_vblank@pipe-b-accuracy-idle.html
> [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@kms_vblank@pipe-b-accuracy-idle.html
>
>
> #### Warnings ####
>
> * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
> - shard-iclb: [FAIL][164] ([i915#2684]) -> [WARN][165] ([i915#2684])
> [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
> [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb1/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
>
> * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
> - shard-iclb: [SKIP][166] ([i915#2920]) -> [SKIP][167] ([i915#658])
> [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
> [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
>
> * igt@kms_psr2_su@page_flip-nv12:
> - shard-iclb: [SKIP][168] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][169] ([i915#5939])
> [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html
> [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
>
> * igt@runner@aborted:
> - shard-apl: ([FAIL][170], [FAIL][171], [FAIL][172], [FAIL][173]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177], [FAIL][178], [FAIL][179]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
> [170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl8/igt@runner@aborted.html
> [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl1/igt@runner@aborted.html
> [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl3/igt@runner@aborted.html
> [173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-apl6/igt@runner@aborted.html
> [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl8/igt@runner@aborted.html
> [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl6/igt@runner@aborted.html
> [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/igt@runner@aborted.html
> [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl7/igt@runner@aborted.html
> [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl3/igt@runner@aborted.html
> [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-apl1/igt@runner@aborted.html
> - shard-tglb: ([FAIL][180], [FAIL][181]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][182], [FAIL][183]) ([i915#3002] / [i915#4312] / [i915#5257])
> [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb8/igt@runner@aborted.html
> [181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-tglb1/igt@runner@aborted.html
> [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb8/igt@runner@aborted.html
> [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-tglb7/igt@runner@aborted.html
> - shard-glk: ([FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][188], [FAIL][189], [FAIL][190], [FAIL][191], [FAIL][192]) ([i915#3002] / [i915#4312] / [i915#5257])
> [184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk6/igt@runner@aborted.html
> [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/igt@runner@aborted.html
> [186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk2/igt@runner@aborted.html
> [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-glk1/igt@runner@aborted.html
> [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk2/igt@runner@aborted.html
> [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk8/igt@runner@aborted.html
> [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk2/igt@runner@aborted.html
> [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@runner@aborted.html
> [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-glk9/igt@runner@aborted.html
> - shard-iclb: ([FAIL][193], [FAIL][194]) ([i915#3002] / [i915#4312] / [i915#5257] / [i915#6599]) -> ([FAIL][195], [FAIL][196]) ([i915#3002] / [i915#4312] / [i915#5257])
> [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb7/igt@runner@aborted.html
> [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12158/shard-iclb5/igt@runner@aborted.html
> [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb4/igt@runner@aborted.html
> [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/shard-iclb6/igt@runner@aborted.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
> [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
> [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
> [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
> [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
> [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
> [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
> [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
> [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
> [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
> [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
> [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
> [i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
> [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
> [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
> [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
> [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
> [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
> [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
> [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
> [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
> [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
> [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
> [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
> [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
> [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
> [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
> [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
> [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
> [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
> [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
> [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
> [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
> [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
> [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
> [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
> [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
> [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
> [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
> [i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
> [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
> [i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386
> [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
> [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
> [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
> [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
> [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
> [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
> [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
> [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
> [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
> [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
> [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
> [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
> [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
> [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
> [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
> [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
> [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
> [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
> [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
> [i915#6537]: https://gitlab.freedesktop.org/drm/intel/issues/6537
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#6599]: https://gitlab.freedesktop.org/drm/intel/issues/6599
> [i915#6864]: https://gitlab.freedesktop.org/drm/intel/issues/6864
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_12158 -> Patchwork_108755v1
>
> CI-20190529: 20190529
> CI_DRM_12158: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_6656: 24100c4e181c50e3678aeca9c641b8a43555ad73 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
> Patchwork_108755v1: 3bde74f15d452bf788ecab8933ee802b2ee9e673 @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_108755v1/index.html
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
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