* [Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating
@ 2023-03-01 13:54 Jani Nikula
2023-03-01 13:54 ` [Intel-gfx] [PATCH 1/6] drm/i915/wm: remove display/ prefix from include Jani Nikula
` (8 more replies)
0 siblings, 9 replies; 17+ messages in thread
From: Jani Nikula @ 2023-03-01 13:54 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Finish off some of the cleanups done earlier in intel_pm.[ch]
Jani Nikula (6):
drm/i915/wm: remove display/ prefix from include
drm/i915/pm: drop intel_pm_setup()
drm/i915/pm: drop intel_suspend_hw()
drm/i915: remove unnecessary intel_pm.h includes
drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch]
drm/i915/clock: mass rename dev_priv to i915
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/display/i9xx_wm.c | 1 -
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../drm/i915/display/intel_display_debugfs.c | 1 -
.../drm/i915/display/intel_modeset_setup.c | 1 -
drivers/gpu/drm/i915/display/intel_wm_types.h | 2 +-
drivers/gpu/drm/i915/display/skl_watermark.c | 1 -
drivers/gpu/drm/i915/gt/intel_gt.c | 1 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 -
drivers/gpu/drm/i915/gt/selftest_llc.c | 1 -
drivers/gpu/drm/i915/i915_debugfs.c | 1 -
drivers/gpu/drm/i915/i915_driver.c | 11 +-
drivers/gpu/drm/i915/i915_gem.c | 8 +-
drivers/gpu/drm/i915/i915_irq.c | 1 -
drivers/gpu/drm/i915/i915_pmu.c | 1 -
drivers/gpu/drm/i915/i915_request.c | 1 -
drivers/gpu/drm/i915/i915_sysfs.c | 1 -
drivers/gpu/drm/i915/intel_clock_gating.c | 888 +++++++++++++++++
drivers/gpu/drm/i915/intel_clock_gating.h | 14 +
drivers/gpu/drm/i915/intel_pm.c | 907 ------------------
drivers/gpu/drm/i915/intel_pm.h | 20 -
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +
drivers/gpu/drm/i915/intel_uncore.c | 1 -
drivers/gpu/drm/i915/vlv_suspend.c | 4 +-
24 files changed, 918 insertions(+), 957 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_clock_gating.c
create mode 100644 drivers/gpu/drm/i915/intel_clock_gating.h
delete mode 100644 drivers/gpu/drm/i915/intel_pm.c
delete mode 100644 drivers/gpu/drm/i915/intel_pm.h
--
2.39.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 1/6] drm/i915/wm: remove display/ prefix from include
2023-03-01 13:54 [Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating Jani Nikula
@ 2023-03-01 13:54 ` Jani Nikula
2023-03-02 18:10 ` Rodrigo Vivi
2023-03-01 13:54 ` [Intel-gfx] [PATCH 2/6] drm/i915/pm: drop intel_pm_setup() Jani Nikula
` (7 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2023-03-01 13:54 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Remove the leftover from moving and renaming the file from driver top
level.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_wm_types.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_wm_types.h b/drivers/gpu/drm/i915/display/intel_wm_types.h
index bac2b6fdc5d0..628b7c0ce484 100644
--- a/drivers/gpu/drm/i915/display/intel_wm_types.h
+++ b/drivers/gpu/drm/i915/display/intel_wm_types.h
@@ -8,7 +8,7 @@
#include <linux/types.h>
-#include "display/intel_display_limits.h"
+#include "intel_display_limits.h"
enum intel_ddb_partitioning {
INTEL_DDB_PART_1_2,
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 2/6] drm/i915/pm: drop intel_pm_setup()
2023-03-01 13:54 [Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating Jani Nikula
2023-03-01 13:54 ` [Intel-gfx] [PATCH 1/6] drm/i915/wm: remove display/ prefix from include Jani Nikula
@ 2023-03-01 13:54 ` Jani Nikula
2023-03-02 18:11 ` Rodrigo Vivi
2023-03-01 13:54 ` [Intel-gfx] [PATCH 3/6] drm/i915/pm: drop intel_suspend_hw() Jani Nikula
` (6 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2023-03-01 13:54 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
All the init in intel_pm_setup() is related to runtime pm. Move them to
intel_runtime_pm_init_early(), and remove intel_pm_setup().
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_driver.c | 1 -
drivers/gpu/drm/i915/intel_pm.c | 6 ------
drivers/gpu/drm/i915/intel_pm.h | 1 -
drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
4 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 8bc76dede332..171ff4edabd6 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -250,7 +250,6 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
/* This must be called before any calls to HAS_PCH_* */
intel_detect_pch(dev_priv);
- intel_pm_setup(dev_priv);
intel_irq_init(dev_priv);
intel_init_display_hooks(dev_priv);
intel_init_clock_gating_hooks(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ddf004e5bb4b..8b02af531e82 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -899,9 +899,3 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
dev_priv->clock_gating_funcs = &nop_clock_gating_funcs;
}
}
-
-void intel_pm_setup(struct drm_i915_private *dev_priv)
-{
- dev_priv->runtime_pm.suspended = false;
- atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
-}
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index eab60df0c6bb..1dd464d2d186 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -15,6 +15,5 @@ struct intel_plane_state;
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
void intel_suspend_hw(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
-void intel_pm_setup(struct drm_i915_private *dev_priv);
#endif /* __INTEL_PM_H__ */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 129746713d07..cf5122299b6b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -652,6 +652,8 @@ void intel_runtime_pm_init_early(struct intel_runtime_pm *rpm)
rpm->kdev = kdev;
rpm->available = HAS_RUNTIME_PM(i915);
+ rpm->suspended = false;
+ atomic_set(&rpm->wakeref_count, 0);
init_intel_runtime_pm_wakeref(rpm);
INIT_LIST_HEAD(&rpm->lmem_userfault_list);
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 3/6] drm/i915/pm: drop intel_suspend_hw()
2023-03-01 13:54 [Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating Jani Nikula
2023-03-01 13:54 ` [Intel-gfx] [PATCH 1/6] drm/i915/wm: remove display/ prefix from include Jani Nikula
2023-03-01 13:54 ` [Intel-gfx] [PATCH 2/6] drm/i915/pm: drop intel_pm_setup() Jani Nikula
@ 2023-03-01 13:54 ` Jani Nikula
2023-03-02 18:36 ` Rodrigo Vivi
2023-03-01 13:54 ` [Intel-gfx] [PATCH 4/6] drm/i915: remove unnecessary intel_pm.h includes Jani Nikula
` (5 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2023-03-01 13:54 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
All intel_suspend_hw() does is clear PCH_LP_PARTITION_LEVEL_DISABLE bit
in SOUTH_DSPCLK_GATE_D for LPT LP. intel_suspend_hw() gets called from
i915_drm_suspend().
However, i915_drm_suspend_late() calls
intel_display_power_suspend_late(), which in turn calls hsw_enable_pc8()
on HSW and BDW. The first thing that does is clear
PCH_LP_PARTITION_LEVEL_DISABLE bit in SOUTH_DSPCLK_GATE_D.
Remove the duplicated clearing of the bit, effectively delaying it from
i915_drm_suspend() to i915_drm_suspend_late(), and remove the
unnecessary intel_suspend_hw() function altogether.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_driver.c | 2 --
drivers/gpu/drm/i915/intel_pm.c | 16 ----------------
drivers/gpu/drm/i915/intel_pm.h | 1 -
3 files changed, 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 171ff4edabd6..a53fd339e2cc 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -1079,8 +1079,6 @@ static int i915_drm_suspend(struct drm_device *dev)
intel_suspend_encoders(dev_priv);
- intel_suspend_hw(dev_priv);
-
/* Must be called before GGTT is suspended. */
intel_dpt_suspend(dev_priv);
i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b02af531e82..c45af0d981fd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -320,16 +320,6 @@ static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
}
-static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
-{
- if (HAS_PCH_LPT_LP(dev_priv)) {
- u32 val = intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D);
-
- val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
- intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, val);
- }
-}
-
static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
int general_prio_credits,
int high_prio_credits)
@@ -789,12 +779,6 @@ void intel_init_clock_gating(struct drm_i915_private *dev_priv)
dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
}
-void intel_suspend_hw(struct drm_i915_private *dev_priv)
-{
- if (HAS_PCH_LPT(dev_priv))
- lpt_suspend_hw(dev_priv);
-}
-
static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
{
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 1dd464d2d186..f774bddcdca6 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -13,7 +13,6 @@ struct intel_crtc_state;
struct intel_plane_state;
void intel_init_clock_gating(struct drm_i915_private *dev_priv);
-void intel_suspend_hw(struct drm_i915_private *dev_priv);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
#endif /* __INTEL_PM_H__ */
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 4/6] drm/i915: remove unnecessary intel_pm.h includes
2023-03-01 13:54 [Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating Jani Nikula
` (2 preceding siblings ...)
2023-03-01 13:54 ` [Intel-gfx] [PATCH 3/6] drm/i915/pm: drop intel_suspend_hw() Jani Nikula
@ 2023-03-01 13:54 ` Jani Nikula
2023-03-02 18:37 ` Rodrigo Vivi
2023-03-01 13:54 ` [Intel-gfx] [PATCH 5/6] drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch] Jani Nikula
` (4 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2023-03-01 13:54 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
As intel_pm.[ch] used to contain much more, intel_pm.h was included in a
lot of places. Many of them are now unnecessary. Remove.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 1 -
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 1 -
drivers/gpu/drm/i915/display/skl_watermark.c | 1 -
drivers/gpu/drm/i915/gt/intel_gt.c | 1 -
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 -
drivers/gpu/drm/i915/gt/selftest_llc.c | 1 -
drivers/gpu/drm/i915/i915_debugfs.c | 1 -
drivers/gpu/drm/i915/i915_irq.c | 1 -
drivers/gpu/drm/i915/i915_pmu.c | 1 -
drivers/gpu/drm/i915/i915_request.c | 1 -
drivers/gpu/drm/i915/i915_sysfs.c | 1 -
drivers/gpu/drm/i915/intel_uncore.c | 1 -
13 files changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 3d4687efe4dd..caef72d38798 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -9,7 +9,6 @@
#include "intel_display.h"
#include "intel_display_trace.h"
#include "intel_mchbar_regs.h"
-#include "intel_pm.h"
#include "intel_wm.h"
#include "skl_watermark.h"
#include "vlv_sideband.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 25013f303c82..1e654ddd0815 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -26,7 +26,6 @@
#include "intel_hdmi.h"
#include "intel_hotplug.h"
#include "intel_panel.h"
-#include "intel_pm.h"
#include "intel_psr.h"
#include "intel_sprite.h"
#include "intel_wm.h"
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 60f71e6f0491..7ff083ec2d1d 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -25,7 +25,6 @@
#include "intel_fifo_underrun.h"
#include "intel_modeset_setup.h"
#include "intel_pch_display.h"
-#include "intel_pm.h"
#include "intel_wm.h"
#include "skl_watermark.h"
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1300965d328a..f0af997d2a23 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -18,7 +18,6 @@
#include "intel_display_types.h"
#include "intel_fb.h"
#include "intel_pcode.h"
-#include "intel_pm.h"
#include "intel_wm.h"
#include "skl_watermark.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index f7f271708fc7..6ca944d01eb6 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -28,7 +28,6 @@
#include "intel_migrate.h"
#include "intel_mocs.h"
#include "intel_pci_config.h"
-#include "intel_pm.h"
#include "intel_rc6.h"
#include "intel_renderstate.h"
#include "intel_rps.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index cef3d6f5c34e..85ae7dc079f2 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -17,7 +17,6 @@
#include "intel_gt_print.h"
#include "intel_gt_requests.h"
#include "intel_llc.h"
-#include "intel_pm.h"
#include "intel_rc6.h"
#include "intel_rps.h"
#include "intel_wakeref.h"
diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
index cfd736d88939..779fadcec7c4 100644
--- a/drivers/gpu/drm/i915/gt/selftest_llc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
@@ -3,7 +3,6 @@
* Copyright © 2019 Intel Corporation
*/
-#include "intel_pm.h" /* intel_gpu_freq() */
#include "selftest_llc.h"
#include "intel_rps.h"
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 45773ce1deac..16011c0286ad 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -52,7 +52,6 @@
#include "i915_irq.h"
#include "i915_scheduler.h"
#include "intel_mchbar_regs.h"
-#include "intel_pm.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 417c981e4968..6ce3c934d832 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -52,7 +52,6 @@
#include "i915_driver.h"
#include "i915_drv.h"
#include "i915_irq.h"
-#include "intel_pm.h"
/**
* DOC: interrupt handling
diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 52531ab28c5f..a76c5ce9513d 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -17,7 +17,6 @@
#include "i915_drv.h"
#include "i915_pmu.h"
-#include "intel_pm.h"
/* Frequency for the sampling timer for events which need it. */
#define FREQUENCY 200
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 7503dcb9043b..630a732aaecc 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -48,7 +48,6 @@
#include "i915_driver.h"
#include "i915_drv.h"
#include "i915_trace.h"
-#include "intel_pm.h"
struct execute_cb {
struct irq_work work;
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 595e8b574990..e88bb4f04305 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -37,7 +37,6 @@
#include "i915_drv.h"
#include "i915_sysfs.h"
-#include "intel_pm.h"
struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
{
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index f018da7ebaac..f4b3b2063018 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -32,7 +32,6 @@
#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
-#include "intel_pm.h"
#define FORCEWAKE_ACK_TIMEOUT_MS 50
#define GT_FIFO_TIMEOUT_MS 10
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 5/6] drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch]
2023-03-01 13:54 [Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating Jani Nikula
` (3 preceding siblings ...)
2023-03-01 13:54 ` [Intel-gfx] [PATCH 4/6] drm/i915: remove unnecessary intel_pm.h includes Jani Nikula
@ 2023-03-01 13:54 ` Jani Nikula
2023-03-02 18:39 ` Rodrigo Vivi
2023-03-01 13:54 ` [Intel-gfx] [PATCH 6/6] drm/i915/clock: mass rename dev_priv to i915 Jani Nikula
` (3 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2023-03-01 13:54 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Observe that intel_pm.[ch] is now purely about clock gating, so rename
them to intel_clock_gating.[ch]. Rename the functions to
intel_clock_gating_*() to follow coding conventions.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
drivers/gpu/drm/i915/i915_driver.c | 8 ++++----
drivers/gpu/drm/i915/i915_gem.c | 8 ++++----
.../i915/{intel_pm.c => intel_clock_gating.c} | 8 ++++----
drivers/gpu/drm/i915/intel_clock_gating.h | 14 ++++++++++++++
drivers/gpu/drm/i915/intel_pm.h | 18 ------------------
drivers/gpu/drm/i915/vlv_suspend.c | 4 ++--
8 files changed, 31 insertions(+), 35 deletions(-)
rename drivers/gpu/drm/i915/{intel_pm.c => intel_clock_gating.c} (99%)
create mode 100644 drivers/gpu/drm/i915/intel_clock_gating.h
delete mode 100644 drivers/gpu/drm/i915/intel_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index b2f91a1f8268..b88df8c10781 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -47,10 +47,10 @@ i915-y += i915_driver.o \
i915_switcheroo.o \
i915_sysfs.o \
i915_utils.o \
+ intel_clock_gating.o \
intel_device_info.o \
intel_memory_region.o \
intel_pcode.o \
- intel_pm.o \
intel_region_ttm.o \
intel_runtime_pm.o \
intel_sbi.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a1fbdf32bd21..3f1b90a2f57c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -63,6 +63,7 @@
#include "intel_audio.h"
#include "intel_bw.h"
#include "intel_cdclk.h"
+#include "intel_clock_gating.h"
#include "intel_color.h"
#include "intel_crt.h"
#include "intel_crtc.h"
@@ -105,7 +106,6 @@
#include "intel_pcode.h"
#include "intel_pipe_crc.h"
#include "intel_plane_initial.h"
-#include "intel_pm.h"
#include "intel_pps.h"
#include "intel_psr.h"
#include "intel_quirks.h"
@@ -850,7 +850,7 @@ void intel_display_finish_reset(struct drm_i915_private *i915)
*/
intel_pps_unlock_regs_wa(i915);
intel_modeset_init_hw(i915);
- intel_init_clock_gating(i915);
+ intel_clock_gating_init(i915);
intel_hpd_init(i915);
ret = __intel_display_resume(i915, state, ctx);
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index a53fd339e2cc..e4809485e47c 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -79,11 +79,11 @@
#include "soc/intel_dram.h"
#include "soc/intel_gmch.h"
-#include "i915_file_private.h"
#include "i915_debugfs.h"
#include "i915_driver.h"
#include "i915_drm_client.h"
#include "i915_drv.h"
+#include "i915_file_private.h"
#include "i915_getparam.h"
#include "i915_hwmon.h"
#include "i915_ioc32.h"
@@ -97,11 +97,11 @@
#include "i915_sysfs.h"
#include "i915_utils.h"
#include "i915_vgpu.h"
+#include "intel_clock_gating.h"
#include "intel_gvt.h"
#include "intel_memory_region.h"
#include "intel_pci_config.h"
#include "intel_pcode.h"
-#include "intel_pm.h"
#include "intel_region_ttm.h"
#include "vlv_suspend.h"
@@ -252,7 +252,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
intel_irq_init(dev_priv);
intel_init_display_hooks(dev_priv);
- intel_init_clock_gating_hooks(dev_priv);
+ intel_clock_gating_hooks_init(dev_priv);
intel_detect_preproduction_hw(dev_priv);
@@ -1238,7 +1238,7 @@ static int i915_drm_resume(struct drm_device *dev)
i915_gem_resume(dev_priv);
intel_modeset_init_hw(dev_priv);
- intel_init_clock_gating(dev_priv);
+ intel_clock_gating_init(dev_priv);
intel_hpd_init(dev_priv);
/* MST sideband requires HPD interrupts enabled */
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 35950fa91406..6b6b0e575ef3 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -58,7 +58,7 @@
#include "i915_file_private.h"
#include "i915_trace.h"
#include "i915_vgpu.h"
-#include "intel_pm.h"
+#include "intel_clock_gating.h"
static int
insert_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node, u32 size)
@@ -1164,7 +1164,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
}
/*
- * Despite its name intel_init_clock_gating applies both display
+ * Despite its name intel_clock_gating_init applies both display
* clock gating workarounds; GT mmio workarounds and the occasional
* GT power context workaround. Worse, sometimes it includes a context
* register workaround which we need to apply before we record the
@@ -1172,7 +1172,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
*
* FIXME: break up the workarounds and apply them at the right time!
*/
- intel_init_clock_gating(dev_priv);
+ intel_clock_gating_init(dev_priv);
for_each_gt(gt, dev_priv, i) {
ret = intel_gt_init(gt);
@@ -1216,7 +1216,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
/* Minimal basic recovery for KMS */
ret = i915_ggtt_enable_hw(dev_priv);
i915_ggtt_resume(to_gt(dev_priv)->ggtt);
- intel_init_clock_gating(dev_priv);
+ intel_clock_gating_init(dev_priv);
}
i915_gem_drain_freed_objects(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_clock_gating.c
similarity index 99%
rename from drivers/gpu/drm/i915/intel_pm.c
rename to drivers/gpu/drm/i915/intel_clock_gating.c
index c45af0d981fd..8cfc19b48760 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -36,8 +36,8 @@
#include "gt/intel_gt_regs.h"
#include "i915_drv.h"
+#include "intel_clock_gating.h"
#include "intel_mchbar_regs.h"
-#include "intel_pm.h"
#include "vlv_sideband.h"
struct drm_i915_clock_gating_funcs {
@@ -774,7 +774,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
_MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
}
-void intel_init_clock_gating(struct drm_i915_private *dev_priv)
+void intel_clock_gating_init(struct drm_i915_private *dev_priv)
{
dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
}
@@ -818,7 +818,7 @@ CG_FUNCS(nop);
#undef CG_FUNCS
/**
- * intel_init_clock_gating_hooks - setup the clock gating hooks
+ * intel_clock_gating_hooks_init - setup the clock gating hooks
* @dev_priv: device private
*
* Setup the hooks that configure which clocks of a given platform can be
@@ -826,7 +826,7 @@ CG_FUNCS(nop);
* platforms. Note that some GT specific workarounds are applied separately
* when GPU contexts or batchbuffers start their execution.
*/
-void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
+void intel_clock_gating_hooks_init(struct drm_i915_private *dev_priv)
{
if (IS_METEORLAKE(dev_priv))
dev_priv->clock_gating_funcs = &nop_clock_gating_funcs;
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.h b/drivers/gpu/drm/i915/intel_clock_gating.h
new file mode 100644
index 000000000000..5b4e4c55b2c2
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_clock_gating.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef __INTEL_CLOCK_GATING_H__
+#define __INTEL_CLOCK_GATING_H__
+
+struct drm_i915_private;
+
+void intel_clock_gating_init(struct drm_i915_private *i915);
+void intel_clock_gating_hooks_init(struct drm_i915_private *i915);
+
+#endif /* __INTEL_CLOCK_GATING_H__ */
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
deleted file mode 100644
index f774bddcdca6..000000000000
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2019 Intel Corporation
- */
-
-#ifndef __INTEL_PM_H__
-#define __INTEL_PM_H__
-
-#include <linux/types.h>
-
-struct drm_i915_private;
-struct intel_crtc_state;
-struct intel_plane_state;
-
-void intel_init_clock_gating(struct drm_i915_private *dev_priv);
-void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
-
-#endif /* __INTEL_PM_H__ */
diff --git a/drivers/gpu/drm/i915/vlv_suspend.c b/drivers/gpu/drm/i915/vlv_suspend.c
index 02e63ed77f60..94595dde2b96 100644
--- a/drivers/gpu/drm/i915/vlv_suspend.c
+++ b/drivers/gpu/drm/i915/vlv_suspend.c
@@ -12,7 +12,7 @@
#include "i915_reg.h"
#include "i915_trace.h"
#include "i915_utils.h"
-#include "intel_pm.h"
+#include "intel_clock_gating.h"
#include "vlv_suspend.h"
#include "gt/intel_gt_regs.h"
@@ -451,7 +451,7 @@ int vlv_resume_prepare(struct drm_i915_private *dev_priv, bool rpm_resume)
vlv_check_no_gt_access(dev_priv);
if (rpm_resume)
- intel_init_clock_gating(dev_priv);
+ intel_clock_gating_init(dev_priv);
return ret;
}
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 6/6] drm/i915/clock: mass rename dev_priv to i915
2023-03-01 13:54 [Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating Jani Nikula
` (4 preceding siblings ...)
2023-03-01 13:54 ` [Intel-gfx] [PATCH 5/6] drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch] Jani Nikula
@ 2023-03-01 13:54 ` Jani Nikula
2023-03-02 18:40 ` Rodrigo Vivi
2023-03-01 20:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: pm cleanups, rename to clock gating Patchwork
` (2 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Jani Nikula @ 2023-03-01 13:54 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Follow the contemporary naming style. Include some indentation fixes
while at it on the affected statements.
One function needs to keep using dev_priv due to implicit dev_priv usage
in a macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_clock_gating.c | 589 +++++++++++-----------
1 file changed, 296 insertions(+), 293 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 8cfc19b48760..2c5302bcba19 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -44,9 +44,9 @@ struct drm_i915_clock_gating_funcs {
void (*init_clock_gating)(struct drm_i915_private *i915);
};
-static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
+static void gen9_init_clock_gating(struct drm_i915_private *i915)
{
- if (HAS_LLC(dev_priv)) {
+ if (HAS_LLC(i915)) {
/*
* WaCompressedResourceDisplayNewHashMode:skl,kbl
* Display WA #0390: skl,kbl
@@ -54,41 +54,42 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
* Must match Sampler, Pixel Back End, and Media. See
* WaCompressedResourceSamplerPbeMediaNewHashMode.
*/
- intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
+ intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
}
/* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
- intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
+ intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
/* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
- intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
+ intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
/*
* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
* Display WA #0859: skl,bxt,kbl,glk,cfl
*/
- intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
+ intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
}
-static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
+static void bxt_init_clock_gating(struct drm_i915_private *i915)
{
- gen9_init_clock_gating(dev_priv);
+ gen9_init_clock_gating(i915);
/* WaDisableSDEUnitClockGating:bxt */
- intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
/*
* FIXME:
* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
*/
- intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
+ intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
/*
* Wa: Backlight PWM may stop in the asserted state, causing backlight
* to stay fully on.
*/
- intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
- PWM1_GATING_DIS | PWM2_GATING_DIS);
+ intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
+ intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
+ PWM1_GATING_DIS | PWM2_GATING_DIS);
/*
* Lower the display internal timeout.
@@ -96,42 +97,43 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
* is off and a MMIO access is attempted by any privilege
* application, using batch buffers or any other means.
*/
- intel_uncore_write(&dev_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
+ intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
/*
* WaFbcTurnOffFbcWatermark:bxt
* Display WA #0562: bxt
*/
- intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+ intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
/*
* WaFbcHighMemBwCorruptionAvoidance:bxt
* Display WA #0883: bxt
*/
- intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0);
+ intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0);
}
-static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
+static void glk_init_clock_gating(struct drm_i915_private *i915)
{
- gen9_init_clock_gating(dev_priv);
+ gen9_init_clock_gating(i915);
/*
* WaDisablePWMClockGating:glk
* Backlight PWM may stop in the asserted state, causing backlight
* to stay fully on.
*/
- intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
- PWM1_GATING_DIS | PWM2_GATING_DIS);
+ intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
+ intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
+ PWM1_GATING_DIS | PWM2_GATING_DIS);
}
-static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
+static void ibx_init_clock_gating(struct drm_i915_private *i915)
{
/*
* On Ibex Peak and Cougar Point, we need to disable clock
* gating for the panel power sequencer or it will fail to
* start up when no ports are active.
*/
- intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
}
static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
@@ -146,7 +148,7 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
}
}
-static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
+static void ilk_init_clock_gating(struct drm_i915_private *i915)
{
u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
@@ -158,11 +160,11 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
- intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS0,
- MARIUNIT_CLOCK_GATE_DISABLE |
- SVSMUNIT_CLOCK_GATE_DISABLE);
- intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS1,
- VFMUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_write(&i915->uncore, PCH_3DCGDIS0,
+ MARIUNIT_CLOCK_GATE_DISABLE |
+ SVSMUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_write(&i915->uncore, PCH_3DCGDIS1,
+ VFMUNIT_CLOCK_GATE_DISABLE);
/*
* According to the spec the following bits should be set in
@@ -171,13 +173,13 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
* The bit 5 of 0x42020
* The bit 15 of 0x45000
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
- (intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
- ILK_DPARB_GATE | ILK_VSDPFD_FULL));
+ intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
+ (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
+ ILK_DPARB_GATE | ILK_VSDPFD_FULL));
dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
- intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL,
- (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
- DISP_FBC_WM_DIS));
+ intel_uncore_write(&i915->uncore, DISP_ARB_CTL,
+ (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) |
+ DISP_FBC_WM_DIS));
/*
* Based on the document from hardware guys the following bits
@@ -186,22 +188,22 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
* The bit 22 of 0x42004
* The bit 7,8,9 of 0x42020.
*/
- if (IS_IRONLAKE_M(dev_priv)) {
+ if (IS_IRONLAKE_M(i915)) {
/* WaFbcAsynchFlipDisableFbcQueue:ilk */
- intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
- intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
+ intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
+ intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
}
- intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
+ intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
- intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
+ intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
- g4x_disable_trickle_feed(dev_priv);
+ g4x_disable_trickle_feed(i915);
- ibx_init_clock_gating(dev_priv);
+ ibx_init_clock_gating(i915);
}
-static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
+static void cpt_init_clock_gating(struct drm_i915_private *i915)
{
enum pipe pipe;
u32 val;
@@ -211,53 +213,53 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
* gating for the panel power sequencer or it will fail to
* start up when no ports are active.
*/
- intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
- PCH_DPLUNIT_CLOCK_GATE_DISABLE |
- PCH_CPUNIT_CLOCK_GATE_DISABLE);
- intel_uncore_rmw(&dev_priv->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);
+ intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
+ PCH_DPLUNIT_CLOCK_GATE_DISABLE |
+ PCH_CPUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);
/* The below fixes the weird display corruption, a few pixels shifted
* downward, on (only) LVDS of some HP laptops with IVY.
*/
- for_each_pipe(dev_priv, pipe) {
- val = intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN2(pipe));
+ for_each_pipe(i915, pipe) {
+ val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe));
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
- if (dev_priv->display.vbt.fdi_rx_polarity_inverted)
+ if (i915->display.vbt.fdi_rx_polarity_inverted)
val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
- intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN2(pipe), val);
+ intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val);
}
/* WADP0ClockGatingDisable */
- for_each_pipe(dev_priv, pipe) {
- intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(pipe),
- TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
+ for_each_pipe(i915, pipe) {
+ intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe),
+ TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
}
}
-static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
+static void gen6_check_mch_setup(struct drm_i915_private *i915)
{
u32 tmp;
- tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
+ tmp = intel_uncore_read(&i915->uncore, MCH_SSKPD);
if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12)
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
tmp);
}
-static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
+static void gen6_init_clock_gating(struct drm_i915_private *i915)
{
u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
- intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
+ intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
- intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
+ intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
- intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
- intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
- GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
- GEN6_CSUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_write(&i915->uncore, GEN6_UCGCTL1,
+ intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) |
+ GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
+ GEN6_CSUNIT_CLOCK_GATE_DISABLE);
/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
* gating disable must be set. Failure to set it results in
@@ -272,9 +274,9 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
* WaDisableRCCUnitClockGating:snb
* WaDisableRCPBUnitClockGating:snb
*/
- intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
- GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
- GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_write(&i915->uncore, GEN6_UCGCTL2,
+ GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
+ GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
/*
* According to the spec the following bits should be
@@ -287,40 +289,40 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
*
* WaFbcAsynchFlipDisableFbcQueue:snb
*/
- intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
- intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
- ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
- intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
- intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
- ILK_DPARB_GATE | ILK_VSDPFD_FULL);
- intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D,
- intel_uncore_read(&dev_priv->uncore, ILK_DSPCLK_GATE_D) |
- ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
- ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
+ intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1,
+ intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) |
+ ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
+ intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
+ intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
+ ILK_DPARB_GATE | ILK_VSDPFD_FULL);
+ intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D,
+ intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) |
+ ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
+ ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
- g4x_disable_trickle_feed(dev_priv);
+ g4x_disable_trickle_feed(i915);
- cpt_init_clock_gating(dev_priv);
+ cpt_init_clock_gating(i915);
- gen6_check_mch_setup(dev_priv);
+ gen6_check_mch_setup(i915);
}
-static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
+static void lpt_init_clock_gating(struct drm_i915_private *i915)
{
/*
* TODO: this bit should only be enabled when really needed, then
* disabled when not needed anymore in order to save power.
*/
- if (HAS_PCH_LPT_LP(dev_priv))
- intel_uncore_rmw(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D,
+ if (HAS_PCH_LPT_LP(i915))
+ intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D,
0, PCH_LP_PARTITION_LEVEL_DISABLE);
/* WADPOClockGatingDisable:hsw */
- intel_uncore_rmw(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A),
+ intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A),
0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
}
-static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
+static void gen8_set_l3sqc_credits(struct drm_i915_private *i915,
int general_prio_credits,
int high_prio_credits)
{
@@ -328,64 +330,64 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
u32 val;
/* WaTempDisableDOPClkGating:bdw */
- misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
+ misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
GEN7_DOP_CLOCK_GATE_ENABLE, 0);
- val = intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_L3SQCREG1);
+ val = intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1);
val &= ~L3_PRIO_CREDITS_MASK;
val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
- intel_gt_mcr_multicast_write(to_gt(dev_priv), GEN8_L3SQCREG1, val);
+ intel_gt_mcr_multicast_write(to_gt(i915), GEN8_L3SQCREG1, val);
/*
* Wait at least 100 clocks before re-enabling clock gating.
* See the definition of L3SQCREG1 in BSpec.
*/
- intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_L3SQCREG1);
+ intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1);
udelay(1);
- intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
+ intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl);
}
-static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
+static void icl_init_clock_gating(struct drm_i915_private *i915)
{
/* Wa_1409120013:icl,ehl */
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+ intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
DPFC_CHICKEN_COMP_DUMMY_PIXEL);
/*Wa_14010594013:icl, ehl */
- intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
+ intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1,
0, ICL_DELAY_PMRSP);
}
-static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
+static void gen12lp_init_clock_gating(struct drm_i915_private *i915)
{
/* Wa_1409120013 */
- if (DISPLAY_VER(dev_priv) == 12)
- intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+ if (DISPLAY_VER(i915) == 12)
+ intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
DPFC_CHICKEN_COMP_DUMMY_PIXEL);
/* Wa_14013723622:tgl,rkl,dg1,adl-s */
- if (DISPLAY_VER(dev_priv) == 12)
- intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
+ if (DISPLAY_VER(i915) == 12)
+ intel_uncore_rmw(&i915->uncore, CLKREQ_POLICY,
CLKREQ_POLICY_MEM_UP_OVRD, 0);
}
-static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
+static void adlp_init_clock_gating(struct drm_i915_private *i915)
{
- gen12lp_init_clock_gating(dev_priv);
+ gen12lp_init_clock_gating(i915);
/* Wa_22011091694:adlp */
- intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
+ intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
/* Bspec/49189 Initialize Sequence */
- intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
+ intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
}
-static void xehpsdv_init_clock_gating(struct drm_i915_private *dev_priv)
+static void xehpsdv_init_clock_gating(struct drm_i915_private *i915)
{
/* Wa_22010146351:xehpsdv */
- if (IS_XEHPSDV_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
+ if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
+ intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
}
static void dg2_init_clock_gating(struct drm_i915_private *i915)
@@ -403,303 +405,303 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
SGR_DIS | SGGI_DIS);
}
-static void pvc_init_clock_gating(struct drm_i915_private *dev_priv)
+static void pvc_init_clock_gating(struct drm_i915_private *i915)
{
/* Wa_14012385139:pvc */
- if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
+ if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0))
+ intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
/* Wa_22010954014:pvc */
- if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
+ if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0))
+ intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
}
-static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
+static void cnp_init_clock_gating(struct drm_i915_private *i915)
{
- if (!HAS_PCH_CNP(dev_priv))
+ if (!HAS_PCH_CNP(i915))
return;
/* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
- intel_uncore_rmw(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE);
+ intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE);
}
-static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
+static void cfl_init_clock_gating(struct drm_i915_private *i915)
{
- cnp_init_clock_gating(dev_priv);
- gen9_init_clock_gating(dev_priv);
+ cnp_init_clock_gating(i915);
+ gen9_init_clock_gating(i915);
/* WAC6entrylatency:cfl */
- intel_uncore_rmw(&dev_priv->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
+ intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
/*
* WaFbcTurnOffFbcWatermark:cfl
* Display WA #0562: cfl
*/
- intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+ intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
/*
* WaFbcNukeOnHostModify:cfl
* Display WA #0873: cfl
*/
- intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+ intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
0, DPFC_NUKE_ON_ANY_MODIFICATION);
}
-static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
+static void kbl_init_clock_gating(struct drm_i915_private *i915)
{
- gen9_init_clock_gating(dev_priv);
+ gen9_init_clock_gating(i915);
/* WAC6entrylatency:kbl */
- intel_uncore_rmw(&dev_priv->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
+ intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
/* WaDisableSDEUnitClockGating:kbl */
- if (IS_KBL_GRAPHICS_STEP(dev_priv, 0, STEP_C0))
- intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6,
+ if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
+ intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6,
0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
/* WaDisableGamClockGating:kbl */
- if (IS_KBL_GRAPHICS_STEP(dev_priv, 0, STEP_C0))
- intel_uncore_rmw(&dev_priv->uncore, GEN6_UCGCTL1,
+ if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
+ intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1,
0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
/*
* WaFbcTurnOffFbcWatermark:kbl
* Display WA #0562: kbl
*/
- intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+ intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
/*
* WaFbcNukeOnHostModify:kbl
* Display WA #0873: kbl
*/
- intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+ intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
0, DPFC_NUKE_ON_ANY_MODIFICATION);
}
-static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
+static void skl_init_clock_gating(struct drm_i915_private *i915)
{
- gen9_init_clock_gating(dev_priv);
+ gen9_init_clock_gating(i915);
/* WaDisableDopClockGating:skl */
- intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
+ intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
GEN7_DOP_CLOCK_GATE_ENABLE, 0);
/* WAC6entrylatency:skl */
- intel_uncore_rmw(&dev_priv->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
+ intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
/*
* WaFbcTurnOffFbcWatermark:skl
* Display WA #0562: skl
*/
- intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
+ intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
/*
* WaFbcNukeOnHostModify:skl
* Display WA #0873: skl
*/
- intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+ intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
0, DPFC_NUKE_ON_ANY_MODIFICATION);
/*
* WaFbcHighMemBwCorruptionAvoidance:skl
* Display WA #0883: skl
*/
- intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0);
+ intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0);
}
-static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
+static void bdw_init_clock_gating(struct drm_i915_private *i915)
{
enum pipe pipe;
/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
- intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
+ intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
/* WaSwitchSolVfFArbitrationPriority:bdw */
- intel_uncore_rmw(&dev_priv->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
+ intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
/* WaPsrDPAMaskVBlankInSRD:bdw */
- intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0, DPA_MASK_VBLANK_SRD);
+ intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, DPA_MASK_VBLANK_SRD);
- for_each_pipe(dev_priv, pipe) {
+ for_each_pipe(i915, pipe) {
/* WaPsrDPRSUnmaskVBlankInSRD:bdw */
- intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
+ intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
0, BDW_DPRS_MASK_VBLANK_SRD);
}
/* WaVSRefCountFullforceMissDisable:bdw */
/* WaDSRefCountFullforceMissDisable:bdw */
- intel_uncore_rmw(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
+ intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE,
GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0);
- intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
- _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
+ intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
+ _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
/* WaDisableSDEUnitClockGating:bdw */
- intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
/* WaProgramL3SqcReg1Default:bdw */
- gen8_set_l3sqc_credits(dev_priv, 30, 2);
+ gen8_set_l3sqc_credits(i915, 30, 2);
/* WaKVMNotificationOnConfigChange:bdw */
- intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR2_1,
+ intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1,
0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
- lpt_init_clock_gating(dev_priv);
+ lpt_init_clock_gating(i915);
/* WaDisableDopClockGating:bdw
*
* Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
* clock gating.
*/
- intel_uncore_rmw(&dev_priv->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
}
-static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
+static void hsw_init_clock_gating(struct drm_i915_private *i915)
{
/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
- intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
+ intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
/* This is required by WaCatErrorRejectionIssue:hsw */
- intel_uncore_rmw(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+ intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
/* WaSwitchSolVfFArbitrationPriority:hsw */
- intel_uncore_rmw(&dev_priv->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
+ intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
- lpt_init_clock_gating(dev_priv);
+ lpt_init_clock_gating(i915);
}
-static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
+static void ivb_init_clock_gating(struct drm_i915_private *i915)
{
- intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
/* WaFbcAsynchFlipDisableFbcQueue:ivb */
- intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
+ intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
/* WaDisableBackToBackFlipFix:ivb */
- intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
- CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
- CHICKEN3_DGMG_DONE_FIX_DISABLE);
+ intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
+ CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
+ CHICKEN3_DGMG_DONE_FIX_DISABLE);
- if (IS_IVB_GT1(dev_priv))
- intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
- _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+ if (IS_IVB_GT1(i915))
+ intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
+ _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
else {
/* must write both registers */
- intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
- _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
- intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2_GT2,
- _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+ intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
+ _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+ intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2_GT2,
+ _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
}
/*
* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
* This implements the WaDisableRCZUnitClockGating:ivb workaround.
*/
- intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
- GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_write(&i915->uncore, GEN6_UCGCTL2,
+ GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
/* This is required by WaCatErrorRejectionIssue:ivb */
- intel_uncore_rmw(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+ intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
- g4x_disable_trickle_feed(dev_priv);
+ g4x_disable_trickle_feed(i915);
- intel_uncore_rmw(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
+ intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
GEN6_MBC_SNPCR_MED);
- if (!HAS_PCH_NOP(dev_priv))
- cpt_init_clock_gating(dev_priv);
+ if (!HAS_PCH_NOP(i915))
+ cpt_init_clock_gating(i915);
- gen6_check_mch_setup(dev_priv);
+ gen6_check_mch_setup(i915);
}
-static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
+static void vlv_init_clock_gating(struct drm_i915_private *i915)
{
/* WaDisableBackToBackFlipFix:vlv */
- intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
- CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
- CHICKEN3_DGMG_DONE_FIX_DISABLE);
+ intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
+ CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
+ CHICKEN3_DGMG_DONE_FIX_DISABLE);
/* WaDisableDopClockGating:vlv */
- intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
- _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
+ intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
+ _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
/* This is required by WaCatErrorRejectionIssue:vlv */
- intel_uncore_rmw(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+ intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
/*
* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
* This implements the WaDisableRCZUnitClockGating:vlv workaround.
*/
- intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
- GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_write(&i915->uncore, GEN6_UCGCTL2,
+ GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
/* WaDisableL3Bank2xClockGate:vlv
* Disabling L3 clock gating- MMIO 940c[25] = 1
* Set bit 25, to disable L3_BANK_2x_CLK_GATING */
- intel_uncore_rmw(&dev_priv->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
+ intel_uncore_rmw(&i915->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
/*
* WaDisableVLVClockGating_VBIIssue:vlv
* Disable clock gating on th GCFG unit to prevent a delay
* in the reporting of vblank events.
*/
- intel_uncore_write(&dev_priv->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
+ intel_uncore_write(&i915->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
}
-static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
+static void chv_init_clock_gating(struct drm_i915_private *i915)
{
/* WaVSRefCountFullforceMissDisable:chv */
/* WaDSRefCountFullforceMissDisable:chv */
- intel_uncore_rmw(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
+ intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE,
GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0);
/* WaDisableSemaphoreAndSyncFlipWait:chv */
- intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
- _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
+ intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
+ _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
/* WaDisableCSUnitClockGating:chv */
- intel_uncore_rmw(&dev_priv->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
/* WaDisableSDEUnitClockGating:chv */
- intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
/*
* WaProgramL3SqcReg1Default:chv
* See gfxspecs/Related Documents/Performance Guide/
* LSQC Setting Recommendations.
*/
- gen8_set_l3sqc_credits(dev_priv, 38, 2);
+ gen8_set_l3sqc_credits(i915, 38, 2);
}
-static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
+static void g4x_init_clock_gating(struct drm_i915_private *i915)
{
u32 dspclk_gate;
- intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, 0);
- intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
- GS_UNIT_CLOCK_GATE_DISABLE |
- CL_UNIT_CLOCK_GATE_DISABLE);
- intel_uncore_write(&dev_priv->uncore, RAMCLK_GATE_D, 0);
+ intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0);
+ intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
+ GS_UNIT_CLOCK_GATE_DISABLE |
+ CL_UNIT_CLOCK_GATE_DISABLE);
+ intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0);
dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
OVRUNIT_CLOCK_GATE_DISABLE |
OVCUNIT_CLOCK_GATE_DISABLE;
- if (IS_GM45(dev_priv))
+ if (IS_GM45(i915))
dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
- intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D(dev_priv), dspclk_gate);
+ intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate);
- g4x_disable_trickle_feed(dev_priv);
+ g4x_disable_trickle_feed(i915);
}
-static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
+static void i965gm_init_clock_gating(struct drm_i915_private *i915)
{
- struct intel_uncore *uncore = &dev_priv->uncore;
+ struct intel_uncore *uncore = &i915->uncore;
intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
- intel_uncore_write(uncore, DSPCLK_GATE_D(dev_priv), 0);
+ intel_uncore_write(uncore, DSPCLK_GATE_D(i915), 0);
intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
intel_uncore_write16(uncore, DEUC, 0);
intel_uncore_write(uncore,
@@ -707,54 +709,55 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
_MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
}
-static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
+static void i965g_init_clock_gating(struct drm_i915_private *i915)
{
- intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
- I965_RCC_CLOCK_GATE_DISABLE |
- I965_RCPB_CLOCK_GATE_DISABLE |
- I965_ISC_CLOCK_GATE_DISABLE |
- I965_FBC_CLOCK_GATE_DISABLE);
- intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, 0);
- intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
- _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
+ intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
+ I965_RCC_CLOCK_GATE_DISABLE |
+ I965_RCPB_CLOCK_GATE_DISABLE |
+ I965_ISC_CLOCK_GATE_DISABLE |
+ I965_FBC_CLOCK_GATE_DISABLE);
+ intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, 0);
+ intel_uncore_write(&i915->uncore, MI_ARB_STATE,
+ _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
}
-static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
+static void gen3_init_clock_gating(struct drm_i915_private *i915)
{
- u32 dstate = intel_uncore_read(&dev_priv->uncore, D_STATE);
+ u32 dstate = intel_uncore_read(&i915->uncore, D_STATE);
dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
DSTATE_DOT_CLOCK_GATING;
- intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
+ intel_uncore_write(&i915->uncore, D_STATE, dstate);
- if (IS_PINEVIEW(dev_priv))
- intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
+ if (IS_PINEVIEW(i915))
+ intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE),
_MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
/* IIR "flip pending" means done if this bit is set */
- intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
+ intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE),
_MASKED_BIT_DISABLE(ECO_FLIP_DONE));
/* interrupts should cause a wake up from C3 */
- intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
+ intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
/* On GEN3 we really need to make sure the ARB C3 LP bit is set */
- intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
+ intel_uncore_write(&i915->uncore, MI_ARB_STATE,
+ _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
- intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
- _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
+ intel_uncore_write(&i915->uncore, MI_ARB_STATE,
+ _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
}
-static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
+static void i85x_init_clock_gating(struct drm_i915_private *i915)
{
- intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
+ intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
/* interrupts should cause a wake up from C3 */
- intel_uncore_write(&dev_priv->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
- _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
+ intel_uncore_write(&i915->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
+ _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
- intel_uncore_write(&dev_priv->uncore, MEM_MODE,
- _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
+ intel_uncore_write(&i915->uncore, MEM_MODE,
+ _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
/*
* Have FBC ignore 3D activity since we use software
@@ -763,25 +766,25 @@ static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
* abosultely nothing) would not allow FBC to recompress
* until a 2D blit occurs.
*/
- intel_uncore_write(&dev_priv->uncore, SCPD0,
- _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
+ intel_uncore_write(&i915->uncore, SCPD0,
+ _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
}
-static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
+static void i830_init_clock_gating(struct drm_i915_private *i915)
{
- intel_uncore_write(&dev_priv->uncore, MEM_MODE,
- _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
- _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
+ intel_uncore_write(&i915->uncore, MEM_MODE,
+ _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
+ _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
}
-void intel_clock_gating_init(struct drm_i915_private *dev_priv)
+void intel_clock_gating_init(struct drm_i915_private *i915)
{
- dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
+ i915->clock_gating_funcs->init_clock_gating(i915);
}
-static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
+static void nop_init_clock_gating(struct drm_i915_private *i915)
{
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(&i915->drm,
"No clock gating settings or workarounds applied.\n");
}
@@ -819,67 +822,67 @@ CG_FUNCS(nop);
/**
* intel_clock_gating_hooks_init - setup the clock gating hooks
- * @dev_priv: device private
+ * @i915: device private
*
* Setup the hooks that configure which clocks of a given platform can be
* gated and also apply various GT and display specific workarounds for these
* platforms. Note that some GT specific workarounds are applied separately
* when GPU contexts or batchbuffers start their execution.
*/
-void intel_clock_gating_hooks_init(struct drm_i915_private *dev_priv)
-{
- if (IS_METEORLAKE(dev_priv))
- dev_priv->clock_gating_funcs = &nop_clock_gating_funcs;
- else if (IS_PONTEVECCHIO(dev_priv))
- dev_priv->clock_gating_funcs = &pvc_clock_gating_funcs;
- else if (IS_DG2(dev_priv))
- dev_priv->clock_gating_funcs = &dg2_clock_gating_funcs;
- else if (IS_XEHPSDV(dev_priv))
- dev_priv->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
- else if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs;
- else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs;
- else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->clock_gating_funcs = &icl_clock_gating_funcs;
- else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->clock_gating_funcs = &cfl_clock_gating_funcs;
- else if (IS_SKYLAKE(dev_priv))
- dev_priv->clock_gating_funcs = &skl_clock_gating_funcs;
- else if (IS_KABYLAKE(dev_priv))
- dev_priv->clock_gating_funcs = &kbl_clock_gating_funcs;
- else if (IS_BROXTON(dev_priv))
- dev_priv->clock_gating_funcs = &bxt_clock_gating_funcs;
- else if (IS_GEMINILAKE(dev_priv))
- dev_priv->clock_gating_funcs = &glk_clock_gating_funcs;
- else if (IS_BROADWELL(dev_priv))
- dev_priv->clock_gating_funcs = &bdw_clock_gating_funcs;
- else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->clock_gating_funcs = &chv_clock_gating_funcs;
- else if (IS_HASWELL(dev_priv))
- dev_priv->clock_gating_funcs = &hsw_clock_gating_funcs;
- else if (IS_IVYBRIDGE(dev_priv))
- dev_priv->clock_gating_funcs = &ivb_clock_gating_funcs;
- else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->clock_gating_funcs = &vlv_clock_gating_funcs;
- else if (GRAPHICS_VER(dev_priv) == 6)
- dev_priv->clock_gating_funcs = &gen6_clock_gating_funcs;
- else if (GRAPHICS_VER(dev_priv) == 5)
- dev_priv->clock_gating_funcs = &ilk_clock_gating_funcs;
- else if (IS_G4X(dev_priv))
- dev_priv->clock_gating_funcs = &g4x_clock_gating_funcs;
- else if (IS_I965GM(dev_priv))
- dev_priv->clock_gating_funcs = &i965gm_clock_gating_funcs;
- else if (IS_I965G(dev_priv))
- dev_priv->clock_gating_funcs = &i965g_clock_gating_funcs;
- else if (GRAPHICS_VER(dev_priv) == 3)
- dev_priv->clock_gating_funcs = &gen3_clock_gating_funcs;
- else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
- dev_priv->clock_gating_funcs = &i85x_clock_gating_funcs;
- else if (GRAPHICS_VER(dev_priv) == 2)
- dev_priv->clock_gating_funcs = &i830_clock_gating_funcs;
+void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
+{
+ if (IS_METEORLAKE(i915))
+ i915->clock_gating_funcs = &nop_clock_gating_funcs;
+ else if (IS_PONTEVECCHIO(i915))
+ i915->clock_gating_funcs = &pvc_clock_gating_funcs;
+ else if (IS_DG2(i915))
+ i915->clock_gating_funcs = &dg2_clock_gating_funcs;
+ else if (IS_XEHPSDV(i915))
+ i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
+ else if (IS_ALDERLAKE_P(i915))
+ i915->clock_gating_funcs = &adlp_clock_gating_funcs;
+ else if (GRAPHICS_VER(i915) == 12)
+ i915->clock_gating_funcs = &gen12lp_clock_gating_funcs;
+ else if (GRAPHICS_VER(i915) == 11)
+ i915->clock_gating_funcs = &icl_clock_gating_funcs;
+ else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
+ i915->clock_gating_funcs = &cfl_clock_gating_funcs;
+ else if (IS_SKYLAKE(i915))
+ i915->clock_gating_funcs = &skl_clock_gating_funcs;
+ else if (IS_KABYLAKE(i915))
+ i915->clock_gating_funcs = &kbl_clock_gating_funcs;
+ else if (IS_BROXTON(i915))
+ i915->clock_gating_funcs = &bxt_clock_gating_funcs;
+ else if (IS_GEMINILAKE(i915))
+ i915->clock_gating_funcs = &glk_clock_gating_funcs;
+ else if (IS_BROADWELL(i915))
+ i915->clock_gating_funcs = &bdw_clock_gating_funcs;
+ else if (IS_CHERRYVIEW(i915))
+ i915->clock_gating_funcs = &chv_clock_gating_funcs;
+ else if (IS_HASWELL(i915))
+ i915->clock_gating_funcs = &hsw_clock_gating_funcs;
+ else if (IS_IVYBRIDGE(i915))
+ i915->clock_gating_funcs = &ivb_clock_gating_funcs;
+ else if (IS_VALLEYVIEW(i915))
+ i915->clock_gating_funcs = &vlv_clock_gating_funcs;
+ else if (GRAPHICS_VER(i915) == 6)
+ i915->clock_gating_funcs = &gen6_clock_gating_funcs;
+ else if (GRAPHICS_VER(i915) == 5)
+ i915->clock_gating_funcs = &ilk_clock_gating_funcs;
+ else if (IS_G4X(i915))
+ i915->clock_gating_funcs = &g4x_clock_gating_funcs;
+ else if (IS_I965GM(i915))
+ i915->clock_gating_funcs = &i965gm_clock_gating_funcs;
+ else if (IS_I965G(i915))
+ i915->clock_gating_funcs = &i965g_clock_gating_funcs;
+ else if (GRAPHICS_VER(i915) == 3)
+ i915->clock_gating_funcs = &gen3_clock_gating_funcs;
+ else if (IS_I85X(i915) || IS_I865G(i915))
+ i915->clock_gating_funcs = &i85x_clock_gating_funcs;
+ else if (GRAPHICS_VER(i915) == 2)
+ i915->clock_gating_funcs = &i830_clock_gating_funcs;
else {
- MISSING_CASE(INTEL_DEVID(dev_priv));
- dev_priv->clock_gating_funcs = &nop_clock_gating_funcs;
+ MISSING_CASE(INTEL_DEVID(i915));
+ i915->clock_gating_funcs = &nop_clock_gating_funcs;
}
}
--
2.39.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: pm cleanups, rename to clock gating
2023-03-01 13:54 [Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating Jani Nikula
` (5 preceding siblings ...)
2023-03-01 13:54 ` [Intel-gfx] [PATCH 6/6] drm/i915/clock: mass rename dev_priv to i915 Jani Nikula
@ 2023-03-01 20:39 ` Patchwork
2023-03-01 21:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-04 9:43 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-03-01 20:39 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: pm cleanups, rename to clock gating
URL : https://patchwork.freedesktop.org/series/114519/
State : warning
== Summary ==
Error: dim checkpatch failed
b692b7687640 drm/i915/wm: remove display/ prefix from include
3c139b502a1f drm/i915/pm: drop intel_pm_setup()
107a5af9ab14 drm/i915/pm: drop intel_suspend_hw()
b19705e1c09f drm/i915: remove unnecessary intel_pm.h includes
f361dedf95d4 drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch]
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:147: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#147:
rename from drivers/gpu/drm/i915/intel_pm.c
total: 0 errors, 1 warnings, 0 checks, 168 lines checked
66cba8ee1b7c drm/i915/clock: mass rename dev_priv to i915
-:1032: CHECK:BRACES: braces {} should be used on all arms of this statement
#1032: FILE: drivers/gpu/drm/i915/intel_clock_gating.c:834:
+ if (IS_METEORLAKE(i915))
[...]
+ else if (IS_PONTEVECCHIO(i915))
[...]
+ else if (IS_DG2(i915))
[...]
+ else if (IS_XEHPSDV(i915))
[...]
+ else if (IS_ALDERLAKE_P(i915))
[...]
+ else if (GRAPHICS_VER(i915) == 12)
[...]
+ else if (GRAPHICS_VER(i915) == 11)
[...]
+ else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
[...]
+ else if (IS_SKYLAKE(i915))
[...]
+ else if (IS_KABYLAKE(i915))
[...]
+ else if (IS_BROXTON(i915))
[...]
+ else if (IS_GEMINILAKE(i915))
[...]
+ else if (IS_BROADWELL(i915))
[...]
+ else if (IS_CHERRYVIEW(i915))
[...]
+ else if (IS_HASWELL(i915))
[...]
+ else if (IS_IVYBRIDGE(i915))
[...]
+ else if (IS_VALLEYVIEW(i915))
[...]
+ else if (GRAPHICS_VER(i915) == 6)
[...]
+ else if (GRAPHICS_VER(i915) == 5)
[...]
+ else if (IS_G4X(i915))
[...]
+ else if (IS_I965GM(i915))
[...]
+ else if (IS_I965G(i915))
[...]
+ else if (GRAPHICS_VER(i915) == 3)
[...]
+ else if (IS_I85X(i915) || IS_I865G(i915))
[...]
+ else if (GRAPHICS_VER(i915) == 2)
[...]
else {
[...]
total: 0 errors, 0 warnings, 1 checks, 1056 lines checked
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: pm cleanups, rename to clock gating
2023-03-01 13:54 [Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating Jani Nikula
` (6 preceding siblings ...)
2023-03-01 20:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: pm cleanups, rename to clock gating Patchwork
@ 2023-03-01 21:02 ` Patchwork
2023-03-04 9:43 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-03-01 21:02 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5849 bytes --]
== Series Details ==
Series: drm/i915: pm cleanups, rename to clock gating
URL : https://patchwork.freedesktop.org/series/114519/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799 -> Patchwork_114519v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/index.html
Participating hosts (40 -> 40)
------------------------------
Additional (1): fi-kbl-soraka
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_114519v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3@smem:
- bat-rpls-1: NOTRUN -> [ABORT][1] ([i915#6687] / [i915#7978])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_selftest@live@execlists:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][4] ([i915#7156] / [i915#7913])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-kbl-soraka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][5] -> [DMESG-FAIL][6] ([i915#5334])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#1886])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-skl-guc: [PASS][8] -> [DMESG-WARN][9] ([i915#8073])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271]) +16 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
#### Possible fixes ####
* igt@i915_selftest@live@migrate:
- bat-atsm-1: [DMESG-FAIL][11] ([i915#7699]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-atsm-1/igt@i915_selftest@live@migrate.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/bat-atsm-1/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@reset:
- bat-rpls-1: [ABORT][13] ([i915#4983]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-1/igt@i915_selftest@live@reset.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/bat-rpls-1/igt@i915_selftest@live@reset.html
#### Warnings ####
* igt@i915_selftest@live@slpc:
- bat-rpls-2: [DMESG-FAIL][15] ([i915#6997] / [i915#7913]) -> [DMESG-FAIL][16] ([i915#6367] / [i915#7913] / [i915#7996])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/bat-rpls-2/igt@i915_selftest@live@slpc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/bat-rpls-2/igt@i915_selftest@live@slpc.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7156]: https://gitlab.freedesktop.org/drm/intel/issues/7156
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
[i915#8073]: https://gitlab.freedesktop.org/drm/intel/issues/8073
Build changes
-------------
* Linux: CI_DRM_12799 -> Patchwork_114519v1
CI-20190529: 20190529
CI_DRM_12799: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7178: ffe3f6670b91ab975f90799ab3fd0941b6eae019 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114519v1: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
7e62d54f42ea drm/i915/clock: mass rename dev_priv to i915
a574ab6194da drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch]
c8a8b3a88810 drm/i915: remove unnecessary intel_pm.h includes
e6dd2e34b688 drm/i915/pm: drop intel_suspend_hw()
fadbe620aa04 drm/i915/pm: drop intel_pm_setup()
98b2bde436b2 drm/i915/wm: remove display/ prefix from include
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/index.html
[-- Attachment #2: Type: text/html, Size: 7007 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 1/6] drm/i915/wm: remove display/ prefix from include
2023-03-01 13:54 ` [Intel-gfx] [PATCH 1/6] drm/i915/wm: remove display/ prefix from include Jani Nikula
@ 2023-03-02 18:10 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2023-03-02 18:10 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Mar 01, 2023 at 03:54:15PM +0200, Jani Nikula wrote:
> Remove the leftover from moving and renaming the file from driver top
> level.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_wm_types.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_wm_types.h b/drivers/gpu/drm/i915/display/intel_wm_types.h
> index bac2b6fdc5d0..628b7c0ce484 100644
> --- a/drivers/gpu/drm/i915/display/intel_wm_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_wm_types.h
> @@ -8,7 +8,7 @@
>
> #include <linux/types.h>
>
> -#include "display/intel_display_limits.h"
> +#include "intel_display_limits.h"
>
> enum intel_ddb_partitioning {
> INTEL_DDB_PART_1_2,
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 2/6] drm/i915/pm: drop intel_pm_setup()
2023-03-01 13:54 ` [Intel-gfx] [PATCH 2/6] drm/i915/pm: drop intel_pm_setup() Jani Nikula
@ 2023-03-02 18:11 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2023-03-02 18:11 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Mar 01, 2023 at 03:54:16PM +0200, Jani Nikula wrote:
> All the init in intel_pm_setup() is related to runtime pm. Move them to
> intel_runtime_pm_init_early(), and remove intel_pm_setup().
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_driver.c | 1 -
> drivers/gpu/drm/i915/intel_pm.c | 6 ------
> drivers/gpu/drm/i915/intel_pm.h | 1 -
> drivers/gpu/drm/i915/intel_runtime_pm.c | 2 ++
> 4 files changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 8bc76dede332..171ff4edabd6 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -250,7 +250,6 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
> /* This must be called before any calls to HAS_PCH_* */
> intel_detect_pch(dev_priv);
>
> - intel_pm_setup(dev_priv);
> intel_irq_init(dev_priv);
> intel_init_display_hooks(dev_priv);
> intel_init_clock_gating_hooks(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ddf004e5bb4b..8b02af531e82 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -899,9 +899,3 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> dev_priv->clock_gating_funcs = &nop_clock_gating_funcs;
> }
> }
> -
> -void intel_pm_setup(struct drm_i915_private *dev_priv)
> -{
> - dev_priv->runtime_pm.suspended = false;
> - atomic_set(&dev_priv->runtime_pm.wakeref_count, 0);
> -}
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index eab60df0c6bb..1dd464d2d186 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -15,6 +15,5 @@ struct intel_plane_state;
> void intel_init_clock_gating(struct drm_i915_private *dev_priv);
> void intel_suspend_hw(struct drm_i915_private *dev_priv);
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
> -void intel_pm_setup(struct drm_i915_private *dev_priv);
>
> #endif /* __INTEL_PM_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 129746713d07..cf5122299b6b 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -652,6 +652,8 @@ void intel_runtime_pm_init_early(struct intel_runtime_pm *rpm)
>
> rpm->kdev = kdev;
> rpm->available = HAS_RUNTIME_PM(i915);
> + rpm->suspended = false;
> + atomic_set(&rpm->wakeref_count, 0);
>
> init_intel_runtime_pm_wakeref(rpm);
> INIT_LIST_HEAD(&rpm->lmem_userfault_list);
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 3/6] drm/i915/pm: drop intel_suspend_hw()
2023-03-01 13:54 ` [Intel-gfx] [PATCH 3/6] drm/i915/pm: drop intel_suspend_hw() Jani Nikula
@ 2023-03-02 18:36 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2023-03-02 18:36 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Mar 01, 2023 at 03:54:17PM +0200, Jani Nikula wrote:
> All intel_suspend_hw() does is clear PCH_LP_PARTITION_LEVEL_DISABLE bit
> in SOUTH_DSPCLK_GATE_D for LPT LP. intel_suspend_hw() gets called from
> i915_drm_suspend().
>
> However, i915_drm_suspend_late() calls
> intel_display_power_suspend_late(), which in turn calls hsw_enable_pc8()
> on HSW and BDW. The first thing that does is clear
> PCH_LP_PARTITION_LEVEL_DISABLE bit in SOUTH_DSPCLK_GATE_D.
For a moment I thought that the if HSW || BDW on the other call would
make some difference, but then I confirmed on intel_pch.c that only
HSW and BDW has PCH_LPT anyway. So,
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Remove the duplicated clearing of the bit, effectively delaying it from
> i915_drm_suspend() to i915_drm_suspend_late(), and remove the
> unnecessary intel_suspend_hw() function altogether.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_driver.c | 2 --
> drivers/gpu/drm/i915/intel_pm.c | 16 ----------------
> drivers/gpu/drm/i915/intel_pm.h | 1 -
> 3 files changed, 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 171ff4edabd6..a53fd339e2cc 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -1079,8 +1079,6 @@ static int i915_drm_suspend(struct drm_device *dev)
>
> intel_suspend_encoders(dev_priv);
>
> - intel_suspend_hw(dev_priv);
> -
> /* Must be called before GGTT is suspended. */
> intel_dpt_suspend(dev_priv);
> i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 8b02af531e82..c45af0d981fd 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -320,16 +320,6 @@ static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
> 0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> }
>
> -static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
> -{
> - if (HAS_PCH_LPT_LP(dev_priv)) {
> - u32 val = intel_uncore_read(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D);
> -
> - val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> - intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, val);
> - }
> -}
> -
> static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> int general_prio_credits,
> int high_prio_credits)
> @@ -789,12 +779,6 @@ void intel_init_clock_gating(struct drm_i915_private *dev_priv)
> dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
> }
>
> -void intel_suspend_hw(struct drm_i915_private *dev_priv)
> -{
> - if (HAS_PCH_LPT(dev_priv))
> - lpt_suspend_hw(dev_priv);
> -}
> -
> static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index 1dd464d2d186..f774bddcdca6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -13,7 +13,6 @@ struct intel_crtc_state;
> struct intel_plane_state;
>
> void intel_init_clock_gating(struct drm_i915_private *dev_priv);
> -void intel_suspend_hw(struct drm_i915_private *dev_priv);
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
>
> #endif /* __INTEL_PM_H__ */
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 4/6] drm/i915: remove unnecessary intel_pm.h includes
2023-03-01 13:54 ` [Intel-gfx] [PATCH 4/6] drm/i915: remove unnecessary intel_pm.h includes Jani Nikula
@ 2023-03-02 18:37 ` Rodrigo Vivi
2023-03-06 17:47 ` Jani Nikula
0 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Vivi @ 2023-03-02 18:37 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Mar 01, 2023 at 03:54:18PM +0200, Jani Nikula wrote:
> As intel_pm.[ch] used to contain much more, intel_pm.h was included in a
> lot of places. Many of them are now unnecessary. Remove.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
trusting the compiler:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 1 -
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
> drivers/gpu/drm/i915/display/intel_modeset_setup.c | 1 -
> drivers/gpu/drm/i915/display/skl_watermark.c | 1 -
> drivers/gpu/drm/i915/gt/intel_gt.c | 1 -
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 -
> drivers/gpu/drm/i915/gt/selftest_llc.c | 1 -
> drivers/gpu/drm/i915/i915_debugfs.c | 1 -
> drivers/gpu/drm/i915/i915_irq.c | 1 -
> drivers/gpu/drm/i915/i915_pmu.c | 1 -
> drivers/gpu/drm/i915/i915_request.c | 1 -
> drivers/gpu/drm/i915/i915_sysfs.c | 1 -
> drivers/gpu/drm/i915/intel_uncore.c | 1 -
> 13 files changed, 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 3d4687efe4dd..caef72d38798 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -9,7 +9,6 @@
> #include "intel_display.h"
> #include "intel_display_trace.h"
> #include "intel_mchbar_regs.h"
> -#include "intel_pm.h"
> #include "intel_wm.h"
> #include "skl_watermark.h"
> #include "vlv_sideband.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 25013f303c82..1e654ddd0815 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -26,7 +26,6 @@
> #include "intel_hdmi.h"
> #include "intel_hotplug.h"
> #include "intel_panel.h"
> -#include "intel_pm.h"
> #include "intel_psr.h"
> #include "intel_sprite.h"
> #include "intel_wm.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index 60f71e6f0491..7ff083ec2d1d 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -25,7 +25,6 @@
> #include "intel_fifo_underrun.h"
> #include "intel_modeset_setup.h"
> #include "intel_pch_display.h"
> -#include "intel_pm.h"
> #include "intel_wm.h"
> #include "skl_watermark.h"
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 1300965d328a..f0af997d2a23 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -18,7 +18,6 @@
> #include "intel_display_types.h"
> #include "intel_fb.h"
> #include "intel_pcode.h"
> -#include "intel_pm.h"
> #include "intel_wm.h"
> #include "skl_watermark.h"
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index f7f271708fc7..6ca944d01eb6 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -28,7 +28,6 @@
> #include "intel_migrate.h"
> #include "intel_mocs.h"
> #include "intel_pci_config.h"
> -#include "intel_pm.h"
> #include "intel_rc6.h"
> #include "intel_renderstate.h"
> #include "intel_rps.h"
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index cef3d6f5c34e..85ae7dc079f2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -17,7 +17,6 @@
> #include "intel_gt_print.h"
> #include "intel_gt_requests.h"
> #include "intel_llc.h"
> -#include "intel_pm.h"
> #include "intel_rc6.h"
> #include "intel_rps.h"
> #include "intel_wakeref.h"
> diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
> index cfd736d88939..779fadcec7c4 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_llc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
> @@ -3,7 +3,6 @@
> * Copyright © 2019 Intel Corporation
> */
>
> -#include "intel_pm.h" /* intel_gpu_freq() */
> #include "selftest_llc.h"
> #include "intel_rps.h"
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 45773ce1deac..16011c0286ad 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -52,7 +52,6 @@
> #include "i915_irq.h"
> #include "i915_scheduler.h"
> #include "intel_mchbar_regs.h"
> -#include "intel_pm.h"
>
> static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
> {
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 417c981e4968..6ce3c934d832 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -52,7 +52,6 @@
> #include "i915_driver.h"
> #include "i915_drv.h"
> #include "i915_irq.h"
> -#include "intel_pm.h"
>
> /**
> * DOC: interrupt handling
> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
> index 52531ab28c5f..a76c5ce9513d 100644
> --- a/drivers/gpu/drm/i915/i915_pmu.c
> +++ b/drivers/gpu/drm/i915/i915_pmu.c
> @@ -17,7 +17,6 @@
>
> #include "i915_drv.h"
> #include "i915_pmu.h"
> -#include "intel_pm.h"
>
> /* Frequency for the sampling timer for events which need it. */
> #define FREQUENCY 200
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index 7503dcb9043b..630a732aaecc 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -48,7 +48,6 @@
> #include "i915_driver.h"
> #include "i915_drv.h"
> #include "i915_trace.h"
> -#include "intel_pm.h"
>
> struct execute_cb {
> struct irq_work work;
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 595e8b574990..e88bb4f04305 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -37,7 +37,6 @@
>
> #include "i915_drv.h"
> #include "i915_sysfs.h"
> -#include "intel_pm.h"
>
> struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
> {
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index f018da7ebaac..f4b3b2063018 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -32,7 +32,6 @@
> #include "i915_reg.h"
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> -#include "intel_pm.h"
>
> #define FORCEWAKE_ACK_TIMEOUT_MS 50
> #define GT_FIFO_TIMEOUT_MS 10
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 5/6] drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch]
2023-03-01 13:54 ` [Intel-gfx] [PATCH 5/6] drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch] Jani Nikula
@ 2023-03-02 18:39 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2023-03-02 18:39 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Mar 01, 2023 at 03:54:19PM +0200, Jani Nikula wrote:
> Observe that intel_pm.[ch] is now purely about clock gating, so rename
> them to intel_clock_gating.[ch]. Rename the functions to
> intel_clock_gating_*() to follow coding conventions.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/Makefile | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> drivers/gpu/drm/i915/i915_driver.c | 8 ++++----
> drivers/gpu/drm/i915/i915_gem.c | 8 ++++----
> .../i915/{intel_pm.c => intel_clock_gating.c} | 8 ++++----
> drivers/gpu/drm/i915/intel_clock_gating.h | 14 ++++++++++++++
> drivers/gpu/drm/i915/intel_pm.h | 18 ------------------
> drivers/gpu/drm/i915/vlv_suspend.c | 4 ++--
> 8 files changed, 31 insertions(+), 35 deletions(-)
> rename drivers/gpu/drm/i915/{intel_pm.c => intel_clock_gating.c} (99%)
> create mode 100644 drivers/gpu/drm/i915/intel_clock_gating.h
> delete mode 100644 drivers/gpu/drm/i915/intel_pm.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index b2f91a1f8268..b88df8c10781 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -47,10 +47,10 @@ i915-y += i915_driver.o \
> i915_switcheroo.o \
> i915_sysfs.o \
> i915_utils.o \
> + intel_clock_gating.o \
> intel_device_info.o \
> intel_memory_region.o \
> intel_pcode.o \
> - intel_pm.o \
> intel_region_ttm.o \
> intel_runtime_pm.o \
> intel_sbi.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a1fbdf32bd21..3f1b90a2f57c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -63,6 +63,7 @@
> #include "intel_audio.h"
> #include "intel_bw.h"
> #include "intel_cdclk.h"
> +#include "intel_clock_gating.h"
> #include "intel_color.h"
> #include "intel_crt.h"
> #include "intel_crtc.h"
> @@ -105,7 +106,6 @@
> #include "intel_pcode.h"
> #include "intel_pipe_crc.h"
> #include "intel_plane_initial.h"
> -#include "intel_pm.h"
> #include "intel_pps.h"
> #include "intel_psr.h"
> #include "intel_quirks.h"
> @@ -850,7 +850,7 @@ void intel_display_finish_reset(struct drm_i915_private *i915)
> */
> intel_pps_unlock_regs_wa(i915);
> intel_modeset_init_hw(i915);
> - intel_init_clock_gating(i915);
> + intel_clock_gating_init(i915);
> intel_hpd_init(i915);
>
> ret = __intel_display_resume(i915, state, ctx);
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index a53fd339e2cc..e4809485e47c 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -79,11 +79,11 @@
> #include "soc/intel_dram.h"
> #include "soc/intel_gmch.h"
>
> -#include "i915_file_private.h"
> #include "i915_debugfs.h"
> #include "i915_driver.h"
> #include "i915_drm_client.h"
> #include "i915_drv.h"
> +#include "i915_file_private.h"
> #include "i915_getparam.h"
> #include "i915_hwmon.h"
> #include "i915_ioc32.h"
> @@ -97,11 +97,11 @@
> #include "i915_sysfs.h"
> #include "i915_utils.h"
> #include "i915_vgpu.h"
> +#include "intel_clock_gating.h"
> #include "intel_gvt.h"
> #include "intel_memory_region.h"
> #include "intel_pci_config.h"
> #include "intel_pcode.h"
> -#include "intel_pm.h"
> #include "intel_region_ttm.h"
> #include "vlv_suspend.h"
>
> @@ -252,7 +252,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
>
> intel_irq_init(dev_priv);
> intel_init_display_hooks(dev_priv);
> - intel_init_clock_gating_hooks(dev_priv);
> + intel_clock_gating_hooks_init(dev_priv);
>
> intel_detect_preproduction_hw(dev_priv);
>
> @@ -1238,7 +1238,7 @@ static int i915_drm_resume(struct drm_device *dev)
> i915_gem_resume(dev_priv);
>
> intel_modeset_init_hw(dev_priv);
> - intel_init_clock_gating(dev_priv);
> + intel_clock_gating_init(dev_priv);
> intel_hpd_init(dev_priv);
>
> /* MST sideband requires HPD interrupts enabled */
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 35950fa91406..6b6b0e575ef3 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -58,7 +58,7 @@
> #include "i915_file_private.h"
> #include "i915_trace.h"
> #include "i915_vgpu.h"
> -#include "intel_pm.h"
> +#include "intel_clock_gating.h"
>
> static int
> insert_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node, u32 size)
> @@ -1164,7 +1164,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
> }
>
> /*
> - * Despite its name intel_init_clock_gating applies both display
> + * Despite its name intel_clock_gating_init applies both display
> * clock gating workarounds; GT mmio workarounds and the occasional
> * GT power context workaround. Worse, sometimes it includes a context
> * register workaround which we need to apply before we record the
> @@ -1172,7 +1172,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
> *
> * FIXME: break up the workarounds and apply them at the right time!
> */
> - intel_init_clock_gating(dev_priv);
> + intel_clock_gating_init(dev_priv);
>
> for_each_gt(gt, dev_priv, i) {
> ret = intel_gt_init(gt);
> @@ -1216,7 +1216,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
> /* Minimal basic recovery for KMS */
> ret = i915_ggtt_enable_hw(dev_priv);
> i915_ggtt_resume(to_gt(dev_priv)->ggtt);
> - intel_init_clock_gating(dev_priv);
> + intel_clock_gating_init(dev_priv);
> }
>
> i915_gem_drain_freed_objects(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> similarity index 99%
> rename from drivers/gpu/drm/i915/intel_pm.c
> rename to drivers/gpu/drm/i915/intel_clock_gating.c
> index c45af0d981fd..8cfc19b48760 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -36,8 +36,8 @@
> #include "gt/intel_gt_regs.h"
>
> #include "i915_drv.h"
> +#include "intel_clock_gating.h"
> #include "intel_mchbar_regs.h"
> -#include "intel_pm.h"
> #include "vlv_sideband.h"
>
> struct drm_i915_clock_gating_funcs {
> @@ -774,7 +774,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
> _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
> }
>
> -void intel_init_clock_gating(struct drm_i915_private *dev_priv)
> +void intel_clock_gating_init(struct drm_i915_private *dev_priv)
> {
> dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
> }
> @@ -818,7 +818,7 @@ CG_FUNCS(nop);
> #undef CG_FUNCS
>
> /**
> - * intel_init_clock_gating_hooks - setup the clock gating hooks
> + * intel_clock_gating_hooks_init - setup the clock gating hooks
> * @dev_priv: device private
> *
> * Setup the hooks that configure which clocks of a given platform can be
> @@ -826,7 +826,7 @@ CG_FUNCS(nop);
> * platforms. Note that some GT specific workarounds are applied separately
> * when GPU contexts or batchbuffers start their execution.
> */
> -void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> +void intel_clock_gating_hooks_init(struct drm_i915_private *dev_priv)
> {
> if (IS_METEORLAKE(dev_priv))
> dev_priv->clock_gating_funcs = &nop_clock_gating_funcs;
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.h b/drivers/gpu/drm/i915/intel_clock_gating.h
> new file mode 100644
> index 000000000000..5b4e4c55b2c2
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2019 Intel Corporation
> + */
> +
> +#ifndef __INTEL_CLOCK_GATING_H__
> +#define __INTEL_CLOCK_GATING_H__
> +
> +struct drm_i915_private;
> +
> +void intel_clock_gating_init(struct drm_i915_private *i915);
> +void intel_clock_gating_hooks_init(struct drm_i915_private *i915);
> +
> +#endif /* __INTEL_CLOCK_GATING_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> deleted file mode 100644
> index f774bddcdca6..000000000000
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -/* SPDX-License-Identifier: MIT */
> -/*
> - * Copyright © 2019 Intel Corporation
> - */
> -
> -#ifndef __INTEL_PM_H__
> -#define __INTEL_PM_H__
> -
> -#include <linux/types.h>
> -
> -struct drm_i915_private;
> -struct intel_crtc_state;
> -struct intel_plane_state;
> -
> -void intel_init_clock_gating(struct drm_i915_private *dev_priv);
> -void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
> -
> -#endif /* __INTEL_PM_H__ */
> diff --git a/drivers/gpu/drm/i915/vlv_suspend.c b/drivers/gpu/drm/i915/vlv_suspend.c
> index 02e63ed77f60..94595dde2b96 100644
> --- a/drivers/gpu/drm/i915/vlv_suspend.c
> +++ b/drivers/gpu/drm/i915/vlv_suspend.c
> @@ -12,7 +12,7 @@
> #include "i915_reg.h"
> #include "i915_trace.h"
> #include "i915_utils.h"
> -#include "intel_pm.h"
> +#include "intel_clock_gating.h"
> #include "vlv_suspend.h"
>
> #include "gt/intel_gt_regs.h"
> @@ -451,7 +451,7 @@ int vlv_resume_prepare(struct drm_i915_private *dev_priv, bool rpm_resume)
> vlv_check_no_gt_access(dev_priv);
>
> if (rpm_resume)
> - intel_init_clock_gating(dev_priv);
> + intel_clock_gating_init(dev_priv);
>
> return ret;
> }
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 6/6] drm/i915/clock: mass rename dev_priv to i915
2023-03-01 13:54 ` [Intel-gfx] [PATCH 6/6] drm/i915/clock: mass rename dev_priv to i915 Jani Nikula
@ 2023-03-02 18:40 ` Rodrigo Vivi
0 siblings, 0 replies; 17+ messages in thread
From: Rodrigo Vivi @ 2023-03-02 18:40 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Mar 01, 2023 at 03:54:20PM +0200, Jani Nikula wrote:
> Follow the contemporary naming style. Include some indentation fixes
> while at it on the affected statements.
>
> One function needs to keep using dev_priv due to implicit dev_priv usage
> in a macro.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_clock_gating.c | 589 +++++++++++-----------
> 1 file changed, 296 insertions(+), 293 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 8cfc19b48760..2c5302bcba19 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -44,9 +44,9 @@ struct drm_i915_clock_gating_funcs {
> void (*init_clock_gating)(struct drm_i915_private *i915);
> };
>
> -static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void gen9_init_clock_gating(struct drm_i915_private *i915)
> {
> - if (HAS_LLC(dev_priv)) {
> + if (HAS_LLC(i915)) {
> /*
> * WaCompressedResourceDisplayNewHashMode:skl,kbl
> * Display WA #0390: skl,kbl
> @@ -54,41 +54,42 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
> * Must match Sampler, Pixel Back End, and Media. See
> * WaCompressedResourceSamplerPbeMediaNewHashMode.
> */
> - intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
> + intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_DE_COMPRESSED_HASH_MODE);
> }
>
> /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> - intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
> + intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, SKL_EDP_PSR_FIX_RDWRAP);
>
> /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> - intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
> + intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1, 0, MASK_WAKEMEM);
>
> /*
> * WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl
> * Display WA #0859: skl,bxt,kbl,glk,cfl
> */
> - intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
> + intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_MEMORY_WAKE);
> }
>
> -static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void bxt_init_clock_gating(struct drm_i915_private *i915)
> {
> - gen9_init_clock_gating(dev_priv);
> + gen9_init_clock_gating(i915);
>
> /* WaDisableSDEUnitClockGating:bxt */
> - intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>
> /*
> * FIXME:
> * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
> */
> - intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
> + intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
>
> /*
> * Wa: Backlight PWM may stop in the asserted state, causing backlight
> * to stay fully on.
> */
> - intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
> - PWM1_GATING_DIS | PWM2_GATING_DIS);
> + intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
> + intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
> + PWM1_GATING_DIS | PWM2_GATING_DIS);
>
> /*
> * Lower the display internal timeout.
> @@ -96,42 +97,43 @@ static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
> * is off and a MMIO access is attempted by any privilege
> * application, using batch buffers or any other means.
> */
> - intel_uncore_write(&dev_priv->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
> + intel_uncore_write(&i915->uncore, RM_TIMEOUT, MMIO_TIMEOUT_US(950));
>
> /*
> * WaFbcTurnOffFbcWatermark:bxt
> * Display WA #0562: bxt
> */
> - intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
> + intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
>
> /*
> * WaFbcHighMemBwCorruptionAvoidance:bxt
> * Display WA #0883: bxt
> */
> - intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0);
> + intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0);
> }
>
> -static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void glk_init_clock_gating(struct drm_i915_private *i915)
> {
> - gen9_init_clock_gating(dev_priv);
> + gen9_init_clock_gating(i915);
>
> /*
> * WaDisablePWMClockGating:glk
> * Backlight PWM may stop in the asserted state, causing backlight
> * to stay fully on.
> */
> - intel_uncore_write(&dev_priv->uncore, GEN9_CLKGATE_DIS_0, intel_uncore_read(&dev_priv->uncore, GEN9_CLKGATE_DIS_0) |
> - PWM1_GATING_DIS | PWM2_GATING_DIS);
> + intel_uncore_write(&i915->uncore, GEN9_CLKGATE_DIS_0,
> + intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) |
> + PWM1_GATING_DIS | PWM2_GATING_DIS);
> }
>
> -static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void ibx_init_clock_gating(struct drm_i915_private *i915)
> {
> /*
> * On Ibex Peak and Cougar Point, we need to disable clock
> * gating for the panel power sequencer or it will fail to
> * start up when no ports are active.
> */
> - intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
> }
>
> static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> @@ -146,7 +148,7 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> }
> }
>
> -static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void ilk_init_clock_gating(struct drm_i915_private *i915)
> {
> u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>
> @@ -158,11 +160,11 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
>
> - intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS0,
> - MARIUNIT_CLOCK_GATE_DISABLE |
> - SVSMUNIT_CLOCK_GATE_DISABLE);
> - intel_uncore_write(&dev_priv->uncore, PCH_3DCGDIS1,
> - VFMUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_write(&i915->uncore, PCH_3DCGDIS0,
> + MARIUNIT_CLOCK_GATE_DISABLE |
> + SVSMUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_write(&i915->uncore, PCH_3DCGDIS1,
> + VFMUNIT_CLOCK_GATE_DISABLE);
>
> /*
> * According to the spec the following bits should be set in
> @@ -171,13 +173,13 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> * The bit 5 of 0x42020
> * The bit 15 of 0x45000
> */
> - intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> - (intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
> - ILK_DPARB_GATE | ILK_VSDPFD_FULL));
> + intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
> + (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
> + ILK_DPARB_GATE | ILK_VSDPFD_FULL));
> dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> - intel_uncore_write(&dev_priv->uncore, DISP_ARB_CTL,
> - (intel_uncore_read(&dev_priv->uncore, DISP_ARB_CTL) |
> - DISP_FBC_WM_DIS));
> + intel_uncore_write(&i915->uncore, DISP_ARB_CTL,
> + (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) |
> + DISP_FBC_WM_DIS));
>
> /*
> * Based on the document from hardware guys the following bits
> @@ -186,22 +188,22 @@ static void ilk_init_clock_gating(struct drm_i915_private *dev_priv)
> * The bit 22 of 0x42004
> * The bit 7,8,9 of 0x42020.
> */
> - if (IS_IRONLAKE_M(dev_priv)) {
> + if (IS_IRONLAKE_M(i915)) {
> /* WaFbcAsynchFlipDisableFbcQueue:ilk */
> - intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> - intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
> + intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> + intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_DPARB_GATE);
> }
>
> - intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> + intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
>
> - intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> + intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
>
> - g4x_disable_trickle_feed(dev_priv);
> + g4x_disable_trickle_feed(i915);
>
> - ibx_init_clock_gating(dev_priv);
> + ibx_init_clock_gating(i915);
> }
>
> -static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void cpt_init_clock_gating(struct drm_i915_private *i915)
> {
> enum pipe pipe;
> u32 val;
> @@ -211,53 +213,53 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
> * gating for the panel power sequencer or it will fail to
> * start up when no ports are active.
> */
> - intel_uncore_write(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
> - PCH_DPLUNIT_CLOCK_GATE_DISABLE |
> - PCH_CPUNIT_CLOCK_GATE_DISABLE);
> - intel_uncore_rmw(&dev_priv->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);
> + intel_uncore_write(&i915->uncore, SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
> + PCH_DPLUNIT_CLOCK_GATE_DISABLE |
> + PCH_CPUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_rmw(&i915->uncore, SOUTH_CHICKEN2, 0, DPLS_EDP_PPS_FIX_DIS);
> /* The below fixes the weird display corruption, a few pixels shifted
> * downward, on (only) LVDS of some HP laptops with IVY.
> */
> - for_each_pipe(dev_priv, pipe) {
> - val = intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN2(pipe));
> + for_each_pipe(i915, pipe) {
> + val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe));
> val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
> val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> - if (dev_priv->display.vbt.fdi_rx_polarity_inverted)
> + if (i915->display.vbt.fdi_rx_polarity_inverted)
> val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
> val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
> val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
> - intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN2(pipe), val);
> + intel_uncore_write(&i915->uncore, TRANS_CHICKEN2(pipe), val);
> }
> /* WADP0ClockGatingDisable */
> - for_each_pipe(dev_priv, pipe) {
> - intel_uncore_write(&dev_priv->uncore, TRANS_CHICKEN1(pipe),
> - TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> + for_each_pipe(i915, pipe) {
> + intel_uncore_write(&i915->uncore, TRANS_CHICKEN1(pipe),
> + TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> }
> }
>
> -static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
> +static void gen6_check_mch_setup(struct drm_i915_private *i915)
> {
> u32 tmp;
>
> - tmp = intel_uncore_read(&dev_priv->uncore, MCH_SSKPD);
> + tmp = intel_uncore_read(&i915->uncore, MCH_SSKPD);
> if (REG_FIELD_GET(SSKPD_WM0_MASK_SNB, tmp) != 12)
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(&i915->drm,
> "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
> tmp);
> }
>
> -static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void gen6_init_clock_gating(struct drm_i915_private *i915)
> {
> u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>
> - intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
> + intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, dspclk_gate);
>
> - intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
> + intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN2, 0, ILK_ELPIN_409_SELECT);
>
> - intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL1,
> - intel_uncore_read(&dev_priv->uncore, GEN6_UCGCTL1) |
> - GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
> - GEN6_CSUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_write(&i915->uncore, GEN6_UCGCTL1,
> + intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) |
> + GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
> + GEN6_CSUNIT_CLOCK_GATE_DISABLE);
>
> /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
> * gating disable must be set. Failure to set it results in
> @@ -272,9 +274,9 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> * WaDisableRCCUnitClockGating:snb
> * WaDisableRCPBUnitClockGating:snb
> */
> - intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
> - GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
> - GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_write(&i915->uncore, GEN6_UCGCTL2,
> + GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
> + GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
>
> /*
> * According to the spec the following bits should be
> @@ -287,40 +289,40 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
> *
> * WaFbcAsynchFlipDisableFbcQueue:snb
> */
> - intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1,
> - intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1) |
> - ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> - intel_uncore_write(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2,
> - intel_uncore_read(&dev_priv->uncore, ILK_DISPLAY_CHICKEN2) |
> - ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> - intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D,
> - intel_uncore_read(&dev_priv->uncore, ILK_DSPCLK_GATE_D) |
> - ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
> - ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
> + intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN1,
> + intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) |
> + ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
> + intel_uncore_write(&i915->uncore, ILK_DISPLAY_CHICKEN2,
> + intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) |
> + ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> + intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D,
> + intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) |
> + ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
> + ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
>
> - g4x_disable_trickle_feed(dev_priv);
> + g4x_disable_trickle_feed(i915);
>
> - cpt_init_clock_gating(dev_priv);
> + cpt_init_clock_gating(i915);
>
> - gen6_check_mch_setup(dev_priv);
> + gen6_check_mch_setup(i915);
> }
>
> -static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void lpt_init_clock_gating(struct drm_i915_private *i915)
> {
> /*
> * TODO: this bit should only be enabled when really needed, then
> * disabled when not needed anymore in order to save power.
> */
> - if (HAS_PCH_LPT_LP(dev_priv))
> - intel_uncore_rmw(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D,
> + if (HAS_PCH_LPT_LP(i915))
> + intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D,
> 0, PCH_LP_PARTITION_LEVEL_DISABLE);
>
> /* WADPOClockGatingDisable:hsw */
> - intel_uncore_rmw(&dev_priv->uncore, TRANS_CHICKEN1(PIPE_A),
> + intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A),
> 0, TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> }
>
> -static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> +static void gen8_set_l3sqc_credits(struct drm_i915_private *i915,
> int general_prio_credits,
> int high_prio_credits)
> {
> @@ -328,64 +330,64 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> u32 val;
>
> /* WaTempDisableDOPClkGating:bdw */
> - misccpctl = intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
> + misccpctl = intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
> GEN7_DOP_CLOCK_GATE_ENABLE, 0);
>
> - val = intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_L3SQCREG1);
> + val = intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1);
> val &= ~L3_PRIO_CREDITS_MASK;
> val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
> val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
> - intel_gt_mcr_multicast_write(to_gt(dev_priv), GEN8_L3SQCREG1, val);
> + intel_gt_mcr_multicast_write(to_gt(i915), GEN8_L3SQCREG1, val);
>
> /*
> * Wait at least 100 clocks before re-enabling clock gating.
> * See the definition of L3SQCREG1 in BSpec.
> */
> - intel_gt_mcr_read_any(to_gt(dev_priv), GEN8_L3SQCREG1);
> + intel_gt_mcr_read_any(to_gt(i915), GEN8_L3SQCREG1);
> udelay(1);
> - intel_uncore_write(&dev_priv->uncore, GEN7_MISCCPCTL, misccpctl);
> + intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl);
> }
>
> -static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void icl_init_clock_gating(struct drm_i915_private *i915)
> {
> /* Wa_1409120013:icl,ehl */
> - intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> + intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>
> /*Wa_14010594013:icl, ehl */
> - intel_uncore_rmw(&dev_priv->uncore, GEN8_CHICKEN_DCPR_1,
> + intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1,
> 0, ICL_DELAY_PMRSP);
> }
>
> -static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void gen12lp_init_clock_gating(struct drm_i915_private *i915)
> {
> /* Wa_1409120013 */
> - if (DISPLAY_VER(dev_priv) == 12)
> - intel_uncore_write(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> + if (DISPLAY_VER(i915) == 12)
> + intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> DPFC_CHICKEN_COMP_DUMMY_PIXEL);
>
> /* Wa_14013723622:tgl,rkl,dg1,adl-s */
> - if (DISPLAY_VER(dev_priv) == 12)
> - intel_uncore_rmw(&dev_priv->uncore, CLKREQ_POLICY,
> + if (DISPLAY_VER(i915) == 12)
> + intel_uncore_rmw(&i915->uncore, CLKREQ_POLICY,
> CLKREQ_POLICY_MEM_UP_OVRD, 0);
> }
>
> -static void adlp_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void adlp_init_clock_gating(struct drm_i915_private *i915)
> {
> - gen12lp_init_clock_gating(dev_priv);
> + gen12lp_init_clock_gating(i915);
>
> /* Wa_22011091694:adlp */
> - intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
> + intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
>
> /* Bspec/49189 Initialize Sequence */
> - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
> + intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
> }
>
> -static void xehpsdv_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void xehpsdv_init_clock_gating(struct drm_i915_private *i915)
> {
> /* Wa_22010146351:xehpsdv */
> - if (IS_XEHPSDV_GRAPHICS_STEP(dev_priv, STEP_A0, STEP_B0))
> - intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
> + if (IS_XEHPSDV_GRAPHICS_STEP(i915, STEP_A0, STEP_B0))
> + intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
> }
>
> static void dg2_init_clock_gating(struct drm_i915_private *i915)
> @@ -403,303 +405,303 @@ static void dg2_init_clock_gating(struct drm_i915_private *i915)
> SGR_DIS | SGGI_DIS);
> }
>
> -static void pvc_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void pvc_init_clock_gating(struct drm_i915_private *i915)
> {
> /* Wa_14012385139:pvc */
> - if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0))
> - intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
> + if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0))
> + intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGR_DIS);
>
> /* Wa_22010954014:pvc */
> - if (IS_PVC_BD_STEP(dev_priv, STEP_A0, STEP_B0))
> - intel_uncore_rmw(&dev_priv->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
> + if (IS_PVC_BD_STEP(i915, STEP_A0, STEP_B0))
> + intel_uncore_rmw(&i915->uncore, XEHP_CLOCK_GATE_DIS, 0, SGSI_SIDECLK_DIS);
> }
>
> -static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void cnp_init_clock_gating(struct drm_i915_private *i915)
> {
> - if (!HAS_PCH_CNP(dev_priv))
> + if (!HAS_PCH_CNP(i915))
> return;
>
> /* Display WA #1181 WaSouthDisplayDisablePWMCGEGating: cnp */
> - intel_uncore_rmw(&dev_priv->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE);
> + intel_uncore_rmw(&i915->uncore, SOUTH_DSPCLK_GATE_D, 0, CNP_PWM_CGE_GATING_DISABLE);
> }
>
> -static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void cfl_init_clock_gating(struct drm_i915_private *i915)
> {
> - cnp_init_clock_gating(dev_priv);
> - gen9_init_clock_gating(dev_priv);
> + cnp_init_clock_gating(i915);
> + gen9_init_clock_gating(i915);
>
> /* WAC6entrylatency:cfl */
> - intel_uncore_rmw(&dev_priv->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
> + intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
>
> /*
> * WaFbcTurnOffFbcWatermark:cfl
> * Display WA #0562: cfl
> */
> - intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
> + intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
>
> /*
> * WaFbcNukeOnHostModify:cfl
> * Display WA #0873: cfl
> */
> - intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> + intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> 0, DPFC_NUKE_ON_ANY_MODIFICATION);
> }
>
> -static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void kbl_init_clock_gating(struct drm_i915_private *i915)
> {
> - gen9_init_clock_gating(dev_priv);
> + gen9_init_clock_gating(i915);
>
> /* WAC6entrylatency:kbl */
> - intel_uncore_rmw(&dev_priv->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
> + intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
>
> /* WaDisableSDEUnitClockGating:kbl */
> - if (IS_KBL_GRAPHICS_STEP(dev_priv, 0, STEP_C0))
> - intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6,
> + if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
> + intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6,
> 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>
> /* WaDisableGamClockGating:kbl */
> - if (IS_KBL_GRAPHICS_STEP(dev_priv, 0, STEP_C0))
> - intel_uncore_rmw(&dev_priv->uncore, GEN6_UCGCTL1,
> + if (IS_KBL_GRAPHICS_STEP(i915, 0, STEP_C0))
> + intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1,
> 0, GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
>
> /*
> * WaFbcTurnOffFbcWatermark:kbl
> * Display WA #0562: kbl
> */
> - intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
> + intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
>
> /*
> * WaFbcNukeOnHostModify:kbl
> * Display WA #0873: kbl
> */
> - intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> + intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> 0, DPFC_NUKE_ON_ANY_MODIFICATION);
> }
>
> -static void skl_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void skl_init_clock_gating(struct drm_i915_private *i915)
> {
> - gen9_init_clock_gating(dev_priv);
> + gen9_init_clock_gating(i915);
>
> /* WaDisableDopClockGating:skl */
> - intel_uncore_rmw(&dev_priv->uncore, GEN7_MISCCPCTL,
> + intel_uncore_rmw(&i915->uncore, GEN7_MISCCPCTL,
> GEN7_DOP_CLOCK_GATE_ENABLE, 0);
>
> /* WAC6entrylatency:skl */
> - intel_uncore_rmw(&dev_priv->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
> + intel_uncore_rmw(&i915->uncore, FBC_LLC_READ_CTRL, 0, FBC_LLC_FULLY_OPEN);
>
> /*
> * WaFbcTurnOffFbcWatermark:skl
> * Display WA #0562: skl
> */
> - intel_uncore_rmw(&dev_priv->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
> + intel_uncore_rmw(&i915->uncore, DISP_ARB_CTL, 0, DISP_FBC_WM_DIS);
>
> /*
> * WaFbcNukeOnHostModify:skl
> * Display WA #0873: skl
> */
> - intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> + intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
> 0, DPFC_NUKE_ON_ANY_MODIFICATION);
>
> /*
> * WaFbcHighMemBwCorruptionAvoidance:skl
> * Display WA #0883: skl
> */
> - intel_uncore_rmw(&dev_priv->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0);
> + intel_uncore_rmw(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A), 0, DPFC_DISABLE_DUMMY0);
> }
>
> -static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void bdw_init_clock_gating(struct drm_i915_private *i915)
> {
> enum pipe pipe;
>
> /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> - intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
> + intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
>
> /* WaSwitchSolVfFArbitrationPriority:bdw */
> - intel_uncore_rmw(&dev_priv->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
> + intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
>
> /* WaPsrDPAMaskVBlankInSRD:bdw */
> - intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR1_1, 0, DPA_MASK_VBLANK_SRD);
> + intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, DPA_MASK_VBLANK_SRD);
>
> - for_each_pipe(dev_priv, pipe) {
> + for_each_pipe(i915, pipe) {
> /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
> - intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(pipe),
> + intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe),
> 0, BDW_DPRS_MASK_VBLANK_SRD);
> }
>
> /* WaVSRefCountFullforceMissDisable:bdw */
> /* WaDSRefCountFullforceMissDisable:bdw */
> - intel_uncore_rmw(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
> + intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE,
> GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0);
>
> - intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
> - _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> + intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
> + _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
>
> /* WaDisableSDEUnitClockGating:bdw */
> - intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>
> /* WaProgramL3SqcReg1Default:bdw */
> - gen8_set_l3sqc_credits(dev_priv, 30, 2);
> + gen8_set_l3sqc_credits(i915, 30, 2);
>
> /* WaKVMNotificationOnConfigChange:bdw */
> - intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PAR2_1,
> + intel_uncore_rmw(&i915->uncore, CHICKEN_PAR2_1,
> 0, KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
>
> - lpt_init_clock_gating(dev_priv);
> + lpt_init_clock_gating(i915);
>
> /* WaDisableDopClockGating:bdw
> *
> * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP
> * clock gating.
> */
> - intel_uncore_rmw(&dev_priv->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
> }
>
> -static void hsw_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void hsw_init_clock_gating(struct drm_i915_private *i915)
> {
> /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
> - intel_uncore_rmw(&dev_priv->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
> + intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS);
>
> /* This is required by WaCatErrorRejectionIssue:hsw */
> - intel_uncore_rmw(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> + intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> /* WaSwitchSolVfFArbitrationPriority:hsw */
> - intel_uncore_rmw(&dev_priv->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
> + intel_uncore_rmw(&i915->uncore, GAM_ECOCHK, 0, HSW_ECOCHK_ARB_PRIO_SOL);
>
> - lpt_init_clock_gating(dev_priv);
> + lpt_init_clock_gating(i915);
> }
>
> -static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void ivb_init_clock_gating(struct drm_i915_private *i915)
> {
> - intel_uncore_write(&dev_priv->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_write(&i915->uncore, ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
>
> /* WaFbcAsynchFlipDisableFbcQueue:ivb */
> - intel_uncore_rmw(&dev_priv->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
> + intel_uncore_rmw(&i915->uncore, ILK_DISPLAY_CHICKEN1, 0, ILK_FBCQ_DIS);
>
> /* WaDisableBackToBackFlipFix:ivb */
> - intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
> - CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> - CHICKEN3_DGMG_DONE_FIX_DISABLE);
> + intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
> + CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> + CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> - if (IS_IVB_GT1(dev_priv))
> - intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
> - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> + if (IS_IVB_GT1(i915))
> + intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
> + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> else {
> /* must write both registers */
> - intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
> - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> - intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2_GT2,
> - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> + intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
> + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> + intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2_GT2,
> + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> }
>
> /*
> * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> * This implements the WaDisableRCZUnitClockGating:ivb workaround.
> */
> - intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
> - GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_write(&i915->uncore, GEN6_UCGCTL2,
> + GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>
> /* This is required by WaCatErrorRejectionIssue:ivb */
> - intel_uncore_rmw(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> + intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> - g4x_disable_trickle_feed(dev_priv);
> + g4x_disable_trickle_feed(i915);
>
> - intel_uncore_rmw(&dev_priv->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
> + intel_uncore_rmw(&i915->uncore, GEN6_MBCUNIT_SNPCR, GEN6_MBC_SNPCR_MASK,
> GEN6_MBC_SNPCR_MED);
>
> - if (!HAS_PCH_NOP(dev_priv))
> - cpt_init_clock_gating(dev_priv);
> + if (!HAS_PCH_NOP(i915))
> + cpt_init_clock_gating(i915);
>
> - gen6_check_mch_setup(dev_priv);
> + gen6_check_mch_setup(i915);
> }
>
> -static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void vlv_init_clock_gating(struct drm_i915_private *i915)
> {
> /* WaDisableBackToBackFlipFix:vlv */
> - intel_uncore_write(&dev_priv->uncore, IVB_CHICKEN3,
> - CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> - CHICKEN3_DGMG_DONE_FIX_DISABLE);
> + intel_uncore_write(&i915->uncore, IVB_CHICKEN3,
> + CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
> + CHICKEN3_DGMG_DONE_FIX_DISABLE);
>
> /* WaDisableDopClockGating:vlv */
> - intel_uncore_write(&dev_priv->uncore, GEN7_ROW_CHICKEN2,
> - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
> + intel_uncore_write(&i915->uncore, GEN7_ROW_CHICKEN2,
> + _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
>
> /* This is required by WaCatErrorRejectionIssue:vlv */
> - intel_uncore_rmw(&dev_priv->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> + intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
> 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
>
> /*
> * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
> * This implements the WaDisableRCZUnitClockGating:vlv workaround.
> */
> - intel_uncore_write(&dev_priv->uncore, GEN6_UCGCTL2,
> - GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_write(&i915->uncore, GEN6_UCGCTL2,
> + GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>
> /* WaDisableL3Bank2xClockGate:vlv
> * Disabling L3 clock gating- MMIO 940c[25] = 1
> * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
> - intel_uncore_rmw(&dev_priv->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
> + intel_uncore_rmw(&i915->uncore, GEN7_UCGCTL4, 0, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
>
> /*
> * WaDisableVLVClockGating_VBIIssue:vlv
> * Disable clock gating on th GCFG unit to prevent a delay
> * in the reporting of vblank events.
> */
> - intel_uncore_write(&dev_priv->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
> + intel_uncore_write(&i915->uncore, VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
> }
>
> -static void chv_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void chv_init_clock_gating(struct drm_i915_private *i915)
> {
> /* WaVSRefCountFullforceMissDisable:chv */
> /* WaDSRefCountFullforceMissDisable:chv */
> - intel_uncore_rmw(&dev_priv->uncore, GEN7_FF_THREAD_MODE,
> + intel_uncore_rmw(&i915->uncore, GEN7_FF_THREAD_MODE,
> GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME, 0);
>
> /* WaDisableSemaphoreAndSyncFlipWait:chv */
> - intel_uncore_write(&dev_priv->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
> - _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
> + intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE),
> + _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
>
> /* WaDisableCSUnitClockGating:chv */
> - intel_uncore_rmw(&dev_priv->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_rmw(&i915->uncore, GEN6_UCGCTL1, 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
>
> /* WaDisableSDEUnitClockGating:chv */
> - intel_uncore_rmw(&dev_priv->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_rmw(&i915->uncore, GEN8_UCGCTL6, 0, GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
>
> /*
> * WaProgramL3SqcReg1Default:chv
> * See gfxspecs/Related Documents/Performance Guide/
> * LSQC Setting Recommendations.
> */
> - gen8_set_l3sqc_credits(dev_priv, 38, 2);
> + gen8_set_l3sqc_credits(i915, 38, 2);
> }
>
> -static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void g4x_init_clock_gating(struct drm_i915_private *i915)
> {
> u32 dspclk_gate;
>
> - intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, 0);
> - intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
> - GS_UNIT_CLOCK_GATE_DISABLE |
> - CL_UNIT_CLOCK_GATE_DISABLE);
> - intel_uncore_write(&dev_priv->uncore, RAMCLK_GATE_D, 0);
> + intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, 0);
> + intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
> + GS_UNIT_CLOCK_GATE_DISABLE |
> + CL_UNIT_CLOCK_GATE_DISABLE);
> + intel_uncore_write(&i915->uncore, RAMCLK_GATE_D, 0);
> dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
> OVRUNIT_CLOCK_GATE_DISABLE |
> OVCUNIT_CLOCK_GATE_DISABLE;
> - if (IS_GM45(dev_priv))
> + if (IS_GM45(i915))
> dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
> - intel_uncore_write(&dev_priv->uncore, DSPCLK_GATE_D(dev_priv), dspclk_gate);
> + intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate);
>
> - g4x_disable_trickle_feed(dev_priv);
> + g4x_disable_trickle_feed(i915);
> }
>
> -static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void i965gm_init_clock_gating(struct drm_i915_private *i915)
> {
> - struct intel_uncore *uncore = &dev_priv->uncore;
> + struct intel_uncore *uncore = &i915->uncore;
>
> intel_uncore_write(uncore, RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
> intel_uncore_write(uncore, RENCLK_GATE_D2, 0);
> - intel_uncore_write(uncore, DSPCLK_GATE_D(dev_priv), 0);
> + intel_uncore_write(uncore, DSPCLK_GATE_D(i915), 0);
> intel_uncore_write(uncore, RAMCLK_GATE_D, 0);
> intel_uncore_write16(uncore, DEUC, 0);
> intel_uncore_write(uncore,
> @@ -707,54 +709,55 @@ static void i965gm_init_clock_gating(struct drm_i915_private *dev_priv)
> _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
> }
>
> -static void i965g_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void i965g_init_clock_gating(struct drm_i915_private *i915)
> {
> - intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
> - I965_RCC_CLOCK_GATE_DISABLE |
> - I965_RCPB_CLOCK_GATE_DISABLE |
> - I965_ISC_CLOCK_GATE_DISABLE |
> - I965_FBC_CLOCK_GATE_DISABLE);
> - intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D2, 0);
> - intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
> - _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
> + intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
> + I965_RCC_CLOCK_GATE_DISABLE |
> + I965_RCPB_CLOCK_GATE_DISABLE |
> + I965_ISC_CLOCK_GATE_DISABLE |
> + I965_FBC_CLOCK_GATE_DISABLE);
> + intel_uncore_write(&i915->uncore, RENCLK_GATE_D2, 0);
> + intel_uncore_write(&i915->uncore, MI_ARB_STATE,
> + _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
> }
>
> -static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void gen3_init_clock_gating(struct drm_i915_private *i915)
> {
> - u32 dstate = intel_uncore_read(&dev_priv->uncore, D_STATE);
> + u32 dstate = intel_uncore_read(&i915->uncore, D_STATE);
>
> dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
> DSTATE_DOT_CLOCK_GATING;
> - intel_uncore_write(&dev_priv->uncore, D_STATE, dstate);
> + intel_uncore_write(&i915->uncore, D_STATE, dstate);
>
> - if (IS_PINEVIEW(dev_priv))
> - intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
> + if (IS_PINEVIEW(i915))
> + intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE),
> _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
>
> /* IIR "flip pending" means done if this bit is set */
> - intel_uncore_write(&dev_priv->uncore, ECOSKPD(RENDER_RING_BASE),
> + intel_uncore_write(&i915->uncore, ECOSKPD(RENDER_RING_BASE),
> _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
>
> /* interrupts should cause a wake up from C3 */
> - intel_uncore_write(&dev_priv->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
> + intel_uncore_write(&i915->uncore, INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
>
> /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
> - intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
> + intel_uncore_write(&i915->uncore, MI_ARB_STATE,
> + _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
>
> - intel_uncore_write(&dev_priv->uncore, MI_ARB_STATE,
> - _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
> + intel_uncore_write(&i915->uncore, MI_ARB_STATE,
> + _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
> }
>
> -static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void i85x_init_clock_gating(struct drm_i915_private *i915)
> {
> - intel_uncore_write(&dev_priv->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
> + intel_uncore_write(&i915->uncore, RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
>
> /* interrupts should cause a wake up from C3 */
> - intel_uncore_write(&dev_priv->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
> - _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
> + intel_uncore_write(&i915->uncore, MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
> + _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
>
> - intel_uncore_write(&dev_priv->uncore, MEM_MODE,
> - _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
> + intel_uncore_write(&i915->uncore, MEM_MODE,
> + _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
>
> /*
> * Have FBC ignore 3D activity since we use software
> @@ -763,25 +766,25 @@ static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
> * abosultely nothing) would not allow FBC to recompress
> * until a 2D blit occurs.
> */
> - intel_uncore_write(&dev_priv->uncore, SCPD0,
> - _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
> + intel_uncore_write(&i915->uncore, SCPD0,
> + _MASKED_BIT_ENABLE(SCPD_FBC_IGNORE_3D));
> }
>
> -static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void i830_init_clock_gating(struct drm_i915_private *i915)
> {
> - intel_uncore_write(&dev_priv->uncore, MEM_MODE,
> - _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
> - _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
> + intel_uncore_write(&i915->uncore, MEM_MODE,
> + _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
> + _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
> }
>
> -void intel_clock_gating_init(struct drm_i915_private *dev_priv)
> +void intel_clock_gating_init(struct drm_i915_private *i915)
> {
> - dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
> + i915->clock_gating_funcs->init_clock_gating(i915);
> }
>
> -static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
> +static void nop_init_clock_gating(struct drm_i915_private *i915)
> {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(&i915->drm,
> "No clock gating settings or workarounds applied.\n");
> }
>
> @@ -819,67 +822,67 @@ CG_FUNCS(nop);
>
> /**
> * intel_clock_gating_hooks_init - setup the clock gating hooks
> - * @dev_priv: device private
> + * @i915: device private
> *
> * Setup the hooks that configure which clocks of a given platform can be
> * gated and also apply various GT and display specific workarounds for these
> * platforms. Note that some GT specific workarounds are applied separately
> * when GPU contexts or batchbuffers start their execution.
> */
> -void intel_clock_gating_hooks_init(struct drm_i915_private *dev_priv)
> -{
> - if (IS_METEORLAKE(dev_priv))
> - dev_priv->clock_gating_funcs = &nop_clock_gating_funcs;
> - else if (IS_PONTEVECCHIO(dev_priv))
> - dev_priv->clock_gating_funcs = &pvc_clock_gating_funcs;
> - else if (IS_DG2(dev_priv))
> - dev_priv->clock_gating_funcs = &dg2_clock_gating_funcs;
> - else if (IS_XEHPSDV(dev_priv))
> - dev_priv->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
> - else if (IS_ALDERLAKE_P(dev_priv))
> - dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs;
> - else if (GRAPHICS_VER(dev_priv) == 12)
> - dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs;
> - else if (GRAPHICS_VER(dev_priv) == 11)
> - dev_priv->clock_gating_funcs = &icl_clock_gating_funcs;
> - else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
> - dev_priv->clock_gating_funcs = &cfl_clock_gating_funcs;
> - else if (IS_SKYLAKE(dev_priv))
> - dev_priv->clock_gating_funcs = &skl_clock_gating_funcs;
> - else if (IS_KABYLAKE(dev_priv))
> - dev_priv->clock_gating_funcs = &kbl_clock_gating_funcs;
> - else if (IS_BROXTON(dev_priv))
> - dev_priv->clock_gating_funcs = &bxt_clock_gating_funcs;
> - else if (IS_GEMINILAKE(dev_priv))
> - dev_priv->clock_gating_funcs = &glk_clock_gating_funcs;
> - else if (IS_BROADWELL(dev_priv))
> - dev_priv->clock_gating_funcs = &bdw_clock_gating_funcs;
> - else if (IS_CHERRYVIEW(dev_priv))
> - dev_priv->clock_gating_funcs = &chv_clock_gating_funcs;
> - else if (IS_HASWELL(dev_priv))
> - dev_priv->clock_gating_funcs = &hsw_clock_gating_funcs;
> - else if (IS_IVYBRIDGE(dev_priv))
> - dev_priv->clock_gating_funcs = &ivb_clock_gating_funcs;
> - else if (IS_VALLEYVIEW(dev_priv))
> - dev_priv->clock_gating_funcs = &vlv_clock_gating_funcs;
> - else if (GRAPHICS_VER(dev_priv) == 6)
> - dev_priv->clock_gating_funcs = &gen6_clock_gating_funcs;
> - else if (GRAPHICS_VER(dev_priv) == 5)
> - dev_priv->clock_gating_funcs = &ilk_clock_gating_funcs;
> - else if (IS_G4X(dev_priv))
> - dev_priv->clock_gating_funcs = &g4x_clock_gating_funcs;
> - else if (IS_I965GM(dev_priv))
> - dev_priv->clock_gating_funcs = &i965gm_clock_gating_funcs;
> - else if (IS_I965G(dev_priv))
> - dev_priv->clock_gating_funcs = &i965g_clock_gating_funcs;
> - else if (GRAPHICS_VER(dev_priv) == 3)
> - dev_priv->clock_gating_funcs = &gen3_clock_gating_funcs;
> - else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
> - dev_priv->clock_gating_funcs = &i85x_clock_gating_funcs;
> - else if (GRAPHICS_VER(dev_priv) == 2)
> - dev_priv->clock_gating_funcs = &i830_clock_gating_funcs;
> +void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
> +{
> + if (IS_METEORLAKE(i915))
> + i915->clock_gating_funcs = &nop_clock_gating_funcs;
> + else if (IS_PONTEVECCHIO(i915))
> + i915->clock_gating_funcs = &pvc_clock_gating_funcs;
> + else if (IS_DG2(i915))
> + i915->clock_gating_funcs = &dg2_clock_gating_funcs;
> + else if (IS_XEHPSDV(i915))
> + i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
> + else if (IS_ALDERLAKE_P(i915))
> + i915->clock_gating_funcs = &adlp_clock_gating_funcs;
> + else if (GRAPHICS_VER(i915) == 12)
> + i915->clock_gating_funcs = &gen12lp_clock_gating_funcs;
> + else if (GRAPHICS_VER(i915) == 11)
> + i915->clock_gating_funcs = &icl_clock_gating_funcs;
> + else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
> + i915->clock_gating_funcs = &cfl_clock_gating_funcs;
> + else if (IS_SKYLAKE(i915))
> + i915->clock_gating_funcs = &skl_clock_gating_funcs;
> + else if (IS_KABYLAKE(i915))
> + i915->clock_gating_funcs = &kbl_clock_gating_funcs;
> + else if (IS_BROXTON(i915))
> + i915->clock_gating_funcs = &bxt_clock_gating_funcs;
> + else if (IS_GEMINILAKE(i915))
> + i915->clock_gating_funcs = &glk_clock_gating_funcs;
> + else if (IS_BROADWELL(i915))
> + i915->clock_gating_funcs = &bdw_clock_gating_funcs;
> + else if (IS_CHERRYVIEW(i915))
> + i915->clock_gating_funcs = &chv_clock_gating_funcs;
> + else if (IS_HASWELL(i915))
> + i915->clock_gating_funcs = &hsw_clock_gating_funcs;
> + else if (IS_IVYBRIDGE(i915))
> + i915->clock_gating_funcs = &ivb_clock_gating_funcs;
> + else if (IS_VALLEYVIEW(i915))
> + i915->clock_gating_funcs = &vlv_clock_gating_funcs;
> + else if (GRAPHICS_VER(i915) == 6)
> + i915->clock_gating_funcs = &gen6_clock_gating_funcs;
> + else if (GRAPHICS_VER(i915) == 5)
> + i915->clock_gating_funcs = &ilk_clock_gating_funcs;
> + else if (IS_G4X(i915))
> + i915->clock_gating_funcs = &g4x_clock_gating_funcs;
> + else if (IS_I965GM(i915))
> + i915->clock_gating_funcs = &i965gm_clock_gating_funcs;
> + else if (IS_I965G(i915))
> + i915->clock_gating_funcs = &i965g_clock_gating_funcs;
> + else if (GRAPHICS_VER(i915) == 3)
> + i915->clock_gating_funcs = &gen3_clock_gating_funcs;
> + else if (IS_I85X(i915) || IS_I865G(i915))
> + i915->clock_gating_funcs = &i85x_clock_gating_funcs;
> + else if (GRAPHICS_VER(i915) == 2)
> + i915->clock_gating_funcs = &i830_clock_gating_funcs;
> else {
> - MISSING_CASE(INTEL_DEVID(dev_priv));
> - dev_priv->clock_gating_funcs = &nop_clock_gating_funcs;
> + MISSING_CASE(INTEL_DEVID(i915));
> + i915->clock_gating_funcs = &nop_clock_gating_funcs;
> }
> }
> --
> 2.39.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: pm cleanups, rename to clock gating
2023-03-01 13:54 [Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating Jani Nikula
` (7 preceding siblings ...)
2023-03-01 21:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-03-04 9:43 ` Patchwork
8 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-03-04 9:43 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 42033 bytes --]
== Series Details ==
Series: drm/i915: pm cleanups, rename to clock gating
URL : https://patchwork.freedesktop.org/series/114519/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12799_full -> Patchwork_114519v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (19 -> 19)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_114519v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_atomic_transition@modeset-transition-nonblocking@3x-outputs (NEW):
- {shard-dg2-11}: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-dg2-11/igt@kms_atomic_transition@modeset-transition-nonblocking@3x-outputs.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_create@create-ext-cpu-access-big:
- {shard-dg2-10}: NOTRUN -> [ABORT][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-dg2-10/igt@gem_create@create-ext-cpu-access-big.html
* igt@gem_eio@hibernate:
- {shard-dg2-3}: NOTRUN -> [ABORT][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-dg2-3/igt@gem_eio@hibernate.html
* igt@kms_async_flips@crc@pipe-b-dp-2:
- {shard-dg2-12}: NOTRUN -> [FAIL][4] +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-dg2-12/igt@kms_async_flips@crc@pipe-b-dp-2.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
- {shard-dg2-6}: NOTRUN -> [FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render:
- {shard-dg2-5}: NOTRUN -> [FAIL][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html
New tests
---------
New tests have been introduced between CI_DRM_12799_full and Patchwork_114519v1_full:
### New IGT tests (41) ###
* igt@kms_atomic_transition@modeset-transition-nonblocking@3x-outputs:
- Statuses : 1 fail(s)
- Exec time: [0.0] s
* igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-a-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-d-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@ab-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@ab-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@ab-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@ac-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@ac-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@ac-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@ad-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@ad-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@ad-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@bc-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@bc-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@bc-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@bd-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@bd-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@bd-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@cd-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@cd-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-absolute-wf_vblank-interruptible@cd-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-flip-vs-modeset-vs-hang@ab-dp2-dp3:
- Statuses :
- Exec time: [None] s
* igt@kms_flip@2x-plain-flip@ab-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@ab-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@ab-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@ac-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@ac-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@ac-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@ad-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@ad-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@ad-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@bc-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@bc-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@bc-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@bd-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@bd-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@bd-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@cd-dp2-dp3:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@cd-dp2-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@2x-plain-flip@cd-dp3-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_flip@modeset-vs-vblank-race-interruptible@d-dp4:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_114519v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@cold-reset-bound:
- shard-tglu-9: NOTRUN -> [SKIP][7] ([i915#7701])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@device_reset@cold-reset-bound.html
* igt@feature_discovery@psr1:
- shard-tglu-9: NOTRUN -> [SKIP][8] ([i915#658])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@feature_discovery@psr1.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-tglu-10: NOTRUN -> [SKIP][9] ([i915#5325])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_ctx_isolation@preservation-s3@bcs0:
- shard-apl: [PASS][10] -> [ABORT][11] ([i915#180])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-apl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-apl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html
* igt@gem_ctx_sseu@mmap-args:
- shard-tglu-10: NOTRUN -> [SKIP][12] ([i915#280])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-tglu-9: NOTRUN -> [FAIL][15] ([i915#2842]) +4 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-tglu-9: NOTRUN -> [SKIP][16] ([fdo#109313])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-tglu-9: NOTRUN -> [SKIP][17] ([fdo#109283])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_lmem_swapping@random-engines:
- shard-tglu-9: NOTRUN -> [SKIP][18] ([i915#4613])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify:
- shard-tglu-10: NOTRUN -> [SKIP][19] ([i915#4613])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@gem_lmem_swapping@verify.html
* igt@gem_pwrite@basic-exhaustion:
- shard-tglu-10: NOTRUN -> [WARN][20] ([i915#2658])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-tglu-9: NOTRUN -> [SKIP][21] ([i915#4270])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_userptr_blits@vma-merge:
- shard-tglu-9: NOTRUN -> [FAIL][22] ([i915#3318])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_render_linear_blits:
- shard-tglu-10: NOTRUN -> [SKIP][23] ([fdo#109289])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@gen3_render_linear_blits.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-tglu-10: NOTRUN -> [SKIP][24] ([i915#2527] / [i915#2856]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@gen9_exec_parse@batch-zero-length.html
* igt@i915_pm_backlight@bad-brightness:
- shard-tglu-10: NOTRUN -> [SKIP][25] ([i915#7561])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@i915_pm_backlight@bad-brightness.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][26] -> [DMESG-FAIL][27] ([i915#5334])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-apl7/igt@i915_selftest@live@gt_heartbeat.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-apl4/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-tglu-10: NOTRUN -> [INCOMPLETE][28] ([i915#7443])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
- shard-tglu-10: NOTRUN -> [SKIP][29] ([i915#5286])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-180:
- shard-tglu-9: NOTRUN -> [SKIP][30] ([fdo#111615] / [i915#1845] / [i915#7651])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_big_fb@yf-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-tglu-10: NOTRUN -> [SKIP][31] ([fdo#111615]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][32] ([i915#3689] / [i915#3886]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_mc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][33] ([i915#3689] / [i915#6095])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-tglu-9: NOTRUN -> [SKIP][34] ([i915#1845] / [i915#7651]) +27 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_dg2_rc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][35] ([i915#6095])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_ccs@pipe-c-crc-primary-basic-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][36] ([fdo#111615] / [i915#3689]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-tglu-10: NOTRUN -> [SKIP][37] ([i915#3689]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium_color@ctm-0-75:
- shard-tglu-9: NOTRUN -> [SKIP][38] ([fdo#111827])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_chamelium_color@ctm-0-75.html
* igt@kms_chamelium_frames@dp-crc-multiple:
- shard-tglu-9: NOTRUN -> [SKIP][39] ([i915#7828]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_chamelium_frames@dp-crc-multiple.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-tglu-10: NOTRUN -> [SKIP][40] ([i915#7828]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_color@ctm-0-25@pipe-b-hdmi-a-1:
- shard-tglu-10: NOTRUN -> [FAIL][41] ([i915#315] / [i915#6946]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_color@ctm-0-25@pipe-b-hdmi-a-1.html
* igt@kms_color@ctm-max:
- shard-tglu-9: NOTRUN -> [SKIP][42] ([i915#3546])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_color@ctm-max.html
* igt@kms_cursor_crc@cursor-offscreen-128x128:
- shard-tglu-9: NOTRUN -> [SKIP][43] ([i915#1845]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_cursor_crc@cursor-offscreen-128x128.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-tglu-10: NOTRUN -> [SKIP][44] ([fdo#109274])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][45] -> [FAIL][46] ([i915#2346])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglu-10: NOTRUN -> [FAIL][47] ([i915#4767])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-dpms-vs-vblank-race:
- shard-tglu-9: NOTRUN -> [SKIP][48] ([fdo#109274] / [i915#3637])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_flip@2x-dpms-vs-vblank-race.html
* igt@kms_flip@2x-flip-vs-suspend:
- shard-tglu-10: NOTRUN -> [SKIP][49] ([fdo#109274] / [i915#3637]) +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_flip@2x-flip-vs-suspend.html
* igt@kms_flip@flip-vs-panning-interruptible:
- shard-tglu-9: NOTRUN -> [SKIP][50] ([i915#3637]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_flip@flip-vs-panning-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling:
- shard-tglu-9: NOTRUN -> [SKIP][51] ([i915#3555]) +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_flip_scaled_crc@flip-32bpp-xtile-to-64bpp-xtile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu-10: NOTRUN -> [SKIP][52] ([i915#2587] / [i915#2672])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-tglu-10: NOTRUN -> [SKIP][53] ([fdo#109285])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
- shard-tglu-9: NOTRUN -> [SKIP][54] ([i915#1849]) +18 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-tglu-10: NOTRUN -> [SKIP][55] ([fdo#109280]) +6 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:
- shard-tglu-10: NOTRUN -> [SKIP][56] ([fdo#110189]) +7 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html
* igt@kms_plane_multiple@tiling-yf:
- shard-tglu-10: NOTRUN -> [SKIP][57] ([i915#3555])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][58] ([fdo#109271]) +23 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-snb5/igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-vga-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-tglu-10: NOTRUN -> [SKIP][59] ([i915#5235]) +3 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_prime@basic-crc-hybrid:
- shard-tglu-10: NOTRUN -> [SKIP][60] ([i915#6524])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
- shard-tglu-10: NOTRUN -> [SKIP][61] ([i915#658])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-tglu-9: NOTRUN -> [SKIP][62] ([fdo#109642] / [fdo#111068] / [i915#658])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@cursor_plane_onoff:
- shard-tglu-9: NOTRUN -> [SKIP][63] ([fdo#110189])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_psr@cursor_plane_onoff.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-tglu-10: NOTRUN -> [SKIP][64] ([i915#5289])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_universal_plane@cursor-fb-leak-pipe-b:
- shard-tglu-9: NOTRUN -> [SKIP][65] ([fdo#109274]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak-pipe-b.html
* igt@prime_vgem@fence-flip-hang:
- shard-tglu-9: NOTRUN -> [SKIP][66] ([fdo#109295])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@prime_vgem@fence-flip-hang.html
* igt@v3d/v3d_mmap@mmap-bo:
- shard-tglu-9: NOTRUN -> [SKIP][67] ([fdo#109315] / [i915#2575]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@v3d/v3d_mmap@mmap-bo.html
* igt@v3d/v3d_perfmon@create-perfmon-0:
- shard-tglu-10: NOTRUN -> [SKIP][68] ([fdo#109315] / [i915#2575])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@v3d/v3d_perfmon@create-perfmon-0.html
* igt@vc4/vc4_perfmon@destroy-invalid-perfmon:
- shard-tglu-10: NOTRUN -> [SKIP][69] ([i915#2575]) +3 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-10/igt@vc4/vc4_perfmon@destroy-invalid-perfmon.html
* igt@vc4/vc4_purgeable_bo@mark-purgeable-twice:
- shard-tglu-9: NOTRUN -> [SKIP][70] ([i915#2575])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-tglu-9/igt@vc4/vc4_purgeable_bo@mark-purgeable-twice.html
#### Possible fixes ####
* igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
- {shard-rkl}: [SKIP][71] ([i915#3281]) -> [PASS][72] +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-4/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-rkl-5/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
* igt@gem_exec_schedule@semaphore-power:
- {shard-rkl}: [SKIP][73] ([i915#7276]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-4/igt@gem_exec_schedule@semaphore-power.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-rkl-5/igt@gem_exec_schedule@semaphore-power.html
* igt@gen9_exec_parse@cmd-crossing-page:
- {shard-rkl}: [SKIP][75] ([i915#2527]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-4/igt@gen9_exec_parse@cmd-crossing-page.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-rkl-5/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_hangman@gt-engine-error@bcs0:
- {shard-rkl}: [SKIP][77] ([i915#6258]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-rkl-4/igt@i915_hangman@gt-engine-error@bcs0.html
* igt@kms_atomic@atomic_plane_damage:
- {shard-rkl}: [SKIP][79] ([i915#4098]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-4/igt@kms_atomic@atomic_plane_damage.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-rkl-6/igt@kms_atomic@atomic_plane_damage.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- {shard-rkl}: [SKIP][81] ([i915#1845] / [i915#4098]) -> [PASS][82] +20 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-rkl-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][83] ([i915#2346]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
- shard-apl: [FAIL][85] ([i915#2346]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-apl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-apl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2:
- shard-glk: [FAIL][87] ([i915#79]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-glk8/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a2.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt:
- {shard-rkl}: [SKIP][89] ([i915#1849] / [i915#4098]) -> [PASS][90] +10 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_properties@crtc-properties-legacy:
- {shard-rkl}: [SKIP][91] ([i915#1849]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@kms_properties@crtc-properties-legacy.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-rkl-6/igt@kms_properties@crtc-properties-legacy.html
* igt@kms_psr@cursor_blt:
- {shard-rkl}: [SKIP][93] ([i915#1072]) -> [PASS][94] +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@kms_psr@cursor_blt.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-rkl-6/igt@kms_psr@cursor_blt.html
* igt@perf@gen12-oa-tlb-invalidate:
- {shard-rkl}: [SKIP][95] ([fdo#109289]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12799/shard-rkl-5/igt@perf@gen12-oa-tlb-invalidate.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/shard-rkl-4/igt@perf@gen12-oa-tlb-invalidate.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#5107]: https://gitlab.freedesktop.org/drm/intel/issues/5107
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5410]: https://gitlab.freedesktop.org/drm/intel/issues/5410
[i915#5431]: https://gitlab.freedesktop.org/drm/intel/issues/5431
[i915#5433]: https://gitlab.freedesktop.org/drm/intel/issues/5433
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5445]: https://gitlab.freedesktop.org/drm/intel/issues/5445
[i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5882]: https://gitlab.freedesktop.org/drm/intel/issues/5882
[i915#5889]: https://gitlab.freedesktop.org/drm/intel/issues/5889
[i915#5892]: https://gitlab.freedesktop.org/drm/intel/issues/5892
[i915#5978]: https://gitlab.freedesktop.org/drm/intel/issues/5978
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6118]: https://gitlab.freedesktop.org/drm/intel/issues/6118
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6228]: https://gitlab.freedesktop.org/drm/intel/issues/6228
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6259]: https://gitlab.freedesktop.org/drm/intel/issues/6259
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
[i915#7091]: https://gitlab.freedesktop.org/drm/intel/issues/7091
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7679]: https://gitlab.freedesktop.org/drm/intel/issues/7679
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150
[i915#8152]: https://gitlab.freedesktop.org/drm/intel/issues/8152
[i915#8154]: https://gitlab.freedesktop.org/drm/intel/issues/8154
[i915#8155]: https://gitlab.freedesktop.org/drm/intel/issues/8155
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
Build changes
-------------
* Linux: CI_DRM_12799 -> Patchwork_114519v1
CI-20190529: 20190529
CI_DRM_12799: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7178: ffe3f6670b91ab975f90799ab3fd0941b6eae019 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_114519v1: 5f6631c00a7f226c990aecc643bc9fa70da1599a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_114519v1/index.html
[-- Attachment #2: Type: text/html, Size: 38248 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH 4/6] drm/i915: remove unnecessary intel_pm.h includes
2023-03-02 18:37 ` Rodrigo Vivi
@ 2023-03-06 17:47 ` Jani Nikula
0 siblings, 0 replies; 17+ messages in thread
From: Jani Nikula @ 2023-03-06 17:47 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
On Thu, 02 Mar 2023, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Wed, Mar 01, 2023 at 03:54:18PM +0200, Jani Nikula wrote:
>> As intel_pm.[ch] used to contain much more, intel_pm.h was included in a
>> lot of places. Many of them are now unnecessary. Remove.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> trusting the compiler:
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Thanks, pushed 1-4 to drm-intel-next. The rename in patch 5 leads to
conflicts with drm-intel-gt-next changing stuff in intel_pm.c.
BR,
Jani.
>
>
>> ---
>> drivers/gpu/drm/i915/display/i9xx_wm.c | 1 -
>> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
>> drivers/gpu/drm/i915/display/intel_modeset_setup.c | 1 -
>> drivers/gpu/drm/i915/display/skl_watermark.c | 1 -
>> drivers/gpu/drm/i915/gt/intel_gt.c | 1 -
>> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 -
>> drivers/gpu/drm/i915/gt/selftest_llc.c | 1 -
>> drivers/gpu/drm/i915/i915_debugfs.c | 1 -
>> drivers/gpu/drm/i915/i915_irq.c | 1 -
>> drivers/gpu/drm/i915/i915_pmu.c | 1 -
>> drivers/gpu/drm/i915/i915_request.c | 1 -
>> drivers/gpu/drm/i915/i915_sysfs.c | 1 -
>> drivers/gpu/drm/i915/intel_uncore.c | 1 -
>> 13 files changed, 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> index 3d4687efe4dd..caef72d38798 100644
>> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> @@ -9,7 +9,6 @@
>> #include "intel_display.h"
>> #include "intel_display_trace.h"
>> #include "intel_mchbar_regs.h"
>> -#include "intel_pm.h"
>> #include "intel_wm.h"
>> #include "skl_watermark.h"
>> #include "vlv_sideband.h"
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> index 25013f303c82..1e654ddd0815 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>> @@ -26,7 +26,6 @@
>> #include "intel_hdmi.h"
>> #include "intel_hotplug.h"
>> #include "intel_panel.h"
>> -#include "intel_pm.h"
>> #include "intel_psr.h"
>> #include "intel_sprite.h"
>> #include "intel_wm.h"
>> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
>> index 60f71e6f0491..7ff083ec2d1d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
>> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
>> @@ -25,7 +25,6 @@
>> #include "intel_fifo_underrun.h"
>> #include "intel_modeset_setup.h"
>> #include "intel_pch_display.h"
>> -#include "intel_pm.h"
>> #include "intel_wm.h"
>> #include "skl_watermark.h"
>>
>> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>> index 1300965d328a..f0af997d2a23 100644
>> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
>> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>> @@ -18,7 +18,6 @@
>> #include "intel_display_types.h"
>> #include "intel_fb.h"
>> #include "intel_pcode.h"
>> -#include "intel_pm.h"
>> #include "intel_wm.h"
>> #include "skl_watermark.h"
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index f7f271708fc7..6ca944d01eb6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -28,7 +28,6 @@
>> #include "intel_migrate.h"
>> #include "intel_mocs.h"
>> #include "intel_pci_config.h"
>> -#include "intel_pm.h"
>> #include "intel_rc6.h"
>> #include "intel_renderstate.h"
>> #include "intel_rps.h"
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> index cef3d6f5c34e..85ae7dc079f2 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> @@ -17,7 +17,6 @@
>> #include "intel_gt_print.h"
>> #include "intel_gt_requests.h"
>> #include "intel_llc.h"
>> -#include "intel_pm.h"
>> #include "intel_rc6.h"
>> #include "intel_rps.h"
>> #include "intel_wakeref.h"
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_llc.c b/drivers/gpu/drm/i915/gt/selftest_llc.c
>> index cfd736d88939..779fadcec7c4 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_llc.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_llc.c
>> @@ -3,7 +3,6 @@
>> * Copyright © 2019 Intel Corporation
>> */
>>
>> -#include "intel_pm.h" /* intel_gpu_freq() */
>> #include "selftest_llc.h"
>> #include "intel_rps.h"
>>
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 45773ce1deac..16011c0286ad 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -52,7 +52,6 @@
>> #include "i915_irq.h"
>> #include "i915_scheduler.h"
>> #include "intel_mchbar_regs.h"
>> -#include "intel_pm.h"
>>
>> static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
>> {
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index 417c981e4968..6ce3c934d832 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -52,7 +52,6 @@
>> #include "i915_driver.h"
>> #include "i915_drv.h"
>> #include "i915_irq.h"
>> -#include "intel_pm.h"
>>
>> /**
>> * DOC: interrupt handling
>> diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
>> index 52531ab28c5f..a76c5ce9513d 100644
>> --- a/drivers/gpu/drm/i915/i915_pmu.c
>> +++ b/drivers/gpu/drm/i915/i915_pmu.c
>> @@ -17,7 +17,6 @@
>>
>> #include "i915_drv.h"
>> #include "i915_pmu.h"
>> -#include "intel_pm.h"
>>
>> /* Frequency for the sampling timer for events which need it. */
>> #define FREQUENCY 200
>> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
>> index 7503dcb9043b..630a732aaecc 100644
>> --- a/drivers/gpu/drm/i915/i915_request.c
>> +++ b/drivers/gpu/drm/i915/i915_request.c
>> @@ -48,7 +48,6 @@
>> #include "i915_driver.h"
>> #include "i915_drv.h"
>> #include "i915_trace.h"
>> -#include "intel_pm.h"
>>
>> struct execute_cb {
>> struct irq_work work;
>> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
>> index 595e8b574990..e88bb4f04305 100644
>> --- a/drivers/gpu/drm/i915/i915_sysfs.c
>> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
>> @@ -37,7 +37,6 @@
>>
>> #include "i915_drv.h"
>> #include "i915_sysfs.h"
>> -#include "intel_pm.h"
>>
>> struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
>> {
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index f018da7ebaac..f4b3b2063018 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -32,7 +32,6 @@
>> #include "i915_reg.h"
>> #include "i915_trace.h"
>> #include "i915_vgpu.h"
>> -#include "intel_pm.h"
>>
>> #define FORCEWAKE_ACK_TIMEOUT_MS 50
>> #define GT_FIFO_TIMEOUT_MS 10
>> --
>> 2.39.1
>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2023-03-06 17:47 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-01 13:54 [Intel-gfx] [PATCH 0/6] drm/i915: pm cleanups, rename to clock gating Jani Nikula
2023-03-01 13:54 ` [Intel-gfx] [PATCH 1/6] drm/i915/wm: remove display/ prefix from include Jani Nikula
2023-03-02 18:10 ` Rodrigo Vivi
2023-03-01 13:54 ` [Intel-gfx] [PATCH 2/6] drm/i915/pm: drop intel_pm_setup() Jani Nikula
2023-03-02 18:11 ` Rodrigo Vivi
2023-03-01 13:54 ` [Intel-gfx] [PATCH 3/6] drm/i915/pm: drop intel_suspend_hw() Jani Nikula
2023-03-02 18:36 ` Rodrigo Vivi
2023-03-01 13:54 ` [Intel-gfx] [PATCH 4/6] drm/i915: remove unnecessary intel_pm.h includes Jani Nikula
2023-03-02 18:37 ` Rodrigo Vivi
2023-03-06 17:47 ` Jani Nikula
2023-03-01 13:54 ` [Intel-gfx] [PATCH 5/6] drm/i915: rename intel_pm.[ch] to intel_clock_gating.[ch] Jani Nikula
2023-03-02 18:39 ` Rodrigo Vivi
2023-03-01 13:54 ` [Intel-gfx] [PATCH 6/6] drm/i915/clock: mass rename dev_priv to i915 Jani Nikula
2023-03-02 18:40 ` Rodrigo Vivi
2023-03-01 20:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: pm cleanups, rename to clock gating Patchwork
2023-03-01 21:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-04 9:43 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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