* [Intel-xe] [PATCH igt 0/4] Add LNL support to xe tests
@ 2023-08-29 14:11 ` Lucas De Marchi
0 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-08-29 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: Lucas De Marchi, intel-xe
Add Lunar Lake support so xe driver can be tested. This brings the new
xe_pciids.h from kernel since now the PCI IDs is not going to be added
on the i915 side.
Janga Rahul Kumar (1):
tests/xe_debugfs: skip page table level check for Xe2
Lucas De Marchi (2):
lib: Add xe_pciids.h
lib/intel_chipset: Add Lunar Lake support
Zbigniew Kempczyński (1):
lib/intel_device_info: Add blitter cmd info for Lunar Lake
docs/reference/igt-gpu-tools/meson.build | 1 +
lib/intel_chipset.h | 5 +
lib/intel_device_info.c | 14 ++
lib/xe_pciids.h | 215 +++++++++++++++++++++++
tests/xe/xe_debugfs.c | 23 +--
5 files changed, 248 insertions(+), 10 deletions(-)
create mode 100644 lib/xe_pciids.h
--
2.40.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* [igt-dev] [PATCH igt 0/4] Add LNL support to xe tests
@ 2023-08-29 14:11 ` Lucas De Marchi
0 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-08-29 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: Lucas De Marchi, intel-xe
Add Lunar Lake support so xe driver can be tested. This brings the new
xe_pciids.h from kernel since now the PCI IDs is not going to be added
on the i915 side.
Janga Rahul Kumar (1):
tests/xe_debugfs: skip page table level check for Xe2
Lucas De Marchi (2):
lib: Add xe_pciids.h
lib/intel_chipset: Add Lunar Lake support
Zbigniew Kempczyński (1):
lib/intel_device_info: Add blitter cmd info for Lunar Lake
docs/reference/igt-gpu-tools/meson.build | 1 +
lib/intel_chipset.h | 5 +
lib/intel_device_info.c | 14 ++
lib/xe_pciids.h | 215 +++++++++++++++++++++++
tests/xe/xe_debugfs.c | 23 +--
5 files changed, 248 insertions(+), 10 deletions(-)
create mode 100644 lib/xe_pciids.h
--
2.40.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Intel-xe] [PATCH igt 1/4] lib: Add xe_pciids.h
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
@ 2023-08-29 14:11 ` Lucas De Marchi
-1 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-08-29 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: Lucas De Marchi, intel-xe
With the introduction of Lunar Lake, igt won't be able to just re-use
i915_pciids.h for both drivers anymore since the support for LNL is only
coming with the xe module. Copy xe_pciids.h from the drm-xe-next branch
(up to commit b9c9020fc816 ("drm/xe/pvc: Use fast copy engines as
migrate engine on PVC") and start including it where needed. This brings
all the LNL PCI IDs.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
docs/reference/igt-gpu-tools/meson.build | 1 +
lib/intel_device_info.c | 1 +
lib/xe_pciids.h | 215 +++++++++++++++++++++++
3 files changed, 217 insertions(+)
create mode 100644 lib/xe_pciids.h
diff --git a/docs/reference/igt-gpu-tools/meson.build b/docs/reference/igt-gpu-tools/meson.build
index 6b832ad27..513385b4b 100644
--- a/docs/reference/igt-gpu-tools/meson.build
+++ b/docs/reference/igt-gpu-tools/meson.build
@@ -21,6 +21,7 @@ ignore_headers = [
'media_fill_gen9.h',
'gen9_render.h',
'version.h',
+ 'xe_pciids.h',
]
test_groups = [
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 2c9a45b68..5d53d2906 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -1,6 +1,7 @@
#include "intel_chipset.h"
#include "i915_pciids.h"
#include "i915_pciids_local.h"
+#include "xe_pciids.h"
#include <strings.h> /* ffs() */
diff --git a/lib/xe_pciids.h b/lib/xe_pciids.h
new file mode 100644
index 000000000..29f07a00a
--- /dev/null
+++ b/lib/xe_pciids.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _XE_PCIIDS_H_
+#define _XE_PCIIDS_H_
+
+/*
+ * Lists below can be turned into initializers for a struct pci_device_id
+ * by defining INTEL_VGA_DEVICE:
+ *
+ * #define INTEL_VGA_DEVICE(id, info) { \
+ * 0x8086, id, \
+ * ~0, ~0, \
+ * 0x030000, 0xff0000, \
+ * (unsigned long) info }
+ *
+ * And then calling like:
+ *
+ * XE_TGL_12_GT1_IDS(INTEL_VGA_DEVICE, ## __VA_ARGS__)
+ *
+ * To turn them into something else, just provide a different macro passed as
+ * first argument.
+ */
+
+/* TGL */
+#define XE_TGL_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x9A60, ## __VA_ARGS__), \
+ MACRO__(0x9A68, ## __VA_ARGS__), \
+ MACRO__(0x9A70, ## __VA_ARGS__)
+
+#define XE_TGL_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x9A40, ## __VA_ARGS__), \
+ MACRO__(0x9A49, ## __VA_ARGS__), \
+ MACRO__(0x9A59, ## __VA_ARGS__), \
+ MACRO__(0x9A78, ## __VA_ARGS__), \
+ MACRO__(0x9AC0, ## __VA_ARGS__), \
+ MACRO__(0x9AC9, ## __VA_ARGS__), \
+ MACRO__(0x9AD9, ## __VA_ARGS__), \
+ MACRO__(0x9AF8, ## __VA_ARGS__)
+
+#define XE_TGL_IDS(MACRO__, ...) \
+ XE_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__),\
+ XE_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
+
+/* RKL */
+#define XE_RKL_IDS(MACRO__, ...) \
+ MACRO__(0x4C80, ## __VA_ARGS__), \
+ MACRO__(0x4C8A, ## __VA_ARGS__), \
+ MACRO__(0x4C8B, ## __VA_ARGS__), \
+ MACRO__(0x4C8C, ## __VA_ARGS__), \
+ MACRO__(0x4C90, ## __VA_ARGS__), \
+ MACRO__(0x4C9A, ## __VA_ARGS__)
+
+/* DG1 */
+#define XE_DG1_IDS(MACRO__, ...) \
+ MACRO__(0x4905, ## __VA_ARGS__), \
+ MACRO__(0x4906, ## __VA_ARGS__), \
+ MACRO__(0x4907, ## __VA_ARGS__), \
+ MACRO__(0x4908, ## __VA_ARGS__), \
+ MACRO__(0x4909, ## __VA_ARGS__)
+
+/* ADL-S */
+#define XE_ADLS_IDS(MACRO__, ...) \
+ MACRO__(0x4680, ## __VA_ARGS__), \
+ MACRO__(0x4682, ## __VA_ARGS__), \
+ MACRO__(0x4688, ## __VA_ARGS__), \
+ MACRO__(0x468A, ## __VA_ARGS__), \
+ MACRO__(0x4690, ## __VA_ARGS__), \
+ MACRO__(0x4692, ## __VA_ARGS__), \
+ MACRO__(0x4693, ## __VA_ARGS__)
+
+/* ADL-P */
+#define XE_ADLP_IDS(MACRO__, ...) \
+ MACRO__(0x46A0, ## __VA_ARGS__), \
+ MACRO__(0x46A1, ## __VA_ARGS__), \
+ MACRO__(0x46A2, ## __VA_ARGS__), \
+ MACRO__(0x46A3, ## __VA_ARGS__), \
+ MACRO__(0x46A6, ## __VA_ARGS__), \
+ MACRO__(0x46A8, ## __VA_ARGS__), \
+ MACRO__(0x46AA, ## __VA_ARGS__), \
+ MACRO__(0x462A, ## __VA_ARGS__), \
+ MACRO__(0x4626, ## __VA_ARGS__), \
+ MACRO__(0x4628, ## __VA_ARGS__), \
+ MACRO__(0x46B0, ## __VA_ARGS__), \
+ MACRO__(0x46B1, ## __VA_ARGS__), \
+ MACRO__(0x46B2, ## __VA_ARGS__), \
+ MACRO__(0x46B3, ## __VA_ARGS__), \
+ MACRO__(0x46C0, ## __VA_ARGS__), \
+ MACRO__(0x46C1, ## __VA_ARGS__), \
+ MACRO__(0x46C2, ## __VA_ARGS__), \
+ MACRO__(0x46C3, ## __VA_ARGS__)
+
+/* ADL-N */
+#define XE_ADLN_IDS(MACRO__, ...) \
+ MACRO__(0x46D0, ## __VA_ARGS__), \
+ MACRO__(0x46D1, ## __VA_ARGS__), \
+ MACRO__(0x46D2, ## __VA_ARGS__)
+
+/* RPL-S */
+#define XE_RPLS_IDS(MACRO__, ...) \
+ MACRO__(0xA780, ## __VA_ARGS__), \
+ MACRO__(0xA781, ## __VA_ARGS__), \
+ MACRO__(0xA782, ## __VA_ARGS__), \
+ MACRO__(0xA783, ## __VA_ARGS__), \
+ MACRO__(0xA788, ## __VA_ARGS__), \
+ MACRO__(0xA789, ## __VA_ARGS__), \
+ MACRO__(0xA78A, ## __VA_ARGS__), \
+ MACRO__(0xA78B, ## __VA_ARGS__)
+
+/* RPL-U */
+#define XE_RPLU_IDS(MACRO__, ...) \
+ MACRO__(0xA721, ## __VA_ARGS__), \
+ MACRO__(0xA7A1, ## __VA_ARGS__), \
+ MACRO__(0xA7A9, ## __VA_ARGS__)
+
+/* RPL-P */
+#define XE_RPLP_IDS(MACRO__, ...) \
+ MACRO__(0xA720, ## __VA_ARGS__), \
+ MACRO__(0xA7A0, ## __VA_ARGS__), \
+ MACRO__(0xA7A8, ## __VA_ARGS__)
+
+/* DG2 */
+#define XE_DG2_G10_IDS(MACRO__, ...) \
+ MACRO__(0x5690, ## __VA_ARGS__), \
+ MACRO__(0x5691, ## __VA_ARGS__), \
+ MACRO__(0x5692, ## __VA_ARGS__), \
+ MACRO__(0x56A0, ## __VA_ARGS__), \
+ MACRO__(0x56A1, ## __VA_ARGS__), \
+ MACRO__(0x56A2, ## __VA_ARGS__)
+
+#define XE_DG2_G11_IDS(MACRO__, ...) \
+ MACRO__(0x5693, ## __VA_ARGS__), \
+ MACRO__(0x5694, ## __VA_ARGS__), \
+ MACRO__(0x5695, ## __VA_ARGS__), \
+ MACRO__(0x5698, ## __VA_ARGS__), \
+ MACRO__(0x56A5, ## __VA_ARGS__), \
+ MACRO__(0x56A6, ## __VA_ARGS__), \
+ MACRO__(0x56B0, ## __VA_ARGS__), \
+ MACRO__(0x56B1, ## __VA_ARGS__)
+
+#define XE_DG2_G12_IDS(MACRO__, ...) \
+ MACRO__(0x5696, ## __VA_ARGS__), \
+ MACRO__(0x5697, ## __VA_ARGS__), \
+ MACRO__(0x56A3, ## __VA_ARGS__), \
+ MACRO__(0x56A4, ## __VA_ARGS__), \
+ MACRO__(0x56B2, ## __VA_ARGS__), \
+ MACRO__(0x56B3, ## __VA_ARGS__)
+
+#define XE_DG2_IDS(MACRO__, ...) \
+ XE_DG2_G10_IDS(MACRO__, ## __VA_ARGS__),\
+ XE_DG2_G11_IDS(MACRO__, ## __VA_ARGS__),\
+ XE_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
+
+#define XE_ATS_M150_IDS(MACRO__, ...) \
+ MACRO__(0x56C0, ## __VA_ARGS__)
+
+#define XE_ATS_M75_IDS(MACRO__, ...) \
+ MACRO__(0x56C1, ## __VA_ARGS__)
+
+#define XE_ATS_M_IDS(MACRO__, ...) \
+ XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\
+ XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
+
+/* PVC */
+#define XE_PVC_XT_IDS(MACRO__, ...) \
+ MACRO__(0x0BD5, ## __VA_ARGS__), \
+ MACRO__(0x0BD6, ## __VA_ARGS__), \
+ MACRO__(0x0BD7, ## __VA_ARGS__), \
+ MACRO__(0x0BD8, ## __VA_ARGS__), \
+ MACRO__(0x0BD9, ## __VA_ARGS__), \
+ MACRO__(0x0BDA, ## __VA_ARGS__), \
+ MACRO__(0x0BDB, ## __VA_ARGS__), \
+ MACRO__(0x0BE0, ## __VA_ARGS__), \
+ MACRO__(0x0BE1, ## __VA_ARGS__), \
+ MACRO__(0x0BE5, ## __VA_ARGS__)
+
+#define XE_PVC_IDS(MACRO__, ...) \
+ XE_PVC_XT_IDS(MACRO__, ## __VA_ARGS__)
+
+/* MTL */
+#define XE_MTL_M_IDS(MACRO__, ...) \
+ MACRO__(0x7D40, ## __VA_ARGS__), \
+ MACRO__(0x7D43, ## __VA_ARGS__), \
+ MACRO__(0x7DC0, ## __VA_ARGS__)
+
+#define XE_MTL_P_IDS(MACRO__, ...) \
+ MACRO__(0x7D45, ## __VA_ARGS__), \
+ MACRO__(0x7D47, ## __VA_ARGS__), \
+ MACRO__(0x7D50, ## __VA_ARGS__), \
+ MACRO__(0x7D55, ## __VA_ARGS__), \
+ MACRO__(0x7DC5, ## __VA_ARGS__), \
+ MACRO__(0x7DD0, ## __VA_ARGS__), \
+ MACRO__(0x7DD5, ## __VA_ARGS__)
+
+#define XE_MTL_S_IDS(MACRO__, ...) \
+ MACRO__(0x7D60, ## __VA_ARGS__), \
+ MACRO__(0x7DE0, ## __VA_ARGS__)
+
+#define XE_ARL_IDS(MACRO__, ...) \
+ MACRO__(0x7D67, ## __VA_ARGS__)
+
+#define XE_MTL_IDS(MACRO__, ...) \
+ XE_MTL_M_IDS(MACRO__, ## __VA_ARGS__), \
+ XE_MTL_P_IDS(MACRO__, ## __VA_ARGS__), \
+ XE_MTL_S_IDS(MACRO__, ## __VA_ARGS__), \
+ XE_ARL_IDS(MACRO__, ## __VA_ARGS__)
+
+#define XE_LNL_IDS(MACRO__, ...) \
+ MACRO__(0x6420, ## __VA_ARGS__), \
+ MACRO__(0x64A0, ## __VA_ARGS__), \
+ MACRO__(0x64B0, ## __VA_ARGS__)
+
+#endif
--
2.40.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [igt-dev] [PATCH igt 1/4] lib: Add xe_pciids.h
@ 2023-08-29 14:11 ` Lucas De Marchi
0 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-08-29 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: Lucas De Marchi, intel-xe
With the introduction of Lunar Lake, igt won't be able to just re-use
i915_pciids.h for both drivers anymore since the support for LNL is only
coming with the xe module. Copy xe_pciids.h from the drm-xe-next branch
(up to commit b9c9020fc816 ("drm/xe/pvc: Use fast copy engines as
migrate engine on PVC") and start including it where needed. This brings
all the LNL PCI IDs.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
docs/reference/igt-gpu-tools/meson.build | 1 +
lib/intel_device_info.c | 1 +
lib/xe_pciids.h | 215 +++++++++++++++++++++++
3 files changed, 217 insertions(+)
create mode 100644 lib/xe_pciids.h
diff --git a/docs/reference/igt-gpu-tools/meson.build b/docs/reference/igt-gpu-tools/meson.build
index 6b832ad27..513385b4b 100644
--- a/docs/reference/igt-gpu-tools/meson.build
+++ b/docs/reference/igt-gpu-tools/meson.build
@@ -21,6 +21,7 @@ ignore_headers = [
'media_fill_gen9.h',
'gen9_render.h',
'version.h',
+ 'xe_pciids.h',
]
test_groups = [
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 2c9a45b68..5d53d2906 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -1,6 +1,7 @@
#include "intel_chipset.h"
#include "i915_pciids.h"
#include "i915_pciids_local.h"
+#include "xe_pciids.h"
#include <strings.h> /* ffs() */
diff --git a/lib/xe_pciids.h b/lib/xe_pciids.h
new file mode 100644
index 000000000..29f07a00a
--- /dev/null
+++ b/lib/xe_pciids.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef _XE_PCIIDS_H_
+#define _XE_PCIIDS_H_
+
+/*
+ * Lists below can be turned into initializers for a struct pci_device_id
+ * by defining INTEL_VGA_DEVICE:
+ *
+ * #define INTEL_VGA_DEVICE(id, info) { \
+ * 0x8086, id, \
+ * ~0, ~0, \
+ * 0x030000, 0xff0000, \
+ * (unsigned long) info }
+ *
+ * And then calling like:
+ *
+ * XE_TGL_12_GT1_IDS(INTEL_VGA_DEVICE, ## __VA_ARGS__)
+ *
+ * To turn them into something else, just provide a different macro passed as
+ * first argument.
+ */
+
+/* TGL */
+#define XE_TGL_GT1_IDS(MACRO__, ...) \
+ MACRO__(0x9A60, ## __VA_ARGS__), \
+ MACRO__(0x9A68, ## __VA_ARGS__), \
+ MACRO__(0x9A70, ## __VA_ARGS__)
+
+#define XE_TGL_GT2_IDS(MACRO__, ...) \
+ MACRO__(0x9A40, ## __VA_ARGS__), \
+ MACRO__(0x9A49, ## __VA_ARGS__), \
+ MACRO__(0x9A59, ## __VA_ARGS__), \
+ MACRO__(0x9A78, ## __VA_ARGS__), \
+ MACRO__(0x9AC0, ## __VA_ARGS__), \
+ MACRO__(0x9AC9, ## __VA_ARGS__), \
+ MACRO__(0x9AD9, ## __VA_ARGS__), \
+ MACRO__(0x9AF8, ## __VA_ARGS__)
+
+#define XE_TGL_IDS(MACRO__, ...) \
+ XE_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__),\
+ XE_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
+
+/* RKL */
+#define XE_RKL_IDS(MACRO__, ...) \
+ MACRO__(0x4C80, ## __VA_ARGS__), \
+ MACRO__(0x4C8A, ## __VA_ARGS__), \
+ MACRO__(0x4C8B, ## __VA_ARGS__), \
+ MACRO__(0x4C8C, ## __VA_ARGS__), \
+ MACRO__(0x4C90, ## __VA_ARGS__), \
+ MACRO__(0x4C9A, ## __VA_ARGS__)
+
+/* DG1 */
+#define XE_DG1_IDS(MACRO__, ...) \
+ MACRO__(0x4905, ## __VA_ARGS__), \
+ MACRO__(0x4906, ## __VA_ARGS__), \
+ MACRO__(0x4907, ## __VA_ARGS__), \
+ MACRO__(0x4908, ## __VA_ARGS__), \
+ MACRO__(0x4909, ## __VA_ARGS__)
+
+/* ADL-S */
+#define XE_ADLS_IDS(MACRO__, ...) \
+ MACRO__(0x4680, ## __VA_ARGS__), \
+ MACRO__(0x4682, ## __VA_ARGS__), \
+ MACRO__(0x4688, ## __VA_ARGS__), \
+ MACRO__(0x468A, ## __VA_ARGS__), \
+ MACRO__(0x4690, ## __VA_ARGS__), \
+ MACRO__(0x4692, ## __VA_ARGS__), \
+ MACRO__(0x4693, ## __VA_ARGS__)
+
+/* ADL-P */
+#define XE_ADLP_IDS(MACRO__, ...) \
+ MACRO__(0x46A0, ## __VA_ARGS__), \
+ MACRO__(0x46A1, ## __VA_ARGS__), \
+ MACRO__(0x46A2, ## __VA_ARGS__), \
+ MACRO__(0x46A3, ## __VA_ARGS__), \
+ MACRO__(0x46A6, ## __VA_ARGS__), \
+ MACRO__(0x46A8, ## __VA_ARGS__), \
+ MACRO__(0x46AA, ## __VA_ARGS__), \
+ MACRO__(0x462A, ## __VA_ARGS__), \
+ MACRO__(0x4626, ## __VA_ARGS__), \
+ MACRO__(0x4628, ## __VA_ARGS__), \
+ MACRO__(0x46B0, ## __VA_ARGS__), \
+ MACRO__(0x46B1, ## __VA_ARGS__), \
+ MACRO__(0x46B2, ## __VA_ARGS__), \
+ MACRO__(0x46B3, ## __VA_ARGS__), \
+ MACRO__(0x46C0, ## __VA_ARGS__), \
+ MACRO__(0x46C1, ## __VA_ARGS__), \
+ MACRO__(0x46C2, ## __VA_ARGS__), \
+ MACRO__(0x46C3, ## __VA_ARGS__)
+
+/* ADL-N */
+#define XE_ADLN_IDS(MACRO__, ...) \
+ MACRO__(0x46D0, ## __VA_ARGS__), \
+ MACRO__(0x46D1, ## __VA_ARGS__), \
+ MACRO__(0x46D2, ## __VA_ARGS__)
+
+/* RPL-S */
+#define XE_RPLS_IDS(MACRO__, ...) \
+ MACRO__(0xA780, ## __VA_ARGS__), \
+ MACRO__(0xA781, ## __VA_ARGS__), \
+ MACRO__(0xA782, ## __VA_ARGS__), \
+ MACRO__(0xA783, ## __VA_ARGS__), \
+ MACRO__(0xA788, ## __VA_ARGS__), \
+ MACRO__(0xA789, ## __VA_ARGS__), \
+ MACRO__(0xA78A, ## __VA_ARGS__), \
+ MACRO__(0xA78B, ## __VA_ARGS__)
+
+/* RPL-U */
+#define XE_RPLU_IDS(MACRO__, ...) \
+ MACRO__(0xA721, ## __VA_ARGS__), \
+ MACRO__(0xA7A1, ## __VA_ARGS__), \
+ MACRO__(0xA7A9, ## __VA_ARGS__)
+
+/* RPL-P */
+#define XE_RPLP_IDS(MACRO__, ...) \
+ MACRO__(0xA720, ## __VA_ARGS__), \
+ MACRO__(0xA7A0, ## __VA_ARGS__), \
+ MACRO__(0xA7A8, ## __VA_ARGS__)
+
+/* DG2 */
+#define XE_DG2_G10_IDS(MACRO__, ...) \
+ MACRO__(0x5690, ## __VA_ARGS__), \
+ MACRO__(0x5691, ## __VA_ARGS__), \
+ MACRO__(0x5692, ## __VA_ARGS__), \
+ MACRO__(0x56A0, ## __VA_ARGS__), \
+ MACRO__(0x56A1, ## __VA_ARGS__), \
+ MACRO__(0x56A2, ## __VA_ARGS__)
+
+#define XE_DG2_G11_IDS(MACRO__, ...) \
+ MACRO__(0x5693, ## __VA_ARGS__), \
+ MACRO__(0x5694, ## __VA_ARGS__), \
+ MACRO__(0x5695, ## __VA_ARGS__), \
+ MACRO__(0x5698, ## __VA_ARGS__), \
+ MACRO__(0x56A5, ## __VA_ARGS__), \
+ MACRO__(0x56A6, ## __VA_ARGS__), \
+ MACRO__(0x56B0, ## __VA_ARGS__), \
+ MACRO__(0x56B1, ## __VA_ARGS__)
+
+#define XE_DG2_G12_IDS(MACRO__, ...) \
+ MACRO__(0x5696, ## __VA_ARGS__), \
+ MACRO__(0x5697, ## __VA_ARGS__), \
+ MACRO__(0x56A3, ## __VA_ARGS__), \
+ MACRO__(0x56A4, ## __VA_ARGS__), \
+ MACRO__(0x56B2, ## __VA_ARGS__), \
+ MACRO__(0x56B3, ## __VA_ARGS__)
+
+#define XE_DG2_IDS(MACRO__, ...) \
+ XE_DG2_G10_IDS(MACRO__, ## __VA_ARGS__),\
+ XE_DG2_G11_IDS(MACRO__, ## __VA_ARGS__),\
+ XE_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
+
+#define XE_ATS_M150_IDS(MACRO__, ...) \
+ MACRO__(0x56C0, ## __VA_ARGS__)
+
+#define XE_ATS_M75_IDS(MACRO__, ...) \
+ MACRO__(0x56C1, ## __VA_ARGS__)
+
+#define XE_ATS_M_IDS(MACRO__, ...) \
+ XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\
+ XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
+
+/* PVC */
+#define XE_PVC_XT_IDS(MACRO__, ...) \
+ MACRO__(0x0BD5, ## __VA_ARGS__), \
+ MACRO__(0x0BD6, ## __VA_ARGS__), \
+ MACRO__(0x0BD7, ## __VA_ARGS__), \
+ MACRO__(0x0BD8, ## __VA_ARGS__), \
+ MACRO__(0x0BD9, ## __VA_ARGS__), \
+ MACRO__(0x0BDA, ## __VA_ARGS__), \
+ MACRO__(0x0BDB, ## __VA_ARGS__), \
+ MACRO__(0x0BE0, ## __VA_ARGS__), \
+ MACRO__(0x0BE1, ## __VA_ARGS__), \
+ MACRO__(0x0BE5, ## __VA_ARGS__)
+
+#define XE_PVC_IDS(MACRO__, ...) \
+ XE_PVC_XT_IDS(MACRO__, ## __VA_ARGS__)
+
+/* MTL */
+#define XE_MTL_M_IDS(MACRO__, ...) \
+ MACRO__(0x7D40, ## __VA_ARGS__), \
+ MACRO__(0x7D43, ## __VA_ARGS__), \
+ MACRO__(0x7DC0, ## __VA_ARGS__)
+
+#define XE_MTL_P_IDS(MACRO__, ...) \
+ MACRO__(0x7D45, ## __VA_ARGS__), \
+ MACRO__(0x7D47, ## __VA_ARGS__), \
+ MACRO__(0x7D50, ## __VA_ARGS__), \
+ MACRO__(0x7D55, ## __VA_ARGS__), \
+ MACRO__(0x7DC5, ## __VA_ARGS__), \
+ MACRO__(0x7DD0, ## __VA_ARGS__), \
+ MACRO__(0x7DD5, ## __VA_ARGS__)
+
+#define XE_MTL_S_IDS(MACRO__, ...) \
+ MACRO__(0x7D60, ## __VA_ARGS__), \
+ MACRO__(0x7DE0, ## __VA_ARGS__)
+
+#define XE_ARL_IDS(MACRO__, ...) \
+ MACRO__(0x7D67, ## __VA_ARGS__)
+
+#define XE_MTL_IDS(MACRO__, ...) \
+ XE_MTL_M_IDS(MACRO__, ## __VA_ARGS__), \
+ XE_MTL_P_IDS(MACRO__, ## __VA_ARGS__), \
+ XE_MTL_S_IDS(MACRO__, ## __VA_ARGS__), \
+ XE_ARL_IDS(MACRO__, ## __VA_ARGS__)
+
+#define XE_LNL_IDS(MACRO__, ...) \
+ MACRO__(0x6420, ## __VA_ARGS__), \
+ MACRO__(0x64A0, ## __VA_ARGS__), \
+ MACRO__(0x64B0, ## __VA_ARGS__)
+
+#endif
--
2.40.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-xe] [PATCH igt 2/4] lib/intel_chipset: Add Lunar Lake support
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
@ 2023-08-29 14:11 ` Lucas De Marchi
-1 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-08-29 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: Lucas De Marchi, intel-xe, Swati Sharma
Add basic definition for the Lunar Lake platform. This uses the PCI ID
from the xe_pciids.h which has a macro in a slighlty different form.
Going forward we could also trim down a little bit the the info struct
like was done in the kernel, relying on gmdid and IP version checks.
This is left for later.
Cc: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
lib/intel_chipset.h | 5 +++++
lib/intel_device_info.c | 12 ++++++++++++
2 files changed, 17 insertions(+)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 84cf1799e..52b15ccea 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -46,6 +46,7 @@ struct intel_device_info {
bool has_4tile : 1;
bool has_flatccs : 1;
bool has_oam : 1;
+ bool has_gmdid : 1;
bool is_mobile : 1;
bool is_whitney : 1;
bool is_almador : 1;
@@ -90,6 +91,7 @@ struct intel_device_info {
bool is_alderlake_n : 1;
bool is_meteorlake : 1;
bool is_pontevecchio : 1;
+ bool is_lunarlake : 1;
const struct intel_cmds_info *cmds_info;
const char *codename;
};
@@ -203,6 +205,7 @@ void intel_check_pch(void);
#define IS_ALDERLAKE_N(devid) (intel_get_device_info(devid)->is_alderlake_n)
#define IS_METEORLAKE(devid) (intel_get_device_info(devid)->is_meteorlake)
#define IS_PONTEVECCHIO(devid) (intel_get_device_info(devid)->is_pontevecchio)
+#define IS_LUNARLAKE(devid) (intel_get_device_info(devid)->is_lunarlake)
#define IS_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver == x)
#define AT_LEAST_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver >= x)
@@ -236,4 +239,6 @@ void intel_check_pch(void);
#define HAS_OAM(devid) (intel_get_device_info(devid)->has_oam)
+#define HAS_GMDID(devid) (intel_get_device_info(devid)->has_gmdid)
+
#endif /* _INTEL_CHIPSET_H */
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 5d53d2906..86a8b3650 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -504,6 +504,16 @@ static const struct intel_device_info intel_pontevecchio_info = {
.cmds_info = &gen12_pvc_cmds_info,
};
+static const struct intel_device_info intel_lunarlake_info = {
+ .graphics_ver = 20,
+ .graphics_rel = 4,
+ .display_ver = 20,
+ .has_4tile = true,
+ .has_gmdid = true,
+ .is_lunarlake = true,
+ .codename = "lunarlake"
+};
+
static const struct pci_id_match intel_device_match[] = {
INTEL_I810_IDS(&intel_i810_info),
INTEL_I815_IDS(&intel_i815_info),
@@ -607,6 +617,8 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_PVC_IDS(&intel_pontevecchio_info),
+ XE_LNL_IDS(INTEL_VGA_DEVICE, &intel_lunarlake_info),
+
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
};
--
2.40.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [igt-dev] [PATCH igt 2/4] lib/intel_chipset: Add Lunar Lake support
@ 2023-08-29 14:11 ` Lucas De Marchi
0 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-08-29 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: Lucas De Marchi, intel-xe
Add basic definition for the Lunar Lake platform. This uses the PCI ID
from the xe_pciids.h which has a macro in a slighlty different form.
Going forward we could also trim down a little bit the the info struct
like was done in the kernel, relying on gmdid and IP version checks.
This is left for later.
Cc: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
lib/intel_chipset.h | 5 +++++
lib/intel_device_info.c | 12 ++++++++++++
2 files changed, 17 insertions(+)
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index 84cf1799e..52b15ccea 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -46,6 +46,7 @@ struct intel_device_info {
bool has_4tile : 1;
bool has_flatccs : 1;
bool has_oam : 1;
+ bool has_gmdid : 1;
bool is_mobile : 1;
bool is_whitney : 1;
bool is_almador : 1;
@@ -90,6 +91,7 @@ struct intel_device_info {
bool is_alderlake_n : 1;
bool is_meteorlake : 1;
bool is_pontevecchio : 1;
+ bool is_lunarlake : 1;
const struct intel_cmds_info *cmds_info;
const char *codename;
};
@@ -203,6 +205,7 @@ void intel_check_pch(void);
#define IS_ALDERLAKE_N(devid) (intel_get_device_info(devid)->is_alderlake_n)
#define IS_METEORLAKE(devid) (intel_get_device_info(devid)->is_meteorlake)
#define IS_PONTEVECCHIO(devid) (intel_get_device_info(devid)->is_pontevecchio)
+#define IS_LUNARLAKE(devid) (intel_get_device_info(devid)->is_lunarlake)
#define IS_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver == x)
#define AT_LEAST_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver >= x)
@@ -236,4 +239,6 @@ void intel_check_pch(void);
#define HAS_OAM(devid) (intel_get_device_info(devid)->has_oam)
+#define HAS_GMDID(devid) (intel_get_device_info(devid)->has_gmdid)
+
#endif /* _INTEL_CHIPSET_H */
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 5d53d2906..86a8b3650 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -504,6 +504,16 @@ static const struct intel_device_info intel_pontevecchio_info = {
.cmds_info = &gen12_pvc_cmds_info,
};
+static const struct intel_device_info intel_lunarlake_info = {
+ .graphics_ver = 20,
+ .graphics_rel = 4,
+ .display_ver = 20,
+ .has_4tile = true,
+ .has_gmdid = true,
+ .is_lunarlake = true,
+ .codename = "lunarlake"
+};
+
static const struct pci_id_match intel_device_match[] = {
INTEL_I810_IDS(&intel_i810_info),
INTEL_I815_IDS(&intel_i815_info),
@@ -607,6 +617,8 @@ static const struct pci_id_match intel_device_match[] = {
INTEL_PVC_IDS(&intel_pontevecchio_info),
+ XE_LNL_IDS(INTEL_VGA_DEVICE, &intel_lunarlake_info),
+
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
};
--
2.40.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-xe] [PATCH igt 3/4] lib/intel_device_info: Add blitter cmd info for Lunar Lake
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
@ 2023-08-29 14:11 ` Lucas De Marchi
-1 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-08-29 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: Lucas De Marchi, intel-xe, Swati Sharma
From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Add separate cmd info for LunarLake. This re-uses the commands for PVC
since all the commands being used in IGT match the ones for PVC.
Cc: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
lib/intel_device_info.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 86a8b3650..d1c268482 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -511,7 +511,8 @@ static const struct intel_device_info intel_lunarlake_info = {
.has_4tile = true,
.has_gmdid = true,
.is_lunarlake = true,
- .codename = "lunarlake"
+ .codename = "lunarlake",
+ .cmds_info = &gen12_pvc_cmds_info,
};
static const struct pci_id_match intel_device_match[] = {
--
2.40.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [igt-dev] [PATCH igt 3/4] lib/intel_device_info: Add blitter cmd info for Lunar Lake
@ 2023-08-29 14:11 ` Lucas De Marchi
0 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-08-29 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: Lucas De Marchi, intel-xe
From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Add separate cmd info for LunarLake. This re-uses the commands for PVC
since all the commands being used in IGT match the ones for PVC.
Cc: Swati Sharma <swati2.sharma@intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
lib/intel_device_info.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
index 86a8b3650..d1c268482 100644
--- a/lib/intel_device_info.c
+++ b/lib/intel_device_info.c
@@ -511,7 +511,8 @@ static const struct intel_device_info intel_lunarlake_info = {
.has_4tile = true,
.has_gmdid = true,
.is_lunarlake = true,
- .codename = "lunarlake"
+ .codename = "lunarlake",
+ .cmds_info = &gen12_pvc_cmds_info,
};
static const struct pci_id_match intel_device_match[] = {
--
2.40.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Intel-xe] [PATCH igt 4/4] tests/xe_debugfs: skip page table level check for Xe2
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
@ 2023-08-29 14:11 ` Lucas De Marchi
-1 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-08-29 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: Janga Rahul Kumar, Lucas De Marchi, intel-xe
From: Janga Rahul Kumar <janga.rahul.kumar@intel.com>
Starting with Xe2, a 5-level page table is always used, regardless of
the actual virtual address range supported by the platform. Do not
depend on VA range to configure max page table level.
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: Janga Rahul Kumar <janga.rahul.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
tests/xe/xe_debugfs.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/tests/xe/xe_debugfs.c b/tests/xe/xe_debugfs.c
index e51d03661..72c069bfc 100644
--- a/tests/xe/xe_debugfs.c
+++ b/tests/xe/xe_debugfs.c
@@ -74,6 +74,7 @@ static int validate_entries(int fd, const char *add_path, const char * const str
static void
test_base(int fd, struct drm_xe_query_config *config)
{
+ uint16_t devid = intel_get_drm_devid(fd);
static const char * const expected_files[] = {
"gt0",
"gt1",
@@ -86,7 +87,6 @@ test_base(int fd, struct drm_xe_query_config *config)
"clients",
"name"
};
-
char reference[4096];
int val = 0;
@@ -104,16 +104,19 @@ test_base(int fd, struct drm_xe_query_config *config)
igt_assert(igt_debugfs_search(fd, "info", reference));
- switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
- case 48:
- val = 3;
- break;
- case 57:
- val = 4;
- break;
+ if (!AT_LEAST_GEN(devid, 20)) {
+ switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
+ case 48:
+ val = 3;
+ break;
+ case 57:
+ val = 4;
+ break;
+ }
+
+ sprintf(reference, "vm_max_level %d", val);
+ igt_assert(igt_debugfs_search(fd, "info", reference));
}
- sprintf(reference, "vm_max_level %d", val);
- igt_assert(igt_debugfs_search(fd, "info", reference));
igt_assert(igt_debugfs_exists(fd, "gt0", O_RDONLY));
if (config->info[XE_QUERY_CONFIG_GT_COUNT] > 1)
--
2.40.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [igt-dev] [PATCH igt 4/4] tests/xe_debugfs: skip page table level check for Xe2
@ 2023-08-29 14:11 ` Lucas De Marchi
0 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-08-29 14:11 UTC (permalink / raw)
To: igt-dev; +Cc: Lucas De Marchi, intel-xe
From: Janga Rahul Kumar <janga.rahul.kumar@intel.com>
Starting with Xe2, a 5-level page table is always used, regardless of
the actual virtual address range supported by the platform. Do not
depend on VA range to configure max page table level.
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: Janga Rahul Kumar <janga.rahul.kumar@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
tests/xe/xe_debugfs.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/tests/xe/xe_debugfs.c b/tests/xe/xe_debugfs.c
index e51d03661..72c069bfc 100644
--- a/tests/xe/xe_debugfs.c
+++ b/tests/xe/xe_debugfs.c
@@ -74,6 +74,7 @@ static int validate_entries(int fd, const char *add_path, const char * const str
static void
test_base(int fd, struct drm_xe_query_config *config)
{
+ uint16_t devid = intel_get_drm_devid(fd);
static const char * const expected_files[] = {
"gt0",
"gt1",
@@ -86,7 +87,6 @@ test_base(int fd, struct drm_xe_query_config *config)
"clients",
"name"
};
-
char reference[4096];
int val = 0;
@@ -104,16 +104,19 @@ test_base(int fd, struct drm_xe_query_config *config)
igt_assert(igt_debugfs_search(fd, "info", reference));
- switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
- case 48:
- val = 3;
- break;
- case 57:
- val = 4;
- break;
+ if (!AT_LEAST_GEN(devid, 20)) {
+ switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
+ case 48:
+ val = 3;
+ break;
+ case 57:
+ val = 4;
+ break;
+ }
+
+ sprintf(reference, "vm_max_level %d", val);
+ igt_assert(igt_debugfs_search(fd, "info", reference));
}
- sprintf(reference, "vm_max_level %d", val);
- igt_assert(igt_debugfs_search(fd, "info", reference));
igt_assert(igt_debugfs_exists(fd, "gt0", O_RDONLY));
if (config->info[XE_QUERY_CONFIG_GT_COUNT] > 1)
--
2.40.1
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [igt-dev] ✗ GitLab.Pipeline: warning for Add LNL support to xe tests
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
` (4 preceding siblings ...)
(?)
@ 2023-08-29 14:26 ` Patchwork
-1 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2023-08-29 14:26 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: igt-dev
== Series Details ==
Series: Add LNL support to xe tests
URL : https://patchwork.freedesktop.org/series/123016/
State : warning
== Summary ==
Pipeline status: FAILED.
see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/972546 for the overview.
build-containers:build-debian has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48164094):
time="2023-08-29T14:21:56Z" level=fatal msg="Invalid status code returned when fetching blob 404 (Not Found)"
Building!
STEP 1: FROM debian:buster
Getting image source signatures
Copying blob sha256:d6b7393fb4f375905c31c483d81ce2a2905f88aba8cb198874da2b54035bc41d
Copying config sha256:de08540e8ff0e470ff7956df4bed403725a5f45c186e9bf495da5344ff8fbe84
Writing manifest to image destination
Storing signatures
STEP 2: RUN apt-get update
error running container: error creating container for [/bin/sh -c apt-get update]: time="2023-08-29T14:22:00Z" level=warning msg="signal: killed"
time="2023-08-29T14:22:00Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
: exit status 1
Error: error building at STEP "RUN apt-get update": error while running runtime: exit status 1
section_end:1693318921:step_script
section_start:1693318921:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1693318921:cleanup_file_variables
ERROR: Job failed: exit code 1
build-containers:build-debian-arm64 has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48164096):
time="2023-08-29T14:21:57Z" level=fatal msg="Invalid status code returned when fetching blob 404 (Not Found)"
Building!
STEP 1: FROM debian:buster
Getting image source signatures
Copying blob sha256:d6b7393fb4f375905c31c483d81ce2a2905f88aba8cb198874da2b54035bc41d
Copying config sha256:de08540e8ff0e470ff7956df4bed403725a5f45c186e9bf495da5344ff8fbe84
Writing manifest to image destination
Storing signatures
STEP 2: RUN apt-get update
error running container: error creating container for [/bin/sh -c apt-get update]: time="2023-08-29T14:22:01Z" level=warning msg="signal: killed"
time="2023-08-29T14:22:01Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
: exit status 1
Error: error building at STEP "RUN apt-get update": error while running runtime: exit status 1
section_end:1693318922:step_script
section_start:1693318922:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1693318922:cleanup_file_variables
ERROR: Job failed: exit code 1
build-containers:build-debian-armhf has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48164095):
time="2023-08-29T14:21:57Z" level=fatal msg="Invalid status code returned when fetching blob 404 (Not Found)"
Building!
STEP 1: FROM debian:buster
Getting image source signatures
Copying blob sha256:d6b7393fb4f375905c31c483d81ce2a2905f88aba8cb198874da2b54035bc41d
Copying config sha256:de08540e8ff0e470ff7956df4bed403725a5f45c186e9bf495da5344ff8fbe84
Writing manifest to image destination
Storing signatures
STEP 2: RUN apt-get update
error running container: error creating container for [/bin/sh -c apt-get update]: time="2023-08-29T14:22:01Z" level=warning msg="signal: killed"
time="2023-08-29T14:22:01Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
: exit status 1
Error: error building at STEP "RUN apt-get update": error while running runtime: exit status 1
section_end:1693318922:step_script
section_start:1693318922:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1693318922:cleanup_file_variables
ERROR: Job failed: exit code 1
build-containers:build-debian-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48164097):
time="2023-08-29T14:21:57Z" level=fatal msg="Invalid status code returned when fetching blob 404 (Not Found)"
Building!
STEP 1: FROM debian:buster
Getting image source signatures
Copying blob sha256:d6b7393fb4f375905c31c483d81ce2a2905f88aba8cb198874da2b54035bc41d
Copying config sha256:de08540e8ff0e470ff7956df4bed403725a5f45c186e9bf495da5344ff8fbe84
Writing manifest to image destination
Storing signatures
STEP 2: RUN apt-get update
error running container: error creating container for [/bin/sh -c apt-get update]: time="2023-08-29T14:22:02Z" level=warning msg="signal: killed"
time="2023-08-29T14:22:02Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
: exit status 1
Error: error building at STEP "RUN apt-get update": error while running runtime: exit status 1
section_end:1693318922:step_script
section_start:1693318922:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1693318923:cleanup_file_variables
ERROR: Job failed: exit code 1
build-containers:build-fedora has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/48164098):
time="2023-08-29T14:21:57Z" level=fatal msg="Invalid status code returned when fetching blob 404 (Not Found)"
Building!
STEP 1: FROM fedora:31
Getting image source signatures
Copying blob sha256:854946d575a439a894349addd141568875d7c1e673d3286b08250f3dde002e6a
Copying config sha256:7e94ed77b448a8d2ff08b92d3ca743e4e862c744892d6886c73487581eb5863a
Writing manifest to image destination
Storing signatures
STEP 2: RUN dnf install -y gcc flex bison libatomic meson ninja-build xdotool 'pkgconfig(libdrm)' 'pkgconfig(pciaccess)' 'pkgconfig(libkmod)' 'pkgconfig(libprocps)' 'pkgconfig(libunwind)' 'pkgconfig(libdw)' 'pkgconfig(pixman-1)' 'pkgconfig(valgrind)' 'pkgconfig(cairo)' 'pkgconfig(libudev)' 'pkgconfig(glib-2.0)' 'pkgconfig(gsl)' 'pkgconfig(alsa)' 'pkgconfig(xmlrpc)' 'pkgconfig(xmlrpc_util)' 'pkgconfig(xmlrpc_client)' 'pkgconfig(json-c)' 'pkgconfig(gtk-doc)' 'pkgconfig(xv)' 'pkgconfig(xrandr)' python3-docutils
error running container: error creating container for [/bin/sh -c dnf install -y gcc flex bison libatomic meson ninja-build xdotool 'pkgconfig(libdrm)' 'pkgconfig(pciaccess)' 'pkgconfig(libkmod)' 'pkgconfig(libprocps)' 'pkgconfig(libunwind)' 'pkgconfig(libdw)' 'pkgconfig(pixman-1)' 'pkgconfig(valgrind)' 'pkgconfig(cairo)' 'pkgconfig(libudev)' 'pkgconfig(glib-2.0)' 'pkgconfig(gsl)' 'pkgconfig(alsa)' 'pkgconfig(xmlrpc)' 'pkgconfig(xmlrpc_util)' 'pkgconfig(xmlrpc_client)' 'pkgconfig(json-c)' 'pkgconfig(gtk-doc)' 'pkgconfig(xv)' 'pkgconfig(xrandr)' python3-docutils]: time="2023-08-29T14:22:03Z" level=warning msg="signal: killed"
time="2023-08-29T14:22:03Z" level=error msg="container_linux.go:346: starting container process caused \"process_linux.go:297: applying cgroup configuration for process caused \\\"mountpoint for cgroup not found\\\"\"\n"
container_linux.go:346: starting container process caused "process_linux.go:297: applying cgroup configuration for process caused \"mountpoint for cgroup not found\""
: exit status 1
Error: error building at STEP "RUN dnf install -y gcc flex bison libatomic meson ninja-build xdotool 'pkgconfig(libdrm)' 'pkgconfig(pciaccess)' 'pkgconfig(libkmod)' 'pkgconfig(libprocps)' 'pkgconfig(libunwind)' 'pkgconfig(libdw)' 'pkgconfig(pixman-1)' 'pkgconfig(valgrind)' 'pkgconfig(cairo)' 'pkgconfig(libudev)' 'pkgconfig(glib-2.0)' 'pkgconfig(gsl)' 'pkgconfig(alsa)' 'pkgconfig(xmlrpc)' 'pkgconfig(xmlrpc_util)' 'pkgconfig(xmlrpc_client)' 'pkgconfig(json-c)' 'pkgconfig(gtk-doc)' 'pkgconfig(xv)' 'pkgconfig(xrandr)' python3-docutils": error while running runtime: exit status 1
section_end:1693318923:step_script
section_start:1693318923:cleanup_file_variables
Cleaning up project directory and file based variables
section_end:1693318924:cleanup_file_variables
ERROR: Job failed: exit code 1
== Logs ==
For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/972546
^ permalink raw reply [flat|nested] 35+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for Add LNL support to xe tests
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
` (5 preceding siblings ...)
(?)
@ 2023-08-29 14:59 ` Patchwork
-1 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2023-08-29 14:59 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 4315 bytes --]
== Series Details ==
Series: Add LNL support to xe tests
URL : https://patchwork.freedesktop.org/series/123016/
State : success
== Summary ==
CI Bug Log - changes from IGT_7458 -> IGTPW_9679
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/index.html
Participating hosts (40 -> 38)
------------------------------
Missing (2): fi-kbl-soraka fi-snb-2520m
Known issues
------------
Here are the changes found in IGTPW_9679 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-rkl-11600: [PASS][1] -> [DMESG-FAIL][2] ([i915#5334] / [i915#7872])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/fi-rkl-11600/igt@i915_selftest@live@gt_heartbeat.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/fi-rkl-11600/igt@i915_selftest@live@gt_heartbeat.html
- fi-apl-guc: [PASS][3] -> [DMESG-FAIL][4] ([i915#5334])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- bat-mtlp-8: [PASS][5] -> [ABORT][6] ([i915#7982] / [i915#8865])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/bat-mtlp-8/igt@i915_selftest@live@requests.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/bat-mtlp-8/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#6645])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/bat-mtlp-6/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-mtlp-6: NOTRUN -> [SKIP][8] ([i915#1845] / [i915#4078])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/bat-mtlp-6/igt@kms_pipe_crc_basic@suspend-read-crc.html
#### Possible fixes ####
* igt@i915_selftest@live@requests:
- bat-mtlp-6: [ABORT][9] ([i915#7982] / [i915#8865]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/bat-mtlp-6/igt@i915_selftest@live@requests.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/bat-mtlp-6/igt@i915_selftest@live@requests.html
#### Warnings ####
* igt@kms_psr@cursor_plane_move:
- bat-rplp-1: [SKIP][11] ([i915#1072]) -> [ABORT][12] ([i915#8469] / [i915#8668])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/bat-rplp-1/igt@kms_psr@cursor_plane_move.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/bat-rplp-1/igt@kms_psr@cursor_plane_move.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#484]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/484
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4550]: https://gitlab.freedesktop.org/drm/intel/issues/4550
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7359]: https://gitlab.freedesktop.org/drm/intel/issues/7359
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7953]: https://gitlab.freedesktop.org/drm/intel/issues/7953
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8469]: https://gitlab.freedesktop.org/drm/intel/issues/8469
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7458 -> IGTPW_9679
CI-20190529: 20190529
CI_DRM_13573: cb94b8169f58bc821f95f5fd8f333074576f71ac @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9679: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/index.html
IGT_7458: 7458
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/index.html
[-- Attachment #2: Type: text/html, Size: 4982 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* [igt-dev] ✓ CI.xeBAT: success for Add LNL support to xe tests
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
` (6 preceding siblings ...)
(?)
@ 2023-08-29 15:26 ` Patchwork
-1 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2023-08-29 15:26 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 1272 bytes --]
== Series Details ==
Series: Add LNL support to xe tests
URL : https://patchwork.freedesktop.org/series/123016/
State : success
== Summary ==
CI Bug Log - changes from XEIGT_7458_BAT -> XEIGTPW_9679_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in XEIGTPW_9679_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- bat-adlp-7: [PASS][1] -> [FAIL][2] ([Intel XE#480]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/IGT_7458/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/IGTPW_9679/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480
Build changes
-------------
* IGT: IGT_7458 -> IGTPW_9679
IGTPW_9679: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/index.html
IGT_7458: 7458
xe-340-c77796cf84361b4716839141f2e48de2bf7f4bd5: c77796cf84361b4716839141f2e48de2bf7f4bd5
[-- Attachment #2: Type: text/html, Size: 1742 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Intel-xe] ✗ CI.Patch_applied: failure for Add LNL support to xe tests
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
` (7 preceding siblings ...)
(?)
@ 2023-08-29 15:28 ` Patchwork
-1 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2023-08-29 15:28 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-xe
== Series Details ==
Series: Add LNL support to xe tests
URL : https://patchwork.freedesktop.org/series/123015/
State : failure
== Summary ==
=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: d8c08057a drm/xe: Add patch version on guc firmware init
=== git am output follows ===
error: docs/reference/igt-gpu-tools/meson.build: does not exist in index
error: lib/intel_device_info.c: does not exist in index
hint: Use 'git am --show-current-patch' to see the failed patch
Applying: lib: Add xe_pciids.h
Patch failed at 0001 lib: Add xe_pciids.h
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 35+ messages in thread
* [igt-dev] ✗ Fi.CI.IGT: failure for Add LNL support to xe tests
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
` (8 preceding siblings ...)
(?)
@ 2023-08-29 21:38 ` Patchwork
-1 siblings, 0 replies; 35+ messages in thread
From: Patchwork @ 2023-08-29 21:38 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: igt-dev
[-- Attachment #1: Type: text/plain, Size: 82786 bytes --]
== Series Details ==
Series: Add LNL support to xe tests
URL : https://patchwork.freedesktop.org/series/123016/
State : failure
== Summary ==
CI Bug Log - changes from IGT_7458_full -> IGTPW_9679_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_9679_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_9679_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/index.html
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-tglu0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_9679_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_fence@basic-busy-all:
- shard-rkl: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-rkl-6/igt@gem_exec_fence@basic-busy-all.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-4/igt@gem_exec_fence@basic-busy-all.html
* igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][3] +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-15/igt@kms_dirtyfb@dirtyfb-ioctl@psr-hdmi-a-4.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-rkl: [PASS][4] -> [INCOMPLETE][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-rkl-2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
Known issues
------------
Here are the changes found in IGTPW_9679_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@cold-reset-bound:
- shard-dg2: NOTRUN -> [SKIP][6] ([i915#7701])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-10/igt@device_reset@cold-reset-bound.html
* igt@drm_buddy@drm_buddy_test:
- shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#8661])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-snb4/igt@drm_buddy@drm_buddy_test.html
* igt@drm_fdinfo@most-busy-check-all@bcs0:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#8414]) +20 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@drm_fdinfo@most-busy-check-all@bcs0.html
* igt@feature_discovery@chamelium:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#4854])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@feature_discovery@chamelium.html
- shard-rkl: NOTRUN -> [SKIP][10] ([fdo#111827]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@feature_discovery@chamelium.html
* igt@feature_discovery@display-3x:
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#1839])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-12/igt@feature_discovery@display-3x.html
* igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0:
- shard-dg2: NOTRUN -> [INCOMPLETE][12] ([i915#6311] / [i915#7297])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@gem_ccs@suspend-resume@tile4-compressed-compfmt0-smem-lmem0.html
* igt@gem_create@create-ext-set-pat:
- shard-dg2: NOTRUN -> [SKIP][13] ([i915#8562])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-1/igt@gem_create@create-ext-set-pat.html
- shard-rkl: NOTRUN -> [SKIP][14] ([i915#8562])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-1/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_param@set-priority-not-supported:
- shard-dg2: NOTRUN -> [SKIP][15] ([fdo#109314])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@gem_ctx_param@set-priority-not-supported.html
* igt@gem_ctx_persistence@heartbeat-close:
- shard-dg1: NOTRUN -> [SKIP][16] ([i915#8555])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-13/igt@gem_ctx_persistence@heartbeat-close.html
* igt@gem_ctx_persistence@heartbeat-hang:
- shard-dg2: NOTRUN -> [SKIP][17] ([i915#8555])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-10/igt@gem_ctx_persistence@heartbeat-hang.html
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1099]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-snb2/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_ctx_sseu@engines:
- shard-dg2: NOTRUN -> [SKIP][19] ([i915#280])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@gem_ctx_sseu@engines.html
* igt@gem_eio@in-flight-contexts-1us:
- shard-mtlp: [PASS][20] -> [ABORT][21] ([i915#8503])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-4/igt@gem_eio@in-flight-contexts-1us.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-1/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_balancer@bonded-pair:
- shard-dg2: NOTRUN -> [SKIP][22] ([i915#4771])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-10/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@bonded-true-hang:
- shard-dg2: NOTRUN -> [SKIP][23] ([i915#4812]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@gem_exec_balancer@bonded-true-hang.html
* igt@gem_exec_balancer@invalid-bonds:
- shard-dg2: NOTRUN -> [SKIP][24] ([i915#4036])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@gem_exec_balancer@invalid-bonds.html
* igt@gem_exec_endless@dispatch@ccs0:
- shard-mtlp: [PASS][25] -> [TIMEOUT][26] ([i915#7016])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-8/igt@gem_exec_endless@dispatch@ccs0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-4/igt@gem_exec_endless@dispatch@ccs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: [PASS][27] -> [FAIL][28] ([i915#2846])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-rkl-1/igt@gem_exec_fair@basic-deadline.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-tglu: NOTRUN -> [FAIL][29] ([i915#2842]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-6/igt@gem_exec_fair@basic-none-solo@rcs0.html
- shard-apl: [PASS][30] -> [FAIL][31] ([i915#2842])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none-vip:
- shard-dg1: NOTRUN -> [SKIP][32] ([i915#3539] / [i915#4852])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-18/igt@gem_exec_fair@basic-none-vip.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: NOTRUN -> [FAIL][33] ([i915#2842]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk8/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: NOTRUN -> [FAIL][34] ([i915#2842])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [PASS][35] -> [FAIL][36] ([i915#2842]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-glk4/igt@gem_exec_fair@basic-pace@rcs0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk8/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fence@parallel@vcs0:
- shard-mtlp: [PASS][37] -> [DMESG-FAIL][38] ([i915#9121])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-2/igt@gem_exec_fence@parallel@vcs0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-4/igt@gem_exec_fence@parallel@vcs0.html
* igt@gem_exec_fence@parallel@vecs0:
- shard-mtlp: [PASS][39] -> [FAIL][40] ([i915#8957]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-2/igt@gem_exec_fence@parallel@vecs0.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-4/igt@gem_exec_fence@parallel@vecs0.html
* igt@gem_exec_fence@submit67:
- shard-mtlp: NOTRUN -> [SKIP][41] ([i915#4812])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-4/igt@gem_exec_fence@submit67.html
* igt@gem_exec_flush@basic-uc-pro-default:
- shard-dg2: NOTRUN -> [SKIP][42] ([i915#3539] / [i915#4852]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-8/igt@gem_exec_flush@basic-uc-pro-default.html
* igt@gem_exec_flush@basic-uc-prw-default:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#3539]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@gem_exec_flush@basic-uc-prw-default.html
* igt@gem_exec_gttfill@multigpu-basic:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#7697]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@gem_exec_gttfill@multigpu-basic.html
* igt@gem_exec_params@secure-non-root:
- shard-dg2: NOTRUN -> [SKIP][45] ([fdo#112283])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-8/igt@gem_exec_params@secure-non-root.html
* igt@gem_exec_reloc@basic-cpu-wc-active:
- shard-mtlp: NOTRUN -> [SKIP][46] ([i915#3281]) +1 similar issue
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-1/igt@gem_exec_reloc@basic-cpu-wc-active.html
* igt@gem_exec_reloc@basic-gtt-wc:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#3281]) +8 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@gem_exec_reloc@basic-gtt-wc.html
- shard-rkl: NOTRUN -> [SKIP][48] ([i915#3281])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-wc.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain:
- shard-dg2: NOTRUN -> [SKIP][49] ([i915#4537] / [i915#4812])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@gem_exec_schedule@preempt-queue-contexts-chain.html
* igt@gem_exec_schedule@preemptive-hang@vcs0:
- shard-mtlp: NOTRUN -> [FAIL][50] ([i915#9051])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-1/igt@gem_exec_schedule@preemptive-hang@vcs0.html
* igt@gem_fence_thrash@bo-write-verify-threaded-none:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#4860])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@gem_fence_thrash@bo-write-verify-threaded-none.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-tglu: NOTRUN -> [SKIP][52] ([i915#4613])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-7/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-glk: NOTRUN -> [SKIP][53] ([fdo#109271] / [i915#4613])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk6/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
* igt@gem_mmap_gtt@coherency:
- shard-rkl: NOTRUN -> [SKIP][54] ([fdo#111656])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-2/igt@gem_mmap_gtt@coherency.html
* igt@gem_mmap_gtt@cpuset-big-copy-odd:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#4077]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-7/igt@gem_mmap_gtt@cpuset-big-copy-odd.html
* igt@gem_mmap_wc@write-read-distinct:
- shard-dg2: NOTRUN -> [SKIP][56] ([i915#4083]) +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@gem_mmap_wc@write-read-distinct.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#3282]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-7/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gem_pwrite@basic-exhaustion:
- shard-glk: NOTRUN -> [WARN][58] ([i915#2658])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk1/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_pxp@create-regular-context-1:
- shard-tglu: NOTRUN -> [SKIP][59] ([i915#4270])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-8/igt@gem_pxp@create-regular-context-1.html
* igt@gem_pxp@display-protected-crc:
- shard-mtlp: NOTRUN -> [SKIP][60] ([i915#4270])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-7/igt@gem_pxp@display-protected-crc.html
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-dg2: NOTRUN -> [SKIP][61] ([i915#4270]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-8/igt@gem_pxp@regular-baseline-src-copy-readible.html
* igt@gem_readwrite@beyond-eob:
- shard-dg2: NOTRUN -> [SKIP][62] ([i915#3282]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-12/igt@gem_readwrite@beyond-eob.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs:
- shard-mtlp: NOTRUN -> [SKIP][63] ([i915#8428]) +3 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-1/igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html
* igt@gem_set_tiling_vs_blt@tiled-to-untiled:
- shard-dg2: NOTRUN -> [SKIP][64] ([i915#4079]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
* igt@gem_set_tiling_vs_pwrite:
- shard-rkl: NOTRUN -> [SKIP][65] ([i915#3282]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_spin_batch@user-each:
- shard-mtlp: [PASS][66] -> [DMESG-FAIL][67] ([i915#8962] / [i915#9121]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-2/igt@gem_spin_batch@user-each.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-4/igt@gem_spin_batch@user-each.html
* igt@gem_tiled_swapping@non-threaded:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#4077]) +13 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@gem_tiled_swapping@non-threaded.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#3297]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-2/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg2: NOTRUN -> [SKIP][70] ([i915#3297] / [i915#4880])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglu: NOTRUN -> [SKIP][71] ([i915#3297])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-3/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][72] ([i915#2724])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-snb1/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_mixed_blits:
- shard-rkl: NOTRUN -> [SKIP][73] ([fdo#109289])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-2/igt@gen3_mixed_blits.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-tglu: NOTRUN -> [SKIP][74] ([fdo#109289])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-10/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@gen9_exec_parse@bb-chained:
- shard-tglu: NOTRUN -> [SKIP][75] ([i915#2527] / [i915#2856])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-3/igt@gen9_exec_parse@bb-chained.html
* igt@gen9_exec_parse@shadow-peek:
- shard-dg2: NOTRUN -> [SKIP][76] ([i915#2856]) +4 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-8/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_fb_tiling:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#4881])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@i915_fb_tiling.html
* igt@i915_hangman@engine-engine-error@vcs0:
- shard-mtlp: [PASS][78] -> [FAIL][79] ([i915#7069])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-4/igt@i915_hangman@engine-engine-error@vcs0.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-6/igt@i915_hangman@engine-engine-error@vcs0.html
* igt@i915_pm_dc@dc5-psr:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#658]) +7 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@i915_pm_dc@dc5-psr.html
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#658]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-4/igt@i915_pm_dc@dc5-psr.html
* igt@i915_pm_dc@dc6-dpms:
- shard-mtlp: NOTRUN -> [SKIP][82] ([i915#3361])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-4/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_dc@dc9-dpms:
- shard-tglu: [PASS][83] -> [SKIP][84] ([i915#4281])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-tglu-4/igt@i915_pm_dc@dc9-dpms.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-5/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vcs0:
- shard-dg1: [PASS][85] -> [FAIL][86] ([i915#3591])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-17/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-dg2: NOTRUN -> [SKIP][87] ([i915#1397]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@i915_pm_rpm@modeset-lpsp-stress.html
- shard-rkl: NOTRUN -> [SKIP][88] ([i915#1397])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg2: [PASS][89] -> [SKIP][90] ([i915#1397]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-1/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-10/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@pc8-residency:
- shard-dg2: NOTRUN -> [SKIP][91] ([fdo#109506])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@i915_pm_rpm@pc8-residency.html
* igt@i915_pm_sseu@full-enable:
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#4387])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@i915_pm_sseu@full-enable.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-tglu: NOTRUN -> [INCOMPLETE][93] ([i915#7443] / [i915#8102])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-5/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][94] ([i915#4212]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
- shard-mtlp: [PASS][95] -> [FAIL][96] ([i915#2521])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-3/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc_ccs:
- shard-dg1: NOTRUN -> [SKIP][97] ([i915#8502]) +7 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-12/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [FAIL][98] ([i915#8247]) +3 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@kms_async_flips@crc@pipe-d-dp-4.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#1769] / [i915#3555])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-5/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#5286])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-tglu: NOTRUN -> [SKIP][101] ([fdo#111615] / [i915#5286])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-mtlp: [PASS][102] -> [FAIL][103] ([i915#5138])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@linear-16bpp-rotate-90:
- shard-dg2: NOTRUN -> [SKIP][104] ([fdo#111614]) +4 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-5/igt@kms_big_fb@linear-16bpp-rotate-90.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][105] ([fdo#111614]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-8/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-mtlp: NOTRUN -> [FAIL][106] ([i915#3743])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#5190]) +13 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-270:
- shard-tglu: NOTRUN -> [SKIP][108] ([fdo#111614])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-8/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][109] ([fdo#111615]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-1/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-0:
- shard-dg2: NOTRUN -> [SKIP][110] ([i915#4538] / [i915#5190]) +5 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-10/igt@kms_big_fb@yf-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-dg1: NOTRUN -> [SKIP][111] ([i915#4538])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-12/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-tglu: NOTRUN -> [SKIP][112] ([fdo#111615])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_joiner@2x-modeset:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#2705])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-1/igt@kms_big_joiner@2x-modeset.html
* igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs:
- shard-tglu: NOTRUN -> [SKIP][114] ([fdo#111615] / [i915#3689] / [i915#5354] / [i915#6095]) +2 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-8/igt@kms_ccs@pipe-a-bad-aux-stride-yf_tiled_ccs.html
* igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_mtl_rc_ccs:
- shard-tglu: NOTRUN -> [SKIP][115] ([i915#5354] / [i915#6095]) +2 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-6/igt@kms_ccs@pipe-a-bad-rotation-90-4_tiled_mtl_rc_ccs.html
* igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-dg1: NOTRUN -> [SKIP][116] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-12/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs:
- shard-dg1: NOTRUN -> [SKIP][117] ([i915#3689] / [i915#5354] / [i915#6095]) +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-17/igt@kms_ccs@pipe-a-crc-primary-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-mtlp: NOTRUN -> [SKIP][118] ([i915#3886] / [i915#5354] / [i915#6095])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-2/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_dg2_rc_ccs_cc:
- shard-rkl: NOTRUN -> [SKIP][119] ([i915#5354] / [i915#6095]) +2 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-7/igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][120] ([i915#3689] / [i915#3886] / [i915#5354]) +10 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-12/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][121] ([i915#3886] / [i915#5354] / [i915#6095])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-4/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-tglu: NOTRUN -> [SKIP][122] ([i915#3689] / [i915#3886] / [i915#5354] / [i915#6095]) +1 similar issue
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-3/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-mtlp: NOTRUN -> [SKIP][123] ([i915#3886] / [i915#6095])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-8/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_mtl_rc_ccs:
- shard-dg1: NOTRUN -> [SKIP][124] ([i915#5354] / [i915#6095])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-13/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_mtl_rc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][125] ([i915#5354]) +10 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-glk: NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#3886]) +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk5/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_rc_ccs_cc:
- shard-mtlp: NOTRUN -> [SKIP][127] ([i915#6095]) +5 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-8/igt@kms_ccs@pipe-d-bad-pixel-format-4_tiled_dg2_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-basic-yf_tiled_ccs:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#3689] / [i915#5354]) +21 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@kms_ccs@pipe-d-crc-primary-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_ccs:
- shard-tglu: NOTRUN -> [SKIP][129] ([i915#3689] / [i915#5354] / [i915#6095]) +2 similar issues
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-9/igt@kms_ccs@pipe-d-missing-ccs-buffer-y_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-glk: NOTRUN -> [SKIP][130] ([fdo#109271]) +73 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk7/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium_color@ctm-green-to-red:
- shard-dg2: NOTRUN -> [SKIP][131] ([fdo#111827]) +4 similar issues
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@kms_chamelium_color@ctm-green-to-red.html
* igt@kms_chamelium_color@ctm-max:
- shard-tglu: NOTRUN -> [SKIP][132] ([fdo#111827])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-3/igt@kms_chamelium_color@ctm-max.html
* igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k:
- shard-tglu: NOTRUN -> [SKIP][133] ([i915#7828]) +1 similar issue
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-4/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k.html
* igt@kms_chamelium_frames@vga-frame-dump:
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#7828])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-4/igt@kms_chamelium_frames@vga-frame-dump.html
* igt@kms_chamelium_hpd@hdmi-hpd:
- shard-mtlp: NOTRUN -> [SKIP][135] ([i915#7828]) +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-3/igt@kms_chamelium_hpd@hdmi-hpd.html
* igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
- shard-dg2: NOTRUN -> [SKIP][136] ([i915#7828]) +7 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-12/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#3299])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-1/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@mei_interface:
- shard-dg2: NOTRUN -> [SKIP][138] ([i915#7118]) +3 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-2/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_crc@cursor-offscreen-512x512:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#3359])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-5/igt@kms_cursor_crc@cursor-offscreen-512x512.html
- shard-rkl: NOTRUN -> [SKIP][140] ([i915#3359])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-4/igt@kms_cursor_crc@cursor-offscreen-512x512.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-rkl: NOTRUN -> [SKIP][141] ([i915#3555]) +1 similar issue
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-1/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x32:
- shard-mtlp: NOTRUN -> [SKIP][142] ([i915#8814])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-3/igt@kms_cursor_crc@cursor-rapid-movement-32x32.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-mtlp: NOTRUN -> [SKIP][143] ([i915#3359])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-8/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-dg2: NOTRUN -> [SKIP][144] ([fdo#109274] / [fdo#111767] / [i915#5354])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-12/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
- shard-rkl: NOTRUN -> [SKIP][145] ([fdo#111767] / [fdo#111825])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-dg2: NOTRUN -> [SKIP][146] ([i915#4103] / [i915#4213]) +1 similar issue
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
- shard-dg2: NOTRUN -> [SKIP][147] ([fdo#109274] / [i915#5354]) +4 similar issues
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-5/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
- shard-rkl: NOTRUN -> [SKIP][148] ([fdo#111825]) +1 similar issue
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-7/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
- shard-tglu: NOTRUN -> [SKIP][149] ([fdo#109274])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-3/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions:
- shard-tglu: NOTRUN -> [SKIP][150] ([fdo#109274] / [fdo#111767])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-3/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [PASS][151] -> [FAIL][152] ([i915#2346])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][153] ([i915#3804])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-rkl: NOTRUN -> [SKIP][154] ([i915#3555] / [i915#3840])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@kms_dsc@dsc-with-bpc-formats.html
- shard-tglu: NOTRUN -> [SKIP][155] ([i915#3555] / [i915#3840])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-6/igt@kms_dsc@dsc-with-bpc-formats.html
- shard-mtlp: NOTRUN -> [SKIP][156] ([i915#3840])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-3/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-dg2: NOTRUN -> [SKIP][157] ([i915#3555] / [i915#3840]) +1 similar issue
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-12/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-dg2: NOTRUN -> [SKIP][158] ([fdo#109274]) +5 similar issues
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-1/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-mtlp: NOTRUN -> [SKIP][159] ([i915#3637])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-2/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-dg2: NOTRUN -> [SKIP][160] ([fdo#109274] / [fdo#111767])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-12/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
- shard-snb: NOTRUN -> [SKIP][161] ([fdo#109271] / [fdo#111767])
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-snb5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][162] ([i915#8381]) +1 similar issue
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-1/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1:
- shard-glk: [PASS][163] -> [FAIL][164] ([i915#79])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-glk1/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-vga1:
- shard-snb: NOTRUN -> [DMESG-WARN][165] ([i915#8841]) +9 similar issues
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-snb1/igt@kms_flip@flip-vs-suspend-interruptible@a-vga1.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1:
- shard-mtlp: [PASS][166] -> [DMESG-WARN][167] ([i915#1982])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-2/igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-4/igt@kms_flip@wf_vblank-ts-check-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][168] ([i915#2672]) +3 similar issues
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#2672])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][170] ([i915#2587] / [i915#2672])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
- shard-dg2: [PASS][171] -> [FAIL][172] ([i915#6880])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt:
- shard-dg2: NOTRUN -> [FAIL][173] ([i915#6880])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt:
- shard-dg2: NOTRUN -> [SKIP][174] ([i915#5354]) +52 similar issues
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
- shard-mtlp: NOTRUN -> [SKIP][175] ([i915#1825]) +7 similar issues
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
- shard-dg1: NOTRUN -> [SKIP][176] ([fdo#111825]) +2 similar issues
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-tglu: NOTRUN -> [SKIP][177] ([fdo#109280]) +9 similar issues
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][178] ([i915#5460])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][179] ([i915#3458]) +18 similar issues
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
- shard-rkl: NOTRUN -> [SKIP][180] ([fdo#111825] / [i915#1825]) +7 similar issues
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-rkl: NOTRUN -> [SKIP][181] ([i915#3023]) +9 similar issues
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#8708]) +1 similar issue
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][183] ([i915#8708]) +18 similar issues
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-tglu: NOTRUN -> [SKIP][184] ([i915#3555] / [i915#8228]) +1 similar issue
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-10/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@static-toggle:
- shard-dg2: NOTRUN -> [SKIP][185] ([i915#3555] / [i915#8228]) +1 similar issue
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@kms_hdr@static-toggle.html
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-mtlp: NOTRUN -> [SKIP][186] ([fdo#109289])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-5/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-2:
- shard-dg2: NOTRUN -> [FAIL][187] ([i915#8292])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-12/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-2.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][188] ([i915#8292])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-7/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [FAIL][189] ([i915#8292])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-13/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#5176]) +3 similar issues
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-d-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][191] ([i915#5176]) +3 similar issues
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-6/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-d-edp-1.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][192] ([i915#5176]) +27 similar issues
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-19/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][193] ([i915#5176]) +5 similar issues
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-7/igt@kms_plane_scaling@plane-upscale-with-rotation-20x20@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][194] ([i915#5235]) +7 similar issues
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-8/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][195] ([fdo#109271]) +261 similar issues
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-snb2/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][196] ([i915#5235]) +15 similar issues
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-18/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4.html
* igt@kms_prime@basic-crc-hybrid:
- shard-dg2: NOTRUN -> [SKIP][197] ([i915#6524] / [i915#6805]) +1 similar issue
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-tglu: NOTRUN -> [SKIP][198] ([i915#658])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-8/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-glk: NOTRUN -> [SKIP][199] ([fdo#109271] / [i915#658])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk6/igt@kms_psr2_sf@overlay-plane-move-continuous-sf.html
* igt@kms_psr@cursor_render:
- shard-rkl: NOTRUN -> [SKIP][200] ([i915#1072])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@kms_psr@cursor_render.html
* igt@kms_psr@dpms:
- shard-dg2: NOTRUN -> [SKIP][201] ([i915#1072]) +7 similar issues
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-1/igt@kms_psr@dpms.html
* igt@kms_psr@psr2_cursor_render:
- shard-tglu: NOTRUN -> [SKIP][202] ([fdo#110189]) +6 similar issues
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-7/igt@kms_psr@psr2_cursor_render.html
* igt@kms_rotation_crc@bad-tiling:
- shard-dg2: NOTRUN -> [SKIP][203] ([i915#4235])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-tglu: NOTRUN -> [SKIP][204] ([i915#5289])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-3/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#4235] / [i915#5190]) +1 similar issue
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
* igt@kms_scaling_modes@scaling-mode-none:
- shard-dg2: NOTRUN -> [SKIP][206] ([i915#3555]) +4 similar issues
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-10/igt@kms_scaling_modes@scaling-mode-none.html
* igt@kms_selftest@drm_damage:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#8661])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@kms_selftest@drm_damage.html
- shard-rkl: NOTRUN -> [SKIP][208] ([i915#8661])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@kms_selftest@drm_damage.html
* igt@kms_selftest@framebuffer:
- shard-glk: NOTRUN -> [SKIP][209] ([fdo#109271] / [i915#8661])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk9/igt@kms_selftest@framebuffer.html
* igt@kms_setmode@basic@pipe-a-vga-1:
- shard-snb: NOTRUN -> [FAIL][210] ([i915#5465]) +1 similar issue
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-snb6/igt@kms_setmode@basic@pipe-a-vga-1.html
* igt@kms_vblank@pipe-c-query-forked-busy-hang:
- shard-rkl: NOTRUN -> [SKIP][211] ([i915#4070] / [i915#6768]) +1 similar issue
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-7/igt@kms_vblank@pipe-c-query-forked-busy-hang.html
* igt@kms_vblank@pipe-d-query-forked-hang:
- shard-rkl: NOTRUN -> [SKIP][212] ([i915#4070] / [i915#533] / [i915#6768]) +1 similar issue
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-2/igt@kms_vblank@pipe-d-query-forked-hang.html
* igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend:
- shard-dg2: [PASS][213] -> [FAIL][214] ([fdo#103375]) +1 similar issue
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-3/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-5/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html
* igt@kms_vrr@flip-basic:
- shard-tglu: NOTRUN -> [SKIP][215] ([i915#3555])
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-5/igt@kms_vrr@flip-basic.html
* igt@kms_writeback@writeback-check-output:
- shard-glk: NOTRUN -> [SKIP][216] ([fdo#109271] / [i915#2437])
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk7/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-dg2: NOTRUN -> [SKIP][217] ([i915#2437])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-10/igt@kms_writeback@writeback-pixel-formats.html
* igt@perf@enable-disable@0-rcs0:
- shard-dg2: [PASS][218] -> [FAIL][219] ([i915#8724])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-5/igt@perf@enable-disable@0-rcs0.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@perf@enable-disable@0-rcs0.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [PASS][220] -> [FAIL][221] ([i915#7484])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-1/igt@perf@non-zero-reason@0-rcs0.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf@per-context-mode-unprivileged:
- shard-dg2: NOTRUN -> [SKIP][222] ([fdo#109289]) +2 similar issues
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-1/igt@perf@per-context-mode-unprivileged.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [PASS][223] -> [FAIL][224] ([i915#4349]) +11 similar issues
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-2/igt@perf_pmu@busy-double-start@vecs1.html
* igt@perf_pmu@module-unload:
- shard-dg2: NOTRUN -> [FAIL][225] ([i915#5793] / [i915#6121])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-1/igt@perf_pmu@module-unload.html
* igt@perf_pmu@render-node-busy-idle@vcs1:
- shard-dg1: [PASS][226] -> [FAIL][227] ([i915#4349]) +2 similar issues
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg1-19/igt@perf_pmu@render-node-busy-idle@vcs1.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-15/igt@perf_pmu@render-node-busy-idle@vcs1.html
* igt@prime_vgem@basic-fence-mmap:
- shard-mtlp: NOTRUN -> [SKIP][228] ([i915#3708] / [i915#4077])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-4/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@coherency-gtt:
- shard-dg2: NOTRUN -> [SKIP][229] ([i915#3708] / [i915#4077])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-2/igt@prime_vgem@coherency-gtt.html
* igt@prime_vgem@fence-read-hang:
- shard-dg2: NOTRUN -> [SKIP][230] ([i915#3708])
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-3/igt@prime_vgem@fence-read-hang.html
- shard-rkl: NOTRUN -> [SKIP][231] ([fdo#109295] / [i915#3708])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@prime_vgem@fence-read-hang.html
* igt@syncobj_wait@signal:
- shard-mtlp: NOTRUN -> [DMESG-WARN][232] ([i915#2017])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-4/igt@syncobj_wait@signal.html
* igt@sysfs_preempt_timeout@timeout@vecs0:
- shard-mtlp: [PASS][233] -> [TIMEOUT][234] ([i915#8521])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-4/igt@sysfs_preempt_timeout@timeout@vecs0.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-5/igt@sysfs_preempt_timeout@timeout@vecs0.html
* igt@sysfs_timeslice_duration@timeout@vecs0:
- shard-mtlp: [PASS][235] -> [ABORT][236] ([i915#8521] / [i915#8865])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-8/igt@sysfs_timeslice_duration@timeout@vecs0.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-5/igt@sysfs_timeslice_duration@timeout@vecs0.html
* igt@template@b:
- shard-snb: NOTRUN -> [ABORT][237] ([i915#8865])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-snb7/igt@template@b.html
* igt@v3d/v3d_perfmon@get-values-invalid-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][238] ([i915#2575]) +2 similar issues
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-3/igt@v3d/v3d_perfmon@get-values-invalid-perfmon.html
* igt@v3d/v3d_submit_cl@bad-multisync-extension:
- shard-rkl: NOTRUN -> [SKIP][239] ([fdo#109315]) +2 similar issues
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-2/igt@v3d/v3d_submit_cl@bad-multisync-extension.html
* igt@v3d/v3d_submit_csd@bad-multisync-extension:
- shard-tglu: NOTRUN -> [SKIP][240] ([fdo#109315] / [i915#2575]) +2 similar issues
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-10/igt@v3d/v3d_submit_csd@bad-multisync-extension.html
* igt@v3d/v3d_submit_csd@job-perfmon:
- shard-dg1: NOTRUN -> [SKIP][241] ([i915#2575])
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-19/igt@v3d/v3d_submit_csd@job-perfmon.html
* igt@v3d/v3d_submit_csd@single-out-sync:
- shard-dg2: NOTRUN -> [SKIP][242] ([i915#2575]) +13 similar issues
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-1/igt@v3d/v3d_submit_csd@single-out-sync.html
* igt@vc4/vc4_label_bo@set-kernel-name:
- shard-dg1: NOTRUN -> [SKIP][243] ([i915#7711])
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-12/igt@vc4/vc4_label_bo@set-kernel-name.html
* igt@vc4/vc4_perfmon@get-values-invalid-pointer:
- shard-tglu: NOTRUN -> [SKIP][244] ([i915#2575]) +1 similar issue
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-4/igt@vc4/vc4_perfmon@get-values-invalid-pointer.html
* igt@vc4/vc4_purgeable_bo@mark-purgeable:
- shard-mtlp: NOTRUN -> [SKIP][245] ([i915#7711]) +1 similar issue
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-1/igt@vc4/vc4_purgeable_bo@mark-purgeable.html
* igt@vc4/vc4_tiling@get-bad-handle:
- shard-dg2: NOTRUN -> [SKIP][246] ([i915#7711]) +9 similar issues
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@vc4/vc4_tiling@get-bad-handle.html
* igt@vc4/vc4_tiling@set-bad-modifier:
- shard-rkl: NOTRUN -> [SKIP][247] ([i915#7711])
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-1/igt@vc4/vc4_tiling@set-bad-modifier.html
#### Possible fixes ####
* igt@fbdev@read:
- shard-mtlp: [FAIL][248] -> [PASS][249]
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-5/igt@fbdev@read.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-6/igt@fbdev@read.html
- shard-apl: [FAIL][250] -> [PASS][251]
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-apl3/igt@fbdev@read.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-apl4/igt@fbdev@read.html
- shard-glk: [FAIL][252] -> [PASS][253]
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-glk2/igt@fbdev@read.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk5/igt@fbdev@read.html
- shard-rkl: [FAIL][254] -> [PASS][255]
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-rkl-4/igt@fbdev@read.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-2/igt@fbdev@read.html
- shard-dg1: [FAIL][256] -> [PASS][257]
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg1-16/igt@fbdev@read.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-17/igt@fbdev@read.html
- shard-snb: [FAIL][258] -> [PASS][259]
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-snb1/igt@fbdev@read.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-snb2/igt@fbdev@read.html
- shard-tglu: [FAIL][260] -> [PASS][261]
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-tglu-3/igt@fbdev@read.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-2/igt@fbdev@read.html
* igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0:
- shard-dg2: [INCOMPLETE][262] ([i915#6311] / [i915#7297]) -> [PASS][263]
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-6/igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0.html
* igt@gem_eio@in-flight-contexts-immediate:
- shard-mtlp: [ABORT][264] ([i915#8503]) -> [PASS][265]
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-4/igt@gem_eio@in-flight-contexts-immediate.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-1/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_capture@capture@vcs0-smem:
- shard-mtlp: [DMESG-WARN][266] ([i915#5591]) -> [PASS][267]
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-1/igt@gem_exec_capture@capture@vcs0-smem.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-8/igt@gem_exec_capture@capture@vcs0-smem.html
* igt@gem_exec_capture@pi@bcs0:
- shard-mtlp: [FAIL][268] ([i915#4475] / [i915#7765]) -> [PASS][269]
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-8/igt@gem_exec_capture@pi@bcs0.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-3/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_capture@pi@rcs0:
- shard-mtlp: [FAIL][270] ([i915#4475]) -> [PASS][271]
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-8/igt@gem_exec_capture@pi@rcs0.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-3/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-rkl: [FAIL][272] ([i915#2842]) -> [PASS][273]
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-rkl-1/igt@gem_exec_fair@basic-none-share@rcs0.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-4/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [FAIL][274] ([i915#2842]) -> [PASS][275]
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-tglu-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_suspend@basic-s4-devices@smem:
- shard-tglu: [ABORT][276] ([i915#7975] / [i915#8213]) -> [PASS][277]
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-tglu-10/igt@gem_exec_suspend@basic-s4-devices@smem.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-3/igt@gem_exec_suspend@basic-s4-devices@smem.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg2: [DMESG-WARN][278] ([i915#7061] / [i915#8617]) -> [PASS][279]
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_dc@dc6-dpms:
- shard-tglu: [FAIL][280] ([i915#3989] / [i915#454]) -> [PASS][281]
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-tglu-2/igt@i915_pm_dc@dc6-dpms.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-9/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg1: [SKIP][282] ([i915#1397]) -> [PASS][283] +2 similar issues
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg1-19/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-16/igt@i915_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-rkl: [SKIP][284] ([i915#1397]) -> [PASS][285] +1 similar issue
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-rkl-7/igt@i915_pm_rpm@dpms-non-lpsp.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-4/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_suspend@forcewake:
- shard-dg2: [FAIL][286] ([fdo#103375]) -> [PASS][287] +3 similar issues
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-5/igt@i915_suspend@forcewake.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-1/igt@i915_suspend@forcewake.html
* igt@i915_suspend@sysfs-reader:
- shard-dg2: [INCOMPLETE][288] ([i915#4817]) -> [PASS][289]
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-5/igt@i915_suspend@sysfs-reader.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-8/igt@i915_suspend@sysfs-reader.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-mtlp: [FAIL][290] ([i915#2521]) -> [PASS][291] +1 similar issue
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-3/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
- shard-mtlp: [FAIL][292] ([i915#3743]) -> [PASS][293] +1 similar issue
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][294] ([i915#2346]) -> [PASS][295]
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
- shard-mtlp: [FAIL][296] ([i915#2346]) -> [PASS][297]
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1:
- shard-glk: [FAIL][298] ([i915#79]) -> [PASS][299]
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-glk6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-glk3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
* igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
- shard-dg2: [FAIL][300] ([i915#6880]) -> [PASS][301] +2 similar issues
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
* igt@perf_pmu@busy-idle@ccs3:
- shard-dg2: [FAIL][302] ([i915#4349]) -> [PASS][303] +2 similar issues
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-3/igt@perf_pmu@busy-idle@ccs3.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-8/igt@perf_pmu@busy-idle@ccs3.html
* igt@sysfs_heartbeat_interval@nopreempt@bcs0:
- shard-mtlp: [FAIL][304] ([i915#6015]) -> [PASS][305] +2 similar issues
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-3/igt@sysfs_heartbeat_interval@nopreempt@bcs0.html
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-8/igt@sysfs_heartbeat_interval@nopreempt@bcs0.html
#### Warnings ####
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglu: [FAIL][306] ([i915#2842]) -> [FAIL][307] ([i915#2876])
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-tglu-4/igt@gem_exec_fair@basic-pace@rcs0.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@i915_pm_dc@dc9-dpms:
- shard-apl: [SKIP][308] ([fdo#109271]) -> [FAIL][309] ([i915#4275])
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-apl4/igt@i915_pm_dc@dc9-dpms.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-apl6/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- shard-tglu: [FAIL][310] ([i915#2681] / [i915#3591]) -> [WARN][311] ([i915#2681])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-tglu-10/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-tglu-2/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [INCOMPLETE][312] ([i915#4817]) -> [FAIL][313] ([fdo#103375])
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-rkl-7/igt@i915_suspend@basic-s3-without-i915.html
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-6/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_async_flips@crc@pipe-a-edp-1:
- shard-mtlp: [DMESG-FAIL][314] ([i915#1982] / [i915#8561]) -> [DMESG-FAIL][315] ([i915#8561])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-mtlp-1/igt@kms_async_flips@crc@pipe-a-edp-1.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-mtlp-3/igt@kms_async_flips@crc@pipe-a-edp-1.html
* igt@kms_content_protection@content_type_change:
- shard-dg2: [SKIP][316] ([i915#7118]) -> [SKIP][317] ([i915#7118] / [i915#7162])
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-5/igt@kms_content_protection@content_type_change.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-11/igt@kms_content_protection@content_type_change.html
* igt@kms_fbcon_fbt@psr:
- shard-rkl: [SKIP][318] ([fdo#110189] / [i915#3955]) -> [SKIP][319] ([i915#3955])
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-rkl-1/igt@kms_fbcon_fbt@psr.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-4/igt@kms_fbcon_fbt@psr.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][320] ([i915#4070] / [i915#4816]) -> [SKIP][321] ([i915#4816])
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_psr@cursor_plane_move:
- shard-dg1: [SKIP][322] ([i915#1072]) -> [SKIP][323] ([i915#1072] / [i915#4078]) +2 similar issues
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg1-17/igt@kms_psr@cursor_plane_move.html
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg1-18/igt@kms_psr@cursor_plane_move.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][324] ([i915#5493]) -> [CRASH][325] ([i915#7331])
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_7458/shard-dg2-5/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2876]: https://gitlab.freedesktop.org/drm/intel/issues/2876
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4275]: https://gitlab.freedesktop.org/drm/intel/issues/4275
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
[i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
[i915#5793]: https://gitlab.freedesktop.org/drm/intel/issues/5793
[i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
[i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6805]: https://gitlab.freedesktop.org/drm/intel/issues/6805
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#7016]: https://gitlab.freedesktop.org/drm/intel/issues/7016
[i915#7061]: https://gitlab.freedesktop.org/drm/intel/issues/7061
[i915#7069]: https://gitlab.freedesktop.org/drm/intel/issues/7069
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7297]: https://gitlab.freedesktop.org/drm/intel/issues/7297
[i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7765]: https://gitlab.freedesktop.org/drm/intel/issues/7765
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8102]: https://gitlab.freedesktop.org/drm/intel/issues/8102
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8503]: https://gitlab.freedesktop.org/drm/intel/issues/8503
[i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521
[i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
[i915#8561]: https://gitlab.freedesktop.org/drm/intel/issues/8561
[i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
[i915#8617]: https://gitlab.freedesktop.org/drm/intel/issues/8617
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8724]: https://gitlab.freedesktop.org/drm/intel/issues/8724
[i915#8814]: https://gitlab.freedesktop.org/drm/intel/issues/8814
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8865]: https://gitlab.freedesktop.org/drm/intel/issues/8865
[i915#8957]: https://gitlab.freedesktop.org/drm/intel/issues/8957
[i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
[i915#9051]: https://gitlab.freedesktop.org/drm/intel/issues/9051
[i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_7458 -> IGTPW_9679
CI-20190529: 20190529
CI_DRM_13573: cb94b8169f58bc821f95f5fd8f333074576f71ac @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_9679: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/index.html
IGT_7458: 7458
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_9679/index.html
[-- Attachment #2: Type: text/html, Size: 101712 bytes --]
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-xe] [PATCH igt 0/4] Add LNL support to xe tests
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
@ 2023-08-30 21:07 ` Rodrigo Vivi
-1 siblings, 0 replies; 35+ messages in thread
From: Rodrigo Vivi @ 2023-08-30 21:07 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: igt-dev, intel-xe
On Tue, Aug 29, 2023 at 07:11:03AM -0700, Lucas De Marchi wrote:
> Add Lunar Lake support so xe driver can be tested. This brings the new
> xe_pciids.h from kernel since now the PCI IDs is not going to be added
> on the i915 side.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
for the series
>
> Janga Rahul Kumar (1):
> tests/xe_debugfs: skip page table level check for Xe2
>
> Lucas De Marchi (2):
> lib: Add xe_pciids.h
> lib/intel_chipset: Add Lunar Lake support
>
> Zbigniew Kempczyński (1):
> lib/intel_device_info: Add blitter cmd info for Lunar Lake
>
> docs/reference/igt-gpu-tools/meson.build | 1 +
> lib/intel_chipset.h | 5 +
> lib/intel_device_info.c | 14 ++
> lib/xe_pciids.h | 215 +++++++++++++++++++++++
> tests/xe/xe_debugfs.c | 23 +--
> 5 files changed, 248 insertions(+), 10 deletions(-)
> create mode 100644 lib/xe_pciids.h
>
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [igt-dev] [Intel-xe] [PATCH igt 0/4] Add LNL support to xe tests
@ 2023-08-30 21:07 ` Rodrigo Vivi
0 siblings, 0 replies; 35+ messages in thread
From: Rodrigo Vivi @ 2023-08-30 21:07 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: igt-dev, intel-xe
On Tue, Aug 29, 2023 at 07:11:03AM -0700, Lucas De Marchi wrote:
> Add Lunar Lake support so xe driver can be tested. This brings the new
> xe_pciids.h from kernel since now the PCI IDs is not going to be added
> on the i915 side.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
for the series
>
> Janga Rahul Kumar (1):
> tests/xe_debugfs: skip page table level check for Xe2
>
> Lucas De Marchi (2):
> lib: Add xe_pciids.h
> lib/intel_chipset: Add Lunar Lake support
>
> Zbigniew Kempczyński (1):
> lib/intel_device_info: Add blitter cmd info for Lunar Lake
>
> docs/reference/igt-gpu-tools/meson.build | 1 +
> lib/intel_chipset.h | 5 +
> lib/intel_device_info.c | 14 ++
> lib/xe_pciids.h | 215 +++++++++++++++++++++++
> tests/xe/xe_debugfs.c | 23 +--
> 5 files changed, 248 insertions(+), 10 deletions(-)
> create mode 100644 lib/xe_pciids.h
>
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-xe] [igt-dev] [PATCH igt 3/4] lib/intel_device_info: Add blitter cmd info for Lunar Lake
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
@ 2023-08-30 23:48 ` Srivatsa, Anusha
-1 siblings, 0 replies; 35+ messages in thread
From: Srivatsa, Anusha @ 2023-08-30 23:48 UTC (permalink / raw)
To: De Marchi, Lucas, igt-dev; +Cc: De Marchi, Lucas, intel-xe
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De
> Marchi
> Sent: Tuesday, August 29, 2023 7:11 AM
> To: igt-dev@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; intel-
> xe@lists.freedesktop.org
> Subject: [igt-dev] [PATCH igt 3/4] lib/intel_device_info: Add blitter cmd info for
> Lunar Lake
>
> From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>
> Add separate cmd info for LunarLake. This re-uses the commands for PVC since all
> the commands being used in IGT match the ones for PVC.
>
> Cc: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> lib/intel_device_info.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c index
> 86a8b3650..d1c268482 100644
> --- a/lib/intel_device_info.c
> +++ b/lib/intel_device_info.c
> @@ -511,7 +511,8 @@ static const struct intel_device_info intel_lunarlake_info
> = {
> .has_4tile = true,
> .has_gmdid = true,
> .is_lunarlake = true,
> - .codename = "lunarlake"
> + .codename = "lunarlake",
> + .cmds_info = &gen12_pvc_cmds_info,
> };
>
> static const struct pci_id_match intel_device_match[] = {
> --
> 2.40.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [igt-dev] [PATCH igt 3/4] lib/intel_device_info: Add blitter cmd info for Lunar Lake
@ 2023-08-30 23:48 ` Srivatsa, Anusha
0 siblings, 0 replies; 35+ messages in thread
From: Srivatsa, Anusha @ 2023-08-30 23:48 UTC (permalink / raw)
To: De Marchi, Lucas, igt-dev; +Cc: De Marchi, Lucas, intel-xe
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De
> Marchi
> Sent: Tuesday, August 29, 2023 7:11 AM
> To: igt-dev@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; intel-
> xe@lists.freedesktop.org
> Subject: [igt-dev] [PATCH igt 3/4] lib/intel_device_info: Add blitter cmd info for
> Lunar Lake
>
> From: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
>
> Add separate cmd info for LunarLake. This re-uses the commands for PVC since all
> the commands being used in IGT match the ones for PVC.
>
> Cc: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> lib/intel_device_info.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c index
> 86a8b3650..d1c268482 100644
> --- a/lib/intel_device_info.c
> +++ b/lib/intel_device_info.c
> @@ -511,7 +511,8 @@ static const struct intel_device_info intel_lunarlake_info
> = {
> .has_4tile = true,
> .has_gmdid = true,
> .is_lunarlake = true,
> - .codename = "lunarlake"
> + .codename = "lunarlake",
> + .cmds_info = &gen12_pvc_cmds_info,
> };
>
> static const struct pci_id_match intel_device_match[] = {
> --
> 2.40.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-xe] [igt-dev] [PATCH igt 4/4] tests/xe_debugfs: skip page table level check for Xe2
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
@ 2023-08-30 23:50 ` Srivatsa, Anusha
-1 siblings, 0 replies; 35+ messages in thread
From: Srivatsa, Anusha @ 2023-08-30 23:50 UTC (permalink / raw)
To: De Marchi, Lucas, igt-dev; +Cc: De Marchi, Lucas, intel-xe
> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De
> Marchi
> Sent: Tuesday, August 29, 2023 7:11 AM
> To: igt-dev@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; intel-
> xe@lists.freedesktop.org
> Subject: [igt-dev] [PATCH igt 4/4] tests/xe_debugfs: skip page table level check
> for Xe2
>
> From: Janga Rahul Kumar <janga.rahul.kumar@intel.com>
>
> Starting with Xe2, a 5-level page table is always used, regardless of the actual
> virtual address range supported by the platform. Do not depend on VA range to
> configure max page table level.
>
> Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
> Signed-off-by: Janga Rahul Kumar <janga.rahul.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> tests/xe/xe_debugfs.c | 23 +++++++++++++----------
> 1 file changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/tests/xe/xe_debugfs.c b/tests/xe/xe_debugfs.c index
> e51d03661..72c069bfc 100644
> --- a/tests/xe/xe_debugfs.c
> +++ b/tests/xe/xe_debugfs.c
> @@ -74,6 +74,7 @@ static int validate_entries(int fd, const char *add_path,
> const char * const str static void test_base(int fd, struct drm_xe_query_config
> *config) {
> + uint16_t devid = intel_get_drm_devid(fd);
> static const char * const expected_files[] = {
> "gt0",
> "gt1",
> @@ -86,7 +87,6 @@ test_base(int fd, struct drm_xe_query_config *config)
> "clients",
> "name"
> };
> -
> char reference[4096];
> int val = 0;
>
> @@ -104,16 +104,19 @@ test_base(int fd, struct drm_xe_query_config *config)
>
> igt_assert(igt_debugfs_search(fd, "info", reference));
>
> - switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
> - case 48:
> - val = 3;
> - break;
> - case 57:
> - val = 4;
> - break;
> + if (!AT_LEAST_GEN(devid, 20)) {
> + switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
> + case 48:
> + val = 3;
> + break;
> + case 57:
> + val = 4;
> + break;
> + }
> +
> + sprintf(reference, "vm_max_level %d", val);
> + igt_assert(igt_debugfs_search(fd, "info", reference));
> }
> - sprintf(reference, "vm_max_level %d", val);
> - igt_assert(igt_debugfs_search(fd, "info", reference));
>
> igt_assert(igt_debugfs_exists(fd, "gt0", O_RDONLY));
> if (config->info[XE_QUERY_CONFIG_GT_COUNT] > 1)
> --
> 2.40.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [igt-dev] [PATCH igt 4/4] tests/xe_debugfs: skip page table level check for Xe2
@ 2023-08-30 23:50 ` Srivatsa, Anusha
0 siblings, 0 replies; 35+ messages in thread
From: Srivatsa, Anusha @ 2023-08-30 23:50 UTC (permalink / raw)
To: De Marchi, Lucas, igt-dev; +Cc: De Marchi, Lucas, intel-xe
> -----Original Message-----
> From: igt-dev <igt-dev-bounces@lists.freedesktop.org> On Behalf Of Lucas De
> Marchi
> Sent: Tuesday, August 29, 2023 7:11 AM
> To: igt-dev@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; intel-
> xe@lists.freedesktop.org
> Subject: [igt-dev] [PATCH igt 4/4] tests/xe_debugfs: skip page table level check
> for Xe2
>
> From: Janga Rahul Kumar <janga.rahul.kumar@intel.com>
>
> Starting with Xe2, a 5-level page table is always used, regardless of the actual
> virtual address range supported by the platform. Do not depend on VA range to
> configure max page table level.
>
> Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
> Signed-off-by: Janga Rahul Kumar <janga.rahul.kumar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> tests/xe/xe_debugfs.c | 23 +++++++++++++----------
> 1 file changed, 13 insertions(+), 10 deletions(-)
>
> diff --git a/tests/xe/xe_debugfs.c b/tests/xe/xe_debugfs.c index
> e51d03661..72c069bfc 100644
> --- a/tests/xe/xe_debugfs.c
> +++ b/tests/xe/xe_debugfs.c
> @@ -74,6 +74,7 @@ static int validate_entries(int fd, const char *add_path,
> const char * const str static void test_base(int fd, struct drm_xe_query_config
> *config) {
> + uint16_t devid = intel_get_drm_devid(fd);
> static const char * const expected_files[] = {
> "gt0",
> "gt1",
> @@ -86,7 +87,6 @@ test_base(int fd, struct drm_xe_query_config *config)
> "clients",
> "name"
> };
> -
> char reference[4096];
> int val = 0;
>
> @@ -104,16 +104,19 @@ test_base(int fd, struct drm_xe_query_config *config)
>
> igt_assert(igt_debugfs_search(fd, "info", reference));
>
> - switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
> - case 48:
> - val = 3;
> - break;
> - case 57:
> - val = 4;
> - break;
> + if (!AT_LEAST_GEN(devid, 20)) {
> + switch (config->info[XE_QUERY_CONFIG_VA_BITS]) {
> + case 48:
> + val = 3;
> + break;
> + case 57:
> + val = 4;
> + break;
> + }
> +
> + sprintf(reference, "vm_max_level %d", val);
> + igt_assert(igt_debugfs_search(fd, "info", reference));
> }
> - sprintf(reference, "vm_max_level %d", val);
> - igt_assert(igt_debugfs_search(fd, "info", reference));
>
> igt_assert(igt_debugfs_exists(fd, "gt0", O_RDONLY));
> if (config->info[XE_QUERY_CONFIG_GT_COUNT] > 1)
> --
> 2.40.1
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-xe] [PATCH igt 1/4] lib: Add xe_pciids.h
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
@ 2023-08-31 6:28 ` Balasubramani Vivekanandan
-1 siblings, 0 replies; 35+ messages in thread
From: Balasubramani Vivekanandan @ 2023-08-31 6:28 UTC (permalink / raw)
To: Lucas De Marchi, igt-dev; +Cc: intel-xe
On 29.08.2023 07:11, Lucas De Marchi wrote:
> With the introduction of Lunar Lake, igt won't be able to just re-use
> i915_pciids.h for both drivers anymore since the support for LNL is only
> coming with the xe module. Copy xe_pciids.h from the drm-xe-next branch
> (up to commit b9c9020fc816 ("drm/xe/pvc: Use fast copy engines as
> migrate engine on PVC") and start including it where needed. This brings
> all the LNL PCI IDs.
I couldn't find the commit hash b9c9020fc816. Is it lost due to rebase?
In that case, does it make sense to use the commit hash or just keep the
commit subject?
Regards,
Bala
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> docs/reference/igt-gpu-tools/meson.build | 1 +
> lib/intel_device_info.c | 1 +
> lib/xe_pciids.h | 215 +++++++++++++++++++++++
> 3 files changed, 217 insertions(+)
> create mode 100644 lib/xe_pciids.h
>
> diff --git a/docs/reference/igt-gpu-tools/meson.build b/docs/reference/igt-gpu-tools/meson.build
> index 6b832ad27..513385b4b 100644
> --- a/docs/reference/igt-gpu-tools/meson.build
> +++ b/docs/reference/igt-gpu-tools/meson.build
> @@ -21,6 +21,7 @@ ignore_headers = [
> 'media_fill_gen9.h',
> 'gen9_render.h',
> 'version.h',
> + 'xe_pciids.h',
> ]
>
> test_groups = [
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> index 2c9a45b68..5d53d2906 100644
> --- a/lib/intel_device_info.c
> +++ b/lib/intel_device_info.c
> @@ -1,6 +1,7 @@
> #include "intel_chipset.h"
> #include "i915_pciids.h"
> #include "i915_pciids_local.h"
> +#include "xe_pciids.h"
>
> #include <strings.h> /* ffs() */
>
> diff --git a/lib/xe_pciids.h b/lib/xe_pciids.h
> new file mode 100644
> index 000000000..29f07a00a
> --- /dev/null
> +++ b/lib/xe_pciids.h
> @@ -0,0 +1,215 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef _XE_PCIIDS_H_
> +#define _XE_PCIIDS_H_
> +
> +/*
> + * Lists below can be turned into initializers for a struct pci_device_id
> + * by defining INTEL_VGA_DEVICE:
> + *
> + * #define INTEL_VGA_DEVICE(id, info) { \
> + * 0x8086, id, \
> + * ~0, ~0, \
> + * 0x030000, 0xff0000, \
> + * (unsigned long) info }
> + *
> + * And then calling like:
> + *
> + * XE_TGL_12_GT1_IDS(INTEL_VGA_DEVICE, ## __VA_ARGS__)
> + *
> + * To turn them into something else, just provide a different macro passed as
> + * first argument.
> + */
> +
> +/* TGL */
> +#define XE_TGL_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x9A60, ## __VA_ARGS__), \
> + MACRO__(0x9A68, ## __VA_ARGS__), \
> + MACRO__(0x9A70, ## __VA_ARGS__)
> +
> +#define XE_TGL_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x9A40, ## __VA_ARGS__), \
> + MACRO__(0x9A49, ## __VA_ARGS__), \
> + MACRO__(0x9A59, ## __VA_ARGS__), \
> + MACRO__(0x9A78, ## __VA_ARGS__), \
> + MACRO__(0x9AC0, ## __VA_ARGS__), \
> + MACRO__(0x9AC9, ## __VA_ARGS__), \
> + MACRO__(0x9AD9, ## __VA_ARGS__), \
> + MACRO__(0x9AF8, ## __VA_ARGS__)
> +
> +#define XE_TGL_IDS(MACRO__, ...) \
> + XE_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__),\
> + XE_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +/* RKL */
> +#define XE_RKL_IDS(MACRO__, ...) \
> + MACRO__(0x4C80, ## __VA_ARGS__), \
> + MACRO__(0x4C8A, ## __VA_ARGS__), \
> + MACRO__(0x4C8B, ## __VA_ARGS__), \
> + MACRO__(0x4C8C, ## __VA_ARGS__), \
> + MACRO__(0x4C90, ## __VA_ARGS__), \
> + MACRO__(0x4C9A, ## __VA_ARGS__)
> +
> +/* DG1 */
> +#define XE_DG1_IDS(MACRO__, ...) \
> + MACRO__(0x4905, ## __VA_ARGS__), \
> + MACRO__(0x4906, ## __VA_ARGS__), \
> + MACRO__(0x4907, ## __VA_ARGS__), \
> + MACRO__(0x4908, ## __VA_ARGS__), \
> + MACRO__(0x4909, ## __VA_ARGS__)
> +
> +/* ADL-S */
> +#define XE_ADLS_IDS(MACRO__, ...) \
> + MACRO__(0x4680, ## __VA_ARGS__), \
> + MACRO__(0x4682, ## __VA_ARGS__), \
> + MACRO__(0x4688, ## __VA_ARGS__), \
> + MACRO__(0x468A, ## __VA_ARGS__), \
> + MACRO__(0x4690, ## __VA_ARGS__), \
> + MACRO__(0x4692, ## __VA_ARGS__), \
> + MACRO__(0x4693, ## __VA_ARGS__)
> +
> +/* ADL-P */
> +#define XE_ADLP_IDS(MACRO__, ...) \
> + MACRO__(0x46A0, ## __VA_ARGS__), \
> + MACRO__(0x46A1, ## __VA_ARGS__), \
> + MACRO__(0x46A2, ## __VA_ARGS__), \
> + MACRO__(0x46A3, ## __VA_ARGS__), \
> + MACRO__(0x46A6, ## __VA_ARGS__), \
> + MACRO__(0x46A8, ## __VA_ARGS__), \
> + MACRO__(0x46AA, ## __VA_ARGS__), \
> + MACRO__(0x462A, ## __VA_ARGS__), \
> + MACRO__(0x4626, ## __VA_ARGS__), \
> + MACRO__(0x4628, ## __VA_ARGS__), \
> + MACRO__(0x46B0, ## __VA_ARGS__), \
> + MACRO__(0x46B1, ## __VA_ARGS__), \
> + MACRO__(0x46B2, ## __VA_ARGS__), \
> + MACRO__(0x46B3, ## __VA_ARGS__), \
> + MACRO__(0x46C0, ## __VA_ARGS__), \
> + MACRO__(0x46C1, ## __VA_ARGS__), \
> + MACRO__(0x46C2, ## __VA_ARGS__), \
> + MACRO__(0x46C3, ## __VA_ARGS__)
> +
> +/* ADL-N */
> +#define XE_ADLN_IDS(MACRO__, ...) \
> + MACRO__(0x46D0, ## __VA_ARGS__), \
> + MACRO__(0x46D1, ## __VA_ARGS__), \
> + MACRO__(0x46D2, ## __VA_ARGS__)
> +
> +/* RPL-S */
> +#define XE_RPLS_IDS(MACRO__, ...) \
> + MACRO__(0xA780, ## __VA_ARGS__), \
> + MACRO__(0xA781, ## __VA_ARGS__), \
> + MACRO__(0xA782, ## __VA_ARGS__), \
> + MACRO__(0xA783, ## __VA_ARGS__), \
> + MACRO__(0xA788, ## __VA_ARGS__), \
> + MACRO__(0xA789, ## __VA_ARGS__), \
> + MACRO__(0xA78A, ## __VA_ARGS__), \
> + MACRO__(0xA78B, ## __VA_ARGS__)
> +
> +/* RPL-U */
> +#define XE_RPLU_IDS(MACRO__, ...) \
> + MACRO__(0xA721, ## __VA_ARGS__), \
> + MACRO__(0xA7A1, ## __VA_ARGS__), \
> + MACRO__(0xA7A9, ## __VA_ARGS__)
> +
> +/* RPL-P */
> +#define XE_RPLP_IDS(MACRO__, ...) \
> + MACRO__(0xA720, ## __VA_ARGS__), \
> + MACRO__(0xA7A0, ## __VA_ARGS__), \
> + MACRO__(0xA7A8, ## __VA_ARGS__)
> +
> +/* DG2 */
> +#define XE_DG2_G10_IDS(MACRO__, ...) \
> + MACRO__(0x5690, ## __VA_ARGS__), \
> + MACRO__(0x5691, ## __VA_ARGS__), \
> + MACRO__(0x5692, ## __VA_ARGS__), \
> + MACRO__(0x56A0, ## __VA_ARGS__), \
> + MACRO__(0x56A1, ## __VA_ARGS__), \
> + MACRO__(0x56A2, ## __VA_ARGS__)
> +
> +#define XE_DG2_G11_IDS(MACRO__, ...) \
> + MACRO__(0x5693, ## __VA_ARGS__), \
> + MACRO__(0x5694, ## __VA_ARGS__), \
> + MACRO__(0x5695, ## __VA_ARGS__), \
> + MACRO__(0x5698, ## __VA_ARGS__), \
> + MACRO__(0x56A5, ## __VA_ARGS__), \
> + MACRO__(0x56A6, ## __VA_ARGS__), \
> + MACRO__(0x56B0, ## __VA_ARGS__), \
> + MACRO__(0x56B1, ## __VA_ARGS__)
> +
> +#define XE_DG2_G12_IDS(MACRO__, ...) \
> + MACRO__(0x5696, ## __VA_ARGS__), \
> + MACRO__(0x5697, ## __VA_ARGS__), \
> + MACRO__(0x56A3, ## __VA_ARGS__), \
> + MACRO__(0x56A4, ## __VA_ARGS__), \
> + MACRO__(0x56B2, ## __VA_ARGS__), \
> + MACRO__(0x56B3, ## __VA_ARGS__)
> +
> +#define XE_DG2_IDS(MACRO__, ...) \
> + XE_DG2_G10_IDS(MACRO__, ## __VA_ARGS__),\
> + XE_DG2_G11_IDS(MACRO__, ## __VA_ARGS__),\
> + XE_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define XE_ATS_M150_IDS(MACRO__, ...) \
> + MACRO__(0x56C0, ## __VA_ARGS__)
> +
> +#define XE_ATS_M75_IDS(MACRO__, ...) \
> + MACRO__(0x56C1, ## __VA_ARGS__)
> +
> +#define XE_ATS_M_IDS(MACRO__, ...) \
> + XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\
> + XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
> +
> +/* PVC */
> +#define XE_PVC_XT_IDS(MACRO__, ...) \
> + MACRO__(0x0BD5, ## __VA_ARGS__), \
> + MACRO__(0x0BD6, ## __VA_ARGS__), \
> + MACRO__(0x0BD7, ## __VA_ARGS__), \
> + MACRO__(0x0BD8, ## __VA_ARGS__), \
> + MACRO__(0x0BD9, ## __VA_ARGS__), \
> + MACRO__(0x0BDA, ## __VA_ARGS__), \
> + MACRO__(0x0BDB, ## __VA_ARGS__), \
> + MACRO__(0x0BE0, ## __VA_ARGS__), \
> + MACRO__(0x0BE1, ## __VA_ARGS__), \
> + MACRO__(0x0BE5, ## __VA_ARGS__)
> +
> +#define XE_PVC_IDS(MACRO__, ...) \
> + XE_PVC_XT_IDS(MACRO__, ## __VA_ARGS__)
> +
> +/* MTL */
> +#define XE_MTL_M_IDS(MACRO__, ...) \
> + MACRO__(0x7D40, ## __VA_ARGS__), \
> + MACRO__(0x7D43, ## __VA_ARGS__), \
> + MACRO__(0x7DC0, ## __VA_ARGS__)
> +
> +#define XE_MTL_P_IDS(MACRO__, ...) \
> + MACRO__(0x7D45, ## __VA_ARGS__), \
> + MACRO__(0x7D47, ## __VA_ARGS__), \
> + MACRO__(0x7D50, ## __VA_ARGS__), \
> + MACRO__(0x7D55, ## __VA_ARGS__), \
> + MACRO__(0x7DC5, ## __VA_ARGS__), \
> + MACRO__(0x7DD0, ## __VA_ARGS__), \
> + MACRO__(0x7DD5, ## __VA_ARGS__)
> +
> +#define XE_MTL_S_IDS(MACRO__, ...) \
> + MACRO__(0x7D60, ## __VA_ARGS__), \
> + MACRO__(0x7DE0, ## __VA_ARGS__)
> +
> +#define XE_ARL_IDS(MACRO__, ...) \
> + MACRO__(0x7D67, ## __VA_ARGS__)
> +
> +#define XE_MTL_IDS(MACRO__, ...) \
> + XE_MTL_M_IDS(MACRO__, ## __VA_ARGS__), \
> + XE_MTL_P_IDS(MACRO__, ## __VA_ARGS__), \
> + XE_MTL_S_IDS(MACRO__, ## __VA_ARGS__), \
> + XE_ARL_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define XE_LNL_IDS(MACRO__, ...) \
> + MACRO__(0x6420, ## __VA_ARGS__), \
> + MACRO__(0x64A0, ## __VA_ARGS__), \
> + MACRO__(0x64B0, ## __VA_ARGS__)
> +
> +#endif
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [igt-dev] [Intel-xe] [PATCH igt 1/4] lib: Add xe_pciids.h
@ 2023-08-31 6:28 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 35+ messages in thread
From: Balasubramani Vivekanandan @ 2023-08-31 6:28 UTC (permalink / raw)
To: Lucas De Marchi, igt-dev; +Cc: intel-xe
On 29.08.2023 07:11, Lucas De Marchi wrote:
> With the introduction of Lunar Lake, igt won't be able to just re-use
> i915_pciids.h for both drivers anymore since the support for LNL is only
> coming with the xe module. Copy xe_pciids.h from the drm-xe-next branch
> (up to commit b9c9020fc816 ("drm/xe/pvc: Use fast copy engines as
> migrate engine on PVC") and start including it where needed. This brings
> all the LNL PCI IDs.
I couldn't find the commit hash b9c9020fc816. Is it lost due to rebase?
In that case, does it make sense to use the commit hash or just keep the
commit subject?
Regards,
Bala
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> docs/reference/igt-gpu-tools/meson.build | 1 +
> lib/intel_device_info.c | 1 +
> lib/xe_pciids.h | 215 +++++++++++++++++++++++
> 3 files changed, 217 insertions(+)
> create mode 100644 lib/xe_pciids.h
>
> diff --git a/docs/reference/igt-gpu-tools/meson.build b/docs/reference/igt-gpu-tools/meson.build
> index 6b832ad27..513385b4b 100644
> --- a/docs/reference/igt-gpu-tools/meson.build
> +++ b/docs/reference/igt-gpu-tools/meson.build
> @@ -21,6 +21,7 @@ ignore_headers = [
> 'media_fill_gen9.h',
> 'gen9_render.h',
> 'version.h',
> + 'xe_pciids.h',
> ]
>
> test_groups = [
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> index 2c9a45b68..5d53d2906 100644
> --- a/lib/intel_device_info.c
> +++ b/lib/intel_device_info.c
> @@ -1,6 +1,7 @@
> #include "intel_chipset.h"
> #include "i915_pciids.h"
> #include "i915_pciids_local.h"
> +#include "xe_pciids.h"
>
> #include <strings.h> /* ffs() */
>
> diff --git a/lib/xe_pciids.h b/lib/xe_pciids.h
> new file mode 100644
> index 000000000..29f07a00a
> --- /dev/null
> +++ b/lib/xe_pciids.h
> @@ -0,0 +1,215 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef _XE_PCIIDS_H_
> +#define _XE_PCIIDS_H_
> +
> +/*
> + * Lists below can be turned into initializers for a struct pci_device_id
> + * by defining INTEL_VGA_DEVICE:
> + *
> + * #define INTEL_VGA_DEVICE(id, info) { \
> + * 0x8086, id, \
> + * ~0, ~0, \
> + * 0x030000, 0xff0000, \
> + * (unsigned long) info }
> + *
> + * And then calling like:
> + *
> + * XE_TGL_12_GT1_IDS(INTEL_VGA_DEVICE, ## __VA_ARGS__)
> + *
> + * To turn them into something else, just provide a different macro passed as
> + * first argument.
> + */
> +
> +/* TGL */
> +#define XE_TGL_GT1_IDS(MACRO__, ...) \
> + MACRO__(0x9A60, ## __VA_ARGS__), \
> + MACRO__(0x9A68, ## __VA_ARGS__), \
> + MACRO__(0x9A70, ## __VA_ARGS__)
> +
> +#define XE_TGL_GT2_IDS(MACRO__, ...) \
> + MACRO__(0x9A40, ## __VA_ARGS__), \
> + MACRO__(0x9A49, ## __VA_ARGS__), \
> + MACRO__(0x9A59, ## __VA_ARGS__), \
> + MACRO__(0x9A78, ## __VA_ARGS__), \
> + MACRO__(0x9AC0, ## __VA_ARGS__), \
> + MACRO__(0x9AC9, ## __VA_ARGS__), \
> + MACRO__(0x9AD9, ## __VA_ARGS__), \
> + MACRO__(0x9AF8, ## __VA_ARGS__)
> +
> +#define XE_TGL_IDS(MACRO__, ...) \
> + XE_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__),\
> + XE_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
> +
> +/* RKL */
> +#define XE_RKL_IDS(MACRO__, ...) \
> + MACRO__(0x4C80, ## __VA_ARGS__), \
> + MACRO__(0x4C8A, ## __VA_ARGS__), \
> + MACRO__(0x4C8B, ## __VA_ARGS__), \
> + MACRO__(0x4C8C, ## __VA_ARGS__), \
> + MACRO__(0x4C90, ## __VA_ARGS__), \
> + MACRO__(0x4C9A, ## __VA_ARGS__)
> +
> +/* DG1 */
> +#define XE_DG1_IDS(MACRO__, ...) \
> + MACRO__(0x4905, ## __VA_ARGS__), \
> + MACRO__(0x4906, ## __VA_ARGS__), \
> + MACRO__(0x4907, ## __VA_ARGS__), \
> + MACRO__(0x4908, ## __VA_ARGS__), \
> + MACRO__(0x4909, ## __VA_ARGS__)
> +
> +/* ADL-S */
> +#define XE_ADLS_IDS(MACRO__, ...) \
> + MACRO__(0x4680, ## __VA_ARGS__), \
> + MACRO__(0x4682, ## __VA_ARGS__), \
> + MACRO__(0x4688, ## __VA_ARGS__), \
> + MACRO__(0x468A, ## __VA_ARGS__), \
> + MACRO__(0x4690, ## __VA_ARGS__), \
> + MACRO__(0x4692, ## __VA_ARGS__), \
> + MACRO__(0x4693, ## __VA_ARGS__)
> +
> +/* ADL-P */
> +#define XE_ADLP_IDS(MACRO__, ...) \
> + MACRO__(0x46A0, ## __VA_ARGS__), \
> + MACRO__(0x46A1, ## __VA_ARGS__), \
> + MACRO__(0x46A2, ## __VA_ARGS__), \
> + MACRO__(0x46A3, ## __VA_ARGS__), \
> + MACRO__(0x46A6, ## __VA_ARGS__), \
> + MACRO__(0x46A8, ## __VA_ARGS__), \
> + MACRO__(0x46AA, ## __VA_ARGS__), \
> + MACRO__(0x462A, ## __VA_ARGS__), \
> + MACRO__(0x4626, ## __VA_ARGS__), \
> + MACRO__(0x4628, ## __VA_ARGS__), \
> + MACRO__(0x46B0, ## __VA_ARGS__), \
> + MACRO__(0x46B1, ## __VA_ARGS__), \
> + MACRO__(0x46B2, ## __VA_ARGS__), \
> + MACRO__(0x46B3, ## __VA_ARGS__), \
> + MACRO__(0x46C0, ## __VA_ARGS__), \
> + MACRO__(0x46C1, ## __VA_ARGS__), \
> + MACRO__(0x46C2, ## __VA_ARGS__), \
> + MACRO__(0x46C3, ## __VA_ARGS__)
> +
> +/* ADL-N */
> +#define XE_ADLN_IDS(MACRO__, ...) \
> + MACRO__(0x46D0, ## __VA_ARGS__), \
> + MACRO__(0x46D1, ## __VA_ARGS__), \
> + MACRO__(0x46D2, ## __VA_ARGS__)
> +
> +/* RPL-S */
> +#define XE_RPLS_IDS(MACRO__, ...) \
> + MACRO__(0xA780, ## __VA_ARGS__), \
> + MACRO__(0xA781, ## __VA_ARGS__), \
> + MACRO__(0xA782, ## __VA_ARGS__), \
> + MACRO__(0xA783, ## __VA_ARGS__), \
> + MACRO__(0xA788, ## __VA_ARGS__), \
> + MACRO__(0xA789, ## __VA_ARGS__), \
> + MACRO__(0xA78A, ## __VA_ARGS__), \
> + MACRO__(0xA78B, ## __VA_ARGS__)
> +
> +/* RPL-U */
> +#define XE_RPLU_IDS(MACRO__, ...) \
> + MACRO__(0xA721, ## __VA_ARGS__), \
> + MACRO__(0xA7A1, ## __VA_ARGS__), \
> + MACRO__(0xA7A9, ## __VA_ARGS__)
> +
> +/* RPL-P */
> +#define XE_RPLP_IDS(MACRO__, ...) \
> + MACRO__(0xA720, ## __VA_ARGS__), \
> + MACRO__(0xA7A0, ## __VA_ARGS__), \
> + MACRO__(0xA7A8, ## __VA_ARGS__)
> +
> +/* DG2 */
> +#define XE_DG2_G10_IDS(MACRO__, ...) \
> + MACRO__(0x5690, ## __VA_ARGS__), \
> + MACRO__(0x5691, ## __VA_ARGS__), \
> + MACRO__(0x5692, ## __VA_ARGS__), \
> + MACRO__(0x56A0, ## __VA_ARGS__), \
> + MACRO__(0x56A1, ## __VA_ARGS__), \
> + MACRO__(0x56A2, ## __VA_ARGS__)
> +
> +#define XE_DG2_G11_IDS(MACRO__, ...) \
> + MACRO__(0x5693, ## __VA_ARGS__), \
> + MACRO__(0x5694, ## __VA_ARGS__), \
> + MACRO__(0x5695, ## __VA_ARGS__), \
> + MACRO__(0x5698, ## __VA_ARGS__), \
> + MACRO__(0x56A5, ## __VA_ARGS__), \
> + MACRO__(0x56A6, ## __VA_ARGS__), \
> + MACRO__(0x56B0, ## __VA_ARGS__), \
> + MACRO__(0x56B1, ## __VA_ARGS__)
> +
> +#define XE_DG2_G12_IDS(MACRO__, ...) \
> + MACRO__(0x5696, ## __VA_ARGS__), \
> + MACRO__(0x5697, ## __VA_ARGS__), \
> + MACRO__(0x56A3, ## __VA_ARGS__), \
> + MACRO__(0x56A4, ## __VA_ARGS__), \
> + MACRO__(0x56B2, ## __VA_ARGS__), \
> + MACRO__(0x56B3, ## __VA_ARGS__)
> +
> +#define XE_DG2_IDS(MACRO__, ...) \
> + XE_DG2_G10_IDS(MACRO__, ## __VA_ARGS__),\
> + XE_DG2_G11_IDS(MACRO__, ## __VA_ARGS__),\
> + XE_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define XE_ATS_M150_IDS(MACRO__, ...) \
> + MACRO__(0x56C0, ## __VA_ARGS__)
> +
> +#define XE_ATS_M75_IDS(MACRO__, ...) \
> + MACRO__(0x56C1, ## __VA_ARGS__)
> +
> +#define XE_ATS_M_IDS(MACRO__, ...) \
> + XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\
> + XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
> +
> +/* PVC */
> +#define XE_PVC_XT_IDS(MACRO__, ...) \
> + MACRO__(0x0BD5, ## __VA_ARGS__), \
> + MACRO__(0x0BD6, ## __VA_ARGS__), \
> + MACRO__(0x0BD7, ## __VA_ARGS__), \
> + MACRO__(0x0BD8, ## __VA_ARGS__), \
> + MACRO__(0x0BD9, ## __VA_ARGS__), \
> + MACRO__(0x0BDA, ## __VA_ARGS__), \
> + MACRO__(0x0BDB, ## __VA_ARGS__), \
> + MACRO__(0x0BE0, ## __VA_ARGS__), \
> + MACRO__(0x0BE1, ## __VA_ARGS__), \
> + MACRO__(0x0BE5, ## __VA_ARGS__)
> +
> +#define XE_PVC_IDS(MACRO__, ...) \
> + XE_PVC_XT_IDS(MACRO__, ## __VA_ARGS__)
> +
> +/* MTL */
> +#define XE_MTL_M_IDS(MACRO__, ...) \
> + MACRO__(0x7D40, ## __VA_ARGS__), \
> + MACRO__(0x7D43, ## __VA_ARGS__), \
> + MACRO__(0x7DC0, ## __VA_ARGS__)
> +
> +#define XE_MTL_P_IDS(MACRO__, ...) \
> + MACRO__(0x7D45, ## __VA_ARGS__), \
> + MACRO__(0x7D47, ## __VA_ARGS__), \
> + MACRO__(0x7D50, ## __VA_ARGS__), \
> + MACRO__(0x7D55, ## __VA_ARGS__), \
> + MACRO__(0x7DC5, ## __VA_ARGS__), \
> + MACRO__(0x7DD0, ## __VA_ARGS__), \
> + MACRO__(0x7DD5, ## __VA_ARGS__)
> +
> +#define XE_MTL_S_IDS(MACRO__, ...) \
> + MACRO__(0x7D60, ## __VA_ARGS__), \
> + MACRO__(0x7DE0, ## __VA_ARGS__)
> +
> +#define XE_ARL_IDS(MACRO__, ...) \
> + MACRO__(0x7D67, ## __VA_ARGS__)
> +
> +#define XE_MTL_IDS(MACRO__, ...) \
> + XE_MTL_M_IDS(MACRO__, ## __VA_ARGS__), \
> + XE_MTL_P_IDS(MACRO__, ## __VA_ARGS__), \
> + XE_MTL_S_IDS(MACRO__, ## __VA_ARGS__), \
> + XE_ARL_IDS(MACRO__, ## __VA_ARGS__)
> +
> +#define XE_LNL_IDS(MACRO__, ...) \
> + MACRO__(0x6420, ## __VA_ARGS__), \
> + MACRO__(0x64A0, ## __VA_ARGS__), \
> + MACRO__(0x64B0, ## __VA_ARGS__)
> +
> +#endif
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-xe] [PATCH igt 2/4] lib/intel_chipset: Add Lunar Lake support
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
@ 2023-08-31 6:48 ` Balasubramani Vivekanandan
-1 siblings, 0 replies; 35+ messages in thread
From: Balasubramani Vivekanandan @ 2023-08-31 6:48 UTC (permalink / raw)
To: Lucas De Marchi, igt-dev; +Cc: intel-xe, Swati Sharma
On 29.08.2023 07:11, Lucas De Marchi wrote:
> Add basic definition for the Lunar Lake platform. This uses the PCI ID
> from the xe_pciids.h which has a macro in a slighlty different form.
>
> Going forward we could also trim down a little bit the the info struct
> like was done in the kernel, relying on gmdid and IP version checks.
> This is left for later.
>
> Cc: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> lib/intel_chipset.h | 5 +++++
> lib/intel_device_info.c | 12 ++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> index 84cf1799e..52b15ccea 100644
> --- a/lib/intel_chipset.h
> +++ b/lib/intel_chipset.h
> @@ -46,6 +46,7 @@ struct intel_device_info {
> bool has_4tile : 1;
> bool has_flatccs : 1;
> bool has_oam : 1;
> + bool has_gmdid : 1;
> bool is_mobile : 1;
> bool is_whitney : 1;
> bool is_almador : 1;
> @@ -90,6 +91,7 @@ struct intel_device_info {
> bool is_alderlake_n : 1;
> bool is_meteorlake : 1;
> bool is_pontevecchio : 1;
> + bool is_lunarlake : 1;
> const struct intel_cmds_info *cmds_info;
> const char *codename;
> };
> @@ -203,6 +205,7 @@ void intel_check_pch(void);
> #define IS_ALDERLAKE_N(devid) (intel_get_device_info(devid)->is_alderlake_n)
> #define IS_METEORLAKE(devid) (intel_get_device_info(devid)->is_meteorlake)
> #define IS_PONTEVECCHIO(devid) (intel_get_device_info(devid)->is_pontevecchio)
> +#define IS_LUNARLAKE(devid) (intel_get_device_info(devid)->is_lunarlake)
>
> #define IS_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver == x)
> #define AT_LEAST_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver >= x)
> @@ -236,4 +239,6 @@ void intel_check_pch(void);
>
> #define HAS_OAM(devid) (intel_get_device_info(devid)->has_oam)
>
> +#define HAS_GMDID(devid) (intel_get_device_info(devid)->has_gmdid)
> +
> #endif /* _INTEL_CHIPSET_H */
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> index 5d53d2906..86a8b3650 100644
> --- a/lib/intel_device_info.c
> +++ b/lib/intel_device_info.c
> @@ -504,6 +504,16 @@ static const struct intel_device_info intel_pontevecchio_info = {
> .cmds_info = &gen12_pvc_cmds_info,
> };
>
> +static const struct intel_device_info intel_lunarlake_info = {
> + .graphics_ver = 20,
> + .graphics_rel = 4,
> + .display_ver = 20,
> + .has_4tile = true,
> + .has_gmdid = true,
has_gmdid should be set true even for Meteorlake. If not in this patch,
in a follow up.
Regards,
Bala
> + .is_lunarlake = true,
> + .codename = "lunarlake"
> +};
> +
> static const struct pci_id_match intel_device_match[] = {
> INTEL_I810_IDS(&intel_i810_info),
> INTEL_I815_IDS(&intel_i815_info),
> @@ -607,6 +617,8 @@ static const struct pci_id_match intel_device_match[] = {
>
> INTEL_PVC_IDS(&intel_pontevecchio_info),
>
> + XE_LNL_IDS(INTEL_VGA_DEVICE, &intel_lunarlake_info),
> +
> INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
> };
>
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [igt-dev] [Intel-xe] [PATCH igt 2/4] lib/intel_chipset: Add Lunar Lake support
@ 2023-08-31 6:48 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 35+ messages in thread
From: Balasubramani Vivekanandan @ 2023-08-31 6:48 UTC (permalink / raw)
To: Lucas De Marchi, igt-dev; +Cc: intel-xe
On 29.08.2023 07:11, Lucas De Marchi wrote:
> Add basic definition for the Lunar Lake platform. This uses the PCI ID
> from the xe_pciids.h which has a macro in a slighlty different form.
>
> Going forward we could also trim down a little bit the the info struct
> like was done in the kernel, relying on gmdid and IP version checks.
> This is left for later.
>
> Cc: Swati Sharma <swati2.sharma@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> lib/intel_chipset.h | 5 +++++
> lib/intel_device_info.c | 12 ++++++++++++
> 2 files changed, 17 insertions(+)
>
> diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> index 84cf1799e..52b15ccea 100644
> --- a/lib/intel_chipset.h
> +++ b/lib/intel_chipset.h
> @@ -46,6 +46,7 @@ struct intel_device_info {
> bool has_4tile : 1;
> bool has_flatccs : 1;
> bool has_oam : 1;
> + bool has_gmdid : 1;
> bool is_mobile : 1;
> bool is_whitney : 1;
> bool is_almador : 1;
> @@ -90,6 +91,7 @@ struct intel_device_info {
> bool is_alderlake_n : 1;
> bool is_meteorlake : 1;
> bool is_pontevecchio : 1;
> + bool is_lunarlake : 1;
> const struct intel_cmds_info *cmds_info;
> const char *codename;
> };
> @@ -203,6 +205,7 @@ void intel_check_pch(void);
> #define IS_ALDERLAKE_N(devid) (intel_get_device_info(devid)->is_alderlake_n)
> #define IS_METEORLAKE(devid) (intel_get_device_info(devid)->is_meteorlake)
> #define IS_PONTEVECCHIO(devid) (intel_get_device_info(devid)->is_pontevecchio)
> +#define IS_LUNARLAKE(devid) (intel_get_device_info(devid)->is_lunarlake)
>
> #define IS_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver == x)
> #define AT_LEAST_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver >= x)
> @@ -236,4 +239,6 @@ void intel_check_pch(void);
>
> #define HAS_OAM(devid) (intel_get_device_info(devid)->has_oam)
>
> +#define HAS_GMDID(devid) (intel_get_device_info(devid)->has_gmdid)
> +
> #endif /* _INTEL_CHIPSET_H */
> diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> index 5d53d2906..86a8b3650 100644
> --- a/lib/intel_device_info.c
> +++ b/lib/intel_device_info.c
> @@ -504,6 +504,16 @@ static const struct intel_device_info intel_pontevecchio_info = {
> .cmds_info = &gen12_pvc_cmds_info,
> };
>
> +static const struct intel_device_info intel_lunarlake_info = {
> + .graphics_ver = 20,
> + .graphics_rel = 4,
> + .display_ver = 20,
> + .has_4tile = true,
> + .has_gmdid = true,
has_gmdid should be set true even for Meteorlake. If not in this patch,
in a follow up.
Regards,
Bala
> + .is_lunarlake = true,
> + .codename = "lunarlake"
> +};
> +
> static const struct pci_id_match intel_device_match[] = {
> INTEL_I810_IDS(&intel_i810_info),
> INTEL_I815_IDS(&intel_i815_info),
> @@ -607,6 +617,8 @@ static const struct pci_id_match intel_device_match[] = {
>
> INTEL_PVC_IDS(&intel_pontevecchio_info),
>
> + XE_LNL_IDS(INTEL_VGA_DEVICE, &intel_lunarlake_info),
> +
> INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
> };
>
> --
> 2.40.1
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-xe] [PATCH igt 2/4] lib/intel_chipset: Add Lunar Lake support
2023-08-31 6:48 ` [igt-dev] " Balasubramani Vivekanandan
@ 2023-08-31 6:51 ` Balasubramani Vivekanandan
-1 siblings, 0 replies; 35+ messages in thread
From: Balasubramani Vivekanandan @ 2023-08-31 6:51 UTC (permalink / raw)
To: Lucas De Marchi, igt-dev; +Cc: intel-xe, Swati Sharma
On 31.08.2023 12:18, Balasubramani Vivekanandan wrote:
> On 29.08.2023 07:11, Lucas De Marchi wrote:
> > Add basic definition for the Lunar Lake platform. This uses the PCI ID
> > from the xe_pciids.h which has a macro in a slighlty different form.
> >
> > Going forward we could also trim down a little bit the the info struct
> > like was done in the kernel, relying on gmdid and IP version checks.
> > This is left for later.
> >
> > Cc: Swati Sharma <swati2.sharma@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > lib/intel_chipset.h | 5 +++++
> > lib/intel_device_info.c | 12 ++++++++++++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> > index 84cf1799e..52b15ccea 100644
> > --- a/lib/intel_chipset.h
> > +++ b/lib/intel_chipset.h
> > @@ -46,6 +46,7 @@ struct intel_device_info {
> > bool has_4tile : 1;
> > bool has_flatccs : 1;
> > bool has_oam : 1;
> > + bool has_gmdid : 1;
> > bool is_mobile : 1;
> > bool is_whitney : 1;
> > bool is_almador : 1;
> > @@ -90,6 +91,7 @@ struct intel_device_info {
> > bool is_alderlake_n : 1;
> > bool is_meteorlake : 1;
> > bool is_pontevecchio : 1;
> > + bool is_lunarlake : 1;
> > const struct intel_cmds_info *cmds_info;
> > const char *codename;
> > };
> > @@ -203,6 +205,7 @@ void intel_check_pch(void);
> > #define IS_ALDERLAKE_N(devid) (intel_get_device_info(devid)->is_alderlake_n)
> > #define IS_METEORLAKE(devid) (intel_get_device_info(devid)->is_meteorlake)
> > #define IS_PONTEVECCHIO(devid) (intel_get_device_info(devid)->is_pontevecchio)
> > +#define IS_LUNARLAKE(devid) (intel_get_device_info(devid)->is_lunarlake)
> >
> > #define IS_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver == x)
> > #define AT_LEAST_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver >= x)
> > @@ -236,4 +239,6 @@ void intel_check_pch(void);
> >
> > #define HAS_OAM(devid) (intel_get_device_info(devid)->has_oam)
> >
> > +#define HAS_GMDID(devid) (intel_get_device_info(devid)->has_gmdid)
> > +
> > #endif /* _INTEL_CHIPSET_H */
> > diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> > index 5d53d2906..86a8b3650 100644
> > --- a/lib/intel_device_info.c
> > +++ b/lib/intel_device_info.c
> > @@ -504,6 +504,16 @@ static const struct intel_device_info intel_pontevecchio_info = {
> > .cmds_info = &gen12_pvc_cmds_info,
> > };
> >
> > +static const struct intel_device_info intel_lunarlake_info = {
> > + .graphics_ver = 20,
> > + .graphics_rel = 4,
> > + .display_ver = 20,
> > + .has_4tile = true,
> > + .has_gmdid = true,
>
> has_gmdid should be set true even for Meteorlake. If not in this patch,
> in a follow up.
>
> Regards,
> Bala
Other than this comment,
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Regards,
Bala
>
> > + .is_lunarlake = true,
> > + .codename = "lunarlake"
> > +};
> > +
> > static const struct pci_id_match intel_device_match[] = {
> > INTEL_I810_IDS(&intel_i810_info),
> > INTEL_I815_IDS(&intel_i815_info),
> > @@ -607,6 +617,8 @@ static const struct pci_id_match intel_device_match[] = {
> >
> > INTEL_PVC_IDS(&intel_pontevecchio_info),
> >
> > + XE_LNL_IDS(INTEL_VGA_DEVICE, &intel_lunarlake_info),
> > +
> > INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
> > };
> >
> > --
> > 2.40.1
> >
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [igt-dev] [Intel-xe] [PATCH igt 2/4] lib/intel_chipset: Add Lunar Lake support
@ 2023-08-31 6:51 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 35+ messages in thread
From: Balasubramani Vivekanandan @ 2023-08-31 6:51 UTC (permalink / raw)
To: Lucas De Marchi, igt-dev; +Cc: intel-xe
On 31.08.2023 12:18, Balasubramani Vivekanandan wrote:
> On 29.08.2023 07:11, Lucas De Marchi wrote:
> > Add basic definition for the Lunar Lake platform. This uses the PCI ID
> > from the xe_pciids.h which has a macro in a slighlty different form.
> >
> > Going forward we could also trim down a little bit the the info struct
> > like was done in the kernel, relying on gmdid and IP version checks.
> > This is left for later.
> >
> > Cc: Swati Sharma <swati2.sharma@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > lib/intel_chipset.h | 5 +++++
> > lib/intel_device_info.c | 12 ++++++++++++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> > index 84cf1799e..52b15ccea 100644
> > --- a/lib/intel_chipset.h
> > +++ b/lib/intel_chipset.h
> > @@ -46,6 +46,7 @@ struct intel_device_info {
> > bool has_4tile : 1;
> > bool has_flatccs : 1;
> > bool has_oam : 1;
> > + bool has_gmdid : 1;
> > bool is_mobile : 1;
> > bool is_whitney : 1;
> > bool is_almador : 1;
> > @@ -90,6 +91,7 @@ struct intel_device_info {
> > bool is_alderlake_n : 1;
> > bool is_meteorlake : 1;
> > bool is_pontevecchio : 1;
> > + bool is_lunarlake : 1;
> > const struct intel_cmds_info *cmds_info;
> > const char *codename;
> > };
> > @@ -203,6 +205,7 @@ void intel_check_pch(void);
> > #define IS_ALDERLAKE_N(devid) (intel_get_device_info(devid)->is_alderlake_n)
> > #define IS_METEORLAKE(devid) (intel_get_device_info(devid)->is_meteorlake)
> > #define IS_PONTEVECCHIO(devid) (intel_get_device_info(devid)->is_pontevecchio)
> > +#define IS_LUNARLAKE(devid) (intel_get_device_info(devid)->is_lunarlake)
> >
> > #define IS_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver == x)
> > #define AT_LEAST_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver >= x)
> > @@ -236,4 +239,6 @@ void intel_check_pch(void);
> >
> > #define HAS_OAM(devid) (intel_get_device_info(devid)->has_oam)
> >
> > +#define HAS_GMDID(devid) (intel_get_device_info(devid)->has_gmdid)
> > +
> > #endif /* _INTEL_CHIPSET_H */
> > diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> > index 5d53d2906..86a8b3650 100644
> > --- a/lib/intel_device_info.c
> > +++ b/lib/intel_device_info.c
> > @@ -504,6 +504,16 @@ static const struct intel_device_info intel_pontevecchio_info = {
> > .cmds_info = &gen12_pvc_cmds_info,
> > };
> >
> > +static const struct intel_device_info intel_lunarlake_info = {
> > + .graphics_ver = 20,
> > + .graphics_rel = 4,
> > + .display_ver = 20,
> > + .has_4tile = true,
> > + .has_gmdid = true,
>
> has_gmdid should be set true even for Meteorlake. If not in this patch,
> in a follow up.
>
> Regards,
> Bala
Other than this comment,
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Regards,
Bala
>
> > + .is_lunarlake = true,
> > + .codename = "lunarlake"
> > +};
> > +
> > static const struct pci_id_match intel_device_match[] = {
> > INTEL_I810_IDS(&intel_i810_info),
> > INTEL_I815_IDS(&intel_i815_info),
> > @@ -607,6 +617,8 @@ static const struct pci_id_match intel_device_match[] = {
> >
> > INTEL_PVC_IDS(&intel_pontevecchio_info),
> >
> > + XE_LNL_IDS(INTEL_VGA_DEVICE, &intel_lunarlake_info),
> > +
> > INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
> > };
> >
> > --
> > 2.40.1
> >
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-xe] [PATCH igt 1/4] lib: Add xe_pciids.h
2023-08-31 6:28 ` [igt-dev] " Balasubramani Vivekanandan
@ 2023-08-31 6:55 ` Balasubramani Vivekanandan
-1 siblings, 0 replies; 35+ messages in thread
From: Balasubramani Vivekanandan @ 2023-08-31 6:55 UTC (permalink / raw)
To: Lucas De Marchi, igt-dev; +Cc: intel-xe
On 31.08.2023 11:58, Balasubramani Vivekanandan wrote:
> On 29.08.2023 07:11, Lucas De Marchi wrote:
> > With the introduction of Lunar Lake, igt won't be able to just re-use
> > i915_pciids.h for both drivers anymore since the support for LNL is only
> > coming with the xe module. Copy xe_pciids.h from the drm-xe-next branch
> > (up to commit b9c9020fc816 ("drm/xe/pvc: Use fast copy engines as
> > migrate engine on PVC") and start including it where needed. This brings
> > all the LNL PCI IDs.
>
> I couldn't find the commit hash b9c9020fc816. Is it lost due to rebase?
> In that case, does it make sense to use the commit hash or just keep the
> commit subject?
>
> Regards,
> Bala
Apart from that.
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Regards,
Bala
>
> >
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > docs/reference/igt-gpu-tools/meson.build | 1 +
> > lib/intel_device_info.c | 1 +
> > lib/xe_pciids.h | 215 +++++++++++++++++++++++
> > 3 files changed, 217 insertions(+)
> > create mode 100644 lib/xe_pciids.h
> >
> > diff --git a/docs/reference/igt-gpu-tools/meson.build b/docs/reference/igt-gpu-tools/meson.build
> > index 6b832ad27..513385b4b 100644
> > --- a/docs/reference/igt-gpu-tools/meson.build
> > +++ b/docs/reference/igt-gpu-tools/meson.build
> > @@ -21,6 +21,7 @@ ignore_headers = [
> > 'media_fill_gen9.h',
> > 'gen9_render.h',
> > 'version.h',
> > + 'xe_pciids.h',
> > ]
> >
> > test_groups = [
> > diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> > index 2c9a45b68..5d53d2906 100644
> > --- a/lib/intel_device_info.c
> > +++ b/lib/intel_device_info.c
> > @@ -1,6 +1,7 @@
> > #include "intel_chipset.h"
> > #include "i915_pciids.h"
> > #include "i915_pciids_local.h"
> > +#include "xe_pciids.h"
> >
> > #include <strings.h> /* ffs() */
> >
> > diff --git a/lib/xe_pciids.h b/lib/xe_pciids.h
> > new file mode 100644
> > index 000000000..29f07a00a
> > --- /dev/null
> > +++ b/lib/xe_pciids.h
> > @@ -0,0 +1,215 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2022 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_PCIIDS_H_
> > +#define _XE_PCIIDS_H_
> > +
> > +/*
> > + * Lists below can be turned into initializers for a struct pci_device_id
> > + * by defining INTEL_VGA_DEVICE:
> > + *
> > + * #define INTEL_VGA_DEVICE(id, info) { \
> > + * 0x8086, id, \
> > + * ~0, ~0, \
> > + * 0x030000, 0xff0000, \
> > + * (unsigned long) info }
> > + *
> > + * And then calling like:
> > + *
> > + * XE_TGL_12_GT1_IDS(INTEL_VGA_DEVICE, ## __VA_ARGS__)
> > + *
> > + * To turn them into something else, just provide a different macro passed as
> > + * first argument.
> > + */
> > +
> > +/* TGL */
> > +#define XE_TGL_GT1_IDS(MACRO__, ...) \
> > + MACRO__(0x9A60, ## __VA_ARGS__), \
> > + MACRO__(0x9A68, ## __VA_ARGS__), \
> > + MACRO__(0x9A70, ## __VA_ARGS__)
> > +
> > +#define XE_TGL_GT2_IDS(MACRO__, ...) \
> > + MACRO__(0x9A40, ## __VA_ARGS__), \
> > + MACRO__(0x9A49, ## __VA_ARGS__), \
> > + MACRO__(0x9A59, ## __VA_ARGS__), \
> > + MACRO__(0x9A78, ## __VA_ARGS__), \
> > + MACRO__(0x9AC0, ## __VA_ARGS__), \
> > + MACRO__(0x9AC9, ## __VA_ARGS__), \
> > + MACRO__(0x9AD9, ## __VA_ARGS__), \
> > + MACRO__(0x9AF8, ## __VA_ARGS__)
> > +
> > +#define XE_TGL_IDS(MACRO__, ...) \
> > + XE_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__),\
> > + XE_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
> > +
> > +/* RKL */
> > +#define XE_RKL_IDS(MACRO__, ...) \
> > + MACRO__(0x4C80, ## __VA_ARGS__), \
> > + MACRO__(0x4C8A, ## __VA_ARGS__), \
> > + MACRO__(0x4C8B, ## __VA_ARGS__), \
> > + MACRO__(0x4C8C, ## __VA_ARGS__), \
> > + MACRO__(0x4C90, ## __VA_ARGS__), \
> > + MACRO__(0x4C9A, ## __VA_ARGS__)
> > +
> > +/* DG1 */
> > +#define XE_DG1_IDS(MACRO__, ...) \
> > + MACRO__(0x4905, ## __VA_ARGS__), \
> > + MACRO__(0x4906, ## __VA_ARGS__), \
> > + MACRO__(0x4907, ## __VA_ARGS__), \
> > + MACRO__(0x4908, ## __VA_ARGS__), \
> > + MACRO__(0x4909, ## __VA_ARGS__)
> > +
> > +/* ADL-S */
> > +#define XE_ADLS_IDS(MACRO__, ...) \
> > + MACRO__(0x4680, ## __VA_ARGS__), \
> > + MACRO__(0x4682, ## __VA_ARGS__), \
> > + MACRO__(0x4688, ## __VA_ARGS__), \
> > + MACRO__(0x468A, ## __VA_ARGS__), \
> > + MACRO__(0x4690, ## __VA_ARGS__), \
> > + MACRO__(0x4692, ## __VA_ARGS__), \
> > + MACRO__(0x4693, ## __VA_ARGS__)
> > +
> > +/* ADL-P */
> > +#define XE_ADLP_IDS(MACRO__, ...) \
> > + MACRO__(0x46A0, ## __VA_ARGS__), \
> > + MACRO__(0x46A1, ## __VA_ARGS__), \
> > + MACRO__(0x46A2, ## __VA_ARGS__), \
> > + MACRO__(0x46A3, ## __VA_ARGS__), \
> > + MACRO__(0x46A6, ## __VA_ARGS__), \
> > + MACRO__(0x46A8, ## __VA_ARGS__), \
> > + MACRO__(0x46AA, ## __VA_ARGS__), \
> > + MACRO__(0x462A, ## __VA_ARGS__), \
> > + MACRO__(0x4626, ## __VA_ARGS__), \
> > + MACRO__(0x4628, ## __VA_ARGS__), \
> > + MACRO__(0x46B0, ## __VA_ARGS__), \
> > + MACRO__(0x46B1, ## __VA_ARGS__), \
> > + MACRO__(0x46B2, ## __VA_ARGS__), \
> > + MACRO__(0x46B3, ## __VA_ARGS__), \
> > + MACRO__(0x46C0, ## __VA_ARGS__), \
> > + MACRO__(0x46C1, ## __VA_ARGS__), \
> > + MACRO__(0x46C2, ## __VA_ARGS__), \
> > + MACRO__(0x46C3, ## __VA_ARGS__)
> > +
> > +/* ADL-N */
> > +#define XE_ADLN_IDS(MACRO__, ...) \
> > + MACRO__(0x46D0, ## __VA_ARGS__), \
> > + MACRO__(0x46D1, ## __VA_ARGS__), \
> > + MACRO__(0x46D2, ## __VA_ARGS__)
> > +
> > +/* RPL-S */
> > +#define XE_RPLS_IDS(MACRO__, ...) \
> > + MACRO__(0xA780, ## __VA_ARGS__), \
> > + MACRO__(0xA781, ## __VA_ARGS__), \
> > + MACRO__(0xA782, ## __VA_ARGS__), \
> > + MACRO__(0xA783, ## __VA_ARGS__), \
> > + MACRO__(0xA788, ## __VA_ARGS__), \
> > + MACRO__(0xA789, ## __VA_ARGS__), \
> > + MACRO__(0xA78A, ## __VA_ARGS__), \
> > + MACRO__(0xA78B, ## __VA_ARGS__)
> > +
> > +/* RPL-U */
> > +#define XE_RPLU_IDS(MACRO__, ...) \
> > + MACRO__(0xA721, ## __VA_ARGS__), \
> > + MACRO__(0xA7A1, ## __VA_ARGS__), \
> > + MACRO__(0xA7A9, ## __VA_ARGS__)
> > +
> > +/* RPL-P */
> > +#define XE_RPLP_IDS(MACRO__, ...) \
> > + MACRO__(0xA720, ## __VA_ARGS__), \
> > + MACRO__(0xA7A0, ## __VA_ARGS__), \
> > + MACRO__(0xA7A8, ## __VA_ARGS__)
> > +
> > +/* DG2 */
> > +#define XE_DG2_G10_IDS(MACRO__, ...) \
> > + MACRO__(0x5690, ## __VA_ARGS__), \
> > + MACRO__(0x5691, ## __VA_ARGS__), \
> > + MACRO__(0x5692, ## __VA_ARGS__), \
> > + MACRO__(0x56A0, ## __VA_ARGS__), \
> > + MACRO__(0x56A1, ## __VA_ARGS__), \
> > + MACRO__(0x56A2, ## __VA_ARGS__)
> > +
> > +#define XE_DG2_G11_IDS(MACRO__, ...) \
> > + MACRO__(0x5693, ## __VA_ARGS__), \
> > + MACRO__(0x5694, ## __VA_ARGS__), \
> > + MACRO__(0x5695, ## __VA_ARGS__), \
> > + MACRO__(0x5698, ## __VA_ARGS__), \
> > + MACRO__(0x56A5, ## __VA_ARGS__), \
> > + MACRO__(0x56A6, ## __VA_ARGS__), \
> > + MACRO__(0x56B0, ## __VA_ARGS__), \
> > + MACRO__(0x56B1, ## __VA_ARGS__)
> > +
> > +#define XE_DG2_G12_IDS(MACRO__, ...) \
> > + MACRO__(0x5696, ## __VA_ARGS__), \
> > + MACRO__(0x5697, ## __VA_ARGS__), \
> > + MACRO__(0x56A3, ## __VA_ARGS__), \
> > + MACRO__(0x56A4, ## __VA_ARGS__), \
> > + MACRO__(0x56B2, ## __VA_ARGS__), \
> > + MACRO__(0x56B3, ## __VA_ARGS__)
> > +
> > +#define XE_DG2_IDS(MACRO__, ...) \
> > + XE_DG2_G10_IDS(MACRO__, ## __VA_ARGS__),\
> > + XE_DG2_G11_IDS(MACRO__, ## __VA_ARGS__),\
> > + XE_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
> > +
> > +#define XE_ATS_M150_IDS(MACRO__, ...) \
> > + MACRO__(0x56C0, ## __VA_ARGS__)
> > +
> > +#define XE_ATS_M75_IDS(MACRO__, ...) \
> > + MACRO__(0x56C1, ## __VA_ARGS__)
> > +
> > +#define XE_ATS_M_IDS(MACRO__, ...) \
> > + XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\
> > + XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
> > +
> > +/* PVC */
> > +#define XE_PVC_XT_IDS(MACRO__, ...) \
> > + MACRO__(0x0BD5, ## __VA_ARGS__), \
> > + MACRO__(0x0BD6, ## __VA_ARGS__), \
> > + MACRO__(0x0BD7, ## __VA_ARGS__), \
> > + MACRO__(0x0BD8, ## __VA_ARGS__), \
> > + MACRO__(0x0BD9, ## __VA_ARGS__), \
> > + MACRO__(0x0BDA, ## __VA_ARGS__), \
> > + MACRO__(0x0BDB, ## __VA_ARGS__), \
> > + MACRO__(0x0BE0, ## __VA_ARGS__), \
> > + MACRO__(0x0BE1, ## __VA_ARGS__), \
> > + MACRO__(0x0BE5, ## __VA_ARGS__)
> > +
> > +#define XE_PVC_IDS(MACRO__, ...) \
> > + XE_PVC_XT_IDS(MACRO__, ## __VA_ARGS__)
> > +
> > +/* MTL */
> > +#define XE_MTL_M_IDS(MACRO__, ...) \
> > + MACRO__(0x7D40, ## __VA_ARGS__), \
> > + MACRO__(0x7D43, ## __VA_ARGS__), \
> > + MACRO__(0x7DC0, ## __VA_ARGS__)
> > +
> > +#define XE_MTL_P_IDS(MACRO__, ...) \
> > + MACRO__(0x7D45, ## __VA_ARGS__), \
> > + MACRO__(0x7D47, ## __VA_ARGS__), \
> > + MACRO__(0x7D50, ## __VA_ARGS__), \
> > + MACRO__(0x7D55, ## __VA_ARGS__), \
> > + MACRO__(0x7DC5, ## __VA_ARGS__), \
> > + MACRO__(0x7DD0, ## __VA_ARGS__), \
> > + MACRO__(0x7DD5, ## __VA_ARGS__)
> > +
> > +#define XE_MTL_S_IDS(MACRO__, ...) \
> > + MACRO__(0x7D60, ## __VA_ARGS__), \
> > + MACRO__(0x7DE0, ## __VA_ARGS__)
> > +
> > +#define XE_ARL_IDS(MACRO__, ...) \
> > + MACRO__(0x7D67, ## __VA_ARGS__)
> > +
> > +#define XE_MTL_IDS(MACRO__, ...) \
> > + XE_MTL_M_IDS(MACRO__, ## __VA_ARGS__), \
> > + XE_MTL_P_IDS(MACRO__, ## __VA_ARGS__), \
> > + XE_MTL_S_IDS(MACRO__, ## __VA_ARGS__), \
> > + XE_ARL_IDS(MACRO__, ## __VA_ARGS__)
> > +
> > +#define XE_LNL_IDS(MACRO__, ...) \
> > + MACRO__(0x6420, ## __VA_ARGS__), \
> > + MACRO__(0x64A0, ## __VA_ARGS__), \
> > + MACRO__(0x64B0, ## __VA_ARGS__)
> > +
> > +#endif
> > --
> > 2.40.1
> >
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [igt-dev] [Intel-xe] [PATCH igt 1/4] lib: Add xe_pciids.h
@ 2023-08-31 6:55 ` Balasubramani Vivekanandan
0 siblings, 0 replies; 35+ messages in thread
From: Balasubramani Vivekanandan @ 2023-08-31 6:55 UTC (permalink / raw)
To: Lucas De Marchi, igt-dev; +Cc: intel-xe
On 31.08.2023 11:58, Balasubramani Vivekanandan wrote:
> On 29.08.2023 07:11, Lucas De Marchi wrote:
> > With the introduction of Lunar Lake, igt won't be able to just re-use
> > i915_pciids.h for both drivers anymore since the support for LNL is only
> > coming with the xe module. Copy xe_pciids.h from the drm-xe-next branch
> > (up to commit b9c9020fc816 ("drm/xe/pvc: Use fast copy engines as
> > migrate engine on PVC") and start including it where needed. This brings
> > all the LNL PCI IDs.
>
> I couldn't find the commit hash b9c9020fc816. Is it lost due to rebase?
> In that case, does it make sense to use the commit hash or just keep the
> commit subject?
>
> Regards,
> Bala
Apart from that.
Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Regards,
Bala
>
> >
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > docs/reference/igt-gpu-tools/meson.build | 1 +
> > lib/intel_device_info.c | 1 +
> > lib/xe_pciids.h | 215 +++++++++++++++++++++++
> > 3 files changed, 217 insertions(+)
> > create mode 100644 lib/xe_pciids.h
> >
> > diff --git a/docs/reference/igt-gpu-tools/meson.build b/docs/reference/igt-gpu-tools/meson.build
> > index 6b832ad27..513385b4b 100644
> > --- a/docs/reference/igt-gpu-tools/meson.build
> > +++ b/docs/reference/igt-gpu-tools/meson.build
> > @@ -21,6 +21,7 @@ ignore_headers = [
> > 'media_fill_gen9.h',
> > 'gen9_render.h',
> > 'version.h',
> > + 'xe_pciids.h',
> > ]
> >
> > test_groups = [
> > diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> > index 2c9a45b68..5d53d2906 100644
> > --- a/lib/intel_device_info.c
> > +++ b/lib/intel_device_info.c
> > @@ -1,6 +1,7 @@
> > #include "intel_chipset.h"
> > #include "i915_pciids.h"
> > #include "i915_pciids_local.h"
> > +#include "xe_pciids.h"
> >
> > #include <strings.h> /* ffs() */
> >
> > diff --git a/lib/xe_pciids.h b/lib/xe_pciids.h
> > new file mode 100644
> > index 000000000..29f07a00a
> > --- /dev/null
> > +++ b/lib/xe_pciids.h
> > @@ -0,0 +1,215 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2022 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_PCIIDS_H_
> > +#define _XE_PCIIDS_H_
> > +
> > +/*
> > + * Lists below can be turned into initializers for a struct pci_device_id
> > + * by defining INTEL_VGA_DEVICE:
> > + *
> > + * #define INTEL_VGA_DEVICE(id, info) { \
> > + * 0x8086, id, \
> > + * ~0, ~0, \
> > + * 0x030000, 0xff0000, \
> > + * (unsigned long) info }
> > + *
> > + * And then calling like:
> > + *
> > + * XE_TGL_12_GT1_IDS(INTEL_VGA_DEVICE, ## __VA_ARGS__)
> > + *
> > + * To turn them into something else, just provide a different macro passed as
> > + * first argument.
> > + */
> > +
> > +/* TGL */
> > +#define XE_TGL_GT1_IDS(MACRO__, ...) \
> > + MACRO__(0x9A60, ## __VA_ARGS__), \
> > + MACRO__(0x9A68, ## __VA_ARGS__), \
> > + MACRO__(0x9A70, ## __VA_ARGS__)
> > +
> > +#define XE_TGL_GT2_IDS(MACRO__, ...) \
> > + MACRO__(0x9A40, ## __VA_ARGS__), \
> > + MACRO__(0x9A49, ## __VA_ARGS__), \
> > + MACRO__(0x9A59, ## __VA_ARGS__), \
> > + MACRO__(0x9A78, ## __VA_ARGS__), \
> > + MACRO__(0x9AC0, ## __VA_ARGS__), \
> > + MACRO__(0x9AC9, ## __VA_ARGS__), \
> > + MACRO__(0x9AD9, ## __VA_ARGS__), \
> > + MACRO__(0x9AF8, ## __VA_ARGS__)
> > +
> > +#define XE_TGL_IDS(MACRO__, ...) \
> > + XE_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__),\
> > + XE_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__)
> > +
> > +/* RKL */
> > +#define XE_RKL_IDS(MACRO__, ...) \
> > + MACRO__(0x4C80, ## __VA_ARGS__), \
> > + MACRO__(0x4C8A, ## __VA_ARGS__), \
> > + MACRO__(0x4C8B, ## __VA_ARGS__), \
> > + MACRO__(0x4C8C, ## __VA_ARGS__), \
> > + MACRO__(0x4C90, ## __VA_ARGS__), \
> > + MACRO__(0x4C9A, ## __VA_ARGS__)
> > +
> > +/* DG1 */
> > +#define XE_DG1_IDS(MACRO__, ...) \
> > + MACRO__(0x4905, ## __VA_ARGS__), \
> > + MACRO__(0x4906, ## __VA_ARGS__), \
> > + MACRO__(0x4907, ## __VA_ARGS__), \
> > + MACRO__(0x4908, ## __VA_ARGS__), \
> > + MACRO__(0x4909, ## __VA_ARGS__)
> > +
> > +/* ADL-S */
> > +#define XE_ADLS_IDS(MACRO__, ...) \
> > + MACRO__(0x4680, ## __VA_ARGS__), \
> > + MACRO__(0x4682, ## __VA_ARGS__), \
> > + MACRO__(0x4688, ## __VA_ARGS__), \
> > + MACRO__(0x468A, ## __VA_ARGS__), \
> > + MACRO__(0x4690, ## __VA_ARGS__), \
> > + MACRO__(0x4692, ## __VA_ARGS__), \
> > + MACRO__(0x4693, ## __VA_ARGS__)
> > +
> > +/* ADL-P */
> > +#define XE_ADLP_IDS(MACRO__, ...) \
> > + MACRO__(0x46A0, ## __VA_ARGS__), \
> > + MACRO__(0x46A1, ## __VA_ARGS__), \
> > + MACRO__(0x46A2, ## __VA_ARGS__), \
> > + MACRO__(0x46A3, ## __VA_ARGS__), \
> > + MACRO__(0x46A6, ## __VA_ARGS__), \
> > + MACRO__(0x46A8, ## __VA_ARGS__), \
> > + MACRO__(0x46AA, ## __VA_ARGS__), \
> > + MACRO__(0x462A, ## __VA_ARGS__), \
> > + MACRO__(0x4626, ## __VA_ARGS__), \
> > + MACRO__(0x4628, ## __VA_ARGS__), \
> > + MACRO__(0x46B0, ## __VA_ARGS__), \
> > + MACRO__(0x46B1, ## __VA_ARGS__), \
> > + MACRO__(0x46B2, ## __VA_ARGS__), \
> > + MACRO__(0x46B3, ## __VA_ARGS__), \
> > + MACRO__(0x46C0, ## __VA_ARGS__), \
> > + MACRO__(0x46C1, ## __VA_ARGS__), \
> > + MACRO__(0x46C2, ## __VA_ARGS__), \
> > + MACRO__(0x46C3, ## __VA_ARGS__)
> > +
> > +/* ADL-N */
> > +#define XE_ADLN_IDS(MACRO__, ...) \
> > + MACRO__(0x46D0, ## __VA_ARGS__), \
> > + MACRO__(0x46D1, ## __VA_ARGS__), \
> > + MACRO__(0x46D2, ## __VA_ARGS__)
> > +
> > +/* RPL-S */
> > +#define XE_RPLS_IDS(MACRO__, ...) \
> > + MACRO__(0xA780, ## __VA_ARGS__), \
> > + MACRO__(0xA781, ## __VA_ARGS__), \
> > + MACRO__(0xA782, ## __VA_ARGS__), \
> > + MACRO__(0xA783, ## __VA_ARGS__), \
> > + MACRO__(0xA788, ## __VA_ARGS__), \
> > + MACRO__(0xA789, ## __VA_ARGS__), \
> > + MACRO__(0xA78A, ## __VA_ARGS__), \
> > + MACRO__(0xA78B, ## __VA_ARGS__)
> > +
> > +/* RPL-U */
> > +#define XE_RPLU_IDS(MACRO__, ...) \
> > + MACRO__(0xA721, ## __VA_ARGS__), \
> > + MACRO__(0xA7A1, ## __VA_ARGS__), \
> > + MACRO__(0xA7A9, ## __VA_ARGS__)
> > +
> > +/* RPL-P */
> > +#define XE_RPLP_IDS(MACRO__, ...) \
> > + MACRO__(0xA720, ## __VA_ARGS__), \
> > + MACRO__(0xA7A0, ## __VA_ARGS__), \
> > + MACRO__(0xA7A8, ## __VA_ARGS__)
> > +
> > +/* DG2 */
> > +#define XE_DG2_G10_IDS(MACRO__, ...) \
> > + MACRO__(0x5690, ## __VA_ARGS__), \
> > + MACRO__(0x5691, ## __VA_ARGS__), \
> > + MACRO__(0x5692, ## __VA_ARGS__), \
> > + MACRO__(0x56A0, ## __VA_ARGS__), \
> > + MACRO__(0x56A1, ## __VA_ARGS__), \
> > + MACRO__(0x56A2, ## __VA_ARGS__)
> > +
> > +#define XE_DG2_G11_IDS(MACRO__, ...) \
> > + MACRO__(0x5693, ## __VA_ARGS__), \
> > + MACRO__(0x5694, ## __VA_ARGS__), \
> > + MACRO__(0x5695, ## __VA_ARGS__), \
> > + MACRO__(0x5698, ## __VA_ARGS__), \
> > + MACRO__(0x56A5, ## __VA_ARGS__), \
> > + MACRO__(0x56A6, ## __VA_ARGS__), \
> > + MACRO__(0x56B0, ## __VA_ARGS__), \
> > + MACRO__(0x56B1, ## __VA_ARGS__)
> > +
> > +#define XE_DG2_G12_IDS(MACRO__, ...) \
> > + MACRO__(0x5696, ## __VA_ARGS__), \
> > + MACRO__(0x5697, ## __VA_ARGS__), \
> > + MACRO__(0x56A3, ## __VA_ARGS__), \
> > + MACRO__(0x56A4, ## __VA_ARGS__), \
> > + MACRO__(0x56B2, ## __VA_ARGS__), \
> > + MACRO__(0x56B3, ## __VA_ARGS__)
> > +
> > +#define XE_DG2_IDS(MACRO__, ...) \
> > + XE_DG2_G10_IDS(MACRO__, ## __VA_ARGS__),\
> > + XE_DG2_G11_IDS(MACRO__, ## __VA_ARGS__),\
> > + XE_DG2_G12_IDS(MACRO__, ## __VA_ARGS__)
> > +
> > +#define XE_ATS_M150_IDS(MACRO__, ...) \
> > + MACRO__(0x56C0, ## __VA_ARGS__)
> > +
> > +#define XE_ATS_M75_IDS(MACRO__, ...) \
> > + MACRO__(0x56C1, ## __VA_ARGS__)
> > +
> > +#define XE_ATS_M_IDS(MACRO__, ...) \
> > + XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\
> > + XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__)
> > +
> > +/* PVC */
> > +#define XE_PVC_XT_IDS(MACRO__, ...) \
> > + MACRO__(0x0BD5, ## __VA_ARGS__), \
> > + MACRO__(0x0BD6, ## __VA_ARGS__), \
> > + MACRO__(0x0BD7, ## __VA_ARGS__), \
> > + MACRO__(0x0BD8, ## __VA_ARGS__), \
> > + MACRO__(0x0BD9, ## __VA_ARGS__), \
> > + MACRO__(0x0BDA, ## __VA_ARGS__), \
> > + MACRO__(0x0BDB, ## __VA_ARGS__), \
> > + MACRO__(0x0BE0, ## __VA_ARGS__), \
> > + MACRO__(0x0BE1, ## __VA_ARGS__), \
> > + MACRO__(0x0BE5, ## __VA_ARGS__)
> > +
> > +#define XE_PVC_IDS(MACRO__, ...) \
> > + XE_PVC_XT_IDS(MACRO__, ## __VA_ARGS__)
> > +
> > +/* MTL */
> > +#define XE_MTL_M_IDS(MACRO__, ...) \
> > + MACRO__(0x7D40, ## __VA_ARGS__), \
> > + MACRO__(0x7D43, ## __VA_ARGS__), \
> > + MACRO__(0x7DC0, ## __VA_ARGS__)
> > +
> > +#define XE_MTL_P_IDS(MACRO__, ...) \
> > + MACRO__(0x7D45, ## __VA_ARGS__), \
> > + MACRO__(0x7D47, ## __VA_ARGS__), \
> > + MACRO__(0x7D50, ## __VA_ARGS__), \
> > + MACRO__(0x7D55, ## __VA_ARGS__), \
> > + MACRO__(0x7DC5, ## __VA_ARGS__), \
> > + MACRO__(0x7DD0, ## __VA_ARGS__), \
> > + MACRO__(0x7DD5, ## __VA_ARGS__)
> > +
> > +#define XE_MTL_S_IDS(MACRO__, ...) \
> > + MACRO__(0x7D60, ## __VA_ARGS__), \
> > + MACRO__(0x7DE0, ## __VA_ARGS__)
> > +
> > +#define XE_ARL_IDS(MACRO__, ...) \
> > + MACRO__(0x7D67, ## __VA_ARGS__)
> > +
> > +#define XE_MTL_IDS(MACRO__, ...) \
> > + XE_MTL_M_IDS(MACRO__, ## __VA_ARGS__), \
> > + XE_MTL_P_IDS(MACRO__, ## __VA_ARGS__), \
> > + XE_MTL_S_IDS(MACRO__, ## __VA_ARGS__), \
> > + XE_ARL_IDS(MACRO__, ## __VA_ARGS__)
> > +
> > +#define XE_LNL_IDS(MACRO__, ...) \
> > + MACRO__(0x6420, ## __VA_ARGS__), \
> > + MACRO__(0x64A0, ## __VA_ARGS__), \
> > + MACRO__(0x64B0, ## __VA_ARGS__)
> > +
> > +#endif
> > --
> > 2.40.1
> >
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-xe] [PATCH igt 2/4] lib/intel_chipset: Add Lunar Lake support
2023-08-31 6:48 ` [igt-dev] " Balasubramani Vivekanandan
@ 2023-08-31 17:15 ` Matt Roper
-1 siblings, 0 replies; 35+ messages in thread
From: Matt Roper @ 2023-08-31 17:15 UTC (permalink / raw)
To: Balasubramani Vivekanandan
Cc: igt-dev, Lucas De Marchi, intel-xe, Swati Sharma
On Thu, Aug 31, 2023 at 12:18:22PM +0530, Balasubramani Vivekanandan wrote:
> On 29.08.2023 07:11, Lucas De Marchi wrote:
> > Add basic definition for the Lunar Lake platform. This uses the PCI ID
> > from the xe_pciids.h which has a macro in a slighlty different form.
> >
> > Going forward we could also trim down a little bit the the info struct
> > like was done in the kernel, relying on gmdid and IP version checks.
> > This is left for later.
> >
> > Cc: Swati Sharma <swati2.sharma@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > lib/intel_chipset.h | 5 +++++
> > lib/intel_device_info.c | 12 ++++++++++++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> > index 84cf1799e..52b15ccea 100644
> > --- a/lib/intel_chipset.h
> > +++ b/lib/intel_chipset.h
> > @@ -46,6 +46,7 @@ struct intel_device_info {
> > bool has_4tile : 1;
> > bool has_flatccs : 1;
> > bool has_oam : 1;
> > + bool has_gmdid : 1;
> > bool is_mobile : 1;
> > bool is_whitney : 1;
> > bool is_almador : 1;
> > @@ -90,6 +91,7 @@ struct intel_device_info {
> > bool is_alderlake_n : 1;
> > bool is_meteorlake : 1;
> > bool is_pontevecchio : 1;
> > + bool is_lunarlake : 1;
> > const struct intel_cmds_info *cmds_info;
> > const char *codename;
> > };
> > @@ -203,6 +205,7 @@ void intel_check_pch(void);
> > #define IS_ALDERLAKE_N(devid) (intel_get_device_info(devid)->is_alderlake_n)
> > #define IS_METEORLAKE(devid) (intel_get_device_info(devid)->is_meteorlake)
> > #define IS_PONTEVECCHIO(devid) (intel_get_device_info(devid)->is_pontevecchio)
> > +#define IS_LUNARLAKE(devid) (intel_get_device_info(devid)->is_lunarlake)
> >
> > #define IS_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver == x)
> > #define AT_LEAST_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver >= x)
> > @@ -236,4 +239,6 @@ void intel_check_pch(void);
> >
> > #define HAS_OAM(devid) (intel_get_device_info(devid)->has_oam)
> >
> > +#define HAS_GMDID(devid) (intel_get_device_info(devid)->has_gmdid)
> > +
> > #endif /* _INTEL_CHIPSET_H */
> > diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> > index 5d53d2906..86a8b3650 100644
> > --- a/lib/intel_device_info.c
> > +++ b/lib/intel_device_info.c
> > @@ -504,6 +504,16 @@ static const struct intel_device_info intel_pontevecchio_info = {
> > .cmds_info = &gen12_pvc_cmds_info,
> > };
> >
> > +static const struct intel_device_info intel_lunarlake_info = {
> > + .graphics_ver = 20,
> > + .graphics_rel = 4,
> > + .display_ver = 20,
> > + .has_4tile = true,
> > + .has_gmdid = true,
>
> has_gmdid should be set true even for Meteorlake. If not in this patch,
> in a follow up.
Yeah, we probably shouldn't even be introducing has_gmdid / HAS_GMDID in
this patch since it isn't used anywhere yet (and since userspace doesn't
have any interface to query the GMD_ID values from yet). That support
should probably come in a separate series, and be paired with XeKMD
changes that allow userspace to access those values.
Matt
>
> Regards,
> Bala
>
> > + .is_lunarlake = true,
> > + .codename = "lunarlake"
> > +};
> > +
> > static const struct pci_id_match intel_device_match[] = {
> > INTEL_I810_IDS(&intel_i810_info),
> > INTEL_I815_IDS(&intel_i815_info),
> > @@ -607,6 +617,8 @@ static const struct pci_id_match intel_device_match[] = {
> >
> > INTEL_PVC_IDS(&intel_pontevecchio_info),
> >
> > + XE_LNL_IDS(INTEL_VGA_DEVICE, &intel_lunarlake_info),
> > +
> > INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
> > };
> >
> > --
> > 2.40.1
> >
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [igt-dev] [Intel-xe] [PATCH igt 2/4] lib/intel_chipset: Add Lunar Lake support
@ 2023-08-31 17:15 ` Matt Roper
0 siblings, 0 replies; 35+ messages in thread
From: Matt Roper @ 2023-08-31 17:15 UTC (permalink / raw)
To: Balasubramani Vivekanandan; +Cc: igt-dev, Lucas De Marchi, intel-xe
On Thu, Aug 31, 2023 at 12:18:22PM +0530, Balasubramani Vivekanandan wrote:
> On 29.08.2023 07:11, Lucas De Marchi wrote:
> > Add basic definition for the Lunar Lake platform. This uses the PCI ID
> > from the xe_pciids.h which has a macro in a slighlty different form.
> >
> > Going forward we could also trim down a little bit the the info struct
> > like was done in the kernel, relying on gmdid and IP version checks.
> > This is left for later.
> >
> > Cc: Swati Sharma <swati2.sharma@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > lib/intel_chipset.h | 5 +++++
> > lib/intel_device_info.c | 12 ++++++++++++
> > 2 files changed, 17 insertions(+)
> >
> > diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
> > index 84cf1799e..52b15ccea 100644
> > --- a/lib/intel_chipset.h
> > +++ b/lib/intel_chipset.h
> > @@ -46,6 +46,7 @@ struct intel_device_info {
> > bool has_4tile : 1;
> > bool has_flatccs : 1;
> > bool has_oam : 1;
> > + bool has_gmdid : 1;
> > bool is_mobile : 1;
> > bool is_whitney : 1;
> > bool is_almador : 1;
> > @@ -90,6 +91,7 @@ struct intel_device_info {
> > bool is_alderlake_n : 1;
> > bool is_meteorlake : 1;
> > bool is_pontevecchio : 1;
> > + bool is_lunarlake : 1;
> > const struct intel_cmds_info *cmds_info;
> > const char *codename;
> > };
> > @@ -203,6 +205,7 @@ void intel_check_pch(void);
> > #define IS_ALDERLAKE_N(devid) (intel_get_device_info(devid)->is_alderlake_n)
> > #define IS_METEORLAKE(devid) (intel_get_device_info(devid)->is_meteorlake)
> > #define IS_PONTEVECCHIO(devid) (intel_get_device_info(devid)->is_pontevecchio)
> > +#define IS_LUNARLAKE(devid) (intel_get_device_info(devid)->is_lunarlake)
> >
> > #define IS_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver == x)
> > #define AT_LEAST_GEN(devid, x) (intel_get_device_info(devid)->graphics_ver >= x)
> > @@ -236,4 +239,6 @@ void intel_check_pch(void);
> >
> > #define HAS_OAM(devid) (intel_get_device_info(devid)->has_oam)
> >
> > +#define HAS_GMDID(devid) (intel_get_device_info(devid)->has_gmdid)
> > +
> > #endif /* _INTEL_CHIPSET_H */
> > diff --git a/lib/intel_device_info.c b/lib/intel_device_info.c
> > index 5d53d2906..86a8b3650 100644
> > --- a/lib/intel_device_info.c
> > +++ b/lib/intel_device_info.c
> > @@ -504,6 +504,16 @@ static const struct intel_device_info intel_pontevecchio_info = {
> > .cmds_info = &gen12_pvc_cmds_info,
> > };
> >
> > +static const struct intel_device_info intel_lunarlake_info = {
> > + .graphics_ver = 20,
> > + .graphics_rel = 4,
> > + .display_ver = 20,
> > + .has_4tile = true,
> > + .has_gmdid = true,
>
> has_gmdid should be set true even for Meteorlake. If not in this patch,
> in a follow up.
Yeah, we probably shouldn't even be introducing has_gmdid / HAS_GMDID in
this patch since it isn't used anywhere yet (and since userspace doesn't
have any interface to query the GMD_ID values from yet). That support
should probably come in a separate series, and be paired with XeKMD
changes that allow userspace to access those values.
Matt
>
> Regards,
> Bala
>
> > + .is_lunarlake = true,
> > + .codename = "lunarlake"
> > +};
> > +
> > static const struct pci_id_match intel_device_match[] = {
> > INTEL_I810_IDS(&intel_i810_info),
> > INTEL_I815_IDS(&intel_i815_info),
> > @@ -607,6 +617,8 @@ static const struct pci_id_match intel_device_match[] = {
> >
> > INTEL_PVC_IDS(&intel_pontevecchio_info),
> >
> > + XE_LNL_IDS(INTEL_VGA_DEVICE, &intel_lunarlake_info),
> > +
> > INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
> > };
> >
> > --
> > 2.40.1
> >
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-xe] [PATCH igt 1/4] lib: Add xe_pciids.h
2023-08-31 6:28 ` [igt-dev] " Balasubramani Vivekanandan
@ 2023-09-01 9:21 ` Lucas De Marchi
-1 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-09-01 9:21 UTC (permalink / raw)
To: Balasubramani Vivekanandan; +Cc: igt-dev, intel-xe, Rodrigo Vivi
+Rodrigo
On Thu, Aug 31, 2023 at 11:58:23AM +0530, Balasubramani Vivekanandan wrote:
>On 29.08.2023 07:11, Lucas De Marchi wrote:
>> With the introduction of Lunar Lake, igt won't be able to just re-use
>> i915_pciids.h for both drivers anymore since the support for LNL is only
>> coming with the xe module. Copy xe_pciids.h from the drm-xe-next branch
>> (up to commit b9c9020fc816 ("drm/xe/pvc: Use fast copy engines as
>> migrate engine on PVC") and start including it where needed. This brings
>> all the LNL PCI IDs.
>
>I couldn't find the commit hash b9c9020fc816. Is it lost due to rebase?
>In that case, does it make sense to use the commit hash or just keep the
>commit subject?
Rodrigo, did you tag the branch before force pushing? If so, can you
push a tag like the archive/* ones? This would allow people to see the
commit referenced, even if later we force push the branch.
Lucas De Marchi
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [igt-dev] [Intel-xe] [PATCH igt 1/4] lib: Add xe_pciids.h
@ 2023-09-01 9:21 ` Lucas De Marchi
0 siblings, 0 replies; 35+ messages in thread
From: Lucas De Marchi @ 2023-09-01 9:21 UTC (permalink / raw)
To: Balasubramani Vivekanandan; +Cc: igt-dev, intel-xe, Rodrigo Vivi
+Rodrigo
On Thu, Aug 31, 2023 at 11:58:23AM +0530, Balasubramani Vivekanandan wrote:
>On 29.08.2023 07:11, Lucas De Marchi wrote:
>> With the introduction of Lunar Lake, igt won't be able to just re-use
>> i915_pciids.h for both drivers anymore since the support for LNL is only
>> coming with the xe module. Copy xe_pciids.h from the drm-xe-next branch
>> (up to commit b9c9020fc816 ("drm/xe/pvc: Use fast copy engines as
>> migrate engine on PVC") and start including it where needed. This brings
>> all the LNL PCI IDs.
>
>I couldn't find the commit hash b9c9020fc816. Is it lost due to rebase?
>In that case, does it make sense to use the commit hash or just keep the
>commit subject?
Rodrigo, did you tag the branch before force pushing? If so, can you
push a tag like the archive/* ones? This would allow people to see the
commit referenced, even if later we force push the branch.
Lucas De Marchi
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Intel-xe] [PATCH igt 1/4] lib: Add xe_pciids.h
2023-09-01 9:21 ` [igt-dev] " Lucas De Marchi
@ 2023-09-01 12:17 ` Vivi, Rodrigo
-1 siblings, 0 replies; 35+ messages in thread
From: Vivi, Rodrigo @ 2023-09-01 12:17 UTC (permalink / raw)
To: Vivekanandan, Balasubramani, De Marchi, Lucas; +Cc: igt-dev, intel-xe
On Fri, 2023-09-01 at 02:21 -0700, Lucas De Marchi wrote:
> +Rodrigo
>
> On Thu, Aug 31, 2023 at 11:58:23AM +0530, Balasubramani Vivekanandan
> wrote:
> > On 29.08.2023 07:11, Lucas De Marchi wrote:
> > > With the introduction of Lunar Lake, igt won't be able to just
> > > re-use
> > > i915_pciids.h for both drivers anymore since the support for LNL
> > > is only
> > > coming with the xe module. Copy xe_pciids.h from the drm-xe-next
> > > branch
> > > (up to commit b9c9020fc816 ("drm/xe/pvc: Use fast copy engines as
> > > migrate engine on PVC") and start including it where needed. This
> > > brings
> > > all the LNL PCI IDs.
> >
> > I couldn't find the commit hash b9c9020fc816. Is it lost due to
> > rebase?
> > In that case, does it make sense to use the commit hash or just
> > keep the
> > commit subject?
>
> Rodrigo, did you tag the branch before force pushing? If so, can you
> push a tag like the archive/* ones? This would allow people to see
> the
> commit referenced, even if later we force push the branch.
ops, sorry for that.
The tag is there now:
drm-xe-next-2023-08-29
btw, I noticed we are using 2 different styles, should we always add
'archive/' or should we drop that?
Is there any tag that is not an archive?
>
>
> Lucas De Marchi
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [igt-dev] [Intel-xe] [PATCH igt 1/4] lib: Add xe_pciids.h
@ 2023-09-01 12:17 ` Vivi, Rodrigo
0 siblings, 0 replies; 35+ messages in thread
From: Vivi, Rodrigo @ 2023-09-01 12:17 UTC (permalink / raw)
To: Vivekanandan, Balasubramani, De Marchi, Lucas; +Cc: igt-dev, intel-xe
On Fri, 2023-09-01 at 02:21 -0700, Lucas De Marchi wrote:
> +Rodrigo
>
> On Thu, Aug 31, 2023 at 11:58:23AM +0530, Balasubramani Vivekanandan
> wrote:
> > On 29.08.2023 07:11, Lucas De Marchi wrote:
> > > With the introduction of Lunar Lake, igt won't be able to just
> > > re-use
> > > i915_pciids.h for both drivers anymore since the support for LNL
> > > is only
> > > coming with the xe module. Copy xe_pciids.h from the drm-xe-next
> > > branch
> > > (up to commit b9c9020fc816 ("drm/xe/pvc: Use fast copy engines as
> > > migrate engine on PVC") and start including it where needed. This
> > > brings
> > > all the LNL PCI IDs.
> >
> > I couldn't find the commit hash b9c9020fc816. Is it lost due to
> > rebase?
> > In that case, does it make sense to use the commit hash or just
> > keep the
> > commit subject?
>
> Rodrigo, did you tag the branch before force pushing? If so, can you
> push a tag like the archive/* ones? This would allow people to see
> the
> commit referenced, even if later we force push the branch.
ops, sorry for that.
The tag is there now:
drm-xe-next-2023-08-29
btw, I noticed we are using 2 different styles, should we always add
'archive/' or should we drop that?
Is there any tag that is not an archive?
>
>
> Lucas De Marchi
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2023-09-01 12:18 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-08-29 14:11 [Intel-xe] [PATCH igt 0/4] Add LNL support to xe tests Lucas De Marchi
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
2023-08-29 14:11 ` [Intel-xe] [PATCH igt 1/4] lib: Add xe_pciids.h Lucas De Marchi
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
2023-08-31 6:28 ` [Intel-xe] " Balasubramani Vivekanandan
2023-08-31 6:28 ` [igt-dev] " Balasubramani Vivekanandan
2023-08-31 6:55 ` Balasubramani Vivekanandan
2023-08-31 6:55 ` [igt-dev] " Balasubramani Vivekanandan
2023-09-01 9:21 ` Lucas De Marchi
2023-09-01 9:21 ` [igt-dev] " Lucas De Marchi
2023-09-01 12:17 ` Vivi, Rodrigo
2023-09-01 12:17 ` [igt-dev] " Vivi, Rodrigo
2023-08-29 14:11 ` [Intel-xe] [PATCH igt 2/4] lib/intel_chipset: Add Lunar Lake support Lucas De Marchi
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
2023-08-31 6:48 ` [Intel-xe] " Balasubramani Vivekanandan
2023-08-31 6:48 ` [igt-dev] " Balasubramani Vivekanandan
2023-08-31 6:51 ` Balasubramani Vivekanandan
2023-08-31 6:51 ` [igt-dev] " Balasubramani Vivekanandan
2023-08-31 17:15 ` Matt Roper
2023-08-31 17:15 ` [igt-dev] " Matt Roper
2023-08-29 14:11 ` [Intel-xe] [PATCH igt 3/4] lib/intel_device_info: Add blitter cmd info for Lunar Lake Lucas De Marchi
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
2023-08-30 23:48 ` [Intel-xe] " Srivatsa, Anusha
2023-08-30 23:48 ` Srivatsa, Anusha
2023-08-29 14:11 ` [Intel-xe] [PATCH igt 4/4] tests/xe_debugfs: skip page table level check for Xe2 Lucas De Marchi
2023-08-29 14:11 ` [igt-dev] " Lucas De Marchi
2023-08-30 23:50 ` [Intel-xe] " Srivatsa, Anusha
2023-08-30 23:50 ` Srivatsa, Anusha
2023-08-29 14:26 ` [igt-dev] ✗ GitLab.Pipeline: warning for Add LNL support to xe tests Patchwork
2023-08-29 14:59 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
2023-08-29 15:26 ` [igt-dev] ✓ CI.xeBAT: " Patchwork
2023-08-29 15:28 ` [Intel-xe] ✗ CI.Patch_applied: failure " Patchwork
2023-08-29 21:38 ` [igt-dev] ✗ Fi.CI.IGT: " Patchwork
2023-08-30 21:07 ` [Intel-xe] [PATCH igt 0/4] " Rodrigo Vivi
2023-08-30 21:07 ` [igt-dev] " Rodrigo Vivi
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.