* [Intel-xe] ✓ CI.Patch_applied: success for Add HWMON support for DGFX (rev5)
2023-09-21 10:25 ` Badal Nilawar
(?)
@ 2023-09-21 10:21 ` Patchwork
-1 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2023-09-21 10:21 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
== Series Details ==
Series: Add HWMON support for DGFX (rev5)
URL : https://patchwork.freedesktop.org/series/118934/
State : success
== Summary ==
=== Applying kernel patches on branch 'drm-xe-next' with base: ===
Base commit: 57039c55b fixup! drm/xe/bo: Evict VRAM to TT rather than to system
=== git am output follows ===
.git/rebase-apply/patch:43: new blank line at EOF.
+
.git/rebase-apply/patch:507: new blank line at EOF.
+
warning: 2 lines add whitespace errors.
.git/rebase-apply/patch:41: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
.git/rebase-apply/patch:24: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
Applying: drm/xe: Add XE_MISSING_CASE macro
Applying: drm/xe/hwmon: Expose power attributes
Applying: drm/xe/hwmon: Expose card reactive critical power
Applying: drm/xe/hwmon: Expose input voltage attribute
Applying: drm/xe/hwmon: Expose hwmon energy attribute
Applying: drm/xe/hwmon: Expose power1_max_interval
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-xe] ✗ CI.checkpatch: warning for Add HWMON support for DGFX (rev5)
2023-09-21 10:25 ` Badal Nilawar
(?)
(?)
@ 2023-09-21 10:21 ` Patchwork
-1 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2023-09-21 10:21 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
== Series Details ==
Series: Add HWMON support for DGFX (rev5)
URL : https://patchwork.freedesktop.org/series/118934/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
63c2b6b160bca2df6efc7bc4cea6f442097d7854
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 6623782667f2423737f0a3df93bde8e3ff639a6e
Author: Badal Nilawar <badal.nilawar@intel.com>
Date: Thu Sep 21 15:55:19 2023 +0530
drm/xe/hwmon: Expose power1_max_interval
Expose power1_max_interval, that is the tau corresponding to PL1, as a
custom hwmon attribute. Some bit manipulation is needed because of the
format of PKG_PWR_LIM_1_TIME in
PACKAGE_RAPL_LIMIT register (1.x * power(2,y))
v2: Get rpm wake ref while accessing power1_max_interval
v3: %s/hwmon/xe_hwmon/
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
+ /mt/dim checkpatch 57039c55bac31a639ce66355c26fe345f338c075 drm-intel
a26e2637c drm/xe: Add XE_MISSING_CASE macro
d50bb8d1c drm/xe/hwmon: Expose power attributes
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 6, in <module>
from ply import lex, yacc
ModuleNotFoundError: No module named 'ply'
-:28: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 473 lines checked
ded4ac88b drm/xe/hwmon: Expose card reactive critical power
88a517751 drm/xe/hwmon: Expose input voltage attribute
e25dd62d1 drm/xe/hwmon: Expose hwmon energy attribute
662378266 drm/xe/hwmon: Expose power1_max_interval
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-xe] ✓ CI.KUnit: success for Add HWMON support for DGFX (rev5)
2023-09-21 10:25 ` Badal Nilawar
` (2 preceding siblings ...)
(?)
@ 2023-09-21 10:23 ` Patchwork
-1 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2023-09-21 10:23 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
== Series Details ==
Series: Add HWMON support for DGFX (rev5)
URL : https://patchwork.freedesktop.org/series/118934/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
stty: 'standard input': Inappropriate ioctl for device
[10:21:50] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:21:54] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[10:22:14] Starting KUnit Kernel (1/1)...
[10:22:14] ============================================================
[10:22:14] ==================== xe_bo (2 subtests) ====================
[10:22:14] [SKIPPED] xe_ccs_migrate_kunit
[10:22:14] [SKIPPED] xe_bo_evict_kunit
[10:22:14] ===================== [SKIPPED] xe_bo ======================
[10:22:14] ================== xe_dma_buf (1 subtest) ==================
[10:22:14] [SKIPPED] xe_dma_buf_kunit
[10:22:14] =================== [SKIPPED] xe_dma_buf ===================
[10:22:14] ================== xe_migrate (1 subtest) ==================
[10:22:14] [SKIPPED] xe_migrate_sanity_kunit
[10:22:14] =================== [SKIPPED] xe_migrate ===================
[10:22:14] =================== xe_pci (2 subtests) ====================
[10:22:14] [PASSED] xe_gmdid_graphics_ip
[10:22:14] [PASSED] xe_gmdid_media_ip
[10:22:14] ===================== [PASSED] xe_pci ======================
[10:22:14] ==================== xe_rtp (1 subtest) ====================
[10:22:14] ================== xe_rtp_process_tests ===================
[10:22:14] [PASSED] coalesce-same-reg
[10:22:14] [PASSED] no-match-no-add
[10:22:14] [PASSED] no-match-no-add-multiple-rules
[10:22:14] [PASSED] two-regs-two-entries
[10:22:14] [PASSED] clr-one-set-other
[10:22:14] [PASSED] set-field
[10:22:14] [PASSED] conflict-duplicate
[10:22:14] [PASSED] conflict-not-disjoint
[10:22:14] [PASSED] conflict-reg-type
[10:22:14] ============== [PASSED] xe_rtp_process_tests ===============
[10:22:14] ===================== [PASSED] xe_rtp ======================
[10:22:14] ==================== xe_wa (1 subtest) =====================
[10:22:14] ======================== xe_wa_gt =========================
[10:22:14] [PASSED] TIGERLAKE (B0)
[10:22:14] [PASSED] DG1 (A0)
[10:22:14] [PASSED] DG1 (B0)
[10:22:14] [PASSED] ALDERLAKE_S (A0)
[10:22:14] [PASSED] ALDERLAKE_S (B0)
[10:22:14] [PASSED] ALDERLAKE_S (C0)
[10:22:14] [PASSED] ALDERLAKE_S (D0)
[10:22:14] [PASSED] ALDERLAKE_P (A0)
[10:22:14] [PASSED] ALDERLAKE_P (B0)
[10:22:14] [PASSED] ALDERLAKE_P (C0)
[10:22:14] [PASSED] DG2_G10 (A0)
[10:22:14] [PASSED] DG2_G10 (A1)
[10:22:14] [PASSED] DG2_G10 (B0)
[10:22:14] [PASSED] DG2_G10 (C0)
[10:22:14] [PASSED] DG2_G11 (A0)
[10:22:14] [PASSED] DG2_G11 (B0)
[10:22:14] [PASSED] DG2_G11 (B1)
[10:22:14] [PASSED] DG2_G12 (A0)
[10:22:14] [PASSED] DG2_G12 (A1)
[10:22:14] [PASSED] PVC (B0)
[10:22:14] [PASSED] PVC (B1)
[10:22:14] [PASSED] PVC (C0)
[10:22:14] ==================== [PASSED] xe_wa_gt =====================
[10:22:14] ====================== [PASSED] xe_wa ======================
[10:22:14] ============================================================
[10:22:14] Testing complete. Ran 37 tests: passed: 33, skipped: 4
[10:22:14] Elapsed time: 23.981s total, 4.209s configuring, 19.602s building, 0.145s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[10:22:14] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[10:22:16] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make ARCH=um O=.kunit --jobs=48
[10:22:35] Starting KUnit Kernel (1/1)...
[10:22:35] ============================================================
[10:22:35] ============ drm_test_pick_cmdline (2 subtests) ============
[10:22:35] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[10:22:35] =============== drm_test_pick_cmdline_named ===============
[10:22:35] [PASSED] NTSC
[10:22:35] [PASSED] NTSC-J
[10:22:35] [PASSED] PAL
[10:22:35] [PASSED] PAL-M
[10:22:35] =========== [PASSED] drm_test_pick_cmdline_named ===========
[10:22:35] ============== [PASSED] drm_test_pick_cmdline ==============
[10:22:35] ================== drm_buddy (6 subtests) ==================
[10:22:35] [PASSED] drm_test_buddy_alloc_limit
[10:22:35] [PASSED] drm_test_buddy_alloc_range
[10:22:35] [PASSED] drm_test_buddy_alloc_optimistic
[10:22:35] [PASSED] drm_test_buddy_alloc_pessimistic
[10:22:35] [PASSED] drm_test_buddy_alloc_smoke
[10:22:35] [PASSED] drm_test_buddy_alloc_pathological
[10:22:35] ==================== [PASSED] drm_buddy ====================
[10:22:35] ============= drm_cmdline_parser (40 subtests) =============
[10:22:35] [PASSED] drm_test_cmdline_force_d_only
[10:22:35] [PASSED] drm_test_cmdline_force_D_only_dvi
[10:22:35] [PASSED] drm_test_cmdline_force_D_only_hdmi
[10:22:35] [PASSED] drm_test_cmdline_force_D_only_not_digital
[10:22:35] [PASSED] drm_test_cmdline_force_e_only
[10:22:35] [PASSED] drm_test_cmdline_res
[10:22:35] [PASSED] drm_test_cmdline_res_vesa
[10:22:35] [PASSED] drm_test_cmdline_res_vesa_rblank
[10:22:35] [PASSED] drm_test_cmdline_res_rblank
[10:22:35] [PASSED] drm_test_cmdline_res_bpp
[10:22:35] [PASSED] drm_test_cmdline_res_refresh
[10:22:35] [PASSED] drm_test_cmdline_res_bpp_refresh
[10:22:35] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[10:22:35] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[10:22:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[10:22:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[10:22:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[10:22:35] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[10:22:35] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[10:22:35] [PASSED] drm_test_cmdline_res_margins_force_on
[10:22:35] [PASSED] drm_test_cmdline_res_vesa_margins
[10:22:35] [PASSED] drm_test_cmdline_name
[10:22:35] [PASSED] drm_test_cmdline_name_bpp
[10:22:35] [PASSED] drm_test_cmdline_name_option
[10:22:35] [PASSED] drm_test_cmdline_name_bpp_option
[10:22:35] [PASSED] drm_test_cmdline_rotate_0
[10:22:35] [PASSED] drm_test_cmdline_rotate_90
[10:22:35] [PASSED] drm_test_cmdline_rotate_180
[10:22:35] [PASSED] drm_test_cmdline_rotate_270
[10:22:35] [PASSED] drm_test_cmdline_hmirror
[10:22:35] [PASSED] drm_test_cmdline_vmirror
[10:22:35] [PASSED] drm_test_cmdline_margin_options
[10:22:35] [PASSED] drm_test_cmdline_multiple_options
[10:22:35] [PASSED] drm_test_cmdline_bpp_extra_and_option
[10:22:35] [PASSED] drm_test_cmdline_extra_and_option
[10:22:35] [PASSED] drm_test_cmdline_freestanding_options
[10:22:35] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[10:22:35] [PASSED] drm_test_cmdline_panel_orientation
[10:22:35] ================ drm_test_cmdline_invalid =================
[10:22:35] [PASSED] margin_only
[10:22:35] [PASSED] interlace_only
[10:22:35] [PASSED] res_missing_x
[10:22:35] [PASSED] res_missing_y
[10:22:35] [PASSED] res_bad_y
[10:22:35] [PASSED] res_missing_y_bpp
[10:22:35] [PASSED] res_bad_bpp
[10:22:35] [PASSED] res_bad_refresh
[10:22:35] [PASSED] res_bpp_refresh_force_on_off
[10:22:35] [PASSED] res_invalid_mode
[10:22:35] [PASSED] res_bpp_wrong_place_mode
[10:22:35] [PASSED] name_bpp_refresh
[10:22:35] [PASSED] name_refresh
[10:22:35] [PASSED] name_refresh_wrong_mode
[10:22:35] [PASSED] name_refresh_invalid_mode
[10:22:35] [PASSED] rotate_multiple
[10:22:35] [PASSED] rotate_invalid_val
[10:22:35] [PASSED] rotate_truncated
[10:22:35] [PASSED] invalid_option
[10:22:35] [PASSED] invalid_tv_option
[10:22:35] [PASSED] truncated_tv_option
[10:22:35] ============ [PASSED] drm_test_cmdline_invalid =============
[10:22:35] =============== drm_test_cmdline_tv_options ===============
[10:22:35] [PASSED] NTSC
[10:22:35] [PASSED] NTSC_443
[10:22:35] [PASSED] NTSC_J
[10:22:35] [PASSED] PAL
[10:22:35] [PASSED] PAL_M
[10:22:35] [PASSED] PAL_N
[10:22:35] [PASSED] SECAM
[10:22:35] =========== [PASSED] drm_test_cmdline_tv_options ===========
[10:22:35] =============== [PASSED] drm_cmdline_parser ================
[10:22:35] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[10:22:35] ========== drm_test_get_tv_mode_from_name_valid ===========
[10:22:35] [PASSED] NTSC
[10:22:35] [PASSED] NTSC-443
[10:22:35] [PASSED] NTSC-J
[10:22:35] [PASSED] PAL
[10:22:35] [PASSED] PAL-M
[10:22:35] [PASSED] PAL-N
[10:22:35] [PASSED] SECAM
[10:22:35] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[10:22:35] [PASSED] drm_test_get_tv_mode_from_name_truncated
[10:22:35] ============ [PASSED] drm_get_tv_mode_from_name ============
[10:22:35] ============= drm_damage_helper (21 subtests) ==============
[10:22:35] [PASSED] drm_test_damage_iter_no_damage
[10:22:35] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[10:22:35] [PASSED] drm_test_damage_iter_no_damage_src_moved
[10:22:35] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[10:22:35] [PASSED] drm_test_damage_iter_no_damage_not_visible
[10:22:35] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[10:22:35] [PASSED] drm_test_damage_iter_no_damage_no_fb
[10:22:35] [PASSED] drm_test_damage_iter_simple_damage
[10:22:35] [PASSED] drm_test_damage_iter_single_damage
[10:22:35] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[10:22:35] [PASSED] drm_test_damage_iter_single_damage_outside_src
[10:22:35] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[10:22:35] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[10:22:35] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[10:22:35] [PASSED] drm_test_damage_iter_single_damage_src_moved
[10:22:35] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[10:22:35] [PASSED] drm_test_damage_iter_damage
[10:22:35] [PASSED] drm_test_damage_iter_damage_one_intersect
[10:22:35] [PASSED] drm_test_damage_iter_damage_one_outside
[10:22:35] [PASSED] drm_test_damage_iter_damage_src_moved
[10:22:35] [PASSED] drm_test_damage_iter_damage_not_visible
[10:22:35] ================ [PASSED] drm_damage_helper ================
[10:22:35] ============== drm_dp_mst_helper (2 subtests) ==============
[10:22:35] ============== drm_test_dp_mst_calc_pbn_mode ==============
[10:22:35] [PASSED] Clock 154000 BPP 30 DSC disabled
[10:22:35] [PASSED] Clock 234000 BPP 30 DSC disabled
[10:22:35] [PASSED] Clock 297000 BPP 24 DSC disabled
[10:22:35] [PASSED] Clock 332880 BPP 24 DSC enabled
[10:22:35] [PASSED] Clock 324540 BPP 24 DSC enabled
[10:22:35] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[10:22:35] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[10:22:35] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[10:22:35] [PASSED] DP_POWER_UP_PHY with port number
[10:22:35] [PASSED] DP_POWER_DOWN_PHY with port number
[10:22:35] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[10:22:35] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[10:22:35] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[10:22:35] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[10:22:35] [PASSED] DP_QUERY_PAYLOAD with port number
[10:22:35] [PASSED] DP_QUERY_PAYLOAD with VCPI
[10:22:35] [PASSED] DP_REMOTE_DPCD_READ with port number
[10:22:35] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[10:22:35] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[10:22:35] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[10:22:35] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[10:22:35] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[10:22:35] [PASSED] DP_REMOTE_I2C_READ with port number
[10:22:35] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[10:22:35] [PASSED] DP_REMOTE_I2C_READ with transactions array
[10:22:35] [PASSED] DP_REMOTE_I2C_WRITE with port number
[10:22:35] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[10:22:35] [PASSED] DP_REMOTE_I2C_WRITE with data array
[10:22:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[10:22:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[10:22:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[10:22:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[10:22:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[10:22:35] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[10:22:35] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[10:22:35] ================ [PASSED] drm_dp_mst_helper ================
[10:22:35] =========== drm_format_helper_test (11 subtests) ===========
[10:22:35] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[10:22:35] [PASSED] single_pixel_source_buffer
[10:22:35] [PASSED] single_pixel_clip_rectangle
[10:22:35] [PASSED] well_known_colors
[10:22:35] [PASSED] destination_pitch
[10:22:35] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[10:22:35] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[10:22:35] [PASSED] single_pixel_source_buffer
[10:22:35] [PASSED] single_pixel_clip_rectangle
[10:22:35] [PASSED] well_known_colors
[10:22:35] [PASSED] destination_pitch
[10:22:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[10:22:35] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[10:22:35] [PASSED] single_pixel_source_buffer
[10:22:35] [PASSED] single_pixel_clip_rectangle
[10:22:35] [PASSED] well_known_colors
[10:22:35] [PASSED] destination_pitch
[10:22:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[10:22:35] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[10:22:35] [PASSED] single_pixel_source_buffer
[10:22:35] [PASSED] single_pixel_clip_rectangle
[10:22:35] [PASSED] well_known_colors
[10:22:35] [PASSED] destination_pitch
[10:22:35] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[10:22:35] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[10:22:35] [PASSED] single_pixel_source_buffer
[10:22:35] [PASSED] single_pixel_clip_rectangle
[10:22:35] [PASSED] well_known_colors
[10:22:35] [PASSED] destination_pitch
[10:22:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[10:22:35] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[10:22:35] [PASSED] single_pixel_source_buffer
[10:22:35] [PASSED] single_pixel_clip_rectangle
[10:22:35] [PASSED] well_known_colors
[10:22:35] [PASSED] destination_pitch
[10:22:35] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[10:22:35] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[10:22:35] [PASSED] single_pixel_source_buffer
[10:22:35] [PASSED] single_pixel_clip_rectangle
[10:22:35] [PASSED] well_known_colors
[10:22:35] [PASSED] destination_pitch
[10:22:35] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[10:22:35] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[10:22:35] [PASSED] single_pixel_source_buffer
[10:22:35] [PASSED] single_pixel_clip_rectangle
[10:22:35] [PASSED] well_known_colors
[10:22:35] [PASSED] destination_pitch
[10:22:35] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[10:22:35] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[10:22:35] [PASSED] single_pixel_source_buffer
[10:22:35] [PASSED] single_pixel_clip_rectangle
[10:22:35] [PASSED] well_known_colors
[10:22:35] [PASSED] destination_pitch
[10:22:35] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[10:22:35] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[10:22:35] [PASSED] single_pixel_source_buffer
[10:22:35] [PASSED] single_pixel_clip_rectangle
[10:22:35] [PASSED] well_known_colors
[10:22:35] [PASSED] destination_pitch
[10:22:35] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[10:22:35] ============== drm_test_fb_xrgb8888_to_mono ===============
[10:22:35] [PASSED] single_pixel_source_buffer
[10:22:35] [PASSED] single_pixel_clip_rectangle
[10:22:35] [PASSED] well_known_colors
[10:22:35] [PASSED] destination_pitch
[10:22:35] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[10:22:35] ============= [PASSED] drm_format_helper_test ==============
[10:22:35] ================= drm_format (18 subtests) =================
[10:22:35] [PASSED] drm_test_format_block_width_invalid
[10:22:35] [PASSED] drm_test_format_block_width_one_plane
[10:22:35] [PASSED] drm_test_format_block_width_two_plane
[10:22:35] [PASSED] drm_test_format_block_width_three_plane
[10:22:35] [PASSED] drm_test_format_block_width_tiled
[10:22:35] [PASSED] drm_test_format_block_height_invalid
[10:22:35] [PASSED] drm_test_format_block_height_one_plane
[10:22:35] [PASSED] drm_test_format_block_height_two_plane
[10:22:35] [PASSED] drm_test_format_block_height_three_plane
[10:22:35] [PASSED] drm_test_format_block_height_tiled
[10:22:35] [PASSED] drm_test_format_min_pitch_invalid
[10:22:35] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[10:22:35] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[10:22:35] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[10:22:35] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[10:22:35] [PASSED] drm_test_format_min_pitch_two_plane
[10:22:35] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[10:22:35] [PASSED] drm_test_format_min_pitch_tiled
[10:22:35] =================== [PASSED] drm_format ====================
[10:22:35] =============== drm_framebuffer (1 subtest) ================
[10:22:35] =============== drm_test_framebuffer_create ===============
[10:22:35] [PASSED] ABGR8888 normal sizes
[10:22:35] [PASSED] ABGR8888 max sizes
[10:22:35] [PASSED] ABGR8888 pitch greater than min required
[10:22:35] [PASSED] ABGR8888 pitch less than min required
[10:22:35] [PASSED] ABGR8888 Invalid width
[10:22:35] [PASSED] ABGR8888 Invalid buffer handle
[10:22:35] [PASSED] No pixel format
[10:22:35] [PASSED] ABGR8888 Width 0
[10:22:35] [PASSED] ABGR8888 Height 0
[10:22:35] [PASSED] ABGR8888 Out of bound height * pitch combination
[10:22:35] [PASSED] ABGR8888 Large buffer offset
[10:22:35] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[10:22:35] [PASSED] ABGR8888 Valid buffer modifier
[10:22:35] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[10:22:35] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[10:22:35] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[10:22:35] [PASSED] NV12 Normal sizes
[10:22:35] [PASSED] NV12 Max sizes
[10:22:35] [PASSED] NV12 Invalid pitch
[10:22:35] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[10:22:35] [PASSED] NV12 different modifier per-plane
[10:22:35] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[10:22:35] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[10:22:35] [PASSED] NV12 Modifier for inexistent plane
[10:22:35] [PASSED] NV12 Handle for inexistent plane
[10:22:35] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[10:22:35] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[10:22:35] [PASSED] YVU420 Normal sizes
[10:22:35] [PASSED] YVU420 Max sizes
[10:22:35] [PASSED] YVU420 Invalid pitch
[10:22:35] [PASSED] YVU420 Different pitches
[10:22:35] [PASSED] YVU420 Different buffer offsets/pitches
[10:22:35] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[10:22:35] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[10:22:35] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[10:22:35] [PASSED] YVU420 Valid modifier
[10:22:35] [PASSED] YVU420 Different modifiers per plane
[10:22:35] [PASSED] YVU420 Modifier for inexistent plane
[10:22:35] [PASSED] X0L2 Normal sizes
[10:22:35] [PASSED] X0L2 Max sizes
[10:22:35] [PASSED] X0L2 Invalid pitch
[10:22:35] [PASSED] X0L2 Pitch greater than minimum required
stty: 'standard input': Inappropriate ioctl for device
[10:22:35] [PASSED] X0L2 Handle for inexistent plane
[10:22:35] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[10:22:35] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[10:22:35] [PASSED] X0L2 Valid modifier
[10:22:35] [PASSED] X0L2 Modifier for inexistent plane
[10:22:35] =========== [PASSED] drm_test_framebuffer_create ===========
[10:22:35] ================= [PASSED] drm_framebuffer =================
[10:22:35] =============== drm-test-managed (1 subtest) ===============
[10:22:35] [PASSED] drm_test_managed_run_action
[10:22:35] ================ [PASSED] drm-test-managed =================
[10:22:35] =================== drm_mm (19 subtests) ===================
[10:22:35] [PASSED] drm_test_mm_init
[10:22:35] [PASSED] drm_test_mm_debug
[10:22:45] [PASSED] drm_test_mm_reserve
[10:22:55] [PASSED] drm_test_mm_insert
[10:22:55] [PASSED] drm_test_mm_replace
[10:22:55] [PASSED] drm_test_mm_insert_range
[10:22:55] [PASSED] drm_test_mm_frag
[10:22:55] [PASSED] drm_test_mm_align
[10:22:55] [PASSED] drm_test_mm_align32
[10:22:56] [PASSED] drm_test_mm_align64
[10:22:56] [PASSED] drm_test_mm_evict
[10:22:56] [PASSED] drm_test_mm_evict_range
[10:22:56] [PASSED] drm_test_mm_topdown
[10:22:56] [PASSED] drm_test_mm_bottomup
[10:22:56] [PASSED] drm_test_mm_lowest
[10:22:56] [PASSED] drm_test_mm_highest
[10:22:57] [PASSED] drm_test_mm_color
[10:22:57] [PASSED] drm_test_mm_color_evict
[10:22:57] [PASSED] drm_test_mm_color_evict_range
[10:22:57] ===================== [PASSED] drm_mm ======================
[10:22:57] ============= drm_modes_analog_tv (4 subtests) =============
[10:22:57] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[10:22:57] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[10:22:57] [PASSED] drm_test_modes_analog_tv_pal_576i
[10:22:57] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[10:22:57] =============== [PASSED] drm_modes_analog_tv ===============
[10:22:57] ============== drm_plane_helper (2 subtests) ===============
[10:22:57] =============== drm_test_check_plane_state ================
[10:22:57] [PASSED] clipping_simple
[10:22:57] [PASSED] clipping_rotate_reflect
[10:22:57] [PASSED] positioning_simple
[10:22:57] [PASSED] upscaling
[10:22:57] [PASSED] downscaling
[10:22:57] [PASSED] rounding1
[10:22:57] [PASSED] rounding2
[10:22:57] [PASSED] rounding3
[10:22:57] [PASSED] rounding4
[10:22:57] =========== [PASSED] drm_test_check_plane_state ============
[10:22:57] =========== drm_test_check_invalid_plane_state ============
[10:22:57] [PASSED] positioning_invalid
[10:22:57] [PASSED] upscaling_invalid
[10:22:57] [PASSED] downscaling_invalid
[10:22:57] ======= [PASSED] drm_test_check_invalid_plane_state ========
[10:22:57] ================ [PASSED] drm_plane_helper =================
[10:22:57] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[10:22:57] ====== drm_test_connector_helper_tv_get_modes_check =======
[10:22:57] [PASSED] None
[10:22:57] [PASSED] PAL
[10:22:57] [PASSED] NTSC
[10:22:57] [PASSED] Both, NTSC Default
[10:22:57] [PASSED] Both, PAL Default
[10:22:57] [PASSED] Both, NTSC Default, with PAL on command-line
[10:22:57] [PASSED] Both, PAL Default, with NTSC on command-line
[10:22:57] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[10:22:57] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[10:22:57] ================== drm_rect (9 subtests) ===================
[10:22:57] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[10:22:57] [PASSED] drm_test_rect_clip_scaled_not_clipped
[10:22:57] [PASSED] drm_test_rect_clip_scaled_clipped
[10:22:57] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[10:22:57] ================= drm_test_rect_intersect =================
[10:22:57] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[10:22:57] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[10:22:57] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[10:22:57] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[10:22:57] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[10:22:57] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[10:22:57] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[10:22:57] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[10:22:57] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[10:22:57] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[10:22:57] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[10:22:57] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[10:22:57] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[10:22:57] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[10:22:57] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[10:22:57] ============= [PASSED] drm_test_rect_intersect =============
[10:22:57] ================ drm_test_rect_calc_hscale ================
[10:22:57] [PASSED] normal use
[10:22:57] [PASSED] out of max range
[10:22:57] [PASSED] out of min range
[10:22:57] [PASSED] zero dst
[10:22:57] [PASSED] negative src
[10:22:57] [PASSED] negative dst
[10:22:57] ============ [PASSED] drm_test_rect_calc_hscale ============
[10:22:57] ================ drm_test_rect_calc_vscale ================
[10:22:57] [PASSED] normal use
[10:22:57] [PASSED] out of max range
[10:22:57] [PASSED] out of min range
[10:22:57] [PASSED] zero dst
[10:22:57] [PASSED] negative src
[10:22:57] [PASSED] negative dst
[10:22:57] ============ [PASSED] drm_test_rect_calc_vscale ============
[10:22:57] ================== drm_test_rect_rotate ===================
[10:22:57] [PASSED] reflect-x
[10:22:57] [PASSED] reflect-y
[10:22:57] [PASSED] rotate-0
[10:22:57] [PASSED] rotate-90
[10:22:57] [PASSED] rotate-180
[10:22:57] [PASSED] rotate-270
[10:22:57] ============== [PASSED] drm_test_rect_rotate ===============
[10:22:57] ================ drm_test_rect_rotate_inv =================
[10:22:57] [PASSED] reflect-x
[10:22:57] [PASSED] reflect-y
[10:22:57] [PASSED] rotate-0
[10:22:57] [PASSED] rotate-90
[10:22:57] [PASSED] rotate-180
[10:22:57] [PASSED] rotate-270
[10:22:57] ============ [PASSED] drm_test_rect_rotate_inv =============
[10:22:57] ==================== [PASSED] drm_rect =====================
[10:22:57] ================== drm_exec (7 subtests) ===================
[10:22:57] [PASSED] sanitycheck
[10:22:57] [PASSED] test_lock
[10:22:57] [PASSED] test_lock_unlock
[10:22:57] [PASSED] test_duplicates
[10:22:57] [PASSED] test_prepare
[10:22:57] [PASSED] test_prepare_array
[10:22:57] [PASSED] test_multiple_loops
[10:22:57] ==================== [PASSED] drm_exec =====================
[10:22:57] ============================================================
[10:22:57] Testing complete. Ran 340 tests: passed: 340
[10:22:57] Elapsed time: 43.481s total, 1.656s configuring, 18.997s building, 22.802s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-xe] [PATCH v5 0/6] Add HWMON support for DGFX
@ 2023-09-21 10:25 ` Badal Nilawar
0 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon; +Cc: linux, rodrigo.vivi
This series adds the hwmon support on xe driver for
DGFX. This is ported from i915 hwmon.
v3: Fix review comments (Matt Brost/Andi)
v4:
- Squashed "Add HWMON infrastructure" patch to "Expose power attributes"
- Dropped changes related to disable PL1 to boost firmware loading.
Will handle it saperate patch/series.
- Dropped changes related to gt specific energy attributes.
Will handle gt specific energy attributes in saperate patch/series with design
change suggested by Guenter
- Fix review comments (Andi/Guenter)
v5: Rebased and clean up
Badal Nilawar (6):
drm/xe: Add XE_MISSING_CASE macro
drm/xe/hwmon: Expose power attributes
drm/xe/hwmon: Expose card reactive critical power
drm/xe/hwmon: Expose input voltage attribute
drm/xe/hwmon: Expose hwmon energy attribute
drm/xe/hwmon: Expose power1_max_interval
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 72 ++
drivers/gpu/drm/xe/Makefile | 3 +
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 9 +
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 44 +
drivers/gpu/drm/xe/xe_device.c | 3 +
drivers/gpu/drm/xe/xe_device_types.h | 2 +
drivers/gpu/drm/xe/xe_hwmon.c | 758 ++++++++++++++++++
drivers/gpu/drm/xe/xe_hwmon.h | 20 +
drivers/gpu/drm/xe/xe_macros.h | 4 +
drivers/gpu/drm/xe/xe_pcode.h | 5 +
drivers/gpu/drm/xe/xe_pcode_api.h | 7 +
11 files changed, 927 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
create mode 100644 drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
create mode 100644 drivers/gpu/drm/xe/xe_hwmon.c
create mode 100644 drivers/gpu/drm/xe/xe_hwmon.h
--
2.25.1
^ permalink raw reply [flat|nested] 53+ messages in thread
* [PATCH v5 0/6] Add HWMON support for DGFX
@ 2023-09-21 10:25 ` Badal Nilawar
0 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon
Cc: anshuman.gupta, ashutosh.dixit, linux, andi.shyti, riana.tauro,
matthew.brost, rodrigo.vivi
This series adds the hwmon support on xe driver for
DGFX. This is ported from i915 hwmon.
v3: Fix review comments (Matt Brost/Andi)
v4:
- Squashed "Add HWMON infrastructure" patch to "Expose power attributes"
- Dropped changes related to disable PL1 to boost firmware loading.
Will handle it saperate patch/series.
- Dropped changes related to gt specific energy attributes.
Will handle gt specific energy attributes in saperate patch/series with design
change suggested by Guenter
- Fix review comments (Andi/Guenter)
v5: Rebased and clean up
Badal Nilawar (6):
drm/xe: Add XE_MISSING_CASE macro
drm/xe/hwmon: Expose power attributes
drm/xe/hwmon: Expose card reactive critical power
drm/xe/hwmon: Expose input voltage attribute
drm/xe/hwmon: Expose hwmon energy attribute
drm/xe/hwmon: Expose power1_max_interval
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 72 ++
drivers/gpu/drm/xe/Makefile | 3 +
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 9 +
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 44 +
drivers/gpu/drm/xe/xe_device.c | 3 +
drivers/gpu/drm/xe/xe_device_types.h | 2 +
drivers/gpu/drm/xe/xe_hwmon.c | 758 ++++++++++++++++++
drivers/gpu/drm/xe/xe_hwmon.h | 20 +
drivers/gpu/drm/xe/xe_macros.h | 4 +
drivers/gpu/drm/xe/xe_pcode.h | 5 +
drivers/gpu/drm/xe/xe_pcode_api.h | 7 +
11 files changed, 927 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
create mode 100644 drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
create mode 100644 drivers/gpu/drm/xe/xe_hwmon.c
create mode 100644 drivers/gpu/drm/xe/xe_hwmon.h
--
2.25.1
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-xe] [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-21 10:25 ` Badal Nilawar
-1 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon; +Cc: linux, rodrigo.vivi
Add XE_MISSING_CASE macro to handle missing switch case
v2: Add comment about macro usage (Himal)
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/xe_macros.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
index daf56c846d03..6c74c69920ed 100644
--- a/drivers/gpu/drm/xe/xe_macros.h
+++ b/drivers/gpu/drm/xe/xe_macros.h
@@ -15,4 +15,8 @@
"Ioctl argument check failed at %s:%d: %s", \
__FILE__, __LINE__, #cond), 1))
+/* Parameter to macro should be a variable name */
+#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
+ __stringify(x), (long)(x))
+
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
@ 2023-09-21 10:25 ` Badal Nilawar
0 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon
Cc: anshuman.gupta, ashutosh.dixit, linux, andi.shyti, riana.tauro,
matthew.brost, rodrigo.vivi
Add XE_MISSING_CASE macro to handle missing switch case
v2: Add comment about macro usage (Himal)
Cc: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
---
drivers/gpu/drm/xe/xe_macros.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
index daf56c846d03..6c74c69920ed 100644
--- a/drivers/gpu/drm/xe/xe_macros.h
+++ b/drivers/gpu/drm/xe/xe_macros.h
@@ -15,4 +15,8 @@
"Ioctl argument check failed at %s:%d: %s", \
__FILE__, __LINE__, #cond), 1))
+/* Parameter to macro should be a variable name */
+#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
+ __stringify(x), (long)(x))
+
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-xe] [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-21 10:25 ` Badal Nilawar
-1 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon; +Cc: linux, rodrigo.vivi
Expose Card reactive sustained (pl1) power limit as power_max and
card default power limit (tdp) as power_rated_max.
v2:
- Fix review comments (Riana)
v3:
- Use drmm_mutex_init (Matt Brost)
- Print error value (Matt Brost)
- Convert enums to uppercase (Matt Brost)
- Avoid extra reg read in hwmon_is_visible function (Riana)
- Use xe_device_assert_mem_access when applicable (Matt Brost)
- Add intel-xe@lists.freedesktop.org in Documentation (Matt Brost)
v4:
- Use prefix xe_hwmon prefix for all functions (Matt Brost/Andi)
- %s/hwmon_reg/xe_hwmon_reg (Andi)
- Fix review comments (Guenter/Andi)
v5:
- Fix review comments (Riana)
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 22 ++
drivers/gpu/drm/xe/Makefile | 3 +
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 33 ++
drivers/gpu/drm/xe/xe_device.c | 3 +
drivers/gpu/drm/xe/xe_device_types.h | 2 +
drivers/gpu/drm/xe/xe_hwmon.c | 358 ++++++++++++++++++
drivers/gpu/drm/xe/xe_hwmon.h | 20 +
8 files changed, 445 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
create mode 100644 drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
create mode 100644 drivers/gpu/drm/xe/xe_hwmon.c
create mode 100644 drivers/gpu/drm/xe/xe_hwmon.h
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
new file mode 100644
index 000000000000..da0197a29fe4
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -0,0 +1,22 @@
+What: /sys/devices/.../hwmon/hwmon<i>/power1_max
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RW. Card reactive sustained (PL1) power limit in microwatts.
+
+ The power controller will throttle the operating frequency
+ if the power averaged over a window (typically seconds)
+ exceeds this limit. A read value of 0 means that the PL1
+ power limit is disabled, writing 0 disables the
+ limit. Writing values > 0 and <= TDP will enable the power limit.
+
+ Only supported for particular Intel xe graphics platforms.
+
+What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RO. Card default power limit (default TDP setting).
+
+ Only supported for particular Intel xe graphics platforms.
+
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 86c8bd4c05a3..ca77aff60d48 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -117,6 +117,9 @@ xe-y += xe_bb.o \
xe_wa.o \
xe_wopcm.o
+# graphics hardware monitoring (HWMON) support
+xe-$(CONFIG_HWMON) += xe_hwmon.o
+
# i915 Display compat #defines and #includes
subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
-I$(srctree)/$(src)/display/ext \
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index e13fbbdf6929..679cdba9f383 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -410,4 +410,8 @@
#define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
#define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
+#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
+#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
+#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
+
#endif
diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
new file mode 100644
index 000000000000..27f1d42baf6d
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_MCHBAR_REGS_H_
+#define _XE_MCHBAR_REGS_H_
+
+#include "regs/xe_reg_defs.h"
+
+/*
+ * MCHBAR mirror.
+ *
+ * This mirrors the MCHBAR MMIO space whose location is determined by
+ * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
+ * every way.
+ */
+
+#define MCHBAR_MIRROR_BASE_SNB 0x140000
+
+#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
+#define PKG_TDP GENMASK_ULL(14, 0)
+#define PKG_MIN_PWR GENMASK_ULL(30, 16)
+#define PKG_MAX_PWR GENMASK_ULL(46, 32)
+
+#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
+#define PKG_PWR_UNIT REG_GENMASK(3, 0)
+
+#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
+#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
+#define PKG_PWR_LIM_1_EN REG_BIT(15)
+
+#endif /* _XE_MCHBAR_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index b6bcb6c3482e..2acdc22a6027 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -34,6 +34,7 @@
#include "xe_vm.h"
#include "xe_vm_madvise.h"
#include "xe_wait_user_fence.h"
+#include "xe_hwmon.h"
#ifdef CONFIG_LOCKDEP
struct lockdep_map xe_device_mem_access_lockdep_map = {
@@ -337,6 +338,8 @@ int xe_device_probe(struct xe_device *xe)
xe_pmu_register(&xe->pmu);
+ xe_hwmon_register(xe);
+
err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
if (err)
return err;
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index a82f28c6a3a0..d1e319f305ef 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -365,6 +365,8 @@ struct xe_device {
/** @pmu: performance monitoring unit */
struct xe_pmu pmu;
+ struct xe_hwmon *hwmon;
+
/* private: */
#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
new file mode 100644
index 000000000000..7f4599d98541
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -0,0 +1,358 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include <linux/hwmon.h>
+
+#include <drm/drm_managed.h>
+#include "regs/xe_gt_regs.h"
+#include "regs/xe_mchbar_regs.h"
+#include "xe_device.h"
+#include "xe_gt.h"
+#include "xe_hwmon.h"
+#include "xe_mmio.h"
+
+enum xe_hwmon_reg {
+ REG_PKG_RAPL_LIMIT,
+ REG_PKG_POWER_SKU,
+ REG_PKG_POWER_SKU_UNIT,
+};
+
+enum xe_hwmon_reg_operation {
+ REG_READ,
+ REG_WRITE,
+ REG_RMW,
+};
+
+/*
+ * SF_* - scale factors for particular quantities according to hwmon spec.
+ */
+#define SF_POWER 1000000 /* microwatts */
+
+struct xe_hwmon {
+ struct device *hwmon_dev;
+ struct xe_gt *gt;
+ struct mutex hwmon_lock; /* rmw operations*/
+ int scl_shift_power;
+};
+
+static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
+{
+ struct xe_device *xe = gt_to_xe(hwmon->gt);
+ struct xe_reg reg = XE_REG(0);
+
+ switch (hwmon_reg) {
+ case REG_PKG_RAPL_LIMIT:
+ if (xe->info.platform == XE_DG2)
+ reg = PCU_CR_PACKAGE_RAPL_LIMIT;
+ else if (xe->info.platform == XE_PVC)
+ reg = PVC_GT0_PACKAGE_RAPL_LIMIT;
+ break;
+ case REG_PKG_POWER_SKU:
+ if (xe->info.platform == XE_DG2)
+ reg = PCU_CR_PACKAGE_POWER_SKU;
+ else if (xe->info.platform == XE_PVC)
+ reg = PVC_GT0_PACKAGE_POWER_SKU;
+ break;
+ case REG_PKG_POWER_SKU_UNIT:
+ if (xe->info.platform == XE_DG2)
+ reg = PCU_CR_PACKAGE_POWER_SKU_UNIT;
+ else if (xe->info.platform == XE_PVC)
+ reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;
+ break;
+ default:
+ XE_MISSING_CASE(hwmon_reg);
+ break;
+ }
+
+ return reg.raw;
+}
+
+static int xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
+ enum xe_hwmon_reg_operation operation, u32 *value,
+ u32 clr, u32 set)
+{
+ struct xe_reg reg;
+
+ reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
+
+ if (!reg.raw)
+ return -EOPNOTSUPP;
+
+ switch (operation) {
+ case REG_READ:
+ *value = xe_mmio_read32(hwmon->gt, reg);
+ return 0;
+ case REG_WRITE:
+ xe_mmio_write32(hwmon->gt, reg, *value);
+ return 0;
+ case REG_RMW:
+ *value = xe_mmio_rmw32(hwmon->gt, reg, clr, set);
+ return 0;
+ default:
+ XE_MISSING_CASE(operation);
+ return -EOPNOTSUPP;
+ }
+}
+
+int xe_hwmon_process_reg_read64(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, u64 *value)
+{
+ struct xe_reg reg;
+
+ reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
+
+ if (!reg.raw)
+ return -EOPNOTSUPP;
+
+ *value = xe_mmio_read64_2x32(hwmon->gt, reg);
+
+ return 0;
+}
+
+#define PL1_DISABLE 0
+
+/*
+ * HW allows arbitrary PL1 limits to be set but silently clamps these values to
+ * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the
+ * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
+ * clamped values when read.
+ */
+static int xe_hwmon_power_max_read(struct xe_hwmon *hwmon, long *value)
+{
+ u32 reg_val;
+ u64 reg_val64, min, max;
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val, 0, 0);
+ /* Check if PL1 limit is disabled */
+ if (!(reg_val & PKG_PWR_LIM_1_EN)) {
+ *value = PL1_DISABLE;
+ return 0;
+ }
+
+ reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);
+ *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
+
+ xe_hwmon_process_reg_read64(hwmon, REG_PKG_POWER_SKU, ®_val64);
+ min = REG_FIELD_GET(PKG_MIN_PWR, reg_val64);
+ min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
+ max = REG_FIELD_GET(PKG_MAX_PWR, reg_val64);
+ max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
+
+ if (min && max)
+ *value = clamp_t(u64, *value, min, max);
+
+ return 0;
+}
+
+static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
+{
+ u32 reg_val;
+
+ /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
+ if (value == PL1_DISABLE) {
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
+ PKG_PWR_LIM_1_EN, 0);
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
+ PKG_PWR_LIM_1_EN, 0);
+
+ if (reg_val & PKG_PWR_LIM_1_EN)
+ return -ENODEV;
+ }
+
+ /* Computation in 64-bits to avoid overflow. Round to nearest. */
+ reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
+ reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
+ PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
+
+ return 0;
+}
+
+static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
+{
+ u32 reg_val;
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ, ®_val, 0, 0);
+ reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
+ *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
+
+ return 0;
+}
+
+static const struct hwmon_channel_info *hwmon_info[] = {
+ HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
+ NULL
+};
+
+static umode_t
+xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
+{
+ switch (attr) {
+ case hwmon_power_max:
+ return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
+ case hwmon_power_rated_max:
+ return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
+ default:
+ return 0;
+ }
+}
+
+static int
+xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
+{
+ switch (attr) {
+ case hwmon_power_max:
+ return xe_hwmon_power_max_read(hwmon, val);
+ case hwmon_power_rated_max:
+ return xe_hwmon_power_rated_max_read(hwmon, val);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int
+xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
+{
+ switch (attr) {
+ case hwmon_power_max:
+ return xe_hwmon_power_max_write(hwmon, val);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static umode_t
+xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+ struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata;
+ int ret;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ switch (type) {
+ case hwmon_power:
+ ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return ret;
+}
+
+static int
+xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
+ int channel, long *val)
+{
+ struct xe_hwmon *hwmon = dev_get_drvdata(dev);
+ int ret;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ switch (type) {
+ case hwmon_power:
+ ret = xe_hwmon_power_read(hwmon, attr, channel, val);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return ret;
+}
+
+static int
+xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
+ int channel, long val)
+{
+ struct xe_hwmon *hwmon = dev_get_drvdata(dev);
+ int ret;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ switch (type) {
+ case hwmon_power:
+ ret = xe_hwmon_power_write(hwmon, attr, channel, val);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return ret;
+}
+
+static const struct hwmon_ops hwmon_ops = {
+ .is_visible = xe_hwmon_is_visible,
+ .read = xe_hwmon_read,
+ .write = xe_hwmon_write,
+};
+
+static const struct hwmon_chip_info hwmon_chip_info = {
+ .ops = &hwmon_ops,
+ .info = hwmon_info,
+};
+
+static void
+xe_hwmon_get_preregistration_info(struct xe_device *xe)
+{
+ struct xe_hwmon *hwmon = xe->hwmon;
+ u32 val_sku_unit = 0;
+ int ret;
+
+ ret = xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU_UNIT, REG_READ, &val_sku_unit, 0, 0);
+ /*
+ * The contents of register PKG_POWER_SKU_UNIT do not change,
+ * so read it once and store the shift values.
+ */
+ if (!ret)
+ hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
+}
+
+void xe_hwmon_register(struct xe_device *xe)
+{
+ struct device *dev = xe->drm.dev;
+ struct xe_hwmon *hwmon;
+
+ /* hwmon is available only for dGfx */
+ if (!IS_DGFX(xe))
+ return;
+
+ hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
+ if (!hwmon)
+ return;
+
+ xe->hwmon = hwmon;
+
+ drmm_mutex_init(&xe->drm, &hwmon->hwmon_lock);
+
+ /* primary GT to access device level properties */
+ hwmon->gt = xe->tiles[0].primary_gt;
+
+ xe_hwmon_get_preregistration_info(xe);
+
+ drm_dbg(&xe->drm, "Register xe hwmon interface\n");
+
+ /* hwmon_dev points to device hwmon<i> */
+ hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
+ "xe",
+ hwmon,
+ &hwmon_chip_info,
+ NULL);
+ if (IS_ERR(hwmon->hwmon_dev)) {
+ drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
+ xe->hwmon = NULL;
+ return;
+ }
+}
+
diff --git a/drivers/gpu/drm/xe/xe_hwmon.h b/drivers/gpu/drm/xe/xe_hwmon.h
new file mode 100644
index 000000000000..1ec45cf1d19b
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_hwmon.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: MIT */
+
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_HWMON_H_
+#define _XE_HWMON_H_
+
+#include <linux/types.h>
+
+struct xe_device;
+
+#if IS_REACHABLE(CONFIG_HWMON)
+void xe_hwmon_register(struct xe_device *xe);
+#else
+static inline void xe_hwmon_register(struct xe_device *xe) { };
+#endif
+
+#endif /* _XE_HWMON_H_ */
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
@ 2023-09-21 10:25 ` Badal Nilawar
0 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon
Cc: anshuman.gupta, ashutosh.dixit, linux, andi.shyti, riana.tauro,
matthew.brost, rodrigo.vivi
Expose Card reactive sustained (pl1) power limit as power_max and
card default power limit (tdp) as power_rated_max.
v2:
- Fix review comments (Riana)
v3:
- Use drmm_mutex_init (Matt Brost)
- Print error value (Matt Brost)
- Convert enums to uppercase (Matt Brost)
- Avoid extra reg read in hwmon_is_visible function (Riana)
- Use xe_device_assert_mem_access when applicable (Matt Brost)
- Add intel-xe@lists.freedesktop.org in Documentation (Matt Brost)
v4:
- Use prefix xe_hwmon prefix for all functions (Matt Brost/Andi)
- %s/hwmon_reg/xe_hwmon_reg (Andi)
- Fix review comments (Guenter/Andi)
v5:
- Fix review comments (Riana)
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 22 ++
drivers/gpu/drm/xe/Makefile | 3 +
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 33 ++
drivers/gpu/drm/xe/xe_device.c | 3 +
drivers/gpu/drm/xe/xe_device_types.h | 2 +
drivers/gpu/drm/xe/xe_hwmon.c | 358 ++++++++++++++++++
drivers/gpu/drm/xe/xe_hwmon.h | 20 +
8 files changed, 445 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
create mode 100644 drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
create mode 100644 drivers/gpu/drm/xe/xe_hwmon.c
create mode 100644 drivers/gpu/drm/xe/xe_hwmon.h
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
new file mode 100644
index 000000000000..da0197a29fe4
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -0,0 +1,22 @@
+What: /sys/devices/.../hwmon/hwmon<i>/power1_max
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RW. Card reactive sustained (PL1) power limit in microwatts.
+
+ The power controller will throttle the operating frequency
+ if the power averaged over a window (typically seconds)
+ exceeds this limit. A read value of 0 means that the PL1
+ power limit is disabled, writing 0 disables the
+ limit. Writing values > 0 and <= TDP will enable the power limit.
+
+ Only supported for particular Intel xe graphics platforms.
+
+What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RO. Card default power limit (default TDP setting).
+
+ Only supported for particular Intel xe graphics platforms.
+
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 86c8bd4c05a3..ca77aff60d48 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -117,6 +117,9 @@ xe-y += xe_bb.o \
xe_wa.o \
xe_wopcm.o
+# graphics hardware monitoring (HWMON) support
+xe-$(CONFIG_HWMON) += xe_hwmon.o
+
# i915 Display compat #defines and #includes
subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
-I$(srctree)/$(src)/display/ext \
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index e13fbbdf6929..679cdba9f383 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -410,4 +410,8 @@
#define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
#define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
+#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
+#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
+#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
+
#endif
diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
new file mode 100644
index 000000000000..27f1d42baf6d
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_MCHBAR_REGS_H_
+#define _XE_MCHBAR_REGS_H_
+
+#include "regs/xe_reg_defs.h"
+
+/*
+ * MCHBAR mirror.
+ *
+ * This mirrors the MCHBAR MMIO space whose location is determined by
+ * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
+ * every way.
+ */
+
+#define MCHBAR_MIRROR_BASE_SNB 0x140000
+
+#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
+#define PKG_TDP GENMASK_ULL(14, 0)
+#define PKG_MIN_PWR GENMASK_ULL(30, 16)
+#define PKG_MAX_PWR GENMASK_ULL(46, 32)
+
+#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
+#define PKG_PWR_UNIT REG_GENMASK(3, 0)
+
+#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
+#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
+#define PKG_PWR_LIM_1_EN REG_BIT(15)
+
+#endif /* _XE_MCHBAR_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index b6bcb6c3482e..2acdc22a6027 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -34,6 +34,7 @@
#include "xe_vm.h"
#include "xe_vm_madvise.h"
#include "xe_wait_user_fence.h"
+#include "xe_hwmon.h"
#ifdef CONFIG_LOCKDEP
struct lockdep_map xe_device_mem_access_lockdep_map = {
@@ -337,6 +338,8 @@ int xe_device_probe(struct xe_device *xe)
xe_pmu_register(&xe->pmu);
+ xe_hwmon_register(xe);
+
err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
if (err)
return err;
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index a82f28c6a3a0..d1e319f305ef 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -365,6 +365,8 @@ struct xe_device {
/** @pmu: performance monitoring unit */
struct xe_pmu pmu;
+ struct xe_hwmon *hwmon;
+
/* private: */
#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
new file mode 100644
index 000000000000..7f4599d98541
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -0,0 +1,358 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include <linux/hwmon.h>
+
+#include <drm/drm_managed.h>
+#include "regs/xe_gt_regs.h"
+#include "regs/xe_mchbar_regs.h"
+#include "xe_device.h"
+#include "xe_gt.h"
+#include "xe_hwmon.h"
+#include "xe_mmio.h"
+
+enum xe_hwmon_reg {
+ REG_PKG_RAPL_LIMIT,
+ REG_PKG_POWER_SKU,
+ REG_PKG_POWER_SKU_UNIT,
+};
+
+enum xe_hwmon_reg_operation {
+ REG_READ,
+ REG_WRITE,
+ REG_RMW,
+};
+
+/*
+ * SF_* - scale factors for particular quantities according to hwmon spec.
+ */
+#define SF_POWER 1000000 /* microwatts */
+
+struct xe_hwmon {
+ struct device *hwmon_dev;
+ struct xe_gt *gt;
+ struct mutex hwmon_lock; /* rmw operations*/
+ int scl_shift_power;
+};
+
+static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
+{
+ struct xe_device *xe = gt_to_xe(hwmon->gt);
+ struct xe_reg reg = XE_REG(0);
+
+ switch (hwmon_reg) {
+ case REG_PKG_RAPL_LIMIT:
+ if (xe->info.platform == XE_DG2)
+ reg = PCU_CR_PACKAGE_RAPL_LIMIT;
+ else if (xe->info.platform == XE_PVC)
+ reg = PVC_GT0_PACKAGE_RAPL_LIMIT;
+ break;
+ case REG_PKG_POWER_SKU:
+ if (xe->info.platform == XE_DG2)
+ reg = PCU_CR_PACKAGE_POWER_SKU;
+ else if (xe->info.platform == XE_PVC)
+ reg = PVC_GT0_PACKAGE_POWER_SKU;
+ break;
+ case REG_PKG_POWER_SKU_UNIT:
+ if (xe->info.platform == XE_DG2)
+ reg = PCU_CR_PACKAGE_POWER_SKU_UNIT;
+ else if (xe->info.platform == XE_PVC)
+ reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;
+ break;
+ default:
+ XE_MISSING_CASE(hwmon_reg);
+ break;
+ }
+
+ return reg.raw;
+}
+
+static int xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
+ enum xe_hwmon_reg_operation operation, u32 *value,
+ u32 clr, u32 set)
+{
+ struct xe_reg reg;
+
+ reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
+
+ if (!reg.raw)
+ return -EOPNOTSUPP;
+
+ switch (operation) {
+ case REG_READ:
+ *value = xe_mmio_read32(hwmon->gt, reg);
+ return 0;
+ case REG_WRITE:
+ xe_mmio_write32(hwmon->gt, reg, *value);
+ return 0;
+ case REG_RMW:
+ *value = xe_mmio_rmw32(hwmon->gt, reg, clr, set);
+ return 0;
+ default:
+ XE_MISSING_CASE(operation);
+ return -EOPNOTSUPP;
+ }
+}
+
+int xe_hwmon_process_reg_read64(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, u64 *value)
+{
+ struct xe_reg reg;
+
+ reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
+
+ if (!reg.raw)
+ return -EOPNOTSUPP;
+
+ *value = xe_mmio_read64_2x32(hwmon->gt, reg);
+
+ return 0;
+}
+
+#define PL1_DISABLE 0
+
+/*
+ * HW allows arbitrary PL1 limits to be set but silently clamps these values to
+ * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the
+ * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
+ * clamped values when read.
+ */
+static int xe_hwmon_power_max_read(struct xe_hwmon *hwmon, long *value)
+{
+ u32 reg_val;
+ u64 reg_val64, min, max;
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val, 0, 0);
+ /* Check if PL1 limit is disabled */
+ if (!(reg_val & PKG_PWR_LIM_1_EN)) {
+ *value = PL1_DISABLE;
+ return 0;
+ }
+
+ reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);
+ *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
+
+ xe_hwmon_process_reg_read64(hwmon, REG_PKG_POWER_SKU, ®_val64);
+ min = REG_FIELD_GET(PKG_MIN_PWR, reg_val64);
+ min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
+ max = REG_FIELD_GET(PKG_MAX_PWR, reg_val64);
+ max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
+
+ if (min && max)
+ *value = clamp_t(u64, *value, min, max);
+
+ return 0;
+}
+
+static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
+{
+ u32 reg_val;
+
+ /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
+ if (value == PL1_DISABLE) {
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
+ PKG_PWR_LIM_1_EN, 0);
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
+ PKG_PWR_LIM_1_EN, 0);
+
+ if (reg_val & PKG_PWR_LIM_1_EN)
+ return -ENODEV;
+ }
+
+ /* Computation in 64-bits to avoid overflow. Round to nearest. */
+ reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
+ reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
+ PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
+
+ return 0;
+}
+
+static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
+{
+ u32 reg_val;
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ, ®_val, 0, 0);
+ reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
+ *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
+
+ return 0;
+}
+
+static const struct hwmon_channel_info *hwmon_info[] = {
+ HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
+ NULL
+};
+
+static umode_t
+xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
+{
+ switch (attr) {
+ case hwmon_power_max:
+ return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
+ case hwmon_power_rated_max:
+ return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
+ default:
+ return 0;
+ }
+}
+
+static int
+xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
+{
+ switch (attr) {
+ case hwmon_power_max:
+ return xe_hwmon_power_max_read(hwmon, val);
+ case hwmon_power_rated_max:
+ return xe_hwmon_power_rated_max_read(hwmon, val);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int
+xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
+{
+ switch (attr) {
+ case hwmon_power_max:
+ return xe_hwmon_power_max_write(hwmon, val);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static umode_t
+xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+ struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata;
+ int ret;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ switch (type) {
+ case hwmon_power:
+ ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return ret;
+}
+
+static int
+xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
+ int channel, long *val)
+{
+ struct xe_hwmon *hwmon = dev_get_drvdata(dev);
+ int ret;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ switch (type) {
+ case hwmon_power:
+ ret = xe_hwmon_power_read(hwmon, attr, channel, val);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return ret;
+}
+
+static int
+xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
+ int channel, long val)
+{
+ struct xe_hwmon *hwmon = dev_get_drvdata(dev);
+ int ret;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ switch (type) {
+ case hwmon_power:
+ ret = xe_hwmon_power_write(hwmon, attr, channel, val);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return ret;
+}
+
+static const struct hwmon_ops hwmon_ops = {
+ .is_visible = xe_hwmon_is_visible,
+ .read = xe_hwmon_read,
+ .write = xe_hwmon_write,
+};
+
+static const struct hwmon_chip_info hwmon_chip_info = {
+ .ops = &hwmon_ops,
+ .info = hwmon_info,
+};
+
+static void
+xe_hwmon_get_preregistration_info(struct xe_device *xe)
+{
+ struct xe_hwmon *hwmon = xe->hwmon;
+ u32 val_sku_unit = 0;
+ int ret;
+
+ ret = xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU_UNIT, REG_READ, &val_sku_unit, 0, 0);
+ /*
+ * The contents of register PKG_POWER_SKU_UNIT do not change,
+ * so read it once and store the shift values.
+ */
+ if (!ret)
+ hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
+}
+
+void xe_hwmon_register(struct xe_device *xe)
+{
+ struct device *dev = xe->drm.dev;
+ struct xe_hwmon *hwmon;
+
+ /* hwmon is available only for dGfx */
+ if (!IS_DGFX(xe))
+ return;
+
+ hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
+ if (!hwmon)
+ return;
+
+ xe->hwmon = hwmon;
+
+ drmm_mutex_init(&xe->drm, &hwmon->hwmon_lock);
+
+ /* primary GT to access device level properties */
+ hwmon->gt = xe->tiles[0].primary_gt;
+
+ xe_hwmon_get_preregistration_info(xe);
+
+ drm_dbg(&xe->drm, "Register xe hwmon interface\n");
+
+ /* hwmon_dev points to device hwmon<i> */
+ hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
+ "xe",
+ hwmon,
+ &hwmon_chip_info,
+ NULL);
+ if (IS_ERR(hwmon->hwmon_dev)) {
+ drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
+ xe->hwmon = NULL;
+ return;
+ }
+}
+
diff --git a/drivers/gpu/drm/xe/xe_hwmon.h b/drivers/gpu/drm/xe/xe_hwmon.h
new file mode 100644
index 000000000000..1ec45cf1d19b
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_hwmon.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: MIT */
+
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_HWMON_H_
+#define _XE_HWMON_H_
+
+#include <linux/types.h>
+
+struct xe_device;
+
+#if IS_REACHABLE(CONFIG_HWMON)
+void xe_hwmon_register(struct xe_device *xe);
+#else
+static inline void xe_hwmon_register(struct xe_device *xe) { };
+#endif
+
+#endif /* _XE_HWMON_H_ */
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-xe] [PATCH v5 3/6] drm/xe/hwmon: Expose card reactive critical power
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-21 10:25 ` Badal Nilawar
-1 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon; +Cc: linux, rodrigo.vivi
Expose the card reactive critical (I1) power. I1 is exposed as
power1_crit in microwatts (typically for client products) or as
curr1_crit in milliamperes (typically for server).
v2: Move PCODE_MBOX macro to pcode file (Riana)
v3: s/IS_DG2/(gt_to_xe(gt)->info.platform == XE_DG2)
v4: Fix review comments (Andi)
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
---
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 26 +++++
drivers/gpu/drm/xe/xe_hwmon.c | 105 +++++++++++++++++-
drivers/gpu/drm/xe/xe_pcode.h | 5 +
drivers/gpu/drm/xe/xe_pcode_api.h | 7 ++
4 files changed, 142 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index da0197a29fe4..37263b09b6e4 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -20,3 +20,29 @@ Description: RO. Card default power limit (default TDP setting).
Only supported for particular Intel xe graphics platforms.
+What: /sys/devices/.../hwmon/hwmon<i>/power1_crit
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RW. Card reactive critical (I1) power limit in microwatts.
+
+ Card reactive critical (I1) power limit in microwatts is exposed
+ for client products. The power controller will throttle the
+ operating frequency if the power averaged over a window exceeds
+ this limit.
+
+ Only supported for particular Intel xe graphics platforms.
+
+What: /sys/devices/.../hwmon/hwmon<i>/curr1_crit
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RW. Card reactive critical (I1) power limit in milliamperes.
+
+ Card reactive critical (I1) power limit in milliamperes is
+ exposed for server products. The power controller will throttle
+ the operating frequency if the power averaged over a window
+ exceeds this limit.
+
+ Only supported for particular Intel xe graphics platforms.
+
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 7f4599d98541..ef0893bf1268 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -12,6 +12,8 @@
#include "xe_gt.h"
#include "xe_hwmon.h"
#include "xe_mmio.h"
+#include "xe_pcode.h"
+#include "xe_pcode_api.h"
enum xe_hwmon_reg {
REG_PKG_RAPL_LIMIT,
@@ -29,6 +31,7 @@ enum xe_hwmon_reg_operation {
* SF_* - scale factors for particular quantities according to hwmon spec.
*/
#define SF_POWER 1000000 /* microwatts */
+#define SF_CURR 1000 /* milliamperes */
struct xe_hwmon {
struct device *hwmon_dev;
@@ -182,18 +185,43 @@ static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
}
static const struct hwmon_channel_info *hwmon_info[] = {
- HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
+ HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
+ HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
NULL
};
+/* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
+static int xe_hwmon_pcode_read_i1(struct xe_gt *gt, u32 *uval)
+{
+ /* Avoid Illegal Subcommand error */
+ if (gt_to_xe(gt)->info.platform == XE_DG2)
+ return -ENXIO;
+
+ return xe_pcode_read(gt, PCODE_MBOX(PCODE_POWER_SETUP,
+ POWER_SETUP_SUBCOMMAND_READ_I1, 0),
+ uval, 0);
+}
+
+static int xe_hwmon_pcode_write_i1(struct xe_gt *gt, u32 uval)
+{
+ return xe_pcode_write(gt, PCODE_MBOX(PCODE_POWER_SETUP,
+ POWER_SETUP_SUBCOMMAND_WRITE_I1, 0),
+ uval);
+}
+
static umode_t
xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
{
+ u32 uval;
+
switch (attr) {
case hwmon_power_max:
return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
case hwmon_power_rated_max:
return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
+ case hwmon_power_crit:
+ return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) ||
+ !(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
default:
return 0;
}
@@ -202,11 +230,23 @@ xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
static int
xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
{
+ int ret;
+ u32 uval;
+
switch (attr) {
case hwmon_power_max:
return xe_hwmon_power_max_read(hwmon, val);
case hwmon_power_rated_max:
return xe_hwmon_power_rated_max_read(hwmon, val);
+ case hwmon_power_crit:
+ ret = xe_hwmon_pcode_read_i1(hwmon->gt, &uval);
+ if (ret)
+ return ret;
+ if (!(uval & POWER_SETUP_I1_WATTS))
+ return -ENODEV;
+ *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
+ SF_POWER, POWER_SETUP_I1_SHIFT);
+ return 0;
default:
return -EOPNOTSUPP;
}
@@ -215,9 +255,63 @@ xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
static int
xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
{
+ u32 uval;
+
switch (attr) {
case hwmon_power_max:
return xe_hwmon_power_max_write(hwmon, val);
+ case hwmon_power_crit:
+ uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_POWER);
+ return xe_hwmon_pcode_write_i1(hwmon->gt, uval);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static umode_t
+xe_hwmon_curr_is_visible(const struct xe_hwmon *hwmon, u32 attr)
+{
+ u32 uval;
+
+ switch (attr) {
+ case hwmon_curr_crit:
+ return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) ||
+ (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
+ default:
+ return 0;
+ }
+}
+
+static int
+xe_hwmon_curr_read(struct xe_hwmon *hwmon, u32 attr, long *val)
+{
+ int ret;
+ u32 uval;
+
+ switch (attr) {
+ case hwmon_curr_crit:
+ ret = xe_hwmon_pcode_read_i1(hwmon->gt, &uval);
+ if (ret)
+ return ret;
+ if (uval & POWER_SETUP_I1_WATTS)
+ return -ENODEV;
+ *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
+ SF_CURR, POWER_SETUP_I1_SHIFT);
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int
+xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, long val)
+{
+ u32 uval;
+
+ switch (attr) {
+ case hwmon_curr_crit:
+ uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_CURR);
+ return xe_hwmon_pcode_write_i1(hwmon->gt, uval);
default:
return -EOPNOTSUPP;
}
@@ -236,6 +330,9 @@ xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
case hwmon_power:
ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
break;
+ case hwmon_curr:
+ ret = xe_hwmon_curr_is_visible(hwmon, attr);
+ break;
default:
ret = 0;
break;
@@ -259,6 +356,9 @@ xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
case hwmon_power:
ret = xe_hwmon_power_read(hwmon, attr, channel, val);
break;
+ case hwmon_curr:
+ ret = xe_hwmon_curr_read(hwmon, attr, val);
+ break;
default:
ret = -EOPNOTSUPP;
break;
@@ -282,6 +382,9 @@ xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
case hwmon_power:
ret = xe_hwmon_power_write(hwmon, attr, channel, val);
break;
+ case hwmon_curr:
+ ret = xe_hwmon_curr_write(hwmon, attr, val);
+ break;
default:
ret = -EOPNOTSUPP;
break;
diff --git a/drivers/gpu/drm/xe/xe_pcode.h b/drivers/gpu/drm/xe/xe_pcode.h
index 3b4aa8c1a3ba..08cb1d047cba 100644
--- a/drivers/gpu/drm/xe/xe_pcode.h
+++ b/drivers/gpu/drm/xe/xe_pcode.h
@@ -22,4 +22,9 @@ int xe_pcode_write_timeout(struct xe_gt *gt, u32 mbox, u32 val,
int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_ms);
+#define PCODE_MBOX(mbcmd, param1, param2)\
+ (FIELD_PREP(PCODE_MB_COMMAND, mbcmd)\
+ | FIELD_PREP(PCODE_MB_PARAM1, param1)\
+ | FIELD_PREP(PCODE_MB_PARAM2, param2))
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 837ff7c71280..5935cfe30204 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -35,6 +35,13 @@
#define DGFX_GET_INIT_STATUS 0x0
#define DGFX_INIT_STATUS_COMPLETE 0x1
+#define PCODE_POWER_SETUP 0x7C
+#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
+#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
+#define POWER_SETUP_I1_WATTS REG_BIT(31)
+#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
+#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
+
struct pcode_err_decode {
int errno;
const char *str;
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v5 3/6] drm/xe/hwmon: Expose card reactive critical power
@ 2023-09-21 10:25 ` Badal Nilawar
0 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon
Cc: anshuman.gupta, ashutosh.dixit, linux, andi.shyti, riana.tauro,
matthew.brost, rodrigo.vivi
Expose the card reactive critical (I1) power. I1 is exposed as
power1_crit in microwatts (typically for client products) or as
curr1_crit in milliamperes (typically for server).
v2: Move PCODE_MBOX macro to pcode file (Riana)
v3: s/IS_DG2/(gt_to_xe(gt)->info.platform == XE_DG2)
v4: Fix review comments (Andi)
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
---
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 26 +++++
drivers/gpu/drm/xe/xe_hwmon.c | 105 +++++++++++++++++-
drivers/gpu/drm/xe/xe_pcode.h | 5 +
drivers/gpu/drm/xe/xe_pcode_api.h | 7 ++
4 files changed, 142 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index da0197a29fe4..37263b09b6e4 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -20,3 +20,29 @@ Description: RO. Card default power limit (default TDP setting).
Only supported for particular Intel xe graphics platforms.
+What: /sys/devices/.../hwmon/hwmon<i>/power1_crit
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RW. Card reactive critical (I1) power limit in microwatts.
+
+ Card reactive critical (I1) power limit in microwatts is exposed
+ for client products. The power controller will throttle the
+ operating frequency if the power averaged over a window exceeds
+ this limit.
+
+ Only supported for particular Intel xe graphics platforms.
+
+What: /sys/devices/.../hwmon/hwmon<i>/curr1_crit
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RW. Card reactive critical (I1) power limit in milliamperes.
+
+ Card reactive critical (I1) power limit in milliamperes is
+ exposed for server products. The power controller will throttle
+ the operating frequency if the power averaged over a window
+ exceeds this limit.
+
+ Only supported for particular Intel xe graphics platforms.
+
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 7f4599d98541..ef0893bf1268 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -12,6 +12,8 @@
#include "xe_gt.h"
#include "xe_hwmon.h"
#include "xe_mmio.h"
+#include "xe_pcode.h"
+#include "xe_pcode_api.h"
enum xe_hwmon_reg {
REG_PKG_RAPL_LIMIT,
@@ -29,6 +31,7 @@ enum xe_hwmon_reg_operation {
* SF_* - scale factors for particular quantities according to hwmon spec.
*/
#define SF_POWER 1000000 /* microwatts */
+#define SF_CURR 1000 /* milliamperes */
struct xe_hwmon {
struct device *hwmon_dev;
@@ -182,18 +185,43 @@ static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
}
static const struct hwmon_channel_info *hwmon_info[] = {
- HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
+ HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
+ HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
NULL
};
+/* I1 is exposed as power_crit or as curr_crit depending on bit 31 */
+static int xe_hwmon_pcode_read_i1(struct xe_gt *gt, u32 *uval)
+{
+ /* Avoid Illegal Subcommand error */
+ if (gt_to_xe(gt)->info.platform == XE_DG2)
+ return -ENXIO;
+
+ return xe_pcode_read(gt, PCODE_MBOX(PCODE_POWER_SETUP,
+ POWER_SETUP_SUBCOMMAND_READ_I1, 0),
+ uval, 0);
+}
+
+static int xe_hwmon_pcode_write_i1(struct xe_gt *gt, u32 uval)
+{
+ return xe_pcode_write(gt, PCODE_MBOX(PCODE_POWER_SETUP,
+ POWER_SETUP_SUBCOMMAND_WRITE_I1, 0),
+ uval);
+}
+
static umode_t
xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
{
+ u32 uval;
+
switch (attr) {
case hwmon_power_max:
return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
case hwmon_power_rated_max:
return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
+ case hwmon_power_crit:
+ return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) ||
+ !(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
default:
return 0;
}
@@ -202,11 +230,23 @@ xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
static int
xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
{
+ int ret;
+ u32 uval;
+
switch (attr) {
case hwmon_power_max:
return xe_hwmon_power_max_read(hwmon, val);
case hwmon_power_rated_max:
return xe_hwmon_power_rated_max_read(hwmon, val);
+ case hwmon_power_crit:
+ ret = xe_hwmon_pcode_read_i1(hwmon->gt, &uval);
+ if (ret)
+ return ret;
+ if (!(uval & POWER_SETUP_I1_WATTS))
+ return -ENODEV;
+ *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
+ SF_POWER, POWER_SETUP_I1_SHIFT);
+ return 0;
default:
return -EOPNOTSUPP;
}
@@ -215,9 +255,63 @@ xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
static int
xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
{
+ u32 uval;
+
switch (attr) {
case hwmon_power_max:
return xe_hwmon_power_max_write(hwmon, val);
+ case hwmon_power_crit:
+ uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_POWER);
+ return xe_hwmon_pcode_write_i1(hwmon->gt, uval);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static umode_t
+xe_hwmon_curr_is_visible(const struct xe_hwmon *hwmon, u32 attr)
+{
+ u32 uval;
+
+ switch (attr) {
+ case hwmon_curr_crit:
+ return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) ||
+ (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644;
+ default:
+ return 0;
+ }
+}
+
+static int
+xe_hwmon_curr_read(struct xe_hwmon *hwmon, u32 attr, long *val)
+{
+ int ret;
+ u32 uval;
+
+ switch (attr) {
+ case hwmon_curr_crit:
+ ret = xe_hwmon_pcode_read_i1(hwmon->gt, &uval);
+ if (ret)
+ return ret;
+ if (uval & POWER_SETUP_I1_WATTS)
+ return -ENODEV;
+ *val = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval),
+ SF_CURR, POWER_SETUP_I1_SHIFT);
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int
+xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, long val)
+{
+ u32 uval;
+
+ switch (attr) {
+ case hwmon_curr_crit:
+ uval = DIV_ROUND_CLOSEST_ULL(val << POWER_SETUP_I1_SHIFT, SF_CURR);
+ return xe_hwmon_pcode_write_i1(hwmon->gt, uval);
default:
return -EOPNOTSUPP;
}
@@ -236,6 +330,9 @@ xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
case hwmon_power:
ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
break;
+ case hwmon_curr:
+ ret = xe_hwmon_curr_is_visible(hwmon, attr);
+ break;
default:
ret = 0;
break;
@@ -259,6 +356,9 @@ xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
case hwmon_power:
ret = xe_hwmon_power_read(hwmon, attr, channel, val);
break;
+ case hwmon_curr:
+ ret = xe_hwmon_curr_read(hwmon, attr, val);
+ break;
default:
ret = -EOPNOTSUPP;
break;
@@ -282,6 +382,9 @@ xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
case hwmon_power:
ret = xe_hwmon_power_write(hwmon, attr, channel, val);
break;
+ case hwmon_curr:
+ ret = xe_hwmon_curr_write(hwmon, attr, val);
+ break;
default:
ret = -EOPNOTSUPP;
break;
diff --git a/drivers/gpu/drm/xe/xe_pcode.h b/drivers/gpu/drm/xe/xe_pcode.h
index 3b4aa8c1a3ba..08cb1d047cba 100644
--- a/drivers/gpu/drm/xe/xe_pcode.h
+++ b/drivers/gpu/drm/xe/xe_pcode.h
@@ -22,4 +22,9 @@ int xe_pcode_write_timeout(struct xe_gt *gt, u32 mbox, u32 val,
int xe_pcode_request(struct xe_gt *gt, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_ms);
+#define PCODE_MBOX(mbcmd, param1, param2)\
+ (FIELD_PREP(PCODE_MB_COMMAND, mbcmd)\
+ | FIELD_PREP(PCODE_MB_PARAM1, param1)\
+ | FIELD_PREP(PCODE_MB_PARAM2, param2))
+
#endif
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 837ff7c71280..5935cfe30204 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -35,6 +35,13 @@
#define DGFX_GET_INIT_STATUS 0x0
#define DGFX_INIT_STATUS_COMPLETE 0x1
+#define PCODE_POWER_SETUP 0x7C
+#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
+#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
+#define POWER_SETUP_I1_WATTS REG_BIT(31)
+#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
+#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
+
struct pcode_err_decode {
int errno;
const char *str;
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-xe] [PATCH v5 4/6] drm/xe/hwmon: Expose input voltage attribute
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-21 10:25 ` Badal Nilawar
-1 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon; +Cc: linux, rodrigo.vivi
Use Xe HWMON subsystem to display the input voltage.
v2:
- Rename hwm_get_vltg to hwm_get_voltage (Riana)
- Use scale factor SF_VOLTAGE (Riana)
v3:
- %s/gt_perf_status/REG_GT_PERF_STATUS/
- Remove platform check from hwmon_get_voltage()
v4:
- Fix review comments (Andi)
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
---
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 6 ++
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +
drivers/gpu/drm/xe/xe_hwmon.c | 58 +++++++++++++++++++
3 files changed, 67 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index 37263b09b6e4..7f9407c20864 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -44,5 +44,11 @@ Description: RW. Card reactive critical (I1) power limit in milliamperes.
the operating frequency if the power averaged over a window
exceeds this limit.
+What: /sys/devices/.../hwmon/hwmon<i>/in0_input
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RO. Current Voltage in millivolt.
+
Only supported for particular Intel xe graphics platforms.
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 679cdba9f383..102663cbc320 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -374,6 +374,9 @@
#define GT_GFX_RC6_LOCKED XE_REG(0x138104)
#define GT_GFX_RC6 XE_REG(0x138108)
+#define GT_PERF_STATUS XE_REG(0x1381b4)
+#define VOLTAGE_MASK REG_GENMASK(10, 0)
+
#define GT_INTR_DW(x) XE_REG(0x190018 + ((x) * 4))
#define GUC_SG_INTR_ENABLE XE_REG(0x190038)
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index ef0893bf1268..431995045faa 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -3,7 +3,9 @@
* Copyright © 2023 Intel Corporation
*/
+#include <linux/hwmon-sysfs.h>
#include <linux/hwmon.h>
+#include <linux/types.h>
#include <drm/drm_managed.h>
#include "regs/xe_gt_regs.h"
@@ -19,6 +21,7 @@ enum xe_hwmon_reg {
REG_PKG_RAPL_LIMIT,
REG_PKG_POWER_SKU,
REG_PKG_POWER_SKU_UNIT,
+ REG_GT_PERF_STATUS,
};
enum xe_hwmon_reg_operation {
@@ -32,6 +35,7 @@ enum xe_hwmon_reg_operation {
*/
#define SF_POWER 1000000 /* microwatts */
#define SF_CURR 1000 /* milliamperes */
+#define SF_VOLTAGE 1000 /* millivolts */
struct xe_hwmon {
struct device *hwmon_dev;
@@ -64,6 +68,10 @@ static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
else if (xe->info.platform == XE_PVC)
reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;
break;
+ case REG_GT_PERF_STATUS:
+ if (xe->info.platform == XE_DG2)
+ reg = GT_PERF_STATUS;
+ break;
default:
XE_MISSING_CASE(hwmon_reg);
break;
@@ -187,6 +195,7 @@ static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
static const struct hwmon_channel_info *hwmon_info[] = {
HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
+ HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
NULL
};
@@ -209,6 +218,18 @@ static int xe_hwmon_pcode_write_i1(struct xe_gt *gt, u32 uval)
uval);
}
+static int xe_hwmon_get_voltage(struct xe_hwmon *hwmon, long *value)
+{
+ u32 reg_val;
+
+ xe_hwmon_process_reg(hwmon, REG_GT_PERF_STATUS,
+ REG_READ, ®_val, 0, 0);
+ /* HW register value in units of 2.5 millivolt */
+ *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
+
+ return 0;
+}
+
static umode_t
xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
{
@@ -317,6 +338,37 @@ xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, long val)
}
}
+static umode_t
+xe_hwmon_in_is_visible(struct xe_hwmon *hwmon, u32 attr)
+{
+ switch (attr) {
+ case hwmon_in_input:
+ return xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS) ? 0444 : 0;
+ default:
+ return 0;
+ }
+}
+
+static int
+xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, long *val)
+{
+ int ret;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ switch (attr) {
+ case hwmon_in_input:
+ ret = xe_hwmon_get_voltage(hwmon, val);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ }
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return ret;
+}
+
static umode_t
xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
u32 attr, int channel)
@@ -333,6 +385,9 @@ xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
case hwmon_curr:
ret = xe_hwmon_curr_is_visible(hwmon, attr);
break;
+ case hwmon_in:
+ ret = xe_hwmon_in_is_visible(hwmon, attr);
+ break;
default:
ret = 0;
break;
@@ -359,6 +414,9 @@ xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
case hwmon_curr:
ret = xe_hwmon_curr_read(hwmon, attr, val);
break;
+ case hwmon_in:
+ ret = xe_hwmon_in_read(hwmon, attr, val);
+ break;
default:
ret = -EOPNOTSUPP;
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v5 4/6] drm/xe/hwmon: Expose input voltage attribute
@ 2023-09-21 10:25 ` Badal Nilawar
0 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon
Cc: anshuman.gupta, ashutosh.dixit, linux, andi.shyti, riana.tauro,
matthew.brost, rodrigo.vivi
Use Xe HWMON subsystem to display the input voltage.
v2:
- Rename hwm_get_vltg to hwm_get_voltage (Riana)
- Use scale factor SF_VOLTAGE (Riana)
v3:
- %s/gt_perf_status/REG_GT_PERF_STATUS/
- Remove platform check from hwmon_get_voltage()
v4:
- Fix review comments (Andi)
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
---
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 6 ++
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +
drivers/gpu/drm/xe/xe_hwmon.c | 58 +++++++++++++++++++
3 files changed, 67 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index 37263b09b6e4..7f9407c20864 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -44,5 +44,11 @@ Description: RW. Card reactive critical (I1) power limit in milliamperes.
the operating frequency if the power averaged over a window
exceeds this limit.
+What: /sys/devices/.../hwmon/hwmon<i>/in0_input
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RO. Current Voltage in millivolt.
+
Only supported for particular Intel xe graphics platforms.
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 679cdba9f383..102663cbc320 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -374,6 +374,9 @@
#define GT_GFX_RC6_LOCKED XE_REG(0x138104)
#define GT_GFX_RC6 XE_REG(0x138108)
+#define GT_PERF_STATUS XE_REG(0x1381b4)
+#define VOLTAGE_MASK REG_GENMASK(10, 0)
+
#define GT_INTR_DW(x) XE_REG(0x190018 + ((x) * 4))
#define GUC_SG_INTR_ENABLE XE_REG(0x190038)
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index ef0893bf1268..431995045faa 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -3,7 +3,9 @@
* Copyright © 2023 Intel Corporation
*/
+#include <linux/hwmon-sysfs.h>
#include <linux/hwmon.h>
+#include <linux/types.h>
#include <drm/drm_managed.h>
#include "regs/xe_gt_regs.h"
@@ -19,6 +21,7 @@ enum xe_hwmon_reg {
REG_PKG_RAPL_LIMIT,
REG_PKG_POWER_SKU,
REG_PKG_POWER_SKU_UNIT,
+ REG_GT_PERF_STATUS,
};
enum xe_hwmon_reg_operation {
@@ -32,6 +35,7 @@ enum xe_hwmon_reg_operation {
*/
#define SF_POWER 1000000 /* microwatts */
#define SF_CURR 1000 /* milliamperes */
+#define SF_VOLTAGE 1000 /* millivolts */
struct xe_hwmon {
struct device *hwmon_dev;
@@ -64,6 +68,10 @@ static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
else if (xe->info.platform == XE_PVC)
reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;
break;
+ case REG_GT_PERF_STATUS:
+ if (xe->info.platform == XE_DG2)
+ reg = GT_PERF_STATUS;
+ break;
default:
XE_MISSING_CASE(hwmon_reg);
break;
@@ -187,6 +195,7 @@ static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
static const struct hwmon_channel_info *hwmon_info[] = {
HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
+ HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
NULL
};
@@ -209,6 +218,18 @@ static int xe_hwmon_pcode_write_i1(struct xe_gt *gt, u32 uval)
uval);
}
+static int xe_hwmon_get_voltage(struct xe_hwmon *hwmon, long *value)
+{
+ u32 reg_val;
+
+ xe_hwmon_process_reg(hwmon, REG_GT_PERF_STATUS,
+ REG_READ, ®_val, 0, 0);
+ /* HW register value in units of 2.5 millivolt */
+ *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE);
+
+ return 0;
+}
+
static umode_t
xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
{
@@ -317,6 +338,37 @@ xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, long val)
}
}
+static umode_t
+xe_hwmon_in_is_visible(struct xe_hwmon *hwmon, u32 attr)
+{
+ switch (attr) {
+ case hwmon_in_input:
+ return xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS) ? 0444 : 0;
+ default:
+ return 0;
+ }
+}
+
+static int
+xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, long *val)
+{
+ int ret;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ switch (attr) {
+ case hwmon_in_input:
+ ret = xe_hwmon_get_voltage(hwmon, val);
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ }
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return ret;
+}
+
static umode_t
xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
u32 attr, int channel)
@@ -333,6 +385,9 @@ xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
case hwmon_curr:
ret = xe_hwmon_curr_is_visible(hwmon, attr);
break;
+ case hwmon_in:
+ ret = xe_hwmon_in_is_visible(hwmon, attr);
+ break;
default:
ret = 0;
break;
@@ -359,6 +414,9 @@ xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
case hwmon_curr:
ret = xe_hwmon_curr_read(hwmon, attr, val);
break;
+ case hwmon_in:
+ ret = xe_hwmon_in_read(hwmon, attr, val);
+ break;
default:
ret = -EOPNOTSUPP;
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-xe] [PATCH v5 5/6] drm/xe/hwmon: Expose hwmon energy attribute
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-21 10:25 ` Badal Nilawar
-1 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon; +Cc: linux, rodrigo.vivi
Expose hwmon energy attribute to show device level energy usage
v2:
- %s/hwm_/hwmon_/
- Convert enums to upper case
v3:
- %s/hwmon_/xe_hwmon
- Remove gt specific hwmon attributes
v4:
- %s/REG_PKG_ENERGY_STATUS/REG_ENERGY_STATUS_ALL (Riana)
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 7 ++
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 3 +
drivers/gpu/drm/xe/xe_hwmon.c | 105 +++++++++++++++++-
4 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index 7f9407c20864..1a7a6c23e141 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -52,3 +52,10 @@ Description: RO. Current Voltage in millivolt.
Only supported for particular Intel xe graphics platforms.
+What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RO. Energy input of device in microjoules.
+
+ Only supported for particular Intel xe graphics platforms.
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 102663cbc320..9e6ce74fdd68 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -413,8 +413,10 @@
#define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
#define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
+#define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004)
#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
+#define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
#endif
diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
index 27f1d42baf6d..d8ecbe1858d1 100644
--- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
@@ -25,6 +25,9 @@
#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
#define PKG_PWR_UNIT REG_GENMASK(3, 0)
+#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
+
+#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 431995045faa..cb75b9a386c0 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -22,6 +22,7 @@ enum xe_hwmon_reg {
REG_PKG_POWER_SKU,
REG_PKG_POWER_SKU_UNIT,
REG_GT_PERF_STATUS,
+ REG_PKG_ENERGY_STATUS,
};
enum xe_hwmon_reg_operation {
@@ -36,12 +37,20 @@ enum xe_hwmon_reg_operation {
#define SF_POWER 1000000 /* microwatts */
#define SF_CURR 1000 /* milliamperes */
#define SF_VOLTAGE 1000 /* millivolts */
+#define SF_ENERGY 1000000 /* microjoules */
+
+struct hwmon_energy_info {
+ u32 reg_val_prev;
+ long accum_energy; /* Accumulated energy for energy1_input */
+};
struct xe_hwmon {
struct device *hwmon_dev;
struct xe_gt *gt;
struct mutex hwmon_lock; /* rmw operations*/
int scl_shift_power;
+ int scl_shift_energy;
+ struct hwmon_energy_info ei; /* Energy info for energy1_input */
};
static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
@@ -72,6 +81,12 @@ static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
if (xe->info.platform == XE_DG2)
reg = GT_PERF_STATUS;
break;
+ case REG_PKG_ENERGY_STATUS:
+ if (xe->info.platform == XE_DG2)
+ reg = PCU_CR_PACKAGE_ENERGY_STATUS;
+ else if (xe->info.platform == XE_PVC)
+ reg = PVC_GT0_PLATFORM_ENERGY_STATUS;
+ break;
default:
XE_MISSING_CASE(hwmon_reg);
break;
@@ -192,10 +207,59 @@ static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
return 0;
}
+/*
+ * xe_hwmon_energy_get - Obtain energy value
+ *
+ * The underlying energy hardware register is 32-bits and is subject to
+ * overflow. How long before overflow? For example, with an example
+ * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and
+ * a power draw of 1000 watts, the 32-bit counter will overflow in
+ * approximately 4.36 minutes.
+ *
+ * Examples:
+ * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days
+ * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes
+ *
+ * The function significantly increases overflow duration (from 4.36
+ * minutes) by accumulating the energy register into a 'long' as allowed by
+ * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()),
+ * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and
+ * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
+ * energy1_input overflows. This at 1000 W is an overflow duration of 278 years.
+ */
+static void
+xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)
+{
+ struct hwmon_energy_info *ei = &hwmon->ei;
+ u32 reg_val;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ mutex_lock(&hwmon->hwmon_lock);
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_ENERGY_STATUS, REG_READ,
+ ®_val, 0, 0);
+
+ if (reg_val >= ei->reg_val_prev)
+ ei->accum_energy += reg_val - ei->reg_val_prev;
+ else
+ ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val;
+
+ ei->reg_val_prev = reg_val;
+
+ *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,
+ hwmon->scl_shift_energy);
+
+ mutex_unlock(&hwmon->hwmon_lock);
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+}
+
static const struct hwmon_channel_info *hwmon_info[] = {
HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
+ HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
NULL
};
@@ -369,6 +433,29 @@ xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, long *val)
return ret;
}
+static umode_t
+xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr)
+{
+ switch (attr) {
+ case hwmon_energy_input:
+ return xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS) ? 0444 : 0;
+ default:
+ return 0;
+ }
+}
+
+static int
+xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, long *val)
+{
+ switch (attr) {
+ case hwmon_energy_input:
+ xe_hwmon_energy_get(hwmon, val);
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static umode_t
xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
u32 attr, int channel)
@@ -388,6 +475,9 @@ xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
case hwmon_in:
ret = xe_hwmon_in_is_visible(hwmon, attr);
break;
+ case hwmon_energy:
+ ret = xe_hwmon_energy_is_visible(hwmon, attr);
+ break;
default:
ret = 0;
break;
@@ -417,6 +507,9 @@ xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
case hwmon_in:
ret = xe_hwmon_in_read(hwmon, attr, val);
break;
+ case hwmon_energy:
+ ret = xe_hwmon_energy_read(hwmon, attr, val);
+ break;
default:
ret = -EOPNOTSUPP;
break;
@@ -468,6 +561,7 @@ static void
xe_hwmon_get_preregistration_info(struct xe_device *xe)
{
struct xe_hwmon *hwmon = xe->hwmon;
+ long energy;
u32 val_sku_unit = 0;
int ret;
@@ -476,8 +570,17 @@ xe_hwmon_get_preregistration_info(struct xe_device *xe)
* The contents of register PKG_POWER_SKU_UNIT do not change,
* so read it once and store the shift values.
*/
- if (!ret)
+ if (!ret) {
hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
+ hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
+ }
+
+ /*
+ * Initialize 'struct hwmon_energy_info', i.e. set fields to the
+ * first value of the energy register read
+ */
+ if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, 0))
+ xe_hwmon_energy_get(hwmon, &energy);
}
void xe_hwmon_register(struct xe_device *xe)
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v5 5/6] drm/xe/hwmon: Expose hwmon energy attribute
@ 2023-09-21 10:25 ` Badal Nilawar
0 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon
Cc: anshuman.gupta, ashutosh.dixit, linux, andi.shyti, riana.tauro,
matthew.brost, rodrigo.vivi
Expose hwmon energy attribute to show device level energy usage
v2:
- %s/hwm_/hwmon_/
- Convert enums to upper case
v3:
- %s/hwmon_/xe_hwmon
- Remove gt specific hwmon attributes
v4:
- %s/REG_PKG_ENERGY_STATUS/REG_ENERGY_STATUS_ALL (Riana)
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 7 ++
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 3 +
drivers/gpu/drm/xe/xe_hwmon.c | 105 +++++++++++++++++-
4 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index 7f9407c20864..1a7a6c23e141 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -52,3 +52,10 @@ Description: RO. Current Voltage in millivolt.
Only supported for particular Intel xe graphics platforms.
+What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RO. Energy input of device in microjoules.
+
+ Only supported for particular Intel xe graphics platforms.
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 102663cbc320..9e6ce74fdd68 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -413,8 +413,10 @@
#define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
#define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
+#define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004)
#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
+#define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
#endif
diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
index 27f1d42baf6d..d8ecbe1858d1 100644
--- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
@@ -25,6 +25,9 @@
#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
#define PKG_PWR_UNIT REG_GENMASK(3, 0)
+#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
+
+#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 431995045faa..cb75b9a386c0 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -22,6 +22,7 @@ enum xe_hwmon_reg {
REG_PKG_POWER_SKU,
REG_PKG_POWER_SKU_UNIT,
REG_GT_PERF_STATUS,
+ REG_PKG_ENERGY_STATUS,
};
enum xe_hwmon_reg_operation {
@@ -36,12 +37,20 @@ enum xe_hwmon_reg_operation {
#define SF_POWER 1000000 /* microwatts */
#define SF_CURR 1000 /* milliamperes */
#define SF_VOLTAGE 1000 /* millivolts */
+#define SF_ENERGY 1000000 /* microjoules */
+
+struct hwmon_energy_info {
+ u32 reg_val_prev;
+ long accum_energy; /* Accumulated energy for energy1_input */
+};
struct xe_hwmon {
struct device *hwmon_dev;
struct xe_gt *gt;
struct mutex hwmon_lock; /* rmw operations*/
int scl_shift_power;
+ int scl_shift_energy;
+ struct hwmon_energy_info ei; /* Energy info for energy1_input */
};
static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
@@ -72,6 +81,12 @@ static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
if (xe->info.platform == XE_DG2)
reg = GT_PERF_STATUS;
break;
+ case REG_PKG_ENERGY_STATUS:
+ if (xe->info.platform == XE_DG2)
+ reg = PCU_CR_PACKAGE_ENERGY_STATUS;
+ else if (xe->info.platform == XE_PVC)
+ reg = PVC_GT0_PLATFORM_ENERGY_STATUS;
+ break;
default:
XE_MISSING_CASE(hwmon_reg);
break;
@@ -192,10 +207,59 @@ static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
return 0;
}
+/*
+ * xe_hwmon_energy_get - Obtain energy value
+ *
+ * The underlying energy hardware register is 32-bits and is subject to
+ * overflow. How long before overflow? For example, with an example
+ * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and
+ * a power draw of 1000 watts, the 32-bit counter will overflow in
+ * approximately 4.36 minutes.
+ *
+ * Examples:
+ * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days
+ * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes
+ *
+ * The function significantly increases overflow duration (from 4.36
+ * minutes) by accumulating the energy register into a 'long' as allowed by
+ * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()),
+ * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and
+ * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
+ * energy1_input overflows. This at 1000 W is an overflow duration of 278 years.
+ */
+static void
+xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)
+{
+ struct hwmon_energy_info *ei = &hwmon->ei;
+ u32 reg_val;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ mutex_lock(&hwmon->hwmon_lock);
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_ENERGY_STATUS, REG_READ,
+ ®_val, 0, 0);
+
+ if (reg_val >= ei->reg_val_prev)
+ ei->accum_energy += reg_val - ei->reg_val_prev;
+ else
+ ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val;
+
+ ei->reg_val_prev = reg_val;
+
+ *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,
+ hwmon->scl_shift_energy);
+
+ mutex_unlock(&hwmon->hwmon_lock);
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+}
+
static const struct hwmon_channel_info *hwmon_info[] = {
HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
+ HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
NULL
};
@@ -369,6 +433,29 @@ xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, long *val)
return ret;
}
+static umode_t
+xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr)
+{
+ switch (attr) {
+ case hwmon_energy_input:
+ return xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS) ? 0444 : 0;
+ default:
+ return 0;
+ }
+}
+
+static int
+xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, long *val)
+{
+ switch (attr) {
+ case hwmon_energy_input:
+ xe_hwmon_energy_get(hwmon, val);
+ return 0;
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
static umode_t
xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
u32 attr, int channel)
@@ -388,6 +475,9 @@ xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
case hwmon_in:
ret = xe_hwmon_in_is_visible(hwmon, attr);
break;
+ case hwmon_energy:
+ ret = xe_hwmon_energy_is_visible(hwmon, attr);
+ break;
default:
ret = 0;
break;
@@ -417,6 +507,9 @@ xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
case hwmon_in:
ret = xe_hwmon_in_read(hwmon, attr, val);
break;
+ case hwmon_energy:
+ ret = xe_hwmon_energy_read(hwmon, attr, val);
+ break;
default:
ret = -EOPNOTSUPP;
break;
@@ -468,6 +561,7 @@ static void
xe_hwmon_get_preregistration_info(struct xe_device *xe)
{
struct xe_hwmon *hwmon = xe->hwmon;
+ long energy;
u32 val_sku_unit = 0;
int ret;
@@ -476,8 +570,17 @@ xe_hwmon_get_preregistration_info(struct xe_device *xe)
* The contents of register PKG_POWER_SKU_UNIT do not change,
* so read it once and store the shift values.
*/
- if (!ret)
+ if (!ret) {
hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
+ hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
+ }
+
+ /*
+ * Initialize 'struct hwmon_energy_info', i.e. set fields to the
+ * first value of the energy register read
+ */
+ if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, 0))
+ xe_hwmon_energy_get(hwmon, &energy);
}
void xe_hwmon_register(struct xe_device *xe)
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-xe] [PATCH v5 6/6] drm/xe/hwmon: Expose power1_max_interval
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-21 10:25 ` Badal Nilawar
-1 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon; +Cc: linux, rodrigo.vivi
Expose power1_max_interval, that is the tau corresponding to PL1, as a
custom hwmon attribute. Some bit manipulation is needed because of the
format of PKG_PWR_LIM_1_TIME in
PACKAGE_RAPL_LIMIT register (1.x * power(2,y))
v2: Get rpm wake ref while accessing power1_max_interval
v3: %s/hwmon/xe_hwmon/
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 11 ++
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 8 +
drivers/gpu/drm/xe/xe_hwmon.c | 138 +++++++++++++++++-
3 files changed, 156 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index 1a7a6c23e141..9ceb9c04b52b 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -59,3 +59,14 @@ Contact: intel-xe@lists.freedesktop.org
Description: RO. Energy input of device in microjoules.
Only supported for particular Intel xe graphics platforms.
+
+What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
+ milliseconds over which sustained power is averaged.
+
+ Only supported for particular Intel xe graphics platforms.
+
+
diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
index d8ecbe1858d1..519dd1067a19 100644
--- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
@@ -22,15 +22,23 @@
#define PKG_TDP GENMASK_ULL(14, 0)
#define PKG_MIN_PWR GENMASK_ULL(30, 16)
#define PKG_MAX_PWR GENMASK_ULL(46, 32)
+#define PKG_MAX_WIN GENMASK_ULL(54, 48)
+#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
+#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
+
#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
#define PKG_PWR_UNIT REG_GENMASK(3, 0)
#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
+#define PKG_TIME_UNIT REG_GENMASK(19, 16)
#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
#define PKG_PWR_LIM_1_EN REG_BIT(15)
+#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
+#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
+#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
#endif /* _XE_MCHBAR_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index cb75b9a386c0..dfa638942d47 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -38,6 +38,7 @@ enum xe_hwmon_reg_operation {
#define SF_CURR 1000 /* milliamperes */
#define SF_VOLTAGE 1000 /* millivolts */
#define SF_ENERGY 1000000 /* microjoules */
+#define SF_TIME 1000 /* milliseconds */
struct hwmon_energy_info {
u32 reg_val_prev;
@@ -50,6 +51,7 @@ struct xe_hwmon {
struct mutex hwmon_lock; /* rmw operations*/
int scl_shift_power;
int scl_shift_energy;
+ int scl_shift_time;
struct hwmon_energy_info ei; /* Energy info for energy1_input */
};
@@ -255,6 +257,138 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)
xe_device_mem_access_put(gt_to_xe(hwmon->gt));
}
+static ssize_t
+xe_hwmon_power1_max_interval_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct xe_hwmon *hwmon = dev_get_drvdata(dev);
+ u32 r, x, y, x_w = 2; /* 2 bits */
+ u64 tau4, out;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
+ REG_READ, &r, 0, 0);
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
+ y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
+ /*
+ * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
+ * = (4 | x) << (y - 2)
+ * where (y - 2) ensures a 1.x fixed point representation of 1.x
+ * However because y can be < 2, we compute
+ * tau4 = (4 | x) << y
+ * but add 2 when doing the final right shift to account for units
+ */
+ tau4 = ((1 << x_w) | x) << y;
+ /* val in hwmon interface units (millisec) */
+ out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
+
+ return sysfs_emit(buf, "%llu\n", out);
+}
+
+static ssize_t
+xe_hwmon_power1_max_interval_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct xe_hwmon *hwmon = dev_get_drvdata(dev);
+ u32 x, y, rxy, x_w = 2; /* 2 bits */
+ u64 tau4, r, max_win;
+ unsigned long val;
+ int ret;
+
+ ret = kstrtoul(buf, 0, &val);
+ if (ret)
+ return ret;
+
+ /*
+ * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12
+ * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds
+ */
+#define PKG_MAX_WIN_DEFAULT 0x12ull
+
+ /*
+ * val must be < max in hwmon interface units. The steps below are
+ * explained in xe_hwmon_power1_max_interval_show()
+ */
+ r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
+ x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
+ y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
+ tau4 = ((1 << x_w) | x) << y;
+ max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
+
+ if (val > max_win)
+ return -EINVAL;
+
+ /* val in hw units */
+ val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
+ /* Convert to 1.x * power(2,y) */
+ if (!val) {
+ /* Avoid ilog2(0) */
+ y = 0;
+ x = 0;
+ } else {
+ y = ilog2(val);
+ /* x = (val - (1 << y)) >> (y - 2); */
+ x = (val - (1ul << y)) << x_w >> y;
+ }
+
+ rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ mutex_lock(&hwmon->hwmon_lock);
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, (u32 *)&r,
+ PKG_PWR_LIM_1_TIME, rxy);
+
+ mutex_unlock(&hwmon->hwmon_lock);
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return count;
+}
+
+static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
+ xe_hwmon_power1_max_interval_show,
+ xe_hwmon_power1_max_interval_store, 0);
+
+static struct attribute *hwmon_attributes[] = {
+ &sensor_dev_attr_power1_max_interval.dev_attr.attr,
+ NULL
+};
+
+static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,
+ struct attribute *attr, int index)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct xe_hwmon *hwmon = dev_get_drvdata(dev);
+ u32 reg_val;
+ int ret = 0;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
+ ret = xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
+ REG_READ, ®_val, 0, 0) ? 0 : attr->mode;
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return ret;
+}
+
+static const struct attribute_group hwmon_attrgroup = {
+ .attrs = hwmon_attributes,
+ .is_visible = xe_hwmon_attributes_visible,
+};
+
+static const struct attribute_group *hwmon_groups[] = {
+ &hwmon_attrgroup,
+ NULL
+};
+
static const struct hwmon_channel_info *hwmon_info[] = {
HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
@@ -573,6 +707,7 @@ xe_hwmon_get_preregistration_info(struct xe_device *xe)
if (!ret) {
hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
+ hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
}
/*
@@ -612,7 +747,8 @@ void xe_hwmon_register(struct xe_device *xe)
"xe",
hwmon,
&hwmon_chip_info,
- NULL);
+ hwmon_groups);
+
if (IS_ERR(hwmon->hwmon_dev)) {
drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
xe->hwmon = NULL;
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [PATCH v5 6/6] drm/xe/hwmon: Expose power1_max_interval
@ 2023-09-21 10:25 ` Badal Nilawar
0 siblings, 0 replies; 53+ messages in thread
From: Badal Nilawar @ 2023-09-21 10:25 UTC (permalink / raw)
To: intel-xe, linux-hwmon
Cc: anshuman.gupta, ashutosh.dixit, linux, andi.shyti, riana.tauro,
matthew.brost, rodrigo.vivi
Expose power1_max_interval, that is the tau corresponding to PL1, as a
custom hwmon attribute. Some bit manipulation is needed because of the
format of PKG_PWR_LIM_1_TIME in
PACKAGE_RAPL_LIMIT register (1.x * power(2,y))
v2: Get rpm wake ref while accessing power1_max_interval
v3: %s/hwmon/xe_hwmon/
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
.../ABI/testing/sysfs-driver-intel-xe-hwmon | 11 ++
drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 8 +
drivers/gpu/drm/xe/xe_hwmon.c | 138 +++++++++++++++++-
3 files changed, 156 insertions(+), 1 deletion(-)
diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
index 1a7a6c23e141..9ceb9c04b52b 100644
--- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
+++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
@@ -59,3 +59,14 @@ Contact: intel-xe@lists.freedesktop.org
Description: RO. Energy input of device in microjoules.
Only supported for particular Intel xe graphics platforms.
+
+What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
+Date: September 2023
+KernelVersion: 6.5
+Contact: intel-xe@lists.freedesktop.org
+Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
+ milliseconds over which sustained power is averaged.
+
+ Only supported for particular Intel xe graphics platforms.
+
+
diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
index d8ecbe1858d1..519dd1067a19 100644
--- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
@@ -22,15 +22,23 @@
#define PKG_TDP GENMASK_ULL(14, 0)
#define PKG_MIN_PWR GENMASK_ULL(30, 16)
#define PKG_MAX_PWR GENMASK_ULL(46, 32)
+#define PKG_MAX_WIN GENMASK_ULL(54, 48)
+#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
+#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
+
#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
#define PKG_PWR_UNIT REG_GENMASK(3, 0)
#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
+#define PKG_TIME_UNIT REG_GENMASK(19, 16)
#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
#define PKG_PWR_LIM_1_EN REG_BIT(15)
+#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
+#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
+#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
#endif /* _XE_MCHBAR_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index cb75b9a386c0..dfa638942d47 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -38,6 +38,7 @@ enum xe_hwmon_reg_operation {
#define SF_CURR 1000 /* milliamperes */
#define SF_VOLTAGE 1000 /* millivolts */
#define SF_ENERGY 1000000 /* microjoules */
+#define SF_TIME 1000 /* milliseconds */
struct hwmon_energy_info {
u32 reg_val_prev;
@@ -50,6 +51,7 @@ struct xe_hwmon {
struct mutex hwmon_lock; /* rmw operations*/
int scl_shift_power;
int scl_shift_energy;
+ int scl_shift_time;
struct hwmon_energy_info ei; /* Energy info for energy1_input */
};
@@ -255,6 +257,138 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)
xe_device_mem_access_put(gt_to_xe(hwmon->gt));
}
+static ssize_t
+xe_hwmon_power1_max_interval_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct xe_hwmon *hwmon = dev_get_drvdata(dev);
+ u32 r, x, y, x_w = 2; /* 2 bits */
+ u64 tau4, out;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
+ REG_READ, &r, 0, 0);
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
+ y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
+ /*
+ * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
+ * = (4 | x) << (y - 2)
+ * where (y - 2) ensures a 1.x fixed point representation of 1.x
+ * However because y can be < 2, we compute
+ * tau4 = (4 | x) << y
+ * but add 2 when doing the final right shift to account for units
+ */
+ tau4 = ((1 << x_w) | x) << y;
+ /* val in hwmon interface units (millisec) */
+ out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
+
+ return sysfs_emit(buf, "%llu\n", out);
+}
+
+static ssize_t
+xe_hwmon_power1_max_interval_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct xe_hwmon *hwmon = dev_get_drvdata(dev);
+ u32 x, y, rxy, x_w = 2; /* 2 bits */
+ u64 tau4, r, max_win;
+ unsigned long val;
+ int ret;
+
+ ret = kstrtoul(buf, 0, &val);
+ if (ret)
+ return ret;
+
+ /*
+ * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12
+ * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds
+ */
+#define PKG_MAX_WIN_DEFAULT 0x12ull
+
+ /*
+ * val must be < max in hwmon interface units. The steps below are
+ * explained in xe_hwmon_power1_max_interval_show()
+ */
+ r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
+ x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
+ y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
+ tau4 = ((1 << x_w) | x) << y;
+ max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
+
+ if (val > max_win)
+ return -EINVAL;
+
+ /* val in hw units */
+ val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
+ /* Convert to 1.x * power(2,y) */
+ if (!val) {
+ /* Avoid ilog2(0) */
+ y = 0;
+ x = 0;
+ } else {
+ y = ilog2(val);
+ /* x = (val - (1 << y)) >> (y - 2); */
+ x = (val - (1ul << y)) << x_w >> y;
+ }
+
+ rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ mutex_lock(&hwmon->hwmon_lock);
+
+ xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, (u32 *)&r,
+ PKG_PWR_LIM_1_TIME, rxy);
+
+ mutex_unlock(&hwmon->hwmon_lock);
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return count;
+}
+
+static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
+ xe_hwmon_power1_max_interval_show,
+ xe_hwmon_power1_max_interval_store, 0);
+
+static struct attribute *hwmon_attributes[] = {
+ &sensor_dev_attr_power1_max_interval.dev_attr.attr,
+ NULL
+};
+
+static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,
+ struct attribute *attr, int index)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct xe_hwmon *hwmon = dev_get_drvdata(dev);
+ u32 reg_val;
+ int ret = 0;
+
+ xe_device_mem_access_get(gt_to_xe(hwmon->gt));
+
+ if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
+ ret = xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
+ REG_READ, ®_val, 0, 0) ? 0 : attr->mode;
+
+ xe_device_mem_access_put(gt_to_xe(hwmon->gt));
+
+ return ret;
+}
+
+static const struct attribute_group hwmon_attrgroup = {
+ .attrs = hwmon_attributes,
+ .is_visible = xe_hwmon_attributes_visible,
+};
+
+static const struct attribute_group *hwmon_groups[] = {
+ &hwmon_attrgroup,
+ NULL
+};
+
static const struct hwmon_channel_info *hwmon_info[] = {
HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
@@ -573,6 +707,7 @@ xe_hwmon_get_preregistration_info(struct xe_device *xe)
if (!ret) {
hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
+ hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
}
/*
@@ -612,7 +747,8 @@ void xe_hwmon_register(struct xe_device *xe)
"xe",
hwmon,
&hwmon_chip_info,
- NULL);
+ hwmon_groups);
+
if (IS_ERR(hwmon->hwmon_dev)) {
drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
xe->hwmon = NULL;
--
2.25.1
^ permalink raw reply related [flat|nested] 53+ messages in thread
* [Intel-xe] ✓ CI.Build: success for Add HWMON support for DGFX (rev5)
2023-09-21 10:25 ` Badal Nilawar
` (9 preceding siblings ...)
(?)
@ 2023-09-21 10:30 ` Patchwork
-1 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2023-09-21 10:30 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
== Series Details ==
Series: Add HWMON support for DGFX (rev5)
URL : https://patchwork.freedesktop.org/series/118934/
State : success
== Summary ==
+ trap cleanup EXIT
+ cd /kernel
+ git clone https://gitlab.freedesktop.org/drm/xe/ci.git .ci
Cloning into '.ci'...
++ date +%s
+ echo -e '\e[0Ksection_start:1695291789:build_x86_64[collapsed=true]\r\e[0KBuild x86-64'
+ mkdir -p build64-default
^[[0Ksection_start:1695291789:build_x86_64[collapsed=true]
^[[0KBuild x86-64
+ cp .ci/kernel/kconfig build64-default/.config
+ make O=build64-default olddefconfig
make[1]: Entering directory '/kernel/build64-default'
GEN Makefile
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/conf.o
HOSTCC scripts/kconfig/confdata.o
HOSTCC scripts/kconfig/expr.o
LEX scripts/kconfig/lexer.lex.c
YACC scripts/kconfig/parser.tab.[ch]
HOSTCC scripts/kconfig/lexer.lex.o
HOSTCC scripts/kconfig/menu.o
HOSTCC scripts/kconfig/parser.tab.o
HOSTCC scripts/kconfig/preprocess.o
HOSTCC scripts/kconfig/symbol.o
HOSTCC scripts/kconfig/util.o
HOSTLD scripts/kconfig/conf
#
# configuration written to .config
#
make[1]: Leaving directory '/kernel/build64-default'
++ nproc
+ make O=build64-default -j48
make[1]: Entering directory '/kernel/build64-default'
GEN Makefile
SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h
WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h
WRAP arch/x86/include/generated/uapi/asm/errno.h
SYSTBL arch/x86/include/generated/asm/syscalls_32.h
SYSHDR arch/x86/include/generated/asm/unistd_32_ia32.h
GEN arch/x86/include/generated/asm/orc_hash.h
WRAP arch/x86/include/generated/uapi/asm/fcntl.h
SYSHDR arch/x86/include/generated/asm/unistd_64_x32.h
WRAP arch/x86/include/generated/uapi/asm/ioctl.h
SYSTBL arch/x86/include/generated/asm/syscalls_64.h
WRAP arch/x86/include/generated/uapi/asm/ioctls.h
WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h
WRAP arch/x86/include/generated/uapi/asm/param.h
WRAP arch/x86/include/generated/uapi/asm/poll.h
WRAP arch/x86/include/generated/uapi/asm/resource.h
WRAP arch/x86/include/generated/uapi/asm/sockios.h
WRAP arch/x86/include/generated/uapi/asm/socket.h
WRAP arch/x86/include/generated/uapi/asm/termbits.h
WRAP arch/x86/include/generated/uapi/asm/termios.h
WRAP arch/x86/include/generated/uapi/asm/types.h
HOSTCC arch/x86/tools/relocs_32.o
HOSTCC arch/x86/tools/relocs_64.o
HOSTCC arch/x86/tools/relocs_common.o
WRAP arch/x86/include/generated/asm/early_ioremap.h
WRAP arch/x86/include/generated/asm/export.h
WRAP arch/x86/include/generated/asm/mcs_spinlock.h
WRAP arch/x86/include/generated/asm/irq_regs.h
WRAP arch/x86/include/generated/asm/kmap_size.h
WRAP arch/x86/include/generated/asm/local64.h
WRAP arch/x86/include/generated/asm/mmiowb.h
WRAP arch/x86/include/generated/asm/module.lds.h
WRAP arch/x86/include/generated/asm/rwonce.h
UPD include/generated/uapi/linux/version.h
WRAP arch/x86/include/generated/asm/unaligned.h
UPD include/config/kernel.release
UPD include/generated/compile.h
HOSTCC scripts/kallsyms
HOSTCC scripts/sorttable
HOSTCC scripts/asn1_compiler
HOSTCC scripts/unifdef
UPD include/generated/utsrelease.h
DESCEND objtool
HOSTCC /kernel/build64-default/tools/objtool/fixdep.o
HOSTLD /kernel/build64-default/tools/objtool/fixdep-in.o
LINK /kernel/build64-default/tools/objtool/fixdep
HOSTLD arch/x86/tools/relocs
INSTALL /kernel/build64-default/tools/objtool/libsubcmd/include/subcmd/exec-cmd.h
INSTALL /kernel/build64-default/tools/objtool/libsubcmd/include/subcmd/help.h
INSTALL /kernel/build64-default/tools/objtool/libsubcmd/include/subcmd/pager.h
INSTALL /kernel/build64-default/tools/objtool/libsubcmd/include/subcmd/parse-options.h
INSTALL /kernel/build64-default/tools/objtool/libsubcmd/include/subcmd/run-command.h
CC /kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o
CC /kernel/build64-default/tools/objtool/libsubcmd/help.o
CC /kernel/build64-default/tools/objtool/libsubcmd/pager.o
INSTALL libsubcmd_headers
CC /kernel/build64-default/tools/objtool/libsubcmd/parse-options.o
CC /kernel/build64-default/tools/objtool/libsubcmd/run-command.o
CC /kernel/build64-default/tools/objtool/libsubcmd/sigchain.o
CC /kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o
CC scripts/mod/empty.o
HOSTCC scripts/mod/mk_elfconfig
CC scripts/mod/devicetable-offsets.s
HDRINST usr/include/video/edid.h
HDRINST usr/include/video/sisfb.h
HDRINST usr/include/video/uvesafb.h
HDRINST usr/include/drm/amdgpu_drm.h
HDRINST usr/include/drm/qaic_accel.h
HDRINST usr/include/drm/i915_drm.h
HDRINST usr/include/drm/vgem_drm.h
HDRINST usr/include/drm/virtgpu_drm.h
HDRINST usr/include/drm/xe_drm.h
HDRINST usr/include/drm/omap_drm.h
HDRINST usr/include/drm/tegra_drm.h
HDRINST usr/include/drm/radeon_drm.h
HDRINST usr/include/drm/drm_mode.h
HDRINST usr/include/drm/ivpu_accel.h
HDRINST usr/include/drm/exynos_drm.h
HDRINST usr/include/drm/drm_sarea.h
HDRINST usr/include/drm/qxl_drm.h
HDRINST usr/include/drm/v3d_drm.h
HDRINST usr/include/drm/drm_fourcc.h
HDRINST usr/include/drm/nouveau_drm.h
HDRINST usr/include/drm/habanalabs_accel.h
HDRINST usr/include/drm/vmwgfx_drm.h
HDRINST usr/include/drm/msm_drm.h
HDRINST usr/include/drm/etnaviv_drm.h
HDRINST usr/include/drm/panfrost_drm.h
HDRINST usr/include/drm/vc4_drm.h
HDRINST usr/include/drm/drm.h
HDRINST usr/include/drm/lima_drm.h
HDRINST usr/include/drm/armada_drm.h
HDRINST usr/include/mtd/inftl-user.h
HDRINST usr/include/mtd/nftl-user.h
HDRINST usr/include/mtd/mtd-user.h
HDRINST usr/include/mtd/ubi-user.h
HDRINST usr/include/mtd/mtd-abi.h
HDRINST usr/include/xen/gntdev.h
HDRINST usr/include/xen/gntalloc.h
HDRINST usr/include/xen/evtchn.h
HDRINST usr/include/xen/privcmd.h
HDRINST usr/include/asm-generic/auxvec.h
HDRINST usr/include/asm-generic/bitsperlong.h
HDRINST usr/include/asm-generic/posix_types.h
HDRINST usr/include/asm-generic/ioctls.h
HDRINST usr/include/asm-generic/mman.h
HDRINST usr/include/asm-generic/shmbuf.h
HDRINST usr/include/asm-generic/bpf_perf_event.h
HDRINST usr/include/asm-generic/types.h
HDRINST usr/include/asm-generic/poll.h
HDRINST usr/include/asm-generic/msgbuf.h
HDRINST usr/include/asm-generic/swab.h
HDRINST usr/include/asm-generic/statfs.h
HDRINST usr/include/asm-generic/unistd.h
HDRINST usr/include/asm-generic/hugetlb_encode.h
HDRINST usr/include/asm-generic/resource.h
UPD scripts/mod/devicetable-offsets.h
HDRINST usr/include/asm-generic/param.h
HDRINST usr/include/asm-generic/termbits-common.h
HDRINST usr/include/asm-generic/sockios.h
HDRINST usr/include/asm-generic/kvm_para.h
HDRINST usr/include/asm-generic/errno.h
HDRINST usr/include/asm-generic/termios.h
HDRINST usr/include/asm-generic/mman-common.h
HDRINST usr/include/asm-generic/ioctl.h
HDRINST usr/include/asm-generic/socket.h
HDRINST usr/include/asm-generic/signal-defs.h
HDRINST usr/include/asm-generic/termbits.h
HDRINST usr/include/asm-generic/int-ll64.h
HDRINST usr/include/asm-generic/signal.h
HDRINST usr/include/asm-generic/siginfo.h
HDRINST usr/include/asm-generic/stat.h
HDRINST usr/include/asm-generic/int-l64.h
HDRINST usr/include/asm-generic/errno-base.h
HDRINST usr/include/asm-generic/fcntl.h
HDRINST usr/include/asm-generic/setup.h
HDRINST usr/include/asm-generic/ipcbuf.h
HDRINST usr/include/asm-generic/sembuf.h
HDRINST usr/include/asm-generic/ucontext.h
HDRINST usr/include/rdma/mlx5_user_ioctl_cmds.h
HDRINST usr/include/rdma/irdma-abi.h
HDRINST usr/include/rdma/mana-abi.h
HDRINST usr/include/rdma/hfi/hfi1_user.h
HDRINST usr/include/rdma/hfi/hfi1_ioctl.h
HDRINST usr/include/rdma/rdma_user_rxe.h
HDRINST usr/include/rdma/rdma_user_ioctl.h
HDRINST usr/include/rdma/mlx5_user_ioctl_verbs.h
HDRINST usr/include/rdma/bnxt_re-abi.h
HDRINST usr/include/rdma/hns-abi.h
HDRINST usr/include/rdma/qedr-abi.h
MKELF scripts/mod/elfconfig.h
HDRINST usr/include/rdma/ib_user_ioctl_cmds.h
HDRINST usr/include/rdma/vmw_pvrdma-abi.h
HDRINST usr/include/rdma/ib_user_sa.h
HDRINST usr/include/rdma/ib_user_ioctl_verbs.h
HDRINST usr/include/rdma/rvt-abi.h
HDRINST usr/include/rdma/mlx5-abi.h
HOSTCC scripts/mod/modpost.o
HDRINST usr/include/rdma/rdma_netlink.h
HOSTCC scripts/mod/file2alias.o
HDRINST usr/include/rdma/erdma-abi.h
HOSTCC scripts/mod/sumversion.o
HDRINST usr/include/rdma/rdma_user_ioctl_cmds.h
HDRINST usr/include/rdma/rdma_user_cm.h
HDRINST usr/include/rdma/ib_user_verbs.h
HDRINST usr/include/rdma/efa-abi.h
HDRINST usr/include/rdma/siw-abi.h
HDRINST usr/include/rdma/mlx4-abi.h
HDRINST usr/include/rdma/mthca-abi.h
HDRINST usr/include/rdma/ib_user_mad.h
HDRINST usr/include/rdma/ocrdma-abi.h
HDRINST usr/include/rdma/cxgb4-abi.h
HDRINST usr/include/misc/xilinx_sdfec.h
HDRINST usr/include/misc/uacce/hisi_qm.h
HDRINST usr/include/misc/uacce/uacce.h
HDRINST usr/include/misc/cxl.h
HDRINST usr/include/misc/ocxl.h
HDRINST usr/include/misc/fastrpc.h
HDRINST usr/include/misc/pvpanic.h
HDRINST usr/include/linux/i8k.h
HDRINST usr/include/linux/acct.h
HDRINST usr/include/linux/atmmpc.h
HDRINST usr/include/linux/fs.h
HDRINST usr/include/linux/cifs/cifs_mount.h
HDRINST usr/include/linux/cifs/cifs_netlink.h
HDRINST usr/include/linux/if_packet.h
HDRINST usr/include/linux/route.h
HDRINST usr/include/linux/patchkey.h
HDRINST usr/include/linux/tc_ematch/tc_em_cmp.h
HDRINST usr/include/linux/tc_ematch/tc_em_ipt.h
HDRINST usr/include/linux/tc_ematch/tc_em_meta.h
HDRINST usr/include/linux/tc_ematch/tc_em_nbyte.h
HDRINST usr/include/linux/tc_ematch/tc_em_text.h
HDRINST usr/include/linux/virtio_pmem.h
HDRINST usr/include/linux/rkisp1-config.h
HDRINST usr/include/linux/vhost.h
HDRINST usr/include/linux/cec-funcs.h
HDRINST usr/include/linux/ppdev.h
HDRINST usr/include/linux/isdn/capicmd.h
HDRINST usr/include/linux/virtio_fs.h
HDRINST usr/include/linux/netfilter_ipv6.h
HDRINST usr/include/linux/lirc.h
HDRINST usr/include/linux/mroute6.h
HDRINST usr/include/linux/nl80211-vnd-intel.h
HDRINST usr/include/linux/ivtvfb.h
HDRINST usr/include/linux/auxvec.h
HDRINST usr/include/linux/dm-log-userspace.h
HDRINST usr/include/linux/dccp.h
HDRINST usr/include/linux/virtio_scmi.h
HDRINST usr/include/linux/atmarp.h
HDRINST usr/include/linux/arcfb.h
HDRINST usr/include/linux/nbd-netlink.h
HDRINST usr/include/linux/sched/types.h
HDRINST usr/include/linux/tcp.h
HDRINST usr/include/linux/neighbour.h
HDRINST usr/include/linux/dlm_device.h
HDRINST usr/include/linux/wmi.h
HDRINST usr/include/linux/btrfs_tree.h
HDRINST usr/include/linux/virtio_crypto.h
HDRINST usr/include/linux/vbox_err.h
HDRINST usr/include/linux/edd.h
HDRINST usr/include/linux/loop.h
HDRINST usr/include/linux/nvme_ioctl.h
HDRINST usr/include/linux/mmtimer.h
HDRINST usr/include/linux/if_pppol2tp.h
HDRINST usr/include/linux/mtio.h
HDRINST usr/include/linux/if_arcnet.h
HDRINST usr/include/linux/romfs_fs.h
HDRINST usr/include/linux/posix_types.h
HDRINST usr/include/linux/rtc.h
HDRINST usr/include/linux/landlock.h
HDRINST usr/include/linux/gpio.h
HDRINST usr/include/linux/selinux_netlink.h
HDRINST usr/include/linux/pps.h
HDRINST usr/include/linux/ndctl.h
HDRINST usr/include/linux/virtio_gpu.h
HDRINST usr/include/linux/android/binderfs.h
HDRINST usr/include/linux/android/binder.h
HDRINST usr/include/linux/virtio_vsock.h
HDRINST usr/include/linux/sound.h
HDRINST usr/include/linux/vtpm_proxy.h
HDRINST usr/include/linux/nfs_fs.h
HDRINST usr/include/linux/elf-fdpic.h
HDRINST usr/include/linux/adfs_fs.h
HDRINST usr/include/linux/target_core_user.h
HDRINST usr/include/linux/netlink_diag.h
HDRINST usr/include/linux/const.h
HDRINST usr/include/linux/firewire-cdev.h
HDRINST usr/include/linux/vdpa.h
HDRINST usr/include/linux/if_infiniband.h
HDRINST usr/include/linux/serial.h
HDRINST usr/include/linux/iio/types.h
HDRINST usr/include/linux/iio/buffer.h
HDRINST usr/include/linux/iio/events.h
HDRINST usr/include/linux/baycom.h
HDRINST usr/include/linux/major.h
HDRINST usr/include/linux/atmppp.h
HDRINST usr/include/linux/ipv6_route.h
HDRINST usr/include/linux/spi/spidev.h
HDRINST usr/include/linux/spi/spi.h
HDRINST usr/include/linux/virtio_ring.h
HDRINST usr/include/linux/hdlc/ioctl.h
HDRINST usr/include/linux/remoteproc_cdev.h
HDRINST usr/include/linux/hyperv.h
HDRINST usr/include/linux/rpl_iptunnel.h
HDRINST usr/include/linux/sync_file.h
HDRINST usr/include/linux/igmp.h
HDRINST usr/include/linux/v4l2-dv-timings.h
HDRINST usr/include/linux/virtio_i2c.h
HDRINST usr/include/linux/xfrm.h
HDRINST usr/include/linux/capability.h
HDRINST usr/include/linux/gtp.h
HDRINST usr/include/linux/xdp_diag.h
HDRINST usr/include/linux/pkt_cls.h
HDRINST usr/include/linux/suspend_ioctls.h
HDRINST usr/include/linux/vt.h
HDRINST usr/include/linux/loadpin.h
HDRINST usr/include/linux/dlm_plock.h
HDRINST usr/include/linux/fb.h
HDRINST usr/include/linux/max2175.h
HDRINST usr/include/linux/sunrpc/debug.h
HDRINST usr/include/linux/gsmmux.h
HDRINST usr/include/linux/watchdog.h
HDRINST usr/include/linux/vhost_types.h
HDRINST usr/include/linux/vduse.h
HDRINST usr/include/linux/ila.h
HDRINST usr/include/linux/tdx-guest.h
HDRINST usr/include/linux/close_range.h
HDRINST usr/include/linux/ivtv.h
HDRINST usr/include/linux/cryptouser.h
HDRINST usr/include/linux/netfilter/xt_string.h
HDRINST usr/include/linux/netfilter/nfnetlink_compat.h
HDRINST usr/include/linux/netfilter/nf_nat.h
HDRINST usr/include/linux/netfilter/xt_recent.h
HDRINST usr/include/linux/netfilter/xt_addrtype.h
HDRINST usr/include/linux/netfilter/nf_conntrack_tcp.h
HDRINST usr/include/linux/netfilter/xt_MARK.h
HDRINST usr/include/linux/netfilter/xt_SYNPROXY.h
HDRINST usr/include/linux/netfilter/xt_multiport.h
HDRINST usr/include/linux/netfilter/nfnetlink.h
HDRINST usr/include/linux/netfilter/xt_cgroup.h
HDRINST usr/include/linux/netfilter/nf_synproxy.h
HDRINST usr/include/linux/netfilter/xt_TCPOPTSTRIP.h
HDRINST usr/include/linux/netfilter/nfnetlink_log.h
HDRINST usr/include/linux/netfilter/xt_TPROXY.h
HDRINST usr/include/linux/netfilter/xt_u32.h
HDRINST usr/include/linux/netfilter/nfnetlink_osf.h
HDRINST usr/include/linux/netfilter/xt_ecn.h
HDRINST usr/include/linux/netfilter/xt_esp.h
HDRINST usr/include/linux/netfilter/nfnetlink_hook.h
HDRINST usr/include/linux/netfilter/xt_mac.h
HDRINST usr/include/linux/netfilter/xt_comment.h
HDRINST usr/include/linux/netfilter/xt_NFQUEUE.h
HDRINST usr/include/linux/netfilter/xt_osf.h
HDRINST usr/include/linux/netfilter/xt_hashlimit.h
HDRINST usr/include/linux/netfilter/nf_conntrack_sctp.h
HDRINST usr/include/linux/netfilter/xt_socket.h
HDRINST usr/include/linux/netfilter/xt_connmark.h
HDRINST usr/include/linux/netfilter/xt_sctp.h
HDRINST usr/include/linux/netfilter/xt_tcpudp.h
HDRINST usr/include/linux/netfilter/xt_DSCP.h
HDRINST usr/include/linux/netfilter/xt_time.h
HDRINST usr/include/linux/netfilter/xt_IDLETIMER.h
HDRINST usr/include/linux/netfilter/xt_policy.h
HDRINST usr/include/linux/netfilter/xt_rpfilter.h
HDRINST usr/include/linux/netfilter/xt_nfacct.h
HDRINST usr/include/linux/netfilter/xt_SECMARK.h
HDRINST usr/include/linux/netfilter/xt_length.h
HDRINST usr/include/linux/netfilter/nfnetlink_cthelper.h
HDRINST usr/include/linux/netfilter/xt_quota.h
HDRINST usr/include/linux/netfilter/xt_CLASSIFY.h
HDRINST usr/include/linux/netfilter/xt_ipcomp.h
HDRINST usr/include/linux/netfilter/xt_iprange.h
HDRINST usr/include/linux/netfilter/xt_bpf.h
HDRINST usr/include/linux/netfilter/xt_LOG.h
HDRINST usr/include/linux/netfilter/xt_rateest.h
HDRINST usr/include/linux/netfilter/xt_CONNSECMARK.h
HDRINST usr/include/linux/netfilter/xt_HMARK.h
HDRINST usr/include/linux/netfilter/xt_CONNMARK.h
HDRINST usr/include/linux/netfilter/xt_pkttype.h
HDRINST usr/include/linux/netfilter/xt_ipvs.h
HDRINST usr/include/linux/netfilter/xt_devgroup.h
HDRINST usr/include/linux/netfilter/xt_AUDIT.h
HDRINST usr/include/linux/netfilter/xt_realm.h
HDRINST usr/include/linux/netfilter/nf_conntrack_common.h
HDRINST usr/include/linux/netfilter/xt_set.h
HDRINST usr/include/linux/netfilter/xt_LED.h
HDRINST usr/include/linux/netfilter/xt_connlabel.h
HDRINST usr/include/linux/netfilter/xt_owner.h
HDRINST usr/include/linux/netfilter/xt_dccp.h
HDRINST usr/include/linux/netfilter/xt_limit.h
HDRINST usr/include/linux/netfilter/xt_conntrack.h
HDRINST usr/include/linux/netfilter/xt_TEE.h
HDRINST usr/include/linux/netfilter/xt_RATEEST.h
HDRINST usr/include/linux/netfilter/xt_connlimit.h
HDRINST usr/include/linux/netfilter/ipset/ip_set.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_list.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_hash.h
HDRINST usr/include/linux/netfilter/ipset/ip_set_bitmap.h
HDRINST usr/include/linux/netfilter/x_tables.h
HDRINST usr/include/linux/netfilter/xt_dscp.h
HDRINST usr/include/linux/netfilter/nf_conntrack_ftp.h
HDRINST usr/include/linux/netfilter/xt_cluster.h
HDRINST usr/include/linux/netfilter/nf_conntrack_tuple_common.h
HDRINST usr/include/linux/netfilter/nf_log.h
HDRINST usr/include/linux/netfilter/xt_tcpmss.h
HDRINST usr/include/linux/netfilter/xt_NFLOG.h
HDRINST usr/include/linux/netfilter/xt_l2tp.h
HDRINST usr/include/linux/netfilter/xt_helper.h
HDRINST usr/include/linux/netfilter/xt_statistic.h
HDRINST usr/include/linux/netfilter/nfnetlink_queue.h
HDRINST usr/include/linux/netfilter/nfnetlink_cttimeout.h
HDRINST usr/include/linux/netfilter/xt_CT.h
HDRINST usr/include/linux/netfilter/xt_CHECKSUM.h
HDRINST usr/include/linux/netfilter/xt_connbytes.h
HDRINST usr/include/linux/netfilter/xt_state.h
HDRINST usr/include/linux/netfilter/nf_tables.h
HDRINST usr/include/linux/netfilter/xt_mark.h
HDRINST usr/include/linux/netfilter/xt_cpu.h
HDRINST usr/include/linux/netfilter/nf_tables_compat.h
HDRINST usr/include/linux/netfilter/xt_physdev.h
HDRINST usr/include/linux/netfilter/nfnetlink_conntrack.h
HDRINST usr/include/linux/netfilter/nfnetlink_acct.h
HDRINST usr/include/linux/netfilter/xt_TCPMSS.h
HDRINST usr/include/linux/tty_flags.h
HDRINST usr/include/linux/if_phonet.h
HDRINST usr/include/linux/elf-em.h
HDRINST usr/include/linux/vm_sockets.h
HDRINST usr/include/linux/dlmconstants.h
HDRINST usr/include/linux/bsg.h
HDRINST usr/include/linux/matroxfb.h
HDRINST usr/include/linux/sysctl.h
HDRINST usr/include/linux/unix_diag.h
HDRINST usr/include/linux/pcitest.h
HDRINST usr/include/linux/mman.h
HDRINST usr/include/linux/if_plip.h
HDRINST usr/include/linux/virtio_balloon.h
HDRINST usr/include/linux/pidfd.h
HDRINST usr/include/linux/f2fs.h
HDRINST usr/include/linux/x25.h
HDRINST usr/include/linux/if_cablemodem.h
HDRINST usr/include/linux/utsname.h
HDRINST usr/include/linux/counter.h
HDRINST usr/include/linux/atm_tcp.h
HDRINST usr/include/linux/atalk.h
HDRINST usr/include/linux/virtio_rng.h
HDRINST usr/include/linux/vboxguest.h
HDRINST usr/include/linux/bpf_perf_event.h
HDRINST usr/include/linux/ipmi_ssif_bmc.h
HDRINST usr/include/linux/nfs_mount.h
HDRINST usr/include/linux/sonet.h
HDRINST usr/include/linux/netfilter.h
HDRINST usr/include/linux/keyctl.h
HDRINST usr/include/linux/nl80211.h
HDRINST usr/include/linux/misc/bcm_vk.h
HDRINST usr/include/linux/audit.h
HDRINST usr/include/linux/tipc_config.h
HDRINST usr/include/linux/tipc_sockets_diag.h
HDRINST usr/include/linux/futex.h
HDRINST usr/include/linux/sev-guest.h
HDRINST usr/include/linux/ublk_cmd.h
HDRINST usr/include/linux/types.h
HDRINST usr/include/linux/virtio_input.h
HDRINST usr/include/linux/if_slip.h
HDRINST usr/include/linux/personality.h
HDRINST usr/include/linux/openat2.h
HDRINST usr/include/linux/poll.h
HDRINST usr/include/linux/posix_acl.h
HDRINST usr/include/linux/smc_diag.h
HDRINST usr/include/linux/snmp.h
HDRINST usr/include/linux/errqueue.h
HDRINST usr/include/linux/if_tunnel.h
HDRINST usr/include/linux/fanotify.h
HDRINST usr/include/linux/kernel.h
HDRINST usr/include/linux/rtnetlink.h
HDRINST usr/include/linux/rpl.h
HDRINST usr/include/linux/memfd.h
HDRINST usr/include/linux/serial_core.h
HDRINST usr/include/linux/dns_resolver.h
HDRINST usr/include/linux/pr.h
HDRINST usr/include/linux/atm_eni.h
HDRINST usr/include/linux/lp.h
HDRINST usr/include/linux/virtio_mem.h
HDRINST usr/include/linux/ultrasound.h
HDRINST usr/include/linux/sctp.h
HDRINST usr/include/linux/uio.h
HDRINST usr/include/linux/tcp_metrics.h
HDRINST usr/include/linux/wwan.h
HDRINST usr/include/linux/atmbr2684.h
HDRINST usr/include/linux/in_route.h
HDRINST usr/include/linux/qemu_fw_cfg.h
HDRINST usr/include/linux/if_macsec.h
HDRINST usr/include/linux/usb/charger.h
HDRINST usr/include/linux/usb/g_uvc.h
HDRINST usr/include/linux/usb/gadgetfs.h
HDRINST usr/include/linux/usb/raw_gadget.h
HDRINST usr/include/linux/usb/cdc-wdm.h
HDRINST usr/include/linux/usb/g_printer.h
HDRINST usr/include/linux/usb/midi.h
HDRINST usr/include/linux/usb/tmc.h
HDRINST usr/include/linux/usb/video.h
HDRINST usr/include/linux/usb/functionfs.h
HDRINST usr/include/linux/usb/audio.h
HDRINST usr/include/linux/usb/ch11.h
HDRINST usr/include/linux/usb/ch9.h
HDRINST usr/include/linux/usb/cdc.h
HDRINST usr/include/linux/jffs2.h
HDRINST usr/include/linux/ax25.h
HDRINST usr/include/linux/auto_fs.h
HDRINST usr/include/linux/tiocl.h
HDRINST usr/include/linux/scc.h
HDRINST usr/include/linux/psci.h
HDRINST usr/include/linux/swab.h
HDRINST usr/include/linux/cec.h
HDRINST usr/include/linux/kfd_ioctl.h
HDRINST usr/include/linux/smc.h
HDRINST usr/include/linux/qrtr.h
HDRINST usr/include/linux/screen_info.h
HDRINST usr/include/linux/nfsacl.h
HDRINST usr/include/linux/seg6_hmac.h
HDRINST usr/include/linux/gameport.h
HDRINST usr/include/linux/wireless.h
HDRINST usr/include/linux/fdreg.h
HDRINST usr/include/linux/cciss_defs.h
HDRINST usr/include/linux/serial_reg.h
HDRINST usr/include/linux/perf_event.h
HDRINST usr/include/linux/in6.h
HDRINST usr/include/linux/hid.h
HDRINST usr/include/linux/netlink.h
HDRINST usr/include/linux/fuse.h
HDRINST usr/include/linux/magic.h
HDRINST usr/include/linux/ioam6_iptunnel.h
HDRINST usr/include/linux/stm.h
HDRINST usr/include/linux/vsockmon.h
HDRINST usr/include/linux/seg6.h
HDRINST usr/include/linux/idxd.h
HDRINST usr/include/linux/nitro_enclaves.h
HDRINST usr/include/linux/ptrace.h
HDRINST usr/include/linux/ioam6_genl.h
HDRINST usr/include/linux/qnx4_fs.h
HDRINST usr/include/linux/fsl_mc.h
HDRINST usr/include/linux/net_tstamp.h
HDRINST usr/include/linux/msg.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_TTL.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ttl.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ah.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ECN.h
HDRINST usr/include/linux/netfilter_ipv4/ip_tables.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_ecn.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_REJECT.h
HDRINST usr/include/linux/netfilter_ipv4/ipt_LOG.h
HDRINST usr/include/linux/sem.h
HDRINST usr/include/linux/net_namespace.h
HDRINST usr/include/linux/radeonfb.h
HDRINST usr/include/linux/tee.h
HDRINST usr/include/linux/udp.h
HDRINST usr/include/linux/virtio_bt.h
HDRINST usr/include/linux/v4l2-subdev.h
HDRINST usr/include/linux/posix_acl_xattr.h
HDRINST usr/include/linux/v4l2-mediabus.h
HDRINST usr/include/linux/atmapi.h
HDRINST usr/include/linux/raid/md_p.h
HDRINST usr/include/linux/raid/md_u.h
HDRINST usr/include/linux/zorro_ids.h
HDRINST usr/include/linux/nbd.h
HDRINST usr/include/linux/isst_if.h
HDRINST usr/include/linux/rxrpc.h
HDRINST usr/include/linux/unistd.h
HDRINST usr/include/linux/if_arp.h
HDRINST usr/include/linux/atm_zatm.h
HDRINST usr/include/linux/io_uring.h
HDRINST usr/include/linux/if_fddi.h
HDRINST usr/include/linux/bpqether.h
HDRINST usr/include/linux/sysinfo.h
HDRINST usr/include/linux/auto_dev-ioctl.h
HDRINST usr/include/linux/nfs4_mount.h
HDRINST usr/include/linux/keyboard.h
HDRINST usr/include/linux/virtio_mmio.h
HDRINST usr/include/linux/input.h
HDRINST usr/include/linux/qnxtypes.h
HDRINST usr/include/linux/mdio.h
HDRINST usr/include/linux/lwtunnel.h
HDRINST usr/include/linux/gfs2_ondisk.h
HDRINST usr/include/linux/eventfd.h
HDRINST usr/include/linux/nfs4.h
HDRINST usr/include/linux/ptp_clock.h
HDRINST usr/include/linux/nubus.h
HDRINST usr/include/linux/if_bonding.h
HDRINST usr/include/linux/kcov.h
HDRINST usr/include/linux/fadvise.h
HDRINST usr/include/linux/taskstats.h
HDRINST usr/include/linux/veth.h
HDRINST usr/include/linux/atm.h
HDRINST usr/include/linux/ipmi.h
HDRINST usr/include/linux/kdev_t.h
HDRINST usr/include/linux/mount.h
HDRINST usr/include/linux/shm.h
HDRINST usr/include/linux/resource.h
HDRINST usr/include/linux/prctl.h
HDRINST usr/include/linux/watch_queue.h
HDRINST usr/include/linux/sched.h
HDRINST usr/include/linux/phonet.h
HDRINST usr/include/linux/random.h
HDRINST usr/include/linux/tty.h
HDRINST usr/include/linux/apm_bios.h
HDRINST usr/include/linux/fd.h
HDRINST usr/include/linux/um_timetravel.h
HDRINST usr/include/linux/tls.h
HDRINST usr/include/linux/rpmsg_types.h
HDRINST usr/include/linux/pfrut.h
HDRINST usr/include/linux/mei.h
HDRINST usr/include/linux/fsi.h
HDRINST usr/include/linux/rds.h
HDRINST usr/include/linux/if_x25.h
HDRINST usr/include/linux/param.h
HDRINST usr/include/linux/netdevice.h
HDRINST usr/include/linux/binfmts.h
HDRINST usr/include/linux/if_pppox.h
HDRINST usr/include/linux/sockios.h
HDRINST usr/include/linux/kcm.h
HDRINST usr/include/linux/virtio_9p.h
HDRINST usr/include/linux/genwqe/genwqe_card.h
HDRINST usr/include/linux/if_tun.h
HDRINST usr/include/linux/ext4.h
HDRINST usr/include/linux/if_ether.h
HDRINST usr/include/linux/kvm_para.h
HDRINST usr/include/linux/kernel-page-flags.h
HDRINST usr/include/linux/cdrom.h
HDRINST usr/include/linux/un.h
HDRINST usr/include/linux/module.h
HDRINST usr/include/linux/mqueue.h
HDRINST usr/include/linux/a.out.h
HDRINST usr/include/linux/input-event-codes.h
HDRINST usr/include/linux/coda.h
HDRINST usr/include/linux/rio_mport_cdev.h
HDRINST usr/include/linux/ipsec.h
HDRINST usr/include/linux/blkpg.h
HDRINST usr/include/linux/blkzoned.h
HDRINST usr/include/linux/netfilter_bridge/ebt_arpreply.h
HDRINST usr/include/linux/netfilter_bridge/ebt_redirect.h
HDRINST usr/include/linux/netfilter_bridge/ebt_nflog.h
HDRINST usr/include/linux/netfilter_bridge/ebt_802_3.h
HDRINST usr/include/linux/netfilter_bridge/ebt_nat.h
HDRINST usr/include/linux/netfilter_bridge/ebt_mark_m.h
HDRINST usr/include/linux/netfilter_bridge/ebtables.h
HDRINST usr/include/linux/netfilter_bridge/ebt_vlan.h
HDRINST usr/include/linux/netfilter_bridge/ebt_limit.h
HDRINST usr/include/linux/netfilter_bridge/ebt_log.h
HDRINST usr/include/linux/netfilter_bridge/ebt_stp.h
HDRINST usr/include/linux/netfilter_bridge/ebt_pkttype.h
HDRINST usr/include/linux/netfilter_bridge/ebt_ip.h
HDRINST usr/include/linux/netfilter_bridge/ebt_ip6.h
HDRINST usr/include/linux/netfilter_bridge/ebt_arp.h
HDRINST usr/include/linux/netfilter_bridge/ebt_mark_t.h
HDRINST usr/include/linux/netfilter_bridge/ebt_among.h
HDRINST usr/include/linux/reiserfs_fs.h
HDRINST usr/include/linux/cciss_ioctl.h
HDRINST usr/include/linux/fsmap.h
HDRINST usr/include/linux/smiapp.h
HDRINST usr/include/linux/switchtec_ioctl.h
HDRINST usr/include/linux/atmdev.h
HDRINST usr/include/linux/hpet.h
HDRINST usr/include/linux/virtio_config.h
LD /kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o
HDRINST usr/include/linux/string.h
HDRINST usr/include/linux/kfd_sysfs.h
HDRINST usr/include/linux/inet_diag.h
HDRINST usr/include/linux/netdev.h
HDRINST usr/include/linux/xattr.h
HDRINST usr/include/linux/iommufd.h
HDRINST usr/include/linux/user_events.h
HDRINST usr/include/linux/errno.h
HDRINST usr/include/linux/icmp.h
HDRINST usr/include/linux/i2o-dev.h
HDRINST usr/include/linux/pg.h
HDRINST usr/include/linux/if_bridge.h
HDRINST usr/include/linux/thermal.h
HDRINST usr/include/linux/uinput.h
HDRINST usr/include/linux/handshake.h
HDRINST usr/include/linux/dqblk_xfs.h
HDRINST usr/include/linux/v4l2-common.h
HDRINST usr/include/linux/nvram.h
HDRINST usr/include/linux/if_vlan.h
HDRINST usr/include/linux/uhid.h
HDRINST usr/include/linux/omap3isp.h
HDRINST usr/include/linux/rose.h
HDRINST usr/include/linux/phantom.h
HDRINST usr/include/linux/ipmi_msgdefs.h
HDRINST usr/include/linux/bcm933xx_hcs.h
HDRINST usr/include/linux/bpf.h
HDRINST usr/include/linux/mempolicy.h
HDRINST usr/include/linux/efs_fs_sb.h
HDRINST usr/include/linux/nexthop.h
HDRINST usr/include/linux/net_dropmon.h
HDRINST usr/include/linux/surface_aggregator/cdev.h
HDRINST usr/include/linux/surface_aggregator/dtx.h
AR /kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a
HDRINST usr/include/linux/net.h
HDRINST usr/include/linux/mii.h
HDRINST usr/include/linux/virtio_pcidev.h
HDRINST usr/include/linux/termios.h
HDRINST usr/include/linux/cgroupstats.h
HDRINST usr/include/linux/mpls.h
HDRINST usr/include/linux/iommu.h
HDRINST usr/include/linux/toshiba.h
HDRINST usr/include/linux/virtio_scsi.h
HDRINST usr/include/linux/zorro.h
HDRINST usr/include/linux/chio.h
HDRINST usr/include/linux/pkt_sched.h
HDRINST usr/include/linux/cramfs_fs.h
HDRINST usr/include/linux/nfs3.h
HDRINST usr/include/linux/vfio_ccw.h
HDRINST usr/include/linux/atm_nicstar.h
HDRINST usr/include/linux/ncsi.h
HDRINST usr/include/linux/virtio_net.h
HDRINST usr/include/linux/ioctl.h
HDRINST usr/include/linux/stddef.h
HDRINST usr/include/linux/limits.h
HDRINST usr/include/linux/ipmi_bmc.h
HDRINST usr/include/linux/netfilter_arp.h
HDRINST usr/include/linux/if_addr.h
HDRINST usr/include/linux/rpmsg.h
HDRINST usr/include/linux/media-bus-format.h
HDRINST usr/include/linux/kernelcapi.h
HDRINST usr/include/linux/ppp_defs.h
HDRINST usr/include/linux/ethtool.h
HDRINST usr/include/linux/aspeed-video.h
HDRINST usr/include/linux/hdlc.h
HDRINST usr/include/linux/fscrypt.h
HDRINST usr/include/linux/batadv_packet.h
HDRINST usr/include/linux/uuid.h
HDRINST usr/include/linux/capi.h
HDRINST usr/include/linux/mptcp.h
HDRINST usr/include/linux/hidraw.h
HDRINST usr/include/linux/virtio_console.h
HDRINST usr/include/linux/irqnr.h
HDRINST usr/include/linux/coresight-stm.h
HDRINST usr/include/linux/cxl_mem.h
HDRINST usr/include/linux/iso_fs.h
HDRINST usr/include/linux/virtio_blk.h
HDRINST usr/include/linux/udf_fs_i.h
HDRINST usr/include/linux/coff.h
HDRINST usr/include/linux/dma-buf.h
HDRINST usr/include/linux/ife.h
HDRINST usr/include/linux/agpgart.h
HDRINST usr/include/linux/socket.h
HDRINST usr/include/linux/nilfs2_ondisk.h
HDRINST usr/include/linux/connector.h
HDRINST usr/include/linux/auto_fs4.h
HDRINST usr/include/linux/bt-bmc.h
HDRINST usr/include/linux/map_to_7segment.h
HDRINST usr/include/linux/tc_act/tc_skbedit.h
HDRINST usr/include/linux/tc_act/tc_ctinfo.h
HDRINST usr/include/linux/tc_act/tc_defact.h
HDRINST usr/include/linux/tc_act/tc_gact.h
HDRINST usr/include/linux/tc_act/tc_vlan.h
HDRINST usr/include/linux/tc_act/tc_skbmod.h
HDRINST usr/include/linux/tc_act/tc_sample.h
HDRINST usr/include/linux/tc_act/tc_tunnel_key.h
HDRINST usr/include/linux/tc_act/tc_gate.h
HDRINST usr/include/linux/tc_act/tc_mirred.h
HDRINST usr/include/linux/tc_act/tc_nat.h
CC /kernel/build64-default/tools/objtool/weak.o
HDRINST usr/include/linux/tc_act/tc_csum.h
HDRINST usr/include/linux/tc_act/tc_connmark.h
CC /kernel/build64-default/tools/objtool/check.o
HDRINST usr/include/linux/tc_act/tc_ife.h
HDRINST usr/include/linux/tc_act/tc_mpls.h
CC /kernel/build64-default/tools/objtool/special.o
HDRINST usr/include/linux/tc_act/tc_ct.h
HDRINST usr/include/linux/tc_act/tc_pedit.h
CC /kernel/build64-default/tools/objtool/builtin-check.o
HDRINST usr/include/linux/tc_act/tc_bpf.h
MKDIR /kernel/build64-default/tools/objtool/arch/x86/
HDRINST usr/include/linux/tc_act/tc_ipt.h
CC /kernel/build64-default/tools/objtool/elf.o
HDRINST usr/include/linux/netrom.h
HDRINST usr/include/linux/joystick.h
CC /kernel/build64-default/tools/objtool/objtool.o
MKDIR /kernel/build64-default/tools/objtool/arch/x86/lib/
CC /kernel/build64-default/tools/objtool/orc_gen.o
HDRINST usr/include/linux/falloc.h
CC /kernel/build64-default/tools/objtool/orc_dump.o
CC /kernel/build64-default/tools/objtool/arch/x86/special.o
HDRINST usr/include/linux/cycx_cfm.h
CC /kernel/build64-default/tools/objtool/libstring.o
CC /kernel/build64-default/tools/objtool/libctype.o
HDRINST usr/include/linux/omapfb.h
GEN /kernel/build64-default/tools/objtool/arch/x86/lib/inat-tables.c
CC /kernel/build64-default/tools/objtool/str_error_r.o
HDRINST usr/include/linux/msdos_fs.h
CC /kernel/build64-default/tools/objtool/librbtree.o
HDRINST usr/include/linux/virtio_types.h
HDRINST usr/include/linux/mroute.h
HDRINST usr/include/linux/psample.h
HDRINST usr/include/linux/ipv6.h
HDRINST usr/include/linux/dw100.h
HDRINST usr/include/linux/psp-sev.h
HDRINST usr/include/linux/vfio.h
HDRINST usr/include/linux/if_ppp.h
HDRINST usr/include/linux/byteorder/big_endian.h
HDRINST usr/include/linux/byteorder/little_endian.h
HDRINST usr/include/linux/comedi.h
HDRINST usr/include/linux/scif_ioctl.h
HDRINST usr/include/linux/timerfd.h
HDRINST usr/include/linux/time_types.h
HDRINST usr/include/linux/firewire-constants.h
HDRINST usr/include/linux/virtio_snd.h
HDRINST usr/include/linux/ppp-ioctl.h
HDRINST usr/include/linux/fib_rules.h
HDRINST usr/include/linux/gen_stats.h
HDRINST usr/include/linux/virtio_iommu.h
HDRINST usr/include/linux/genetlink.h
HDRINST usr/include/linux/uvcvideo.h
HDRINST usr/include/linux/pfkeyv2.h
HDRINST usr/include/linux/soundcard.h
HDRINST usr/include/linux/times.h
HDRINST usr/include/linux/nfc.h
HDRINST usr/include/linux/affs_hardblocks.h
HDRINST usr/include/linux/nilfs2_api.h
HDRINST usr/include/linux/rseq.h
HDRINST usr/include/linux/caif/caif_socket.h
HDRINST usr/include/linux/caif/if_caif.h
HDRINST usr/include/linux/i2c-dev.h
HDRINST usr/include/linux/cuda.h
HDRINST usr/include/linux/mei_uuid.h
HDRINST usr/include/linux/cn_proc.h
HDRINST usr/include/linux/parport.h
HDRINST usr/include/linux/v4l2-controls.h
HDRINST usr/include/linux/hsi/cs-protocol.h
HDRINST usr/include/linux/hsi/hsi_char.h
HDRINST usr/include/linux/seg6_genl.h
HDRINST usr/include/linux/am437x-vpfe.h
HDRINST usr/include/linux/amt.h
HDRINST usr/include/linux/netconf.h
HDRINST usr/include/linux/erspan.h
HDRINST usr/include/linux/nsfs.h
HDRINST usr/include/linux/xilinx-v4l2-controls.h
HDRINST usr/include/linux/aspeed-p2a-ctrl.h
HDRINST usr/include/linux/vfio_zdev.h
HDRINST usr/include/linux/serio.h
HDRINST usr/include/linux/acrn.h
HDRINST usr/include/linux/nfs2.h
HDRINST usr/include/linux/virtio_pci.h
HDRINST usr/include/linux/ipc.h
HDRINST usr/include/linux/ethtool_netlink.h
HDRINST usr/include/linux/kd.h
HDRINST usr/include/linux/elf.h
HDRINST usr/include/linux/videodev2.h
HDRINST usr/include/linux/if_alg.h
HDRINST usr/include/linux/sonypi.h
HDRINST usr/include/linux/fsverity.h
HDRINST usr/include/linux/if.h
HDRINST usr/include/linux/btrfs.h
HDRINST usr/include/linux/vm_sockets_diag.h
CC /kernel/build64-default/tools/objtool/arch/x86/decode.o
HDRINST usr/include/linux/netfilter_bridge.h
HDRINST usr/include/linux/packet_diag.h
HDRINST usr/include/linux/netfilter_ipv4.h
HDRINST usr/include/linux/kvm.h
HDRINST usr/include/linux/pci.h
HDRINST usr/include/linux/if_addrlabel.h
HDRINST usr/include/linux/hdlcdrv.h
HDRINST usr/include/linux/cfm_bridge.h
HDRINST usr/include/linux/fiemap.h
HDRINST usr/include/linux/dm-ioctl.h
HDRINST usr/include/linux/aspeed-lpc-ctrl.h
HDRINST usr/include/linux/atmioc.h
HDRINST usr/include/linux/dlm.h
HDRINST usr/include/linux/pci_regs.h
HDRINST usr/include/linux/cachefiles.h
HDRINST usr/include/linux/membarrier.h
HDRINST usr/include/linux/nfs_idmap.h
HDRINST usr/include/linux/ip.h
HDRINST usr/include/linux/atm_he.h
HDRINST usr/include/linux/nfsd/export.h
HDRINST usr/include/linux/nfsd/stats.h
HDRINST usr/include/linux/nfsd/debug.h
HDRINST usr/include/linux/nfsd/cld.h
HDRINST usr/include/linux/ip_vs.h
HDRINST usr/include/linux/vmcore.h
HDRINST usr/include/linux/vbox_vmmdev_types.h
HDRINST usr/include/linux/dvb/osd.h
HDRINST usr/include/linux/dvb/dmx.h
HDRINST usr/include/linux/dvb/net.h
HDRINST usr/include/linux/dvb/frontend.h
HDRINST usr/include/linux/dvb/ca.h
HDRINST usr/include/linux/dvb/version.h
HDRINST usr/include/linux/dvb/video.h
HDRINST usr/include/linux/dvb/audio.h
HDRINST usr/include/linux/nfs.h
HDRINST usr/include/linux/if_link.h
HDRINST usr/include/linux/wait.h
HDRINST usr/include/linux/icmpv6.h
HDRINST usr/include/linux/media.h
HDRINST usr/include/linux/seg6_local.h
HDRINST usr/include/linux/tps6594_pfsm.h
HDRINST usr/include/linux/openvswitch.h
HDRINST usr/include/linux/atmsap.h
HDRINST usr/include/linux/bpfilter.h
HDRINST usr/include/linux/fpga-dfl.h
HDRINST usr/include/linux/userio.h
HDRINST usr/include/linux/signal.h
HDRINST usr/include/linux/map_to_14segment.h
HDRINST usr/include/linux/hdreg.h
HDRINST usr/include/linux/utime.h
HDRINST usr/include/linux/usbdevice_fs.h
HDRINST usr/include/linux/timex.h
HDRINST usr/include/linux/if_fc.h
HDRINST usr/include/linux/reiserfs_xattr.h
HDRINST usr/include/linux/hw_breakpoint.h
HDRINST usr/include/linux/quota.h
HDRINST usr/include/linux/ioprio.h
HDRINST usr/include/linux/eventpoll.h
HDRINST usr/include/linux/atmclip.h
HDRINST usr/include/linux/can.h
HDRINST usr/include/linux/if_team.h
HDRINST usr/include/linux/usbip.h
HDRINST usr/include/linux/stat.h
HDRINST usr/include/linux/fou.h
HDRINST usr/include/linux/hash_info.h
HDRINST usr/include/linux/ppp-comp.h
HDRINST usr/include/linux/ip6_tunnel.h
HDRINST usr/include/linux/tipc_netlink.h
HDRINST usr/include/linux/in.h
HDRINST usr/include/linux/wireguard.h
HDRINST usr/include/linux/btf.h
HDRINST usr/include/linux/batman_adv.h
HDRINST usr/include/linux/fcntl.h
HDRINST usr/include/linux/if_ltalk.h
HDRINST usr/include/linux/i2c.h
HDRINST usr/include/linux/atm_idt77105.h
HDRINST usr/include/linux/kexec.h
HDRINST usr/include/linux/arm_sdei.h
HDRINST usr/include/linux/netfilter_ipv6/ip6_tables.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_ah.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_NPT.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_rt.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_REJECT.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_opts.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_srh.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_LOG.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_mh.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_HL.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_hl.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_frag.h
HDRINST usr/include/linux/netfilter_ipv6/ip6t_ipv6header.h
HDRINST usr/include/linux/minix_fs.h
HDRINST usr/include/linux/aio_abi.h
HDRINST usr/include/linux/pktcdvd.h
HDRINST usr/include/linux/libc-compat.h
HDRINST usr/include/linux/atmlec.h
HDRINST usr/include/linux/signalfd.h
HDRINST usr/include/linux/bpf_common.h
HDRINST usr/include/linux/seg6_iptunnel.h
HDRINST usr/include/linux/synclink.h
HDRINST usr/include/linux/mpls_iptunnel.h
HDRINST usr/include/linux/mctp.h
HDRINST usr/include/linux/if_xdp.h
HDRINST usr/include/linux/llc.h
HDRINST usr/include/linux/atmsvc.h
HDRINST usr/include/linux/sed-opal.h
HDRINST usr/include/linux/sock_diag.h
HDRINST usr/include/linux/time.h
HDRINST usr/include/linux/securebits.h
HDRINST usr/include/linux/fsl_hypervisor.h
HDRINST usr/include/linux/if_hippi.h
HDRINST usr/include/linux/seccomp.h
HDRINST usr/include/linux/oom.h
HDRINST usr/include/linux/filter.h
HDRINST usr/include/linux/inotify.h
HDRINST usr/include/linux/rfkill.h
HDRINST usr/include/linux/reboot.h
HDRINST usr/include/linux/can/vxcan.h
HDRINST usr/include/linux/can/j1939.h
HDRINST usr/include/linux/can/netlink.h
HDRINST usr/include/linux/can/bcm.h
HDRINST usr/include/linux/can/raw.h
HDRINST usr/include/linux/can/gw.h
HDRINST usr/include/linux/can/error.h
HDRINST usr/include/linux/can/isotp.h
HDRINST usr/include/linux/if_eql.h
HDRINST usr/include/linux/hiddev.h
HDRINST usr/include/linux/blktrace_api.h
HDRINST usr/include/linux/ccs.h
HDRINST usr/include/linux/ioam6.h
HDRINST usr/include/linux/hsr_netlink.h
HDRINST usr/include/linux/mmc/ioctl.h
HDRINST usr/include/linux/bfs_fs.h
HDRINST usr/include/linux/rio_cm_cdev.h
HDRINST usr/include/linux/uleds.h
HDRINST usr/include/linux/mrp_bridge.h
HDRINST usr/include/linux/adb.h
HDRINST usr/include/linux/pmu.h
HDRINST usr/include/linux/udmabuf.h
HDRINST usr/include/linux/kcmp.h
HDRINST usr/include/linux/dma-heap.h
HDRINST usr/include/linux/userfaultfd.h
HDRINST usr/include/linux/netfilter_arp/arpt_mangle.h
HDRINST usr/include/linux/netfilter_arp/arp_tables.h
HDRINST usr/include/linux/tipc.h
HDRINST usr/include/linux/virtio_ids.h
HDRINST usr/include/linux/l2tp.h
HDRINST usr/include/linux/devlink.h
HDRINST usr/include/linux/virtio_gpio.h
HDRINST usr/include/linux/dcbnl.h
HDRINST usr/include/linux/cyclades.h
HDRINST usr/include/sound/intel/avs/tokens.h
HDRINST usr/include/sound/sof/fw.h
HDRINST usr/include/sound/sof/abi.h
HDRINST usr/include/sound/sof/tokens.h
HDRINST usr/include/sound/sof/header.h
HDRINST usr/include/sound/usb_stream.h
HDRINST usr/include/sound/sfnt_info.h
HDRINST usr/include/sound/asequencer.h
HDRINST usr/include/sound/tlv.h
HDRINST usr/include/sound/asound.h
HDRINST usr/include/sound/asoc.h
HDRINST usr/include/sound/sb16_csp.h
HDRINST usr/include/sound/compress_offload.h
HDRINST usr/include/sound/hdsp.h
HDRINST usr/include/sound/emu10k1.h
HDRINST usr/include/sound/snd_ar_tokens.h
HDRINST usr/include/sound/snd_sst_tokens.h
HDRINST usr/include/sound/asound_fm.h
HDRINST usr/include/sound/hdspm.h
HDRINST usr/include/sound/compress_params.h
HDRINST usr/include/sound/firewire.h
HDRINST usr/include/sound/skl-tplg-interface.h
HDRINST usr/include/scsi/scsi_bsg_ufs.h
HDRINST usr/include/scsi/scsi_netlink_fc.h
HDRINST usr/include/scsi/scsi_bsg_mpi3mr.h
HDRINST usr/include/scsi/fc/fc_ns.h
HDRINST usr/include/scsi/fc/fc_fs.h
HDRINST usr/include/scsi/fc/fc_els.h
HDRINST usr/include/scsi/fc/fc_gs.h
HDRINST usr/include/scsi/scsi_bsg_fc.h
HDRINST usr/include/scsi/cxlflash_ioctl.h
HDRINST usr/include/scsi/scsi_netlink.h
HDRINST usr/include/linux/version.h
HDRINST usr/include/asm/processor-flags.h
HDRINST usr/include/asm/auxvec.h
HDRINST usr/include/asm/svm.h
HDRINST usr/include/asm/bitsperlong.h
HDRINST usr/include/asm/kvm_perf.h
HDRINST usr/include/asm/mce.h
HDRINST usr/include/asm/posix_types.h
HDRINST usr/include/asm/msr.h
HDRINST usr/include/asm/sigcontext32.h
HDRINST usr/include/asm/mman.h
HDRINST usr/include/asm/shmbuf.h
HDRINST usr/include/asm/e820.h
HDRINST usr/include/asm/posix_types_64.h
HDRINST usr/include/asm/vsyscall.h
HDRINST usr/include/asm/msgbuf.h
HDRINST usr/include/asm/swab.h
HDRINST usr/include/asm/statfs.h
HDRINST usr/include/asm/posix_types_x32.h
HDRINST usr/include/asm/ptrace.h
HDRINST usr/include/asm/ist.h
HDRINST usr/include/asm/unistd.h
HDRINST usr/include/asm/prctl.h
HDRINST usr/include/asm/boot.h
HDRINST usr/include/asm/sigcontext.h
HDRINST usr/include/asm/posix_types_32.h
HDRINST usr/include/asm/kvm_para.h
HDRINST usr/include/asm/mtrr.h
HDRINST usr/include/asm/a.out.h
HDRINST usr/include/asm/amd_hsmp.h
HDRINST usr/include/asm/hwcap2.h
HDRINST usr/include/asm/vm86.h
HDRINST usr/include/asm/ptrace-abi.h
HDRINST usr/include/asm/vmx.h
HDRINST usr/include/asm/ldt.h
HDRINST usr/include/asm/perf_regs.h
HDRINST usr/include/asm/kvm.h
HDRINST usr/include/asm/debugreg.h
HDRINST usr/include/asm/signal.h
HDRINST usr/include/asm/bootparam.h
HDRINST usr/include/asm/siginfo.h
HDRINST usr/include/asm/hw_breakpoint.h
HDRINST usr/include/asm/stat.h
HDRINST usr/include/asm/setup.h
HDRINST usr/include/asm/sembuf.h
HDRINST usr/include/asm/sgx.h
HDRINST usr/include/asm/ucontext.h
HDRINST usr/include/asm/byteorder.h
HDRINST usr/include/asm/unistd_64.h
HDRINST usr/include/asm/ioctls.h
HDRINST usr/include/asm/bpf_perf_event.h
HDRINST usr/include/asm/types.h
HDRINST usr/include/asm/poll.h
HDRINST usr/include/asm/resource.h
HDRINST usr/include/asm/param.h
HDRINST usr/include/asm/sockios.h
HDRINST usr/include/asm/errno.h
HDRINST usr/include/asm/unistd_x32.h
HDRINST usr/include/asm/termios.h
HDRINST usr/include/asm/ioctl.h
HDRINST usr/include/asm/socket.h
HDRINST usr/include/asm/unistd_32.h
HDRINST usr/include/asm/termbits.h
HDRINST usr/include/asm/fcntl.h
HDRINST usr/include/asm/ipcbuf.h
HOSTLD scripts/mod/modpost
CC kernel/bounds.s
CHKSHA1 ../include/linux/atomic/atomic-arch-fallback.h
CHKSHA1 ../include/linux/atomic/atomic-instrumented.h
CHKSHA1 ../include/linux/atomic/atomic-long.h
UPD include/generated/timeconst.h
UPD include/generated/bounds.h
CC arch/x86/kernel/asm-offsets.s
LD /kernel/build64-default/tools/objtool/arch/x86/objtool-in.o
UPD include/generated/asm-offsets.h
CALL ../scripts/checksyscalls.sh
LD /kernel/build64-default/tools/objtool/objtool-in.o
LINK /kernel/build64-default/tools/objtool/objtool
LDS scripts/module.lds
CC ipc/compat.o
CC ipc/util.o
CC ipc/msgutil.o
CC ipc/msg.o
CC ipc/sem.o
HOSTCC usr/gen_init_cpio
CC ipc/shm.o
AR certs/built-in.a
CC init/main.o
CC ipc/syscall.o
CC ipc/ipc_sysctl.o
AS arch/x86/lib/clear_page_64.o
CC init/do_mounts.o
CC arch/x86/lib/cmdline.o
CC init/do_mounts_initrd.o
CC ipc/mqueue.o
UPD init/utsversion-tmp.h
CC ipc/namespace.o
CC block/bdev.o
CC init/initramfs.o
AS arch/x86/lib/cmpxchg16b_emu.o
CC security/commoncap.o
CC block/fops.o
CC ipc/mq_sysctl.o
CC arch/x86/power/cpu.o
AR arch/x86/video/built-in.a
CC io_uring/io_uring.o
CC block/bio.o
CC arch/x86/pci/i386.o
CC arch/x86/realmode/init.o
CC block/partitions/core.o
AR arch/x86/ia32/built-in.a
AR virt/lib/built-in.a
AS arch/x86/crypto/aesni-intel_asm.o
CC [M] arch/x86/video/fbdev.o
CC net/core/sock.o
CC security/keys/gc.o
CC net/llc/llc_core.o
AR drivers/irqchip/built-in.a
CC net/core/request_sock.o
AR sound/i2c/other/built-in.a
CC arch/x86/kernel/fpu/init.o
AR arch/x86/platform/atom/built-in.a
CC arch/x86/events/amd/core.o
CC arch/x86/mm/pat/set_memory.o
CC sound/core/seq/seq.o
CC [M] virt/lib/irqbypass.o
CC fs/notify/dnotify/dnotify.o
CC arch/x86/kernel/fpu/bugs.o
AR sound/i2c/built-in.a
CC arch/x86/entry/vdso/vma.o
AR drivers/bus/mhi/built-in.a
AR drivers/phy/allwinner/built-in.a
CC arch/x86/platform/efi/memmap.o
AR arch/x86/platform/ce4100/built-in.a
CC lib/kunit/test.o
AR drivers/bus/built-in.a
CC arch/x86/mm/init.o
AR drivers/phy/amlogic/built-in.a
CC mm/kasan/common.o
CC sound/core/seq/seq_lock.o
CC arch/x86/crypto/aesni-intel_glue.o
CC kernel/sched/core.o
AR drivers/phy/broadcom/built-in.a
CC crypto/api.o
AR drivers/phy/cadence/built-in.a
AR drivers/phy/freescale/built-in.a
AR drivers/phy/hisilicon/built-in.a
CC arch/x86/lib/copy_mc.o
AR drivers/phy/ingenic/built-in.a
AR drivers/phy/intel/built-in.a
AR drivers/phy/lantiq/built-in.a
AR drivers/phy/marvell/built-in.a
AR drivers/phy/mediatek/built-in.a
AR drivers/phy/microchip/built-in.a
AR drivers/phy/motorola/built-in.a
CC kernel/sched/fair.o
AR drivers/phy/mscc/built-in.a
AR drivers/phy/qualcomm/built-in.a
AR drivers/phy/ralink/built-in.a
AR drivers/phy/renesas/built-in.a
AR drivers/phy/rockchip/built-in.a
AR drivers/phy/samsung/built-in.a
AR drivers/phy/socionext/built-in.a
GEN usr/initramfs_data.cpio
COPY usr/initramfs_inc_data
AR drivers/phy/st/built-in.a
AS usr/initramfs_data.o
AR drivers/phy/sunplus/built-in.a
AR usr/built-in.a
AR drivers/phy/tegra/built-in.a
CC net/llc/llc_input.o
AR drivers/phy/ti/built-in.a
AR drivers/phy/xilinx/built-in.a
CC drivers/phy/phy-core.o
CC arch/x86/kernel/fpu/core.o
CC arch/x86/kernel/fpu/regset.o
AS arch/x86/lib/copy_mc_64.o
CC sound/core/seq/seq_clientmgr.o
AS arch/x86/lib/copy_page_64.o
AR virt/built-in.a
CC mm/filemap.o
AS arch/x86/lib/copy_user_64.o
AS arch/x86/lib/copy_user_uncached_64.o
AS arch/x86/crypto/aesni-intel_avx-x86_64.o
CC arch/x86/lib/cpu.o
CC net/llc/llc_output.o
CC arch/x86/lib/delay.o
AS arch/x86/realmode/rm/header.o
CC fs/nfs_common/grace.o
AS arch/x86/realmode/rm/trampoline_64.o
AS arch/x86/realmode/rm/stack.o
CC arch/x86/kernel/fpu/signal.o
CC security/keys/key.o
AS arch/x86/realmode/rm/reboot.o
CC fs/iomap/trace.o
AS arch/x86/realmode/rm/wakeup_asm.o
AR fs/notify/dnotify/built-in.a
AR fs/quota/built-in.a
CC arch/x86/kernel/fpu/xstate.o
CC fs/notify/inotify/inotify_fsnotify.o
CC arch/x86/realmode/rm/wakemain.o
CC arch/x86/pci/init.o
CC lib/kunit/resource.o
CC fs/notify/inotify/inotify_user.o
CC arch/x86/platform/efi/quirks.o
CC arch/x86/realmode/rm/video-mode.o
CC net/core/skbuff.o
CC arch/x86/entry/vdso/extable.o
CC lib/math/div64.o
CC arch/x86/power/hibernate_64.o
CC mm/kasan/report.o
CC security/keys/keyring.o
CC block/partitions/ldm.o
AS arch/x86/realmode/rm/copy.o
CC fs/iomap/iter.o
CC lib/math/gcd.o
AS arch/x86/realmode/rm/bioscall.o
CC mm/kasan/init.o
CC crypto/cipher.o
CC arch/x86/realmode/rm/regs.o
AS arch/x86/lib/getuser.o
GEN arch/x86/lib/inat-tables.c
CC lib/math/lcm.o
CC arch/x86/realmode/rm/video-vga.o
CC mm/kasan/generic.o
CC arch/x86/lib/insn-eval.o
CC init/calibrate.o
CC lib/math/int_pow.o
CC arch/x86/pci/mmconfig_64.o
AS arch/x86/crypto/aes_ctrby8_avx-x86_64.o
CC arch/x86/events/amd/lbr.o
CC lib/math/int_sqrt.o
CC arch/x86/realmode/rm/video-vesa.o
CC kernel/sched/build_policy.o
CC lib/math/reciprocal_div.o
AS [M] arch/x86/crypto/ghash-clmulni-intel_asm.o
CC [M] arch/x86/crypto/ghash-clmulni-intel_glue.o
CC arch/x86/realmode/rm/video-bios.o
CC lib/math/rational.o
AS [M] arch/x86/crypto/crc32-pclmul_asm.o
CC security/min_addr.o
CC arch/x86/mm/init_64.o
CC security/inode.o
CC security/device_cgroup.o
CC [M] arch/x86/crypto/crc32-pclmul_glue.o
CC kernel/sched/build_utility.o
PASYMS arch/x86/realmode/rm/pasyms.h
LDS arch/x86/realmode/rm/realmode.lds
LD arch/x86/realmode/rm/realmode.elf
RELOCS arch/x86/realmode/rm/realmode.relocs
OBJCOPY arch/x86/realmode/rm/realmode.bin
AS arch/x86/realmode/rmpiggy.o
CC lib/kunit/static_stub.o
AR arch/x86/realmode/built-in.a
CC mm/kasan/report_generic.o
AR net/llc/built-in.a
CC fs/iomap/buffered-io.o
AR fs/nfs_common/built-in.a
CC arch/x86/pci/direct.o
CC net/core/datagram.o
AR drivers/phy/built-in.a
AR drivers/pinctrl/actions/built-in.a
AR drivers/pinctrl/bcm/built-in.a
CC net/core/stream.o
AR drivers/pinctrl/cirrus/built-in.a
AR drivers/pinctrl/freescale/built-in.a
CC drivers/pinctrl/intel/pinctrl-baytrail.o
CC drivers/pinctrl/intel/pinctrl-intel.o
CC init/init_task.o
CC arch/x86/entry/vdso/vdso32-setup.o
CC arch/x86/pci/mmconfig-shared.o
CC crypto/compress.o
CC [M] lib/math/prime_numbers.o
AS arch/x86/power/hibernate_asm_64.o
CC arch/x86/power/hibernate.o
CC fs/iomap/direct-io.o
CC arch/x86/mm/pat/memtype.o
AR drivers/pinctrl/mediatek/built-in.a
CC arch/x86/platform/efi/efi.o
AR drivers/pinctrl/mvebu/built-in.a
CC net/ethernet/eth.o
CC mm/kasan/shadow.o
LDS arch/x86/entry/vdso/vdso.lds
AS [M] arch/x86/crypto/crct10dif-pcl-asm_64.o
CC arch/x86/mm/pat/memtype_interval.o
AR lib/math/built-in.a
CC arch/x86/platform/efi/efi_64.o
CC [M] arch/x86/crypto/crct10dif-pclmul_glue.o
AR arch/x86/net/built-in.a
AS arch/x86/entry/vdso/vdso-note.o
CC [M] arch/x86/kvm/../../../virt/kvm/kvm_main.o
CC arch/x86/entry/vdso/vclock_gettime.o
AS arch/x86/platform/efi/efi_stub_64.o
AR fs/notify/inotify/built-in.a
CC fs/proc/task_mmu.o
CC fs/notify/fanotify/fanotify.o
CC arch/x86/entry/vdso/vgetcpu.o
CC fs/kernfs/mount.o
CC fs/kernfs/inode.o
CC fs/sysfs/file.o
CC lib/kunit/string-stream.o
HOSTCC arch/x86/entry/vdso/vdso2c
CC arch/x86/events/amd/ibs.o
CC fs/kernfs/dir.o
CC lib/kunit/assert.o
CC sound/core/seq/seq_memory.o
CC arch/x86/lib/insn.o
AR arch/x86/kernel/fpu/built-in.a
CC arch/x86/kernel/cpu/mce/core.o
CC arch/x86/kernel/cpu/mtrr/mtrr.o
CC block/partitions/msdos.o
CC sound/core/seq/seq_queue.o
CC crypto/algapi.o
AR ipc/built-in.a
CC fs/sysfs/dir.o
CC fs/iomap/fiemap.o
CC security/keys/keyctl.o
CC init/version.o
AS arch/x86/lib/memcpy_64.o
LD [M] arch/x86/crypto/ghash-clmulni-intel.o
LD [M] arch/x86/crypto/crc32-pclmul.o
CC arch/x86/mm/fault.o
LD [M] arch/x86/crypto/crct10dif-pclmul.o
AR arch/x86/crypto/built-in.a
CC crypto/scatterwalk.o
LDS arch/x86/entry/vdso/vdso32/vdso32.lds
CC fs/configfs/inode.o
CC mm/kasan/quarantine.o
AS arch/x86/lib/memmove_64.o
AS arch/x86/entry/vdso/vdso32/note.o
AR arch/x86/power/built-in.a
CC fs/configfs/file.o
AS arch/x86/entry/vdso/vdso32/system_call.o
AS arch/x86/lib/memset_64.o
AS arch/x86/entry/vdso/vdso32/sigreturn.o
CC arch/x86/lib/misc.o
CC fs/configfs/dir.o
CC arch/x86/entry/vdso/vdso32/vclock_gettime.o
CC arch/x86/lib/pc-conf-reg.o
AR init/built-in.a
CC lib/kunit/try-catch.o
CC arch/x86/kernel/cpu/mce/severity.o
CC arch/x86/pci/fixup.o
CC fs/devpts/inode.o
AR sound/drivers/opl3/built-in.a
AR sound/drivers/opl4/built-in.a
CC fs/ext4/balloc.o
AR sound/drivers/mpu401/built-in.a
CC fs/ext4/bitmap.o
AR sound/drivers/vx/built-in.a
CC net/core/scm.o
AR sound/drivers/pcsp/built-in.a
CC arch/x86/kernel/cpu/mce/genpool.o
AR sound/drivers/built-in.a
CC fs/ext4/block_validity.o
AR arch/x86/mm/pat/built-in.a
AS arch/x86/lib/putuser.o
CC arch/x86/entry/vsyscall/vsyscall_64.o
AS arch/x86/lib/retpoline.o
AR sound/isa/ad1816a/built-in.a
AR sound/isa/ad1848/built-in.a
AR sound/isa/cs423x/built-in.a
AR sound/isa/es1688/built-in.a
CC arch/x86/lib/usercopy.o
AR sound/isa/galaxy/built-in.a
AS arch/x86/entry/vsyscall/vsyscall_emu_64.o
AR sound/isa/gus/built-in.a
CC fs/sysfs/symlink.o
AS arch/x86/entry/entry.o
AR sound/isa/msnd/built-in.a
AR sound/isa/opti9xx/built-in.a
AS arch/x86/entry/entry_64.o
AR arch/x86/platform/efi/built-in.a
CC fs/iomap/seek.o
AR sound/isa/sb/built-in.a
AR arch/x86/platform/geode/built-in.a
AR sound/isa/wavefront/built-in.a
AR arch/x86/platform/iris/built-in.a
AR sound/isa/wss/built-in.a
CC net/core/gen_stats.o
AR sound/isa/built-in.a
CC arch/x86/platform/intel/iosf_mbi.o
CC fs/iomap/swapfile.o
CC fs/ext4/dir.o
CC [M] drivers/pinctrl/intel/pinctrl-cherryview.o
CC arch/x86/entry/syscall_64.o
CC fs/ext4/ext4_jbd2.o
CC arch/x86/kernel/cpu/mtrr/if.o
CC fs/notify/fanotify/fanotify_user.o
CC lib/kunit/executor.o
CC arch/x86/lib/usercopy_64.o
CC sound/core/seq/seq_fifo.o
CC block/partitions/efi.o
AR net/ethernet/built-in.a
CC arch/x86/events/amd/uncore.o
CC net/802/p8022.o
CC net/sched/sch_generic.o
CC arch/x86/lib/msr-smp.o
CC net/netlink/af_netlink.o
CC arch/x86/entry/vdso/vdso32/vgetcpu.o
AR mm/kasan/built-in.a
CC arch/x86/pci/acpi.o
CC fs/kernfs/file.o
CC net/sched/sch_mq.o
VDSO arch/x86/entry/vdso/vdso64.so.dbg
CC net/sched/sch_frag.o
VDSO arch/x86/entry/vdso/vdso32.so.dbg
OBJCOPY arch/x86/entry/vdso/vdso64.so
OBJCOPY arch/x86/entry/vdso/vdso32.so
VDSO2C arch/x86/entry/vdso/vdso-image-64.c
VDSO2C arch/x86/entry/vdso/vdso-image-32.c
CC arch/x86/entry/vdso/vdso-image-64.o
CC fs/sysfs/mount.o
AR sound/pci/ac97/built-in.a
AR sound/pci/ali5451/built-in.a
AR sound/pci/asihpi/built-in.a
AR fs/devpts/built-in.a
CC arch/x86/entry/vdso/vdso-image-32.o
AR sound/pci/au88x0/built-in.a
CC fs/jbd2/transaction.o
AR sound/pci/aw2/built-in.a
CC crypto/proc.o
AR sound/pci/ctxfi/built-in.a
CC fs/jbd2/commit.o
AR sound/pci/ca0106/built-in.a
AR sound/pci/cs46xx/built-in.a
CC fs/jbd2/recovery.o
CC security/keys/permission.o
CC fs/jbd2/checkpoint.o
AR sound/pci/cs5535audio/built-in.a
CC lib/kunit/hooks.o
AR sound/pci/lola/built-in.a
AR arch/x86/entry/vsyscall/built-in.a
AR sound/pci/lx6464es/built-in.a
CC fs/jbd2/revoke.o
CC fs/jbd2/journal.o
CC arch/x86/entry/common.o
AR sound/pci/echoaudio/built-in.a
CC mm/mempool.o
AR sound/pci/emu10k1/built-in.a
AR sound/pci/hda/built-in.a
AR fs/iomap/built-in.a
CC arch/x86/kernel/cpu/mtrr/generic.o
CC mm/oom_kill.o
CC [M] sound/pci/hda/hda_bind.o
CC arch/x86/lib/cache-smp.o
CC sound/core/seq/seq_prioq.o
AR arch/x86/platform/intel/built-in.a
CC arch/x86/mm/ioremap.o
AR arch/x86/entry/vdso/built-in.a
AR arch/x86/platform/intel-mid/built-in.a
CC [M] sound/pci/hda/hda_codec.o
AR arch/x86/platform/intel-quark/built-in.a
CC fs/configfs/symlink.o
AR arch/x86/platform/olpc/built-in.a
CC [M] arch/x86/kvm/../../../virt/kvm/eventfd.o
AR arch/x86/platform/scx200/built-in.a
AR arch/x86/platform/ts5500/built-in.a
AR arch/x86/platform/uv/built-in.a
AR arch/x86/platform/built-in.a
CC arch/x86/lib/msr.o
AR lib/kunit/built-in.a
CC fs/kernfs/symlink.o
CC lib/crypto/memneq.o
CC fs/proc/inode.o
CC arch/x86/kernel/cpu/mce/intel.o
CC lib/crypto/utils.o
CC net/802/psnap.o
CC [M] sound/pci/hda/hda_jack.o
AR block/partitions/built-in.a
CC lib/zlib_inflate/inffast.o
CC block/elevator.o
CC arch/x86/pci/legacy.o
AR arch/x86/events/amd/built-in.a
CC arch/x86/events/intel/core.o
CC crypto/aead.o
CC security/keys/process_keys.o
CC fs/sysfs/group.o
CC [M] drivers/pinctrl/intel/pinctrl-broxton.o
CC lib/zlib_inflate/inflate.o
CC arch/x86/events/intel/bts.o
CC arch/x86/pci/irq.o
CC arch/x86/kernel/cpu/mce/threshold.o
CC block/blk-core.o
AS arch/x86/entry/thunk_64.o
CC lib/crypto/chacha.o
CC sound/core/seq/seq_timer.o
AS arch/x86/entry/entry_64_compat.o
CC security/keys/request_key.o
CC [M] arch/x86/kvm/../../../virt/kvm/binary_stats.o
CC arch/x86/entry/syscall_32.o
CC fs/ext4/extents.o
CC fs/configfs/mount.o
AR fs/kernfs/built-in.a
CC lib/zlib_deflate/deflate.o
CC lib/crypto/aes.o
AR fs/notify/fanotify/built-in.a
CC fs/notify/fsnotify.o
CC lib/zlib_deflate/deftree.o
AS arch/x86/lib/msr-reg.o
CC lib/crypto/gf128mul.o
CC arch/x86/lib/msr-reg-export.o
CC lib/zlib_deflate/deflate_syms.o
CC fs/notify/notification.o
CC lib/lzo/lzo1x_compress.o
CC arch/x86/mm/extable.o
CC lib/lzo/lzo1x_decompress_safe.o
CC kernel/locking/mutex.o
CC arch/x86/kernel/cpu/mtrr/cleanup.o
CC [M] drivers/pinctrl/intel/pinctrl-geminilake.o
CC net/802/stp.o
CC fs/proc/root.o
AS arch/x86/lib/hweight.o
CC arch/x86/lib/iomem.o
AR fs/sysfs/built-in.a
CC kernel/locking/semaphore.o
CC crypto/geniv.o
CC lib/zlib_inflate/infutil.o
CC kernel/power/qos.o
CC kernel/printk/printk.o
CC fs/configfs/item.o
AR arch/x86/entry/built-in.a
CC kernel/printk/printk_safe.o
CC [M] arch/x86/kvm/../../../virt/kvm/vfio.o
CC io_uring/xattr.o
CC kernel/power/main.o
CC sound/core/seq/seq_system.o
CC crypto/skcipher.o
AR lib/lzo/built-in.a
CC crypto/seqiv.o
CC security/keys/request_key_auth.o
CC sound/core/seq/seq_ports.o
CC lib/lz4/lz4_compress.o
CC arch/x86/kernel/cpu/mce/apei.o
CC arch/x86/events/intel/ds.o
CC lib/lz4/lz4hc_compress.o
CC lib/crypto/blake2s.o
CC arch/x86/events/zhaoxin/core.o
CC arch/x86/events/core.o
CC [M] drivers/pinctrl/intel/pinctrl-sunrisepoint.o
CC lib/crypto/blake2s-generic.o
AS arch/x86/lib/iomap_copy_64.o
CC arch/x86/lib/inat.o
CC lib/crypto/blake2s-selftest.o
CC lib/zlib_inflate/inftrees.o
CC net/sched/sch_api.o
CC fs/notify/group.o
AR arch/x86/lib/built-in.a
AR arch/x86/lib/lib.a
CC fs/notify/mark.o
AR lib/zlib_deflate/built-in.a
CC arch/x86/mm/mmap.o
CC lib/zlib_inflate/inflate_syms.o
CC lib/zstd/zstd_compress_module.o
CC arch/x86/pci/common.o
CC fs/proc/base.o
CC lib/zstd/compress/fse_compress.o
AR fs/configfs/built-in.a
CC lib/crypto/des.o
CC lib/zstd/compress/hist.o
AR net/802/built-in.a
CC arch/x86/pci/early.o
CC arch/x86/events/probe.o
CC kernel/printk/printk_ringbuffer.o
CC mm/fadvise.o
CC block/blk-sysfs.o
AR arch/x86/kernel/cpu/mtrr/built-in.a
CC fs/ramfs/inode.o
CC sound/core/seq/seq_info.o
CC fs/ramfs/file-mmu.o
AR net/bpf/built-in.a
CC lib/zstd/compress/huf_compress.o
AR drivers/pinctrl/intel/built-in.a
AR drivers/pinctrl/nomadik/built-in.a
CC fs/proc/generic.o
AR lib/zlib_inflate/built-in.a
AR arch/x86/kernel/cpu/mce/built-in.a
CC security/keys/user_defined.o
AR drivers/pinctrl/nuvoton/built-in.a
CC fs/proc/array.o
CC arch/x86/kernel/cpu/cacheinfo.o
AR drivers/pinctrl/nxp/built-in.a
AR drivers/pinctrl/qcom/built-in.a
AR drivers/pinctrl/sprd/built-in.a
AR drivers/pinctrl/sunplus/built-in.a
AR drivers/pinctrl/ti/built-in.a
CC drivers/pinctrl/core.o
CC io_uring/nop.o
CC lib/xz/xz_dec_syms.o
CC lib/zstd/compress/zstd_compress.o
CC arch/x86/events/intel/knc.o
CC lib/xz/xz_dec_stream.o
CC net/netlink/genetlink.o
CC [M] arch/x86/kvm/../../../virt/kvm/coalesced_mmio.o
CC net/core/gen_estimator.o
CC [M] sound/pci/hda/hda_auto_parser.o
AR arch/x86/events/zhaoxin/built-in.a
CC lib/crypto/sha1.o
CC lib/lz4/lz4_decompress.o
CC arch/x86/mm/pgtable.o
CC kernel/power/console.o
CC arch/x86/pci/bus_numa.o
CC crypto/echainiv.o
CC [M] arch/x86/kvm/../../../virt/kvm/async_pf.o
AR sound/core/seq/built-in.a
CC drivers/pinctrl/pinctrl-utils.o
CC sound/core/sound.o
CC fs/notify/fdinfo.o
CC [M] arch/x86/kvm/../../../virt/kvm/irqchip.o
CC net/core/net_namespace.o
CC arch/x86/mm/physaddr.o
CC net/netlink/policy.o
AR fs/jbd2/built-in.a
CC mm/maccess.o
CC fs/hugetlbfs/inode.o
CC mm/page-writeback.o
AR fs/ramfs/built-in.a
CC arch/x86/kernel/cpu/scattered.o
CC security/keys/compat.o
CC [M] arch/x86/kvm/../../../virt/kvm/dirty_ring.o
CC drivers/pinctrl/pinmux.o
CC lib/xz/xz_dec_lzma2.o
CC io_uring/fs.o
CC lib/crypto/sha256.o
CC block/blk-flush.o
CC arch/x86/events/intel/lbr.o
CC fs/fat/cache.o
CC kernel/locking/rwsem.o
CC arch/x86/kernel/cpu/topology.o
CC fs/fat/dir.o
CC drivers/pinctrl/pinconf.o
CC fs/ext4/extents_status.o
CC crypto/ahash.o
CC security/keys/proc.o
CC kernel/power/process.o
CC kernel/printk/sysctl.o
CC arch/x86/pci/amd_bus.o
CC sound/core/init.o
AR fs/notify/built-in.a
CC fs/ext4/file.o
CC fs/fat/fatent.o
CC arch/x86/kernel/cpu/common.o
CC arch/x86/events/intel/p4.o
CC sound/core/memory.o
CC drivers/pinctrl/pinconf-generic.o
CC arch/x86/mm/tlb.o
AR sound/pci/ice1712/built-in.a
CC arch/x86/kernel/acpi/boot.o
CC net/ethtool/ioctl.o
CC arch/x86/kernel/acpi/sleep.o
CC security/keys/sysctl.o
AR kernel/printk/built-in.a
AR sound/pci/korg1212/built-in.a
CC mm/folio-compat.o
AR sound/pci/mixart/built-in.a
AR kernel/sched/built-in.a
CC arch/x86/mm/cpu_entry_area.o
CC net/netlink/diag.o
AR sound/pci/nm256/built-in.a
CC arch/x86/mm/maccess.o
CC fs/nfs/client.o
AR sound/pci/oxygen/built-in.a
CC [M] sound/pci/hda/hda_sysfs.o
CC net/ethtool/common.o
AR lib/lz4/built-in.a
CC fs/exportfs/expfs.o
CC kernel/irq/irqdesc.o
CC lib/zstd/compress/zstd_compress_literals.o
CC lib/raid6/algos.o
CC arch/x86/events/utils.o
CC [M] lib/crypto/arc4.o
CC lib/xz/xz_dec_bcj.o
CC kernel/power/suspend.o
AR sound/pci/pcxhr/built-in.a
CC mm/readahead.o
CC [M] arch/x86/kvm/../../../virt/kvm/pfncache.o
CC net/core/secure_seq.o
CC kernel/rcu/update.o
CC io_uring/splice.o
AR kernel/livepatch/built-in.a
CC fs/ext4/fsmap.o
CC kernel/rcu/sync.o
CC kernel/dma/mapping.o
CC block/blk-settings.o
AR drivers/pinctrl/built-in.a
CC drivers/gpio/gpiolib.o
AR arch/x86/pci/built-in.a
CC kernel/entry/common.o
AR security/keys/built-in.a
AR security/built-in.a
CC net/sched/sch_blackhole.o
CC kernel/entry/syscall_user_dispatch.o
CC [M] sound/pci/hda/hda_controller.o
AR lib/crypto/built-in.a
LD [M] lib/crypto/libarc4.o
CC kernel/dma/direct.o
CC crypto/shash.o
CC crypto/akcipher.o
CC arch/x86/kernel/apic/apic.o
CC arch/x86/kernel/apic/apic_common.o
CC sound/core/control.o
AR fs/hugetlbfs/built-in.a
CC lib/raid6/recov.o
CC fs/proc/fd.o
AR lib/xz/built-in.a
CC arch/x86/kernel/apic/apic_noop.o
CC arch/x86/events/intel/p6.o
CC crypto/sig.o
AR fs/exportfs/built-in.a
CC arch/x86/kernel/apic/ipi.o
CC kernel/entry/kvm.o
CC arch/x86/events/rapl.o
CC fs/proc/proc_tty.o
HOSTCC lib/raid6/mktables
CC crypto/kpp.o
AR drivers/pwm/built-in.a
CC arch/x86/events/intel/pt.o
CC kernel/irq/handle.o
CC lib/zstd/compress/zstd_compress_sequences.o
CC [M] arch/x86/kvm/x86.o
CC arch/x86/mm/pgprot.o
CC kernel/dma/ops_helpers.o
CC sound/core/misc.o
CC kernel/power/hibernate.o
CC kernel/locking/percpu-rwsem.o
AR net/netlink/built-in.a
CC arch/x86/mm/hugetlbpage.o
CC arch/x86/kernel/apic/vector.o
CC kernel/rcu/srcutree.o
CC io_uring/sync.o
CC fs/fat/file.o
AS arch/x86/kernel/acpi/wakeup_64.o
CC kernel/module/main.o
CC arch/x86/kernel/acpi/apei.o
CC kernel/module/strict_rwx.o
CC mm/swap.o
CC fs/fat/inode.o
UNROLL lib/raid6/int1.c
UNROLL lib/raid6/int2.c
UNROLL lib/raid6/int4.c
UNROLL lib/raid6/int8.c
UNROLL lib/raid6/int16.c
CC kernel/irq/manage.o
UNROLL lib/raid6/int32.c
CC lib/raid6/recov_ssse3.o
CC block/blk-ioc.o
CC arch/x86/kernel/kprobes/core.o
CC kernel/power/snapshot.o
CC arch/x86/kernel/kprobes/opt.o
CC arch/x86/kernel/cpu/rdrand.o
CC fs/lockd/clntlock.o
CC arch/x86/kernel/kprobes/ftrace.o
CC net/core/flow_dissector.o
CC fs/lockd/clntproc.o
CC net/sched/sch_fifo.o
CC fs/proc/cmdline.o
CC fs/lockd/clntxdr.o
CC kernel/time/time.o
CC fs/proc/consoles.o
CC crypto/acompress.o
CC lib/raid6/recov_avx2.o
CC kernel/irq/spurious.o
AR kernel/entry/built-in.a
CC arch/x86/kernel/cpu/match.o
CC net/core/sysctl_net_core.o
CC kernel/dma/dummy.o
CC kernel/irq/resend.o
CC kernel/time/timer.o
CC [M] net/netfilter/ipvs/ip_vs_conn.o
CC net/netfilter/core.o
CC kernel/locking/irqflag-debug.o
CC arch/x86/kernel/acpi/cppc.o
CC kernel/locking/mutex-debug.o
CC [M] net/netfilter/ipvs/ip_vs_core.o
CC arch/x86/mm/kasan_init_64.o
CC crypto/scompress.o
CC fs/nfs/dir.o
CC fs/ext4/fsync.o
CC lib/zstd/compress/zstd_compress_superblock.o
CC io_uring/advise.o
CC fs/proc/cpuinfo.o
CC [M] sound/pci/hda/hda_proc.o
CC kernel/locking/lockdep.o
CC kernel/futex/core.o
CC arch/x86/kernel/cpu/bugs.o
CC mm/truncate.o
CC lib/raid6/mmx.o
CC kernel/irq/chip.o
CC arch/x86/events/intel/uncore.o
CC [M] sound/pci/hda/hda_hwdep.o
CC fs/proc/devices.o
CC lib/raid6/sse1.o
CC lib/zstd/compress/zstd_double_fast.o
CC kernel/dma/contiguous.o
CC lib/raid6/sse2.o
CC lib/raid6/avx2.o
CC block/blk-map.o
CC [M] arch/x86/kvm/emulate.o
CC fs/nfs/file.o
CC arch/x86/kernel/acpi/cstate.o
AR arch/x86/kernel/kprobes/built-in.a
CC net/netfilter/nf_log.o
CC sound/core/device.o
CC kernel/rcu/tree.o
CC io_uring/filetable.o
CC fs/proc/interrupts.o
CC [M] arch/x86/kvm/i8259.o
CC drivers/gpio/gpiolib-devres.o
AR net/sched/built-in.a
CC net/ethtool/netlink.o
CC fs/proc/loadavg.o
CC kernel/time/hrtimer.o
CC arch/x86/mm/numa.o
CC fs/lockd/host.o
CC crypto/algboss.o
CC lib/raid6/avx512.o
CC arch/x86/kernel/apic/hw_nmi.o
CC fs/fat/misc.o
CC fs/proc/meminfo.o
CC sound/core/info.o
CC net/ethtool/bitset.o
CC kernel/dma/swiotlb.o
CC lib/raid6/recov_avx512.o
CC kernel/power/swap.o
CC kernel/power/user.o
AR arch/x86/kernel/acpi/built-in.a
CC net/netfilter/nf_queue.o
CC arch/x86/mm/numa_64.o
AR sound/pci/riptide/built-in.a
CC arch/x86/mm/amdtopology.o
CC io_uring/openclose.o
CC fs/proc/stat.o
CC fs/ext4/hash.o
CC [M] sound/pci/hda/hda_generic.o
CC kernel/futex/syscalls.o
CC kernel/cgroup/cgroup.o
CC kernel/irq/dummychip.o
CC net/netfilter/nf_sockopt.o
CC fs/nls/nls_base.o
CC mm/vmscan.o
CC block/blk-merge.o
CC arch/x86/kernel/cpu/aperfmperf.o
CC drivers/gpio/gpiolib-legacy.o
CC arch/x86/kernel/apic/io_apic.o
TABLE lib/raid6/tables.c
CC lib/raid6/int1.o
CC kernel/futex/pi.o
CC kernel/module/kmod.o
CC kernel/cgroup/rstat.o
CC lib/raid6/int2.o
CC drivers/gpio/gpiolib-cdev.o
CC fs/fat/nfs.o
CC crypto/testmgr.o
CC io_uring/uring_cmd.o
CC fs/proc/uptime.o
CC net/core/dev.o
CC kernel/irq/devres.o
CC fs/nfs/getroot.o
CC kernel/cgroup/namespace.o
CC fs/fat/namei_vfat.o
CC io_uring/epoll.o
CC fs/nls/nls_cp437.o
CC arch/x86/mm/srat.o
CC sound/core/isadma.o
CC arch/x86/kernel/apic/msi.o
CC fs/lockd/svc.o
CC fs/proc/util.o
CC kernel/futex/requeue.o
CC arch/x86/kernel/cpu/cpuid-deps.o
CC arch/x86/events/intel/uncore_nhmex.o
CC fs/ext4/ialloc.o
CC sound/core/vmaster.o
CC kernel/futex/waitwake.o
CC [M] net/netfilter/ipvs/ip_vs_ctl.o
CC kernel/time/timekeeping.o
CC kernel/irq/autoprobe.o
CC [M] arch/x86/kvm/irq.o
CC fs/ext4/indirect.o
CC fs/fat/namei_msdos.o
CC fs/nls/nls_ascii.o
CC arch/x86/events/intel/uncore_snb.o
CC kernel/dma/remap.o
CC kernel/irq/irqdomain.o
CC net/ethtool/strset.o
CC fs/nfs/inode.o
CC lib/raid6/int4.o
CC fs/nls/nls_iso8859-1.o
CC fs/proc/version.o
CC kernel/power/poweroff.o
CC crypto/cmac.o
CC kernel/module/tree_lookup.o
CC arch/x86/kernel/cpu/umwait.o
CC block/blk-timeout.o
CC kernel/cgroup/cgroup-v1.o
CC arch/x86/mm/pkeys.o
CC fs/ext4/inline.o
CC io_uring/statx.o
CC kernel/module/debug_kmemleak.o
AR kernel/power/built-in.a
CC fs/nls/nls_utf8.o
CC arch/x86/mm/pti.o
CC net/ethtool/linkinfo.o
CC sound/core/ctljack.o
CC arch/x86/events/intel/uncore_snbep.o
CC kernel/module/kallsyms.o
AR fs/unicode/built-in.a
CC arch/x86/events/intel/uncore_discovery.o
AR kernel/futex/built-in.a
CC kernel/trace/trace_clock.o
CC fs/nfs/super.o
AR kernel/dma/built-in.a
CC fs/ntfs/aops.o
CC fs/proc/softirqs.o
CC sound/core/jack.o
LDS arch/x86/kernel/vmlinux.lds
CC arch/x86/events/intel/cstate.o
AR fs/hostfs/built-in.a
CC fs/nfs/io.o
CC net/netfilter/utils.o
CC lib/raid6/int8.o
AR fs/nls/built-in.a
CC fs/proc/namespaces.o
CC fs/debugfs/inode.o
CC fs/tracefs/inode.o
CC arch/x86/kernel/cpu/proc.o
AR fs/fat/built-in.a
MKCAP arch/x86/kernel/cpu/capflags.c
CC block/blk-lib.o
CC crypto/hmac.o
CC fs/lockd/svclock.o
CC lib/raid6/int16.o
CC arch/x86/events/msr.o
CC kernel/time/ntp.o
CC kernel/trace/ftrace.o
CC arch/x86/kernel/apic/x2apic_phys.o
CC fs/btrfs/super.o
CC io_uring/net.o
AR arch/x86/mm/built-in.a
CC drivers/gpio/gpiolib-sysfs.o
CC [M] net/netfilter/ipvs/ip_vs_sched.o
CC fs/proc/self.o
CC kernel/irq/proc.o
CC kernel/irq/migration.o
CC kernel/module/procfs.o
CC net/ethtool/linkmodes.o
CC sound/core/timer.o
CC [M] net/netfilter/nfnetlink.o
CC fs/debugfs/file.o
CC arch/x86/kernel/cpu/powerflags.o
CC arch/x86/kernel/apic/x2apic_cluster.o
CC kernel/module/sysfs.o
CC lib/raid6/int32.o
CC fs/ntfs/attrib.o
CC kernel/cgroup/freezer.o
CC net/core/dev_addr_lists.o
AR fs/tracefs/built-in.a
CC fs/ext4/inode.o
CC block/blk-mq.o
AR sound/ppc/built-in.a
AR net/ipv4/netfilter/built-in.a
CC [M] net/ipv4/netfilter/nf_defrag_ipv4.o
CC net/ipv4/route.o
CC lib/zstd/compress/zstd_fast.o
AR sound/arm/built-in.a
AR sound/sh/built-in.a
CC arch/x86/kernel/cpu/feat_ctl.o
CC crypto/vmac.o
CC [M] net/ipv4/netfilter/nf_reject_ipv4.o
CC fs/proc/thread_self.o
AR sound/synth/emux/built-in.a
CC kernel/time/clocksource.o
AR sound/synth/built-in.a
CC kernel/time/jiffies.o
AR sound/usb/misc/built-in.a
AR sound/usb/usx2y/built-in.a
AR sound/usb/caiaq/built-in.a
AR sound/usb/6fire/built-in.a
AR sound/usb/hiface/built-in.a
CC kernel/trace/ring_buffer.o
AR sound/usb/bcd2000/built-in.a
AR sound/usb/built-in.a
CC lib/zstd/compress/zstd_lazy.o
CC kernel/locking/lockdep_proc.o
CC drivers/gpio/gpiolib-acpi.o
CC net/core/dst.o
CC kernel/irq/cpuhotplug.o
CC fs/lockd/svcshare.o
CC kernel/bpf/core.o
CC net/xfrm/xfrm_policy.o
CC lib/raid6/tables.o
CC block/blk-mq-tag.o
CC lib/zstd/compress/zstd_ldm.o
CC net/xfrm/xfrm_state.o
CC fs/nfs/direct.o
CC arch/x86/kernel/apic/apic_flat_64.o
CC net/xfrm/xfrm_hash.o
CC kernel/locking/spinlock.o
CC kernel/time/timer_list.o
AR kernel/module/built-in.a
CC net/core/netevent.o
CC fs/proc/proc_sysctl.o
CC kernel/cgroup/legacy_freezer.o
CC net/ethtool/rss.o
CC crypto/xcbc.o
CC kernel/irq/pm.o
AR fs/debugfs/built-in.a
CC kernel/time/timeconv.o
CC fs/ntfs/collate.o
CC kernel/time/timecounter.o
CC lib/zstd/compress/zstd_opt.o
CC kernel/time/alarmtimer.o
CC [M] arch/x86/kvm/lapic.o
CC kernel/locking/osq_lock.o
CC kernel/irq/msi.o
CC fs/ntfs/compress.o
CC fs/lockd/svcproc.o
AR arch/x86/events/intel/built-in.a
AR arch/x86/events/built-in.a
CC fs/ntfs/debug.o
CC [M] net/ipv4/netfilter/ip_tables.o
CC arch/x86/kernel/apic/probe_64.o
CC kernel/events/core.o
CC [M] net/netfilter/ipvs/ip_vs_xmit.o
CC io_uring/msg_ring.o
CC [M] sound/pci/hda/patch_realtek.o
AR lib/raid6/built-in.a
CC kernel/events/ring_buffer.o
CC fs/nfs/pagelist.o
CC drivers/gpio/gpiolib-swnode.o
CC fs/ext4/ioctl.o
CC kernel/locking/qspinlock.o
AR arch/x86/kernel/apic/built-in.a
CC fs/ext4/mballoc.o
CC [M] net/netfilter/ipvs/ip_vs_app.o
CC crypto/crypto_null.o
CC net/xfrm/xfrm_input.o
CC sound/core/hrtimer.o
CC kernel/rcu/rcu_segcblist.o
CC lib/fonts/fonts.o
CC net/core/neighbour.o
CC lib/fonts/font_8x8.o
CC mm/shmem.o
CC mm/util.o
CC lib/fonts/font_8x16.o
CC kernel/cgroup/pids.o
CC crypto/md5.o
AS arch/x86/kernel/head_64.o
CC arch/x86/kernel/head64.o
CC net/ethtool/linkstate.o
AR drivers/gpio/built-in.a
CC kernel/locking/rtmutex_api.o
CC arch/x86/kernel/ebda.o
CC drivers/pci/msi/pcidev_msi.o
CC sound/core/seq_device.o
AR lib/fonts/built-in.a
CC drivers/pci/msi/api.o
CC fs/ntfs/dir.o
AR kernel/rcu/built-in.a
CC lib/zstd/zstd_decompress_module.o
CC kernel/time/posix-timers.o
CC crypto/sha1_generic.o
CC fs/lockd/svcsubs.o
CC fs/proc/proc_net.o
CC arch/x86/kernel/cpu/intel.o
AR sound/firewire/built-in.a
AR sound/sparc/built-in.a
CC [M] arch/x86/kvm/i8254.o
AR sound/spi/built-in.a
CC kernel/irq/affinity.o
CC fs/proc/kcore.o
CC kernel/cgroup/cpuset.o
CC io_uring/timeout.o
CC fs/nfs/read.o
CC crypto/sha256_generic.o
CC arch/x86/kernel/platform-quirks.o
CC kernel/irq/matrix.o
CC fs/ntfs/file.o
CC [M] arch/x86/kvm/ioapic.o
CC [M] sound/core/control_led.o
CC lib/argv_split.o
CC [M] net/ipv4/netfilter/iptable_filter.o
CC drivers/pci/msi/msi.o
CC net/ethtool/debug.o
CC [M] net/netfilter/ipvs/ip_vs_sync.o
CC io_uring/sqpoll.o
CC arch/x86/kernel/process_64.o
CC kernel/trace/trace.o
CC kernel/events/callchain.o
AR kernel/bpf/built-in.a
CC kernel/fork.o
CC net/ethtool/wol.o
CC kernel/trace/trace_output.o
CC net/xfrm/xfrm_output.o
CC crypto/sha512_generic.o
CC fs/proc/kmsg.o
CC kernel/exec_domain.o
CC net/ipv4/inetpeer.o
CC [M] net/ipv4/netfilter/iptable_mangle.o
CC fs/ntfs/index.o
CC fs/ext4/migrate.o
CC kernel/locking/spinlock_debug.o
CC net/xfrm/xfrm_sysctl.o
CC fs/lockd/mon.o
CC [M] net/netfilter/nf_conntrack_core.o
CC arch/x86/kernel/cpu/intel_pconfig.o
CC [M] sound/core/hwdep.o
CC io_uring/fdinfo.o
CC crypto/sha3_generic.o
CC arch/x86/kernel/cpu/tsx.o
CC fs/nfs/symlink.o
CC fs/proc/page.o
CC kernel/trace/trace_seq.o
CC [M] net/netfilter/ipvs/ip_vs_est.o
CC kernel/time/posix-cpu-timers.o
CC drivers/pci/msi/irqdomain.o
CC fs/btrfs/ctree.o
CC fs/ntfs/inode.o
CC kernel/panic.o
CC kernel/cpu.o
CC kernel/locking/qrwlock.o
CC kernel/trace/trace_stat.o
AR kernel/irq/built-in.a
CC arch/x86/kernel/cpu/intel_epb.o
CC kernel/time/posix-clock.o
CC io_uring/tctx.o
CC block/blk-stat.o
CC net/ethtool/features.o
CC fs/lockd/trace.o
CC [M] sound/pci/hda/patch_analog.o
CC fs/ntfs/mft.o
CC io_uring/poll.o
CC crypto/blake2b_generic.o
CC [M] sound/core/pcm.o
CC arch/x86/kernel/cpu/amd.o
CC [M] net/ipv4/netfilter/iptable_nat.o
CC kernel/trace/trace_printk.o
CC fs/ext4/mmp.o
AR kernel/locking/built-in.a
CC crypto/ecb.o
CC fs/ntfs/mst.o
CC mm/mmzone.o
CC [M] net/netfilter/nf_conntrack_standalone.o
CC kernel/trace/pid_list.o
CC lib/zstd/decompress/huf_decompress.o
CC arch/x86/kernel/signal.o
CC kernel/exit.o
AR drivers/pci/msi/built-in.a
CC drivers/pci/pcie/portdrv.o
AR fs/proc/built-in.a
CC drivers/pci/hotplug/pci_hotplug_core.o
AR drivers/pci/controller/dwc/built-in.a
CC kernel/softirq.o
AR drivers/pci/controller/mobiveil/built-in.a
CC mm/vmstat.o
CC drivers/pci/controller/vmd.o
CC io_uring/cancel.o
AR sound/parisc/built-in.a
CC io_uring/kbuf.o
AR sound/pcmcia/vx/built-in.a
CC fs/nfs/unlink.o
AR sound/pcmcia/pdaudiocf/built-in.a
AR sound/pcmcia/built-in.a
CC [M] arch/x86/kvm/irq_comm.o
CC block/blk-mq-sysfs.o
CC drivers/pci/pcie/rcec.o
CC [M] net/netfilter/nf_conntrack_expect.o
CC net/xfrm/xfrm_replay.o
CC [M] net/ipv4/netfilter/ipt_REJECT.o
CC kernel/resource.o
CC kernel/time/itimer.o
CC [M] sound/pci/hda/patch_hdmi.o
CC drivers/pci/pcie/aspm.o
CC lib/zstd/decompress/zstd_ddict.o
CC [M] net/netfilter/ipvs/ip_vs_proto.o
CC net/ethtool/privflags.o
CC [M] sound/core/pcm_native.o
CC lib/bug.o
CC crypto/cbc.o
CC mm/backing-dev.o
CC fs/lockd/xdr.o
AR kernel/cgroup/built-in.a
CC arch/x86/kernel/signal_64.o
CC kernel/sysctl.o
CC arch/x86/kernel/cpu/hygon.o
CC net/core/rtnetlink.o
CC fs/ntfs/namei.o
CC arch/x86/kernel/traps.o
CC kernel/trace/trace_sched_switch.o
CC kernel/capability.o
CC fs/nfs/write.o
CC fs/ext4/move_extent.o
CC arch/x86/kernel/cpu/centaur.o
CC fs/btrfs/extent-tree.o
CC drivers/pci/hotplug/acpi_pcihp.o
CC fs/pstore/inode.o
CC fs/nfs/namespace.o
CC crypto/pcbc.o
CC block/blk-mq-cpumap.o
AR drivers/pci/controller/built-in.a
AR drivers/pci/switch/built-in.a
CC drivers/pci/access.o
CC arch/x86/kernel/cpu/zhaoxin.o
CC drivers/pci/hotplug/pciehp_core.o
CC drivers/pci/pcie/aer.o
CC io_uring/rsrc.o
CC [M] arch/x86/kvm/cpuid.o
CC fs/efivarfs/inode.o
CC kernel/time/clockevents.o
CC net/ipv4/protocol.o
CC fs/efivarfs/file.o
CC fs/ntfs/runlist.o
CC drivers/pci/hotplug/pciehp_ctrl.o
CC fs/nfs/mount_clnt.o
CC [M] arch/x86/kvm/pmu.o
CC fs/efivarfs/super.o
CC net/ethtool/rings.o
CC kernel/ptrace.o
CC crypto/cts.o
CC drivers/pci/pcie/err.o
CC [M] arch/x86/kvm/mtrr.o
CC net/xfrm/xfrm_device.o
CC net/ethtool/channels.o
CC arch/x86/kernel/cpu/perfctr-watchdog.o
CC arch/x86/kernel/idt.o
CC [M] fs/netfs/buffered_read.o
CC fs/lockd/clnt4xdr.o
CC block/blk-mq-sched.o
CC fs/pstore/platform.o
CC [M] fs/netfs/io.o
CC net/core/utils.o
CC arch/x86/kernel/cpu/vmware.o
CC [M] net/netfilter/ipvs/ip_vs_pe.o
CC [M] net/netfilter/nf_conntrack_helper.o
CC lib/zstd/decompress/zstd_decompress.o
CC fs/efivarfs/vars.o
CC kernel/time/tick-common.o
CC drivers/pci/hotplug/pciehp_pci.o
CC fs/pstore/pmsg.o
CC arch/x86/kernel/irq.o
CC mm/mm_init.o
CC fs/ext4/namei.o
CC [M] arch/x86/kvm/hyperv.o
CC drivers/pci/hotplug/pciehp_hpc.o
CC fs/nfs/nfstrace.o
CC kernel/trace/trace_functions.o
CC net/ipv4/ip_input.o
CC lib/zstd/decompress/zstd_decompress_block.o
CC crypto/lrw.o
CC [M] arch/x86/kvm/debugfs.o
CC mm/percpu.o
CC arch/x86/kernel/irq_64.o
CC arch/x86/kernel/cpu/hypervisor.o
CC fs/nfs/export.o
CC fs/ntfs/super.o
CC [M] arch/x86/kvm/mmu/mmu.o
CC drivers/pci/pcie/aer_inject.o
CC fs/ext4/page-io.o
CC net/ethtool/coalesce.o
AR fs/pstore/built-in.a
CC [M] sound/core/pcm_lib.o
CC [M] sound/pci/hda/hda_eld.o
CC lib/zstd/zstd_common_module.o
CC kernel/user.o
CC net/ipv4/ip_fragment.o
CC arch/x86/kernel/cpu/mshyperv.o
CC [M] net/netfilter/nf_conntrack_proto.o
CC drivers/pci/pcie/pme.o
AR fs/efivarfs/built-in.a
CC block/ioctl.o
CC [M] fs/fscache/cache.o
CC fs/lockd/xdr4.o
CC [M] fs/fscache/cookie.o
CC fs/lockd/svc4proc.o
CC [M] arch/x86/kvm/mmu/page_track.o
CC [M] net/netfilter/ipvs/ip_vs_proto_tcp.o
CC [M] fs/netfs/iterator.o
CC net/xfrm/xfrm_algo.o
CC kernel/time/tick-broadcast.o
CC crypto/xts.o
CC drivers/pci/bus.o
CC [M] net/netfilter/nf_conntrack_proto_generic.o
CC io_uring/rw.o
CC drivers/video/console/dummycon.o
CC drivers/video/logo/logo.o
CC drivers/video/backlight/backlight.o
CC fs/nfs/sysfs.o
CC drivers/video/fbdev/core/fb_notify.o
CC kernel/trace/trace_preemptirq.o
CC drivers/pci/hotplug/acpiphp_core.o
CC crypto/ctr.o
CC [M] sound/pci/hda/hda_intel.o
CC drivers/video/console/vgacon.o
CC drivers/pci/pcie/dpc.o
CC drivers/pci/probe.o
CC arch/x86/kernel/cpu/capflags.o
HOSTCC drivers/video/logo/pnmtologo
AR sound/pci/rme9652/built-in.a
CC lib/zstd/common/debug.o
AR arch/x86/kernel/cpu/built-in.a
CC net/core/link_watch.o
CC arch/x86/kernel/dumpstack_64.o
CC fs/nfs/fs_context.o
CC net/ethtool/pause.o
CC [M] fs/netfs/main.o
CC [M] fs/netfs/objects.o
CC drivers/idle/intel_idle.o
AR drivers/char/ipmi/built-in.a
CC net/unix/af_unix.o
CC block/genhd.o
CC kernel/time/tick-broadcast-hrtimer.o
CC net/unix/garbage.o
CC kernel/time/tick-oneshot.o
LOGO drivers/video/logo/logo_linux_clut224.c
LD [M] sound/pci/hda/snd-hda-codec.o
CC drivers/video/logo/logo_linux_clut224.o
CC net/ethtool/eee.o
CC fs/ntfs/sysctl.o
CC fs/ntfs/unistr.o
AR drivers/video/logo/built-in.a
CC drivers/pci/host-bridge.o
CC block/ioprio.o
AR net/ipv6/netfilter/built-in.a
CC crypto/gcm.o
CC net/ipv6/af_inet6.o
CC [M] net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
CC kernel/events/hw_breakpoint.o
CC net/ipv4/ip_forward.o
CC [M] net/ipv6/netfilter/nf_conntrack_reasm.o
CC fs/lockd/procfs.o
CC drivers/pci/hotplug/acpiphp_glue.o
CC lib/zstd/common/entropy_common.o
CC [M] drivers/video/fbdev/core/fb_info.o
CC net/xfrm/xfrm_user.o
CC kernel/trace/trace_nop.o
AR drivers/video/backlight/built-in.a
CC [M] net/netfilter/nf_conntrack_proto_tcp.o
CC drivers/video/aperture.o
CC drivers/pci/remove.o
CC arch/x86/kernel/time.o
CC kernel/time/tick-sched.o
CC kernel/events/uprobes.o
AR drivers/pci/pcie/built-in.a
CC drivers/pci/pci.o
CC [M] fs/fscache/io.o
CC [M] net/netfilter/ipvs/ip_vs_proto_udp.o
CC [M] sound/core/pcm_misc.o
CC fs/nfs/sysctl.o
CC fs/nfs/nfs2super.o
CC [M] net/netfilter/nf_conntrack_proto_udp.o
AR drivers/video/console/built-in.a
CC crypto/pcrypt.o
CC fs/ntfs/upcase.o
CC net/ipv6/anycast.o
CC net/core/filter.o
LD [M] fs/netfs/netfs.o
CC arch/x86/kernel/ioport.o
AR fs/lockd/built-in.a
CC arch/x86/kernel/dumpstack.o
CC [M] net/netfilter/nf_conntrack_proto_icmp.o
CC io_uring/opdef.o
CC [M] fs/fuse/dev.o
CC [M] fs/smb/common/cifs_arc4.o
CC net/ethtool/tsinfo.o
CC kernel/trace/trace_functions_graph.o
CC [M] fs/fuse/dir.o
CC [M] drivers/video/fbdev/core/fbmem.o
AR drivers/idle/built-in.a
CC drivers/video/cmdline.o
CC fs/btrfs/print-tree.o
CC drivers/acpi/acpica/dsargs.o
CC mm/slab_common.o
CC drivers/acpi/acpica/dscontrol.o
CC [M] sound/core/pcm_memory.o
CC drivers/video/nomodeset.o
CC drivers/pnp/pnpacpi/core.o
CC block/badblocks.o
CC drivers/pci/pci-driver.o
CC [M] fs/smb/common/cifs_md4.o
CC crypto/cryptd.o
AR fs/ntfs/built-in.a
CC [M] fs/fscache/main.o
AR drivers/pci/hotplug/built-in.a
AR drivers/amba/built-in.a
CC kernel/signal.o
AR sound/mips/built-in.a
LD [M] sound/pci/hda/snd-hda-codec-generic.o
AR sound/soc/built-in.a
LD [M] sound/pci/hda/snd-hda-codec-realtek.o
LD [M] sound/pci/hda/snd-hda-codec-analog.o
CC drivers/acpi/numa/srat.o
LD [M] sound/pci/hda/snd-hda-codec-hdmi.o
LD [M] sound/pci/hda/snd-hda-intel.o
AR sound/atmel/built-in.a
CC kernel/time/vsyscall.o
AR sound/hda/built-in.a
AR sound/pci/trident/built-in.a
CC [M] fs/fuse/file.o
CC [M] sound/hda/hda_bus_type.o
CC fs/ext4/readpage.o
CC net/ipv4/ip_options.o
AR sound/pci/ymfpci/built-in.a
AR sound/pci/vx222/built-in.a
AR sound/pci/built-in.a
CC kernel/sys.o
CC [M] fs/fscache/volume.o
CC net/ipv4/ip_output.o
CC [M] sound/hda/hdac_bus.o
AR sound/x86/built-in.a
CC arch/x86/kernel/nmi.o
CC mm/compaction.o
LD [M] net/ipv6/netfilter/nf_defrag_ipv6.o
CC drivers/acpi/acpica/dsdebug.o
CC block/blk-rq-qos.o
CC [M] sound/hda/hdac_device.o
CC [M] drivers/video/fbdev/core/fbcmap.o
CC fs/ext4/resize.o
CC lib/zstd/common/error_private.o
CC [M] net/netfilter/ipvs/ip_vs_nfct.o
CC lib/zstd/common/fse_decompress.o
CC net/ipv4/ip_sockglue.o
CC drivers/pnp/pnpacpi/rsparser.o
CC [M] fs/smb/client/trace.o
CC io_uring/notif.o
CC net/ethtool/cabletest.o
CC [M] net/netfilter/nf_conntrack_extend.o
CC kernel/time/timekeeping_debug.o
CC net/ipv4/inet_hashtables.o
CC [M] sound/core/memalloc.o
AR sound/xen/built-in.a
AR sound/virtio/built-in.a
CC sound/sound_core.o
CC drivers/acpi/acpica/dsfield.o
CC net/ipv6/ip6_output.o
CC kernel/trace/fgraph.o
CC lib/buildid.o
CC mm/show_mem.o
AR drivers/acpi/numa/built-in.a
CC drivers/acpi/apei/apei-base.o
AR kernel/events/built-in.a
CC lib/cmdline.o
AR drivers/acpi/pmic/built-in.a
CC crypto/des_generic.o
CC sound/last.o
CC fs/btrfs/root-tree.o
CC mm/interval_tree.o
CC net/ipv6/ip6_input.o
CC block/disk-events.o
CC [M] net/netfilter/nf_conntrack_acct.o
CC drivers/acpi/apei/hest.o
CC kernel/umh.o
CC arch/x86/kernel/ldt.o
CC kernel/time/namespace.o
CC [M] drivers/video/fbdev/core/modedb.o
CC net/ethtool/tunnels.o
CC drivers/pci/search.o
CC drivers/acpi/acpica/dsinit.o
CC [M] fs/fscache/proc.o
CC net/unix/sysctl_net_unix.o
CC net/ipv6/addrconf.o
CC fs/nfs/proc.o
CC [M] sound/hda/hdac_sysfs.o
AR drivers/pnp/pnpacpi/built-in.a
CC drivers/pnp/core.o
CC [M] sound/hda/hdac_regmap.o
CC lib/cpumask.o
CC [M] fs/fuse/inode.o
CC crypto/aes_generic.o
CC drivers/pci/pci-sysfs.o
CC drivers/acpi/acpica/dsmethod.o
CC io_uring/io-wq.o
CC [M] net/netfilter/ipvs/ip_vs_rr.o
CC fs/ext4/super.o
CC [M] sound/core/pcm_timer.o
AR net/xfrm/built-in.a
CC [M] fs/overlayfs/super.o
LD [M] sound/core/snd-ctl-led.o
CC net/ethtool/fec.o
CC kernel/workqueue.o
CC drivers/acpi/apei/erst.o
CC kernel/trace/blktrace.o
CC mm/list_lru.o
CC fs/open.o
CC block/blk-ia-ranges.o
LD [M] fs/fscache/fscache.o
AR kernel/time/built-in.a
CC mm/workingset.o
CC fs/read_write.o
CC drivers/acpi/acpica/dsmthdat.o
CC net/ipv6/addrlabel.o
CC drivers/acpi/apei/bert.o
CC block/early-lookup.o
CC lib/zstd/common/zstd_common.o
AR drivers/clk/actions/built-in.a
CC drivers/pnp/card.o
AR drivers/clk/analogbits/built-in.a
CC kernel/pid.o
AR drivers/clk/bcm/built-in.a
AR drivers/clk/imgtec/built-in.a
AR drivers/clk/imx/built-in.a
CC net/unix/diag.o
AR drivers/clk/ingenic/built-in.a
CC net/unix/scm.o
AR drivers/clk/mediatek/built-in.a
CC [M] sound/hda/hdac_controller.o
CC kernel/task_work.o
AR drivers/clk/microchip/built-in.a
AR drivers/clk/mstar/built-in.a
LD [M] sound/core/snd-hwdep.o
CC arch/x86/kernel/setup.o
AR drivers/clk/mvebu/built-in.a
LD [M] sound/core/snd-pcm.o
AR drivers/clk/ralink/built-in.a
AR drivers/clk/renesas/built-in.a
CC [M] drivers/video/fbdev/core/fbcvt.o
AR drivers/clk/socfpga/built-in.a
AR sound/core/built-in.a
AR drivers/clk/sprd/built-in.a
CC drivers/pci/rom.o
AR drivers/clk/starfive/built-in.a
AR drivers/clk/sunxi-ng/built-in.a
AR drivers/clk/ti/built-in.a
AR drivers/clk/versatile/built-in.a
CC drivers/clk/x86/clk-lpss-atom.o
CC [M] drivers/video/fbdev/core/fb_cmdline.o
CC drivers/clk/x86/clk-pmc-atom.o
CC [M] sound/hda/hdac_stream.o
CC drivers/acpi/acpica/dsobject.o
CC fs/btrfs/dir-item.o
LD [M] net/netfilter/ipvs/ip_vs.o
CC drivers/acpi/apei/ghes.o
CC crypto/deflate.o
CC kernel/extable.o
CC fs/nfs/nfs2xdr.o
CC [M] net/netfilter/nf_conntrack_seqadj.o
CC kernel/params.o
CC kernel/trace/trace_events.o
CC block/bsg.o
CC net/ethtool/eeprom.o
CC fs/ext4/symlink.o
CC fs/nfs/nfs3super.o
CC fs/nfs/nfs3client.o
CC net/ethtool/stats.o
CC drivers/pnp/driver.o
CC net/ipv4/inet_timewait_sock.o
CC arch/x86/kernel/x86_init.o
CC kernel/trace/trace_export.o
CC fs/btrfs/file-item.o
CC [M] fs/overlayfs/namei.o
CC net/ethtool/phc_vclocks.o
CC [M] fs/fuse/control.o
CC drivers/pci/setup-res.o
CC fs/nfs/nfs3proc.o
CC drivers/acpi/acpica/dsopcode.o
AR drivers/clk/x86/built-in.a
CC [M] sound/hda/array.o
AR drivers/clk/xilinx/built-in.a
CC drivers/clk/clk-devres.o
CC [M] drivers/video/fbdev/core/fb_io_fops.o
AR drivers/video/fbdev/omap/built-in.a
CC [M] drivers/video/fbdev/core/fb_backlight.o
AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a
AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a
AR io_uring/built-in.a
AR drivers/video/fbdev/omap2/omapfb/built-in.a
CC [M] drivers/video/fbdev/uvesafb.o
AR drivers/video/fbdev/omap2/built-in.a
CC [M] drivers/video/fbdev/core/fbmon.o
CC kernel/trace/trace_event_perf.o
AR net/unix/built-in.a
CC net/packet/af_packet.o
CC net/key/af_key.o
CC crypto/crc32c_generic.o
CC mm/debug.o
CC lib/ctype.o
CC fs/ext4/sysfs.o
CC [M] fs/smb/client/cifsfs.o
CC net/packet/diag.o
CC block/bsg-lib.o
CC drivers/pnp/resource.o
CC arch/x86/kernel/i8259.o
CC mm/gup.o
CC drivers/acpi/acpica/dspkginit.o
CC kernel/trace/trace_events_filter.o
CC drivers/clk/clk-bulk.o
CC arch/x86/kernel/irqinit.o
CC [M] net/netfilter/nf_conntrack_proto_icmpv6.o
CC [M] sound/hda/hdmi_chmap.o
CC drivers/pnp/manager.o
CC [M] drivers/video/fbdev/simplefb.o
CC [M] fs/fuse/xattr.o
CC crypto/crct10dif_common.o
CC net/ethtool/mm.o
CC drivers/pci/irq.o
CC drivers/pci/vpd.o
CC [M] fs/smb/client/cifs_debug.o
CC arch/x86/kernel/jump_label.o
AR drivers/acpi/apei/built-in.a
CC [M] sound/hda/trace.o
CC fs/btrfs/inode-item.o
CC fs/file_table.o
CC net/ethtool/module.o
CC crypto/crct10dif_generic.o
CC net/ethtool/pse-pd.o
CC [M] arch/x86/kvm/mmu/spte.o
CC [M] fs/overlayfs/util.o
CC [M] arch/x86/kvm/mmu/tdp_iter.o
CC drivers/acpi/acpica/dsutils.o
CC fs/ext4/xattr.o
CC [M] net/netfilter/nf_conntrack_proto_dccp.o
CC drivers/clk/clkdev.o
CC net/ipv4/inet_connection_sock.o
CC [M] arch/x86/kvm/mmu/tdp_mmu.o
CC crypto/authenc.o
CC fs/nfs/nfs3xdr.o
CC net/ethtool/plca.o
CC arch/x86/kernel/irq_work.o
CC block/blk-cgroup.o
AR lib/zstd/built-in.a
CC lib/dec_and_lock.o
CC drivers/pci/setup-bus.o
CC crypto/authencesn.o
CC mm/mmap_lock.o
CC arch/x86/kernel/probe_roms.o
CC mm/highmem.o
CC [M] fs/fuse/acl.o
CC [M] fs/overlayfs/inode.o
CC net/ipv4/tcp.o
CC drivers/pnp/support.o
CC [M] drivers/video/fbdev/core/fb_defio.o
CC [M] sound/hda/hdac_component.o
CC lib/decompress.o
CC crypto/lzo.o
CC [M] fs/fuse/readdir.o
CC drivers/acpi/acpica/dswexec.o
CC lib/decompress_bunzip2.o
CC fs/btrfs/disk-io.o
CC drivers/clk/clk.o
CC fs/super.o
CC net/ipv6/route.o
CC block/blk-cgroup-rwstat.o
CC net/ipv4/tcp_input.o
CC drivers/pnp/interface.o
CC [M] fs/fuse/ioctl.o
CC [M] arch/x86/kvm/smm.o
CC drivers/acpi/acpica/dswload.o
CC drivers/pci/vc.o
CC [M] drivers/video/fbdev/core/fb_chrdev.o
CC [M] fs/overlayfs/file.o
CC block/blk-throttle.o
CC arch/x86/kernel/sys_ia32.o
CC [M] arch/x86/kvm/vmx/vmx.o
CC kernel/trace/trace_events_trigger.o
CC drivers/pci/mmap.o
CC mm/memory.o
CC drivers/pnp/quirks.o
CC fs/char_dev.o
CC net/ipv6/ip6_fib.o
AR net/ethtool/built-in.a
CC [M] arch/x86/kvm/kvm-asm-offsets.s
CC drivers/pci/setup-irq.o
CC [M] sound/hda/hdac_i915.o
CC [M] net/netfilter/nf_conntrack_proto_sctp.o
CC [M] fs/smb/client/connect.o
CC crypto/lzo-rle.o
CC net/ipv6/ipv6_sockglue.o
CC drivers/clk/clk-divider.o
CC [M] fs/overlayfs/dir.o
CC lib/decompress_inflate.o
CC [M] sound/hda/intel-dsp-config.o
CC drivers/acpi/acpica/dswload2.o
CC drivers/pnp/system.o
CC [M] fs/overlayfs/readdir.o
CC drivers/clk/clk-fixed-factor.o
CC block/mq-deadline.o
LD [M] fs/fuse/fuse.o
CC drivers/pci/proc.o
CC [M] net/netfilter/nf_conntrack_netlink.o
AR net/bridge/netfilter/built-in.a
CC net/bridge/br.o
CC block/kyber-iosched.o
CC block/bfq-iosched.o
AR net/key/built-in.a
CC [M] fs/smb/client/dir.o
CC crypto/lz4.o
CC [M] drivers/video/fbdev/core/fb_procfs.o
CC fs/stat.o
CC drivers/pci/slot.o
CC lib/decompress_unlz4.o
CC arch/x86/kernel/signal_32.o
AR drivers/pnp/built-in.a
CC drivers/acpi/acpica/dswscope.o
CC drivers/clk/clk-fixed-rate.o
CC drivers/dma/dw/core.o
AR drivers/soc/apple/built-in.a
AR drivers/soc/aspeed/built-in.a
AR drivers/soc/fsl/built-in.a
AR drivers/soc/bcm/bcm63xx/built-in.a
CC drivers/virtio/virtio.o
AR drivers/soc/bcm/built-in.a
CC fs/exec.o
CC drivers/tty/vt/vt_ioctl.o
AR drivers/soc/fujitsu/built-in.a
AR drivers/soc/imx/built-in.a
CC drivers/tty/hvc/hvc_console.o
CC crypto/lz4hc.o
AR drivers/soc/ixp4xx/built-in.a
AR fs/nfs/built-in.a
CC drivers/dma/hsu/hsu.o
AR drivers/soc/loongson/built-in.a
CC [M] fs/smb/client/file.o
CC [M] sound/hda/intel-nhlt.o
AR drivers/soc/mediatek/built-in.a
CC fs/pipe.o
AR drivers/soc/microchip/built-in.a
AR drivers/soc/nuvoton/built-in.a
AR drivers/soc/pxa/built-in.a
AR drivers/soc/amlogic/built-in.a
AR drivers/dma/idxd/built-in.a
CC [M] arch/x86/kvm/vmx/pmu_intel.o
AR drivers/soc/qcom/built-in.a
AR drivers/soc/renesas/built-in.a
AR drivers/soc/rockchip/built-in.a
AR drivers/soc/sifive/built-in.a
AR drivers/soc/sunxi/built-in.a
AR drivers/soc/ti/built-in.a
CC mm/mincore.o
AR drivers/soc/xilinx/built-in.a
AR drivers/soc/built-in.a
CC kernel/trace/trace_eprobe.o
CC crypto/xxhash_generic.o
CC drivers/dma/dw/dw.o
CC drivers/clk/clk-gate.o
CC drivers/tty/serial/8250/8250_core.o
CC drivers/acpi/acpica/dswstate.o
CC lib/decompress_unlzma.o
CC drivers/tty/serial/8250/8250_pnp.o
CC net/ipv4/tcp_output.o
CC [M] net/netfilter/nf_nat_core.o
CC drivers/tty/serial/serial_core.o
AR drivers/tty/ipwireless/built-in.a
CC [M] fs/overlayfs/copy_up.o
CC crypto/rng.o
CC [M] drivers/video/fbdev/core/fbsysfs.o
CC [M] fs/overlayfs/export.o
CC drivers/pci/pci-acpi.o
CC [M] sound/hda/intel-sdw-acpi.o
CC kernel/trace/trace_kprobe.o
CC arch/x86/kernel/sys_x86_64.o
CC drivers/virtio/virtio_ring.o
AR net/packet/built-in.a
CC net/core/sock_diag.o
CC block/bfq-wf2q.o
CC drivers/acpi/dptf/int340x_thermal.o
CC net/bridge/br_device.o
CC drivers/acpi/acpica/evevent.o
CC fs/btrfs/transaction.o
AR drivers/dma/hsu/built-in.a
CC drivers/tty/serial/serial_base_bus.o
CC drivers/char/hw_random/core.o
AR drivers/tty/hvc/built-in.a
CC drivers/char/agp/backend.o
CC [M] net/netfilter/nf_nat_proto.o
CC drivers/tty/vt/vc_screen.o
CC lib/decompress_unlzo.o
AR drivers/dma/mediatek/built-in.a
CC lib/decompress_unxz.o
CC drivers/dma/dw/idma32.o
CC [M] drivers/video/fbdev/core/fbcon.o
LD [M] sound/hda/snd-hda-core.o
LD [M] sound/hda/snd-intel-dspcfg.o
LD [M] sound/hda/snd-intel-sdw-acpi.o
AR sound/built-in.a
CC block/bfq-cgroup.o
CC drivers/tty/serial/8250/8250_port.o
CC drivers/tty/serial/8250/8250_dma.o
AR drivers/acpi/dptf/built-in.a
CC drivers/acpi/tables.o
CC drivers/acpi/acpica/evgpe.o
CC crypto/drbg.o
CC drivers/clk/clk-multiplier.o
CC arch/x86/kernel/espfix_64.o
AR drivers/dma/qcom/built-in.a
AR drivers/dma/ti/built-in.a
CC arch/x86/kernel/ksysfs.o
CC drivers/tty/serial/8250/8250_dwlib.o
CC block/blk-mq-pci.o
CC net/ipv6/ndisc.o
CC drivers/char/tpm/tpm-chip.o
CC kernel/trace/error_report-traces.o
CC arch/x86/kernel/bootflag.o
CC arch/x86/kernel/e820.o
CC [M] fs/overlayfs/params.o
CC drivers/tty/serial/8250/8250_pcilib.o
CC lib/decompress_unzstd.o
CC drivers/char/hw_random/intel-rng.o
CC drivers/pci/quirks.o
CC drivers/char/agp/generic.o
CC drivers/dma/dw/acpi.o
CC drivers/acpi/acpica/evgpeblk.o
CC drivers/tty/vt/selection.o
CC drivers/char/mem.o
CC net/core/dev_ioctl.o
CC drivers/tty/serial/8250/8250_pci.o
CC arch/x86/kernel/pci-dma.o
CC drivers/clk/clk-mux.o
CC fs/btrfs/inode.o
CC arch/x86/kernel/quirks.o
CC [M] net/netfilter/nf_nat_helper.o
CC lib/dump_stack.o
CC block/blk-mq-virtio.o
CC crypto/jitterentropy.o
CC drivers/char/random.o
CC net/bridge/br_fdb.o
CC net/bridge/br_forward.o
CC [M] arch/x86/kvm/vmx/vmcs12.o
CC kernel/trace/power-traces.o
CC drivers/char/agp/isoch.o
CC drivers/acpi/acpica/evgpeinit.o
CC net/ipv4/tcp_timer.o
CC net/bridge/br_if.o
CC block/blk-mq-debugfs.o
CC drivers/char/tpm/tpm-dev-common.o
CC drivers/char/misc.o
CC drivers/virtio/virtio_anchor.o
CC drivers/tty/serial/serial_ctrl.o
AR drivers/char/hw_random/built-in.a
CC fs/btrfs/file.o
CC drivers/dma/dw/pci.o
LD [M] fs/overlayfs/overlay.o
CC drivers/clk/clk-composite.o
CC fs/namei.o
CC kernel/trace/rpm-traces.o
CC drivers/tty/vt/keyboard.o
CC net/bridge/br_input.o
CC [M] net/netfilter/nf_nat_redirect.o
CC drivers/tty/serial/8250/8250_exar.o
CC drivers/acpi/acpica/evgpeutil.o
CC lib/earlycpio.o
CC arch/x86/kernel/topology.o
CC drivers/tty/serial/serial_port.o
CC [M] net/netfilter/nf_nat_masquerade.o
CC lib/extable.o
CC crypto/jitterentropy-kcapi.o
CC drivers/clk/clk-fractional-divider.o
CC drivers/virtio/virtio_pci_modern_dev.o
CC drivers/acpi/blacklist.o
CC kernel/trace/trace_dynevent.o
CC drivers/char/tpm/tpm-dev.o
CC drivers/char/agp/intel-agp.o
CC lib/idr.o
CC lib/flex_proportions.o
CC net/bridge/br_ioctl.o
CC drivers/acpi/acpica/evglock.o
CC net/core/tso.o
CC [M] drivers/video/fbdev/core/bitblit.o
CC drivers/acpi/acpica/evhandler.o
CC drivers/clk/clk-gpio.o
AR drivers/dma/dw/built-in.a
AR drivers/dma/xilinx/built-in.a
CC [M] drivers/dma/ioat/init.o
CC block/blk-pm.o
CC drivers/acpi/acpica/evmisc.o
CC [M] drivers/dma/ioat/dma.o
CC arch/x86/kernel/kdebugfs.o
CC block/holder.o
CC drivers/dma/dmaengine.o
CC drivers/char/agp/intel-gtt.o
CC crypto/ghash-generic.o
CC fs/fcntl.o
CC drivers/acpi/acpica/evregion.o
CC [M] drivers/dma/ioat/prep.o
CC [M] net/netfilter/x_tables.o
CC fs/btrfs/defrag.o
CC fs/ioctl.o
CC drivers/tty/serial/8250/8250_early.o
CC drivers/acpi/osi.o
AR drivers/iommu/amd/built-in.a
CC drivers/iommu/intel/dmar.o
CC drivers/char/tpm/tpm-interface.o
CC lib/irq_regs.o
CC drivers/iommu/intel/iommu.o
AR drivers/clk/built-in.a
CC drivers/tty/serial/earlycon.o
CC net/bridge/br_stp.o
CC drivers/virtio/virtio_pci_legacy_dev.o
CC lib/is_single_threaded.o
CC drivers/tty/serial/8250/8250_dw.o
CC net/ipv4/tcp_ipv4.o
CC kernel/trace/trace_probe.o
CC net/ipv4/tcp_minisocks.o
CC drivers/acpi/osl.o
CC drivers/acpi/acpica/evrgnini.o
AR net/dsa/built-in.a
CC arch/x86/kernel/alternative.o
CC [M] net/netfilter/xt_tcpudp.o
CC mm/mlock.o
CC crypto/af_alg.o
CC net/ipv6/udp.o
AR block/built-in.a
CC [M] arch/x86/kvm/vmx/hyperv.o
CC fs/readdir.o
AR drivers/gpu/host1x/built-in.a
CC drivers/pci/ats.o
AR drivers/gpu/drm/tests/built-in.a
CC [M] drivers/gpu/drm/tests/drm_kunit_helpers.o
CC [M] drivers/video/fbdev/core/softcursor.o
CC [M] drivers/gpu/drm/tests/drm_buddy_test.o
AR drivers/gpu/drm/arm/built-in.a
CC [M] net/netfilter/xt_mark.o
CC net/core/sock_reuseport.o
CC fs/ext4/xattr_hurd.o
CC lib/klist.o
CC drivers/pci/iov.o
CC net/core/fib_notifier.o
AR drivers/gpu/drm/display/built-in.a
CC drivers/tty/vt/consolemap.o
CC [M] drivers/gpu/drm/display/drm_display_helper_mod.o
CC net/ipv6/udplite.o
CC drivers/virtio/virtio_pci_modern.o
CC drivers/acpi/acpica/evsci.o
CC fs/select.o
CC drivers/pci/pci-label.o
CC drivers/tty/serial/8250/8250_lpss.o
CC arch/x86/kernel/i8253.o
AR drivers/char/agp/built-in.a
AR drivers/gpu/drm/renesas/rcar-du/built-in.a
AR drivers/gpu/drm/renesas/built-in.a
CC net/ipv6/raw.o
CC drivers/char/tpm/tpm1-cmd.o
CC [M] drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
CC [M] drivers/dma/ioat/dca.o
CC fs/dcache.o
CC drivers/pci/pci-stub.o
CC lib/kobject.o
CC kernel/trace/trace_uprobe.o
CC crypto/algif_hash.o
CC drivers/char/tpm/tpm2-cmd.o
HOSTCC drivers/tty/vt/conmakehash
CC drivers/char/virtio_console.o
CC drivers/acpi/acpica/evxface.o
CC fs/ext4/xattr_trusted.o
CC net/bridge/br_stp_bpdu.o
CC [M] drivers/video/fbdev/core/tileblit.o
CC arch/x86/kernel/hw_breakpoint.o
CC crypto/algif_skcipher.o
CC drivers/char/tpm/tpmrm-dev.o
CC crypto/xor.o
CC [M] net/netfilter/xt_nat.o
CC drivers/pci/vgaarb.o
CC [M] arch/x86/kvm/vmx/nested.o
CC drivers/tty/serial/serial_mctrl_gpio.o
CC drivers/acpi/acpica/evxfevnt.o
CC drivers/tty/vt/vt.o
CC drivers/tty/serial/8250/8250_mid.o
CC drivers/virtio/virtio_pci_common.o
CC arch/x86/kernel/tsc.o
CC [M] drivers/gpu/drm/tests/drm_cmdline_parser_test.o
CC mm/mmap.o
CC [M] drivers/dma/ioat/sysfs.o
CC mm/mmu_gather.o
CC net/core/xdp.o
CC drivers/tty/serial/8250/8250_pericom.o
CC [M] net/netfilter/xt_REDIRECT.o
CC fs/btrfs/extent_map.o
CC [M] arch/x86/kvm/vmx/posted_intr.o
CC [M] drivers/gpu/drm/tests/drm_connector_test.o
CC [M] drivers/gpu/drm/display/drm_dp_helper.o
CC lib/kobject_uevent.o
CC [M] net/netfilter/xt_MASQUERADE.o
COPY drivers/tty/vt/defkeymap.c
CC drivers/virtio/virtio_pci_legacy.o
CC drivers/char/tpm/tpm2-space.o
CC [M] net/sunrpc/auth_gss/auth_gss.o
CC fs/ext4/xattr_user.o
CC net/sunrpc/clnt.o
CC [M] fs/smb/client/inode.o
CC [M] net/sunrpc/auth_gss/gss_generic_token.o
LD [M] arch/x86/kvm/kvm.o
CC drivers/acpi/acpica/evxfgpe.o
CC drivers/acpi/acpica/evxfregn.o
CC drivers/char/tpm/tpm-sysfs.o
CC [M] drivers/video/fbdev/core/cfbfillrect.o
CC drivers/iommu/intel/pasid.o
CC drivers/char/tpm/eventlog/common.o
CC net/ipv6/icmp.o
CC drivers/iommu/intel/trace.o
CC crypto/hash_info.o
CC net/sunrpc/xprt.o
CC drivers/acpi/acpica/exconcat.o
CC net/ipv6/mcast.o
CC crypto/simd.o
LD [M] drivers/dma/ioat/ioatdma.o
CC [M] drivers/gpu/drm/tests/drm_damage_helper_test.o
AR drivers/tty/serial/8250/built-in.a
CC drivers/dma/virt-dma.o
AR drivers/tty/serial/built-in.a
CC [M] drivers/video/fbdev/core/cfbcopyarea.o
CC net/core/flow_offload.o
CC [M] drivers/virtio/virtio_mem.o
CC net/bridge/br_stp_if.o
UPD arch/x86/kvm/kvm-asm-offsets.h
CC net/ipv4/tcp_cong.o
CC arch/x86/kernel/tsc_msr.o
CC drivers/video/hdmi.o
CC drivers/acpi/acpica/exconfig.o
CC net/ipv4/tcp_metrics.o
CC fs/ext4/fast_commit.o
CC [M] drivers/video/fbdev/core/cfbimgblt.o
AR drivers/pci/built-in.a
CC drivers/tty/tty_io.o
CC net/bridge/br_stp_timer.o
CC [M] fs/smb/client/link.o
AR drivers/virtio/built-in.a
CC drivers/char/hpet.o
CC arch/x86/kernel/io_delay.o
CC net/ipv6/reassembly.o
CC [M] net/netfilter/xt_addrtype.o
CC drivers/char/tpm/eventlog/tpm1.o
CC net/sunrpc/socklib.o
CC [M] drivers/gpu/drm/display/drm_dp_mst_topology.o
CC lib/logic_pio.o
CC mm/mprotect.o
CC net/bridge/br_netlink.o
CC drivers/acpi/acpica/exconvrt.o
CC kernel/trace/rethook.o
CC [M] crypto/md4.o
CC drivers/acpi/utils.o
CC [M] fs/smb/client/misc.o
CC [M] drivers/video/fbdev/core/sysfillrect.o
CC drivers/dma/acpi-dma.o
CC arch/x86/kernel/rtc.o
CC fs/inode.o
CC [M] net/netfilter/xt_conntrack.o
CC net/bridge/br_netlink_tunnel.o
CC kernel/kthread.o
CC drivers/iommu/intel/cap_audit.o
CC [M] drivers/video/fbdev/core/syscopyarea.o
CC net/ipv6/tcp_ipv6.o
CC fs/attr.o
CC drivers/acpi/reboot.o
CC drivers/acpi/acpica/excreate.o
CC [M] drivers/gpu/drm/tests/drm_dp_mst_helper_test.o
CC drivers/tty/n_tty.o
CC [M] crypto/ccm.o
CC drivers/char/tpm/eventlog/tpm2.o
CC lib/maple_tree.o
CC [M] drivers/gpu/drm/display/drm_dsc_helper.o
CC net/core/gro.o
CC fs/bad_inode.o
AR kernel/trace/built-in.a
CC kernel/sys_ni.o
CC drivers/acpi/nvs.o
CC drivers/char/nvram.o
CC arch/x86/kernel/resource.o
CC mm/mremap.o
AR drivers/dma/built-in.a
CC lib/memcat_p.o
CC drivers/connector/cn_queue.o
CC drivers/acpi/acpica/exdebug.o
CC drivers/connector/connector.o
AS arch/x86/kernel/irqflags.o
CC fs/ext4/orphan.o
CC drivers/acpi/wakeup.o
CC net/ipv6/ping.o
CC arch/x86/kernel/static_call.o
CC drivers/base/power/sysfs.o
CC net/sunrpc/xprtsock.o
CC arch/x86/kernel/process.o
CC [M] net/sunrpc/auth_gss/gss_mech_switch.o
CONMK drivers/tty/vt/consolemap_deftbl.c
CC drivers/tty/vt/defkeymap.o
CC [M] drivers/video/fbdev/core/sysimgblt.o
CC net/core/netdev-genl.o
CC drivers/acpi/acpica/exdump.o
CC [M] net/netfilter/xt_ipvs.o
CC drivers/char/tpm/tpm_ppi.o
CC net/ipv4/tcp_fastopen.o
CC [M] drivers/video/fbdev/core/fb_sys_fops.o
AS [M] arch/x86/kvm/vmx/vmenter.o
CC [M] drivers/gpu/drm/tests/drm_format_helper_test.o
CC drivers/base/power/generic_ops.o
CC [M] fs/smb/client/netmisc.o
CC drivers/iommu/intel/irq_remapping.o
CC [M] net/sunrpc/auth_gss/svcauth_gss.o
CC drivers/tty/vt/consolemap_deftbl.o
CC drivers/acpi/acpica/exfield.o
CC lib/nmi_backtrace.o
AR drivers/tty/vt/built-in.a
CC drivers/tty/tty_ioctl.o
CC [M] drivers/gpu/drm/tests/drm_format_test.o
CC drivers/base/power/common.o
CC kernel/nsproxy.o
CC net/bridge/br_arp_nd_proxy.o
CC [M] crypto/arc4.o
CC [M] net/sunrpc/auth_gss/gss_rpc_upcall.o
CC drivers/base/power/qos.o
CC drivers/acpi/acpica/exfldio.o
CC fs/btrfs/sysfs.o
CC net/sunrpc/sched.o
CC drivers/base/power/runtime.o
CC mm/msync.o
CC [M] crypto/ecc.o
CC fs/file.o
CC arch/x86/kernel/ptrace.o
CC [M] net/sunrpc/auth_gss/gss_rpc_xdr.o
CC mm/page_vma_mapped.o
CC drivers/connector/cn_proc.o
CC drivers/tty/tty_ldisc.o
CC kernel/notifier.o
CC drivers/char/tpm/eventlog/acpi.o
CC net/bridge/br_sysfs_if.o
AR drivers/gpu/drm/omapdrm/built-in.a
AR drivers/gpu/vga/built-in.a
CC drivers/base/power/wakeirq.o
AR drivers/gpu/drm/tilcdc/built-in.a
AR drivers/gpu/drm/imx/built-in.a
CC [M] fs/smb/client/smbencrypt.o
AR drivers/gpu/drm/i2c/built-in.a
AR fs/ext4/built-in.a
AR drivers/gpu/drm/panel/built-in.a
AR drivers/gpu/drm/hisilicon/built-in.a
AR drivers/gpu/drm/bridge/analogix/built-in.a
AR drivers/gpu/drm/bridge/cadence/built-in.a
AR drivers/gpu/drm/bridge/imx/built-in.a
AR drivers/gpu/drm/mxsfb/built-in.a
AR drivers/gpu/drm/tiny/built-in.a
CC [M] fs/smb/client/transport.o
AR drivers/gpu/drm/bridge/synopsys/built-in.a
CC [M] fs/smb/client/cached_dir.o
AR drivers/gpu/drm/bridge/built-in.a
AR drivers/gpu/drm/xlnx/built-in.a
CC [M] fs/smb/client/cifs_unicode.o
CC drivers/tty/tty_buffer.o
CC drivers/acpi/acpica/exmisc.o
CC mm/pagewalk.o
CC drivers/acpi/sleep.o
CC fs/filesystems.o
LD [M] drivers/video/fbdev/core/fb.o
AR drivers/video/fbdev/core/built-in.a
CC mm/pgtable-generic.o
AR drivers/video/fbdev/built-in.a
AR drivers/video/built-in.a
CC net/ipv6/exthdrs.o
CC drivers/block/loop.o
CC [M] drivers/gpu/drm/tests/drm_framebuffer_test.o
CC net/core/netdev-genl-gen.o
CC kernel/ksysfs.o
CC [M] drivers/gpu/drm/tests/drm_managed_test.o
LD [M] net/netfilter/nf_conntrack.o
CC [M] net/sunrpc/auth_gss/trace.o
LD [M] net/netfilter/nf_nat.o
AR net/netfilter/built-in.a
CC drivers/base/power/main.o
CC net/8021q/vlan_core.o
CC drivers/base/power/wakeup.o
CC [M] drivers/gpu/drm/tests/drm_mm_test.o
CC drivers/acpi/acpica/exmutex.o
CC net/dcb/dcbnl.o
CC [M] net/8021q/vlan.o
CC [M] drivers/gpu/drm/tests/drm_modes_test.o
CC drivers/char/tpm/eventlog/efi.o
CC net/l3mdev/l3mdev.o
CC net/handshake/genl.o
CC net/ipv4/tcp_rate.o
CC drivers/iommu/intel/perfmon.o
CC arch/x86/kernel/tls.o
CC drivers/char/tpm/tpm_crb.o
CC drivers/tty/tty_port.o
CC [M] fs/smb/client/nterr.o
CC [M] drivers/gpu/drm/tests/drm_plane_helper_test.o
CC kernel/cred.o
CC [M] drivers/gpu/drm/tests/drm_probe_helper_test.o
CC [M] fs/smb/client/cifsencrypt.o
CC mm/rmap.o
CC [M] drivers/gpu/drm/tests/drm_rect_test.o
CC kernel/reboot.o
CC net/core/gso.o
CC drivers/acpi/device_sysfs.o
AR drivers/gpu/drm/gud/built-in.a
CC [M] drivers/gpu/drm/display/drm_hdcp_helper.o
AR drivers/gpu/drm/solomon/built-in.a
AR drivers/connector/built-in.a
CC [M] drivers/gpu/drm/display/drm_hdmi_helper.o
CC net/core/net-sysfs.o
CC drivers/acpi/device_pm.o
CC drivers/acpi/acpica/exnames.o
CC mm/vmalloc.o
CC drivers/acpi/proc.o
CC arch/x86/kernel/step.o
CC net/bridge/br_sysfs_br.o
CC drivers/acpi/bus.o
CC lib/plist.o
CC net/ipv4/tcp_recovery.o
CC net/ipv6/datagram.o
CC net/handshake/netlink.o
CC lib/radix-tree.o
CC mm/page_alloc.o
CC drivers/acpi/acpica/exoparg1.o
CC [M] crypto/essiv.o
CC fs/btrfs/accessors.o
AR net/l3mdev/built-in.a
CC net/core/page_pool.o
CC [M] drivers/gpu/drm/tests/drm_exec_test.o
CC arch/x86/kernel/i8237.o
CC net/dcb/dcbevent.o
CC arch/x86/kernel/stacktrace.o
CC fs/btrfs/xattr.o
CC [M] drivers/gpu/drm/ttm/ttm_tt.o
CC drivers/tty/tty_mutex.o
CC arch/x86/kernel/reboot.o
AR drivers/char/tpm/built-in.a
CC [M] drivers/gpu/drm/scheduler/sched_main.o
AR drivers/char/built-in.a
CC drivers/acpi/glue.o
CC [M] drivers/gpu/drm/scheduler/sched_fence.o
CC [M] drivers/gpu/drm/display/drm_scdc_helper.o
CC [M] crypto/ecdh.o
LD [M] arch/x86/kvm/kvm-intel.o
CC [M] net/8021q/vlan_dev.o
CC kernel/async.o
CC arch/x86/kernel/msr.o
CC mm/init-mm.o
CC [M] drivers/gpu/drm/ttm/ttm_bo.o
CC net/ipv4/tcp_ulp.o
CC drivers/acpi/scan.o
CC [M] drivers/block/nbd.o
CC [M] crypto/ecdh_helper.o
CC [M] drivers/gpu/drm/scheduler/sched_entity.o
AR drivers/iommu/intel/built-in.a
AR drivers/iommu/arm/arm-smmu/built-in.a
AR drivers/iommu/arm/arm-smmu-v3/built-in.a
AR drivers/iommu/arm/built-in.a
CC drivers/acpi/acpica/exoparg2.o
CC fs/namespace.o
AR drivers/iommu/iommufd/built-in.a
CC drivers/iommu/iommu.o
CC arch/x86/kernel/cpuid.o
CC drivers/base/power/wakeup_stats.o
CC kernel/range.o
CC drivers/tty/tty_ldsem.o
CC [M] fs/smb/client/readdir.o
CC drivers/acpi/acpica/exoparg3.o
CC [M] net/8021q/vlan_netlink.o
CC net/ipv6/ip6_flowlabel.o
CC kernel/smpboot.o
CC drivers/acpi/acpica/exoparg6.o
CC kernel/ucount.o
CC drivers/tty/tty_baudrate.o
CC drivers/acpi/resource.o
LD [M] crypto/ecdh_generic.o
CC fs/btrfs/ordered-data.o
AR crypto/built-in.a
AR net/dcb/built-in.a
CC fs/btrfs/extent_io.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_drv.o
AR drivers/block/built-in.a
CC fs/btrfs/volumes.o
CC [M] fs/smb/client/ioctl.o
CC [M] net/sunrpc/auth_gss/gss_krb5_mech.o
CC [M] net/sunrpc/auth_gss/gss_krb5_seal.o
CC [M] drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.o
CC drivers/acpi/acpi_processor.o
CC drivers/base/power/domain.o
CC drivers/acpi/processor_core.o
CC [M] fs/smb/client/sess.o
CC net/handshake/request.o
CC [M] drivers/gpu/drm/display/drm_dp_aux_dev.o
CC net/bridge/br_nf_core.o
CC kernel/regset.o
CC [M] net/bluetooth/af_bluetooth.o
CC net/sunrpc/auth.o
CC net/bridge/br_multicast.o
CC arch/x86/kernel/early-quirks.o
CC drivers/acpi/acpica/exprep.o
CC fs/btrfs/async-thread.o
CC [M] net/dns_resolver/dns_key.o
CC net/core/net-procfs.o
CC [M] net/dns_resolver/dns_query.o
CC lib/ratelimit.o
LD [M] drivers/gpu/drm/amd/amdxcp/amdxcp.o
CC lib/rbtree.o
CC kernel/ksyms_common.o
CC [M] net/8021q/vlanproc.o
CC net/handshake/tlshd.o
CC drivers/tty/tty_jobctrl.o
CC arch/x86/kernel/smp.o
CC fs/btrfs/ioctl.o
CC lib/seq_buf.o
CC [M] drivers/gpu/drm/ttm/ttm_bo_util.o
LD [M] drivers/gpu/drm/scheduler/gpu-sched.o
CC net/ipv4/tcp_offload.o
CC net/devres.o
CC net/handshake/trace.o
CC [M] net/bluetooth/hci_core.o
CC fs/btrfs/locking.o
CC [M] drivers/gpu/drm/i915/i915_driver.o
CC lib/siphash.o
CC drivers/acpi/acpica/exregion.o
CC kernel/groups.o
CC [M] net/sunrpc/auth_gss/gss_krb5_unseal.o
CC lib/string.o
CC net/ipv6/inet6_connection_sock.o
LD [M] drivers/gpu/drm/display/drm_display_helper.o
CC kernel/vhost_task.o
AR drivers/misc/eeprom/built-in.a
AR drivers/misc/cb710/built-in.a
AR drivers/misc/ti-st/built-in.a
AR drivers/misc/lis3lv02d/built-in.a
AR drivers/misc/cardreader/built-in.a
AR drivers/misc/built-in.a
CC [M] drivers/misc/mei/hdcp/mei_hdcp.o
CC [M] drivers/misc/mei/pxp/mei_pxp.o
CC [M] drivers/gpu/drm/vgem/vgem_drv.o
LD [M] net/dns_resolver/dns_resolver.o
CC [M] drivers/gpu/drm/vgem/vgem_fence.o
CC net/socket.o
CC fs/seq_file.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_device.o
CC drivers/acpi/acpica/exresnte.o
CC [M] drivers/gpu/drm/xe/tests/xe_bo_test.o
CC fs/xattr.o
CC drivers/tty/n_null.o
CC fs/btrfs/orphan.o
CC net/core/netpoll.o
AR net/8021q/built-in.a
LD [M] net/8021q/8021q.o
CC net/compat.o
CC drivers/acpi/processor_pdc.o
CC drivers/acpi/ec.o
CC [M] drivers/gpu/drm/xe/xe_bb.o
CC kernel/kcmp.o
CC net/core/fib_rules.o
CC drivers/acpi/dock.o
CC arch/x86/kernel/smpboot.o
CC lib/timerqueue.o
CC [M] net/sunrpc/auth_gss/gss_krb5_seqnum.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell_mgr.o
CC [M] drivers/gpu/drm/ttm/ttm_bo_vm.o
CC drivers/acpi/pci_root.o
CC [M] fs/smb/client/export.o
CC [M] drivers/misc/mei/init.o
CC drivers/iommu/iommu-traces.o
CC [M] drivers/gpu/drm/xe/tests/xe_dma_buf_test.o
CC drivers/acpi/acpica/exresolv.o
CC drivers/base/power/domain_governor.o
CC lib/vsprintf.o
CC drivers/tty/pty.o
CC fs/btrfs/export.o
CC [M] drivers/gpu/drm/xe/tests/xe_migrate_test.o
LD [M] drivers/gpu/drm/vgem/vgem.o
CC [M] drivers/gpu/drm/xe/xe_bo.o
CC mm/memblock.o
AR net/handshake/built-in.a
CC [M] drivers/misc/mei/hbm.o
CC lib/win_minmax.o
CC net/ipv4/tcp_plb.o
CC drivers/acpi/pci_link.o
CC mm/memory_hotplug.o
CC net/sysctl_net.o
CC [M] drivers/gpu/drm/xe/tests/xe_pci_test.o
CC [M] drivers/gpu/drm/xe/xe_bo_evict.o
CC net/ipv6/udp_offload.o
CC [M] drivers/gpu/drm/ttm/ttm_module.o
CC drivers/acpi/acpica/exresop.o
CC drivers/mfd/mfd-core.o
CC [M] net/sunrpc/auth_gss/gss_krb5_wrap.o
CC [M] drivers/gpu/drm/nouveau/nvif/object.o
CC drivers/base/power/clock_ops.o
AR drivers/nfc/built-in.a
CC [M] net/sunrpc/auth_gss/gss_krb5_crypto.o
CC kernel/freezer.o
CC [M] drivers/gpu/drm/i915/i915_drm_client.o
CC mm/madvise.o
CC drivers/iommu/iommu-sysfs.o
CC net/ipv6/seg6.o
CC [M] drivers/gpu/drm/xe/xe_debugfs.o
AR drivers/dax/hmem/built-in.a
CC drivers/dax/super.o
CC [M] drivers/gpu/drm/ttm/ttm_execbuf_util.o
CC [M] fs/smb/client/unc.o
CC drivers/acpi/pci_irq.o
CC fs/libfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_kms.o
CC drivers/tty/sysrq.o
CC drivers/dax/bus.o
CC [M] drivers/misc/mei/interrupt.o
CC drivers/acpi/acpica/exserial.o
CC drivers/acpi/acpica/exstore.o
CC [M] drivers/gpu/drm/xe/tests/xe_rtp_test.o
AR drivers/base/power/built-in.a
CC arch/x86/kernel/tsc_sync.o
CC fs/fs-writeback.o
CC drivers/base/firmware_loader/builtin/main.o
CC fs/pnode.o
CC [M] net/sunrpc/auth_gss/gss_krb5_keys.o
CC drivers/base/firmware_loader/main.o
CC fs/btrfs/tree-log.o
LD [M] net/sunrpc/auth_gss/auth_rpcgss.o
CC drivers/iommu/dma-iommu.o
CC [M] drivers/gpu/drm/xe/tests/xe_wa_test.o
CC [M] fs/smb/client/winucase.o
CC drivers/mfd/intel-lpss.o
CC drivers/iommu/iova.o
CC [M] fs/smb/client/smb2ops.o
CC kernel/stacktrace.o
CC lib/xarray.o
CC drivers/base/regmap/regmap.o
CC [M] drivers/gpu/drm/nouveau/nvif/client.o
AR drivers/base/test/built-in.a
CC drivers/base/component.o
CC [M] drivers/gpu/drm/ttm/ttm_range_manager.o
CC drivers/acpi/acpica/exstoren.o
CC net/ipv4/datagram.o
CC drivers/dma-buf/dma-buf.o
CC net/core/net-traces.o
CC drivers/dma-buf/dma-fence.o
CC net/ipv6/fib6_notifier.o
AR drivers/base/firmware_loader/builtin/built-in.a
CC net/ipv4/raw.o
CC [M] drivers/gpu/drm/i915/i915_config.o
CC drivers/acpi/acpica/exstorob.o
CC net/core/selftests.o
CC drivers/dma-buf/dma-fence-array.o
CC net/ipv6/rpl.o
CC net/ipv6/ioam6.o
CC arch/x86/kernel/setup_percpu.o
CC [M] drivers/misc/mei/client.o
AR drivers/tty/built-in.a
AR drivers/cxl/core/built-in.a
AR drivers/cxl/built-in.a
CC mm/page_io.o
AR drivers/macintosh/built-in.a
CC mm/swap_state.o
CC [M] drivers/gpu/drm/i915/i915_getparam.o
CC fs/btrfs/free-space-cache.o
CC drivers/dma-buf/dma-fence-chain.o
CC drivers/mfd/intel-lpss-pci.o
CC [M] fs/smb/client/smb2maperror.o
CC kernel/dma.o
CC [M] drivers/gpu/drm/i915/i915_ioctl.o
CC drivers/dma-buf/dma-fence-unwrap.o
CC drivers/dma-buf/dma-resv.o
CC drivers/acpi/acpica/exsystem.o
CC [M] drivers/gpu/drm/ttm/ttm_resource.o
CC net/core/ptp_classifier.o
CC fs/splice.o
LD [M] net/sunrpc/auth_gss/rpcsec_gss_krb5.o
AR drivers/dax/built-in.a
CC net/sunrpc/auth_null.o
CC drivers/mfd/intel-lpss-acpi.o
CC [M] drivers/gpu/drm/xe/xe_devcoredump.o
CC net/core/netprio_cgroup.o
CC [M] drivers/gpu/drm/nouveau/nvif/conn.o
CC net/ipv6/sysctl_net_ipv6.o
CC drivers/iommu/irq_remapping.o
CC [M] net/bluetooth/hci_conn.o
CC [M] drivers/gpu/drm/xe/xe_device.o
AR drivers/base/firmware_loader/built-in.a
CC drivers/base/core.o
CC arch/x86/kernel/ftrace.o
CC net/ipv6/xfrm6_policy.o
CC kernel/smp.o
CC drivers/acpi/acpica/extrace.o
CC net/core/dst_cache.o
CC drivers/scsi/scsi.o
CC lib/lockref.o
CC drivers/acpi/acpica/exutils.o
CC net/core/gro_cells.o
CC drivers/mfd/intel_soc_pmic_crc.o
CC kernel/uid16.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.o
CC lib/bcd.o
CC [M] drivers/gpu/drm/i915/i915_irq.o
CC drivers/scsi/hosts.o
CC drivers/dma-buf/sync_file.o
CC drivers/acpi/acpica/hwacpi.o
AS arch/x86/kernel/ftrace_64.o
AR drivers/iommu/built-in.a
CC drivers/base/bus.o
CC drivers/nvme/host/core.o
CC drivers/nvme/host/ioctl.o
AR drivers/nvme/target/built-in.a
CC [M] drivers/gpu/drm/i915/i915_mitigations.o
CC [M] drivers/gpu/drm/xe/xe_device_sysfs.o
CC drivers/nvme/host/sysfs.o
CC lib/sort.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_crtc.o
CC [M] drivers/gpu/drm/nouveau/nvif/device.o
CC [M] drivers/gpu/drm/i915/i915_module.o
CC net/bridge/br_mdb.o
CC [M] drivers/gpu/drm/xe/xe_dma_buf.o
CC [M] net/bluetooth/hci_event.o
CC [M] drivers/gpu/drm/ttm/ttm_pool.o
CC lib/parser.o
CC [M] drivers/gpu/drm/nouveau/nvif/disp.o
CC net/sunrpc/auth_tls.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.o
CC [M] net/bluetooth/mgmt.o
CC drivers/nvme/host/pr.o
CC [M] drivers/gpu/drm/ttm/ttm_device.o
CC mm/swapfile.o
CC arch/x86/kernel/trace_clock.o
CC [M] fs/smb/client/smb2transport.o
CC drivers/acpi/acpica/hwesleep.o
CC net/ipv4/udp.o
CC [M] drivers/gpu/drm/amd/amdgpu/atom.o
CC arch/x86/kernel/trace.o
CC [M] drivers/mfd/lpc_sch.o
CC drivers/dma-buf/sw_sync.o
CC lib/debug_locks.o
CC lib/random32.o
CC [M] drivers/gpu/drm/ttm/ttm_sys_manager.o
CC drivers/acpi/acpi_lpss.o
CC net/sunrpc/auth_unix.o
CC net/ipv6/xfrm6_state.o
CC mm/swap_slots.o
CC [M] fs/smb/client/smb2misc.o
CC drivers/dma-buf/sync_debug.o
CC drivers/nvme/host/trace.o
CC [M] drivers/misc/mei/main.o
CC net/sunrpc/svc.o
CC drivers/acpi/acpica/hwgpe.o
CC net/ipv6/xfrm6_input.o
CC kernel/kallsyms.o
CC arch/x86/kernel/rethook.o
CC [M] drivers/gpu/drm/ttm/ttm_agp_backend.o
CC fs/btrfs/zlib.o
CC lib/bust_spinlocks.o
CC [M] drivers/gpu/drm/nouveau/nvif/driver.o
CC drivers/scsi/scsi_ioctl.o
CC drivers/base/dd.o
CC drivers/acpi/acpi_apd.o
CC drivers/gpu/drm/drm_mipi_dsi.o
CC [M] drivers/gpu/drm/xe/xe_exec.o
CC [M] drivers/gpu/drm/ast/ast_drv.o
CC [M] drivers/gpu/drm/xe/xe_execlist.o
CC [M] drivers/gpu/drm/ast/ast_i2c.o
CC [M] drivers/mfd/lpc_ich.o
CC drivers/acpi/acpi_platform.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fence.o
CC fs/sync.o
CC [M] drivers/dma-buf/selftest.o
CC drivers/base/regmap/regcache.o
CC drivers/acpi/acpica/hwregs.o
CC drivers/scsi/scsicam.o
CC [M] drivers/gpu/drm/i915/i915_params.o
CC mm/dmapool.o
CC arch/x86/kernel/crash_core_64.o
CC lib/kasprintf.o
LD [M] drivers/gpu/drm/ttm/ttm.o
CC [M] drivers/gpu/drm/xe/xe_exec_queue.o
CC [M] drivers/gpu/drm/drm_aperture.o
CC net/sunrpc/svcsock.o
CC drivers/acpi/acpica/hwsleep.o
CC fs/utimes.o
CC mm/hugetlb.o
CC [M] drivers/gpu/drm/nouveau/nvif/event.o
CC drivers/acpi/acpi_pnp.o
CC [M] drivers/misc/mei/dma-ring.o
CC [M] drivers/gpu/drm/i915/i915_pci.o
CC [M] drivers/dma-buf/st-dma-fence.o
CC [M] drivers/gpu/drm/xe/xe_force_wake.o
CC arch/x86/kernel/module.o
CC lib/bitmap.o
CC drivers/acpi/acpica/hwvalid.o
CC [M] drivers/gpu/drm/i915/i915_scatterlist.o
CC [M] drivers/gpu/drm/ast/ast_main.o
CC drivers/acpi/acpica/hwxface.o
CC net/bridge/br_multicast_eht.o
CC fs/d_path.o
CC [M] fs/smb/client/smb2pdu.o
CC drivers/scsi/scsi_error.o
AR drivers/mfd/built-in.a
CC [M] drivers/gpu/drm/drm_atomic.o
CC [M] drivers/gpu/drm/ast/ast_mm.o
CC drivers/acpi/acpica/hwxfsleep.o
CC net/bridge/br_vlan.o
CC drivers/scsi/scsi_lib.o
CC drivers/base/syscore.o
CC kernel/acct.o
CC [M] drivers/gpu/drm/drm_atomic_uapi.o
CC arch/x86/kernel/early_printk.o
CC net/ipv6/xfrm6_output.o
CC lib/scatterlist.o
CC [M] drivers/dma-buf/st-dma-fence-chain.o
CC [M] drivers/gpu/drm/ast/ast_mode.o
CC kernel/crash_core.o
CC fs/btrfs/lzo.o
CC [M] fs/smb/client/smb2inode.o
CC drivers/base/regmap/regcache-rbtree.o
CC [M] drivers/gpu/drm/drm_auth.o
CC [M] drivers/gpu/drm/ast/ast_post.o
CC net/ipv6/xfrm6_protocol.o
CC drivers/acpi/acpica/hwpci.o
CC [M] drivers/dma-buf/st-dma-fence-unwrap.o
CC [M] drivers/misc/mei/bus.o
CC lib/list_sort.o
CC arch/x86/kernel/hpet.o
CC [M] drivers/gpu/drm/nouveau/nvif/fifo.o
CC drivers/acpi/power.o
CC net/ipv6/netfilter.o
CC [M] fs/smb/client/smb2file.o
CC drivers/acpi/acpica/nsaccess.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.o
CC [M] drivers/gpu/drm/xe/xe_ggtt.o
CC [M] drivers/gpu/drm/i915/i915_suspend.o
CC drivers/acpi/acpica/nsalloc.o
CC fs/stack.o
CC arch/x86/kernel/amd_nb.o
CC drivers/acpi/event.o
CC drivers/acpi/acpica/nsarguments.o
CC kernel/compat.o
AR net/core/built-in.a
CC [M] drivers/dma-buf/st-dma-resv.o
CC net/ipv6/fib6_rules.o
CC arch/x86/kernel/kvm.o
CC [M] drivers/gpu/drm/i915/i915_switcheroo.o
CC drivers/ata/libata-core.o
CC drivers/base/driver.o
CC drivers/base/regmap/regcache-flat.o
CC drivers/ata/libata-scsi.o
CC lib/uuid.o
CC drivers/acpi/acpica/nsconvert.o
CC [M] drivers/gpu/drm/xe/xe_gt.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_object.o
CC lib/iov_iter.o
CC drivers/base/class.o
CC drivers/nvme/host/fault_inject.o
CC drivers/base/regmap/regcache-maple.o
CC lib/clz_ctz.o
CC [M] drivers/gpu/drm/xe/xe_gt_clock.o
CC drivers/acpi/acpica/nsdump.o
CC [M] drivers/gpu/drm/nouveau/nvif/head.o
CC drivers/nvme/host/pci.o
CC fs/fs_struct.o
CC drivers/base/regmap/regmap-debugfs.o
CC drivers/acpi/acpica/nseval.o
CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o
CC drivers/acpi/evged.o
CC fs/btrfs/zstd.o
AR drivers/dma-buf/built-in.a
LD [M] drivers/dma-buf/dmabuf_selftests.o
CC [M] fs/smb/client/cifsacl.o
CC mm/hugetlb_vmemmap.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gart.o
CC [M] drivers/misc/mei/bus-fixup.o
CC fs/btrfs/compression.o
CC [M] fs/smb/client/fs_context.o
CC [M] drivers/gpu/drm/xe/xe_gt_idle_sysfs.o
CC drivers/acpi/acpica/nsinit.o
CC fs/statfs.o
CC drivers/acpi/sysfs.o
CC kernel/utsname.o
CC net/ipv4/udplite.o
CC kernel/user_namespace.o
CC net/ipv6/proc.o
CC [M] drivers/misc/mei/debugfs.o
CC drivers/acpi/acpica/nsload.o
CC [M] drivers/gpu/drm/ast/ast_dp501.o
CC [M] drivers/misc/mei/mei-trace.o
CC net/ipv6/syncookies.o
CC drivers/scsi/scsi_lib_dma.o
CC fs/btrfs/delayed-ref.o
CC fs/fs_pin.o
CC fs/nsfs.o
CC [M] drivers/gpu/drm/i915/i915_sysfs.o
CC drivers/base/platform.o
CC [M] drivers/gpu/drm/nouveau/nvif/mem.o
CC drivers/acpi/acpica/nsnames.o
CC fs/btrfs/relocation.o
CC [M] drivers/misc/mei/pci-me.o
CC mm/mempolicy.o
CC drivers/base/cpu.o
CC drivers/base/regmap/regmap-i2c.o
CC net/sunrpc/svcauth.o
CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o
CC drivers/spi/spi.o
CC fs/btrfs/delayed-inode.o
CC drivers/acpi/acpica/nsobject.o
CC arch/x86/kernel/kvmclock.o
CC [M] drivers/gpu/drm/i915/i915_utils.o
CC fs/fs_types.o
CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o
CC drivers/base/firmware.o
CC drivers/acpi/property.o
CC fs/btrfs/scrub.o
CC fs/fs_context.o
CC net/sunrpc/svcauth_unix.o
CC drivers/scsi/scsi_scan.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.o
CC net/ipv6/mip6.o
CC [M] fs/smb/client/dns_resolve.o
CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o
CC net/ipv4/udp_offload.o
CC drivers/acpi/acpica/nsparse.o
CC net/bridge/br_vlan_tunnel.o
CC [M] drivers/gpu/drm/ast/ast_dp.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_display.o
CC net/ipv6/addrconf_core.o
CC kernel/pid_namespace.o
CC [M] drivers/misc/mei/hw-me.o
CC drivers/base/init.o
CC fs/btrfs/backref.o
CC drivers/acpi/acpica/nspredef.o
CC [M] drivers/gpu/drm/i915/intel_clock_gating.o
CC [M] drivers/gpu/drm/nouveau/nvif/mmu.o
CC net/ipv6/exthdrs_core.o
CC drivers/base/regmap/regmap-irq.o
CC arch/x86/kernel/paravirt.o
CC [M] drivers/gpu/drm/i915/intel_device_info.o
CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
CC drivers/acpi/acpica/nsprepkg.o
CC fs/fs_parser.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.o
CC arch/x86/kernel/pvclock.o
CC net/ipv4/arp.o
CC [M] drivers/gpu/drm/drm_blend.o
CC drivers/ata/libata-eh.o
CC net/ipv6/ip6_checksum.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gem.o
CC fs/btrfs/ulist.o
CC fs/fsopen.o
CC arch/x86/kernel/pcspeaker.o
CC [M] drivers/gpu/drm/i915/intel_memory_region.o
CC drivers/ata/libata-transport.o
CC [M] net/bluetooth/hci_sock.o
CC [M] drivers/gpu/drm/drm_bridge.o
CC drivers/acpi/acpica/nsrepair.o
LD [M] drivers/gpu/drm/ast/ast.o
UPD kernel/config_data
CC kernel/stop_machine.o
CC [M] drivers/gpu/drm/nouveau/nvif/outp.o
CC lib/bsearch.o
CC net/ipv6/ip6_icmp.o
ASN.1 fs/smb/client/cifs_spnego_negtokeninit.asn1.[ch]
CC [M] fs/smb/client/smb1ops.o
CC [M] drivers/gpu/drm/drm_cache.o
AR drivers/nvme/host/built-in.a
AR drivers/nvme/built-in.a
CC [M] net/bluetooth/hci_sysfs.o
CC [M] drivers/gpu/drm/xe/xe_gt_topology.o
CC drivers/base/map.o
CC [M] drivers/gpu/drm/i915/intel_pcode.o
GEN drivers/scsi/scsi_devinfo_tbl.c
CC drivers/scsi/scsi_devinfo.o
CC [M] drivers/gpu/drm/drm_client.o
CC [M] drivers/gpu/drm/nouveau/nvif/timer.o
CC arch/x86/kernel/check.o
CC net/ipv4/icmp.o
CC net/ipv6/output_core.o
CC [M] drivers/gpu/drm/drm_client_modeset.o
CC drivers/acpi/acpica/nsrepair2.o
CC net/ipv4/devinet.o
AR drivers/base/regmap/built-in.a
CC mm/sparse.o
CC lib/find_bit.o
CC net/bridge/br_vlan_options.o
CC drivers/net/phy/mdio-boardinfo.o
AR drivers/firewire/built-in.a
CC lib/llist.o
CC drivers/base/devres.o
CC [M] drivers/gpu/drm/drm_color_mgmt.o
AR drivers/net/pse-pd/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ring.o
CC net/bridge/br_mst.o
CC drivers/acpi/acpica/nssearch.o
CC lib/memweight.o
CC net/ipv4/af_inet.o
HOSTCC drivers/gpu/drm/xe/xe_gen_wa_oob
CC [M] fs/smb/client/cifssmb.o
CC drivers/acpi/acpica/nsutils.o
CC [M] drivers/misc/mei/gsc-me.o
CC kernel/kprobes.o
CC net/ipv4/igmp.o
CC lib/kfifo.o
CC net/ipv6/protocol.o
CC drivers/acpi/acpica/nswalk.o
CC kernel/hung_task.o
CC net/ipv6/ip6_offload.o
CC lib/percpu-refcount.o
CC fs/init.o
CC kernel/watchdog.o
CC arch/x86/kernel/uprobes.o
CC net/sunrpc/addr.o
CC [M] drivers/gpu/drm/xe/xe_guc_ads.o
CC [M] fs/smb/client/cifs_spnego_negtokeninit.asn1.o
CC drivers/scsi/scsi_sysctl.o
CC [M] net/bluetooth/l2cap_core.o
CC lib/rhashtable.o
CC fs/kernel_read_file.o
CC fs/btrfs/qgroup.o
CC [M] drivers/gpu/drm/nouveau/nvif/vmm.o
CC drivers/ata/libata-trace.o
CC [M] net/bridge/br_netfilter_hooks.o
AR drivers/cdrom/built-in.a
AR drivers/auxdisplay/built-in.a
CC drivers/usb/common/common.o
CC drivers/usb/core/usb.o
AR drivers/usb/phy/built-in.a
CC [M] drivers/gpu/drm/i915/intel_region_ttm.o
CC drivers/net/phy/mdio_devres.o
CC drivers/acpi/acpica/nsxfeval.o
CC drivers/usb/core/hub.o
CC lib/base64.o
CC [M] net/bridge/br_netfilter_ipv6.o
CC [M] drivers/gpu/drm/drm_connector.o
CC mm/sparse-vmemmap.o
CC drivers/acpi/acpica/nsxfname.o
CC drivers/base/attribute_container.o
CC drivers/usb/core/hcd.o
LD [M] drivers/misc/mei/mei.o
AR drivers/spi/built-in.a
CC arch/x86/kernel/perf_regs.o
CC drivers/scsi/scsi_debugfs.o
CC net/ipv6/tcpv6_offload.o
LD [M] drivers/misc/mei/mei-me.o
CC mm/mmu_notifier.o
CC drivers/base/transport_class.o
LD [M] drivers/misc/mei/mei-gsc.o
CC drivers/usb/core/urb.o
CC drivers/input/serio/serio.o
CC drivers/input/keyboard/atkbd.o
CC drivers/net/mdio/acpi_mdio.o
AR drivers/net/pcs/built-in.a
CC arch/x86/kernel/tracepoint.o
CC drivers/usb/core/message.o
CC drivers/net/mdio/fwnode_mdio.o
CC kernel/watchdog_perf.o
CC fs/mnt_idmapping.o
CC [M] drivers/gpu/drm/drm_crtc.o
CC [M] fs/smb/client/asn1.o
CC net/sunrpc/rpcb_clnt.o
CC net/ipv6/exthdrs_offload.o
CC kernel/seccomp.o
CC drivers/usb/common/debug.o
CC drivers/rtc/lib.o
AR drivers/i2c/algos/built-in.a
AR drivers/i3c/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvif/user.o
CC [M] drivers/i2c/algos/i2c-algo-bit.o
CC [M] drivers/gpu/drm/nouveau/nvif/userc361.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_cs.o
CC drivers/net/phy/phy.o
CC drivers/acpi/acpica/nsxfobj.o
CC drivers/i2c/busses/i2c-designware-common.o
AR drivers/usb/common/built-in.a
CC drivers/base/topology.o
CC drivers/base/container.o
CC drivers/i2c/busses/i2c-designware-master.o
CC net/ipv6/inet6_hashtables.o
CC drivers/scsi/scsi_trace.o
CC drivers/acpi/acpica/psargs.o
CC arch/x86/kernel/itmt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/client.o
CC [M] drivers/gpu/drm/i915/intel_runtime_pm.o
CC net/ipv6/mcast_snoop.o
CC [M] drivers/gpu/drm/xe/xe_guc_ct.o
CC lib/once.o
CC fs/remap_range.o
CC drivers/input/serio/i8042.o
CC drivers/scsi/scsi_logging.o
CC net/ipv4/fib_frontend.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/engine.o
CC [M] net/ipv6/ip6_udp_tunnel.o
CC mm/ksm.o
AR drivers/net/mdio/built-in.a
CC drivers/usb/core/driver.o
CC drivers/ata/libata-sata.o
CC drivers/input/serio/libps2.o
CC drivers/rtc/class.o
CC drivers/scsi/scsi_pm.o
AR net/bridge/built-in.a
CC drivers/scsi/scsi_bsg.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/enum.o
CC drivers/base/property.o
CC fs/buffer.o
CC mm/slub.o
AR drivers/input/keyboard/built-in.a
AR drivers/input/mouse/built-in.a
CC drivers/input/input.o
CC drivers/acpi/acpica/psloop.o
CC drivers/scsi/scsi_common.o
CC drivers/input/input-compat.o
CC lib/refcount.o
CC drivers/net/phy/phy-c45.o
CC lib/rcuref.o
CC arch/x86/kernel/umip.o
CC fs/mpage.o
CC mm/migrate.o
CC kernel/relay.o
CC drivers/i2c/busses/i2c-designware-platdrv.o
CC drivers/base/cacheinfo.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_bios.o
CC drivers/net/phy/phy-core.o
CC fs/proc_namespace.o
CC lib/usercopy.o
CC drivers/i2c/busses/i2c-designware-baytrail.o
CC kernel/utsname_sysctl.o
CC drivers/base/swnode.o
CC drivers/rtc/interface.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.o
LD [M] net/bridge/br_netfilter.o
AR drivers/net/ethernet/adi/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_dp.o
CC drivers/scsi/sd.o
CC drivers/scsi/sg.o
AR drivers/net/ethernet/alacritech/built-in.a
CC drivers/acpi/acpica/psobject.o
CC drivers/acpi/acpica/psopcode.o
AR drivers/net/ethernet/amazon/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/core/event.o
AR drivers/net/ethernet/aquantia/built-in.a
AR drivers/net/ethernet/asix/built-in.a
AR drivers/net/ethernet/cadence/built-in.a
AR drivers/net/ethernet/broadcom/built-in.a
CC drivers/acpi/acpica/psopinfo.o
CC drivers/input/input-mt.o
CC [M] drivers/net/ethernet/broadcom/b44.o
AR drivers/i2c/muxes/built-in.a
CC [M] drivers/i2c/muxes/i2c-mux-gpio.o
CC lib/errseq.o
CC [M] drivers/net/ethernet/broadcom/bnx2.o
CC [M] drivers/gpu/drm/i915/intel_sbi.o
CC drivers/i2c/i2c-boardinfo.o
AR drivers/net/usb/built-in.a
CC [M] drivers/net/usb/pegasus.o
CC lib/bucket_locks.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/firmware.o
CC arch/x86/kernel/unwind_orc.o
AR net/ipv6/built-in.a
CC drivers/i2c/i2c-core-base.o
CC kernel/delayacct.o
CC net/sunrpc/timer.o
CC drivers/ata/libata-sff.o
CC drivers/usb/host/pci-quirks.o
AR drivers/input/serio/built-in.a
CC drivers/usb/host/ehci-hcd.o
CC drivers/usb/storage/scsiglue.o
CC drivers/usb/host/ehci-pci.o
CC drivers/usb/storage/protocol.o
AR drivers/media/i2c/built-in.a
AR drivers/ptp/built-in.a
CC drivers/acpi/acpica/psparse.o
CC [M] drivers/ptp/ptp_clock.o
AR drivers/media/tuners/built-in.a
AR drivers/media/rc/keymaps/built-in.a
AR drivers/media/rc/built-in.a
CC [M] drivers/ptp/ptp_chardev.o
AR drivers/media/common/b2c2/built-in.a
AR drivers/media/common/saa7146/built-in.a
AR drivers/media/common/siano/built-in.a
AR drivers/media/common/v4l2-tpg/built-in.a
CC [M] drivers/i2c/busses/i2c-scmi.o
AR drivers/media/common/videobuf2/built-in.a
AR drivers/media/common/built-in.a
AR drivers/media/platform/allegro-dvt/built-in.a
AR drivers/media/platform/amlogic/meson-ge2d/built-in.a
AR drivers/media/platform/amlogic/built-in.a
AR drivers/media/platform/amphion/built-in.a
CC [M] drivers/ptp/ptp_sysfs.o
AR drivers/media/platform/aspeed/built-in.a
CC [M] drivers/ptp/ptp_vclock.o
AR drivers/media/platform/atmel/built-in.a
CC drivers/scsi/scsi_sysfs.o
CC drivers/i2c/i2c-core-smbus.o
AR drivers/media/platform/cadence/built-in.a
AR drivers/media/platform/chips-media/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o
AR drivers/media/platform/intel/built-in.a
AR drivers/media/platform/marvell/built-in.a
CC lib/generic-radix-tree.o
CC drivers/net/phy/phy_device.o
AR drivers/media/platform/mediatek/jpeg/built-in.a
AR drivers/media/platform/mediatek/mdp/built-in.a
AR drivers/media/platform/mediatek/vcodec/built-in.a
CC drivers/base/auxiliary.o
CC [M] drivers/i2c/busses/i2c-ccgx-ucsi.o
AR drivers/media/platform/mediatek/vpu/built-in.a
CC drivers/usb/core/config.o
AR drivers/media/platform/mediatek/mdp3/built-in.a
AR drivers/media/platform/mediatek/built-in.a
AR drivers/media/platform/microchip/built-in.a
CC kernel/taskstats.o
AR drivers/media/platform/nvidia/tegra-vde/built-in.a
AR drivers/media/platform/nvidia/built-in.a
CC [M] drivers/net/usb/rtl8150.o
AR drivers/media/platform/nxp/dw100/built-in.a
CC fs/btrfs/send.o
CC drivers/acpi/acpica/psscope.o
AR drivers/media/platform/nxp/imx-jpeg/built-in.a
CC drivers/usb/storage/transport.o
AR drivers/media/platform/nxp/imx8-isi/built-in.a
AR drivers/media/platform/nxp/built-in.a
CC drivers/acpi/acpica/pstree.o
AR drivers/media/platform/qcom/camss/built-in.a
AR drivers/media/platform/qcom/venus/built-in.a
AR drivers/media/platform/qcom/built-in.a
AR drivers/media/platform/renesas/rcar-vin/built-in.a
AR drivers/media/platform/renesas/rzg2l-cru/built-in.a
AR drivers/media/platform/renesas/vsp1/built-in.a
AR drivers/media/platform/renesas/built-in.a
AR drivers/media/platform/rockchip/rga/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.o
AR drivers/media/platform/rockchip/rkisp1/built-in.a
AR drivers/media/platform/rockchip/built-in.a
AR drivers/media/platform/samsung/exynos-gsc/built-in.a
CC arch/x86/kernel/callthunks.o
CC [M] drivers/gpu/drm/i915/intel_step.o
AR drivers/media/platform/samsung/exynos4-is/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/core/gpuobj.o
AR drivers/media/platform/samsung/s3c-camif/built-in.a
CC drivers/input/input-poller.o
AR drivers/media/platform/samsung/s5p-g2d/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/core/intr.o
CC drivers/acpi/acpica/psutils.o
AR drivers/media/platform/samsung/s5p-jpeg/built-in.a
AR drivers/media/platform/samsung/s5p-mfc/built-in.a
AR drivers/media/platform/samsung/built-in.a
CC [M] drivers/i2c/busses/i2c-i801.o
CC net/ipv4/fib_semantics.o
CC lib/string_helpers.o
AR drivers/media/platform/st/sti/bdisp/built-in.a
AR drivers/media/platform/st/sti/c8sectpfe/built-in.a
AR drivers/media/platform/st/sti/delta/built-in.a
AR drivers/media/platform/st/sti/hva/built-in.a
CC net/sunrpc/xdr.o
AR drivers/media/platform/st/stm32/built-in.a
AR drivers/media/platform/st/built-in.a
AR drivers/media/platform/sunxi/sun4i-csi/built-in.a
AR drivers/media/platform/sunxi/sun6i-csi/built-in.a
AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a
LD [M] fs/smb/client/cifs.o
CC drivers/base/devtmpfs.o
AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a
AR drivers/media/platform/sunxi/sun8i-di/built-in.a
CC net/sunrpc/sunrpc_syms.o
AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a
CC drivers/net/phy/linkmode.o
AR drivers/media/platform/sunxi/built-in.a
CC drivers/input/ff-core.o
CC drivers/ata/libata-pmp.o
AR drivers/media/platform/ti/am437x/built-in.a
AR drivers/media/platform/ti/cal/built-in.a
CC drivers/ata/libata-acpi.o
CC [M] drivers/i2c/busses/i2c-isch.o
CC drivers/usb/host/ohci-hcd.o
AR drivers/media/platform/ti/vpe/built-in.a
AR drivers/media/platform/ti/davinci/built-in.a
CC drivers/usb/host/ohci-pci.o
AR drivers/media/platform/ti/omap/built-in.a
AR drivers/media/platform/verisilicon/built-in.a
CC net/ipv4/fib_trie.o
AR drivers/media/platform/ti/omap3isp/built-in.a
AR drivers/media/platform/ti/built-in.a
AR drivers/media/platform/via/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o
AR drivers/media/platform/xilinx/built-in.a
AR drivers/media/platform/built-in.a
CC drivers/rtc/nvmem.o
AR drivers/media/pci/ttpci/built-in.a
CC [M] drivers/gpu/drm/xe/xe_guc_log.o
AR drivers/media/pci/b2c2/built-in.a
CC [M] drivers/ptp/ptp_kvm_x86.o
AR drivers/media/pci/pluto2/built-in.a
AR drivers/media/pci/dm1105/built-in.a
CC net/ipv4/fib_notifier.o
AR drivers/media/pci/pt1/built-in.a
CC drivers/acpi/acpica/pswalk.o
AR drivers/media/pci/pt3/built-in.a
CC drivers/usb/host/uhci-hcd.o
AR drivers/media/pci/mantis/built-in.a
AR drivers/media/pci/ngene/built-in.a
CC drivers/rtc/dev.o
AR drivers/media/pci/ddbridge/built-in.a
AR drivers/media/pci/saa7146/built-in.a
AR drivers/media/pci/smipcie/built-in.a
AR drivers/media/pci/netup_unidvb/built-in.a
AR drivers/media/pci/intel/ipu3/built-in.a
AR drivers/media/pci/intel/built-in.a
AR drivers/media/pci/built-in.a
CC [M] net/bluetooth/l2cap_sock.o
AR drivers/media/usb/b2c2/built-in.a
CC [M] net/bluetooth/smp.o
AR drivers/media/usb/dvb-usb/built-in.a
AR drivers/media/usb/dvb-usb-v2/built-in.a
AR drivers/media/usb/s2255/built-in.a
AR drivers/media/usb/siano/built-in.a
AR drivers/media/usb/ttusb-budget/built-in.a
AR drivers/media/usb/ttusb-dec/built-in.a
CC kernel/tsacct.o
AR drivers/media/usb/built-in.a
CC arch/x86/kernel/mmconf-fam10h_64.o
AR drivers/media/mmc/siano/built-in.a
AR drivers/media/mmc/built-in.a
AR drivers/media/firewire/built-in.a
AR drivers/media/spi/built-in.a
AR drivers/media/test-drivers/built-in.a
AR drivers/media/built-in.a
CC fs/direct-io.o
AR drivers/power/reset/built-in.a
CC drivers/power/supply/power_supply_core.o
CC drivers/usb/storage/usb.o
CC drivers/power/supply/power_supply_sysfs.o
CC drivers/acpi/acpica/psxface.o
CC drivers/input/touchscreen.o
CC drivers/usb/core/file.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.o
CC drivers/power/supply/power_supply_leds.o
CC drivers/usb/core/buffer.o
CC kernel/tracepoint.o
CC lib/hexdump.o
CC [M] drivers/net/usb/r8152.o
CC drivers/acpi/acpica/rsaddr.o
CC fs/btrfs/dev-replace.o
CC arch/x86/kernel/vsmp_64.o
CC [M] drivers/gpu/drm/i915/intel_uncore.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/ioctl.o
CC drivers/base/node.o
CC [M] drivers/ptp/ptp_kvm_common.o
LD [M] drivers/ptp/ptp.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_encoders.o
CC [M] drivers/net/ipvlan/ipvlan_core.o
CC lib/kstrtox.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sa.o
CC [M] drivers/net/ipvlan/ipvlan_main.o
CC drivers/rtc/proc.o
CC net/sunrpc/cache.o
CC [M] drivers/gpu/drm/xe/xe_guc_pc.o
AR drivers/scsi/built-in.a
CC net/sunrpc/rpc_pipe.o
CC drivers/usb/host/xhci.o
CC [M] drivers/net/vxlan/vxlan_core.o
CC drivers/net/loopback.o
CC [M] drivers/net/vxlan/vxlan_multicast.o
CC kernel/latencytop.o
CC drivers/acpi/acpica/rscalc.o
CC drivers/usb/core/sysfs.o
CC drivers/hwmon/hwmon.o
CC drivers/ata/libata-pata-timings.o
AR arch/x86/kernel/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/core/memory.o
AR arch/x86/built-in.a
CC [M] drivers/i2c/busses/i2c-ismt.o
CC drivers/input/ff-memless.o
CC drivers/ata/ahci.o
CC drivers/net/phy/mdio_bus.o
AR drivers/thermal/broadcom/built-in.a
AR drivers/thermal/samsung/built-in.a
CC drivers/usb/core/endpoint.o
CC drivers/thermal/intel/intel_tcc.o
CC lib/debug_info.o
CC drivers/net/netconsole.o
CC drivers/rtc/sysfs.o
LD [M] drivers/ptp/ptp_kvm.o
CC drivers/thermal/intel/therm_throt.o
CC drivers/base/memory.o
CC drivers/power/supply/power_supply_hwmon.o
CC drivers/ata/libahci.o
CC drivers/usb/storage/initializers.o
CC drivers/acpi/acpica/rscreate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/mm.o
CC drivers/rtc/rtc-mc146818-lib.o
CC drivers/usb/core/devio.o
CC kernel/irq_work.o
CC mm/memory-tiers.o
CC drivers/i2c/i2c-core-acpi.o
CC drivers/ata/ata_piix.o
CC drivers/usb/core/notify.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/object.o
AR drivers/power/supply/built-in.a
AR drivers/power/built-in.a
CC drivers/input/vivaldi-fmap.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o
CC drivers/acpi/acpica/rsdumpinfo.o
CC drivers/i2c/i2c-core-slave.o
CC [M] drivers/hwmon/acpi_power_meter.o
CC [M] drivers/gpu/drm/xe/xe_guc_submit.o
CC kernel/static_call.o
CC drivers/usb/core/generic.o
CC net/ipv4/inet_fragment.o
CC drivers/usb/storage/sierra_ms.o
CC drivers/input/input-leds.o
CC [M] drivers/i2c/busses/i2c-piix4.o
CC [M] drivers/gpu/drm/drm_displayid.o
CC drivers/usb/host/xhci-mem.o
CC fs/btrfs/raid56.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine.o
CC drivers/rtc/rtc-cmos.o
CC drivers/base/module.o
CC drivers/input/mousedev.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o
CC [M] drivers/net/ipvlan/ipvlan_l3s.o
CC [M] drivers/hwmon/coretemp.o
CC drivers/base/pinctrl.o
CC drivers/acpi/acpica/rsinfo.o
CC [M] drivers/gpu/drm/drm_drv.o
CC net/sunrpc/sysfs.o
CC [M] drivers/net/vxlan/vxlan_vnifilter.o
CC [M] drivers/gpu/drm/i915/intel_wakeref.o
CC kernel/static_call_inline.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/oproxy.o
CC drivers/net/phy/mdio_device.o
CC lib/iomap.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/option.o
CC net/sunrpc/svc_xprt.o
CC [M] drivers/gpu/drm/amd/amdgpu/atombios_i2c.o
CC net/sunrpc/xprtmultipath.o
AR drivers/thermal/intel/built-in.a
AR drivers/thermal/st/built-in.a
AR drivers/thermal/qcom/built-in.a
AR drivers/thermal/tegra/built-in.a
CC drivers/watchdog/watchdog_core.o
AR drivers/thermal/mediatek/built-in.a
CC drivers/thermal/thermal_core.o
CC drivers/watchdog/watchdog_dev.o
CC [M] net/bluetooth/lib.o
CC kernel/user-return-notifier.o
CC drivers/watchdog/softdog.o
CC mm/migrate_device.o
CC drivers/acpi/acpica/rsio.o
CC drivers/usb/storage/option_ms.o
CC drivers/thermal/thermal_sysfs.o
CC drivers/acpi/acpica/rsirq.o
CC drivers/base/devcoredump.o
CC drivers/usb/storage/usual-tables.o
CC [M] drivers/md/persistent-data/dm-array.o
CC drivers/md/md.o
CC kernel/padata.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/ramht.o
CC kernel/jump_label.o
CC [M] drivers/net/ethernet/broadcom/cnic.o
CC [M] drivers/gpu/drm/i915/vlv_sideband.o
CC drivers/input/evdev.o
CC [M] drivers/gpu/drm/i915/vlv_suspend.o
CC drivers/net/phy/swphy.o
CC drivers/acpi/acpica/rslist.o
CC drivers/opp/core.o
AR drivers/ata/built-in.a
CC [M] drivers/i2c/busses/i2c-designware-pcidrv.o
CC drivers/opp/cpu.o
AR drivers/hwmon/built-in.a
AR drivers/rtc/built-in.a
CC [M] drivers/gpu/drm/i915/soc/intel_dram.o
CC drivers/acpi/acpica/rsmemory.o
CC lib/pci_iomap.o
CC drivers/cpufreq/cpufreq.o
CC net/ipv4/ping.o
CC drivers/cpufreq/freq_table.o
CC drivers/thermal/thermal_trip.o
CC drivers/opp/debugfs.o
CC drivers/base/platform-msi.o
CC net/sunrpc/stats.o
AR drivers/usb/storage/built-in.a
LD [M] drivers/net/ipvlan/ipvlan.o
CC drivers/usb/serial/usb-serial.o
AR drivers/usb/misc/built-in.a
CC [M] drivers/net/dummy.o
CC drivers/usb/serial/generic.o
CC [M] drivers/gpu/drm/i915/soc/intel_gmch.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.o
CC drivers/md/md-bitmap.o
CC drivers/thermal/thermal_helpers.o
CC [M] net/bluetooth/ecdh_helper.o
CC drivers/usb/gadget/udc/core.o
CC drivers/acpi/acpica/rsmisc.o
CC drivers/usb/gadget/udc/trace.o
AR drivers/watchdog/built-in.a
CC net/ipv4/ip_tunnel_core.o
AR drivers/usb/gadget/function/built-in.a
AR drivers/usb/gadget/legacy/built-in.a
CC drivers/usb/gadget/usbstring.o
CC drivers/md/md-autodetect.o
CC net/ipv4/gre_offload.o
CC [M] drivers/md/persistent-data/dm-bitset.o
CC drivers/acpi/acpica/rsserial.o
CC [M] net/bluetooth/hci_request.o
CC [M] drivers/gpu/drm/nouveau/nvkm/core/subdev.o
CC drivers/cpuidle/governors/menu.o
CC drivers/net/phy/fixed_phy.o
CC drivers/cpuidle/governors/haltpoll.o
CC lib/iomap_copy.o
CC drivers/usb/core/quirks.o
CC kernel/context_tracking.o
CC drivers/base/physical_location.o
CC drivers/base/trace.o
LD [M] drivers/i2c/busses/i2c-designware-pci.o
AR drivers/i2c/busses/built-in.a
CC drivers/i2c/i2c-dev.o
CC lib/devres.o
CC [M] drivers/net/macvlan.o
CC drivers/thermal/thermal_hwmon.o
CC net/ipv4/metrics.o
CC drivers/acpi/acpica/rsutils.o
CC kernel/iomem.o
CC [M] drivers/i2c/i2c-smbus.o
CC mm/huge_memory.o
AR drivers/input/built-in.a
CC [M] drivers/i2c/i2c-mux.o
CC net/sunrpc/sysctl.o
CC drivers/usb/host/xhci-ext-caps.o
CC [M] drivers/net/phy/phylink.o
CC lib/check_signature.o
CC [M] drivers/net/mii.o
CC drivers/acpi/acpica/rsxface.o
CC drivers/mmc/core/core.o
CC drivers/mmc/host/sdhci.o
CC drivers/mmc/core/bus.o
CC [M] drivers/md/persistent-data/dm-block-manager.o
CC drivers/mmc/host/sdhci-pci-core.o
CC drivers/mmc/core/host.o
CC [M] drivers/gpu/drm/i915/soc/intel_pch.o
CC mm/khugepaged.o
CC fs/btrfs/uuid-tree.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm.o
CC [M] drivers/gpu/drm/xe/xe_hw_fence.o
CC drivers/usb/core/devices.o
AR drivers/ufs/built-in.a
CC [M] drivers/net/mdio.o
CC drivers/thermal/gov_fair_share.o
AR drivers/cpuidle/governors/built-in.a
CC drivers/cpuidle/cpuidle.o
AR drivers/base/built-in.a
CC drivers/acpi/acpica/tbdata.o
AR drivers/leds/trigger/built-in.a
CC [M] drivers/leds/trigger/ledtrig-audio.o
AR drivers/opp/built-in.a
AR drivers/firmware/arm_ffa/built-in.a
AR drivers/firmware/arm_scmi/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/core/uevent.o
AR drivers/firmware/broadcom/built-in.a
AR drivers/firmware/cirrus/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/fw.o
AR drivers/firmware/meson/built-in.a
CC kernel/rseq.o
CC drivers/firmware/efi/efi-bgrt.o
CC lib/interval_tree.o
CC drivers/usb/serial/bus.o
CC drivers/firmware/efi/libstub/efi-stub-helper.o
CC drivers/firmware/efi/efi.o
AR drivers/firmware/imx/built-in.a
CC fs/eventpoll.o
CC drivers/usb/core/phy.o
CC lib/assoc_array.o
CC [M] drivers/net/tun.o
CC drivers/usb/host/xhci-ring.o
CC [M] drivers/net/phy/aquantia_main.o
AR net/sunrpc/built-in.a
CC net/ipv4/netlink.o
AR drivers/usb/gadget/udc/built-in.a
CC drivers/usb/gadget/config.o
CC drivers/usb/core/port.o
CC drivers/usb/host/xhci-hub.o
CC fs/anon_inodes.o
AR drivers/leds/blink/built-in.a
AR drivers/i2c/built-in.a
CC drivers/thermal/gov_step_wise.o
AR drivers/leds/simple/built-in.a
CC [M] drivers/md/persistent-data/dm-space-map-common.o
CC [M] net/bluetooth/mgmt_util.o
CC [M] drivers/gpu/drm/xe/xe_huc.o
CC drivers/leds/led-core.o
CC [M] drivers/net/vxlan/vxlan_mdb.o
CC drivers/cpufreq/cpufreq_ondemand.o
CC drivers/cpufreq/cpufreq_performance.o
CC [M] drivers/md/persistent-data/dm-space-map-disk.o
CC drivers/acpi/acpica/tbfadt.o
CC [M] drivers/net/veth.o
CC [M] drivers/net/phy/aquantia_hwmon.o
CC [M] net/bluetooth/mgmt_config.o
CC net/ipv4/nexthop.o
CC drivers/usb/serial/console.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.o
CC [M] drivers/net/phy/ax88796b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/hs.o
CC drivers/firmware/efi/libstub/gop.o
CC drivers/thermal/gov_user_space.o
CC [M] drivers/usb/class/usbtmc.o
CC drivers/cpufreq/cpufreq_governor.o
CC [M] drivers/net/usb/asix_devices.o
CC [M] drivers/gpu/drm/i915/i915_memcpy.o
CC drivers/usb/core/hcd-pci.o
CC drivers/acpi/acpica/tbfind.o
GZIP kernel/config_data.gz
CC drivers/usb/serial/ftdi_sio.o
CC kernel/configs.o
CC fs/btrfs/props.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ib.o
CC drivers/cpuidle/driver.o
CC drivers/usb/gadget/epautoconf.o
CC drivers/leds/led-class.o
CC lib/list_debug.o
CC drivers/usb/serial/pl2303.o
CC lib/debugobjects.o
CC net/ipv4/udp_tunnel_stub.o
CC [M] drivers/md/persistent-data/dm-space-map-metadata.o
CC drivers/cpuidle/governor.o
CC drivers/usb/core/usb-acpi.o
CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o
CC [M] drivers/gpu/drm/i915/i915_mm.o
CC drivers/cpufreq/cpufreq_governor_attr_set.o
CC [M] drivers/net/ethernet/broadcom/tg3.o
AR drivers/thermal/built-in.a
CC lib/bitrev.o
AR drivers/crypto/stm32/built-in.a
AR drivers/crypto/xilinx/built-in.a
AR drivers/crypto/hisilicon/built-in.a
CC drivers/acpi/acpica/tbinstal.o
AR drivers/crypto/intel/keembay/built-in.a
AR drivers/crypto/intel/ixp4xx/built-in.a
AR drivers/crypto/intel/built-in.a
AR drivers/crypto/starfive/built-in.a
CC drivers/clocksource/acpi_pm.o
AR drivers/crypto/built-in.a
CC [M] drivers/gpu/drm/i915/i915_sw_fence.o
CC lib/crc16.o
CC drivers/clocksource/i8253.o
CC [M] net/bluetooth/hci_codec.o
AR kernel/built-in.a
CC [M] drivers/net/phy/bcm7xxx.o
CC lib/crc-t10dif.o
CC drivers/acpi/acpica/tbprint.o
CC drivers/firmware/efi/libstub/secureboot.o
CC drivers/usb/gadget/composite.o
CC drivers/cpuidle/sysfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/ls.o
CC drivers/cpufreq/acpi-cpufreq.o
CC drivers/leds/led-triggers.o
CC drivers/mmc/core/mmc.o
CC drivers/mmc/host/sdhci-pci-o2micro.o
CC drivers/acpi/acpica/tbutils.o
CC [M] drivers/gpu/drm/xe/xe_irq.o
CC drivers/firmware/efi/vars.o
CC drivers/cpufreq/intel_pstate.o
CC drivers/hid/usbhid/hid-core.o
AR drivers/staging/media/built-in.a
AR drivers/staging/built-in.a
CC drivers/hid/usbhid/hiddev.o
AR drivers/platform/x86/amd/built-in.a
CC drivers/platform/x86/intel/pmc/core.o
AR drivers/usb/core/built-in.a
CC drivers/mailbox/mailbox.o
CC [M] drivers/platform/x86/intel/pmt/class.o
CC drivers/hid/hid-core.o
CC [M] drivers/md/persistent-data/dm-transaction-manager.o
CC drivers/mailbox/pcc.o
AR drivers/clocksource/built-in.a
CC [M] drivers/md/persistent-data/dm-btree.o
CC drivers/mmc/core/mmc_ops.o
CC drivers/firmware/efi/libstub/tpm.o
CC drivers/firmware/efi/reboot.o
CC drivers/acpi/acpi_cmos_rtc.o
CC [M] drivers/net/phy/bcm87xx.o
CC drivers/hid/hid-input.o
CC [M] drivers/net/usb/asix_common.o
CC drivers/acpi/acpica/tbxface.o
HOSTCC lib/gen_crc32table
CC drivers/mmc/core/sd.o
CC drivers/firmware/efi/libstub/file.o
CC drivers/cpuidle/poll_state.o
CC fs/btrfs/free-space-tree.o
CC lib/libcrc32c.o
AR drivers/usb/serial/built-in.a
CC drivers/platform/x86/intel/pmc/core_ssram.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_pll.o
AR drivers/net/ethernet/cavium/common/built-in.a
AR drivers/net/ethernet/cavium/thunder/built-in.a
AR drivers/net/ethernet/cortina/built-in.a
CC drivers/cpuidle/cpuidle-haltpoll.o
AR drivers/net/ethernet/cavium/liquidio/built-in.a
AR drivers/net/ethernet/cavium/octeon/built-in.a
AR drivers/net/ethernet/cavium/built-in.a
AR drivers/leds/built-in.a
CC [M] drivers/net/phy/bcm-phy-lib.o
CC [M] drivers/net/phy/broadcom.o
CC [M] drivers/net/phy/lxt.o
CC [M] net/bluetooth/eir.o
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/acr.o
CC [M] drivers/net/usb/ax88172a.o
CC [M] drivers/gpu/drm/i915/i915_sw_fence_work.o
CC fs/signalfd.o
CC drivers/platform/x86/intel/pmc/spt.o
LD [M] drivers/net/vxlan/vxlan.o
CC [M] drivers/platform/x86/intel/pmt/telemetry.o
AR drivers/mailbox/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.o
CC mm/page_counter.o
CC drivers/firmware/efi/memattr.o
CC drivers/devfreq/devfreq.o
CC lib/xxhash.o
CC drivers/acpi/acpica/tbxfload.o
CC lib/genalloc.o
CC [M] drivers/gpu/drm/xe/xe_lrc.o
AR drivers/net/ethernet/engleder/built-in.a
AR drivers/net/ethernet/ezchip/built-in.a
CC [M] drivers/md/persistent-data/dm-btree-remove.o
AR drivers/net/ethernet/fungible/built-in.a
CC drivers/platform/x86/p2sb.o
AR drivers/net/ethernet/huawei/built-in.a
CC lib/percpu_counter.o
CC drivers/mmc/host/sdhci-pci-arasan.o
AR drivers/cpuidle/built-in.a
CC mm/memcontrol.o
CC drivers/platform/x86/intel/turbo_max_3.o
GEN xe_wa_oob.c xe_wa_oob.h
CC drivers/usb/host/xhci-dbg.o
CC drivers/firmware/efi/libstub/mem.o
CC drivers/mmc/host/sdhci-pci-dwc-mshc.o
CC mm/vmpressure.o
CC drivers/powercap/powercap_sys.o
GEN xe_wa_oob.c xe_wa_oob.h
CC [M] drivers/gpu/drm/i915/i915_syncmap.o
CC [M] drivers/gpu/drm/xe/xe_mmio.o
CC [M] drivers/gpu/drm/xe/xe_mocs.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_main.o
CC [M] drivers/net/ethernet/intel/e1000e/82571.o
CC drivers/acpi/acpica/tbxfroot.o
CC drivers/firmware/efi/libstub/random.o
CC drivers/platform/x86/intel/pmc/cnp.o
CC [M] drivers/gpu/drm/xe/xe_module.o
CC [M] drivers/gpu/drm/i915/i915_user_extensions.o
CC drivers/acpi/acpica/utaddress.o
CC [M] drivers/platform/x86/intel/pmt/crashlog.o
CC [M] drivers/net/usb/ax88179_178a.o
CC [M] drivers/net/usb/cdc_ether.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.o
CC [M] drivers/net/phy/realtek.o
CC [M] drivers/net/ethernet/intel/igb/igb_main.o
AR drivers/hid/usbhid/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.o
CC [M] net/bluetooth/hci_sync.o
CC [M] drivers/net/usb/cdc_eem.o
CC [M] drivers/net/ethernet/intel/e1000e/ich8lan.o
CC [M] drivers/net/ethernet/intel/igc/igc_main.o
CC drivers/platform/x86/pmc_atom.o
CC drivers/mmc/core/sd_ops.o
CC lib/fault-inject.o
CC drivers/usb/host/xhci-trace.o
CC drivers/platform/x86/intel/pmc/icl.o
CC [M] drivers/gpu/drm/drm_dumb_buffers.o
CC [M] drivers/platform/x86/wmi.o
CC drivers/mmc/host/sdhci-pci-gli.o
CC [M] drivers/net/ethernet/intel/igbvf/vf.o
CC drivers/mmc/host/sdhci-acpi.o
CC drivers/usb/gadget/functions.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/base.o
CC [M] drivers/net/ethernet/intel/igbvf/mbx.o
CC [M] drivers/md/persistent-data/dm-btree-spine.o
CC drivers/usb/gadget/configfs.o
CC drivers/mmc/core/sdio.o
AR drivers/cpufreq/built-in.a
CC drivers/platform/x86/intel/pmc/tgl.o
CC [M] drivers/net/ethernet/intel/igbvf/ethtool.o
CC [M] drivers/net/ethernet/intel/igb/igb_ethtool.o
CC drivers/powercap/intel_rapl_common.o
CC drivers/acpi/acpica/utalloc.o
CC net/ipv4/sysctl_net_ipv4.o
CC [M] drivers/platform/x86/intel/vsec.o
CC drivers/firmware/efi/libstub/randomalloc.o
CC [M] drivers/gpu/drm/xe/xe_pat.o
AR drivers/platform/surface/built-in.a
CC drivers/mmc/core/sdio_ops.o
CC fs/btrfs/tree-checker.o
LD [M] drivers/platform/x86/intel/pmt/pmt_class.o
LD [M] drivers/platform/x86/intel/pmt/pmt_telemetry.o
CC drivers/usb/gadget/u_f.o
LD [M] drivers/platform/x86/intel/pmt/pmt_crashlog.o
CC drivers/hid/hid-quirks.o
CC drivers/acpi/acpica/utascii.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.o
CC lib/syscall.o
CC [M] drivers/gpu/drm/i915/i915_ioc32.o
CC [M] drivers/gpu/drm/drm_edid.o
CC drivers/platform/x86/intel/pmc/adl.o
CC drivers/mmc/core/sdio_bus.o
CC drivers/firmware/efi/libstub/pci.o
CC [M] drivers/devfreq/governor_simpleondemand.o
CC drivers/hid/hid-debug.o
CC [M] net/bluetooth/coredump.o
CC [M] drivers/net/usb/smsc75xx.o
CC [M] drivers/gpu/drm/i915/i915_debugfs.o
CC [M] drivers/net/phy/smsc.o
LD [M] drivers/md/persistent-data/dm-persistent-data.o
CC [M] drivers/net/ethernet/intel/igbvf/netdev.o
CC drivers/powercap/intel_rapl_msr.o
CC drivers/acpi/acpica/utbuffer.o
CC drivers/acpi/acpica/utcksum.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sync.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.o
CC [M] drivers/gpu/drm/i915/i915_debugfs_params.o
CC [M] drivers/net/usb/smsc95xx.o
CC drivers/md/dm-uevent.o
CC lib/dynamic_debug.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.o
CC [M] drivers/gpu/drm/xe/xe_pci.o
CC drivers/mmc/host/cqhci-core.o
CC [M] drivers/net/ethernet/intel/e1000e/80003es2lan.o
CC [M] drivers/devfreq/governor_performance.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/fw.o
CC drivers/platform/x86/intel/pmc/mtl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/msgq.o
CC drivers/md/dm.o
CC [M] drivers/net/ethernet/intel/e1000e/mac.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.o
CC drivers/platform/x86/intel/pmc/pltdrv.o
CC drivers/acpi/x86/apple.o
CC [M] drivers/net/ethernet/intel/igb/e1000_82575.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.o
CC drivers/firmware/efi/libstub/skip_spaces.o
CC drivers/acpi/acpica/utcopy.o
CC drivers/firmware/efi/libstub/lib-cmdline.o
CC [M] drivers/gpu/drm/i915/display/intel_display_debugfs.o
CC [M] drivers/platform/x86/intel/rst.o
CC drivers/mmc/core/sdio_cis.o
AR drivers/devfreq/built-in.a
CC drivers/firmware/efi/libstub/lib-ctype.o
CC drivers/md/dm-table.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.o
CC drivers/firmware/efi/libstub/alignedmem.o
AR drivers/powercap/built-in.a
LD [M] drivers/platform/x86/intel/intel_vsec.o
CC drivers/acpi/x86/utils.o
CC net/ipv4/proc.o
AR drivers/usb/gadget/built-in.a
AR drivers/perf/built-in.a
CC net/ipv4/syncookies.o
CC drivers/hid/hidraw.o
CC [M] drivers/gpu/drm/xe/xe_pcode.o
CC [M] drivers/net/ethernet/intel/igb/e1000_mac.o
LD [M] drivers/net/phy/aquantia.o
AR drivers/net/phy/built-in.a
CC [M] net/bluetooth/sco.o
CC [M] drivers/gpu/drm/drm_encoder.o
AR drivers/platform/x86/intel/pmc/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o
CC [M] drivers/net/usb/mcs7830.o
AR drivers/net/ethernet/i825xx/built-in.a
AR drivers/net/ethernet/microsoft/built-in.a
AR drivers/net/ethernet/litex/built-in.a
AR drivers/net/ethernet/microchip/built-in.a
AR drivers/net/ethernet/mscc/built-in.a
AR drivers/net/ethernet/neterion/built-in.a
AR drivers/net/ethernet/netronome/built-in.a
CC drivers/acpi/acpica/utexcep.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_main.o
CC drivers/acpi/acpica/utdebug.o
CC [M] drivers/gpu/drm/i915/display/intel_pipe_crc.o
CC drivers/usb/host/xhci-debugfs.o
CC [M] drivers/net/usb/usbnet.o
AR drivers/platform/x86/intel/built-in.a
LD [M] drivers/platform/x86/intel/intel-rst.o
CC [M] drivers/platform/x86/wmi-bmof.o
CC [M] net/bluetooth/iso.o
AR drivers/net/ethernet/ni/built-in.a
AR drivers/net/ethernet/packetengines/built-in.a
CC [M] drivers/gpu/drm/xe/xe_pm.o
CC [M] drivers/gpu/drm/i915/i915_pmu.o
CC [M] drivers/platform/x86/mxm-wmi.o
CC [M] net/bluetooth/a2mp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/v1.o
CC [M] drivers/platform/x86/intel_ips.o
CC drivers/firmware/efi/libstub/relocate.o
CC drivers/usb/host/xhci-pci.o
CC drivers/mmc/core/sdio_io.o
CC fs/btrfs/space-info.o
CC drivers/acpi/acpica/utdecode.o
CC [M] net/bluetooth/amp.o
CC [M] drivers/mmc/host/sdhci-pltfm.o
AR drivers/firmware/psci/built-in.a
CC [M] drivers/net/ethernet/intel/e1000e/manage.o
CC [M] drivers/net/usb/cdc_ncm.o
CC drivers/firmware/efi/libstub/printk.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/gm200.o
AR drivers/firmware/smccc/built-in.a
CC [M] drivers/gpu/drm/i915/gt/gen2_engine_cs.o
CC drivers/hid/hid-generic.o
CC fs/timerfd.o
CC drivers/acpi/x86/s2idle.o
CC lib/errname.o
CC drivers/acpi/debugfs.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_common.o
CC drivers/firmware/efi/libstub/vsprintf.o
CC lib/nlattr.o
CC drivers/firmware/efi/libstub/x86-stub.o
AR drivers/firmware/tegra/built-in.a
CC drivers/acpi/acpica/utdelete.o
AR drivers/firmware/xilinx/built-in.a
CC drivers/firmware/dmi_scan.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_hw.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.o
CC drivers/md/dm-target.o
CC fs/eventfd.o
CC drivers/acpi/acpi_lpat.o
LD [M] drivers/net/ethernet/intel/igbvf/igbvf.o
CC net/ipv4/esp4.o
CC [M] drivers/net/ethernet/intel/ixgbevf/vf.o
CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o
CC drivers/firmware/efi/tpm.o
CC [M] drivers/net/ethernet/intel/ixgbevf/mbx.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ethtool.o
CC drivers/mmc/core/sdio_irq.o
AR drivers/mmc/host/built-in.a
CC drivers/firmware/efi/memmap.o
CC [M] drivers/gpu/drm/xe/xe_pt.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.o
CC drivers/acpi/acpi_lpit.o
CC drivers/hid/hid-a4tech.o
AR drivers/net/ethernet/intel/built-in.a
CC fs/btrfs/block-rsv.o
AR drivers/platform/x86/built-in.a
AR drivers/platform/built-in.a
CC drivers/ras/ras.o
AR drivers/hwtracing/intel_th/built-in.a
CC drivers/md/dm-linear.o
CC drivers/ras/debugfs.o
CC drivers/acpi/acpica/uterror.o
CC drivers/hid/hid-apple.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_ethtool.o
AR drivers/usb/host/built-in.a
AR drivers/usb/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/gp102.o
CC drivers/acpi/prmt.o
CC drivers/acpi/acpica/uteval.o
CC drivers/hid/hid-belkin.o
CC drivers/md/dm-stripe.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.o
CC [M] drivers/net/ethernet/intel/e1000e/nvm.o
CC [M] drivers/gpu/drm/i915/gt/gen6_engine_cs.o
CC drivers/acpi/acpica/utglobal.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/ga100.o
STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o
CC [M] drivers/gpu/drm/drm_file.o
STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
STUBCPY drivers/firmware/efi/libstub/file.stub.o
STUBCPY drivers/firmware/efi/libstub/gop.stub.o
STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o
STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o
CC drivers/acpi/acpi_pcc.o
STUBCPY drivers/firmware/efi/libstub/mem.stub.o
STUBCPY drivers/firmware/efi/libstub/pci.stub.o
STUBCPY drivers/firmware/efi/libstub/printk.stub.o
STUBCPY drivers/firmware/efi/libstub/random.stub.o
STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o
STUBCPY drivers/firmware/efi/libstub/relocate.stub.o
CC [M] drivers/gpu/drm/i915/gt/gen6_ppgtt.o
CC net/ipv4/esp4_offload.o
STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o
STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o
STUBCPY drivers/firmware/efi/libstub/tpm.stub.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sched.o
STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o
CC lib/checksum.o
STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o
CC drivers/firmware/efi/esrt.o
AR drivers/firmware/efi/libstub/lib.a
CC net/ipv4/netfilter.o
CC drivers/md/dm-ioctl.o
CC drivers/acpi/acpica/uthex.o
CC drivers/firmware/efi/efi-pstore.o
CC lib/cpu_rmap.o
CC [M] net/bluetooth/hci_debugfs.o
CC drivers/mmc/core/slot-gpio.o
CC [M] drivers/net/ethernet/intel/igb/e1000_nvm.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.o
CC [M] drivers/net/usb/r8153_ecm.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.o
CC net/ipv4/inet_diag.o
CC drivers/acpi/acpica/utids.o
CC lib/dynamic_queue_limits.o
CC [M] drivers/net/ethernet/intel/igc/igc_mac.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ids.o
CC drivers/hid/hid-cherry.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.o
CC drivers/acpi/acpica/utinit.o
CC [M] drivers/net/ethernet/intel/igb/e1000_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/ga102.o
CC drivers/mmc/core/regulator.o
CC fs/userfaultfd.o
CC drivers/md/dm-io.o
CC drivers/acpi/acpica/utlock.o
AR drivers/ras/built-in.a
CC drivers/android/binderfs.o
CC drivers/hid/hid-chicony.o
CC drivers/android/binder.o
CC [M] drivers/net/ethernet/intel/igb/e1000_mbx.o
CC lib/glob.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.o
CC mm/swap_cgroup.o
CC drivers/hid/hid-cypress.o
CC [M] drivers/net/ethernet/intel/igc/igc_i225.o
CC drivers/mmc/core/debugfs.o
CC drivers/firmware/efi/cper.o
CC [M] drivers/net/ethernet/intel/igb/e1000_i210.o
CC fs/aio.o
CC fs/btrfs/delalloc-space.o
CC [M] drivers/gpu/drm/xe/xe_pt_walk.o
CC [M] drivers/gpu/drm/drm_fourcc.o
CC drivers/firmware/efi/cper_cxl.o
CC drivers/acpi/acpica/utmath.o
CC [M] drivers/net/ethernet/intel/e1000e/phy.o
CC lib/strncpy_from_user.o
CC drivers/hid/hid-ezkey.o
CC [M] drivers/gpu/drm/xe/xe_query.o
LD [M] drivers/net/usb/asix.o
CC fs/locks.o
CC fs/binfmt_script.o
CC net/ipv4/tcp_diag.o
CC drivers/hid/hid-kensington.o
CC lib/strnlen_user.o
CC [M] drivers/net/ethernet/intel/ixgbevf/ipsec.o
CC drivers/md/dm-kcopyd.o
CC [M] drivers/gpu/drm/i915/gt/gen7_renderclear.o
CC [M] drivers/net/ethernet/intel/igc/igc_base.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.o
AR drivers/net/ethernet/realtek/built-in.a
CC [M] drivers/net/ethernet/realtek/8139cp.o
CC [M] drivers/gpu/drm/xe/xe_range_fence.o
CC drivers/hid/hid-lg.o
CC drivers/mmc/core/block.o
CC mm/hugetlb_cgroup.o
CC drivers/mmc/core/queue.o
CC drivers/md/dm-sysfs.o
CC drivers/acpi/acpica/utmisc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.o
CC [M] drivers/gpu/drm/i915/gt/gen8_engine_cs.o
CC [M] drivers/net/ethernet/intel/igc/igc_nvm.o
CC mm/kmemleak.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.o
CC [M] drivers/net/ethernet/realtek/8139too.o
CC [M] drivers/net/ethernet/intel/e1000/e1000_param.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_82599.o
CC [M] drivers/gpu/drm/drm_framebuffer.o
CC [M] drivers/net/ethernet/intel/igc/igc_phy.o
CC fs/btrfs/block-group.o
CC drivers/acpi/ac.o
CC mm/page_isolation.o
CC lib/net_utils.o
LD [M] net/bluetooth/bluetooth.o
CC drivers/firmware/dmi-sysfs.o
CC drivers/firmware/efi/runtime-wrappers.o
CC [M] drivers/gpu/drm/i915/gt/gen8_ppgtt.o
CC drivers/acpi/acpica/utmutex.o
CC drivers/hid/hid-lg-g15.o
CC fs/btrfs/discard.o
CC [M] drivers/net/ethernet/intel/igb/igb_ptp.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_82598.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.o
CC net/ipv4/udp_diag.o
CC mm/early_ioremap.o
CC fs/btrfs/reflink.o
CC [M] drivers/gpu/drm/xe/xe_reg_sr.o
CC [M] drivers/net/ethernet/intel/igc/igc_diag.o
CC drivers/acpi/acpica/utnonansi.o
CC [M] drivers/net/ethernet/intel/igb/igb_hwmon.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.o
AR drivers/net/ethernet/renesas/built-in.a
CC drivers/acpi/acpica/utobject.o
AR drivers/net/ethernet/sfc/built-in.a
CC drivers/acpi/acpica/utosi.o
CC drivers/md/dm-stats.o
CC [M] drivers/gpu/drm/i915/gt/intel_breadcrumbs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.o
CC lib/sg_pool.o
AR drivers/net/ethernet/smsc/built-in.a
CC [M] drivers/net/ethernet/smsc/smsc9420.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.o
CC fs/btrfs/subpage.o
CC drivers/hid/hid-microsoft.o
CC [M] drivers/net/ethernet/intel/igc/igc_ethtool.o
CC drivers/acpi/button.o
CC drivers/hid/hid-monterey.o
CC lib/stackdepot.o
CC mm/cma.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.o
LD [M] drivers/net/ethernet/intel/e1000/e1000.o
AR drivers/net/ethernet/socionext/built-in.a
AR drivers/nvmem/layouts/built-in.a
CC drivers/nvmem/core.o
AR drivers/net/ethernet/vertexcom/built-in.a
CC [M] drivers/gpu/drm/drm_gem.o
CC drivers/acpi/acpica/utownerid.o
CC [M] drivers/gpu/drm/drm_ioctl.o
CC [M] drivers/net/ethernet/intel/e100.o
CC mm/secretmem.o
CC drivers/firmware/efi/dev-path-parser.o
AR drivers/net/ethernet/wangxun/built-in.a
CC [M] drivers/net/ethernet/intel/igc/igc_ptp.o
AR drivers/net/ethernet/xilinx/built-in.a
CC lib/ucs2_string.o
CC [M] drivers/gpu/drm/drm_lease.o
CC [M] drivers/net/ethernet/intel/e1000e/param.o
CC [M] drivers/gpu/drm/i915/gt/intel_context.o
CC [M] drivers/net/ethernet/realtek/r8169_main.o
CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_phy.o
CC net/ipv4/tcp_cubic.o
CC [M] drivers/net/ethernet/intel/igc/igc_dump.o
CC mm/userfaultfd.o
LD [M] drivers/net/ethernet/intel/ixgbevf/ixgbevf.o
CC drivers/md/dm-rq.o
CC drivers/md/dm-io-rewind.o
CC drivers/acpi/acpica/utpredef.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.o
CC mm/memremap.o
CC drivers/md/dm-builtin.o
CC [M] drivers/gpu/drm/drm_managed.o
CC [M] drivers/net/ethernet/intel/e1000e/ethtool.o
CC fs/binfmt_elf.o
CC [M] drivers/gpu/drm/i915/gt/intel_context_sseu.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.o
CC lib/sbitmap.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gv100.o
CC drivers/acpi/acpica/utresdecode.o
CC fs/compat_binfmt_elf.o
AR drivers/hid/built-in.a
AR drivers/mmc/core/built-in.a
AR drivers/mmc/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_engine_cs.o
CC [M] drivers/mtd/chips/chipreg.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o
LD [M] drivers/net/ethernet/intel/igb/igb.o
CC drivers/firmware/efi/apple-properties.o
CC drivers/firmware/efi/earlycon.o
CC mm/hmm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.o
CC fs/btrfs/tree-mod-log.o
CC [M] drivers/uio/uio.o
CC [M] drivers/gpu/drm/xe/xe_rtp.o
CC [M] drivers/gpu/drm/drm_mm.o
CC drivers/acpi/acpica/utresrc.o
CC lib/group_cpus.o
CC [M] drivers/md/dm-bufio.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_csa.o
AR drivers/nvmem/built-in.a
CC mm/memfd.o
CC drivers/firmware/efi/cper-x86.o
CC [M] drivers/vfio/pci/vfio_pci_core.o
CC [M] drivers/gpu/drm/drm_mode_config.o
CC fs/btrfs/extent-io-tree.o
CC [M] drivers/net/ethernet/intel/e1000e/netdev.o
CC [M] drivers/mtd/mtdcore.o
CC [M] drivers/vfio/pci/vfio_pci_intrs.o
CC [M] drivers/gpu/drm/xe/xe_ring_ops.o
CC fs/btrfs/fs.o
CC [M] drivers/net/ethernet/intel/e1000e/ptp.o
CC [M] drivers/gpu/drm/drm_mode_object.o
CC [M] drivers/vfio/vfio_main.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o
CC [M] drivers/net/ethernet/intel/igc/igc_tsn.o
CC drivers/acpi/acpica/utstate.o
CC mm/bootmem_info.o
CC fs/btrfs/messages.o
CC [M] drivers/gpu/drm/xe/xe_sa.o
CC [M] drivers/mtd/mtdsuper.o
CC [M] drivers/mtd/mtdconcat.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.o
CC net/ipv4/xfrm4_policy.o
CC [M] lib/asn1_decoder.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_pm.o
CC [M] drivers/vfio/pci/vfio_pci_rdwr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.o
CC [M] drivers/net/ethernet/intel/igc/igc_xdp.o
CC [M] drivers/gpu/drm/xe/xe_sched_job.o
AR drivers/firmware/efi/built-in.a
CC drivers/acpi/acpica/utstring.o
CC drivers/firmware/dmi-id.o
CC [M] drivers/pps/pps.o
CC [M] drivers/gpu/drm/xe/xe_step.o
CC [M] drivers/gpu/drm/drm_modes.o
CC [M] drivers/gpu/drm/i915/gt/intel_engine_user.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga100.o
CC [M] drivers/mtd/mtdpart.o
CC [M] drivers/bluetooth/btusb.o
CC fs/mbcache.o
CC [M] drivers/bluetooth/btintel.o
CC [M] drivers/dca/dca-core.o
CC [M] drivers/ssb/main.o
CC [M] drivers/bluetooth/btbcm.o
AR mm/built-in.a
GEN lib/oid_registry_data.c
CC drivers/acpi/fan_core.o
CC fs/posix_acl.o
CC [M] drivers/vhost/net.o
CC [M] lib/oid_registry.o
CC [M] drivers/vfio/pci/vfio_pci_config.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_x540.o
CC [M] drivers/vhost/vhost.o
CC [M] drivers/ssb/scan.o
CC [M] drivers/mtd/mtdchar.o
CC drivers/acpi/acpica/utstrsuppt.o
CC drivers/firmware/memmap.o
CC net/ipv4/xfrm4_state.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.o
CC fs/btrfs/bio.o
CC drivers/acpi/fan_attr.o
CC [M] drivers/vhost/iotlb.o
CC drivers/acpi/acpica/utstrtoul64.o
CC fs/btrfs/lru_cache.o
CC fs/coredump.o
CC [M] drivers/gpu/drm/xe/xe_sync.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.o
CC [M] drivers/pps/kapi.o
CC net/ipv4/xfrm4_input.o
CC [M] drivers/bluetooth/btrtl.o
CC drivers/android/binder_alloc.o
AR lib/lib.a
CC [M] drivers/md/dm-bio-prison-v1.o
GEN lib/crc32table.h
CC [M] drivers/md/dm-bio-prison-v2.o
CC lib/crc32.o
LD [M] drivers/net/ethernet/intel/igc/igc.o
CC [M] drivers/gpu/drm/xe/xe_tile.o
CC drivers/acpi/acpica/utxface.o
CC drivers/acpi/processor_driver.o
CC [M] drivers/vfio/group.o
CC [M] drivers/net/ethernet/realtek/r8169_firmware.o
CC drivers/acpi/acpica/utxfinit.o
CC fs/btrfs/acl.o
CC drivers/acpi/processor_thermal.o
CC [M] drivers/gpu/drm/xe/xe_tile_sysfs.o
CC [M] drivers/dca/dca-sysfs.o
CC drivers/acpi/acpica/utxferror.o
CC net/ipv4/xfrm4_output.o
CC [M] drivers/vfio/iova_bitmap.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.o
AR drivers/firmware/built-in.a
CC drivers/acpi/acpica/utxfmutex.o
CC [M] drivers/gpu/drm/xe/xe_trace.o
CC [M] drivers/md/dm-crypt.o
CC [M] drivers/pps/sysfs.o
CC drivers/acpi/processor_idle.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.o
CC [M] drivers/gpu/drm/i915/gt/intel_execlists_submission.o
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt.o
CC [M] drivers/ssb/sprom.o
CC [M] drivers/ssb/pci.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.o
CC [M] drivers/net/ethernet/realtek/r8169_phy_config.o
AR lib/built-in.a
CC [M] drivers/vfio/pci/vfio_pci.o
CC net/ipv4/xfrm4_protocol.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_x550.o
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o
CC [M] drivers/ssb/pcihost_wrapper.o
CC fs/drop_caches.o
CC drivers/acpi/processor_throttling.o
CC [M] net/ipv4/ip_tunnel.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt.o
AR drivers/acpi/acpica/built-in.a
LD [M] drivers/mtd/mtd.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.o
CC drivers/acpi/processor_perflib.o
CC [M] drivers/gpu/drm/drm_modeset_lock.o
LD [M] drivers/dca/dca.o
LD [M] drivers/pps/pps_core.o
CC fs/sysctls.o
CC [M] drivers/ssb/driver_chipcommon.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_lib.o
CC [M] drivers/gpu/drm/drm_plane.o
CC drivers/acpi/container.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.o
CC [M] drivers/gpu/drm/drm_prime.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.o
CC fs/fhandle.o
CC [M] drivers/vfio/container.o
CC [M] net/ipv4/udp_tunnel_core.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.o
CC [M] drivers/ssb/driver_chipcommon_pmu.o
CC [M] drivers/gpu/drm/drm_print.o
LD [M] drivers/vfio/pci/vfio-pci-core.o
AR drivers/net/ethernet/synopsys/built-in.a
AR drivers/net/ethernet/pensando/built-in.a
AR fs/btrfs/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o
CC [M] drivers/vfio/virqfd.o
LD [M] drivers/vfio/pci/vfio-pci.o
LD [M] drivers/vhost/vhost_iotlb.o
CC [M] drivers/ssb/driver_pcicore.o
LD [M] drivers/vhost/vhost_net.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.o
CC [M] drivers/vfio/vfio_iommu_type1.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.o
CC [M] net/ipv4/udp_tunnel_nic.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.o
CC drivers/acpi/thermal.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.o
AR drivers/android/built-in.a
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.o
LD [M] drivers/net/ethernet/realtek/r8169.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.o
CC [M] drivers/gpu/drm/drm_property.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.o
CC drivers/acpi/acpi_memhotplug.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_umc.o
CC drivers/acpi/ioapic.o
CC drivers/acpi/battery.o
CC [M] drivers/md/dm-thin.o
CC [M] drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.o
AR fs/built-in.a
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.o
CC [M] drivers/md/dm-thin-metadata.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_rap.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.o
CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
CC [M] drivers/gpu/drm/drm_syncobj.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.o
AR net/ipv4/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
CC drivers/acpi/hed.o
LD [M] drivers/md/dm-bio-prison.o
AR drivers/md/built-in.a
CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
LD [M] drivers/vfio/vfio.o
LD [M] drivers/ssb/ssb.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_irq.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_mcr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.o
CC [M] drivers/gpu/drm/drm_sysfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mca.o
CC drivers/acpi/bgrt.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm.o
CC [M] drivers/gpu/drm/xe/xe_tuning.o
CC [M] drivers/gpu/drm/drm_trace_points.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o
CC [M] drivers/gpu/drm/drm_vblank.o
CC drivers/acpi/cppc_acpi.o
CC [M] drivers/gpu/drm/xe/xe_uc.o
CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.o
CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.o
CC [M] drivers/gpu/drm/drm_vblank_work.o
CC drivers/acpi/spcr.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.o
LD [M] net/ipv4/udp_tunnel.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.o
CC [M] drivers/gpu/drm/xe/xe_uc_fw.o
CC [M] drivers/gpu/drm/drm_vma_manager.o
AR net/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_gt_requests.o
CC [M] drivers/gpu/drm/xe/xe_vm.o
CC [M] drivers/gpu/drm/xe/xe_vm_madvise.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_sysfs.o
CC [M] drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik.o
LD [M] drivers/net/ethernet/intel/e1000e/e1000e.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.o
CC drivers/acpi/acpi_pad.o
CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o
CC [M] drivers/acpi/acpi_video.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.o
CC [M] drivers/gpu/drm/i915/gt/intel_gtt.o
CC [M] drivers/gpu/drm/xe/xe_wa.o
CC [M] drivers/gpu/drm/drm_gpuva_mgr.o
CC [M] drivers/gpu/drm/drm_writeback.o
CC [M] drivers/acpi/video_detect.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik_ih.o
CC [M] drivers/gpu/drm/xe/xe_wopcm.o
CC [M] drivers/gpu/drm/xe/xe_hwmon.o
CC [M] drivers/gpu/drm/i915/gt/intel_llc.o
CC [M] drivers/gpu/drm/lib/drm_random.o
CC [M] drivers/gpu/drm/i915/gt/intel_lrc.o
CC [M] drivers/gpu/drm/i915/gt/intel_migrate.o
CC [M] drivers/gpu/drm/drm_ioc32.o
CC [M] drivers/gpu/drm/i915/gt/intel_mocs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.o
CC [M] drivers/gpu/drm/drm_panel.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v8_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v7_0.o
CC [M] drivers/gpu/drm/i915/gt/intel_ppgtt.o
CC [M] drivers/gpu/drm/i915/gt/intel_rc6.o
CC [M] drivers/gpu/drm/amd/amdgpu/cik_sdma.o
CC [M] drivers/gpu/drm/drm_pci.o
CC [M] drivers/gpu/drm/drm_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/intel_region_lmem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v4_2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.o
CC [M] drivers/gpu/drm/xe/xe_display.o
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v2_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.o
CC [M] drivers/gpu/drm/i915/gt/intel_renderstate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.o
CC [M] drivers/gpu/drm/drm_debugfs_crc.o
AR drivers/acpi/built-in.a
CC [M] drivers/gpu/drm/drm_edid_load.o
CC [M] drivers/gpu/drm/amd/amdgpu/si.o
CC [M] drivers/gpu/drm/drm_panel_orientation_quirks.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v6_0.o
LD [M] drivers/md/dm-thin-pool.o
CC [M] drivers/gpu/drm/xe/display/xe_fb_pin.o
CC [M] drivers/gpu/drm/xe/display/xe_hdcp_gsc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.o
CC [M] drivers/gpu/drm/xe/display/xe_plane_initial.o
CC [M] drivers/gpu/drm/xe/display/xe_display_rps.o
CC [M] drivers/gpu/drm/i915/gt/intel_reset.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_irq.o
LD [M] drivers/net/ethernet/intel/ixgbe/ixgbe.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_utils.o
CC [M] drivers/gpu/drm/drm_exec.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v6_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/si_ih.o
AR drivers/net/ethernet/built-in.a
CC [M] drivers/gpu/drm/i915/gt/intel_ring.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.o
AR drivers/net/built-in.a
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.o
CC [M] drivers/gpu/drm/i915/gt/intel_ring_submission.o
CC [M] drivers/gpu/drm/drm_buddy.o
CC [M] drivers/gpu/drm/drm_gem_shmem_helper.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_dram.o
CC [M] drivers/gpu/drm/amd/amdgpu/si_dma.o
CC [M] drivers/gpu/drm/i915/gt/intel_rps.o
CC [M] drivers/gpu/drm/drm_suballoc.o
LD [M] drivers/acpi/video.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v6_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.o
CC [M] drivers/gpu/drm/i915/gt/intel_sa_media.o
CC [M] drivers/gpu/drm/drm_gem_ttm_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/vpstate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.o
CC [M] drivers/gpu/drm/i915/gt/intel_sseu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_pch.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.o
CC [M] drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/intel_timeline.o
CC [M] drivers/gpu/drm/drm_atomic_helper.o
CC [M] drivers/gpu/drm/xe/i915-display/icl_dsi.o
CC [M] drivers/gpu/drm/i915/gt/intel_tlb.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v3_1.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/i915/gt/intel_wopcm.o
CC [M] drivers/gpu/drm/amd/amdgpu/vi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_audio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.o
CC [M] drivers/gpu/drm/i915/gt/intel_workarounds.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_backlight.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_vi.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v6_1.o
CC [M] drivers/gpu/drm/i915/gt/shmem_utils.o
CC [M] drivers/gpu/drm/drm_atomic_state_helper.o
CC [M] drivers/gpu/drm/drm_bridge_connector.o
CC [M] drivers/gpu/drm/drm_crtc_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/soc15.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.o
CC [M] drivers/gpu/drm/drm_damage_helper.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bios.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.o
CC [M] drivers/gpu/drm/amd/amdgpu/emu_soc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.o
CC [M] drivers/gpu/drm/i915/gt/sysfs_engines.o
CC [M] drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_ai.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bw.o
CC [M] drivers/gpu/drm/i915/gt/gen6_renderstate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cdclk.o
CC [M] drivers/gpu/drm/i915/gt/gen7_renderstate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.o
CC [M] drivers/gpu/drm/i915/gt/gen8_renderstate.o
CC [M] drivers/gpu/drm/drm_encoder_slave.o
CC [M] drivers/gpu/drm/drm_flip_work.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega10_reg_init.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.o
CC [M] drivers/gpu/drm/i915/gt/gen9_renderstate.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_busy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega20_reg_init.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.o
CC [M] drivers/gpu/drm/drm_format_helper.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_clflush.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_4.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_context.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_color.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_create.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_domain.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v2_3.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_internal.o
CC [M] drivers/gpu/drm/amd/amdgpu/nv.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_object.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_lmem.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_combo_phy.o
CC [M] drivers/gpu/drm/amd/amdgpu/arct_reg_init.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_mman.o
CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_nv.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_2.o
CC [M] drivers/gpu/drm/drm_gem_atomic_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.o
CC [M] drivers/gpu/drm/drm_gem_framebuffer_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_connector.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v4_0.o
CC [M] drivers/gpu/drm/drm_kms_helper_common.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v5_0.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_pages.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_phys.o
CC [M] drivers/gpu/drm/drm_modeset_helper.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_pm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.o
CC [M] drivers/gpu/drm/amd/amdgpu/aldebaran.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_region.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_shmem.o
CC [M] drivers/gpu/drm/drm_plane_helper.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_shrinker.o
CC [M] drivers/gpu/drm/amd/amdgpu/soc21.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cursor.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_stolen.o
CC [M] drivers/gpu/drm/drm_probe_helper.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_throttle.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cx0_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.o
CC [M] drivers/gpu/drm/drm_rect.o
CC [M] drivers/gpu/drm/amd/amdgpu/sienna_cichlid.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_tiling.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.o
CC [M] drivers/gpu/drm/drm_self_refresh_helper.o
CC [M] drivers/gpu/drm/drm_simple_kms_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v4_3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v6_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.o
CC [M] drivers/gpu/drm/bridge/panel.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_7.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_device.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o
CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v5_2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.o
CC [M] drivers/gpu/drm/drm_fbdev_generic.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_userptr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_driver.o
CC [M] drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.o
CC [M] drivers/gpu/drm/i915/gem/i915_gem_wait.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.o
CC [M] drivers/gpu/drm/i915/gem/i915_gemfs.o
CC [M] drivers/gpu/drm/i915/i915_active.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_irq.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.o
CC [M] drivers/gpu/drm/drm_fb_helper.o
CC [M] drivers/gpu/drm/i915/i915_cmd_parser.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.o
LD [M] drivers/gpu/drm/drm.o
CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_9.o
CC [M] drivers/gpu/drm/i915/i915_deps.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power.o
LD [M] drivers/gpu/drm/drm_shmem_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.o
CC [M] drivers/gpu/drm/i915/i915_gem_evict.o
LD [M] drivers/gpu/drm/drm_suballoc_helper.o
LD [M] drivers/gpu/drm/drm_ttm_helper.o
AR drivers/gpu/drm/built-in.a
CC [M] drivers/gpu/drm/i915/i915_gem_gtt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.o
CC [M] drivers/gpu/drm/i915/i915_gem_ww.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_map.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_well.o
CC [M] drivers/gpu/drm/i915/i915_gem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v1_7.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v3_6.o
CC [M] drivers/gpu/drm/i915/i915_query.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_trace.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_wa.o
CC [M] drivers/gpu/drm/amd/amdgpu/df_v4_3.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v7_0.o
CC [M] drivers/gpu/drm/i915/i915_request.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.o
CC [M] drivers/gpu/drm/i915/i915_scheduler.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v8_0.o
CC [M] drivers/gpu/drm/i915/i915_trace_points.o
CC [M] drivers/gpu/drm/i915/i915_ttm_buddy_manager.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.o
CC [M] drivers/gpu/drm/i915/i915_vma.o
CC [M] drivers/gpu/drm/i915/i915_vma_resource.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v9_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_mst.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_log.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v10_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
LD [M] drivers/gpu/drm/drm_kms_helper.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpt.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_drrs.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsb.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o
CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
CC [M] drivers/gpu/drm/i915/gt/intel_gsc.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.o
CC [M] drivers/gpu/drm/i915/i915_hwmon.o
CC [M] drivers/gpu/drm/i915/display/hsw_ips.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.o
CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v11_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o
CC [M] drivers/gpu/drm/i915/display/intel_atomic.o
CC [M] drivers/gpu/drm/i915/display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.o
CC [M] drivers/gpu/drm/i915/display/intel_audio.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fb.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fbc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fdi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.o
CC [M] drivers/gpu/drm/i915/display/intel_bios.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.o
CC [M] drivers/gpu/drm/i915/display/intel_bw.o
CC [M] drivers/gpu/drm/i915/display/intel_cdclk.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_global_state.o
CC [M] drivers/gpu/drm/i915/display/intel_color.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_gmbus.o
CC [M] drivers/gpu/drm/i915/display/intel_combo_phy.o
CC [M] drivers/gpu/drm/i915/display/intel_connector.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp.o
CC [M] drivers/gpu/drm/i915/display/intel_crtc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdmi.o
CC [M] drivers/gpu/drm/i915/display/intel_crtc_state_dump.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.o
CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_1.o
CC [M] drivers/gpu/drm/i915/display/intel_cursor.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.o
CC [M] drivers/gpu/drm/i915/display/intel_display.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_7.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v8_7.o
CC [M] drivers/gpu/drm/i915/display/intel_display_driver.o
CC [M] drivers/gpu/drm/i915/display/intel_display_irq.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power_map.o
CC [M] drivers/gpu/drm/amd/amdgpu/umc_v8_10.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug_irq.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hti.o
CC [M] drivers/gpu/drm/i915/display/intel_display_power_well.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_irq.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_lspcon.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_lock.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ih.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.o
CC [M] drivers/gpu/drm/i915/display/intel_display_reset.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/iceland_ih.o
CC [M] drivers/gpu/drm/amd/amdgpu/tonga_ih.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.o
CC [M] drivers/gpu/drm/amd/amdgpu/cz_ih.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.o
CC [M] drivers/gpu/drm/i915/display/intel_display_rps.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/i915/display/intel_display_wa.o
CC [M] drivers/gpu/drm/i915/display/intel_dmc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_panel.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega10_ih.o
CC [M] drivers/gpu/drm/i915/display/intel_dpio_phy.o
CC [M] drivers/gpu/drm/i915/display/intel_dpll.o
CC [M] drivers/gpu/drm/i915/display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.o
CC [M] drivers/gpu/drm/amd/amdgpu/vega20_ih.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pmdemand.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pps.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_psr.o
CC [M] drivers/gpu/drm/amd/amdgpu/navi10_ih.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.o
CC [M] drivers/gpu/drm/amd/amdgpu/ih_v6_0.o
CC [M] drivers/gpu/drm/i915/display/intel_dpt.o
CC [M] drivers/gpu/drm/i915/display/intel_drrs.o
CC [M] drivers/gpu/drm/i915/display/intel_dsb.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_qp_tables.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.o
CC [M] drivers/gpu/drm/i915/display/intel_fb.o
CC [M] drivers/gpu/drm/i915/display/intel_fb_pin.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.o
CC [M] drivers/gpu/drm/amd/amdgpu/ih_v6_1.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_psp.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v3_1.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_quirks.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v10_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_phy.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v11_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.o
CC [M] drivers/gpu/drm/i915/display/intel_fbc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_tc.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v12_0.o
CC [M] drivers/gpu/drm/i915/display/intel_fdi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vblank.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vdsc.o
CC [M] drivers/gpu/drm/i915/display/intel_fifo_underrun.o
CC [M] drivers/gpu/drm/i915/display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vga.o
CC [M] drivers/gpu/drm/i915/display/intel_global_state.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vrr.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v13_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_wm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.o
CC [M] drivers/gpu/drm/i915/display/intel_hdcp.o
CC [M] drivers/gpu/drm/i915/display/intel_hdcp_gsc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_scaler.o
CC [M] drivers/gpu/drm/i915/display/intel_hotplug.o
CC [M] drivers/gpu/drm/i915/display/intel_hotplug_irq.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v10_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/dce_v11_0.o
CC [M] drivers/gpu/drm/i915/display/intel_hti.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_universal_plane.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v8_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_0.o
CC [M] drivers/gpu/drm/i915/display/intel_load_detect.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_watermark.o
CC [M] drivers/gpu/drm/i915/display/intel_lpe_audio.o
CC [M] drivers/gpu/drm/xe/xe_pmu.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_acpi.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.o
CC [M] drivers/gpu/drm/i915/display/intel_modeset_lock.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_opregion.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.o
CC [M] drivers/gpu/drm/i915/display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/i915/display/intel_modeset_setup.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v10_0.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fbdev.o
CC [M] drivers/gpu/drm/xe/xe_guc.o
CC [M] drivers/gpu/drm/xe/xe_migrate.o
CC [M] drivers/gpu/drm/i915/display/intel_overlay.o
CC [M] drivers/gpu/drm/i915/display/intel_pch_display.o
CC [M] drivers/gpu/drm/i915/display/intel_pch_refclk.o
HDRTEST drivers/gpu/drm/xe/abi/guc_klvs_abi.h
CC [M] drivers/gpu/drm/i915/display/intel_plane_initial.o
CC [M] drivers/gpu/drm/i915/display/intel_pmdemand.o
CC [M] drivers/gpu/drm/amd/amdgpu/imu_v11_0.o
HDRTEST drivers/gpu/drm/xe/abi/guc_errors_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v11_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.o
CC [M] drivers/gpu/drm/amd/amdgpu/imu_v11_0_3.o
HDRTEST drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v2_4.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.o
HDRTEST drivers/gpu/drm/xe/abi/guc_actions_abi.h
CC [M] drivers/gpu/drm/i915/display/intel_psr.o
HDRTEST drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v3_0.o
HDRTEST drivers/gpu/drm/xe/abi/guc_messages_abi.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_gem.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp102.o
CC [M] drivers/gpu/drm/i915/display/intel_quirks.o
CC [M] drivers/gpu/drm/i915/display/intel_sprite.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h
CC [M] drivers/gpu/drm/i915/display/intel_sprite_uapi.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_irq.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
CC [M] drivers/gpu/drm/i915/display/intel_tc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.o
CC [M] drivers/gpu/drm/i915/display/intel_vblank.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_4.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h
CC [M] drivers/gpu/drm/i915/display/intel_vga.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h
CC [M] drivers/gpu/drm/i915/display/intel_wm.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.o
CC [M] drivers/gpu/drm/i915/display/i9xx_plane.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_config.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v5_0.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h
CC [M] drivers/gpu/drm/i915/display/i9xx_wm.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v5_2.o
CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v6_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mes.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_dram.h
CC [M] drivers/gpu/drm/amd/amdgpu/mes_v10_1.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h
CC [M] drivers/gpu/drm/amd/amdgpu/mes_v11_0.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.o
CC [M] drivers/gpu/drm/i915/display/skl_scaler.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.o
CC [M] drivers/gpu/drm/i915/display/skl_universal_plane.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.o
CC [M] drivers/gpu/drm/i915/display/skl_watermark.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_frontbuffer.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/gt/intel_rps.h
CC [M] drivers/gpu/drm/i915/display/intel_acpi.o
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h
HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_active.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.o
HDRTEST drivers/gpu/drm/xe/regs/xe_reg_defs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_guc_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v5_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v6_0.o
HDRTEST drivers/gpu/drm/xe/regs/xe_gt_regs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_regs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_gpu_commands.h
HDRTEST drivers/gpu/drm/xe/regs/xe_lrc_layout.h
HDRTEST drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_engine_regs.h
HDRTEST drivers/gpu/drm/xe/tests/xe_test.h
CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v7_0.o
CC [M] drivers/gpu/drm/i915/display/intel_opregion.o
HDRTEST drivers/gpu/drm/xe/tests/xe_pci_test.h
HDRTEST drivers/gpu/drm/xe/tests/xe_migrate_test.h
HDRTEST drivers/gpu/drm/xe/tests/xe_dma_buf_test.h
HDRTEST drivers/gpu/drm/xe/tests/xe_bo_test.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vce.o
HDRTEST drivers/gpu/drm/xe/xe_assert.h
HDRTEST drivers/gpu/drm/xe/xe_bb.h
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v3_0.o
HDRTEST drivers/gpu/drm/xe/xe_bb_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.o
HDRTEST drivers/gpu/drm/xe/xe_bo.h
CC [M] drivers/gpu/drm/i915/display/intel_fbdev.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/vce_v4_0.o
HDRTEST drivers/gpu/drm/xe/xe_bo_doc.h
HDRTEST drivers/gpu/drm/xe/xe_bo_evict.h
CC [M] drivers/gpu/drm/i915/display/dvo_ch7017.o
HDRTEST drivers/gpu/drm/xe/xe_bo_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.o
HDRTEST drivers/gpu/drm/xe/xe_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_devcoredump.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.o
HDRTEST drivers/gpu/drm/xe/xe_devcoredump_types.h
CC [M] drivers/gpu/drm/i915/display/dvo_ch7xxx.o
HDRTEST drivers/gpu/drm/xe/xe_device.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.o
HDRTEST drivers/gpu/drm/xe/xe_device_sysfs.h
HDRTEST drivers/gpu/drm/xe/xe_device_types.h
HDRTEST drivers/gpu/drm/xe/xe_display.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.o
CC [M] drivers/gpu/drm/i915/display/dvo_ivch.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v1_0.o
HDRTEST drivers/gpu/drm/xe/xe_dma_buf.h
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v2_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.o
CC [M] drivers/gpu/drm/i915/display/dvo_ns2501.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v2_5.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v3_0.o
CC [M] drivers/gpu/drm/i915/display/dvo_sil164.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v4_0.o
CC [M] drivers/gpu/drm/i915/display/dvo_tfp410.o
CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.o
CC [M] drivers/gpu/drm/i915/display/g4x_dp.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.o
CC [M] drivers/gpu/drm/i915/display/g4x_hdmi.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.o
HDRTEST drivers/gpu/drm/xe/xe_drv.h
HDRTEST drivers/gpu/drm/xe/xe_exec.h
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.o
HDRTEST drivers/gpu/drm/xe/xe_exec_queue.h
HDRTEST drivers/gpu/drm/xe/xe_exec_queue_types.h
CC [M] drivers/gpu/drm/i915/display/icl_dsi.o
HDRTEST drivers/gpu/drm/xe/xe_execlist.h
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.o
CC [M] drivers/gpu/drm/i915/display/intel_backlight.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.o
CC [M] drivers/gpu/drm/i915/display/intel_crt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv4e.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.o
CC [M] drivers/gpu/drm/i915/display/intel_cx0_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgf119.o
HDRTEST drivers/gpu/drm/xe/xe_execlist_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.o
HDRTEST drivers/gpu/drm/xe/xe_force_wake.h
HDRTEST drivers/gpu/drm/xe/xe_force_wake_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.o
HDRTEST drivers/gpu/drm/xe/xe_ggtt.h
CC [M] drivers/gpu/drm/i915/display/intel_ddi.o
HDRTEST drivers/gpu/drm/xe/xe_ggtt_types.h
HDRTEST drivers/gpu/drm/xe/xe_gt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v1_0.o
CC [M] drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v2_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v2_1.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.o
CC [M] drivers/gpu/drm/amd/amdgpu/athub_v3_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v9_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgf119.o
CC [M] drivers/gpu/drm/i915/display/intel_display_device.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.o
HDRTEST drivers/gpu/drm/xe/xe_gt_clock.h
HDRTEST drivers/gpu/drm/xe/xe_gt_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.o
HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs_types.h
HDRTEST drivers/gpu/drm/xe/xe_gt_mcr.h
HDRTEST drivers/gpu/drm/xe/xe_gt_pagefault.h
HDRTEST drivers/gpu/drm/xe/xe_gt_printk.h
HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs.h
HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs_types.h
CC [M] drivers/gpu/drm/i915/display/intel_display_trace.o
CC [M] drivers/gpu/drm/i915/display/intel_dkl_phy.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v11_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0.o
HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
CC [M] drivers/gpu/drm/i915/display/intel_dp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0_3.o
CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0_6.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_reset.o
HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h
HDRTEST drivers/gpu/drm/xe/xe_gt_topology.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.o
HDRTEST drivers/gpu/drm/xe/xe_gt_types.h
CC [M] drivers/gpu/drm/i915/display/intel_dp_aux.o
CC [M] drivers/gpu/drm/amd/amdgpu/mca_v3_0.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.o
HDRTEST drivers/gpu/drm/xe/xe_guc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_module.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.o
HDRTEST drivers/gpu/drm/xe/xe_guc_ads.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.o
HDRTEST drivers/gpu/drm/xe/xe_guc_ads_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_pasid.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.o
HDRTEST drivers/gpu/drm/xe/xe_guc_ct.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.o
HDRTEST drivers/gpu/drm/xe/xe_guc_ct_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_debugfs.h
CC [M] drivers/gpu/drm/i915/display/intel_dp_link_training.o
HDRTEST drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_doorbell.o
CC [M] drivers/gpu/drm/i915/display/intel_dp_mst.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_flat_memory.o
CC [M] drivers/gpu/drm/i915/display/intel_dsi.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/ga102.o
HDRTEST drivers/gpu/drm/xe/xe_guc_fwif.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.o
HDRTEST drivers/gpu/drm/xe/xe_guc_hwconfig.h
HDRTEST drivers/gpu/drm/xe/xe_guc_log.h
HDRTEST drivers/gpu/drm/xe/xe_guc_log_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_pc.h
CC [M] drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_cik.o
HDRTEST drivers/gpu/drm/xe/xe_guc_pc_types.h
CC [M] drivers/gpu/drm/i915/display/intel_dsi_vbt.o
HDRTEST drivers/gpu/drm/xe/xe_guc_submit.h
HDRTEST drivers/gpu/drm/xe/xe_guc_submit_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_types.h
HDRTEST drivers/gpu/drm/xe/xe_huc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.o
HDRTEST drivers/gpu/drm/xe/xe_huc_debugfs.h
CC [M] drivers/gpu/drm/i915/display/intel_dvo.o
HDRTEST drivers/gpu/drm/xe/xe_huc_types.h
HDRTEST drivers/gpu/drm/xe/xe_hw_engine.h
HDRTEST drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v9.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.o
HDRTEST drivers/gpu/drm/xe/xe_hw_engine_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v11.o
HDRTEST drivers/gpu/drm/xe/xe_hw_fence.h
HDRTEST drivers/gpu/drm/xe/xe_hw_fence_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.o
HDRTEST drivers/gpu/drm/xe/xe_hwmon.h
CC [M] drivers/gpu/drm/i915/display/intel_gmbus.o
HDRTEST drivers/gpu/drm/xe/xe_irq.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue.o
HDRTEST drivers/gpu/drm/xe/xe_lrc.h
HDRTEST drivers/gpu/drm/xe/xe_lrc_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager.o
CC [M] drivers/gpu/drm/i915/display/intel_hdmi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_vi.o
HDRTEST drivers/gpu/drm/xe/xe_macros.h
CC [M] drivers/gpu/drm/i915/display/intel_lspcon.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_v9.o
HDRTEST drivers/gpu/drm/xe/xe_map.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process_queue_manager.o
CC [M] drivers/gpu/drm/i915/display/intel_lvds.o
HDRTEST drivers/gpu/drm/xe/xe_migrate.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_cik.o
HDRTEST drivers/gpu/drm/xe/xe_migrate_doc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_vi.o
CC [M] drivers/gpu/drm/i915/display/intel_panel.o
HDRTEST drivers/gpu/drm/xe/xe_mmio.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v9.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.o
CC [M] drivers/gpu/drm/i915/display/intel_pps.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.o
HDRTEST drivers/gpu/drm/xe/xe_mocs.h
HDRTEST drivers/gpu/drm/xe/xe_module.h
HDRTEST drivers/gpu/drm/xe/xe_pat.h
CC [M] drivers/gpu/drm/i915/display/intel_qp_tables.o
HDRTEST drivers/gpu/drm/xe/xe_pci.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v11.o
HDRTEST drivers/gpu/drm/xe/xe_pci_types.h
HDRTEST drivers/gpu/drm/xe/xe_pcode.h
HDRTEST drivers/gpu/drm/xe/xe_pcode_api.h
HDRTEST drivers/gpu/drm/xe/xe_platform_types.h
HDRTEST drivers/gpu/drm/xe/xe_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.o
CC [M] drivers/gpu/drm/i915/display/intel_sdvo.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.o
CC [M] drivers/gpu/drm/i915/display/intel_snps_phy.o
HDRTEST drivers/gpu/drm/xe/xe_pmu.h
CC [M] drivers/gpu/drm/i915/display/intel_tv.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/cik_event_interrupt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v10.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v11.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.o
CC [M] drivers/gpu/drm/i915/display/intel_vdsc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.o
CC [M] drivers/gpu/drm/i915/display/intel_vrr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debug.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.o
HDRTEST drivers/gpu/drm/xe/xe_pmu_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debugfs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.o
CC [M] drivers/gpu/drm/i915/display/vlv_dsi.o
HDRTEST drivers/gpu/drm/xe/xe_preempt_fence.h
CC [M] drivers/gpu/drm/i915/display/vlv_dsi_pll.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.o
CC [M] drivers/gpu/drm/i915/i915_perf.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.o
HDRTEST drivers/gpu/drm/xe/xe_preempt_fence_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp.o
HDRTEST drivers/gpu/drm/xe/xe_pt.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.o
HDRTEST drivers/gpu/drm/xe/xe_pt_types.h
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_tee.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.o
HDRTEST drivers/gpu/drm/xe/xe_pt_walk.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_huc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmmcp77.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_job.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_acp.o
CC [M] drivers/gpu/drm/amd/amdgpu/../acp/acp_hw.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.o
HDRTEST drivers/gpu/drm/xe/xe_query.h
HDRTEST drivers/gpu/drm/xe/xe_range_fence.h
HDRTEST drivers/gpu/drm/xe/xe_reg_sr.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.o
HDRTEST drivers/gpu/drm/xe/xe_reg_sr_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_cmd.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.o
HDRTEST drivers/gpu/drm/xe/xe_reg_whitelist.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.o
HDRTEST drivers/gpu/drm/xe/xe_res_cursor.h
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.o
HDRTEST drivers/gpu/drm/xe/xe_ring_ops.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/arcturus_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.o
HDRTEST drivers/gpu/drm/xe/xe_ring_ops_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.o
HDRTEST drivers/gpu/drm/xe/xe_rtp.h
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_irq.o
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_pm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.o
HDRTEST drivers/gpu/drm/xe/xe_rtp_types.h
CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_session.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.o
HDRTEST drivers/gpu/drm/xe/xe_sa.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/cyan_skillfish_ppt.o
HDRTEST drivers/gpu/drm/xe/xe_sa_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.o
CC [M] drivers/gpu/drm/i915/i915_gpu_error.o
CC [M] drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.o
CC [M] drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/smu_v11_0.o
CC [M] drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.o
HDRTEST drivers/gpu/drm/xe/xe_sched_job.h
HDRTEST drivers/gpu/drm/xe/xe_sched_job_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.o
HDRTEST drivers/gpu/drm/xe/xe_step.h
HDRTEST drivers/gpu/drm/xe/xe_step_types.h
HDRTEST drivers/gpu/drm/xe/xe_sync.h
HDRTEST drivers/gpu/drm/xe/xe_sync_types.h
HDRTEST drivers/gpu/drm/xe/xe_tile.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/renoir_ppt.o
CC [M] drivers/gpu/drm/i915/selftests/i915_random.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/smu_v12_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.o
HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_0_ppt.o
CC [M] drivers/gpu/drm/i915/selftests/i915_selftest.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_4_ppt.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_5_ppt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.o
HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs_types.h
HDRTEST drivers/gpu/drm/xe/xe_trace.h
HDRTEST drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h
HDRTEST drivers/gpu/drm/xe/xe_ttm_sys_mgr.h
HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_7_ppt.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.o
CC [M] drivers/gpu/drm/i915/selftests/igt_atomic.o
CC [M] drivers/gpu/drm/i915/selftests/igt_flush_test.o
HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h
CC [M] drivers/gpu/drm/i915/selftests/igt_live_test.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.o
HDRTEST drivers/gpu/drm/xe/xe_tuning.h
CC [M] drivers/gpu/drm/i915/selftests/igt_mmap.o
HDRTEST drivers/gpu/drm/xe/xe_uc.h
CC [M] drivers/gpu/drm/i915/selftests/igt_reset.o
CC [M] drivers/gpu/drm/i915/selftests/igt_spinner.o
CC [M] drivers/gpu/drm/i915/selftests/librapl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.o
CC [M] drivers/gpu/drm/i915/i915_vgpu.o
HDRTEST drivers/gpu/drm/xe/xe_uc_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.o
HDRTEST drivers/gpu/drm/xe/xe_uc_fw.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.o
HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h
HDRTEST drivers/gpu/drm/xe/xe_uc_fw_abi.h
HDRTEST drivers/gpu/drm/xe/xe_uc_fw_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_crtc_state_dump.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.o
HDRTEST drivers/gpu/drm/i915/display/hsw_ips.h
HDRTEST drivers/gpu/drm/i915/display/g4x_hdmi.h
HDRTEST drivers/gpu/drm/xe/xe_uc_types.h
HDRTEST drivers/gpu/drm/xe/xe_vm.h
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_overlay.h
HDRTEST drivers/gpu/drm/i915/display/intel_display.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.o
HDRTEST drivers/gpu/drm/xe/xe_vm_doc.h
HDRTEST drivers/gpu/drm/i915/display/skl_watermark_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.o
HDRTEST drivers/gpu/drm/xe/xe_vm_madvise.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.o
HDRTEST drivers/gpu/drm/i915/display/intel_dmc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.o
HDRTEST drivers/gpu/drm/i915/display/intel_vga.h
HDRTEST drivers/gpu/drm/i915/display/intel_audio.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.o
HDRTEST drivers/gpu/drm/xe/xe_vm_types.h
HDRTEST drivers/gpu/drm/i915/display/intel_lvds.h
HDRTEST drivers/gpu/drm/xe/xe_wa.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu8_smumgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_modeset_setup.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/tonga_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/fiji_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/polaris10_smumgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_cdclk.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_limits.h
HDRTEST drivers/gpu/drm/i915/display/intel_hotplug.h
HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy.h
HDRTEST drivers/gpu/drm/xe/xe_wait_user_fence.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/iceland_smumgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_atomic.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_driver.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.o
HDRTEST drivers/gpu/drm/i915/display/intel_dpll.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu7_smumgr.o
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp_mst.h
HDRTEST drivers/gpu/drm/i915/display/intel_fdi_regs.h
HDRTEST drivers/gpu/drm/i915/display/g4x_dp.h
HDRTEST drivers/gpu/drm/i915/display/intel_tc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega10_smumgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu10_smumgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_frontbuffer.h
HDRTEST drivers/gpu/drm/i915/display/intel_dsi_vbt.h
HDRTEST drivers/gpu/drm/i915/display/intel_psr.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/ci_smumgr.o
HDRTEST drivers/gpu/drm/xe/xe_wopcm.h
HDRTEST drivers/gpu/drm/i915/display/intel_crt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.o
HDRTEST drivers/gpu/drm/i915/display/intel_opregion.h
HDRTEST drivers/gpu/drm/xe/xe_wopcm_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.o
HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.o
HDRTEST drivers/gpu/drm/i915/display/i9xx_wm.h
HDRTEST drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega12_smumgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_global_state.h
HDRTEST drivers/gpu/drm/i915/display/intel_lpe_audio.h
HDRTEST drivers/gpu/drm/i915/display/intel_drrs.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_rps.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vegam_smumgr.o
LD [M] drivers/gpu/drm/xe/xe.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu9_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.o
HDRTEST drivers/gpu/drm/i915/display/intel_fbdev.h
HDRTEST drivers/gpu/drm/i915/display/intel_pps_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_hdmi.h
HDRTEST drivers/gpu/drm/i915/display/intel_fdi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega20_smumgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.o
HDRTEST drivers/gpu/drm/i915/display/intel_fb.h
HDRTEST drivers/gpu/drm/i915/display/intel_qp_tables.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hwmgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_dsb_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_vdsc.h
HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/processpptables.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hardwaremanager.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_core.h
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu8_hwmgr.o
HDRTEST drivers/gpu/drm/i915/display/intel_dvo_dev.h
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp.h
HDRTEST drivers/gpu/drm/i915/display/intel_sdvo_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pppcielanes.o
HDRTEST drivers/gpu/drm/i915/display/intel_pch_refclk.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/process_pptables_v1_0.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.o
HDRTEST drivers/gpu/drm/i915/display/intel_modeset_lock.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_trace.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomfwctrl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_power.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.o
HDRTEST drivers/gpu/drm/i915/display/i9xx_plane.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_backlight.h
HDRTEST drivers/gpu/drm/i915/display/intel_dpll_mgr.h
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.o
HDRTEST drivers/gpu/drm/i915/display/intel_plane_initial.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_powertune.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_thermal.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_device.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.o
HDRTEST drivers/gpu/drm/i915/display/intel_fifo_underrun.h
HDRTEST drivers/gpu/drm/i915/display/intel_cursor.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.o
HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_clockpowergating.o
HDRTEST drivers/gpu/drm/i915/display/intel_cx0_phy.h
HDRTEST drivers/gpu/drm/i915/display/skl_scaler.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_processpptables.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.o
HDRTEST drivers/gpu/drm/i915/display/intel_hti.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.o
HDRTEST drivers/gpu/drm/i915/display/icl_dsi_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_powertune.o
HDRTEST drivers/gpu/drm/i915/display/intel_atomic_plane.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_thermal.o
HDRTEST drivers/gpu/drm/i915/display/skl_watermark.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu10_hwmgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/base.o
HDRTEST drivers/gpu/drm/i915/display/intel_fbc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_psm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_processpptables.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_hwmgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_thermal.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_reg_defs.h
HDRTEST drivers/gpu/drm/i915/display/intel_acpi.h
HDRTEST drivers/gpu/drm/i915/display/intel_connector.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/uvfn.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/gv100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/tu102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_overdriver.o
HDRTEST drivers/gpu/drm/i915/display/intel_dpt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/ga100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.o
HDRTEST drivers/gpu/drm/i915/display/intel_quirks.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_processpptables.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp_link_training.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_hwmgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.o
HDRTEST drivers/gpu/drm/i915/display/intel_color.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_powertune.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.o
HDRTEST drivers/gpu/drm/i915/display/intel_crtc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_thermal.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/common_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_baco.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/falcon.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_baco.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/xtensa.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu9_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/tonga_baco.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/polaris_baco.o
HDRTEST drivers/gpu/drm/i915/display/intel_modeset_verify.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/fiji_baco.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_power_well.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ci_baco.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.o
HDRTEST drivers/gpu/drm/i915/display/intel_psr_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.o
HDRTEST drivers/gpu/drm/i915/display/intel_wm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_baco.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.o
HDRTEST drivers/gpu/drm/i915/display/intel_pipe_crc.h
HDRTEST drivers/gpu/drm/i915/display/intel_audio_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/amd_powerplay.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/legacy_dpm.o
HDRTEST drivers/gpu/drm/i915/display/intel_panel.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/base.o
HDRTEST drivers/gpu/drm/i915/display/intel_sprite.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/pci.o
HDRTEST drivers/gpu/drm/i915/display/intel_wm_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_dpm.o
HDRTEST drivers/gpu/drm/i915/display/intel_tv.h
HDRTEST drivers/gpu/drm/i915/display/intel_hti_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_vrr.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_smc.o
HDRTEST drivers/gpu/drm/i915/display/intel_load_detect.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_dpm.o
HDRTEST drivers/gpu/drm/i915/display/skl_universal_plane.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_smc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/user.o
HDRTEST drivers/gpu/drm/i915/display/intel_mg_phy_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_pm.o
HDRTEST drivers/gpu/drm/i915/display/intel_bw.h
CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_irq.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/head.o
HDRTEST drivers/gpu/drm/i915/display/intel_de.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crtc.o
HDRTEST drivers/gpu/drm/i915/display/intel_lvds_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_irq.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_color.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.o
HDRTEST drivers/gpu/drm/i915/display/intel_gmbus_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_services.o
HDRTEST drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.o
HDRTEST drivers/gpu/drm/i915/display/intel_dvo.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_psr.o
HDRTEST drivers/gpu/drm/i915/display/intel_sdvo.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_replay.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.o
HDRTEST drivers/gpu/drm/i915/display/intel_vdsc_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.o
HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.o
HDRTEST drivers/gpu/drm/i915/display/intel_dvo_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/conversion.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/fixpt31_32.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.o
HDRTEST drivers/gpu/drm/i915/display/intel_gmbus.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/vector.o
HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_gsc.h
HDRTEST drivers/gpu/drm/i915/display/intel_dsi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.o
HDRTEST drivers/gpu/drm/i915/display/intel_dmc_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dc_common.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_interface.o
HDRTEST drivers/gpu/drm/i915/display/intel_ddi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_helper.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper.o
HDRTEST drivers/gpu/drm/i915/display/intel_hotplug_irq.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.o
HDRTEST drivers/gpu/drm/i915/display/intel_tv_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_common.o
HDRTEST drivers/gpu/drm/i915/display/intel_dsb.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/user.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.o
HDRTEST drivers/gpu/drm/i915/display/intel_bios.h
HDRTEST drivers/gpu/drm/i915/display/intel_pch_display.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper2.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce60/command_table_helper_dce60.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper_dce112.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/chid.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper2_dce112.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dce_calcs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/runq.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/custom_float.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/bw_fixed.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o
HDRTEST drivers/gpu/drm/i915/display/intel_backlight.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_rq_dlg_helpers.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dml1_display_rq_dlg_calc.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.o
HDRTEST drivers/gpu/drm/i915/display/intel_vblank.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/g98.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn10/dcn10_fpu.o
HDRTEST drivers/gpu/drm/i915/display/intel_dp.h
HDRTEST drivers/gpu/drm/i915/display/intel_pmdemand.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_vba.o
HDRTEST drivers/gpu/drm/i915/display/intel_backlight_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.o
HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy_regs.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_reset.h
HDRTEST drivers/gpu/drm/i915/display/intel_display_power_map.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.o
HDRTEST drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20v2.o
HDRTEST drivers/gpu/drm/i915/display/intel_display_wa.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.o
HDRTEST drivers/gpu/drm/i915/display/icl_dsi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.o
HDRTEST drivers/gpu/drm/i915/display/intel_lspcon.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_rq_dlg_calc_21.o
HDRTEST drivers/gpu/drm/i915/display/intel_dpio_phy.h
HDRTEST drivers/gpu/drm/i915/display/intel_dp_hdcp.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.o
HDRTEST drivers/gpu/drm/i915/display/intel_fb_pin.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.o
HDRTEST drivers/gpu/drm/i915/display/intel_pps.h
HDRTEST drivers/gpu/drm/i915/display/intel_sprite_uapi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_rq_dlg_calc_30.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_region.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_lmem.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/base.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_mman.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_rq_dlg_calc_31.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_mode_vba_314.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_clflush.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_tiling.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_stolen.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv44.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_create.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/g84.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_move.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gt200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp79.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gt215.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ioctls.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/mcp89.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_domain.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_internal.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_context.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn321/dcn321_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/huge_gem_object.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_gem_object.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn302/dcn302_fpu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/dcn314_fpu.o
HDRTEST drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dsc/rc_calc_fpu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calcs.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_math.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_auto.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_userptr.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp108.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_pm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce60/dce60_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce100/dce_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_shrinker.h
HDRTEST drivers/gpu/drm/i915/gem/i915_gemfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ga102.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce110/dce110_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object_frontbuffer.h
HDRTEST drivers/gpu/drm/i915/gt/intel_timeline_types.h
HDRTEST drivers/gpu/drm/i915/gt/selftest_engine.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.o
HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce112/dce112_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce120/dce120_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.o
HDRTEST drivers/gpu/drm/i915/gt/intel_context_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_execlists_submission.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv2_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.o
HDRTEST drivers/gpu/drm/i915/gt/selftest_rc6.h
HDRTEST drivers/gpu/drm/i915/gt/intel_llc_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt.h
HDRTEST drivers/gpu/drm/i915/gt/intel_region_lmem.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_requests.h
HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_print.h
HDRTEST drivers/gpu/drm/i915/gt/gen8_ppgtt.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm200.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm20b.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_mcr.h
HDRTEST drivers/gpu/drm/i915/gt/intel_timeline.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/gen6_engine_cs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/dcn301_smu.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds_types.h
HDRTEST drivers/gpu/drm/i915/gt/selftest_rps.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp107.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_smu.o
HDRTEST drivers/gpu/drm/i915/gt/intel_sa_media.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxga102.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_smu.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv31.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv44.o
HDRTEST drivers/gpu/drm/i915/gt/intel_rps_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv50.o
HDRTEST drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h
HDRTEST drivers/gpu/drm/i915/gt/sysfs_engines.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mpeg/g84.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/gen7_renderclear.h
HDRTEST drivers/gpu/drm/i915/gt/intel_context.h
HDRTEST drivers/gpu/drm/i915/gt/intel_wopcm.h
HDRTEST drivers/gpu/drm/i915/gt/intel_mocs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_pm.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_smu.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_rc6.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_defines.h
HDRTEST drivers/gpu/drm/i915/gt/intel_ring_types.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.o
HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds.h
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_regs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h
HDRTEST drivers/gpu/drm/i915/gt/shmem_utils.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_smu.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine.h
HDRTEST drivers/gpu/drm/i915/gt/intel_reset_types.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_regs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.o
HDRTEST drivers/gpu/drm/i915/gt/intel_reset.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/msppp/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/msppp/g98.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/msppp/gt215.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/msppp/gf100.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/msvld/base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_audio.o
HDRTEST drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/msvld/g98.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/msvld/gt215.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/msvld/mcp89.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_link_encoder.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/msvld/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_print.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/msvld/gk104.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/nvenc/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/nvenc/gm107.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_scl_filters.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/nvdec/base.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.o
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h
HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/nvdec/gm107.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_dmcu.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/nvdec/ga102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/pm/base.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/pm/nv40.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_abm.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/pm/nv50.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_ipp.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_print.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/pm/g84.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/pm/gt200.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_hw.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/pm/gt215.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/pm/gf100.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/pm/gf108.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/pm/gf117.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_sw.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_psr.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/pm/gk104.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sec/g98.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm_lcd.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sec2/ga102.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sw/base.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sw/nv04.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_panel_cntl.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_hw_lock_mgr.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_outbox.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sw/nv10.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_replay.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_base.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sw/gf100.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_factory.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_gpio.o
HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sw/chan.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_hpd.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_ddc.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_generic.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_translate.o
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/sw/nvsw.o
HDRTEST drivers/gpu/drm/i915/gt/intel_hwconfig.h
HDRTEST drivers/gpu/drm/i915/gt/intel_llc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce60/hw_translate_dce60.o
HDRTEST drivers/gpu/drm/i915/gt/gen8_engine_cs.h
CC [M] drivers/gpu/drm/nouveau/nvkm/engine/vp/g84.o
CC [M] drivers/gpu/drm/nouveau/nouveau_acpi.o
CC [M] drivers/gpu/drm/nouveau/nouveau_debugfs.o
HDRTEST drivers/gpu/drm/i915/gt/intel_sseu_debugfs.h
HDRTEST drivers/gpu/drm/i915/gt/intel_rc6_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce60/hw_factory_dce60.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_translate_dce80.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_factory_dce80.o
HDRTEST drivers/gpu/drm/i915/gt/intel_context_param.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_translate_dce110.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_factory_dce110.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gpu_commands.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_translate_dce120.o
CC [M] drivers/gpu/drm/nouveau/nouveau_drm.o
HDRTEST drivers/gpu/drm/i915/gt/intel_engine_user.h
HDRTEST drivers/gpu/drm/i915/gt/intel_gt_irq.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_factory_dce120.o
HDRTEST drivers/gpu/drm/i915/gt/intel_gsc.h
CC [M] drivers/gpu/drm/nouveau/nouveau_hwmon.o
HDRTEST drivers/gpu/drm/i915/gt/intel_rps.h
CC [M] drivers/gpu/drm/nouveau/nouveau_ioc32.o
CC [M] drivers/gpu/drm/nouveau/nouveau_led.o
CC [M] drivers/gpu/drm/nouveau/nouveau_nvif.o
HDRTEST drivers/gpu/drm/i915/gt/intel_tlb.h
HDRTEST drivers/gpu/drm/i915/gt/selftest_llc.h
CC [M] drivers/gpu/drm/nouveau/nouveau_usif.o
CC [M] drivers/gpu/drm/nouveau/nouveau_vga.o
HDRTEST drivers/gpu/drm/i915/gt/gen6_ppgtt.h
HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h
CC [M] drivers/gpu/drm/nouveau/nouveau_bo.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_translate_dcn10.o
HDRTEST drivers/gpu/drm/i915/gt/intel_migrate_types.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_factory_dcn10.o
CC [M] drivers/gpu/drm/nouveau/nouveau_bo0039.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_translate_dcn20.o
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_factory_dcn20.o
HDRTEST drivers/gpu/drm/i915/gt/selftests/mock_timeline.h
CC [M] drivers/gpu/drm/nouveau/nouveau_bo5039.o
HDRTEST drivers/gpu/drm/i915/gt/intel_lrc.h
CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn21/hw_translate_dcn21.o
HDRTEST drivers
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-xe] ✗ CI.Hooks: failure for Add HWMON support for DGFX (rev5)
2023-09-21 10:25 ` Badal Nilawar
` (10 preceding siblings ...)
(?)
@ 2023-09-21 10:30 ` Patchwork
-1 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2023-09-21 10:30 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
== Series Details ==
Series: Add HWMON support for DGFX (rev5)
URL : https://patchwork.freedesktop.org/series/118934/
State : failure
== Summary ==
run-parts: executing /workspace/ci/hooks/00-showenv
/workspace
+ pwd
+ ls -la
total 912
drwxrwxr-x 10 1003 1003 4096 Sep 21 10:30 .
drwxr-xr-x 1 root root 4096 Sep 21 10:30 ..
-rw-rw-r-- 1 1003 1003 789726 Sep 21 10:29 build.log
-rw-rw-r-- 1 1003 1003 1968 Sep 21 10:21 checkpatch.log
drwxrwxr-x 5 1003 1003 4096 Sep 21 10:19 ci
drwxrwxr-x 9 1003 1003 4096 Sep 21 10:19 docker
drwxrwxr-x 8 1003 1003 4096 Sep 21 10:19 .git
-rw-rw-r-- 1 1003 1003 822 Sep 21 10:21 git_apply.log
drwxrwxr-x 4 1003 1003 4096 Sep 21 10:19 .github
-rw-rw-r-- 1 1003 1003 233 Sep 21 10:19 .groovylintrc.json
-rw-rw-r-- 1 1003 1003 78 Sep 21 10:30 hooks.log
drwxrwxr-x 31 1003 1003 4096 Sep 21 10:29 kernel
-rw-rw-r-- 1 1003 1003 48570 Sep 21 10:21 kernel.mbox
-rw-rw-r-- 1 1003 1003 26482 Sep 21 10:22 kunit.log
-rw-rw-r-- 1 1003 1003 48 Sep 21 10:21 parent.tag
drwxrwxr-x 45 1003 1003 4096 Sep 21 10:19 pipelines
-rw-rw-r-- 1 1003 1003 793 Sep 21 10:19 README.adoc
drwxrwxr-x 3 1003 1003 4096 Sep 21 10:19 scripts
drwxrwxr-x 2 1003 1003 4096 Sep 21 10:19 .vscode
+ uname -a
Linux 47323f2933a5 5.4.0-149-generic #166-Ubuntu SMP Tue Apr 18 16:51:45 UTC 2023 x86_64 x86_64 x86_64 GNU/Linux
+ export
+ grep -Ei '(^|\W)CI_'
declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-default"
declare -x CI_KERNEL_SRC_DIR="/workspace/kernel"
declare -x CI_TOOLS_SRC_DIR="/workspace/ci"
declare -x CI_WORKSPACE_DIR="/workspace"
+ '[' -n /workspace ']'
+ git_args='-C /workspace/kernel'
+ git_log_args=
+ git --no-pager -C /workspace/kernel log --format=oneline --abbrev-commit
662378266 drm/xe/hwmon: Expose power1_max_interval
e25dd62d1 drm/xe/hwmon: Expose hwmon energy attribute
88a517751 drm/xe/hwmon: Expose input voltage attribute
ded4ac88b drm/xe/hwmon: Expose card reactive critical power
d50bb8d1c drm/xe/hwmon: Expose power attributes
a26e2637c drm/xe: Add XE_MISSING_CASE macro
57039c55b fixup! drm/xe/bo: Evict VRAM to TT rather than to system
run-parts: executing /workspace/ci/hooks/10-build-W1
+ SRC_DIR=/workspace/kernel
+ RESTORE_DISPLAY_CONFIG=0
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ cd /workspace/kernel
+ grep -q -e '^CONFIG_DRM_XE_DISPLAY=[yY]' /workspace/kernel/build64-default/.config
+ RESTORE_DISPLAY_CONFIG=1
+ trap cleanup EXIT
+ ./scripts/config --file /workspace/kernel/build64-default/.config --disable CONFIG_DRM_XE_DISPLAY
++ nproc
+ make -j48 O=/workspace/kernel/build64-default modules_prepare
make[1]: Entering directory '/workspace/kernel/build64-default'
SYNC include/config/auto.conf.cmd
GEN Makefile
GEN Makefile
UPD include/config/kernel.release
UPD include/generated/compile.h
UPD include/generated/utsrelease.h
DESCEND objtool
CALL ../scripts/checksyscalls.sh
HOSTCC /workspace/kernel/build64-default/tools/objtool/fixdep.o
HOSTLD /workspace/kernel/build64-default/tools/objtool/fixdep-in.o
LINK /workspace/kernel/build64-default/tools/objtool/fixdep
INSTALL libsubcmd_headers
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/help.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/pager.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/parse-options.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/run-command.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/sigchain.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o
LD /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o
AR /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a
CC /workspace/kernel/build64-default/tools/objtool/weak.o
CC /workspace/kernel/build64-default/tools/objtool/check.o
CC /workspace/kernel/build64-default/tools/objtool/special.o
CC /workspace/kernel/build64-default/tools/objtool/builtin-check.o
CC /workspace/kernel/build64-default/tools/objtool/elf.o
CC /workspace/kernel/build64-default/tools/objtool/objtool.o
CC /workspace/kernel/build64-default/tools/objtool/orc_gen.o
CC /workspace/kernel/build64-default/tools/objtool/orc_dump.o
CC /workspace/kernel/build64-default/tools/objtool/libstring.o
CC /workspace/kernel/build64-default/tools/objtool/libctype.o
CC /workspace/kernel/build64-default/tools/objtool/str_error_r.o
CC /workspace/kernel/build64-default/tools/objtool/librbtree.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/special.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/decode.o
LD /workspace/kernel/build64-default/tools/objtool/arch/x86/objtool-in.o
LD /workspace/kernel/build64-default/tools/objtool/objtool-in.o
LINK /workspace/kernel/build64-default/tools/objtool/objtool
make[1]: Leaving directory '/workspace/kernel/build64-default'
++ nproc
+ make -j48 O=/workspace/kernel/build64-default M=drivers/gpu/drm/xe W=1
make[1]: Entering directory '/workspace/kernel/build64-default'
CC [M] drivers/gpu/drm/xe/xe_bb.o
CC [M] drivers/gpu/drm/xe/xe_bo.o
CC [M] drivers/gpu/drm/xe/xe_bo_evict.o
CC [M] drivers/gpu/drm/xe/xe_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_devcoredump.o
CC [M] drivers/gpu/drm/xe/xe_device.o
CC [M] drivers/gpu/drm/xe/xe_device_sysfs.o
CC [M] drivers/gpu/drm/xe/xe_dma_buf.o
CC [M] drivers/gpu/drm/xe/xe_exec.o
CC [M] drivers/gpu/drm/xe/xe_execlist.o
CC [M] drivers/gpu/drm/xe/xe_exec_queue.o
CC [M] drivers/gpu/drm/xe/xe_force_wake.o
CC [M] drivers/gpu/drm/xe/xe_ggtt.o
CC [M] drivers/gpu/drm/xe/xe_gt.o
CC [M] drivers/gpu/drm/xe/xe_gt_clock.o
CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_gt_idle_sysfs.o
CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o
CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o
CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o
CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
CC [M] drivers/gpu/drm/xe/xe_gt_topology.o
HOSTCC drivers/gpu/drm/xe/xe_gen_wa_oob
CC [M] drivers/gpu/drm/xe/xe_guc_ads.o
CC [M] drivers/gpu/drm/xe/xe_guc_ct.o
CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o
CC [M] drivers/gpu/drm/xe/xe_guc_log.o
CC [M] drivers/gpu/drm/xe/xe_guc_pc.o
CC [M] drivers/gpu/drm/xe/xe_guc_submit.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o
CC [M] drivers/gpu/drm/xe/xe_hw_fence.o
CC [M] drivers/gpu/drm/xe/xe_huc.o
CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_irq.o
CC [M] drivers/gpu/drm/xe/xe_lrc.o
CC [M] drivers/gpu/drm/xe/xe_mmio.o
CC [M] drivers/gpu/drm/xe/xe_mocs.o
CC [M] drivers/gpu/drm/xe/xe_module.o
CC [M] drivers/gpu/drm/xe/xe_pat.o
CC [M] drivers/gpu/drm/xe/xe_pci.o
CC [M] drivers/gpu/drm/xe/xe_pcode.o
CC [M] drivers/gpu/drm/xe/xe_pm.o
CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o
CC [M] drivers/gpu/drm/xe/xe_pt.o
CC [M] drivers/gpu/drm/xe/xe_pt_walk.o
CC [M] drivers/gpu/drm/xe/xe_query.o
CC [M] drivers/gpu/drm/xe/xe_range_fence.o
CC [M] drivers/gpu/drm/xe/xe_reg_sr.o
CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o
CC [M] drivers/gpu/drm/xe/xe_rtp.o
CC [M] drivers/gpu/drm/xe/xe_sa.o
CC [M] drivers/gpu/drm/xe/xe_sched_job.o
CC [M] drivers/gpu/drm/xe/xe_step.o
CC [M] drivers/gpu/drm/xe/xe_sync.o
CC [M] drivers/gpu/drm/xe/xe_tile.o
CC [M] drivers/gpu/drm/xe/xe_tile_sysfs.o
CC [M] drivers/gpu/drm/xe/xe_trace.o
CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
CC [M] drivers/gpu/drm/xe/xe_tuning.o
CC [M] drivers/gpu/drm/xe/xe_uc.o
CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_uc_fw.o
CC [M] drivers/gpu/drm/xe/xe_vm_madvise.o
CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o
CC [M] drivers/gpu/drm/xe/xe_wopcm.o
CC [M] drivers/gpu/drm/xe/xe_hwmon.o
CC [M] drivers/gpu/drm/xe/xe_pmu.o
HDRTEST drivers/gpu/drm/xe/abi/guc_klvs_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_errors_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h
CC [M] drivers/gpu/drm/xe/tests/xe_bo_test.o
HDRTEST drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_actions_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h
HDRTEST drivers/gpu/drm/xe/abi/guc_messages_abi.h
CC [M] drivers/gpu/drm/xe/tests/xe_dma_buf_test.o
CC [M] drivers/gpu/drm/xe/tests/xe_migrate_test.o
HDRTEST drivers/gpu/drm/xe/regs/xe_reg_defs.h
CC [M] drivers/gpu/drm/xe/tests/xe_pci_test.o
HDRTEST drivers/gpu/drm/xe/regs/xe_guc_regs.h
CC [M] drivers/gpu/drm/xe/tests/xe_rtp_test.o
HDRTEST drivers/gpu/drm/xe/regs/xe_gt_regs.h
CC [M] drivers/gpu/drm/xe/tests/xe_wa_test.o
HDRTEST drivers/gpu/drm/xe/regs/xe_regs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_gpu_commands.h
HDRTEST drivers/gpu/drm/xe/regs/xe_lrc_layout.h
HDRTEST drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
HDRTEST drivers/gpu/drm/xe/regs/xe_engine_regs.h
HDRTEST drivers/gpu/drm/xe/tests/xe_test.h
HDRTEST drivers/gpu/drm/xe/tests/xe_pci_test.h
HDRTEST drivers/gpu/drm/xe/tests/xe_migrate_test.h
HDRTEST drivers/gpu/drm/xe/tests/xe_dma_buf_test.h
HDRTEST drivers/gpu/drm/xe/tests/xe_bo_test.h
HDRTEST drivers/gpu/drm/xe/xe_assert.h
HDRTEST drivers/gpu/drm/xe/xe_bb.h
HDRTEST drivers/gpu/drm/xe/xe_bo.h
HDRTEST drivers/gpu/drm/xe/xe_bb_types.h
HDRTEST drivers/gpu/drm/xe/xe_bo_doc.h
HDRTEST drivers/gpu/drm/xe/xe_bo_evict.h
HDRTEST drivers/gpu/drm/xe/xe_bo_types.h
HDRTEST drivers/gpu/drm/xe/xe_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_devcoredump.h
HDRTEST drivers/gpu/drm/xe/xe_devcoredump_types.h
HDRTEST drivers/gpu/drm/xe/xe_device.h
HDRTEST drivers/gpu/drm/xe/xe_device_sysfs.h
HDRTEST drivers/gpu/drm/xe/xe_device_types.h
HDRTEST drivers/gpu/drm/xe/xe_dma_buf.h
HDRTEST drivers/gpu/drm/xe/xe_drv.h
HDRTEST drivers/gpu/drm/xe/xe_exec.h
HDRTEST drivers/gpu/drm/xe/xe_exec_queue.h
HDRTEST drivers/gpu/drm/xe/xe_exec_queue_types.h
HDRTEST drivers/gpu/drm/xe/xe_execlist.h
HDRTEST drivers/gpu/drm/xe/xe_execlist_types.h
HDRTEST drivers/gpu/drm/xe/xe_force_wake.h
HDRTEST drivers/gpu/drm/xe/xe_force_wake_types.h
HDRTEST drivers/gpu/drm/xe/xe_ggtt.h
HDRTEST drivers/gpu/drm/xe/xe_ggtt_types.h
HDRTEST drivers/gpu/drm/xe/xe_gt.h
HDRTEST drivers/gpu/drm/xe/xe_gt_clock.h
HDRTEST drivers/gpu/drm/xe/xe_gt_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs.h
HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs_types.h
HDRTEST drivers/gpu/drm/xe/xe_gt_mcr.h
HDRTEST drivers/gpu/drm/xe/xe_gt_pagefault.h
HDRTEST drivers/gpu/drm/xe/xe_gt_printk.h
HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs.h
HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs_types.h
HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h
HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h
HDRTEST drivers/gpu/drm/xe/xe_gt_topology.h
HDRTEST drivers/gpu/drm/xe/xe_gt_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ads.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ads_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_ct.h
../drivers/gpu/drm/xe/xe_hwmon.c:127:5: error: no previous prototype for ‘xe_hwmon_process_reg_read64’ [-Werror=missing-prototypes]
127 | int xe_hwmon_process_reg_read64(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, u64 *value)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
HDRTEST drivers/gpu/drm/xe/xe_guc_ct_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_guc_exec_queue_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_fwif.h
HDRTEST drivers/gpu/drm/xe/xe_guc_hwconfig.h
HDRTEST drivers/gpu/drm/xe/xe_guc_log.h
HDRTEST drivers/gpu/drm/xe/xe_guc_log_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_pc.h
HDRTEST drivers/gpu/drm/xe/xe_guc_pc_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_submit.h
HDRTEST drivers/gpu/drm/xe/xe_guc_submit_types.h
HDRTEST drivers/gpu/drm/xe/xe_guc_types.h
HDRTEST drivers/gpu/drm/xe/xe_huc.h
HDRTEST drivers/gpu/drm/xe/xe_huc_debugfs.h
HDRTEST drivers/gpu/drm/xe/xe_hw_engine.h
HDRTEST drivers/gpu/drm/xe/xe_huc_types.h
HDRTEST drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.h
HDRTEST drivers/gpu/drm/xe/xe_hw_engine_types.h
HDRTEST drivers/gpu/drm/xe/xe_hw_fence.h
HDRTEST drivers/gpu/drm/xe/xe_hw_fence_types.h
HDRTEST drivers/gpu/drm/xe/xe_hwmon.h
HDRTEST drivers/gpu/drm/xe/xe_irq.h
HDRTEST drivers/gpu/drm/xe/xe_lrc.h
HDRTEST drivers/gpu/drm/xe/xe_lrc_types.h
HDRTEST drivers/gpu/drm/xe/xe_macros.h
HDRTEST drivers/gpu/drm/xe/xe_map.h
HDRTEST drivers/gpu/drm/xe/xe_migrate.h
HDRTEST drivers/gpu/drm/xe/xe_migrate_doc.h
HDRTEST drivers/gpu/drm/xe/xe_mmio.h
HDRTEST drivers/gpu/drm/xe/xe_mocs.h
HDRTEST drivers/gpu/drm/xe/xe_module.h
HDRTEST drivers/gpu/drm/xe/xe_pat.h
HDRTEST drivers/gpu/drm/xe/xe_pci.h
HDRTEST drivers/gpu/drm/xe/xe_pci_types.h
HDRTEST drivers/gpu/drm/xe/xe_pcode.h
HDRTEST drivers/gpu/drm/xe/xe_pcode_api.h
HDRTEST drivers/gpu/drm/xe/xe_platform_types.h
HDRTEST drivers/gpu/drm/xe/xe_pm.h
HDRTEST drivers/gpu/drm/xe/xe_pmu.h
HDRTEST drivers/gpu/drm/xe/xe_pmu_types.h
HDRTEST drivers/gpu/drm/xe/xe_preempt_fence.h
HDRTEST drivers/gpu/drm/xe/xe_preempt_fence_types.h
HDRTEST drivers/gpu/drm/xe/xe_pt.h
HDRTEST drivers/gpu/drm/xe/xe_pt_types.h
HDRTEST drivers/gpu/drm/xe/xe_pt_walk.h
HDRTEST drivers/gpu/drm/xe/xe_query.h
HDRTEST drivers/gpu/drm/xe/xe_range_fence.h
HDRTEST drivers/gpu/drm/xe/xe_reg_sr.h
HDRTEST drivers/gpu/drm/xe/xe_reg_sr_types.h
HDRTEST drivers/gpu/drm/xe/xe_reg_whitelist.h
HDRTEST drivers/gpu/drm/xe/xe_res_cursor.h
HDRTEST drivers/gpu/drm/xe/xe_ring_ops.h
HDRTEST drivers/gpu/drm/xe/xe_ring_ops_types.h
HDRTEST drivers/gpu/drm/xe/xe_rtp.h
HDRTEST drivers/gpu/drm/xe/xe_rtp_types.h
HDRTEST drivers/gpu/drm/xe/xe_sa.h
HDRTEST drivers/gpu/drm/xe/xe_sa_types.h
HDRTEST drivers/gpu/drm/xe/xe_sched_job.h
HDRTEST drivers/gpu/drm/xe/xe_sched_job_types.h
HDRTEST drivers/gpu/drm/xe/xe_step.h
cc1: all warnings being treated as errors
HDRTEST drivers/gpu/drm/xe/xe_step_types.h
HDRTEST drivers/gpu/drm/xe/xe_sync.h
make[3]: *** [../scripts/Makefile.build:243: drivers/gpu/drm/xe/xe_hwmon.o] Error 1
make[3]: *** Waiting for unfinished jobs....
make[2]: *** [/workspace/kernel/Makefile:2032: drivers/gpu/drm/xe] Error 2
make[1]: *** [/workspace/kernel/Makefile:234: __sub-make] Error 2
make[1]: Leaving directory '/workspace/kernel/build64-default'
make: *** [Makefile:234: __sub-make] Error 2
+ cleanup
+ '[' 1 -eq 1 ']'
+ ./scripts/config --file /workspace/kernel/build64-default/.config --enable CONFIG_DRM_XE_DISPLAY
run-parts: /workspace/ci/hooks/10-build-W1 exited with return code 2
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-xe] ✓ CI.checksparse: success for Add HWMON support for DGFX (rev5)
2023-09-21 10:25 ` Badal Nilawar
` (11 preceding siblings ...)
(?)
@ 2023-09-21 10:31 ` Patchwork
-1 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2023-09-21 10:31 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe
== Series Details ==
Series: Add HWMON support for DGFX (rev5)
URL : https://patchwork.freedesktop.org/series/118934/
State : success
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 57039c55bac31a639ce66355c26fe345f338c075
Sparse version: 0.6.1 (Ubuntu: 0.6.1-2build1)
Fast mode used, each commit won't be checked separately.
Okay!
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Intel-xe] ✗ CI.BAT: failure for Add HWMON support for DGFX (rev5)
2023-09-21 10:25 ` Badal Nilawar
` (12 preceding siblings ...)
(?)
@ 2023-09-21 11:05 ` Patchwork
-1 siblings, 0 replies; 53+ messages in thread
From: Patchwork @ 2023-09-21 11:05 UTC (permalink / raw)
To: Nilawar, Badal; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 4192 bytes --]
== Series Details ==
Series: Add HWMON support for DGFX (rev5)
URL : https://patchwork.freedesktop.org/series/118934/
State : failure
== Summary ==
CI Bug Log - changes from xe-388-57039c55bac31a639ce66355c26fe345f338c075_BAT -> xe-pw-118934v5_BAT
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-118934v5_BAT absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-118934v5_BAT, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (3 -> 4)
------------------------------
Additional (1): bat-pvc-2
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-118934v5_BAT:
### IGT changes ###
#### Possible regressions ####
* igt@core_hotunplug@unbind-rebind:
- bat-dg2-oem2: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-388-57039c55bac31a639ce66355c26fe345f338c075/bat-dg2-oem2/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-118934v5/bat-dg2-oem2/igt@core_hotunplug@unbind-rebind.html
- bat-atsm-2: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-388-57039c55bac31a639ce66355c26fe345f338c075/bat-atsm-2/igt@core_hotunplug@unbind-rebind.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-118934v5/bat-atsm-2/igt@core_hotunplug@unbind-rebind.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-pvc-2: NOTRUN -> [SKIP][5] +63 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-118934v5/bat-pvc-2/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
Known issues
------------
Here are the changes found in xe-pw-118934v5_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- bat-adlp-7: [PASS][6] -> [FAIL][7] ([Intel XE#480])
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-388-57039c55bac31a639ce66355c26fe345f338c075/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-118934v5/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
* igt@xe_intel_bb@intel-bb-blit-y:
- bat-pvc-2: NOTRUN -> [SKIP][8] ([Intel XE#678]) +148 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-118934v5/bat-pvc-2/igt@xe_intel_bb@intel-bb-blit-y.html
* igt@xe_module_load@load:
- bat-pvc-2: NOTRUN -> [SKIP][9] ([Intel XE#378])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-118934v5/bat-pvc-2/igt@xe_module_load@load.html
#### Possible fixes ####
* igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- bat-adlp-7: [FAIL][10] ([Intel XE#480]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-388-57039c55bac31a639ce66355c26fe345f338c075/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-118934v5/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
[Intel XE#480]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/480
[Intel XE#524]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/524
[Intel XE#678]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/678
Build changes
-------------
* Linux: xe-388-57039c55bac31a639ce66355c26fe345f338c075 -> xe-pw-118934v5
IGT_7495: 7ed6190bc4f8a3ebc3f0b8b334e8ae6abae03031 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-388-57039c55bac31a639ce66355c26fe345f338c075: 57039c55bac31a639ce66355c26fe345f338c075
xe-pw-118934v5: 118934v5
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-118934v5/index.html
[-- Attachment #2: Type: text/html, Size: 4953 bytes --]
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 6/6] drm/xe/hwmon: Expose power1_max_interval
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-21 11:43 ` Ghimiray, Himal Prasad
-1 siblings, 0 replies; 53+ messages in thread
From: Ghimiray, Himal Prasad @ 2023-09-21 11:43 UTC (permalink / raw)
To: Badal Nilawar, intel-xe, linux-hwmon; +Cc: linux, rodrigo.vivi
On 21-09-2023 15:55, Badal Nilawar wrote:
> Expose power1_max_interval, that is the tau corresponding to PL1, as a
> custom hwmon attribute. Some bit manipulation is needed because of the
> format of PKG_PWR_LIM_1_TIME in
> PACKAGE_RAPL_LIMIT register (1.x * power(2,y))
>
> v2: Get rpm wake ref while accessing power1_max_interval
> v3: %s/hwmon/xe_hwmon/
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 11 ++
> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 8 +
> drivers/gpu/drm/xe/xe_hwmon.c | 138 +++++++++++++++++-
> 3 files changed, 156 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> index 1a7a6c23e141..9ceb9c04b52b 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -59,3 +59,14 @@ Contact: intel-xe@lists.freedesktop.org
> Description: RO. Energy input of device in microjoules.
>
> Only supported for particular Intel xe graphics platforms.
> +
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
> + milliseconds over which sustained power is averaged.
> +
> + Only supported for particular Intel xe graphics platforms.
> +
> +
> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> index d8ecbe1858d1..519dd1067a19 100644
> --- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> @@ -22,15 +22,23 @@
> #define PKG_TDP GENMASK_ULL(14, 0)
> #define PKG_MIN_PWR GENMASK_ULL(30, 16)
> #define PKG_MAX_PWR GENMASK_ULL(46, 32)
> +#define PKG_MAX_WIN GENMASK_ULL(54, 48)
> +#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
> +#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
> +
>
> #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> #define PKG_PWR_UNIT REG_GENMASK(3, 0)
> #define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
> +#define PKG_TIME_UNIT REG_GENMASK(19, 16)
>
> #define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
>
> #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> #define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> #define PKG_PWR_LIM_1_EN REG_BIT(15)
> +#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
> +#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
> +#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
>
> #endif /* _XE_MCHBAR_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index cb75b9a386c0..dfa638942d47 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -38,6 +38,7 @@ enum xe_hwmon_reg_operation {
> #define SF_CURR 1000 /* milliamperes */
> #define SF_VOLTAGE 1000 /* millivolts */
> #define SF_ENERGY 1000000 /* microjoules */
> +#define SF_TIME 1000 /* milliseconds */
>
> struct hwmon_energy_info {
> u32 reg_val_prev;
> @@ -50,6 +51,7 @@ struct xe_hwmon {
> struct mutex hwmon_lock; /* rmw operations*/
> int scl_shift_power;
> int scl_shift_energy;
> + int scl_shift_time;
> struct hwmon_energy_info ei; /* Energy info for energy1_input */
> };
>
> @@ -255,6 +257,138 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)
> xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> }
>
> +static ssize_t
> +xe_hwmon_power1_max_interval_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + u32 r, x, y, x_w = 2; /* 2 bits */
> + u64 tau4, out;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
> + REG_READ, &r, 0, 0);
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
> + y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
> + /*
> + * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
> + * = (4 | x) << (y - 2)
> + * where (y - 2) ensures a 1.x fixed point representation of 1.x
> + * However because y can be < 2, we compute
> + * tau4 = (4 | x) << y
> + * but add 2 when doing the final right shift to account for units
> + */
> + tau4 = ((1 << x_w) | x) << y;
> + /* val in hwmon interface units (millisec) */
> + out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
> +
> + return sysfs_emit(buf, "%llu\n", out);
> +}
> +
> +static ssize_t
> +xe_hwmon_power1_max_interval_store(struct device *dev, struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + u32 x, y, rxy, x_w = 2; /* 2 bits */
> + u64 tau4, r, max_win;
> + unsigned long val;
> + int ret;
> +
> + ret = kstrtoul(buf, 0, &val);
> + if (ret)
> + return ret;
> +
> + /*
> + * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12
> + * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds
> + */
> +#define PKG_MAX_WIN_DEFAULT 0x12ull
Do we need to determine r, x, y etc for max limit ?
Why cant we simply define MAX_LIMIT 256 ?
BR
Himal
> +
> + /*
> + * val must be < max in hwmon interface units. The steps below are
> + * explained in xe_hwmon_power1_max_interval_show()
> + */
> + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
> + x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
> + y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
> + tau4 = ((1 << x_w) | x) << y;
> + max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
> +
> + if (val > max_win)
> + return -EINVAL;
> +
> + /* val in hw units */
> + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
> + /* Convert to 1.x * power(2,y) */
> + if (!val) {
> + /* Avoid ilog2(0) */
> + y = 0;
> + x = 0;
> + } else {
> + y = ilog2(val);
> + /* x = (val - (1 << y)) >> (y - 2); */
> + x = (val - (1ul << y)) << x_w >> y;
> + }
> +
> + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + mutex_lock(&hwmon->hwmon_lock);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, (u32 *)&r,
> + PKG_PWR_LIM_1_TIME, rxy);
> +
> + mutex_unlock(&hwmon->hwmon_lock);
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return count;
> +}
> +
> +static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
> + xe_hwmon_power1_max_interval_show,
> + xe_hwmon_power1_max_interval_store, 0);
> +
> +static struct attribute *hwmon_attributes[] = {
> + &sensor_dev_attr_power1_max_interval.dev_attr.attr,
> + NULL
> +};
> +
> +static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,
> + struct attribute *attr, int index)
> +{
> + struct device *dev = kobj_to_dev(kobj);
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + u32 reg_val;
> + int ret = 0;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
> + REG_READ, ®_val, 0, 0) ? 0 : attr->mode;
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static const struct attribute_group hwmon_attrgroup = {
> + .attrs = hwmon_attributes,
> + .is_visible = xe_hwmon_attributes_visible,
> +};
> +
> +static const struct attribute_group *hwmon_groups[] = {
> + &hwmon_attrgroup,
> + NULL
> +};
> +
> static const struct hwmon_channel_info *hwmon_info[] = {
> HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
> HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
> @@ -573,6 +707,7 @@ xe_hwmon_get_preregistration_info(struct xe_device *xe)
> if (!ret) {
> hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
> + hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
> }
>
> /*
> @@ -612,7 +747,8 @@ void xe_hwmon_register(struct xe_device *xe)
> "xe",
> hwmon,
> &hwmon_chip_info,
> - NULL);
> + hwmon_groups);
> +
> if (IS_ERR(hwmon->hwmon_dev)) {
> drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
> xe->hwmon = NULL;
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 6/6] drm/xe/hwmon: Expose power1_max_interval
@ 2023-09-21 11:43 ` Ghimiray, Himal Prasad
0 siblings, 0 replies; 53+ messages in thread
From: Ghimiray, Himal Prasad @ 2023-09-21 11:43 UTC (permalink / raw)
To: Badal Nilawar, intel-xe, linux-hwmon; +Cc: linux, rodrigo.vivi
On 21-09-2023 15:55, Badal Nilawar wrote:
> Expose power1_max_interval, that is the tau corresponding to PL1, as a
> custom hwmon attribute. Some bit manipulation is needed because of the
> format of PKG_PWR_LIM_1_TIME in
> PACKAGE_RAPL_LIMIT register (1.x * power(2,y))
>
> v2: Get rpm wake ref while accessing power1_max_interval
> v3: %s/hwmon/xe_hwmon/
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 11 ++
> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 8 +
> drivers/gpu/drm/xe/xe_hwmon.c | 138 +++++++++++++++++-
> 3 files changed, 156 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> index 1a7a6c23e141..9ceb9c04b52b 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -59,3 +59,14 @@ Contact: intel-xe@lists.freedesktop.org
> Description: RO. Energy input of device in microjoules.
>
> Only supported for particular Intel xe graphics platforms.
> +
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
> + milliseconds over which sustained power is averaged.
> +
> + Only supported for particular Intel xe graphics platforms.
> +
> +
> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> index d8ecbe1858d1..519dd1067a19 100644
> --- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> @@ -22,15 +22,23 @@
> #define PKG_TDP GENMASK_ULL(14, 0)
> #define PKG_MIN_PWR GENMASK_ULL(30, 16)
> #define PKG_MAX_PWR GENMASK_ULL(46, 32)
> +#define PKG_MAX_WIN GENMASK_ULL(54, 48)
> +#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
> +#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
> +
>
> #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> #define PKG_PWR_UNIT REG_GENMASK(3, 0)
> #define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
> +#define PKG_TIME_UNIT REG_GENMASK(19, 16)
>
> #define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
>
> #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> #define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> #define PKG_PWR_LIM_1_EN REG_BIT(15)
> +#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
> +#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
> +#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
>
> #endif /* _XE_MCHBAR_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index cb75b9a386c0..dfa638942d47 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -38,6 +38,7 @@ enum xe_hwmon_reg_operation {
> #define SF_CURR 1000 /* milliamperes */
> #define SF_VOLTAGE 1000 /* millivolts */
> #define SF_ENERGY 1000000 /* microjoules */
> +#define SF_TIME 1000 /* milliseconds */
>
> struct hwmon_energy_info {
> u32 reg_val_prev;
> @@ -50,6 +51,7 @@ struct xe_hwmon {
> struct mutex hwmon_lock; /* rmw operations*/
> int scl_shift_power;
> int scl_shift_energy;
> + int scl_shift_time;
> struct hwmon_energy_info ei; /* Energy info for energy1_input */
> };
>
> @@ -255,6 +257,138 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)
> xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> }
>
> +static ssize_t
> +xe_hwmon_power1_max_interval_show(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + u32 r, x, y, x_w = 2; /* 2 bits */
> + u64 tau4, out;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
> + REG_READ, &r, 0, 0);
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
> + y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
> + /*
> + * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
> + * = (4 | x) << (y - 2)
> + * where (y - 2) ensures a 1.x fixed point representation of 1.x
> + * However because y can be < 2, we compute
> + * tau4 = (4 | x) << y
> + * but add 2 when doing the final right shift to account for units
> + */
> + tau4 = ((1 << x_w) | x) << y;
> + /* val in hwmon interface units (millisec) */
> + out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
> +
> + return sysfs_emit(buf, "%llu\n", out);
> +}
> +
> +static ssize_t
> +xe_hwmon_power1_max_interval_store(struct device *dev, struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + u32 x, y, rxy, x_w = 2; /* 2 bits */
> + u64 tau4, r, max_win;
> + unsigned long val;
> + int ret;
> +
> + ret = kstrtoul(buf, 0, &val);
> + if (ret)
> + return ret;
> +
> + /*
> + * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12
> + * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds
> + */
> +#define PKG_MAX_WIN_DEFAULT 0x12ull
Do we need to determine r, x, y etc for max limit ?
Why cant we simply define MAX_LIMIT 256 ?
BR
Himal
> +
> + /*
> + * val must be < max in hwmon interface units. The steps below are
> + * explained in xe_hwmon_power1_max_interval_show()
> + */
> + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
> + x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
> + y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
> + tau4 = ((1 << x_w) | x) << y;
> + max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
> +
> + if (val > max_win)
> + return -EINVAL;
> +
> + /* val in hw units */
> + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME);
> + /* Convert to 1.x * power(2,y) */
> + if (!val) {
> + /* Avoid ilog2(0) */
> + y = 0;
> + x = 0;
> + } else {
> + y = ilog2(val);
> + /* x = (val - (1 << y)) >> (y - 2); */
> + x = (val - (1ul << y)) << x_w >> y;
> + }
> +
> + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + mutex_lock(&hwmon->hwmon_lock);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, (u32 *)&r,
> + PKG_PWR_LIM_1_TIME, rxy);
> +
> + mutex_unlock(&hwmon->hwmon_lock);
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return count;
> +}
> +
> +static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
> + xe_hwmon_power1_max_interval_show,
> + xe_hwmon_power1_max_interval_store, 0);
> +
> +static struct attribute *hwmon_attributes[] = {
> + &sensor_dev_attr_power1_max_interval.dev_attr.attr,
> + NULL
> +};
> +
> +static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,
> + struct attribute *attr, int index)
> +{
> + struct device *dev = kobj_to_dev(kobj);
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + u32 reg_val;
> + int ret = 0;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
> + REG_READ, ®_val, 0, 0) ? 0 : attr->mode;
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static const struct attribute_group hwmon_attrgroup = {
> + .attrs = hwmon_attributes,
> + .is_visible = xe_hwmon_attributes_visible,
> +};
> +
> +static const struct attribute_group *hwmon_groups[] = {
> + &hwmon_attrgroup,
> + NULL
> +};
> +
> static const struct hwmon_channel_info *hwmon_info[] = {
> HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
> HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
> @@ -573,6 +707,7 @@ xe_hwmon_get_preregistration_info(struct xe_device *xe)
> if (!ret) {
> hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
> + hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit);
> }
>
> /*
> @@ -612,7 +747,8 @@ void xe_hwmon_register(struct xe_device *xe)
> "xe",
> hwmon,
> &hwmon_chip_info,
> - NULL);
> + hwmon_groups);
> +
> if (IS_ERR(hwmon->hwmon_dev)) {
> drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
> xe->hwmon = NULL;
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-21 13:22 ` Riana Tauro
-1 siblings, 0 replies; 53+ messages in thread
From: Riana Tauro @ 2023-09-21 13:22 UTC (permalink / raw)
To: Badal Nilawar, intel-xe, linux-hwmon; +Cc: rodrigo.vivi, linux
On 9/21/2023 3:55 PM, Badal Nilawar wrote:
> Expose Card reactive sustained (pl1) power limit as power_max and
> card default power limit (tdp) as power_rated_max.
>
> v2:
> - Fix review comments (Riana)
> v3:
> - Use drmm_mutex_init (Matt Brost)
> - Print error value (Matt Brost)
> - Convert enums to uppercase (Matt Brost)
> - Avoid extra reg read in hwmon_is_visible function (Riana)
> - Use xe_device_assert_mem_access when applicable (Matt Brost)
> - Add intel-xe@lists.freedesktop.org in Documentation (Matt Brost)
> v4:
> - Use prefix xe_hwmon prefix for all functions (Matt Brost/Andi)
> - %s/hwmon_reg/xe_hwmon_reg (Andi)
> - Fix review comments (Guenter/Andi)
> v5:
> - Fix review comments (Riana)
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 22 ++
> drivers/gpu/drm/xe/Makefile | 3 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +
> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 33 ++
> drivers/gpu/drm/xe/xe_device.c | 3 +
> drivers/gpu/drm/xe/xe_device_types.h | 2 +
> drivers/gpu/drm/xe/xe_hwmon.c | 358 ++++++++++++++++++
> drivers/gpu/drm/xe/xe_hwmon.h | 20 +
> 8 files changed, 445 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> create mode 100644 drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.c
> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.h
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> new file mode 100644
> index 000000000000..da0197a29fe4
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -0,0 +1,22 @@
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RW. Card reactive sustained (PL1) power limit in microwatts.
> +
> + The power controller will throttle the operating frequency
> + if the power averaged over a window (typically seconds)
> + exceeds this limit. A read value of 0 means that the PL1
> + power limit is disabled, writing 0 disables the
> + limit. Writing values > 0 and <= TDP will enable the power limit.
> +
> + Only supported for particular Intel xe graphics platforms.
> +
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RO. Card default power limit (default TDP setting).
> +
> + Only supported for particular Intel xe graphics platforms.
> +
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 86c8bd4c05a3..ca77aff60d48 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -117,6 +117,9 @@ xe-y += xe_bb.o \
> xe_wa.o \
> xe_wopcm.o
>
> +# graphics hardware monitoring (HWMON) support
> +xe-$(CONFIG_HWMON) += xe_hwmon.o
> +
> # i915 Display compat #defines and #includes
> subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
> -I$(srctree)/$(src)/display/ext \
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index e13fbbdf6929..679cdba9f383 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -410,4 +410,8 @@
> #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
> #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
>
> +#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
> +#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
> +#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> new file mode 100644
> index 000000000000..27f1d42baf6d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_MCHBAR_REGS_H_
> +#define _XE_MCHBAR_REGS_H_
> +
> +#include "regs/xe_reg_defs.h"
> +
> +/*
> + * MCHBAR mirror.
> + *
> + * This mirrors the MCHBAR MMIO space whose location is determined by
> + * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
> + * every way.
> + */
> +
> +#define MCHBAR_MIRROR_BASE_SNB 0x140000
> +
> +#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
> +#define PKG_TDP GENMASK_ULL(14, 0)
> +#define PKG_MIN_PWR GENMASK_ULL(30, 16)
> +#define PKG_MAX_PWR GENMASK_ULL(46, 32)
> +
> +#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> +#define PKG_PWR_UNIT REG_GENMASK(3, 0)
> +
> +#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> +#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> +#define PKG_PWR_LIM_1_EN REG_BIT(15)
> +
> +#endif /* _XE_MCHBAR_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index b6bcb6c3482e..2acdc22a6027 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -34,6 +34,7 @@
> #include "xe_vm.h"
> #include "xe_vm_madvise.h"
> #include "xe_wait_user_fence.h"
> +#include "xe_hwmon.h"
Should be alphabetical
>
> #ifdef CONFIG_LOCKDEP
> struct lockdep_map xe_device_mem_access_lockdep_map = {
> @@ -337,6 +338,8 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_pmu_register(&xe->pmu);
>
> + xe_hwmon_register(xe);
> +
> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index a82f28c6a3a0..d1e319f305ef 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -365,6 +365,8 @@ struct xe_device {
> /** @pmu: performance monitoring unit */
> struct xe_pmu pmu;
>
> + struct xe_hwmon *hwmon;
> +
> /* private: */
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> new file mode 100644
> index 000000000000..7f4599d98541
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -0,0 +1,358 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <linux/hwmon.h>
> +
> +#include <drm/drm_managed.h>
> +#include "regs/xe_gt_regs.h"
> +#include "regs/xe_mchbar_regs.h"
> +#include "xe_device.h"
> +#include "xe_gt.h"
> +#include "xe_hwmon.h"
> +#include "xe_mmio.h"
> +
> +enum xe_hwmon_reg {
> + REG_PKG_RAPL_LIMIT,
> + REG_PKG_POWER_SKU,
> + REG_PKG_POWER_SKU_UNIT,
> +};
> +
> +enum xe_hwmon_reg_operation {
> + REG_READ,
> + REG_WRITE,
> + REG_RMW,
> +};
> +
> +/*
> + * SF_* - scale factors for particular quantities according to hwmon spec.
> + */
> +#define SF_POWER 1000000 /* microwatts */
> +
> +struct xe_hwmon {
> + struct device *hwmon_dev;
> + struct xe_gt *gt;
> + struct mutex hwmon_lock; /* rmw operations*/
> + int scl_shift_power;
> +};
> +
> +static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
> +{
> + struct xe_device *xe = gt_to_xe(hwmon->gt);
> + struct xe_reg reg = XE_REG(0);
> +
> + switch (hwmon_reg) {
> + case REG_PKG_RAPL_LIMIT:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_RAPL_LIMIT;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_RAPL_LIMIT;
> + break;
> + case REG_PKG_POWER_SKU:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_POWER_SKU;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_POWER_SKU;
> + break;
> + case REG_PKG_POWER_SKU_UNIT:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_POWER_SKU_UNIT;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;
> + break;
> + default:
> + XE_MISSING_CASE(hwmon_reg);
> + break;
> + }
> +
> + return reg.raw;
> +}
> +
> +static int xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
> + enum xe_hwmon_reg_operation operation, u32 *value,
> + u32 clr, u32 set)
> +{
> + struct xe_reg reg;
> +
> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
> +
> + if (!reg.raw)
> + return -EOPNOTSUPP;
> +
> + switch (operation) {
> + case REG_READ:
> + *value = xe_mmio_read32(hwmon->gt, reg);
> + return 0;
> + case REG_WRITE:
> + xe_mmio_write32(hwmon->gt, reg, *value);
> + return 0;
> + case REG_RMW:
> + *value = xe_mmio_rmw32(hwmon->gt, reg, clr, set);
> + return 0;
> + default:
> + XE_MISSING_CASE(operation);
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +int xe_hwmon_process_reg_read64(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, u64 *value)
> +{
> + struct xe_reg reg;
> +
> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
> +
> + if (!reg.raw)
> + return -EOPNOTSUPP;
> +
> + *value = xe_mmio_read64_2x32(hwmon->gt, reg);
> +
> + return 0;
> +}
> +
> +#define PL1_DISABLE 0
> +
> +/*
> + * HW allows arbitrary PL1 limits to be set but silently clamps these values to
> + * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the
> + * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
> + * clamped values when read.
> + */
> +static int xe_hwmon_power_max_read(struct xe_hwmon *hwmon, long *value)
> +{
> + u32 reg_val;
> + u64 reg_val64, min, max;
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val, 0, 0);
> + /* Check if PL1 limit is disabled */
> + if (!(reg_val & PKG_PWR_LIM_1_EN)) {
> + *value = PL1_DISABLE;
> + return 0;
> + }
> +
> + reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);
> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
> +
> + xe_hwmon_process_reg_read64(hwmon, REG_PKG_POWER_SKU, ®_val64);
> + min = REG_FIELD_GET(PKG_MIN_PWR, reg_val64);
> + min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
> + max = REG_FIELD_GET(PKG_MAX_PWR, reg_val64);
> + max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
> +
> + if (min && max)
> + *value = clamp_t(u64, *value, min, max);
> +
> + return 0;
> +}
> +
> +static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
> +{
> + u32 reg_val;
> +
> + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
> + if (value == PL1_DISABLE) {
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> +
> + if (reg_val & PKG_PWR_LIM_1_EN)
> + return -ENODEV;
> + }
> +
> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
> + reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
> + reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
> +
> + return 0;
> +}
> +
> +static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
> +{
> + u32 reg_val;
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ, ®_val, 0, 0);
> + reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
> +
> + return 0;
> +}
> +
> +static const struct hwmon_channel_info *hwmon_info[] = {
> + HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
> + NULL
> +};
> +
> +static umode_t
> +xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
> + case hwmon_power_rated_max:
> + return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_power_max_read(hwmon, val);
> + case hwmon_power_rated_max:
> + return xe_hwmon_power_rated_max_read(hwmon, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static int
> +xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_power_max_write(hwmon, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static umode_t
> +xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> + u32 attr, int channel)
> +{
> + struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata;
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
> + break;
> + default:
> + ret = 0;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static int
> +xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long *val)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_read(hwmon, attr, channel, val);
> + break;
> + default:
> + ret = -EOPNOTSUPP;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static int
> +xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long val)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_write(hwmon, attr, channel, val);
> + break;
> + default:
> + ret = -EOPNOTSUPP;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static const struct hwmon_ops hwmon_ops = {
> + .is_visible = xe_hwmon_is_visible,
> + .read = xe_hwmon_read,
> + .write = xe_hwmon_write,
> +};
> +
> +static const struct hwmon_chip_info hwmon_chip_info = {
> + .ops = &hwmon_ops,
> + .info = hwmon_info,
> +};
> +
> +static void
> +xe_hwmon_get_preregistration_info(struct xe_device *xe)
> +{
> + struct xe_hwmon *hwmon = xe->hwmon;
> + u32 val_sku_unit = 0;
> + int ret;
> +
> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU_UNIT, REG_READ, &val_sku_unit, 0, 0);
> + /*
> + * The contents of register PKG_POWER_SKU_UNIT do not change,
> + * so read it once and store the shift values.
> + */
> + if (!ret)
> + hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> +}
> +
> +void xe_hwmon_register(struct xe_device *xe)
> +{
> + struct device *dev = xe->drm.dev;
> + struct xe_hwmon *hwmon;
> +
> + /* hwmon is available only for dGfx */
> + if (!IS_DGFX(xe))
> + return;
> +
> + hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
> + if (!hwmon)
> + return;
> +
> + xe->hwmon = hwmon;
> +
> + drmm_mutex_init(&xe->drm, &hwmon->hwmon_lock);
> +
> + /* primary GT to access device level properties */
> + hwmon->gt = xe->tiles[0].primary_gt;
> +
> + xe_hwmon_get_preregistration_info(xe);
> +
> + drm_dbg(&xe->drm, "Register xe hwmon interface\n");
> +
> + /* hwmon_dev points to device hwmon<i> */
> + hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
> + "xe",
> + hwmon,
> + &hwmon_chip_info,
> + NULL);
> + if (IS_ERR(hwmon->hwmon_dev)) {
> + drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
> + xe->hwmon = NULL;
> + return;
> + }
> +}
> +
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.h b/drivers/gpu/drm/xe/xe_hwmon.h
> new file mode 100644
> index 000000000000..1ec45cf1d19b
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hwmon.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: MIT */
> +
Remove blank line
With the above comments
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_HWMON_H_
> +#define _XE_HWMON_H_
> +
> +#include <linux/types.h>
> +
> +struct xe_device;
> +
> +#if IS_REACHABLE(CONFIG_HWMON)
> +void xe_hwmon_register(struct xe_device *xe);
> +#else
> +static inline void xe_hwmon_register(struct xe_device *xe) { };
> +#endif
> +
> +#endif /* _XE_HWMON_H_ */
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
@ 2023-09-21 13:22 ` Riana Tauro
0 siblings, 0 replies; 53+ messages in thread
From: Riana Tauro @ 2023-09-21 13:22 UTC (permalink / raw)
To: Badal Nilawar, intel-xe, linux-hwmon
Cc: anshuman.gupta, ashutosh.dixit, linux, andi.shyti, matthew.brost,
rodrigo.vivi
On 9/21/2023 3:55 PM, Badal Nilawar wrote:
> Expose Card reactive sustained (pl1) power limit as power_max and
> card default power limit (tdp) as power_rated_max.
>
> v2:
> - Fix review comments (Riana)
> v3:
> - Use drmm_mutex_init (Matt Brost)
> - Print error value (Matt Brost)
> - Convert enums to uppercase (Matt Brost)
> - Avoid extra reg read in hwmon_is_visible function (Riana)
> - Use xe_device_assert_mem_access when applicable (Matt Brost)
> - Add intel-xe@lists.freedesktop.org in Documentation (Matt Brost)
> v4:
> - Use prefix xe_hwmon prefix for all functions (Matt Brost/Andi)
> - %s/hwmon_reg/xe_hwmon_reg (Andi)
> - Fix review comments (Guenter/Andi)
> v5:
> - Fix review comments (Riana)
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 22 ++
> drivers/gpu/drm/xe/Makefile | 3 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +
> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 33 ++
> drivers/gpu/drm/xe/xe_device.c | 3 +
> drivers/gpu/drm/xe/xe_device_types.h | 2 +
> drivers/gpu/drm/xe/xe_hwmon.c | 358 ++++++++++++++++++
> drivers/gpu/drm/xe/xe_hwmon.h | 20 +
> 8 files changed, 445 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> create mode 100644 drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.c
> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.h
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> new file mode 100644
> index 000000000000..da0197a29fe4
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -0,0 +1,22 @@
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RW. Card reactive sustained (PL1) power limit in microwatts.
> +
> + The power controller will throttle the operating frequency
> + if the power averaged over a window (typically seconds)
> + exceeds this limit. A read value of 0 means that the PL1
> + power limit is disabled, writing 0 disables the
> + limit. Writing values > 0 and <= TDP will enable the power limit.
> +
> + Only supported for particular Intel xe graphics platforms.
> +
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RO. Card default power limit (default TDP setting).
> +
> + Only supported for particular Intel xe graphics platforms.
> +
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 86c8bd4c05a3..ca77aff60d48 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -117,6 +117,9 @@ xe-y += xe_bb.o \
> xe_wa.o \
> xe_wopcm.o
>
> +# graphics hardware monitoring (HWMON) support
> +xe-$(CONFIG_HWMON) += xe_hwmon.o
> +
> # i915 Display compat #defines and #includes
> subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
> -I$(srctree)/$(src)/display/ext \
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index e13fbbdf6929..679cdba9f383 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -410,4 +410,8 @@
> #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
> #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
>
> +#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
> +#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
> +#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> new file mode 100644
> index 000000000000..27f1d42baf6d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_MCHBAR_REGS_H_
> +#define _XE_MCHBAR_REGS_H_
> +
> +#include "regs/xe_reg_defs.h"
> +
> +/*
> + * MCHBAR mirror.
> + *
> + * This mirrors the MCHBAR MMIO space whose location is determined by
> + * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
> + * every way.
> + */
> +
> +#define MCHBAR_MIRROR_BASE_SNB 0x140000
> +
> +#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
> +#define PKG_TDP GENMASK_ULL(14, 0)
> +#define PKG_MIN_PWR GENMASK_ULL(30, 16)
> +#define PKG_MAX_PWR GENMASK_ULL(46, 32)
> +
> +#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> +#define PKG_PWR_UNIT REG_GENMASK(3, 0)
> +
> +#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> +#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> +#define PKG_PWR_LIM_1_EN REG_BIT(15)
> +
> +#endif /* _XE_MCHBAR_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index b6bcb6c3482e..2acdc22a6027 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -34,6 +34,7 @@
> #include "xe_vm.h"
> #include "xe_vm_madvise.h"
> #include "xe_wait_user_fence.h"
> +#include "xe_hwmon.h"
Should be alphabetical
>
> #ifdef CONFIG_LOCKDEP
> struct lockdep_map xe_device_mem_access_lockdep_map = {
> @@ -337,6 +338,8 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_pmu_register(&xe->pmu);
>
> + xe_hwmon_register(xe);
> +
> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index a82f28c6a3a0..d1e319f305ef 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -365,6 +365,8 @@ struct xe_device {
> /** @pmu: performance monitoring unit */
> struct xe_pmu pmu;
>
> + struct xe_hwmon *hwmon;
> +
> /* private: */
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> new file mode 100644
> index 000000000000..7f4599d98541
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -0,0 +1,358 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <linux/hwmon.h>
> +
> +#include <drm/drm_managed.h>
> +#include "regs/xe_gt_regs.h"
> +#include "regs/xe_mchbar_regs.h"
> +#include "xe_device.h"
> +#include "xe_gt.h"
> +#include "xe_hwmon.h"
> +#include "xe_mmio.h"
> +
> +enum xe_hwmon_reg {
> + REG_PKG_RAPL_LIMIT,
> + REG_PKG_POWER_SKU,
> + REG_PKG_POWER_SKU_UNIT,
> +};
> +
> +enum xe_hwmon_reg_operation {
> + REG_READ,
> + REG_WRITE,
> + REG_RMW,
> +};
> +
> +/*
> + * SF_* - scale factors for particular quantities according to hwmon spec.
> + */
> +#define SF_POWER 1000000 /* microwatts */
> +
> +struct xe_hwmon {
> + struct device *hwmon_dev;
> + struct xe_gt *gt;
> + struct mutex hwmon_lock; /* rmw operations*/
> + int scl_shift_power;
> +};
> +
> +static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
> +{
> + struct xe_device *xe = gt_to_xe(hwmon->gt);
> + struct xe_reg reg = XE_REG(0);
> +
> + switch (hwmon_reg) {
> + case REG_PKG_RAPL_LIMIT:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_RAPL_LIMIT;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_RAPL_LIMIT;
> + break;
> + case REG_PKG_POWER_SKU:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_POWER_SKU;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_POWER_SKU;
> + break;
> + case REG_PKG_POWER_SKU_UNIT:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_POWER_SKU_UNIT;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;
> + break;
> + default:
> + XE_MISSING_CASE(hwmon_reg);
> + break;
> + }
> +
> + return reg.raw;
> +}
> +
> +static int xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
> + enum xe_hwmon_reg_operation operation, u32 *value,
> + u32 clr, u32 set)
> +{
> + struct xe_reg reg;
> +
> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
> +
> + if (!reg.raw)
> + return -EOPNOTSUPP;
> +
> + switch (operation) {
> + case REG_READ:
> + *value = xe_mmio_read32(hwmon->gt, reg);
> + return 0;
> + case REG_WRITE:
> + xe_mmio_write32(hwmon->gt, reg, *value);
> + return 0;
> + case REG_RMW:
> + *value = xe_mmio_rmw32(hwmon->gt, reg, clr, set);
> + return 0;
> + default:
> + XE_MISSING_CASE(operation);
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +int xe_hwmon_process_reg_read64(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, u64 *value)
> +{
> + struct xe_reg reg;
> +
> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
> +
> + if (!reg.raw)
> + return -EOPNOTSUPP;
> +
> + *value = xe_mmio_read64_2x32(hwmon->gt, reg);
> +
> + return 0;
> +}
> +
> +#define PL1_DISABLE 0
> +
> +/*
> + * HW allows arbitrary PL1 limits to be set but silently clamps these values to
> + * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the
> + * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
> + * clamped values when read.
> + */
> +static int xe_hwmon_power_max_read(struct xe_hwmon *hwmon, long *value)
> +{
> + u32 reg_val;
> + u64 reg_val64, min, max;
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val, 0, 0);
> + /* Check if PL1 limit is disabled */
> + if (!(reg_val & PKG_PWR_LIM_1_EN)) {
> + *value = PL1_DISABLE;
> + return 0;
> + }
> +
> + reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);
> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
> +
> + xe_hwmon_process_reg_read64(hwmon, REG_PKG_POWER_SKU, ®_val64);
> + min = REG_FIELD_GET(PKG_MIN_PWR, reg_val64);
> + min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
> + max = REG_FIELD_GET(PKG_MAX_PWR, reg_val64);
> + max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
> +
> + if (min && max)
> + *value = clamp_t(u64, *value, min, max);
> +
> + return 0;
> +}
> +
> +static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
> +{
> + u32 reg_val;
> +
> + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
> + if (value == PL1_DISABLE) {
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> +
> + if (reg_val & PKG_PWR_LIM_1_EN)
> + return -ENODEV;
> + }
> +
> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
> + reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
> + reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
> +
> + return 0;
> +}
> +
> +static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
> +{
> + u32 reg_val;
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ, ®_val, 0, 0);
> + reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
> +
> + return 0;
> +}
> +
> +static const struct hwmon_channel_info *hwmon_info[] = {
> + HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
> + NULL
> +};
> +
> +static umode_t
> +xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
> + case hwmon_power_rated_max:
> + return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_power_max_read(hwmon, val);
> + case hwmon_power_rated_max:
> + return xe_hwmon_power_rated_max_read(hwmon, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static int
> +xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_power_max_write(hwmon, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static umode_t
> +xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> + u32 attr, int channel)
> +{
> + struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata;
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
> + break;
> + default:
> + ret = 0;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static int
> +xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long *val)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_read(hwmon, attr, channel, val);
> + break;
> + default:
> + ret = -EOPNOTSUPP;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static int
> +xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long val)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_write(hwmon, attr, channel, val);
> + break;
> + default:
> + ret = -EOPNOTSUPP;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static const struct hwmon_ops hwmon_ops = {
> + .is_visible = xe_hwmon_is_visible,
> + .read = xe_hwmon_read,
> + .write = xe_hwmon_write,
> +};
> +
> +static const struct hwmon_chip_info hwmon_chip_info = {
> + .ops = &hwmon_ops,
> + .info = hwmon_info,
> +};
> +
> +static void
> +xe_hwmon_get_preregistration_info(struct xe_device *xe)
> +{
> + struct xe_hwmon *hwmon = xe->hwmon;
> + u32 val_sku_unit = 0;
> + int ret;
> +
> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU_UNIT, REG_READ, &val_sku_unit, 0, 0);
> + /*
> + * The contents of register PKG_POWER_SKU_UNIT do not change,
> + * so read it once and store the shift values.
> + */
> + if (!ret)
> + hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> +}
> +
> +void xe_hwmon_register(struct xe_device *xe)
> +{
> + struct device *dev = xe->drm.dev;
> + struct xe_hwmon *hwmon;
> +
> + /* hwmon is available only for dGfx */
> + if (!IS_DGFX(xe))
> + return;
> +
> + hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
> + if (!hwmon)
> + return;
> +
> + xe->hwmon = hwmon;
> +
> + drmm_mutex_init(&xe->drm, &hwmon->hwmon_lock);
> +
> + /* primary GT to access device level properties */
> + hwmon->gt = xe->tiles[0].primary_gt;
> +
> + xe_hwmon_get_preregistration_info(xe);
> +
> + drm_dbg(&xe->drm, "Register xe hwmon interface\n");
> +
> + /* hwmon_dev points to device hwmon<i> */
> + hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
> + "xe",
> + hwmon,
> + &hwmon_chip_info,
> + NULL);
> + if (IS_ERR(hwmon->hwmon_dev)) {
> + drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
> + xe->hwmon = NULL;
> + return;
> + }
> +}
> +
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.h b/drivers/gpu/drm/xe/xe_hwmon.h
> new file mode 100644
> index 000000000000..1ec45cf1d19b
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hwmon.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: MIT */
> +
Remove blank line
With the above comments
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_HWMON_H_
> +#define _XE_HWMON_H_
> +
> +#include <linux/types.h>
> +
> +struct xe_device;
> +
> +#if IS_REACHABLE(CONFIG_HWMON)
> +void xe_hwmon_register(struct xe_device *xe);
> +#else
> +static inline void xe_hwmon_register(struct xe_device *xe) { };
> +#endif
> +
> +#endif /* _XE_HWMON_H_ */
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 5/6] drm/xe/hwmon: Expose hwmon energy attribute
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-21 14:09 ` Riana Tauro
-1 siblings, 0 replies; 53+ messages in thread
From: Riana Tauro @ 2023-09-21 14:09 UTC (permalink / raw)
To: Badal Nilawar, intel-xe, linux-hwmon; +Cc: rodrigo.vivi, linux
Hi Badal
On 9/21/2023 3:55 PM, Badal Nilawar wrote:
> Expose hwmon energy attribute to show device level energy usage
>
> v2:
> - %s/hwm_/hwmon_/
> - Convert enums to upper case
> v3:
> - %s/hwmon_/xe_hwmon
> - Remove gt specific hwmon attributes
> v4:
> - %s/REG_PKG_ENERGY_STATUS/REG_ENERGY_STATUS_ALL (Riana)
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 7 ++
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 3 +
> drivers/gpu/drm/xe/xe_hwmon.c | 105 +++++++++++++++++-
> 4 files changed, 116 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> index 7f9407c20864..1a7a6c23e141 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -52,3 +52,10 @@ Description: RO. Current Voltage in millivolt.
>
> Only supported for particular Intel xe graphics platforms.
>
> +What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RO. Energy input of device in microjoules.
> +
> + Only supported for particular Intel xe graphics platforms.
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 102663cbc320..9e6ce74fdd68 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -413,8 +413,10 @@
> #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
> #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
>
> +#define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004)
This is not used in the file
> #define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
> #define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
> +#define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
> #define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
>
> #endif
> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> index 27f1d42baf6d..d8ecbe1858d1 100644
> --- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> @@ -25,6 +25,9 @@
>
> #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> #define PKG_PWR_UNIT REG_GENMASK(3, 0)
> +#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
> +
> +#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
>
> #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> #define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 431995045faa..cb75b9a386c0 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -22,6 +22,7 @@ enum xe_hwmon_reg {
> REG_PKG_POWER_SKU,
> REG_PKG_POWER_SKU_UNIT,
> REG_GT_PERF_STATUS,
> + REG_PKG_ENERGY_STATUS,
PVC register above has it PLATFORM. Is PKG okay incase the other
register is added later?
> };
>
> enum xe_hwmon_reg_operation {
> @@ -36,12 +37,20 @@ enum xe_hwmon_reg_operation {
> #define SF_POWER 1000000 /* microwatts */
> #define SF_CURR 1000 /* milliamperes */
> #define SF_VOLTAGE 1000 /* millivolts */
> +#define SF_ENERGY 1000000 /* microjoules */
> +
> +struct hwmon_energy_info {
Better to retain xe prefix since all the enums and structs have the
prefix across the file
With the above changes
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
> + u32 reg_val_prev;
> + long accum_energy; /* Accumulated energy for energy1_input */
> +};
>
> struct xe_hwmon {
> struct device *hwmon_dev;
> struct xe_gt *gt;
> struct mutex hwmon_lock; /* rmw operations*/
> int scl_shift_power;
> + int scl_shift_energy;
> + struct hwmon_energy_info ei; /* Energy info for energy1_input */
> };
>
> static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
> @@ -72,6 +81,12 @@ static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
> if (xe->info.platform == XE_DG2)
> reg = GT_PERF_STATUS;
> break;
> + case REG_PKG_ENERGY_STATUS:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_ENERGY_STATUS;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PLATFORM_ENERGY_STATUS;
> + break;
> default:
> XE_MISSING_CASE(hwmon_reg);
> break;
> @@ -192,10 +207,59 @@ static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
> return 0;
> }
>
> +/*
> + * xe_hwmon_energy_get - Obtain energy value
> + *
> + * The underlying energy hardware register is 32-bits and is subject to
> + * overflow. How long before overflow? For example, with an example
> + * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and
> + * a power draw of 1000 watts, the 32-bit counter will overflow in
> + * approximately 4.36 minutes.
> + *
> + * Examples:
> + * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days
> + * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes
> + *
> + * The function significantly increases overflow duration (from 4.36
> + * minutes) by accumulating the energy register into a 'long' as allowed by
> + * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()),
> + * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and
> + * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
> + * energy1_input overflows. This at 1000 W is an overflow duration of 278 years.
> + */
> +static void
> +xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)
> +{
> + struct hwmon_energy_info *ei = &hwmon->ei;
> + u32 reg_val;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + mutex_lock(&hwmon->hwmon_lock);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_ENERGY_STATUS, REG_READ,
> + ®_val, 0, 0);
> +
> + if (reg_val >= ei->reg_val_prev)
> + ei->accum_energy += reg_val - ei->reg_val_prev;
> + else
> + ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val;
> +
> + ei->reg_val_prev = reg_val;
> +
> + *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,
> + hwmon->scl_shift_energy);
> +
> + mutex_unlock(&hwmon->hwmon_lock);
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +}
> +
> static const struct hwmon_channel_info *hwmon_info[] = {
> HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
> HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
> HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
> + HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
> NULL
> };
>
> @@ -369,6 +433,29 @@ xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, long *val)
> return ret;
> }
>
> +static umode_t
> +xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr)
> +{
> + switch (attr) {
> + case hwmon_energy_input:
> + return xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS) ? 0444 : 0;
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, long *val)
> +{
> + switch (attr) {
> + case hwmon_energy_input:
> + xe_hwmon_energy_get(hwmon, val);
> + return 0;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> static umode_t
> xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> u32 attr, int channel)
> @@ -388,6 +475,9 @@ xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> case hwmon_in:
> ret = xe_hwmon_in_is_visible(hwmon, attr);
> break;
> + case hwmon_energy:
> + ret = xe_hwmon_energy_is_visible(hwmon, attr);
> + break;
> default:
> ret = 0;
> break;
> @@ -417,6 +507,9 @@ xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> case hwmon_in:
> ret = xe_hwmon_in_read(hwmon, attr, val);
> break;
> + case hwmon_energy:
> + ret = xe_hwmon_energy_read(hwmon, attr, val);
> + break;
> default:
> ret = -EOPNOTSUPP;
> break;
> @@ -468,6 +561,7 @@ static void
> xe_hwmon_get_preregistration_info(struct xe_device *xe)
> {
> struct xe_hwmon *hwmon = xe->hwmon;
> + long energy;
> u32 val_sku_unit = 0;
> int ret;
>
> @@ -476,8 +570,17 @@ xe_hwmon_get_preregistration_info(struct xe_device *xe)
> * The contents of register PKG_POWER_SKU_UNIT do not change,
> * so read it once and store the shift values.
> */
> - if (!ret)
> + if (!ret) {
> hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> + hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
> + }
> +
> + /*
> + * Initialize 'struct hwmon_energy_info', i.e. set fields to the
> + * first value of the energy register read
> + */
> + if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, 0))
> + xe_hwmon_energy_get(hwmon, &energy);
> }
>
> void xe_hwmon_register(struct xe_device *xe)
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v5 5/6] drm/xe/hwmon: Expose hwmon energy attribute
@ 2023-09-21 14:09 ` Riana Tauro
0 siblings, 0 replies; 53+ messages in thread
From: Riana Tauro @ 2023-09-21 14:09 UTC (permalink / raw)
To: Badal Nilawar, intel-xe, linux-hwmon
Cc: anshuman.gupta, ashutosh.dixit, linux, andi.shyti, matthew.brost,
rodrigo.vivi
Hi Badal
On 9/21/2023 3:55 PM, Badal Nilawar wrote:
> Expose hwmon energy attribute to show device level energy usage
>
> v2:
> - %s/hwm_/hwmon_/
> - Convert enums to upper case
> v3:
> - %s/hwmon_/xe_hwmon
> - Remove gt specific hwmon attributes
> v4:
> - %s/REG_PKG_ENERGY_STATUS/REG_ENERGY_STATUS_ALL (Riana)
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 7 ++
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +
> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 3 +
> drivers/gpu/drm/xe/xe_hwmon.c | 105 +++++++++++++++++-
> 4 files changed, 116 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> index 7f9407c20864..1a7a6c23e141 100644
> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -52,3 +52,10 @@ Description: RO. Current Voltage in millivolt.
>
> Only supported for particular Intel xe graphics platforms.
>
> +What: /sys/devices/.../hwmon/hwmon<i>/energy1_input
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RO. Energy input of device in microjoules.
> +
> + Only supported for particular Intel xe graphics platforms.
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 102663cbc320..9e6ce74fdd68 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -413,8 +413,10 @@
> #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
> #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
>
> +#define PVC_GT0_PACKAGE_ENERGY_STATUS XE_REG(0x281004)
This is not used in the file
> #define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
> #define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
> +#define PVC_GT0_PLATFORM_ENERGY_STATUS XE_REG(0x28106c)
> #define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
>
> #endif
> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> index 27f1d42baf6d..d8ecbe1858d1 100644
> --- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> @@ -25,6 +25,9 @@
>
> #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> #define PKG_PWR_UNIT REG_GENMASK(3, 0)
> +#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
> +
> +#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
>
> #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> #define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> index 431995045faa..cb75b9a386c0 100644
> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -22,6 +22,7 @@ enum xe_hwmon_reg {
> REG_PKG_POWER_SKU,
> REG_PKG_POWER_SKU_UNIT,
> REG_GT_PERF_STATUS,
> + REG_PKG_ENERGY_STATUS,
PVC register above has it PLATFORM. Is PKG okay incase the other
register is added later?
> };
>
> enum xe_hwmon_reg_operation {
> @@ -36,12 +37,20 @@ enum xe_hwmon_reg_operation {
> #define SF_POWER 1000000 /* microwatts */
> #define SF_CURR 1000 /* milliamperes */
> #define SF_VOLTAGE 1000 /* millivolts */
> +#define SF_ENERGY 1000000 /* microjoules */
> +
> +struct hwmon_energy_info {
Better to retain xe prefix since all the enums and structs have the
prefix across the file
With the above changes
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
> + u32 reg_val_prev;
> + long accum_energy; /* Accumulated energy for energy1_input */
> +};
>
> struct xe_hwmon {
> struct device *hwmon_dev;
> struct xe_gt *gt;
> struct mutex hwmon_lock; /* rmw operations*/
> int scl_shift_power;
> + int scl_shift_energy;
> + struct hwmon_energy_info ei; /* Energy info for energy1_input */
> };
>
> static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
> @@ -72,6 +81,12 @@ static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
> if (xe->info.platform == XE_DG2)
> reg = GT_PERF_STATUS;
> break;
> + case REG_PKG_ENERGY_STATUS:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_ENERGY_STATUS;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PLATFORM_ENERGY_STATUS;
> + break;
> default:
> XE_MISSING_CASE(hwmon_reg);
> break;
> @@ -192,10 +207,59 @@ static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
> return 0;
> }
>
> +/*
> + * xe_hwmon_energy_get - Obtain energy value
> + *
> + * The underlying energy hardware register is 32-bits and is subject to
> + * overflow. How long before overflow? For example, with an example
> + * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and
> + * a power draw of 1000 watts, the 32-bit counter will overflow in
> + * approximately 4.36 minutes.
> + *
> + * Examples:
> + * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days
> + * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes
> + *
> + * The function significantly increases overflow duration (from 4.36
> + * minutes) by accumulating the energy register into a 'long' as allowed by
> + * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()),
> + * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and
> + * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before
> + * energy1_input overflows. This at 1000 W is an overflow duration of 278 years.
> + */
> +static void
> +xe_hwmon_energy_get(struct xe_hwmon *hwmon, long *energy)
> +{
> + struct hwmon_energy_info *ei = &hwmon->ei;
> + u32 reg_val;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + mutex_lock(&hwmon->hwmon_lock);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_ENERGY_STATUS, REG_READ,
> + ®_val, 0, 0);
> +
> + if (reg_val >= ei->reg_val_prev)
> + ei->accum_energy += reg_val - ei->reg_val_prev;
> + else
> + ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val;
> +
> + ei->reg_val_prev = reg_val;
> +
> + *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY,
> + hwmon->scl_shift_energy);
> +
> + mutex_unlock(&hwmon->hwmon_lock);
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +}
> +
> static const struct hwmon_channel_info *hwmon_info[] = {
> HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT),
> HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
> HWMON_CHANNEL_INFO(in, HWMON_I_INPUT),
> + HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT),
> NULL
> };
>
> @@ -369,6 +433,29 @@ xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, long *val)
> return ret;
> }
>
> +static umode_t
> +xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr)
> +{
> + switch (attr) {
> + case hwmon_energy_input:
> + return xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS) ? 0444 : 0;
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, long *val)
> +{
> + switch (attr) {
> + case hwmon_energy_input:
> + xe_hwmon_energy_get(hwmon, val);
> + return 0;
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> static umode_t
> xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> u32 attr, int channel)
> @@ -388,6 +475,9 @@ xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> case hwmon_in:
> ret = xe_hwmon_in_is_visible(hwmon, attr);
> break;
> + case hwmon_energy:
> + ret = xe_hwmon_energy_is_visible(hwmon, attr);
> + break;
> default:
> ret = 0;
> break;
> @@ -417,6 +507,9 @@ xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> case hwmon_in:
> ret = xe_hwmon_in_read(hwmon, attr, val);
> break;
> + case hwmon_energy:
> + ret = xe_hwmon_energy_read(hwmon, attr, val);
> + break;
> default:
> ret = -EOPNOTSUPP;
> break;
> @@ -468,6 +561,7 @@ static void
> xe_hwmon_get_preregistration_info(struct xe_device *xe)
> {
> struct xe_hwmon *hwmon = xe->hwmon;
> + long energy;
> u32 val_sku_unit = 0;
> int ret;
>
> @@ -476,8 +570,17 @@ xe_hwmon_get_preregistration_info(struct xe_device *xe)
> * The contents of register PKG_POWER_SKU_UNIT do not change,
> * so read it once and store the shift values.
> */
> - if (!ret)
> + if (!ret) {
> hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> + hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit);
> + }
> +
> + /*
> + * Initialize 'struct hwmon_energy_info', i.e. set fields to the
> + * first value of the energy register read
> + */
> + if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, 0))
> + xe_hwmon_energy_get(hwmon, &energy);
> }
>
> void xe_hwmon_register(struct xe_device *xe)
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-21 16:03 ` Rodrigo Vivi
-1 siblings, 0 replies; 53+ messages in thread
From: Rodrigo Vivi @ 2023-09-21 16:03 UTC (permalink / raw)
To: Badal Nilawar; +Cc: linux-hwmon, intel-xe, linux
On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
> Add XE_MISSING_CASE macro to handle missing switch case
>
> v2: Add comment about macro usage (Himal)
>
> Cc: Andi Shyti <andi.shyti@linux.intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
> drivers/gpu/drm/xe/xe_macros.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
> index daf56c846d03..6c74c69920ed 100644
> --- a/drivers/gpu/drm/xe/xe_macros.h
> +++ b/drivers/gpu/drm/xe/xe_macros.h
> @@ -15,4 +15,8 @@
> "Ioctl argument check failed at %s:%d: %s", \
> __FILE__, __LINE__, #cond), 1))
>
> +/* Parameter to macro should be a variable name */
> +#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
> + __stringify(x), (long)(x))
> +
No, please! Let's not add unnecessary macros.
> #endif
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
@ 2023-09-21 16:03 ` Rodrigo Vivi
0 siblings, 0 replies; 53+ messages in thread
From: Rodrigo Vivi @ 2023-09-21 16:03 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, linux-hwmon, anshuman.gupta, ashutosh.dixit, linux,
andi.shyti, riana.tauro, matthew.brost
On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
> Add XE_MISSING_CASE macro to handle missing switch case
>
> v2: Add comment about macro usage (Himal)
>
> Cc: Andi Shyti <andi.shyti@linux.intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
> drivers/gpu/drm/xe/xe_macros.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
> index daf56c846d03..6c74c69920ed 100644
> --- a/drivers/gpu/drm/xe/xe_macros.h
> +++ b/drivers/gpu/drm/xe/xe_macros.h
> @@ -15,4 +15,8 @@
> "Ioctl argument check failed at %s:%d: %s", \
> __FILE__, __LINE__, #cond), 1))
>
> +/* Parameter to macro should be a variable name */
> +#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
> + __stringify(x), (long)(x))
> +
No, please! Let's not add unnecessary macros.
> #endif
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-21 16:25 ` Rodrigo Vivi
-1 siblings, 0 replies; 53+ messages in thread
From: Rodrigo Vivi @ 2023-09-21 16:25 UTC (permalink / raw)
To: Badal Nilawar; +Cc: linux-hwmon, intel-xe, linux
On Thu, Sep 21, 2023 at 03:55:15PM +0530, Badal Nilawar wrote:
> Expose Card reactive sustained (pl1) power limit as power_max and
> card default power limit (tdp) as power_rated_max.
>
> v2:
> - Fix review comments (Riana)
> v3:
> - Use drmm_mutex_init (Matt Brost)
> - Print error value (Matt Brost)
> - Convert enums to uppercase (Matt Brost)
> - Avoid extra reg read in hwmon_is_visible function (Riana)
> - Use xe_device_assert_mem_access when applicable (Matt Brost)
> - Add intel-xe@lists.freedesktop.org in Documentation (Matt Brost)
> v4:
> - Use prefix xe_hwmon prefix for all functions (Matt Brost/Andi)
> - %s/hwmon_reg/xe_hwmon_reg (Andi)
> - Fix review comments (Guenter/Andi)
> v5:
> - Fix review comments (Riana)
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 22 ++
> drivers/gpu/drm/xe/Makefile | 3 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +
> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 33 ++
> drivers/gpu/drm/xe/xe_device.c | 3 +
> drivers/gpu/drm/xe/xe_device_types.h | 2 +
> drivers/gpu/drm/xe/xe_hwmon.c | 358 ++++++++++++++++++
> drivers/gpu/drm/xe/xe_hwmon.h | 20 +
> 8 files changed, 445 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> create mode 100644 drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.c
> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.h
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> new file mode 100644
> index 000000000000..da0197a29fe4
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -0,0 +1,22 @@
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RW. Card reactive sustained (PL1) power limit in microwatts.
> +
> + The power controller will throttle the operating frequency
> + if the power averaged over a window (typically seconds)
> + exceeds this limit. A read value of 0 means that the PL1
> + power limit is disabled, writing 0 disables the
> + limit. Writing values > 0 and <= TDP will enable the power limit.
> +
> + Only supported for particular Intel xe graphics platforms.
> +
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RO. Card default power limit (default TDP setting).
> +
> + Only supported for particular Intel xe graphics platforms.
> +
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 86c8bd4c05a3..ca77aff60d48 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -117,6 +117,9 @@ xe-y += xe_bb.o \
> xe_wa.o \
> xe_wopcm.o
>
> +# graphics hardware monitoring (HWMON) support
> +xe-$(CONFIG_HWMON) += xe_hwmon.o
> +
> # i915 Display compat #defines and #includes
> subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
> -I$(srctree)/$(src)/display/ext \
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index e13fbbdf6929..679cdba9f383 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -410,4 +410,8 @@
> #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
> #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
>
> +#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
> +#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
> +#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> new file mode 100644
> index 000000000000..27f1d42baf6d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_MCHBAR_REGS_H_
> +#define _XE_MCHBAR_REGS_H_
> +
> +#include "regs/xe_reg_defs.h"
> +
> +/*
> + * MCHBAR mirror.
> + *
> + * This mirrors the MCHBAR MMIO space whose location is determined by
> + * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
> + * every way.
> + */
> +
> +#define MCHBAR_MIRROR_BASE_SNB 0x140000
> +
> +#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
> +#define PKG_TDP GENMASK_ULL(14, 0)
> +#define PKG_MIN_PWR GENMASK_ULL(30, 16)
> +#define PKG_MAX_PWR GENMASK_ULL(46, 32)
> +
> +#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> +#define PKG_PWR_UNIT REG_GENMASK(3, 0)
> +
> +#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> +#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> +#define PKG_PWR_LIM_1_EN REG_BIT(15)
> +
> +#endif /* _XE_MCHBAR_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index b6bcb6c3482e..2acdc22a6027 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -34,6 +34,7 @@
> #include "xe_vm.h"
> #include "xe_vm_madvise.h"
> #include "xe_wait_user_fence.h"
> +#include "xe_hwmon.h"
>
> #ifdef CONFIG_LOCKDEP
> struct lockdep_map xe_device_mem_access_lockdep_map = {
> @@ -337,6 +338,8 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_pmu_register(&xe->pmu);
>
> + xe_hwmon_register(xe);
> +
> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index a82f28c6a3a0..d1e319f305ef 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -365,6 +365,8 @@ struct xe_device {
> /** @pmu: performance monitoring unit */
> struct xe_pmu pmu;
>
> + struct xe_hwmon *hwmon;
> +
> /* private: */
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> new file mode 100644
> index 000000000000..7f4599d98541
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -0,0 +1,358 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <linux/hwmon.h>
> +
> +#include <drm/drm_managed.h>
> +#include "regs/xe_gt_regs.h"
> +#include "regs/xe_mchbar_regs.h"
> +#include "xe_device.h"
> +#include "xe_gt.h"
> +#include "xe_hwmon.h"
> +#include "xe_mmio.h"
> +
> +enum xe_hwmon_reg {
> + REG_PKG_RAPL_LIMIT,
> + REG_PKG_POWER_SKU,
> + REG_PKG_POWER_SKU_UNIT,
> +};
> +
> +enum xe_hwmon_reg_operation {
> + REG_READ,
> + REG_WRITE,
> + REG_RMW,
> +};
> +
> +/*
> + * SF_* - scale factors for particular quantities according to hwmon spec.
> + */
> +#define SF_POWER 1000000 /* microwatts */
> +
> +struct xe_hwmon {
> + struct device *hwmon_dev;
> + struct xe_gt *gt;
> + struct mutex hwmon_lock; /* rmw operations*/
> + int scl_shift_power;
> +};
> +
> +static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
> +{
> + struct xe_device *xe = gt_to_xe(hwmon->gt);
> + struct xe_reg reg = XE_REG(0);
> +
> + switch (hwmon_reg) {
> + case REG_PKG_RAPL_LIMIT:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_RAPL_LIMIT;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_RAPL_LIMIT;
> + break;
> + case REG_PKG_POWER_SKU:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_POWER_SKU;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_POWER_SKU;
> + break;
> + case REG_PKG_POWER_SKU_UNIT:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_POWER_SKU_UNIT;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;
> + break;
> + default:
> + XE_MISSING_CASE(hwmon_reg);
> + break;
> + }
> +
> + return reg.raw;
> +}
> +
> +static int xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
> + enum xe_hwmon_reg_operation operation, u32 *value,
> + u32 clr, u32 set)
> +{
> + struct xe_reg reg;
> +
> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
> +
> + if (!reg.raw)
> + return -EOPNOTSUPP;
> +
> + switch (operation) {
> + case REG_READ:
> + *value = xe_mmio_read32(hwmon->gt, reg);
> + return 0;
> + case REG_WRITE:
> + xe_mmio_write32(hwmon->gt, reg, *value);
> + return 0;
> + case REG_RMW:
> + *value = xe_mmio_rmw32(hwmon->gt, reg, clr, set);
> + return 0;
> + default:
> + XE_MISSING_CASE(operation);
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +int xe_hwmon_process_reg_read64(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, u64 *value)
> +{
> + struct xe_reg reg;
> +
> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
> +
> + if (!reg.raw)
> + return -EOPNOTSUPP;
> +
> + *value = xe_mmio_read64_2x32(hwmon->gt, reg);
> +
> + return 0;
> +}
> +
> +#define PL1_DISABLE 0
> +
> +/*
> + * HW allows arbitrary PL1 limits to be set but silently clamps these values to
> + * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the
> + * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
> + * clamped values when read.
> + */
> +static int xe_hwmon_power_max_read(struct xe_hwmon *hwmon, long *value)
> +{
> + u32 reg_val;
> + u64 reg_val64, min, max;
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val, 0, 0);
> + /* Check if PL1 limit is disabled */
> + if (!(reg_val & PKG_PWR_LIM_1_EN)) {
> + *value = PL1_DISABLE;
> + return 0;
> + }
> +
> + reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);
> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
> +
> + xe_hwmon_process_reg_read64(hwmon, REG_PKG_POWER_SKU, ®_val64);
> + min = REG_FIELD_GET(PKG_MIN_PWR, reg_val64);
> + min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
> + max = REG_FIELD_GET(PKG_MAX_PWR, reg_val64);
> + max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
> +
> + if (min && max)
> + *value = clamp_t(u64, *value, min, max);
> +
> + return 0;
> +}
> +
> +static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
> +{
> + u32 reg_val;
> +
> + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
> + if (value == PL1_DISABLE) {
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> +
> + if (reg_val & PKG_PWR_LIM_1_EN)
> + return -ENODEV;
> + }
> +
> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
> + reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
> + reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
> +
> + return 0;
> +}
> +
> +static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
> +{
> + u32 reg_val;
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ, ®_val, 0, 0);
> + reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
> +
> + return 0;
> +}
> +
> +static const struct hwmon_channel_info *hwmon_info[] = {
> + HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
> + NULL
> +};
> +
> +static umode_t
> +xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
> + case hwmon_power_rated_max:
> + return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_power_max_read(hwmon, val);
> + case hwmon_power_rated_max:
> + return xe_hwmon_power_rated_max_read(hwmon, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static int
> +xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_power_max_write(hwmon, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static umode_t
> +xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> + u32 attr, int channel)
> +{
> + struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata;
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
> + break;
> + default:
> + ret = 0;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static int
> +xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long *val)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_read(hwmon, attr, channel, val);
> + break;
> + default:
> + ret = -EOPNOTSUPP;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static int
> +xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long val)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_write(hwmon, attr, channel, val);
> + break;
> + default:
> + ret = -EOPNOTSUPP;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static const struct hwmon_ops hwmon_ops = {
> + .is_visible = xe_hwmon_is_visible,
> + .read = xe_hwmon_read,
> + .write = xe_hwmon_write,
> +};
> +
> +static const struct hwmon_chip_info hwmon_chip_info = {
> + .ops = &hwmon_ops,
> + .info = hwmon_info,
> +};
> +
> +static void
> +xe_hwmon_get_preregistration_info(struct xe_device *xe)
> +{
> + struct xe_hwmon *hwmon = xe->hwmon;
> + u32 val_sku_unit = 0;
> + int ret;
> +
> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU_UNIT, REG_READ, &val_sku_unit, 0, 0);
> + /*
> + * The contents of register PKG_POWER_SKU_UNIT do not change,
> + * so read it once and store the shift values.
> + */
> + if (!ret)
> + hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> +}
> +
> +void xe_hwmon_register(struct xe_device *xe)
> +{
> + struct device *dev = xe->drm.dev;
> + struct xe_hwmon *hwmon;
> +
> + /* hwmon is available only for dGfx */
> + if (!IS_DGFX(xe))
> + return;
> +
> + hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
> + if (!hwmon)
> + return;
> +
> + xe->hwmon = hwmon;
> +
> + drmm_mutex_init(&xe->drm, &hwmon->hwmon_lock);
> +
> + /* primary GT to access device level properties */
> + hwmon->gt = xe->tiles[0].primary_gt;
So, what happens with the other tiles?
We should get them in since the beginning since that will impose
interface changes and bigger changes on IGT tests.
> +
> + xe_hwmon_get_preregistration_info(xe);
> +
> + drm_dbg(&xe->drm, "Register xe hwmon interface\n");
> +
> + /* hwmon_dev points to device hwmon<i> */
> + hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
> + "xe",
> + hwmon,
> + &hwmon_chip_info,
> + NULL);
> + if (IS_ERR(hwmon->hwmon_dev)) {
> + drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
> + xe->hwmon = NULL;
> + return;
> + }
> +}
> +
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.h b/drivers/gpu/drm/xe/xe_hwmon.h
> new file mode 100644
> index 000000000000..1ec45cf1d19b
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hwmon.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: MIT */
> +
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_HWMON_H_
> +#define _XE_HWMON_H_
> +
> +#include <linux/types.h>
> +
> +struct xe_device;
> +
> +#if IS_REACHABLE(CONFIG_HWMON)
> +void xe_hwmon_register(struct xe_device *xe);
> +#else
> +static inline void xe_hwmon_register(struct xe_device *xe) { };
> +#endif
> +
> +#endif /* _XE_HWMON_H_ */
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
@ 2023-09-21 16:25 ` Rodrigo Vivi
0 siblings, 0 replies; 53+ messages in thread
From: Rodrigo Vivi @ 2023-09-21 16:25 UTC (permalink / raw)
To: Badal Nilawar; +Cc: intel-xe, linux-hwmon, linux
On Thu, Sep 21, 2023 at 03:55:15PM +0530, Badal Nilawar wrote:
> Expose Card reactive sustained (pl1) power limit as power_max and
> card default power limit (tdp) as power_rated_max.
>
> v2:
> - Fix review comments (Riana)
> v3:
> - Use drmm_mutex_init (Matt Brost)
> - Print error value (Matt Brost)
> - Convert enums to uppercase (Matt Brost)
> - Avoid extra reg read in hwmon_is_visible function (Riana)
> - Use xe_device_assert_mem_access when applicable (Matt Brost)
> - Add intel-xe@lists.freedesktop.org in Documentation (Matt Brost)
> v4:
> - Use prefix xe_hwmon prefix for all functions (Matt Brost/Andi)
> - %s/hwmon_reg/xe_hwmon_reg (Andi)
> - Fix review comments (Guenter/Andi)
> v5:
> - Fix review comments (Riana)
>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 22 ++
> drivers/gpu/drm/xe/Makefile | 3 +
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +
> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 33 ++
> drivers/gpu/drm/xe/xe_device.c | 3 +
> drivers/gpu/drm/xe/xe_device_types.h | 2 +
> drivers/gpu/drm/xe/xe_hwmon.c | 358 ++++++++++++++++++
> drivers/gpu/drm/xe/xe_hwmon.h | 20 +
> 8 files changed, 445 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> create mode 100644 drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.c
> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.h
>
> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> new file mode 100644
> index 000000000000..da0197a29fe4
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> @@ -0,0 +1,22 @@
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RW. Card reactive sustained (PL1) power limit in microwatts.
> +
> + The power controller will throttle the operating frequency
> + if the power averaged over a window (typically seconds)
> + exceeds this limit. A read value of 0 means that the PL1
> + power limit is disabled, writing 0 disables the
> + limit. Writing values > 0 and <= TDP will enable the power limit.
> +
> + Only supported for particular Intel xe graphics platforms.
> +
> +What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max
> +Date: September 2023
> +KernelVersion: 6.5
> +Contact: intel-xe@lists.freedesktop.org
> +Description: RO. Card default power limit (default TDP setting).
> +
> + Only supported for particular Intel xe graphics platforms.
> +
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index 86c8bd4c05a3..ca77aff60d48 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -117,6 +117,9 @@ xe-y += xe_bb.o \
> xe_wa.o \
> xe_wopcm.o
>
> +# graphics hardware monitoring (HWMON) support
> +xe-$(CONFIG_HWMON) += xe_hwmon.o
> +
> # i915 Display compat #defines and #includes
> subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
> -I$(srctree)/$(src)/display/ext \
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index e13fbbdf6929..679cdba9f383 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -410,4 +410,8 @@
> #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
> #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
>
> +#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
> +#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
> +#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
> +
> #endif
> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> new file mode 100644
> index 000000000000..27f1d42baf6d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_MCHBAR_REGS_H_
> +#define _XE_MCHBAR_REGS_H_
> +
> +#include "regs/xe_reg_defs.h"
> +
> +/*
> + * MCHBAR mirror.
> + *
> + * This mirrors the MCHBAR MMIO space whose location is determined by
> + * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
> + * every way.
> + */
> +
> +#define MCHBAR_MIRROR_BASE_SNB 0x140000
> +
> +#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
> +#define PKG_TDP GENMASK_ULL(14, 0)
> +#define PKG_MIN_PWR GENMASK_ULL(30, 16)
> +#define PKG_MAX_PWR GENMASK_ULL(46, 32)
> +
> +#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> +#define PKG_PWR_UNIT REG_GENMASK(3, 0)
> +
> +#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> +#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> +#define PKG_PWR_LIM_1_EN REG_BIT(15)
> +
> +#endif /* _XE_MCHBAR_REGS_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> index b6bcb6c3482e..2acdc22a6027 100644
> --- a/drivers/gpu/drm/xe/xe_device.c
> +++ b/drivers/gpu/drm/xe/xe_device.c
> @@ -34,6 +34,7 @@
> #include "xe_vm.h"
> #include "xe_vm_madvise.h"
> #include "xe_wait_user_fence.h"
> +#include "xe_hwmon.h"
>
> #ifdef CONFIG_LOCKDEP
> struct lockdep_map xe_device_mem_access_lockdep_map = {
> @@ -337,6 +338,8 @@ int xe_device_probe(struct xe_device *xe)
>
> xe_pmu_register(&xe->pmu);
>
> + xe_hwmon_register(xe);
> +
> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index a82f28c6a3a0..d1e319f305ef 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -365,6 +365,8 @@ struct xe_device {
> /** @pmu: performance monitoring unit */
> struct xe_pmu pmu;
>
> + struct xe_hwmon *hwmon;
> +
> /* private: */
>
> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
> new file mode 100644
> index 000000000000..7f4599d98541
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> @@ -0,0 +1,358 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#include <linux/hwmon.h>
> +
> +#include <drm/drm_managed.h>
> +#include "regs/xe_gt_regs.h"
> +#include "regs/xe_mchbar_regs.h"
> +#include "xe_device.h"
> +#include "xe_gt.h"
> +#include "xe_hwmon.h"
> +#include "xe_mmio.h"
> +
> +enum xe_hwmon_reg {
> + REG_PKG_RAPL_LIMIT,
> + REG_PKG_POWER_SKU,
> + REG_PKG_POWER_SKU_UNIT,
> +};
> +
> +enum xe_hwmon_reg_operation {
> + REG_READ,
> + REG_WRITE,
> + REG_RMW,
> +};
> +
> +/*
> + * SF_* - scale factors for particular quantities according to hwmon spec.
> + */
> +#define SF_POWER 1000000 /* microwatts */
> +
> +struct xe_hwmon {
> + struct device *hwmon_dev;
> + struct xe_gt *gt;
> + struct mutex hwmon_lock; /* rmw operations*/
> + int scl_shift_power;
> +};
> +
> +static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
> +{
> + struct xe_device *xe = gt_to_xe(hwmon->gt);
> + struct xe_reg reg = XE_REG(0);
> +
> + switch (hwmon_reg) {
> + case REG_PKG_RAPL_LIMIT:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_RAPL_LIMIT;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_RAPL_LIMIT;
> + break;
> + case REG_PKG_POWER_SKU:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_POWER_SKU;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_POWER_SKU;
> + break;
> + case REG_PKG_POWER_SKU_UNIT:
> + if (xe->info.platform == XE_DG2)
> + reg = PCU_CR_PACKAGE_POWER_SKU_UNIT;
> + else if (xe->info.platform == XE_PVC)
> + reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;
> + break;
> + default:
> + XE_MISSING_CASE(hwmon_reg);
> + break;
> + }
> +
> + return reg.raw;
> +}
> +
> +static int xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
> + enum xe_hwmon_reg_operation operation, u32 *value,
> + u32 clr, u32 set)
> +{
> + struct xe_reg reg;
> +
> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
> +
> + if (!reg.raw)
> + return -EOPNOTSUPP;
> +
> + switch (operation) {
> + case REG_READ:
> + *value = xe_mmio_read32(hwmon->gt, reg);
> + return 0;
> + case REG_WRITE:
> + xe_mmio_write32(hwmon->gt, reg, *value);
> + return 0;
> + case REG_RMW:
> + *value = xe_mmio_rmw32(hwmon->gt, reg, clr, set);
> + return 0;
> + default:
> + XE_MISSING_CASE(operation);
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +int xe_hwmon_process_reg_read64(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, u64 *value)
> +{
> + struct xe_reg reg;
> +
> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
> +
> + if (!reg.raw)
> + return -EOPNOTSUPP;
> +
> + *value = xe_mmio_read64_2x32(hwmon->gt, reg);
> +
> + return 0;
> +}
> +
> +#define PL1_DISABLE 0
> +
> +/*
> + * HW allows arbitrary PL1 limits to be set but silently clamps these values to
> + * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the
> + * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
> + * clamped values when read.
> + */
> +static int xe_hwmon_power_max_read(struct xe_hwmon *hwmon, long *value)
> +{
> + u32 reg_val;
> + u64 reg_val64, min, max;
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val, 0, 0);
> + /* Check if PL1 limit is disabled */
> + if (!(reg_val & PKG_PWR_LIM_1_EN)) {
> + *value = PL1_DISABLE;
> + return 0;
> + }
> +
> + reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);
> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
> +
> + xe_hwmon_process_reg_read64(hwmon, REG_PKG_POWER_SKU, ®_val64);
> + min = REG_FIELD_GET(PKG_MIN_PWR, reg_val64);
> + min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
> + max = REG_FIELD_GET(PKG_MAX_PWR, reg_val64);
> + max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
> +
> + if (min && max)
> + *value = clamp_t(u64, *value, min, max);
> +
> + return 0;
> +}
> +
> +static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
> +{
> + u32 reg_val;
> +
> + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
> + if (value == PL1_DISABLE) {
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> +
> + if (reg_val & PKG_PWR_LIM_1_EN)
> + return -ENODEV;
> + }
> +
> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
> + reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
> + reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
> +
> + return 0;
> +}
> +
> +static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
> +{
> + u32 reg_val;
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ, ®_val, 0, 0);
> + reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
> +
> + return 0;
> +}
> +
> +static const struct hwmon_channel_info *hwmon_info[] = {
> + HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
> + NULL
> +};
> +
> +static umode_t
> +xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
> + case hwmon_power_rated_max:
> + return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
> + default:
> + return 0;
> + }
> +}
> +
> +static int
> +xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_power_max_read(hwmon, val);
> + case hwmon_power_rated_max:
> + return xe_hwmon_power_rated_max_read(hwmon, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static int
> +xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
> +{
> + switch (attr) {
> + case hwmon_power_max:
> + return xe_hwmon_power_max_write(hwmon, val);
> + default:
> + return -EOPNOTSUPP;
> + }
> +}
> +
> +static umode_t
> +xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
> + u32 attr, int channel)
> +{
> + struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata;
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
> + break;
> + default:
> + ret = 0;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static int
> +xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long *val)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_read(hwmon, attr, channel, val);
> + break;
> + default:
> + ret = -EOPNOTSUPP;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static int
> +xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
> + int channel, long val)
> +{
> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> + int ret;
> +
> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> +
> + switch (type) {
> + case hwmon_power:
> + ret = xe_hwmon_power_write(hwmon, attr, channel, val);
> + break;
> + default:
> + ret = -EOPNOTSUPP;
> + break;
> + }
> +
> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> +
> + return ret;
> +}
> +
> +static const struct hwmon_ops hwmon_ops = {
> + .is_visible = xe_hwmon_is_visible,
> + .read = xe_hwmon_read,
> + .write = xe_hwmon_write,
> +};
> +
> +static const struct hwmon_chip_info hwmon_chip_info = {
> + .ops = &hwmon_ops,
> + .info = hwmon_info,
> +};
> +
> +static void
> +xe_hwmon_get_preregistration_info(struct xe_device *xe)
> +{
> + struct xe_hwmon *hwmon = xe->hwmon;
> + u32 val_sku_unit = 0;
> + int ret;
> +
> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU_UNIT, REG_READ, &val_sku_unit, 0, 0);
> + /*
> + * The contents of register PKG_POWER_SKU_UNIT do not change,
> + * so read it once and store the shift values.
> + */
> + if (!ret)
> + hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
> +}
> +
> +void xe_hwmon_register(struct xe_device *xe)
> +{
> + struct device *dev = xe->drm.dev;
> + struct xe_hwmon *hwmon;
> +
> + /* hwmon is available only for dGfx */
> + if (!IS_DGFX(xe))
> + return;
> +
> + hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
> + if (!hwmon)
> + return;
> +
> + xe->hwmon = hwmon;
> +
> + drmm_mutex_init(&xe->drm, &hwmon->hwmon_lock);
> +
> + /* primary GT to access device level properties */
> + hwmon->gt = xe->tiles[0].primary_gt;
So, what happens with the other tiles?
We should get them in since the beginning since that will impose
interface changes and bigger changes on IGT tests.
> +
> + xe_hwmon_get_preregistration_info(xe);
> +
> + drm_dbg(&xe->drm, "Register xe hwmon interface\n");
> +
> + /* hwmon_dev points to device hwmon<i> */
> + hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
> + "xe",
> + hwmon,
> + &hwmon_chip_info,
> + NULL);
> + if (IS_ERR(hwmon->hwmon_dev)) {
> + drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
> + xe->hwmon = NULL;
> + return;
> + }
> +}
> +
> diff --git a/drivers/gpu/drm/xe/xe_hwmon.h b/drivers/gpu/drm/xe/xe_hwmon.h
> new file mode 100644
> index 000000000000..1ec45cf1d19b
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_hwmon.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: MIT */
> +
> +/*
> + * Copyright © 2023 Intel Corporation
> + */
> +
> +#ifndef _XE_HWMON_H_
> +#define _XE_HWMON_H_
> +
> +#include <linux/types.h>
> +
> +struct xe_device;
> +
> +#if IS_REACHABLE(CONFIG_HWMON)
> +void xe_hwmon_register(struct xe_device *xe);
> +#else
> +static inline void xe_hwmon_register(struct xe_device *xe) { };
> +#endif
> +
> +#endif /* _XE_HWMON_H_ */
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
2023-09-21 16:03 ` Rodrigo Vivi
@ 2023-09-21 16:59 ` Nilawar, Badal
-1 siblings, 0 replies; 53+ messages in thread
From: Nilawar, Badal @ 2023-09-21 16:59 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: linux-hwmon, intel-xe, linux
On 21-09-2023 21:33, Rodrigo Vivi wrote:
> On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
>> Add XE_MISSING_CASE macro to handle missing switch case
>>
>> v2: Add comment about macro usage (Himal)
>>
>> Cc: Andi Shyti <andi.shyti@linux.intel.com>
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_macros.h | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
>> index daf56c846d03..6c74c69920ed 100644
>> --- a/drivers/gpu/drm/xe/xe_macros.h
>> +++ b/drivers/gpu/drm/xe/xe_macros.h
>> @@ -15,4 +15,8 @@
>> "Ioctl argument check failed at %s:%d: %s", \
>> __FILE__, __LINE__, #cond), 1))
>>
>> +/* Parameter to macro should be a variable name */
>> +#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
>> + __stringify(x), (long)(x))
>> +
>
> No, please! Let's not add unnecessary macros.
This was suggested by Andy, in fact he suggested to reuse existing
MISSING_CASE macro from i915. As I couldn't find common place to move it
I went with creating new one.
I will drop this patch and simply use drm_warn.
Regards,
Badal
>
>> #endif
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
@ 2023-09-21 16:59 ` Nilawar, Badal
0 siblings, 0 replies; 53+ messages in thread
From: Nilawar, Badal @ 2023-09-21 16:59 UTC (permalink / raw)
To: Rodrigo Vivi
Cc: intel-xe, linux-hwmon, anshuman.gupta, ashutosh.dixit, linux,
andi.shyti, riana.tauro, matthew.brost
On 21-09-2023 21:33, Rodrigo Vivi wrote:
> On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
>> Add XE_MISSING_CASE macro to handle missing switch case
>>
>> v2: Add comment about macro usage (Himal)
>>
>> Cc: Andi Shyti <andi.shyti@linux.intel.com>
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_macros.h | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
>> index daf56c846d03..6c74c69920ed 100644
>> --- a/drivers/gpu/drm/xe/xe_macros.h
>> +++ b/drivers/gpu/drm/xe/xe_macros.h
>> @@ -15,4 +15,8 @@
>> "Ioctl argument check failed at %s:%d: %s", \
>> __FILE__, __LINE__, #cond), 1))
>>
>> +/* Parameter to macro should be a variable name */
>> +#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
>> + __stringify(x), (long)(x))
>> +
>
> No, please! Let's not add unnecessary macros.
This was suggested by Andy, in fact he suggested to reuse existing
MISSING_CASE macro from i915. As I couldn't find common place to move it
I went with creating new one.
I will drop this patch and simply use drm_warn.
Regards,
Badal
>
>> #endif
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 6/6] drm/xe/hwmon: Expose power1_max_interval
2023-09-21 11:43 ` Ghimiray, Himal Prasad
@ 2023-09-22 9:49 ` Nilawar, Badal
-1 siblings, 0 replies; 53+ messages in thread
From: Nilawar, Badal @ 2023-09-22 9:49 UTC (permalink / raw)
To: Ghimiray, Himal Prasad, intel-xe, linux-hwmon; +Cc: linux, rodrigo.vivi
On 21-09-2023 17:13, Ghimiray, Himal Prasad wrote:
>
> On 21-09-2023 15:55, Badal Nilawar wrote:
>> Expose power1_max_interval, that is the tau corresponding to PL1, as a
>> custom hwmon attribute. Some bit manipulation is needed because of the
>> format of PKG_PWR_LIM_1_TIME in
>> PACKAGE_RAPL_LIMIT register (1.x * power(2,y))
>>
>> v2: Get rpm wake ref while accessing power1_max_interval
>> v3: %s/hwmon/xe_hwmon/
>>
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> ---
>> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 11 ++
>> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 8 +
>> drivers/gpu/drm/xe/xe_hwmon.c | 138 +++++++++++++++++-
>> 3 files changed, 156 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> index 1a7a6c23e141..9ceb9c04b52b 100644
>> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> @@ -59,3 +59,14 @@ Contact: intel-xe@lists.freedesktop.org
>> Description: RO. Energy input of device in microjoules.
>> Only supported for particular Intel xe graphics platforms.
>> +
>> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
>> +Date: September 2023
>> +KernelVersion: 6.5
>> +Contact: intel-xe@lists.freedesktop.org
>> +Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
>> + milliseconds over which sustained power is averaged.
>> +
>> + Only supported for particular Intel xe graphics platforms.
>> +
>> +
>> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> index d8ecbe1858d1..519dd1067a19 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> @@ -22,15 +22,23 @@
>> #define PKG_TDP GENMASK_ULL(14, 0)
>> #define PKG_MIN_PWR GENMASK_ULL(30, 16)
>> #define PKG_MAX_PWR GENMASK_ULL(46, 32)
>> +#define PKG_MAX_WIN GENMASK_ULL(54, 48)
>> +#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
>> +#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
>> +
>> #define PCU_CR_PACKAGE_POWER_SKU_UNIT
>> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
>> #define PKG_PWR_UNIT REG_GENMASK(3, 0)
>> #define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
>> +#define PKG_TIME_UNIT REG_GENMASK(19, 16)
>> #define PCU_CR_PACKAGE_ENERGY_STATUS
>> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
>> #define PCU_CR_PACKAGE_RAPL_LIMIT
>> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
>> #define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
>> #define PKG_PWR_LIM_1_EN REG_BIT(15)
>> +#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
>> +#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
>> +#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
>> #endif /* _XE_MCHBAR_REGS_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c
>> b/drivers/gpu/drm/xe/xe_hwmon.c
>> index cb75b9a386c0..dfa638942d47 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -38,6 +38,7 @@ enum xe_hwmon_reg_operation {
>> #define SF_CURR 1000 /* milliamperes */
>> #define SF_VOLTAGE 1000 /* millivolts */
>> #define SF_ENERGY 1000000 /* microjoules */
>> +#define SF_TIME 1000 /* milliseconds */
>> struct hwmon_energy_info {
>> u32 reg_val_prev;
>> @@ -50,6 +51,7 @@ struct xe_hwmon {
>> struct mutex hwmon_lock; /* rmw operations*/
>> int scl_shift_power;
>> int scl_shift_energy;
>> + int scl_shift_time;
>> struct hwmon_energy_info ei; /* Energy info for
>> energy1_input */
>> };
>> @@ -255,6 +257,138 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, long
>> *energy)
>> xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> }
>> +static ssize_t
>> +xe_hwmon_power1_max_interval_show(struct device *dev, struct
>> device_attribute *attr,
>> + char *buf)
>> +{
>> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
>> + u32 r, x, y, x_w = 2; /* 2 bits */
>> + u64 tau4, out;
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
>> + REG_READ, &r, 0, 0);
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
>> + y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
>> + /*
>> + * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
>> + * = (4 | x) << (y - 2)
>> + * where (y - 2) ensures a 1.x fixed point representation of 1.x
>> + * However because y can be < 2, we compute
>> + * tau4 = (4 | x) << y
>> + * but add 2 when doing the final right shift to account for units
>> + */
>> + tau4 = ((1 << x_w) | x) << y;
>> + /* val in hwmon interface units (millisec) */
>> + out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
>> +
>> + return sysfs_emit(buf, "%llu\n", out);
>> +}
>> +
>> +static ssize_t
>> +xe_hwmon_power1_max_interval_store(struct device *dev, struct
>> device_attribute *attr,
>> + const char *buf, size_t count)
>> +{
>> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
>> + u32 x, y, rxy, x_w = 2; /* 2 bits */
>> + u64 tau4, r, max_win;
>> + unsigned long val;
>> + int ret;
>> +
>> + ret = kstrtoul(buf, 0, &val);
>> + if (ret)
>> + return ret;
>> +
>> + /*
>> + * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y =
>> 0x12
>> + * The hwmon->scl_shift_time default of 0xa results in a max tau
>> of 256 seconds
>> + */
>> +#define PKG_MAX_WIN_DEFAULT 0x12ull
>
> Do we need to determine r, x, y etc for max limit ?
>
> Why cant we simply define MAX_LIMIT 256 ?
PKG_MAX_WIN is field of PKG_PWR_SKU but it is observed that for some
platforms it is invalid and for some not populated. So fixed the max
limit. For future platforms if PKG_MAX_WIN is valid then it is prefered
to read from register, in that case below equation is needed to
calculate max limit.
Regards,
Badal
>
> BR
>
> Himal
>
>> +
>> + /*
>> + * val must be < max in hwmon interface units. The steps below are
>> + * explained in xe_hwmon_power1_max_interval_show()
>> + */
>> + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
>> + x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
>> + y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
>> + tau4 = ((1 << x_w) | x) << y;
>> + max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time +
>> x_w);
>> +
>> + if (val > max_win)
>> + return -EINVAL;
>> +
>> + /* val in hw units */
>> + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time,
>> SF_TIME);
>> + /* Convert to 1.x * power(2,y) */
>> + if (!val) {
>> + /* Avoid ilog2(0) */
>> + y = 0;
>> + x = 0;
>> + } else {
>> + y = ilog2(val);
>> + /* x = (val - (1 << y)) >> (y - 2); */
>> + x = (val - (1ul << y)) << x_w >> y;
>> + }
>> +
>> + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) |
>> REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + mutex_lock(&hwmon->hwmon_lock);
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, (u32 *)&r,
>> + PKG_PWR_LIM_1_TIME, rxy);
>> +
>> + mutex_unlock(&hwmon->hwmon_lock);
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + return count;
>> +}
>> +
>> +static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
>> + xe_hwmon_power1_max_interval_show,
>> + xe_hwmon_power1_max_interval_store, 0);
>> +
>> +static struct attribute *hwmon_attributes[] = {
>> + &sensor_dev_attr_power1_max_interval.dev_attr.attr,
>> + NULL
>> +};
>> +
>> +static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,
>> + struct attribute *attr, int index)
>> +{
>> + struct device *dev = kobj_to_dev(kobj);
>> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
>> + u32 reg_val;
>> + int ret = 0;
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
>> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
>> + REG_READ, ®_val, 0, 0) ? 0 : attr->mode;
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + return ret;
>> +}
>> +
>> +static const struct attribute_group hwmon_attrgroup = {
>> + .attrs = hwmon_attributes,
>> + .is_visible = xe_hwmon_attributes_visible,
>> +};
>> +
>> +static const struct attribute_group *hwmon_groups[] = {
>> + &hwmon_attrgroup,
>> + NULL
>> +};
>> +
>> static const struct hwmon_channel_info *hwmon_info[] = {
>> HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX |
>> HWMON_P_CRIT),
>> HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
>> @@ -573,6 +707,7 @@ xe_hwmon_get_preregistration_info(struct xe_device
>> *xe)
>> if (!ret) {
>> hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT,
>> val_sku_unit);
>> hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT,
>> val_sku_unit);
>> + hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT,
>> val_sku_unit);
>> }
>> /*
>> @@ -612,7 +747,8 @@ void xe_hwmon_register(struct xe_device *xe)
>> "xe",
>> hwmon,
>> &hwmon_chip_info,
>> - NULL);
>> + hwmon_groups);
>> +
>> if (IS_ERR(hwmon->hwmon_dev)) {
>> drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n",
>> hwmon->hwmon_dev);
>> xe->hwmon = NULL;
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 6/6] drm/xe/hwmon: Expose power1_max_interval
@ 2023-09-22 9:49 ` Nilawar, Badal
0 siblings, 0 replies; 53+ messages in thread
From: Nilawar, Badal @ 2023-09-22 9:49 UTC (permalink / raw)
To: Ghimiray, Himal Prasad, intel-xe, linux-hwmon; +Cc: linux, rodrigo.vivi
On 21-09-2023 17:13, Ghimiray, Himal Prasad wrote:
>
> On 21-09-2023 15:55, Badal Nilawar wrote:
>> Expose power1_max_interval, that is the tau corresponding to PL1, as a
>> custom hwmon attribute. Some bit manipulation is needed because of the
>> format of PKG_PWR_LIM_1_TIME in
>> PACKAGE_RAPL_LIMIT register (1.x * power(2,y))
>>
>> v2: Get rpm wake ref while accessing power1_max_interval
>> v3: %s/hwmon/xe_hwmon/
>>
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> ---
>> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 11 ++
>> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 8 +
>> drivers/gpu/drm/xe/xe_hwmon.c | 138 +++++++++++++++++-
>> 3 files changed, 156 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> index 1a7a6c23e141..9ceb9c04b52b 100644
>> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> @@ -59,3 +59,14 @@ Contact: intel-xe@lists.freedesktop.org
>> Description: RO. Energy input of device in microjoules.
>> Only supported for particular Intel xe graphics platforms.
>> +
>> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
>> +Date: September 2023
>> +KernelVersion: 6.5
>> +Contact: intel-xe@lists.freedesktop.org
>> +Description: RW. Sustained power limit interval (Tau in PL1/Tau) in
>> + milliseconds over which sustained power is averaged.
>> +
>> + Only supported for particular Intel xe graphics platforms.
>> +
>> +
>> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> index d8ecbe1858d1..519dd1067a19 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> @@ -22,15 +22,23 @@
>> #define PKG_TDP GENMASK_ULL(14, 0)
>> #define PKG_MIN_PWR GENMASK_ULL(30, 16)
>> #define PKG_MAX_PWR GENMASK_ULL(46, 32)
>> +#define PKG_MAX_WIN GENMASK_ULL(54, 48)
>> +#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
>> +#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
>> +
>> #define PCU_CR_PACKAGE_POWER_SKU_UNIT
>> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
>> #define PKG_PWR_UNIT REG_GENMASK(3, 0)
>> #define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
>> +#define PKG_TIME_UNIT REG_GENMASK(19, 16)
>> #define PCU_CR_PACKAGE_ENERGY_STATUS
>> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
>> #define PCU_CR_PACKAGE_RAPL_LIMIT
>> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
>> #define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
>> #define PKG_PWR_LIM_1_EN REG_BIT(15)
>> +#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
>> +#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
>> +#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
>> #endif /* _XE_MCHBAR_REGS_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c
>> b/drivers/gpu/drm/xe/xe_hwmon.c
>> index cb75b9a386c0..dfa638942d47 100644
>> --- a/drivers/gpu/drm/xe/xe_hwmon.c
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -38,6 +38,7 @@ enum xe_hwmon_reg_operation {
>> #define SF_CURR 1000 /* milliamperes */
>> #define SF_VOLTAGE 1000 /* millivolts */
>> #define SF_ENERGY 1000000 /* microjoules */
>> +#define SF_TIME 1000 /* milliseconds */
>> struct hwmon_energy_info {
>> u32 reg_val_prev;
>> @@ -50,6 +51,7 @@ struct xe_hwmon {
>> struct mutex hwmon_lock; /* rmw operations*/
>> int scl_shift_power;
>> int scl_shift_energy;
>> + int scl_shift_time;
>> struct hwmon_energy_info ei; /* Energy info for
>> energy1_input */
>> };
>> @@ -255,6 +257,138 @@ xe_hwmon_energy_get(struct xe_hwmon *hwmon, long
>> *energy)
>> xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> }
>> +static ssize_t
>> +xe_hwmon_power1_max_interval_show(struct device *dev, struct
>> device_attribute *attr,
>> + char *buf)
>> +{
>> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
>> + u32 r, x, y, x_w = 2; /* 2 bits */
>> + u64 tau4, out;
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
>> + REG_READ, &r, 0, 0);
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
>> + y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
>> + /*
>> + * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
>> + * = (4 | x) << (y - 2)
>> + * where (y - 2) ensures a 1.x fixed point representation of 1.x
>> + * However because y can be < 2, we compute
>> + * tau4 = (4 | x) << y
>> + * but add 2 when doing the final right shift to account for units
>> + */
>> + tau4 = ((1 << x_w) | x) << y;
>> + /* val in hwmon interface units (millisec) */
>> + out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w);
>> +
>> + return sysfs_emit(buf, "%llu\n", out);
>> +}
>> +
>> +static ssize_t
>> +xe_hwmon_power1_max_interval_store(struct device *dev, struct
>> device_attribute *attr,
>> + const char *buf, size_t count)
>> +{
>> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
>> + u32 x, y, rxy, x_w = 2; /* 2 bits */
>> + u64 tau4, r, max_win;
>> + unsigned long val;
>> + int ret;
>> +
>> + ret = kstrtoul(buf, 0, &val);
>> + if (ret)
>> + return ret;
>> +
>> + /*
>> + * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y =
>> 0x12
>> + * The hwmon->scl_shift_time default of 0xa results in a max tau
>> of 256 seconds
>> + */
>> +#define PKG_MAX_WIN_DEFAULT 0x12ull
>
> Do we need to determine r, x, y etc for max limit ?
>
> Why cant we simply define MAX_LIMIT 256 ?
PKG_MAX_WIN is field of PKG_PWR_SKU but it is observed that for some
platforms it is invalid and for some not populated. So fixed the max
limit. For future platforms if PKG_MAX_WIN is valid then it is prefered
to read from register, in that case below equation is needed to
calculate max limit.
Regards,
Badal
>
> BR
>
> Himal
>
>> +
>> + /*
>> + * val must be < max in hwmon interface units. The steps below are
>> + * explained in xe_hwmon_power1_max_interval_show()
>> + */
>> + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
>> + x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
>> + y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
>> + tau4 = ((1 << x_w) | x) << y;
>> + max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time +
>> x_w);
>> +
>> + if (val > max_win)
>> + return -EINVAL;
>> +
>> + /* val in hw units */
>> + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time,
>> SF_TIME);
>> + /* Convert to 1.x * power(2,y) */
>> + if (!val) {
>> + /* Avoid ilog2(0) */
>> + y = 0;
>> + x = 0;
>> + } else {
>> + y = ilog2(val);
>> + /* x = (val - (1 << y)) >> (y - 2); */
>> + x = (val - (1ul << y)) << x_w >> y;
>> + }
>> +
>> + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) |
>> REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + mutex_lock(&hwmon->hwmon_lock);
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, (u32 *)&r,
>> + PKG_PWR_LIM_1_TIME, rxy);
>> +
>> + mutex_unlock(&hwmon->hwmon_lock);
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + return count;
>> +}
>> +
>> +static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
>> + xe_hwmon_power1_max_interval_show,
>> + xe_hwmon_power1_max_interval_store, 0);
>> +
>> +static struct attribute *hwmon_attributes[] = {
>> + &sensor_dev_attr_power1_max_interval.dev_attr.attr,
>> + NULL
>> +};
>> +
>> +static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,
>> + struct attribute *attr, int index)
>> +{
>> + struct device *dev = kobj_to_dev(kobj);
>> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
>> + u32 reg_val;
>> + int ret = 0;
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
>> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
>> + REG_READ, ®_val, 0, 0) ? 0 : attr->mode;
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + return ret;
>> +}
>> +
>> +static const struct attribute_group hwmon_attrgroup = {
>> + .attrs = hwmon_attributes,
>> + .is_visible = xe_hwmon_attributes_visible,
>> +};
>> +
>> +static const struct attribute_group *hwmon_groups[] = {
>> + &hwmon_attrgroup,
>> + NULL
>> +};
>> +
>> static const struct hwmon_channel_info *hwmon_info[] = {
>> HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX |
>> HWMON_P_CRIT),
>> HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT),
>> @@ -573,6 +707,7 @@ xe_hwmon_get_preregistration_info(struct xe_device
>> *xe)
>> if (!ret) {
>> hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT,
>> val_sku_unit);
>> hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT,
>> val_sku_unit);
>> + hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT,
>> val_sku_unit);
>> }
>> /*
>> @@ -612,7 +747,8 @@ void xe_hwmon_register(struct xe_device *xe)
>> "xe",
>> hwmon,
>> &hwmon_chip_info,
>> - NULL);
>> + hwmon_groups);
>> +
>> if (IS_ERR(hwmon->hwmon_dev)) {
>> drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n",
>> hwmon->hwmon_dev);
>> xe->hwmon = NULL;
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
2023-09-21 16:25 ` Rodrigo Vivi
@ 2023-09-22 9:57 ` Nilawar, Badal
-1 siblings, 0 replies; 53+ messages in thread
From: Nilawar, Badal @ 2023-09-22 9:57 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-xe, linux-hwmon, linux
On 21-09-2023 21:55, Rodrigo Vivi wrote:
> On Thu, Sep 21, 2023 at 03:55:15PM +0530, Badal Nilawar wrote:
>> Expose Card reactive sustained (pl1) power limit as power_max and
>> card default power limit (tdp) as power_rated_max.
>>
>> v2:
>> - Fix review comments (Riana)
>> v3:
>> - Use drmm_mutex_init (Matt Brost)
>> - Print error value (Matt Brost)
>> - Convert enums to uppercase (Matt Brost)
>> - Avoid extra reg read in hwmon_is_visible function (Riana)
>> - Use xe_device_assert_mem_access when applicable (Matt Brost)
>> - Add intel-xe@lists.freedesktop.org in Documentation (Matt Brost)
>> v4:
>> - Use prefix xe_hwmon prefix for all functions (Matt Brost/Andi)
>> - %s/hwmon_reg/xe_hwmon_reg (Andi)
>> - Fix review comments (Guenter/Andi)
>> v5:
>> - Fix review comments (Riana)
>>
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> ---
>> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 22 ++
>> drivers/gpu/drm/xe/Makefile | 3 +
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +
>> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 33 ++
>> drivers/gpu/drm/xe/xe_device.c | 3 +
>> drivers/gpu/drm/xe/xe_device_types.h | 2 +
>> drivers/gpu/drm/xe/xe_hwmon.c | 358 ++++++++++++++++++
>> drivers/gpu/drm/xe/xe_hwmon.h | 20 +
>> 8 files changed, 445 insertions(+)
>> create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> create mode 100644 drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.c
>> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.h
>>
>> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> new file mode 100644
>> index 000000000000..da0197a29fe4
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> @@ -0,0 +1,22 @@
>> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max
>> +Date: September 2023
>> +KernelVersion: 6.5
>> +Contact: intel-xe@lists.freedesktop.org
>> +Description: RW. Card reactive sustained (PL1) power limit in microwatts.
>> +
>> + The power controller will throttle the operating frequency
>> + if the power averaged over a window (typically seconds)
>> + exceeds this limit. A read value of 0 means that the PL1
>> + power limit is disabled, writing 0 disables the
>> + limit. Writing values > 0 and <= TDP will enable the power limit.
>> +
>> + Only supported for particular Intel xe graphics platforms.
>> +
>> +What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max
>> +Date: September 2023
>> +KernelVersion: 6.5
>> +Contact: intel-xe@lists.freedesktop.org
>> +Description: RO. Card default power limit (default TDP setting).
>> +
>> + Only supported for particular Intel xe graphics platforms.
>> +
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 86c8bd4c05a3..ca77aff60d48 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -117,6 +117,9 @@ xe-y += xe_bb.o \
>> xe_wa.o \
>> xe_wopcm.o
>>
>> +# graphics hardware monitoring (HWMON) support
>> +xe-$(CONFIG_HWMON) += xe_hwmon.o
>> +
>> # i915 Display compat #defines and #includes
>> subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
>> -I$(srctree)/$(src)/display/ext \
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index e13fbbdf6929..679cdba9f383 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -410,4 +410,8 @@
>> #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
>> #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
>>
>> +#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
>> +#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
>> +#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
>> +
>> #endif
>> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> new file mode 100644
>> index 000000000000..27f1d42baf6d
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> @@ -0,0 +1,33 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_MCHBAR_REGS_H_
>> +#define _XE_MCHBAR_REGS_H_
>> +
>> +#include "regs/xe_reg_defs.h"
>> +
>> +/*
>> + * MCHBAR mirror.
>> + *
>> + * This mirrors the MCHBAR MMIO space whose location is determined by
>> + * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
>> + * every way.
>> + */
>> +
>> +#define MCHBAR_MIRROR_BASE_SNB 0x140000
>> +
>> +#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
>> +#define PKG_TDP GENMASK_ULL(14, 0)
>> +#define PKG_MIN_PWR GENMASK_ULL(30, 16)
>> +#define PKG_MAX_PWR GENMASK_ULL(46, 32)
>> +
>> +#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
>> +#define PKG_PWR_UNIT REG_GENMASK(3, 0)
>> +
>> +#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
>> +#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
>> +#define PKG_PWR_LIM_1_EN REG_BIT(15)
>> +
>> +#endif /* _XE_MCHBAR_REGS_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>> index b6bcb6c3482e..2acdc22a6027 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -34,6 +34,7 @@
>> #include "xe_vm.h"
>> #include "xe_vm_madvise.h"
>> #include "xe_wait_user_fence.h"
>> +#include "xe_hwmon.h"
>>
>> #ifdef CONFIG_LOCKDEP
>> struct lockdep_map xe_device_mem_access_lockdep_map = {
>> @@ -337,6 +338,8 @@ int xe_device_probe(struct xe_device *xe)
>>
>> xe_pmu_register(&xe->pmu);
>>
>> + xe_hwmon_register(xe);
>> +
>> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
>> if (err)
>> return err;
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index a82f28c6a3a0..d1e319f305ef 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -365,6 +365,8 @@ struct xe_device {
>> /** @pmu: performance monitoring unit */
>> struct xe_pmu pmu;
>>
>> + struct xe_hwmon *hwmon;
>> +
>> /* private: */
>>
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> new file mode 100644
>> index 000000000000..7f4599d98541
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -0,0 +1,358 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#include <linux/hwmon.h>
>> +
>> +#include <drm/drm_managed.h>
>> +#include "regs/xe_gt_regs.h"
>> +#include "regs/xe_mchbar_regs.h"
>> +#include "xe_device.h"
>> +#include "xe_gt.h"
>> +#include "xe_hwmon.h"
>> +#include "xe_mmio.h"
>> +
>> +enum xe_hwmon_reg {
>> + REG_PKG_RAPL_LIMIT,
>> + REG_PKG_POWER_SKU,
>> + REG_PKG_POWER_SKU_UNIT,
>> +};
>> +
>> +enum xe_hwmon_reg_operation {
>> + REG_READ,
>> + REG_WRITE,
>> + REG_RMW,
>> +};
>> +
>> +/*
>> + * SF_* - scale factors for particular quantities according to hwmon spec.
>> + */
>> +#define SF_POWER 1000000 /* microwatts */
>> +
>> +struct xe_hwmon {
>> + struct device *hwmon_dev;
>> + struct xe_gt *gt;
>> + struct mutex hwmon_lock; /* rmw operations*/
>> + int scl_shift_power;
>> +};
>> +
>> +static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
>> +{
>> + struct xe_device *xe = gt_to_xe(hwmon->gt);
>> + struct xe_reg reg = XE_REG(0);
>> +
>> + switch (hwmon_reg) {
>> + case REG_PKG_RAPL_LIMIT:
>> + if (xe->info.platform == XE_DG2)
>> + reg = PCU_CR_PACKAGE_RAPL_LIMIT;
>> + else if (xe->info.platform == XE_PVC)
>> + reg = PVC_GT0_PACKAGE_RAPL_LIMIT;
>> + break;
>> + case REG_PKG_POWER_SKU:
>> + if (xe->info.platform == XE_DG2)
>> + reg = PCU_CR_PACKAGE_POWER_SKU;
>> + else if (xe->info.platform == XE_PVC)
>> + reg = PVC_GT0_PACKAGE_POWER_SKU;
>> + break;
>> + case REG_PKG_POWER_SKU_UNIT:
>> + if (xe->info.platform == XE_DG2)
>> + reg = PCU_CR_PACKAGE_POWER_SKU_UNIT;
>> + else if (xe->info.platform == XE_PVC)
>> + reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;
>> + break;
>> + default:
>> + XE_MISSING_CASE(hwmon_reg);
>> + break;
>> + }
>> +
>> + return reg.raw;
>> +}
>> +
>> +static int xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
>> + enum xe_hwmon_reg_operation operation, u32 *value,
>> + u32 clr, u32 set)
>> +{
>> + struct xe_reg reg;
>> +
>> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
>> +
>> + if (!reg.raw)
>> + return -EOPNOTSUPP;
>> +
>> + switch (operation) {
>> + case REG_READ:
>> + *value = xe_mmio_read32(hwmon->gt, reg);
>> + return 0;
>> + case REG_WRITE:
>> + xe_mmio_write32(hwmon->gt, reg, *value);
>> + return 0;
>> + case REG_RMW:
>> + *value = xe_mmio_rmw32(hwmon->gt, reg, clr, set);
>> + return 0;
>> + default:
>> + XE_MISSING_CASE(operation);
>> + return -EOPNOTSUPP;
>> + }
>> +}
>> +
>> +int xe_hwmon_process_reg_read64(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, u64 *value)
>> +{
>> + struct xe_reg reg;
>> +
>> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
>> +
>> + if (!reg.raw)
>> + return -EOPNOTSUPP;
>> +
>> + *value = xe_mmio_read64_2x32(hwmon->gt, reg);
>> +
>> + return 0;
>> +}
>> +
>> +#define PL1_DISABLE 0
>> +
>> +/*
>> + * HW allows arbitrary PL1 limits to be set but silently clamps these values to
>> + * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the
>> + * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
>> + * clamped values when read.
>> + */
>> +static int xe_hwmon_power_max_read(struct xe_hwmon *hwmon, long *value)
>> +{
>> + u32 reg_val;
>> + u64 reg_val64, min, max;
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val, 0, 0);
>> + /* Check if PL1 limit is disabled */
>> + if (!(reg_val & PKG_PWR_LIM_1_EN)) {
>> + *value = PL1_DISABLE;
>> + return 0;
>> + }
>> +
>> + reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);
>> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
>> +
>> + xe_hwmon_process_reg_read64(hwmon, REG_PKG_POWER_SKU, ®_val64);
>> + min = REG_FIELD_GET(PKG_MIN_PWR, reg_val64);
>> + min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
>> + max = REG_FIELD_GET(PKG_MAX_PWR, reg_val64);
>> + max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
>> +
>> + if (min && max)
>> + *value = clamp_t(u64, *value, min, max);
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
>> +{
>> + u32 reg_val;
>> +
>> + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
>> + if (value == PL1_DISABLE) {
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
>> + PKG_PWR_LIM_1_EN, 0);
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
>> + PKG_PWR_LIM_1_EN, 0);
>> +
>> + if (reg_val & PKG_PWR_LIM_1_EN)
>> + return -ENODEV;
>> + }
>> +
>> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
>> + reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
>> + reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
>> + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
>> +{
>> + u32 reg_val;
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ, ®_val, 0, 0);
>> + reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
>> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct hwmon_channel_info *hwmon_info[] = {
>> + HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
>> + NULL
>> +};
>> +
>> +static umode_t
>> +xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
>> +{
>> + switch (attr) {
>> + case hwmon_power_max:
>> + return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
>> + case hwmon_power_rated_max:
>> + return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
>> + default:
>> + return 0;
>> + }
>> +}
>> +
>> +static int
>> +xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
>> +{
>> + switch (attr) {
>> + case hwmon_power_max:
>> + return xe_hwmon_power_max_read(hwmon, val);
>> + case hwmon_power_rated_max:
>> + return xe_hwmon_power_rated_max_read(hwmon, val);
>> + default:
>> + return -EOPNOTSUPP;
>> + }
>> +}
>> +
>> +static int
>> +xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
>> +{
>> + switch (attr) {
>> + case hwmon_power_max:
>> + return xe_hwmon_power_max_write(hwmon, val);
>> + default:
>> + return -EOPNOTSUPP;
>> + }
>> +}
>> +
>> +static umode_t
>> +xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
>> + u32 attr, int channel)
>> +{
>> + struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata;
>> + int ret;
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + switch (type) {
>> + case hwmon_power:
>> + ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
>> + break;
>> + default:
>> + ret = 0;
>> + break;
>> + }
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + return ret;
>> +}
>> +
>> +static int
>> +xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
>> + int channel, long *val)
>> +{
>> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
>> + int ret;
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + switch (type) {
>> + case hwmon_power:
>> + ret = xe_hwmon_power_read(hwmon, attr, channel, val);
>> + break;
>> + default:
>> + ret = -EOPNOTSUPP;
>> + break;
>> + }
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + return ret;
>> +}
>> +
>> +static int
>> +xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
>> + int channel, long val)
>> +{
>> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
>> + int ret;
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + switch (type) {
>> + case hwmon_power:
>> + ret = xe_hwmon_power_write(hwmon, attr, channel, val);
>> + break;
>> + default:
>> + ret = -EOPNOTSUPP;
>> + break;
>> + }
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + return ret;
>> +}
>> +
>> +static const struct hwmon_ops hwmon_ops = {
>> + .is_visible = xe_hwmon_is_visible,
>> + .read = xe_hwmon_read,
>> + .write = xe_hwmon_write,
>> +};
>> +
>> +static const struct hwmon_chip_info hwmon_chip_info = {
>> + .ops = &hwmon_ops,
>> + .info = hwmon_info,
>> +};
>> +
>> +static void
>> +xe_hwmon_get_preregistration_info(struct xe_device *xe)
>> +{
>> + struct xe_hwmon *hwmon = xe->hwmon;
>> + u32 val_sku_unit = 0;
>> + int ret;
>> +
>> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU_UNIT, REG_READ, &val_sku_unit, 0, 0);
>> + /*
>> + * The contents of register PKG_POWER_SKU_UNIT do not change,
>> + * so read it once and store the shift values.
>> + */
>> + if (!ret)
>> + hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
>> +}
>> +
>> +void xe_hwmon_register(struct xe_device *xe)
>> +{
>> + struct device *dev = xe->drm.dev;
>> + struct xe_hwmon *hwmon;
>> +
>> + /* hwmon is available only for dGfx */
>> + if (!IS_DGFX(xe))
>> + return;
>> +
>> + hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
>> + if (!hwmon)
>> + return;
>> +
>> + xe->hwmon = hwmon;
>> +
>> + drmm_mutex_init(&xe->drm, &hwmon->hwmon_lock);
>> +
>> + /* primary GT to access device level properties */
>> + hwmon->gt = xe->tiles[0].primary_gt;
>
> So, what happens with the other tiles?
> We should get them in since the beginning since that will impose
> interface changes and bigger changes on IGT tests.
For now gt specific attributes (Gt energy) are not handled in this
series. When those are added those will be new entries with label and
shouldn't affect existing entries. As discussed offline when lables are
implemented for energy will consider adding it for other entries as
well. As suggested I will drop first patch and resend the series by
adding your acked-by.
Thanks,
Badal
>
>> +
>> + xe_hwmon_get_preregistration_info(xe);
>> +
>> + drm_dbg(&xe->drm, "Register xe hwmon interface\n");
>> +
>> + /* hwmon_dev points to device hwmon<i> */
>> + hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
>> + "xe",
>> + hwmon,
>> + &hwmon_chip_info,
>> + NULL);
>> + if (IS_ERR(hwmon->hwmon_dev)) {
>> + drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
>> + xe->hwmon = NULL;
>> + return;
>> + }
>> +}
>> +
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.h b/drivers/gpu/drm/xe/xe_hwmon.h
>> new file mode 100644
>> index 000000000000..1ec45cf1d19b
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.h
>> @@ -0,0 +1,20 @@
>> +/* SPDX-License-Identifier: MIT */
>> +
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_HWMON_H_
>> +#define _XE_HWMON_H_
>> +
>> +#include <linux/types.h>
>> +
>> +struct xe_device;
>> +
>> +#if IS_REACHABLE(CONFIG_HWMON)
>> +void xe_hwmon_register(struct xe_device *xe);
>> +#else
>> +static inline void xe_hwmon_register(struct xe_device *xe) { };
>> +#endif
>> +
>> +#endif /* _XE_HWMON_H_ */
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
@ 2023-09-22 9:57 ` Nilawar, Badal
0 siblings, 0 replies; 53+ messages in thread
From: Nilawar, Badal @ 2023-09-22 9:57 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: linux-hwmon, intel-xe, linux
On 21-09-2023 21:55, Rodrigo Vivi wrote:
> On Thu, Sep 21, 2023 at 03:55:15PM +0530, Badal Nilawar wrote:
>> Expose Card reactive sustained (pl1) power limit as power_max and
>> card default power limit (tdp) as power_rated_max.
>>
>> v2:
>> - Fix review comments (Riana)
>> v3:
>> - Use drmm_mutex_init (Matt Brost)
>> - Print error value (Matt Brost)
>> - Convert enums to uppercase (Matt Brost)
>> - Avoid extra reg read in hwmon_is_visible function (Riana)
>> - Use xe_device_assert_mem_access when applicable (Matt Brost)
>> - Add intel-xe@lists.freedesktop.org in Documentation (Matt Brost)
>> v4:
>> - Use prefix xe_hwmon prefix for all functions (Matt Brost/Andi)
>> - %s/hwmon_reg/xe_hwmon_reg (Andi)
>> - Fix review comments (Guenter/Andi)
>> v5:
>> - Fix review comments (Riana)
>>
>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> ---
>> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 22 ++
>> drivers/gpu/drm/xe/Makefile | 3 +
>> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 +
>> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 33 ++
>> drivers/gpu/drm/xe/xe_device.c | 3 +
>> drivers/gpu/drm/xe/xe_device_types.h | 2 +
>> drivers/gpu/drm/xe/xe_hwmon.c | 358 ++++++++++++++++++
>> drivers/gpu/drm/xe/xe_hwmon.h | 20 +
>> 8 files changed, 445 insertions(+)
>> create mode 100644 Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> create mode 100644 drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.c
>> create mode 100644 drivers/gpu/drm/xe/xe_hwmon.h
>>
>> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> new file mode 100644
>> index 000000000000..da0197a29fe4
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
>> @@ -0,0 +1,22 @@
>> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max
>> +Date: September 2023
>> +KernelVersion: 6.5
>> +Contact: intel-xe@lists.freedesktop.org
>> +Description: RW. Card reactive sustained (PL1) power limit in microwatts.
>> +
>> + The power controller will throttle the operating frequency
>> + if the power averaged over a window (typically seconds)
>> + exceeds this limit. A read value of 0 means that the PL1
>> + power limit is disabled, writing 0 disables the
>> + limit. Writing values > 0 and <= TDP will enable the power limit.
>> +
>> + Only supported for particular Intel xe graphics platforms.
>> +
>> +What: /sys/devices/.../hwmon/hwmon<i>/power1_rated_max
>> +Date: September 2023
>> +KernelVersion: 6.5
>> +Contact: intel-xe@lists.freedesktop.org
>> +Description: RO. Card default power limit (default TDP setting).
>> +
>> + Only supported for particular Intel xe graphics platforms.
>> +
>> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
>> index 86c8bd4c05a3..ca77aff60d48 100644
>> --- a/drivers/gpu/drm/xe/Makefile
>> +++ b/drivers/gpu/drm/xe/Makefile
>> @@ -117,6 +117,9 @@ xe-y += xe_bb.o \
>> xe_wa.o \
>> xe_wopcm.o
>>
>> +# graphics hardware monitoring (HWMON) support
>> +xe-$(CONFIG_HWMON) += xe_hwmon.o
>> +
>> # i915 Display compat #defines and #includes
>> subdir-ccflags-$(CONFIG_DRM_XE_DISPLAY) += \
>> -I$(srctree)/$(src)/display/ext \
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index e13fbbdf6929..679cdba9f383 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -410,4 +410,8 @@
>> #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118)
>> #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c)
>>
>> +#define PVC_GT0_PACKAGE_RAPL_LIMIT XE_REG(0x281008)
>> +#define PVC_GT0_PACKAGE_POWER_SKU_UNIT XE_REG(0x281068)
>> +#define PVC_GT0_PACKAGE_POWER_SKU XE_REG(0x281080)
>> +
>> #endif
>> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> new file mode 100644
>> index 000000000000..27f1d42baf6d
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
>> @@ -0,0 +1,33 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_MCHBAR_REGS_H_
>> +#define _XE_MCHBAR_REGS_H_
>> +
>> +#include "regs/xe_reg_defs.h"
>> +
>> +/*
>> + * MCHBAR mirror.
>> + *
>> + * This mirrors the MCHBAR MMIO space whose location is determined by
>> + * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
>> + * every way.
>> + */
>> +
>> +#define MCHBAR_MIRROR_BASE_SNB 0x140000
>> +
>> +#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
>> +#define PKG_TDP GENMASK_ULL(14, 0)
>> +#define PKG_MIN_PWR GENMASK_ULL(30, 16)
>> +#define PKG_MAX_PWR GENMASK_ULL(46, 32)
>> +
>> +#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
>> +#define PKG_PWR_UNIT REG_GENMASK(3, 0)
>> +
>> +#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
>> +#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
>> +#define PKG_PWR_LIM_1_EN REG_BIT(15)
>> +
>> +#endif /* _XE_MCHBAR_REGS_H_ */
>> diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
>> index b6bcb6c3482e..2acdc22a6027 100644
>> --- a/drivers/gpu/drm/xe/xe_device.c
>> +++ b/drivers/gpu/drm/xe/xe_device.c
>> @@ -34,6 +34,7 @@
>> #include "xe_vm.h"
>> #include "xe_vm_madvise.h"
>> #include "xe_wait_user_fence.h"
>> +#include "xe_hwmon.h"
>>
>> #ifdef CONFIG_LOCKDEP
>> struct lockdep_map xe_device_mem_access_lockdep_map = {
>> @@ -337,6 +338,8 @@ int xe_device_probe(struct xe_device *xe)
>>
>> xe_pmu_register(&xe->pmu);
>>
>> + xe_hwmon_register(xe);
>> +
>> err = drmm_add_action_or_reset(&xe->drm, xe_device_sanitize, xe);
>> if (err)
>> return err;
>> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>> index a82f28c6a3a0..d1e319f305ef 100644
>> --- a/drivers/gpu/drm/xe/xe_device_types.h
>> +++ b/drivers/gpu/drm/xe/xe_device_types.h
>> @@ -365,6 +365,8 @@ struct xe_device {
>> /** @pmu: performance monitoring unit */
>> struct xe_pmu pmu;
>>
>> + struct xe_hwmon *hwmon;
>> +
>> /* private: */
>>
>> #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
>> new file mode 100644
>> index 000000000000..7f4599d98541
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
>> @@ -0,0 +1,358 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#include <linux/hwmon.h>
>> +
>> +#include <drm/drm_managed.h>
>> +#include "regs/xe_gt_regs.h"
>> +#include "regs/xe_mchbar_regs.h"
>> +#include "xe_device.h"
>> +#include "xe_gt.h"
>> +#include "xe_hwmon.h"
>> +#include "xe_mmio.h"
>> +
>> +enum xe_hwmon_reg {
>> + REG_PKG_RAPL_LIMIT,
>> + REG_PKG_POWER_SKU,
>> + REG_PKG_POWER_SKU_UNIT,
>> +};
>> +
>> +enum xe_hwmon_reg_operation {
>> + REG_READ,
>> + REG_WRITE,
>> + REG_RMW,
>> +};
>> +
>> +/*
>> + * SF_* - scale factors for particular quantities according to hwmon spec.
>> + */
>> +#define SF_POWER 1000000 /* microwatts */
>> +
>> +struct xe_hwmon {
>> + struct device *hwmon_dev;
>> + struct xe_gt *gt;
>> + struct mutex hwmon_lock; /* rmw operations*/
>> + int scl_shift_power;
>> +};
>> +
>> +static u32 xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg)
>> +{
>> + struct xe_device *xe = gt_to_xe(hwmon->gt);
>> + struct xe_reg reg = XE_REG(0);
>> +
>> + switch (hwmon_reg) {
>> + case REG_PKG_RAPL_LIMIT:
>> + if (xe->info.platform == XE_DG2)
>> + reg = PCU_CR_PACKAGE_RAPL_LIMIT;
>> + else if (xe->info.platform == XE_PVC)
>> + reg = PVC_GT0_PACKAGE_RAPL_LIMIT;
>> + break;
>> + case REG_PKG_POWER_SKU:
>> + if (xe->info.platform == XE_DG2)
>> + reg = PCU_CR_PACKAGE_POWER_SKU;
>> + else if (xe->info.platform == XE_PVC)
>> + reg = PVC_GT0_PACKAGE_POWER_SKU;
>> + break;
>> + case REG_PKG_POWER_SKU_UNIT:
>> + if (xe->info.platform == XE_DG2)
>> + reg = PCU_CR_PACKAGE_POWER_SKU_UNIT;
>> + else if (xe->info.platform == XE_PVC)
>> + reg = PVC_GT0_PACKAGE_POWER_SKU_UNIT;
>> + break;
>> + default:
>> + XE_MISSING_CASE(hwmon_reg);
>> + break;
>> + }
>> +
>> + return reg.raw;
>> +}
>> +
>> +static int xe_hwmon_process_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg,
>> + enum xe_hwmon_reg_operation operation, u32 *value,
>> + u32 clr, u32 set)
>> +{
>> + struct xe_reg reg;
>> +
>> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
>> +
>> + if (!reg.raw)
>> + return -EOPNOTSUPP;
>> +
>> + switch (operation) {
>> + case REG_READ:
>> + *value = xe_mmio_read32(hwmon->gt, reg);
>> + return 0;
>> + case REG_WRITE:
>> + xe_mmio_write32(hwmon->gt, reg, *value);
>> + return 0;
>> + case REG_RMW:
>> + *value = xe_mmio_rmw32(hwmon->gt, reg, clr, set);
>> + return 0;
>> + default:
>> + XE_MISSING_CASE(operation);
>> + return -EOPNOTSUPP;
>> + }
>> +}
>> +
>> +int xe_hwmon_process_reg_read64(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, u64 *value)
>> +{
>> + struct xe_reg reg;
>> +
>> + reg.raw = xe_hwmon_get_reg(hwmon, hwmon_reg);
>> +
>> + if (!reg.raw)
>> + return -EOPNOTSUPP;
>> +
>> + *value = xe_mmio_read64_2x32(hwmon->gt, reg);
>> +
>> + return 0;
>> +}
>> +
>> +#define PL1_DISABLE 0
>> +
>> +/*
>> + * HW allows arbitrary PL1 limits to be set but silently clamps these values to
>> + * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the
>> + * same pattern for sysfs, allow arbitrary PL1 limits to be set but display
>> + * clamped values when read.
>> + */
>> +static int xe_hwmon_power_max_read(struct xe_hwmon *hwmon, long *value)
>> +{
>> + u32 reg_val;
>> + u64 reg_val64, min, max;
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val, 0, 0);
>> + /* Check if PL1 limit is disabled */
>> + if (!(reg_val & PKG_PWR_LIM_1_EN)) {
>> + *value = PL1_DISABLE;
>> + return 0;
>> + }
>> +
>> + reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val);
>> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
>> +
>> + xe_hwmon_process_reg_read64(hwmon, REG_PKG_POWER_SKU, ®_val64);
>> + min = REG_FIELD_GET(PKG_MIN_PWR, reg_val64);
>> + min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power);
>> + max = REG_FIELD_GET(PKG_MAX_PWR, reg_val64);
>> + max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power);
>> +
>> + if (min && max)
>> + *value = clamp_t(u64, *value, min, max);
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
>> +{
>> + u32 reg_val;
>> +
>> + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
>> + if (value == PL1_DISABLE) {
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
>> + PKG_PWR_LIM_1_EN, 0);
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
>> + PKG_PWR_LIM_1_EN, 0);
>> +
>> + if (reg_val & PKG_PWR_LIM_1_EN)
>> + return -ENODEV;
>> + }
>> +
>> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
>> + reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
>> + reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
>> + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
>> +
>> + return 0;
>> +}
>> +
>> +static int xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, long *value)
>> +{
>> + u32 reg_val;
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU, REG_READ, ®_val, 0, 0);
>> + reg_val = REG_FIELD_GET(PKG_TDP, reg_val);
>> + *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct hwmon_channel_info *hwmon_info[] = {
>> + HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX),
>> + NULL
>> +};
>> +
>> +static umode_t
>> +xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int chan)
>> +{
>> + switch (attr) {
>> + case hwmon_power_max:
>> + return xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT) ? 0664 : 0;
>> + case hwmon_power_rated_max:
>> + return xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU) ? 0444 : 0;
>> + default:
>> + return 0;
>> + }
>> +}
>> +
>> +static int
>> +xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int chan, long *val)
>> +{
>> + switch (attr) {
>> + case hwmon_power_max:
>> + return xe_hwmon_power_max_read(hwmon, val);
>> + case hwmon_power_rated_max:
>> + return xe_hwmon_power_rated_max_read(hwmon, val);
>> + default:
>> + return -EOPNOTSUPP;
>> + }
>> +}
>> +
>> +static int
>> +xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int chan, long val)
>> +{
>> + switch (attr) {
>> + case hwmon_power_max:
>> + return xe_hwmon_power_max_write(hwmon, val);
>> + default:
>> + return -EOPNOTSUPP;
>> + }
>> +}
>> +
>> +static umode_t
>> +xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type,
>> + u32 attr, int channel)
>> +{
>> + struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata;
>> + int ret;
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + switch (type) {
>> + case hwmon_power:
>> + ret = xe_hwmon_power_is_visible(hwmon, attr, channel);
>> + break;
>> + default:
>> + ret = 0;
>> + break;
>> + }
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + return ret;
>> +}
>> +
>> +static int
>> +xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr,
>> + int channel, long *val)
>> +{
>> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
>> + int ret;
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + switch (type) {
>> + case hwmon_power:
>> + ret = xe_hwmon_power_read(hwmon, attr, channel, val);
>> + break;
>> + default:
>> + ret = -EOPNOTSUPP;
>> + break;
>> + }
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + return ret;
>> +}
>> +
>> +static int
>> +xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr,
>> + int channel, long val)
>> +{
>> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
>> + int ret;
>> +
>> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
>> +
>> + switch (type) {
>> + case hwmon_power:
>> + ret = xe_hwmon_power_write(hwmon, attr, channel, val);
>> + break;
>> + default:
>> + ret = -EOPNOTSUPP;
>> + break;
>> + }
>> +
>> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
>> +
>> + return ret;
>> +}
>> +
>> +static const struct hwmon_ops hwmon_ops = {
>> + .is_visible = xe_hwmon_is_visible,
>> + .read = xe_hwmon_read,
>> + .write = xe_hwmon_write,
>> +};
>> +
>> +static const struct hwmon_chip_info hwmon_chip_info = {
>> + .ops = &hwmon_ops,
>> + .info = hwmon_info,
>> +};
>> +
>> +static void
>> +xe_hwmon_get_preregistration_info(struct xe_device *xe)
>> +{
>> + struct xe_hwmon *hwmon = xe->hwmon;
>> + u32 val_sku_unit = 0;
>> + int ret;
>> +
>> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_POWER_SKU_UNIT, REG_READ, &val_sku_unit, 0, 0);
>> + /*
>> + * The contents of register PKG_POWER_SKU_UNIT do not change,
>> + * so read it once and store the shift values.
>> + */
>> + if (!ret)
>> + hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit);
>> +}
>> +
>> +void xe_hwmon_register(struct xe_device *xe)
>> +{
>> + struct device *dev = xe->drm.dev;
>> + struct xe_hwmon *hwmon;
>> +
>> + /* hwmon is available only for dGfx */
>> + if (!IS_DGFX(xe))
>> + return;
>> +
>> + hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
>> + if (!hwmon)
>> + return;
>> +
>> + xe->hwmon = hwmon;
>> +
>> + drmm_mutex_init(&xe->drm, &hwmon->hwmon_lock);
>> +
>> + /* primary GT to access device level properties */
>> + hwmon->gt = xe->tiles[0].primary_gt;
>
> So, what happens with the other tiles?
> We should get them in since the beginning since that will impose
> interface changes and bigger changes on IGT tests.
For now gt specific attributes (Gt energy) are not handled in this
series. When those are added those will be new entries with label and
shouldn't affect existing entries. As discussed offline when lables are
implemented for energy will consider adding it for other entries as
well. As suggested I will drop first patch and resend the series by
adding your acked-by.
Thanks,
Badal
>
>> +
>> + xe_hwmon_get_preregistration_info(xe);
>> +
>> + drm_dbg(&xe->drm, "Register xe hwmon interface\n");
>> +
>> + /* hwmon_dev points to device hwmon<i> */
>> + hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
>> + "xe",
>> + hwmon,
>> + &hwmon_chip_info,
>> + NULL);
>> + if (IS_ERR(hwmon->hwmon_dev)) {
>> + drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev);
>> + xe->hwmon = NULL;
>> + return;
>> + }
>> +}
>> +
>> diff --git a/drivers/gpu/drm/xe/xe_hwmon.h b/drivers/gpu/drm/xe/xe_hwmon.h
>> new file mode 100644
>> index 000000000000..1ec45cf1d19b
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_hwmon.h
>> @@ -0,0 +1,20 @@
>> +/* SPDX-License-Identifier: MIT */
>> +
>> +/*
>> + * Copyright © 2023 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_HWMON_H_
>> +#define _XE_HWMON_H_
>> +
>> +#include <linux/types.h>
>> +
>> +struct xe_device;
>> +
>> +#if IS_REACHABLE(CONFIG_HWMON)
>> +void xe_hwmon_register(struct xe_device *xe);
>> +#else
>> +static inline void xe_hwmon_register(struct xe_device *xe) { };
>> +#endif
>> +
>> +#endif /* _XE_HWMON_H_ */
>> --
>> 2.25.1
>>
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
2023-09-21 16:59 ` Nilawar, Badal
(?)
@ 2023-09-22 10:05 ` Jani Nikula
-1 siblings, 0 replies; 53+ messages in thread
From: Jani Nikula @ 2023-09-22 10:05 UTC (permalink / raw)
To: Nilawar, Badal, Rodrigo Vivi; +Cc: linux-hwmon, intel-xe, linux
On Thu, 21 Sep 2023, "Nilawar, Badal" <badal.nilawar@intel.com> wrote:
> On 21-09-2023 21:33, Rodrigo Vivi wrote:
>> On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
>>> Add XE_MISSING_CASE macro to handle missing switch case
>>>
>>> v2: Add comment about macro usage (Himal)
>>>
>>> Cc: Andi Shyti <andi.shyti@linux.intel.com>
>>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>>> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>>> ---
>>> drivers/gpu/drm/xe/xe_macros.h | 4 ++++
>>> 1 file changed, 4 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
>>> index daf56c846d03..6c74c69920ed 100644
>>> --- a/drivers/gpu/drm/xe/xe_macros.h
>>> +++ b/drivers/gpu/drm/xe/xe_macros.h
>>> @@ -15,4 +15,8 @@
>>> "Ioctl argument check failed at %s:%d: %s", \
>>> __FILE__, __LINE__, #cond), 1))
>>>
>>> +/* Parameter to macro should be a variable name */
>>> +#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
>>> + __stringify(x), (long)(x))
>>> +
>>
>> No, please! Let's not add unnecessary macros.
> This was suggested by Andy, in fact he suggested to reuse existing
> MISSING_CASE macro from i915. As I couldn't find common place to move it
> I went with creating new one.
>
> I will drop this patch and simply use drm_warn.
Please use drm_WARN() or drm_WARN_ON(). With panic_on_warn=1 in CI,
it'll oops the machine, and we'll actually catch these as opposed to
just leaving them as lines in dmesg.
I guess the main purpose of MISSING_CASE() in i915 was to unify the
behaviour, though I think that was also misused.
BR,
Jani.
>
> Regards,
> Badal
>>
>>> #endif
>>> --
>>> 2.25.1
>>>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
* RE: [Intel-xe] [PATCH v5 6/6] drm/xe/hwmon: Expose power1_max_interval
2023-09-22 9:49 ` Nilawar, Badal
@ 2023-09-22 12:43 ` Ghimiray, Himal Prasad
-1 siblings, 0 replies; 53+ messages in thread
From: Ghimiray, Himal Prasad @ 2023-09-22 12:43 UTC (permalink / raw)
To: Nilawar, Badal, intel-xe, linux-hwmon; +Cc: linux, Vivi, Rodrigo
> -----Original Message-----
> From: Nilawar, Badal <badal.nilawar@intel.com>
> Sent: 22 September 2023 15:19
> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; intel-
> xe@lists.freedesktop.org; linux-hwmon@vger.kernel.org
> Cc: linux@roeck-us.net; Vivi, Rodrigo <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-xe] [PATCH v5 6/6] drm/xe/hwmon: Expose
> power1_max_interval
>
>
>
> On 21-09-2023 17:13, Ghimiray, Himal Prasad wrote:
> >
> > On 21-09-2023 15:55, Badal Nilawar wrote:
> >> Expose power1_max_interval, that is the tau corresponding to PL1, as
> >> a custom hwmon attribute. Some bit manipulation is needed because of
> >> the format of PKG_PWR_LIM_1_TIME in PACKAGE_RAPL_LIMIT register
> (1.x
> >> * power(2,y))
> >>
> >> v2: Get rpm wake ref while accessing power1_max_interval
> >> v3: %s/hwmon/xe_hwmon/
> >>
> >> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> >> ---
> >> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 11 ++
> >> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 8 +
> >> drivers/gpu/drm/xe/xe_hwmon.c | 138
> >> +++++++++++++++++-
> >> 3 files changed, 156 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> >> b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> >> index 1a7a6c23e141..9ceb9c04b52b 100644
> >> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> >> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> >> @@ -59,3 +59,14 @@ Contact: intel-xe@lists.freedesktop.org
> >> Description: RO. Energy input of device in microjoules.
> >> Only supported for particular Intel xe graphics platforms.
> >> +
> >> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
> >> +Date: September 2023
> >> +KernelVersion: 6.5
> >> +Contact: intel-xe@lists.freedesktop.org
> >> +Description: RW. Sustained power limit interval (Tau in PL1/Tau)
> >> +in
> >> + milliseconds over which sustained power is averaged.
> >> +
> >> + Only supported for particular Intel xe graphics platforms.
> >> +
> >> +
> >> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> >> b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> >> index d8ecbe1858d1..519dd1067a19 100644
> >> --- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> >> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> >> @@ -22,15 +22,23 @@
> >> #define PKG_TDP GENMASK_ULL(14, 0)
> >> #define PKG_MIN_PWR GENMASK_ULL(30, 16)
> >> #define PKG_MAX_PWR GENMASK_ULL(46, 32)
> >> +#define PKG_MAX_WIN GENMASK_ULL(54, 48) #define
> >> +PKG_MAX_WIN_X GENMASK_ULL(54, 53) #define
> >> +PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
> >> +
> >> #define PCU_CR_PACKAGE_POWER_SKU_UNIT
> >> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> >> #define PKG_PWR_UNIT REG_GENMASK(3, 0)
> >> #define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
> >> +#define PKG_TIME_UNIT REG_GENMASK(19, 16)
> >> #define PCU_CR_PACKAGE_ENERGY_STATUS
> >> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
> >> #define PCU_CR_PACKAGE_RAPL_LIMIT
> >> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> >> #define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> >> #define PKG_PWR_LIM_1_EN REG_BIT(15)
> >> +#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17) #define
> >> +PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22) #define
> >> +PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
> >> #endif /* _XE_MCHBAR_REGS_H_ */
> >> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c
> >> b/drivers/gpu/drm/xe/xe_hwmon.c index cb75b9a386c0..dfa638942d47
> >> 100644
> >> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> >> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> >> @@ -38,6 +38,7 @@ enum xe_hwmon_reg_operation {
> >> #define SF_CURR 1000 /* milliamperes */
> >> #define SF_VOLTAGE 1000 /* millivolts */
> >> #define SF_ENERGY 1000000 /* microjoules */
> >> +#define SF_TIME 1000 /* milliseconds */
> >> struct hwmon_energy_info {
> >> u32 reg_val_prev;
> >> @@ -50,6 +51,7 @@ struct xe_hwmon {
> >> struct mutex hwmon_lock; /* rmw operations*/
> >> int scl_shift_power;
> >> int scl_shift_energy;
> >> + int scl_shift_time;
> >> struct hwmon_energy_info ei; /* Energy info for
> >> energy1_input */
> >> };
> >> @@ -255,6 +257,138 @@ xe_hwmon_energy_get(struct xe_hwmon
> *hwmon,
> >> long
> >> *energy)
> >> xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> >> }
> >> +static ssize_t
> >> +xe_hwmon_power1_max_interval_show(struct device *dev, struct
> >> device_attribute *attr,
> >> + char *buf)
> >> +{
> >> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> >> + u32 r, x, y, x_w = 2; /* 2 bits */
> >> + u64 tau4, out;
> >> +
> >> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> >> +
> >> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
> >> + REG_READ, &r, 0, 0);
> >> +
> >> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> >> +
> >> + x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
> >> + y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
> >> + /*
> >> + * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
> >> + * = (4 | x) << (y - 2)
> >> + * where (y - 2) ensures a 1.x fixed point representation of 1.x
> >> + * However because y can be < 2, we compute
> >> + * tau4 = (4 | x) << y
> >> + * but add 2 when doing the final right shift to account for
> >> +units
> >> + */
> >> + tau4 = ((1 << x_w) | x) << y;
> >> + /* val in hwmon interface units (millisec) */
> >> + out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time +
> >> +x_w);
> >> +
> >> + return sysfs_emit(buf, "%llu\n", out); }
> >> +
> >> +static ssize_t
> >> +xe_hwmon_power1_max_interval_store(struct device *dev, struct
> >> device_attribute *attr,
> >> + const char *buf, size_t count) {
> >> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> >> + u32 x, y, rxy, x_w = 2; /* 2 bits */
> >> + u64 tau4, r, max_win;
> >> + unsigned long val;
> >> + int ret;
> >> +
> >> + ret = kstrtoul(buf, 0, &val);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + /*
> >> + * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y =
> >> 0x12
> >> + * The hwmon->scl_shift_time default of 0xa results in a max tau
> >> of 256 seconds
> >> + */
> >> +#define PKG_MAX_WIN_DEFAULT 0x12ull
> >
> > Do we need to determine r, x, y etc for max limit ?
> >
> > Why cant we simply define MAX_LIMIT 256 ?
> PKG_MAX_WIN is field of PKG_PWR_SKU but it is observed that for some
> platforms it is invalid and for some not populated. So fixed the max limit. For
> future platforms if PKG_MAX_WIN is valid then it is prefered to read from
> register, in that case below equation is needed to calculate max limit.
That makes sense. LGTM
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>
> Regards,
> Badal
> >
> > BR
> >
> > Himal
> >
> >> +
> >> + /*
> >> + * val must be < max in hwmon interface units. The steps below
> >> +are
> >> + * explained in xe_hwmon_power1_max_interval_show()
> >> + */
> >> + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
> >> + x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
> >> + y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
> >> + tau4 = ((1 << x_w) | x) << y;
> >> + max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time +
> >> x_w);
> >> +
> >> + if (val > max_win)
> >> + return -EINVAL;
> >> +
> >> + /* val in hw units */
> >> + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time,
> >> SF_TIME);
> >> + /* Convert to 1.x * power(2,y) */
> >> + if (!val) {
> >> + /* Avoid ilog2(0) */
> >> + y = 0;
> >> + x = 0;
> >> + } else {
> >> + y = ilog2(val);
> >> + /* x = (val - (1 << y)) >> (y - 2); */
> >> + x = (val - (1ul << y)) << x_w >> y;
> >> + }
> >> +
> >> + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) |
> >> REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
> >> +
> >> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> >> +
> >> + mutex_lock(&hwmon->hwmon_lock);
> >> +
> >> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW,
> (u32
> >> +*)&r,
> >> + PKG_PWR_LIM_1_TIME, rxy);
> >> +
> >> + mutex_unlock(&hwmon->hwmon_lock);
> >> +
> >> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> >> +
> >> + return count;
> >> +}
> >> +
> >> +static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
> >> + xe_hwmon_power1_max_interval_show,
> >> + xe_hwmon_power1_max_interval_store, 0);
> >> +
> >> +static struct attribute *hwmon_attributes[] = {
> >> + &sensor_dev_attr_power1_max_interval.dev_attr.attr,
> >> + NULL
> >> +};
> >> +
> >> +static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,
> >> + struct attribute *attr, int index) {
> >> + struct device *dev = kobj_to_dev(kobj);
> >> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> >> + u32 reg_val;
> >> + int ret = 0;
> >> +
> >> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> >> +
> >> + if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
> >> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
> >> + REG_READ, ®_val, 0, 0) ? 0 : attr->mode;
> >> +
> >> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +static const struct attribute_group hwmon_attrgroup = {
> >> + .attrs = hwmon_attributes,
> >> + .is_visible = xe_hwmon_attributes_visible, };
> >> +
> >> +static const struct attribute_group *hwmon_groups[] = {
> >> + &hwmon_attrgroup,
> >> + NULL
> >> +};
> >> +
> >> static const struct hwmon_channel_info *hwmon_info[] = {
> >> HWMON_CHANNEL_INFO(power, HWMON_P_MAX |
> HWMON_P_RATED_MAX |
> >> HWMON_P_CRIT),
> >> HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT), @@ -573,6 +707,7
> @@
> >> xe_hwmon_get_preregistration_info(struct xe_device
> >> *xe)
> >> if (!ret) {
> >> hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT,
> >> val_sku_unit);
> >> hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT,
> >> val_sku_unit);
> >> + hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT,
> >> val_sku_unit);
> >> }
> >> /*
> >> @@ -612,7 +747,8 @@ void xe_hwmon_register(struct xe_device *xe)
> >> "xe",
> >> hwmon,
> >> &hwmon_chip_info,
> >> - NULL);
> >> + hwmon_groups);
> >> +
> >> if (IS_ERR(hwmon->hwmon_dev)) {
> >> drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n",
> >> hwmon->hwmon_dev);
> >> xe->hwmon = NULL;
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 6/6] drm/xe/hwmon: Expose power1_max_interval
@ 2023-09-22 12:43 ` Ghimiray, Himal Prasad
0 siblings, 0 replies; 53+ messages in thread
From: Ghimiray, Himal Prasad @ 2023-09-22 12:43 UTC (permalink / raw)
To: Nilawar, Badal, intel-xe, linux-hwmon; +Cc: linux, Vivi, Rodrigo
> -----Original Message-----
> From: Nilawar, Badal <badal.nilawar@intel.com>
> Sent: 22 September 2023 15:19
> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; intel-
> xe@lists.freedesktop.org; linux-hwmon@vger.kernel.org
> Cc: linux@roeck-us.net; Vivi, Rodrigo <rodrigo.vivi@intel.com>
> Subject: Re: [Intel-xe] [PATCH v5 6/6] drm/xe/hwmon: Expose
> power1_max_interval
>
>
>
> On 21-09-2023 17:13, Ghimiray, Himal Prasad wrote:
> >
> > On 21-09-2023 15:55, Badal Nilawar wrote:
> >> Expose power1_max_interval, that is the tau corresponding to PL1, as
> >> a custom hwmon attribute. Some bit manipulation is needed because of
> >> the format of PKG_PWR_LIM_1_TIME in PACKAGE_RAPL_LIMIT register
> (1.x
> >> * power(2,y))
> >>
> >> v2: Get rpm wake ref while accessing power1_max_interval
> >> v3: %s/hwmon/xe_hwmon/
> >>
> >> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> >> ---
> >> .../ABI/testing/sysfs-driver-intel-xe-hwmon | 11 ++
> >> drivers/gpu/drm/xe/regs/xe_mchbar_regs.h | 8 +
> >> drivers/gpu/drm/xe/xe_hwmon.c | 138
> >> +++++++++++++++++-
> >> 3 files changed, 156 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> >> b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> >> index 1a7a6c23e141..9ceb9c04b52b 100644
> >> --- a/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> >> +++ b/Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
> >> @@ -59,3 +59,14 @@ Contact: intel-xe@lists.freedesktop.org
> >> Description: RO. Energy input of device in microjoules.
> >> Only supported for particular Intel xe graphics platforms.
> >> +
> >> +What: /sys/devices/.../hwmon/hwmon<i>/power1_max_interval
> >> +Date: September 2023
> >> +KernelVersion: 6.5
> >> +Contact: intel-xe@lists.freedesktop.org
> >> +Description: RW. Sustained power limit interval (Tau in PL1/Tau)
> >> +in
> >> + milliseconds over which sustained power is averaged.
> >> +
> >> + Only supported for particular Intel xe graphics platforms.
> >> +
> >> +
> >> diff --git a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> >> b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> >> index d8ecbe1858d1..519dd1067a19 100644
> >> --- a/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> >> +++ b/drivers/gpu/drm/xe/regs/xe_mchbar_regs.h
> >> @@ -22,15 +22,23 @@
> >> #define PKG_TDP GENMASK_ULL(14, 0)
> >> #define PKG_MIN_PWR GENMASK_ULL(30, 16)
> >> #define PKG_MAX_PWR GENMASK_ULL(46, 32)
> >> +#define PKG_MAX_WIN GENMASK_ULL(54, 48) #define
> >> +PKG_MAX_WIN_X GENMASK_ULL(54, 53) #define
> >> +PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
> >> +
> >> #define PCU_CR_PACKAGE_POWER_SKU_UNIT
> >> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
> >> #define PKG_PWR_UNIT REG_GENMASK(3, 0)
> >> #define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
> >> +#define PKG_TIME_UNIT REG_GENMASK(19, 16)
> >> #define PCU_CR_PACKAGE_ENERGY_STATUS
> >> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
> >> #define PCU_CR_PACKAGE_RAPL_LIMIT
> >> XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
> >> #define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
> >> #define PKG_PWR_LIM_1_EN REG_BIT(15)
> >> +#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17) #define
> >> +PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22) #define
> >> +PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
> >> #endif /* _XE_MCHBAR_REGS_H_ */
> >> diff --git a/drivers/gpu/drm/xe/xe_hwmon.c
> >> b/drivers/gpu/drm/xe/xe_hwmon.c index cb75b9a386c0..dfa638942d47
> >> 100644
> >> --- a/drivers/gpu/drm/xe/xe_hwmon.c
> >> +++ b/drivers/gpu/drm/xe/xe_hwmon.c
> >> @@ -38,6 +38,7 @@ enum xe_hwmon_reg_operation {
> >> #define SF_CURR 1000 /* milliamperes */
> >> #define SF_VOLTAGE 1000 /* millivolts */
> >> #define SF_ENERGY 1000000 /* microjoules */
> >> +#define SF_TIME 1000 /* milliseconds */
> >> struct hwmon_energy_info {
> >> u32 reg_val_prev;
> >> @@ -50,6 +51,7 @@ struct xe_hwmon {
> >> struct mutex hwmon_lock; /* rmw operations*/
> >> int scl_shift_power;
> >> int scl_shift_energy;
> >> + int scl_shift_time;
> >> struct hwmon_energy_info ei; /* Energy info for
> >> energy1_input */
> >> };
> >> @@ -255,6 +257,138 @@ xe_hwmon_energy_get(struct xe_hwmon
> *hwmon,
> >> long
> >> *energy)
> >> xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> >> }
> >> +static ssize_t
> >> +xe_hwmon_power1_max_interval_show(struct device *dev, struct
> >> device_attribute *attr,
> >> + char *buf)
> >> +{
> >> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> >> + u32 r, x, y, x_w = 2; /* 2 bits */
> >> + u64 tau4, out;
> >> +
> >> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> >> +
> >> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
> >> + REG_READ, &r, 0, 0);
> >> +
> >> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> >> +
> >> + x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r);
> >> + y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r);
> >> + /*
> >> + * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17)
> >> + * = (4 | x) << (y - 2)
> >> + * where (y - 2) ensures a 1.x fixed point representation of 1.x
> >> + * However because y can be < 2, we compute
> >> + * tau4 = (4 | x) << y
> >> + * but add 2 when doing the final right shift to account for
> >> +units
> >> + */
> >> + tau4 = ((1 << x_w) | x) << y;
> >> + /* val in hwmon interface units (millisec) */
> >> + out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time +
> >> +x_w);
> >> +
> >> + return sysfs_emit(buf, "%llu\n", out); }
> >> +
> >> +static ssize_t
> >> +xe_hwmon_power1_max_interval_store(struct device *dev, struct
> >> device_attribute *attr,
> >> + const char *buf, size_t count) {
> >> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> >> + u32 x, y, rxy, x_w = 2; /* 2 bits */
> >> + u64 tau4, r, max_win;
> >> + unsigned long val;
> >> + int ret;
> >> +
> >> + ret = kstrtoul(buf, 0, &val);
> >> + if (ret)
> >> + return ret;
> >> +
> >> + /*
> >> + * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y =
> >> 0x12
> >> + * The hwmon->scl_shift_time default of 0xa results in a max tau
> >> of 256 seconds
> >> + */
> >> +#define PKG_MAX_WIN_DEFAULT 0x12ull
> >
> > Do we need to determine r, x, y etc for max limit ?
> >
> > Why cant we simply define MAX_LIMIT 256 ?
> PKG_MAX_WIN is field of PKG_PWR_SKU but it is observed that for some
> platforms it is invalid and for some not populated. So fixed the max limit. For
> future platforms if PKG_MAX_WIN is valid then it is prefered to read from
> register, in that case below equation is needed to calculate max limit.
That makes sense. LGTM
Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>
> Regards,
> Badal
> >
> > BR
> >
> > Himal
> >
> >> +
> >> + /*
> >> + * val must be < max in hwmon interface units. The steps below
> >> +are
> >> + * explained in xe_hwmon_power1_max_interval_show()
> >> + */
> >> + r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT);
> >> + x = REG_FIELD_GET(PKG_MAX_WIN_X, r);
> >> + y = REG_FIELD_GET(PKG_MAX_WIN_Y, r);
> >> + tau4 = ((1 << x_w) | x) << y;
> >> + max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time +
> >> x_w);
> >> +
> >> + if (val > max_win)
> >> + return -EINVAL;
> >> +
> >> + /* val in hw units */
> >> + val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time,
> >> SF_TIME);
> >> + /* Convert to 1.x * power(2,y) */
> >> + if (!val) {
> >> + /* Avoid ilog2(0) */
> >> + y = 0;
> >> + x = 0;
> >> + } else {
> >> + y = ilog2(val);
> >> + /* x = (val - (1 << y)) >> (y - 2); */
> >> + x = (val - (1ul << y)) << x_w >> y;
> >> + }
> >> +
> >> + rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) |
> >> REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y);
> >> +
> >> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> >> +
> >> + mutex_lock(&hwmon->hwmon_lock);
> >> +
> >> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW,
> (u32
> >> +*)&r,
> >> + PKG_PWR_LIM_1_TIME, rxy);
> >> +
> >> + mutex_unlock(&hwmon->hwmon_lock);
> >> +
> >> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> >> +
> >> + return count;
> >> +}
> >> +
> >> +static SENSOR_DEVICE_ATTR(power1_max_interval, 0664,
> >> + xe_hwmon_power1_max_interval_show,
> >> + xe_hwmon_power1_max_interval_store, 0);
> >> +
> >> +static struct attribute *hwmon_attributes[] = {
> >> + &sensor_dev_attr_power1_max_interval.dev_attr.attr,
> >> + NULL
> >> +};
> >> +
> >> +static umode_t xe_hwmon_attributes_visible(struct kobject *kobj,
> >> + struct attribute *attr, int index) {
> >> + struct device *dev = kobj_to_dev(kobj);
> >> + struct xe_hwmon *hwmon = dev_get_drvdata(dev);
> >> + u32 reg_val;
> >> + int ret = 0;
> >> +
> >> + xe_device_mem_access_get(gt_to_xe(hwmon->gt));
> >> +
> >> + if (attr == &sensor_dev_attr_power1_max_interval.dev_attr.attr)
> >> + ret = xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT,
> >> + REG_READ, ®_val, 0, 0) ? 0 : attr->mode;
> >> +
> >> + xe_device_mem_access_put(gt_to_xe(hwmon->gt));
> >> +
> >> + return ret;
> >> +}
> >> +
> >> +static const struct attribute_group hwmon_attrgroup = {
> >> + .attrs = hwmon_attributes,
> >> + .is_visible = xe_hwmon_attributes_visible, };
> >> +
> >> +static const struct attribute_group *hwmon_groups[] = {
> >> + &hwmon_attrgroup,
> >> + NULL
> >> +};
> >> +
> >> static const struct hwmon_channel_info *hwmon_info[] = {
> >> HWMON_CHANNEL_INFO(power, HWMON_P_MAX |
> HWMON_P_RATED_MAX |
> >> HWMON_P_CRIT),
> >> HWMON_CHANNEL_INFO(curr, HWMON_C_CRIT), @@ -573,6 +707,7
> @@
> >> xe_hwmon_get_preregistration_info(struct xe_device
> >> *xe)
> >> if (!ret) {
> >> hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT,
> >> val_sku_unit);
> >> hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT,
> >> val_sku_unit);
> >> + hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT,
> >> val_sku_unit);
> >> }
> >> /*
> >> @@ -612,7 +747,8 @@ void xe_hwmon_register(struct xe_device *xe)
> >> "xe",
> >> hwmon,
> >> &hwmon_chip_info,
> >> - NULL);
> >> + hwmon_groups);
> >> +
> >> if (IS_ERR(hwmon->hwmon_dev)) {
> >> drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n",
> >> hwmon->hwmon_dev);
> >> xe->hwmon = NULL;
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
2023-09-21 16:03 ` Rodrigo Vivi
@ 2023-09-22 15:16 ` Andi Shyti
-1 siblings, 0 replies; 53+ messages in thread
From: Andi Shyti @ 2023-09-22 15:16 UTC (permalink / raw)
To: Rodrigo Vivi
Cc: Badal Nilawar, intel-xe, linux-hwmon, anshuman.gupta,
ashutosh.dixit, linux, andi.shyti, riana.tauro, matthew.brost
Hi Rodrigo,
On Thu, Sep 21, 2023 at 12:03:26PM -0400, Rodrigo Vivi wrote:
> On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
> > Add XE_MISSING_CASE macro to handle missing switch case
> >
> > v2: Add comment about macro usage (Himal)
> >
> > Cc: Andi Shyti <andi.shyti@linux.intel.com>
> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_macros.h | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
> > index daf56c846d03..6c74c69920ed 100644
> > --- a/drivers/gpu/drm/xe/xe_macros.h
> > +++ b/drivers/gpu/drm/xe/xe_macros.h
> > @@ -15,4 +15,8 @@
> > "Ioctl argument check failed at %s:%d: %s", \
> > __FILE__, __LINE__, #cond), 1))
> >
> > +/* Parameter to macro should be a variable name */
> > +#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
> > + __stringify(x), (long)(x))
> > +
>
> No, please! Let's not add unnecessary macros.
it's not a bad idea, actually... in i915 we have the MISSING_CASE
for switch cases with a defined number of cases and print
warnings in case none if them is the one inside the switch.
It's so widely used and actually nice to have that I thought many
times to move it to some core kernel libraries.
Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
@ 2023-09-22 15:16 ` Andi Shyti
0 siblings, 0 replies; 53+ messages in thread
From: Andi Shyti @ 2023-09-22 15:16 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: linux-hwmon, intel-xe, linux
Hi Rodrigo,
On Thu, Sep 21, 2023 at 12:03:26PM -0400, Rodrigo Vivi wrote:
> On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
> > Add XE_MISSING_CASE macro to handle missing switch case
> >
> > v2: Add comment about macro usage (Himal)
> >
> > Cc: Andi Shyti <andi.shyti@linux.intel.com>
> > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_macros.h | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
> > index daf56c846d03..6c74c69920ed 100644
> > --- a/drivers/gpu/drm/xe/xe_macros.h
> > +++ b/drivers/gpu/drm/xe/xe_macros.h
> > @@ -15,4 +15,8 @@
> > "Ioctl argument check failed at %s:%d: %s", \
> > __FILE__, __LINE__, #cond), 1))
> >
> > +/* Parameter to macro should be a variable name */
> > +#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
> > + __stringify(x), (long)(x))
> > +
>
> No, please! Let's not add unnecessary macros.
it's not a bad idea, actually... in i915 we have the MISSING_CASE
for switch cases with a defined number of cases and print
warnings in case none if them is the one inside the switch.
It's so widely used and actually nice to have that I thought many
times to move it to some core kernel libraries.
Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
2023-09-22 15:16 ` [Intel-xe] " Andi Shyti
@ 2023-09-22 15:19 ` Gupta, Anshuman
-1 siblings, 0 replies; 53+ messages in thread
From: Gupta, Anshuman @ 2023-09-22 15:19 UTC (permalink / raw)
To: Andi Shyti, Vivi, Rodrigo; +Cc: linux-hwmon, intel-xe, linux
> -----Original Message-----
> From: Andi Shyti <andi.shyti@linux.intel.com>
> Sent: Friday, September 22, 2023 8:46 PM
> To: Vivi, Rodrigo <rodrigo.vivi@intel.com>
> Cc: Nilawar, Badal <badal.nilawar@intel.com>; intel-xe@lists.freedesktop.org;
> linux-hwmon@vger.kernel.org; Gupta, Anshuman
> <anshuman.gupta@intel.com>; Dixit, Ashutosh <ashutosh.dixit@intel.com>;
> linux@roeck-us.net; andi.shyti@linux.intel.com; Tauro, Riana
> <riana.tauro@intel.com>; Brost, Matthew <matthew.brost@intel.com>
> Subject: Re: [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
>
> Hi Rodrigo,
>
> On Thu, Sep 21, 2023 at 12:03:26PM -0400, Rodrigo Vivi wrote:
> > On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
> > > Add XE_MISSING_CASE macro to handle missing switch case
> > >
> > > v2: Add comment about macro usage (Himal)
> > >
> > > Cc: Andi Shyti <andi.shyti@linux.intel.com>
> > > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > > Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_macros.h | 4 ++++
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_macros.h
> > > b/drivers/gpu/drm/xe/xe_macros.h index daf56c846d03..6c74c69920ed
> > > 100644
> > > --- a/drivers/gpu/drm/xe/xe_macros.h
> > > +++ b/drivers/gpu/drm/xe/xe_macros.h
> > > @@ -15,4 +15,8 @@
> > > "Ioctl argument check failed at %s:%d: %s", \
> > > __FILE__, __LINE__, #cond), 1))
> > >
> > > +/* Parameter to macro should be a variable name */ #define
> > > +XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
> > > + __stringify(x), (long)(x))
> > > +
> >
> > No, please! Let's not add unnecessary macros.
>
> it's not a bad idea, actually... in i915 we have the MISSING_CASE for switch
> cases with a defined number of cases and print warnings in case none if them
> is the one inside the switch.
IMHO Our CI aborts the on MISSING_CASE, which is not recoverable, drm_warn would
Be better alternative here.
Thanks,
Anshuman Gupta.
>
> It's so widely used and actually nice to have that I thought many times to
> move it to some core kernel libraries.
>
> Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* RE: [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
@ 2023-09-22 15:19 ` Gupta, Anshuman
0 siblings, 0 replies; 53+ messages in thread
From: Gupta, Anshuman @ 2023-09-22 15:19 UTC (permalink / raw)
To: Andi Shyti, Vivi, Rodrigo
Cc: Nilawar, Badal, intel-xe, linux-hwmon, Dixit, Ashutosh, linux,
Tauro, Riana, Brost, Matthew
> -----Original Message-----
> From: Andi Shyti <andi.shyti@linux.intel.com>
> Sent: Friday, September 22, 2023 8:46 PM
> To: Vivi, Rodrigo <rodrigo.vivi@intel.com>
> Cc: Nilawar, Badal <badal.nilawar@intel.com>; intel-xe@lists.freedesktop.org;
> linux-hwmon@vger.kernel.org; Gupta, Anshuman
> <anshuman.gupta@intel.com>; Dixit, Ashutosh <ashutosh.dixit@intel.com>;
> linux@roeck-us.net; andi.shyti@linux.intel.com; Tauro, Riana
> <riana.tauro@intel.com>; Brost, Matthew <matthew.brost@intel.com>
> Subject: Re: [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
>
> Hi Rodrigo,
>
> On Thu, Sep 21, 2023 at 12:03:26PM -0400, Rodrigo Vivi wrote:
> > On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
> > > Add XE_MISSING_CASE macro to handle missing switch case
> > >
> > > v2: Add comment about macro usage (Himal)
> > >
> > > Cc: Andi Shyti <andi.shyti@linux.intel.com>
> > > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > > Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_macros.h | 4 ++++
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_macros.h
> > > b/drivers/gpu/drm/xe/xe_macros.h index daf56c846d03..6c74c69920ed
> > > 100644
> > > --- a/drivers/gpu/drm/xe/xe_macros.h
> > > +++ b/drivers/gpu/drm/xe/xe_macros.h
> > > @@ -15,4 +15,8 @@
> > > "Ioctl argument check failed at %s:%d: %s", \
> > > __FILE__, __LINE__, #cond), 1))
> > >
> > > +/* Parameter to macro should be a variable name */ #define
> > > +XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
> > > + __stringify(x), (long)(x))
> > > +
> >
> > No, please! Let's not add unnecessary macros.
>
> it's not a bad idea, actually... in i915 we have the MISSING_CASE for switch
> cases with a defined number of cases and print warnings in case none if them
> is the one inside the switch.
IMHO Our CI aborts the on MISSING_CASE, which is not recoverable, drm_warn would
Be better alternative here.
Thanks,
Anshuman Gupta.
>
> It's so widely used and actually nice to have that I thought many times to
> move it to some core kernel libraries.
>
> Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
2023-09-21 10:25 ` Badal Nilawar
@ 2023-09-22 17:24 ` Andi Shyti
-1 siblings, 0 replies; 53+ messages in thread
From: Andi Shyti @ 2023-09-22 17:24 UTC (permalink / raw)
To: Badal Nilawar
Cc: intel-xe, linux-hwmon, anshuman.gupta, ashutosh.dixit, linux,
andi.shyti, riana.tauro, matthew.brost, rodrigo.vivi
Hi Badal,
[...]
> +static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
> +{
> + u32 reg_val;
> +
> + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
> + if (value == PL1_DISABLE) {
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> +
> + if (reg_val & PKG_PWR_LIM_1_EN)
> + return -ENODEV;
so, here you are trying to disable PL1 and check then if it's
disabled. Shall we try at least twice before returning error?
And why ENODEV? It might be that we failed to write on the
register but it doesn't mean that the device is wrong.
> + }
> +
> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
> + reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
> + reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
> +
> + return 0;
> +}
[...]
> + /* hwmon_dev points to device hwmon<i> */
> + hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
> + "xe",
> + hwmon,
> + &hwmon_chip_info,
> + NULL);
here the allignment is a bit fancy... in this cases I wouldn't
mind going up to 100 characters or not align under the bracket.
I would write it like this
hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
"xe", hwmon, &hwmon_chip_info, NULL);
but, of course, it's a matter of taste. Up to you.
Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
@ 2023-09-22 17:24 ` Andi Shyti
0 siblings, 0 replies; 53+ messages in thread
From: Andi Shyti @ 2023-09-22 17:24 UTC (permalink / raw)
To: Badal Nilawar; +Cc: linux-hwmon, rodrigo.vivi, intel-xe, linux
Hi Badal,
[...]
> +static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
> +{
> + u32 reg_val;
> +
> + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
> + if (value == PL1_DISABLE) {
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> +
> + if (reg_val & PKG_PWR_LIM_1_EN)
> + return -ENODEV;
so, here you are trying to disable PL1 and check then if it's
disabled. Shall we try at least twice before returning error?
And why ENODEV? It might be that we failed to write on the
register but it doesn't mean that the device is wrong.
> + }
> +
> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
> + reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
> + reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
> +
> + return 0;
> +}
[...]
> + /* hwmon_dev points to device hwmon<i> */
> + hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
> + "xe",
> + hwmon,
> + &hwmon_chip_info,
> + NULL);
here the allignment is a bit fancy... in this cases I wouldn't
mind going up to 100 characters or not align under the bracket.
I would write it like this
hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
"xe", hwmon, &hwmon_chip_info, NULL);
but, of course, it's a matter of taste. Up to you.
Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
2023-09-22 15:16 ` [Intel-xe] " Andi Shyti
@ 2023-09-22 19:03 ` Rodrigo Vivi
-1 siblings, 0 replies; 53+ messages in thread
From: Rodrigo Vivi @ 2023-09-22 19:03 UTC (permalink / raw)
To: Andi Shyti
Cc: Badal Nilawar, intel-xe, linux-hwmon, anshuman.gupta,
ashutosh.dixit, linux, riana.tauro, matthew.brost
On Fri, Sep 22, 2023 at 05:16:23PM +0200, Andi Shyti wrote:
> Hi Rodrigo,
>
> On Thu, Sep 21, 2023 at 12:03:26PM -0400, Rodrigo Vivi wrote:
> > On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
> > > Add XE_MISSING_CASE macro to handle missing switch case
> > >
> > > v2: Add comment about macro usage (Himal)
> > >
> > > Cc: Andi Shyti <andi.shyti@linux.intel.com>
> > > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > > Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_macros.h | 4 ++++
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
> > > index daf56c846d03..6c74c69920ed 100644
> > > --- a/drivers/gpu/drm/xe/xe_macros.h
> > > +++ b/drivers/gpu/drm/xe/xe_macros.h
> > > @@ -15,4 +15,8 @@
> > > "Ioctl argument check failed at %s:%d: %s", \
> > > __FILE__, __LINE__, #cond), 1))
> > >
> > > +/* Parameter to macro should be a variable name */
> > > +#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
> > > + __stringify(x), (long)(x))
> > > +
> >
> > No, please! Let's not add unnecessary macros.
>
> it's not a bad idea, actually... in i915 we have the MISSING_CASE
> for switch cases with a defined number of cases and print
> warnings in case none if them is the one inside the switch.
>
> It's so widely used and actually nice to have that I thought many
> times to move it to some core kernel libraries.
to be really honest, I also liked the MISSING_CASE in many occasions.
It is useful for platform enabling so once we add a new hardware we
ensure to get some splats on the first power-on and can easily
identify the missing cases.
But even in i915 I have already seen some miss-usages of that.
And i915 is full of i915isms that we believe it is good but we
never tried to move to core kernel or when we tried we got some push
backs showing that that is not very common and desired way.
I know, just looking around Xe is also starting to get Xeisms,
but I'd like to avoid that as much as we can. in this case here
it is only 2 lines that could be a standard drm_warn or similar call.
I don't believe that it is worth adding a macro for this. So, maybe
if we really want this the right approach is to move the i915's one
to core kernel and then make Xe to start using it.
>
> Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
@ 2023-09-22 19:03 ` Rodrigo Vivi
0 siblings, 0 replies; 53+ messages in thread
From: Rodrigo Vivi @ 2023-09-22 19:03 UTC (permalink / raw)
To: Andi Shyti; +Cc: linux-hwmon, intel-xe, linux
On Fri, Sep 22, 2023 at 05:16:23PM +0200, Andi Shyti wrote:
> Hi Rodrigo,
>
> On Thu, Sep 21, 2023 at 12:03:26PM -0400, Rodrigo Vivi wrote:
> > On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
> > > Add XE_MISSING_CASE macro to handle missing switch case
> > >
> > > v2: Add comment about macro usage (Himal)
> > >
> > > Cc: Andi Shyti <andi.shyti@linux.intel.com>
> > > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> > > Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> > > ---
> > > drivers/gpu/drm/xe/xe_macros.h | 4 ++++
> > > 1 file changed, 4 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
> > > index daf56c846d03..6c74c69920ed 100644
> > > --- a/drivers/gpu/drm/xe/xe_macros.h
> > > +++ b/drivers/gpu/drm/xe/xe_macros.h
> > > @@ -15,4 +15,8 @@
> > > "Ioctl argument check failed at %s:%d: %s", \
> > > __FILE__, __LINE__, #cond), 1))
> > >
> > > +/* Parameter to macro should be a variable name */
> > > +#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
> > > + __stringify(x), (long)(x))
> > > +
> >
> > No, please! Let's not add unnecessary macros.
>
> it's not a bad idea, actually... in i915 we have the MISSING_CASE
> for switch cases with a defined number of cases and print
> warnings in case none if them is the one inside the switch.
>
> It's so widely used and actually nice to have that I thought many
> times to move it to some core kernel libraries.
to be really honest, I also liked the MISSING_CASE in many occasions.
It is useful for platform enabling so once we add a new hardware we
ensure to get some splats on the first power-on and can easily
identify the missing cases.
But even in i915 I have already seen some miss-usages of that.
And i915 is full of i915isms that we believe it is good but we
never tried to move to core kernel or when we tried we got some push
backs showing that that is not very common and desired way.
I know, just looking around Xe is also starting to get Xeisms,
but I'd like to avoid that as much as we can. in this case here
it is only 2 lines that could be a standard drm_warn or similar call.
I don't believe that it is worth adding a macro for this. So, maybe
if we really want this the right approach is to move the i915's one
to core kernel and then make Xe to start using it.
>
> Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
2023-09-22 19:03 ` [Intel-xe] " Rodrigo Vivi
@ 2023-09-25 4:07 ` Nilawar, Badal
-1 siblings, 0 replies; 53+ messages in thread
From: Nilawar, Badal @ 2023-09-25 4:07 UTC (permalink / raw)
To: Rodrigo Vivi, Andi Shyti
Cc: intel-xe, linux-hwmon, anshuman.gupta, ashutosh.dixit, linux,
riana.tauro, matthew.brost
On 23-09-2023 00:33, Rodrigo Vivi wrote:
> On Fri, Sep 22, 2023 at 05:16:23PM +0200, Andi Shyti wrote:
>> Hi Rodrigo,
>>
>> On Thu, Sep 21, 2023 at 12:03:26PM -0400, Rodrigo Vivi wrote:
>>> On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
>>>> Add XE_MISSING_CASE macro to handle missing switch case
>>>>
>>>> v2: Add comment about macro usage (Himal)
>>>>
>>>> Cc: Andi Shyti <andi.shyti@linux.intel.com>
>>>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>>>> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>>>> ---
>>>> drivers/gpu/drm/xe/xe_macros.h | 4 ++++
>>>> 1 file changed, 4 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
>>>> index daf56c846d03..6c74c69920ed 100644
>>>> --- a/drivers/gpu/drm/xe/xe_macros.h
>>>> +++ b/drivers/gpu/drm/xe/xe_macros.h
>>>> @@ -15,4 +15,8 @@
>>>> "Ioctl argument check failed at %s:%d: %s", \
>>>> __FILE__, __LINE__, #cond), 1))
>>>>
>>>> +/* Parameter to macro should be a variable name */
>>>> +#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
>>>> + __stringify(x), (long)(x))
>>>> +
>>>
>>> No, please! Let's not add unnecessary macros.
>>
>> it's not a bad idea, actually... in i915 we have the MISSING_CASE
>> for switch cases with a defined number of cases and print
>> warnings in case none if them is the one inside the switch.
>>
>> It's so widely used and actually nice to have that I thought many
>> times to move it to some core kernel libraries.
>
> to be really honest, I also liked the MISSING_CASE in many occasions.
> It is useful for platform enabling so once we add a new hardware we
> ensure to get some splats on the first power-on and can easily
> identify the missing cases.
>
> But even in i915 I have already seen some miss-usages of that.
> And i915 is full of i915isms that we believe it is good but we
> never tried to move to core kernel or when we tried we got some push
> backs showing that that is not very common and desired way.
>
> I know, just looking around Xe is also starting to get Xeisms,
> but I'd like to avoid that as much as we can. in this case here
> it is only 2 lines that could be a standard drm_warn or similar call.
>
> I don't believe that it is worth adding a macro for this. So, maybe
> if we really want this the right approach is to move the i915's one
> to core kernel and then make Xe to start using it.
Agreed, for this use case I will also prefer to go with drm_warn.
Regards,
Badal
>
>>
>> Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
@ 2023-09-25 4:07 ` Nilawar, Badal
0 siblings, 0 replies; 53+ messages in thread
From: Nilawar, Badal @ 2023-09-25 4:07 UTC (permalink / raw)
To: Rodrigo Vivi, Andi Shyti; +Cc: linux-hwmon, linux, intel-xe
On 23-09-2023 00:33, Rodrigo Vivi wrote:
> On Fri, Sep 22, 2023 at 05:16:23PM +0200, Andi Shyti wrote:
>> Hi Rodrigo,
>>
>> On Thu, Sep 21, 2023 at 12:03:26PM -0400, Rodrigo Vivi wrote:
>>> On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
>>>> Add XE_MISSING_CASE macro to handle missing switch case
>>>>
>>>> v2: Add comment about macro usage (Himal)
>>>>
>>>> Cc: Andi Shyti <andi.shyti@linux.intel.com>
>>>> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>>>> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>>>> ---
>>>> drivers/gpu/drm/xe/xe_macros.h | 4 ++++
>>>> 1 file changed, 4 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/xe/xe_macros.h b/drivers/gpu/drm/xe/xe_macros.h
>>>> index daf56c846d03..6c74c69920ed 100644
>>>> --- a/drivers/gpu/drm/xe/xe_macros.h
>>>> +++ b/drivers/gpu/drm/xe/xe_macros.h
>>>> @@ -15,4 +15,8 @@
>>>> "Ioctl argument check failed at %s:%d: %s", \
>>>> __FILE__, __LINE__, #cond), 1))
>>>>
>>>> +/* Parameter to macro should be a variable name */
>>>> +#define XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
>>>> + __stringify(x), (long)(x))
>>>> +
>>>
>>> No, please! Let's not add unnecessary macros.
>>
>> it's not a bad idea, actually... in i915 we have the MISSING_CASE
>> for switch cases with a defined number of cases and print
>> warnings in case none if them is the one inside the switch.
>>
>> It's so widely used and actually nice to have that I thought many
>> times to move it to some core kernel libraries.
>
> to be really honest, I also liked the MISSING_CASE in many occasions.
> It is useful for platform enabling so once we add a new hardware we
> ensure to get some splats on the first power-on and can easily
> identify the missing cases.
>
> But even in i915 I have already seen some miss-usages of that.
> And i915 is full of i915isms that we believe it is good but we
> never tried to move to core kernel or when we tried we got some push
> backs showing that that is not very common and desired way.
>
> I know, just looking around Xe is also starting to get Xeisms,
> but I'd like to avoid that as much as we can. in this case here
> it is only 2 lines that could be a standard drm_warn or similar call.
>
> I don't believe that it is worth adding a macro for this. So, maybe
> if we really want this the right approach is to move the i915's one
> to core kernel and then make Xe to start using it.
Agreed, for this use case I will also prefer to go with drm_warn.
Regards,
Badal
>
>>
>> Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
2023-09-22 17:24 ` [Intel-xe] " Andi Shyti
@ 2023-09-25 4:34 ` Nilawar, Badal
-1 siblings, 0 replies; 53+ messages in thread
From: Nilawar, Badal @ 2023-09-25 4:34 UTC (permalink / raw)
To: Andi Shyti
Cc: intel-xe, linux-hwmon, anshuman.gupta, ashutosh.dixit, linux,
riana.tauro, matthew.brost, rodrigo.vivi
Hi Andi,
On 22-09-2023 22:54, Andi Shyti wrote:
> Hi Badal,
>
> [...]
>
>> +static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
>> +{
>> + u32 reg_val;
>> +
>> + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
>> + if (value == PL1_DISABLE) {
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
>> + PKG_PWR_LIM_1_EN, 0);
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
>> + PKG_PWR_LIM_1_EN, 0);
>> +
>> + if (reg_val & PKG_PWR_LIM_1_EN)
>> + return -ENODEV;
>
> so, here you are trying to disable PL1 and check then if it's
> disabled. Shall we try at least twice before returning error?
I think lets keep write once only.
>
> And why ENODEV? It might be that we failed to write on the
> register but it doesn't mean that the device is wrong.
Will return ENOSUPP.
>
>> + }
>> +
>> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
>> + reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
>> + reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
>> + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
>> +
>> + return 0;
>> +}
>
> [...]
>
>> + /* hwmon_dev points to device hwmon<i> */
>> + hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
>> + "xe",
>> + hwmon,
>> + &hwmon_chip_info,
>> + NULL);
>
> here the allignment is a bit fancy... in this cases I wouldn't
> mind going up to 100 characters or not align under the bracket.
>
> I would write it like this
>
> hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
> "xe", hwmon, &hwmon_chip_info, NULL);
>
> but, of course, it's a matter of taste. Up to you.
Not sure why this is fancy. Above suggestion checkpatch --strict throws
CHECK: Alignment should match open parenthesis.
If I write like this checkpatch goes fine.
hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe",
hwmon,
&hwmon_chip_info,
NULL);
Regards,
Badal
>
> Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
@ 2023-09-25 4:34 ` Nilawar, Badal
0 siblings, 0 replies; 53+ messages in thread
From: Nilawar, Badal @ 2023-09-25 4:34 UTC (permalink / raw)
To: Andi Shyti; +Cc: linux-hwmon, linux, rodrigo.vivi, intel-xe
Hi Andi,
On 22-09-2023 22:54, Andi Shyti wrote:
> Hi Badal,
>
> [...]
>
>> +static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
>> +{
>> + u32 reg_val;
>> +
>> + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
>> + if (value == PL1_DISABLE) {
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
>> + PKG_PWR_LIM_1_EN, 0);
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
>> + PKG_PWR_LIM_1_EN, 0);
>> +
>> + if (reg_val & PKG_PWR_LIM_1_EN)
>> + return -ENODEV;
>
> so, here you are trying to disable PL1 and check then if it's
> disabled. Shall we try at least twice before returning error?
I think lets keep write once only.
>
> And why ENODEV? It might be that we failed to write on the
> register but it doesn't mean that the device is wrong.
Will return ENOSUPP.
>
>> + }
>> +
>> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
>> + reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
>> + reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
>> +
>> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
>> + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
>> +
>> + return 0;
>> +}
>
> [...]
>
>> + /* hwmon_dev points to device hwmon<i> */
>> + hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
>> + "xe",
>> + hwmon,
>> + &hwmon_chip_info,
>> + NULL);
>
> here the allignment is a bit fancy... in this cases I wouldn't
> mind going up to 100 characters or not align under the bracket.
>
> I would write it like this
>
> hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
> "xe", hwmon, &hwmon_chip_info, NULL);
>
> but, of course, it's a matter of taste. Up to you.
Not sure why this is fancy. Above suggestion checkpatch --strict throws
CHECK: Alignment should match open parenthesis.
If I write like this checkpatch goes fine.
hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe",
hwmon,
&hwmon_chip_info,
NULL);
Regards,
Badal
>
> Andi
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Intel-xe] [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
2023-09-22 15:19 ` Gupta, Anshuman
(?)
@ 2023-09-25 12:08 ` Jani Nikula
-1 siblings, 0 replies; 53+ messages in thread
From: Jani Nikula @ 2023-09-25 12:08 UTC (permalink / raw)
To: Gupta, Anshuman, Andi Shyti, Vivi, Rodrigo; +Cc: linux-hwmon, intel-xe, linux
On Fri, 22 Sep 2023, "Gupta, Anshuman" <anshuman.gupta@intel.com> wrote:
>> -----Original Message-----
>> From: Andi Shyti <andi.shyti@linux.intel.com>
>> Sent: Friday, September 22, 2023 8:46 PM
>> To: Vivi, Rodrigo <rodrigo.vivi@intel.com>
>> Cc: Nilawar, Badal <badal.nilawar@intel.com>; intel-xe@lists.freedesktop.org;
>> linux-hwmon@vger.kernel.org; Gupta, Anshuman
>> <anshuman.gupta@intel.com>; Dixit, Ashutosh <ashutosh.dixit@intel.com>;
>> linux@roeck-us.net; andi.shyti@linux.intel.com; Tauro, Riana
>> <riana.tauro@intel.com>; Brost, Matthew <matthew.brost@intel.com>
>> Subject: Re: [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro
>>
>> Hi Rodrigo,
>>
>> On Thu, Sep 21, 2023 at 12:03:26PM -0400, Rodrigo Vivi wrote:
>> > On Thu, Sep 21, 2023 at 03:55:14PM +0530, Badal Nilawar wrote:
>> > > Add XE_MISSING_CASE macro to handle missing switch case
>> > >
>> > > v2: Add comment about macro usage (Himal)
>> > >
>> > > Cc: Andi Shyti <andi.shyti@linux.intel.com>
>> > > Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
>> > > Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
>> > > ---
>> > > drivers/gpu/drm/xe/xe_macros.h | 4 ++++
>> > > 1 file changed, 4 insertions(+)
>> > >
>> > > diff --git a/drivers/gpu/drm/xe/xe_macros.h
>> > > b/drivers/gpu/drm/xe/xe_macros.h index daf56c846d03..6c74c69920ed
>> > > 100644
>> > > --- a/drivers/gpu/drm/xe/xe_macros.h
>> > > +++ b/drivers/gpu/drm/xe/xe_macros.h
>> > > @@ -15,4 +15,8 @@
>> > > "Ioctl argument check failed at %s:%d: %s", \
>> > > __FILE__, __LINE__, #cond), 1))
>> > >
>> > > +/* Parameter to macro should be a variable name */ #define
>> > > +XE_MISSING_CASE(x) WARN(1, "Missing case (%s == %ld)\n", \
>> > > + __stringify(x), (long)(x))
>> > > +
>> >
>> > No, please! Let's not add unnecessary macros.
>>
>> it's not a bad idea, actually... in i915 we have the MISSING_CASE for switch
>> cases with a defined number of cases and print warnings in case none if them
>> is the one inside the switch.
> IMHO Our CI aborts the on MISSING_CASE, which is not recoverable, drm_warn would
> Be better alternative here.
The whole point is that it aborts, so it won't get ignored. It's only
for cases like this.
BR,
Jani.
> Thanks,
> Anshuman Gupta.
>>
>> It's so widely used and actually nice to have that I thought many times to
>> move it to some core kernel libraries.
>>
>> Andi
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 53+ messages in thread
end of thread, other threads:[~2023-09-25 12:08 UTC | newest]
Thread overview: 53+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-09-21 10:25 [Intel-xe] [PATCH v5 0/6] Add HWMON support for DGFX Badal Nilawar
2023-09-21 10:25 ` Badal Nilawar
2023-09-21 10:21 ` [Intel-xe] ✓ CI.Patch_applied: success for Add HWMON support for DGFX (rev5) Patchwork
2023-09-21 10:21 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-09-21 10:23 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro Badal Nilawar
2023-09-21 10:25 ` Badal Nilawar
2023-09-21 16:03 ` [Intel-xe] " Rodrigo Vivi
2023-09-21 16:03 ` Rodrigo Vivi
2023-09-21 16:59 ` [Intel-xe] " Nilawar, Badal
2023-09-21 16:59 ` Nilawar, Badal
2023-09-22 10:05 ` [Intel-xe] " Jani Nikula
2023-09-22 15:16 ` Andi Shyti
2023-09-22 15:16 ` [Intel-xe] " Andi Shyti
2023-09-22 15:19 ` Gupta, Anshuman
2023-09-22 15:19 ` Gupta, Anshuman
2023-09-25 12:08 ` [Intel-xe] " Jani Nikula
2023-09-22 19:03 ` Rodrigo Vivi
2023-09-22 19:03 ` [Intel-xe] " Rodrigo Vivi
2023-09-25 4:07 ` Nilawar, Badal
2023-09-25 4:07 ` [Intel-xe] " Nilawar, Badal
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes Badal Nilawar
2023-09-21 10:25 ` Badal Nilawar
2023-09-21 13:22 ` [Intel-xe] " Riana Tauro
2023-09-21 13:22 ` Riana Tauro
2023-09-21 16:25 ` [Intel-xe] " Rodrigo Vivi
2023-09-21 16:25 ` Rodrigo Vivi
2023-09-22 9:57 ` Nilawar, Badal
2023-09-22 9:57 ` Nilawar, Badal
2023-09-22 17:24 ` Andi Shyti
2023-09-22 17:24 ` [Intel-xe] " Andi Shyti
2023-09-25 4:34 ` Nilawar, Badal
2023-09-25 4:34 ` [Intel-xe] " Nilawar, Badal
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 3/6] drm/xe/hwmon: Expose card reactive critical power Badal Nilawar
2023-09-21 10:25 ` Badal Nilawar
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 4/6] drm/xe/hwmon: Expose input voltage attribute Badal Nilawar
2023-09-21 10:25 ` Badal Nilawar
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 5/6] drm/xe/hwmon: Expose hwmon energy attribute Badal Nilawar
2023-09-21 10:25 ` Badal Nilawar
2023-09-21 14:09 ` [Intel-xe] " Riana Tauro
2023-09-21 14:09 ` Riana Tauro
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 6/6] drm/xe/hwmon: Expose power1_max_interval Badal Nilawar
2023-09-21 10:25 ` Badal Nilawar
2023-09-21 11:43 ` [Intel-xe] " Ghimiray, Himal Prasad
2023-09-21 11:43 ` Ghimiray, Himal Prasad
2023-09-22 9:49 ` Nilawar, Badal
2023-09-22 9:49 ` Nilawar, Badal
2023-09-22 12:43 ` Ghimiray, Himal Prasad
2023-09-22 12:43 ` Ghimiray, Himal Prasad
2023-09-21 10:30 ` [Intel-xe] ✓ CI.Build: success for Add HWMON support for DGFX (rev5) Patchwork
2023-09-21 10:30 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
2023-09-21 10:31 ` [Intel-xe] ✓ CI.checksparse: success " Patchwork
2023-09-21 11:05 ` [Intel-xe] ✗ CI.BAT: failure " Patchwork
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