* [PATCH v3 0/6] Pointer Masking update for Zjpm v0.8
@ 2024-01-03 18:57 Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
` (5 more replies)
0 siblings, 6 replies; 20+ messages in thread
From: Alexey Baturo @ 2024-01-03 18:57 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Hi,
There patches are updated after Richard's comments:
- moved new tb flags to the end
- used tcg_gen_(s)extract to get the final address
- properly handle CONFIG_USER_ONLY
Thanks
[v2]:
As per Richard's suggestion I made pmm field part of tb_flags.
It allowed to get rid of global variable to store pmlen.
Also it allowed to simplify all the machinery around it.
Thanks
[v1]:
Hi all,
It looks like Zjpm v0.8 is almost frozen and we don't expect it change drastically anymore.
Compared to the original implementation with explicit base and mask CSRs, we now only have
several fixed options for number of masked bits which are set using existing CSRs.
The changes have been tested with handwritten assembly tests and LLVM HWASAN
test suite.
Thanks
Alexey Baturo (6):
target/riscv: Remove obsolete pointer masking extension code.
target/riscv: Add new CSR fields for S{sn,mn,m}pm extensions as part
of Zjpm v0.8
target/riscv: Add helper functions to calculate current number of
masked bits for pointer masking
target/riscv: Add pointer masking tb flags
target/riscv: Update address modify functions to take into account
pointer masking
target/riscv: Enable updates for pointer masking variables and thus
enable pointer masking extension
target/riscv/cpu.c | 18 +-
target/riscv/cpu.h | 45 +++--
target/riscv/cpu_bits.h | 90 +---------
target/riscv/cpu_cfg.h | 3 +
target/riscv/cpu_helper.c | 93 +++++-----
target/riscv/csr.c | 337 ++---------------------------------
target/riscv/machine.c | 15 +-
target/riscv/pmp.c | 13 +-
target/riscv/pmp.h | 11 +-
target/riscv/translate.c | 46 ++---
target/riscv/vector_helper.c | 14 +-
11 files changed, 147 insertions(+), 538 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code.
2024-01-03 18:57 [PATCH v3 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
@ 2024-01-03 18:57 ` Alexey Baturo
2024-01-05 5:04 ` Alistair Francis
2024-01-03 18:57 ` [PATCH v3 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Alexey Baturo
` (4 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Alexey Baturo @ 2024-01-03 18:57 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
The newer version doesn't allow to specify custom mask or base for masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/cpu.c | 10 --
target/riscv/cpu.h | 32 +---
target/riscv/cpu_bits.h | 87 ----------
target/riscv/cpu_helper.c | 52 ------
target/riscv/csr.c | 326 -----------------------------------
target/riscv/machine.c | 9 -
target/riscv/translate.c | 27 +--
target/riscv/vector_helper.c | 2 +-
8 files changed, 10 insertions(+), 535 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 83c7c0cf07..1e6571ce99 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -710,13 +710,6 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
CSR_MSCRATCH,
CSR_SSCRATCH,
CSR_SATP,
- CSR_MMTE,
- CSR_UPMBASE,
- CSR_UPMMASK,
- CSR_SPMBASE,
- CSR_SPMMASK,
- CSR_MPMBASE,
- CSR_MPMMASK,
};
for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
@@ -891,8 +884,6 @@ static void riscv_cpu_reset_hold(Object *obj)
}
i++;
}
- /* mmte is supposed to have pm.current hardwired to 1 */
- env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
/*
* Clear mseccfg and unlock all the PMP entries upon reset.
@@ -906,7 +897,6 @@ static void riscv_cpu_reset_hold(Object *obj)
pmp_unlock_entries(env);
#endif
env->xl = riscv_cpu_mxl(env);
- riscv_cpu_update_mask(env);
cs->exception_index = RISCV_EXCP_NONE;
env->load_res = -1;
set_default_nan_mode(1, &env->fp_status);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d74b361be6..73f7004936 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -374,18 +374,7 @@ struct CPUArchState {
/* True if in debugger mode. */
bool debugger;
- /*
- * CSRs for PointerMasking extension
- */
- target_ulong mmte;
- target_ulong mpmmask;
- target_ulong mpmbase;
- target_ulong spmmask;
- target_ulong spmbase;
- target_ulong upmmask;
- target_ulong upmbase;
-
- /* CSRs for execution environment configuration */
+ /* CSRs for execution enviornment configuration */
uint64_t menvcfg;
uint64_t mstateen[SMSTATEEN_MAX_COUNT];
uint64_t hstateen[SMSTATEEN_MAX_COUNT];
@@ -393,8 +382,6 @@ struct CPUArchState {
target_ulong senvcfg;
uint64_t henvcfg;
#endif
- target_ulong cur_pmmask;
- target_ulong cur_pmbase;
/* Fields from here on are preserved across CPU reset. */
QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
@@ -543,17 +530,14 @@ FIELD(TB_FLAGS, VILL, 14, 1)
FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
/* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
FIELD(TB_FLAGS, XL, 16, 2)
-/* If PointerMasking should be applied */
-FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
-FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
-FIELD(TB_FLAGS, VTA, 20, 1)
-FIELD(TB_FLAGS, VMA, 21, 1)
+FIELD(TB_FLAGS, VTA, 18, 1)
+FIELD(TB_FLAGS, VMA, 19, 1)
/* Native debug itrigger */
-FIELD(TB_FLAGS, ITRIGGER, 22, 1)
+FIELD(TB_FLAGS, ITRIGGER, 20, 1)
/* Virtual mode enabled */
-FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
-FIELD(TB_FLAGS, PRIV, 24, 2)
-FIELD(TB_FLAGS, AXL, 26, 2)
+FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1)
+FIELD(TB_FLAGS, PRIV, 22, 2)
+FIELD(TB_FLAGS, AXL, 24, 2)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
@@ -680,8 +664,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags);
-void riscv_cpu_update_mask(CPURISCVState *env);
-
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index ebd7917d49..1c92458a01 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -491,37 +491,6 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
-/*
- * User PointerMasking registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_UMTE 0x4c0
-#define CSR_UPMMASK 0x4c1
-#define CSR_UPMBASE 0x4c2
-
-/*
- * Machine PointerMasking registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_MMTE 0x3c0
-#define CSR_MPMMASK 0x3c1
-#define CSR_MPMBASE 0x3c2
-
-/*
- * Supervisor PointerMaster registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_SMTE 0x1c0
-#define CSR_SPMMASK 0x1c1
-#define CSR_SPMBASE 0x1c2
-
-/*
- * Hypervisor PointerMaster registers
- * NB: actual CSR numbers might be changed in future
- */
-#define CSR_VSMTE 0x2c0
-#define CSR_VSPMMASK 0x2c1
-#define CSR_VSPMBASE 0x2c2
#define CSR_SCOUNTOVF 0xda0
/* Crypto Extension */
@@ -741,11 +710,6 @@ typedef enum RISCVException {
#define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
#define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
-/* General PointerMasking CSR bits */
-#define PM_ENABLE 0x00000001ULL
-#define PM_CURRENT 0x00000002ULL
-#define PM_INSN 0x00000004ULL
-
/* Execution environment configuration bits */
#define MENVCFG_FIOM BIT(0)
#define MENVCFG_CBIE (3UL << 4)
@@ -778,57 +742,6 @@ typedef enum RISCVException {
#define HENVCFGH_PBMTE MENVCFGH_PBMTE
#define HENVCFGH_STCE MENVCFGH_STCE
-/* Offsets for every pair of control bits per each priv level */
-#define XS_OFFSET 0ULL
-#define U_OFFSET 2ULL
-#define S_OFFSET 5ULL
-#define M_OFFSET 8ULL
-
-#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
-#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
-#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
-#define U_PM_INSN (PM_INSN << U_OFFSET)
-#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
-#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
-#define S_PM_INSN (PM_INSN << S_OFFSET)
-#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
-#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
-#define M_PM_INSN (PM_INSN << M_OFFSET)
-
-/* mmte CSR bits */
-#define MMTE_PM_XS_BITS PM_XS_BITS
-#define MMTE_U_PM_ENABLE U_PM_ENABLE
-#define MMTE_U_PM_CURRENT U_PM_CURRENT
-#define MMTE_U_PM_INSN U_PM_INSN
-#define MMTE_S_PM_ENABLE S_PM_ENABLE
-#define MMTE_S_PM_CURRENT S_PM_CURRENT
-#define MMTE_S_PM_INSN S_PM_INSN
-#define MMTE_M_PM_ENABLE M_PM_ENABLE
-#define MMTE_M_PM_CURRENT M_PM_CURRENT
-#define MMTE_M_PM_INSN M_PM_INSN
-#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \
- MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \
- MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \
- MMTE_PM_XS_BITS)
-
-/* (v)smte CSR bits */
-#define SMTE_PM_XS_BITS PM_XS_BITS
-#define SMTE_U_PM_ENABLE U_PM_ENABLE
-#define SMTE_U_PM_CURRENT U_PM_CURRENT
-#define SMTE_U_PM_INSN U_PM_INSN
-#define SMTE_S_PM_ENABLE S_PM_ENABLE
-#define SMTE_S_PM_CURRENT S_PM_CURRENT
-#define SMTE_S_PM_INSN S_PM_INSN
-#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \
- SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \
- SMTE_PM_XS_BITS)
-
-/* umte CSR bits */
-#define UMTE_U_PM_ENABLE U_PM_ENABLE
-#define UMTE_U_PM_CURRENT U_PM_CURRENT
-#define UMTE_U_PM_INSN U_PM_INSN
-#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
-
/* MISELECT, SISELECT, and VSISELECT bits (AIA) */
#define ISELECT_IPRIO0 0x30
#define ISELECT_IPRIO15 0x3f
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index e7e23b34f4..a3d477d226 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -135,61 +135,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
- if (env->cur_pmmask != 0) {
- flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
- }
- if (env->cur_pmbase != 0) {
- flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
- }
*pflags = flags;
}
-void riscv_cpu_update_mask(CPURISCVState *env)
-{
- target_ulong mask = 0, base = 0;
- RISCVMXL xl = env->xl;
- /*
- * TODO: Current RVJ spec does not specify
- * how the extension interacts with XLEN.
- */
-#ifndef CONFIG_USER_ONLY
- int mode = cpu_address_mode(env);
- xl = cpu_get_xl(env, mode);
- if (riscv_has_ext(env, RVJ)) {
- switch (mode) {
- case PRV_M:
- if (env->mmte & M_PM_ENABLE) {
- mask = env->mpmmask;
- base = env->mpmbase;
- }
- break;
- case PRV_S:
- if (env->mmte & S_PM_ENABLE) {
- mask = env->spmmask;
- base = env->spmbase;
- }
- break;
- case PRV_U:
- if (env->mmte & U_PM_ENABLE) {
- mask = env->upmmask;
- base = env->upmbase;
- }
- break;
- default:
- g_assert_not_reached();
- }
- }
-#endif
- if (xl == MXL_RV32) {
- env->cur_pmmask = mask & UINT32_MAX;
- env->cur_pmbase = base & UINT32_MAX;
- } else {
- env->cur_pmmask = mask;
- env->cur_pmbase = base;
- }
-}
-
#ifndef CONFIG_USER_ONLY
/*
@@ -721,7 +670,6 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
/* tlb_flush is unnecessary as mode is contained in mmu_idx */
env->priv = newpriv;
env->xl = cpu_recompute_xl(env);
- riscv_cpu_update_mask(env);
/*
* Clear the load reservation - otherwise a reservation placed in one
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fde7ce1a53..ea4e1ac6ef 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -483,16 +483,6 @@ static RISCVException hgatp(CPURISCVState *env, int csrno)
return hmode(env, csrno);
}
-/* Checks if PointerMasking registers could be accessed */
-static RISCVException pointer_masking(CPURISCVState *env, int csrno)
-{
- /* Check if j-ext is present */
- if (riscv_has_ext(env, RVJ)) {
- return RISCV_EXCP_NONE;
- }
- return RISCV_EXCP_ILLEGAL_INST;
-}
-
static int aia_hmode(CPURISCVState *env, int csrno)
{
if (!riscv_cpu_cfg(env)->ext_ssaia) {
@@ -1355,7 +1345,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
env->xl = cpu_recompute_xl(env);
}
- riscv_cpu_update_mask(env);
return RISCV_EXCP_NONE;
}
@@ -3900,302 +3889,6 @@ static RISCVException read_tinfo(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-/*
- * Functions to access Pointer Masking feature registers
- * We have to check if current priv lvl could modify
- * csr in given mode
- */
-static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
-{
- int csr_priv = get_field(csrno, 0x300);
- int pm_current;
-
- if (env->debugger) {
- return false;
- }
- /*
- * If priv lvls differ that means we're accessing csr from higher priv lvl,
- * so allow the access
- */
- if (env->priv != csr_priv) {
- return false;
- }
- switch (env->priv) {
- case PRV_M:
- pm_current = get_field(env->mmte, M_PM_CURRENT);
- break;
- case PRV_S:
- pm_current = get_field(env->mmte, S_PM_CURRENT);
- break;
- case PRV_U:
- pm_current = get_field(env->mmte, U_PM_CURRENT);
- break;
- default:
- g_assert_not_reached();
- }
- /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
- return !pm_current;
-}
-
-static RISCVException read_mmte(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->mmte & MMTE_MASK;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_mmte(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
- target_ulong wpri_val = val & MMTE_MASK;
-
- if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
- TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x",
- val, "vs expected 0x", wpri_val);
- }
- /* for machine mode pm.current is hardwired to 1 */
- wpri_val |= MMTE_M_PM_CURRENT;
-
- /* hardwiring pm.instruction bit to 0, since it's not supported yet */
- wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
- env->mmte = wpri_val | EXT_STATUS_DIRTY;
- riscv_cpu_update_mask(env);
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_smte(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->mmte & SMTE_MASK;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_smte(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- target_ulong wpri_val = val & SMTE_MASK;
-
- if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
- TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x",
- val, "vs expected 0x", wpri_val);
- }
-
- /* if pm.current==0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
-
- wpri_val |= (env->mmte & ~SMTE_MASK);
- write_mmte(env, csrno, wpri_val);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_umte(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->mmte & UMTE_MASK;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_umte(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- target_ulong wpri_val = val & UMTE_MASK;
-
- if (val != wpri_val) {
- qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
- TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x",
- val, "vs expected 0x", wpri_val);
- }
-
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
-
- wpri_val |= (env->mmte & ~UMTE_MASK);
- write_mmte(env, csrno, wpri_val);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->mpmmask;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- env->mpmmask = val;
- if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
- env->cur_pmmask = val;
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_spmmask(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->spmmask;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_spmmask(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current==0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->spmmask = val;
- if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
- env->cur_pmmask = val;
- if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
- env->cur_pmmask &= UINT32_MAX;
- }
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_upmmask(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->upmmask;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_upmmask(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current==0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->upmmask = val;
- if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
- env->cur_pmmask = val;
- if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
- env->cur_pmmask &= UINT32_MAX;
- }
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->mpmbase;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- env->mpmbase = val;
- if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
- env->cur_pmbase = val;
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_spmbase(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->spmbase;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_spmbase(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current==0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->spmbase = val;
- if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
- env->cur_pmbase = val;
- if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
- env->cur_pmbase &= UINT32_MAX;
- }
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException read_upmbase(CPURISCVState *env, int csrno,
- target_ulong *val)
-{
- *val = env->upmbase;
- return RISCV_EXCP_NONE;
-}
-
-static RISCVException write_upmbase(CPURISCVState *env, int csrno,
- target_ulong val)
-{
- uint64_t mstatus;
-
- /* if pm.current==0 we can't modify current PM CSRs */
- if (check_pm_current_disabled(env, csrno)) {
- return RISCV_EXCP_NONE;
- }
- env->upmbase = val;
- if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
- env->cur_pmbase = val;
- if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
- env->cur_pmbase &= UINT32_MAX;
- }
- }
- env->mmte |= EXT_STATUS_DIRTY;
-
- /* Set XS and SD bits, since PM CSRs are dirty */
- mstatus = env->mstatus | MSTATUS_XS;
- write_mstatus(env, csrno, mstatus);
- return RISCV_EXCP_NONE;
-}
-
#endif
/* Crypto Extension */
@@ -4800,25 +4493,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
[CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore },
- /* User Pointer Masking */
- [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
- [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask,
- write_upmmask },
- [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase,
- write_upmbase },
- /* Machine Pointer Masking */
- [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
- [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask,
- write_mpmmask },
- [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase,
- write_mpmbase },
- /* Supervisor Pointer Masking */
- [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
- [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask,
- write_spmmask },
- [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase,
- write_spmbase },
-
/* Performance Counters */
[CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter },
[CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter },
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index fdde243e04..860fe56d43 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -164,14 +164,6 @@ static const VMStateDescription vmstate_pointermasking = {
.minimum_version_id = 1,
.needed = pointermasking_needed,
.fields = (VMStateField[]) {
- VMSTATE_UINTTL(env.mmte, RISCVCPU),
- VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
- VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
- VMSTATE_UINTTL(env.spmmask, RISCVCPU),
- VMSTATE_UINTTL(env.spmbase, RISCVCPU),
- VMSTATE_UINTTL(env.upmmask, RISCVCPU),
- VMSTATE_UINTTL(env.upmbase, RISCVCPU),
-
VMSTATE_END_OF_LIST()
}
};
@@ -267,7 +259,6 @@ static int riscv_cpu_post_load(void *opaque, int version_id)
CPURISCVState *env = &cpu->env;
env->xl = cpu_recompute_xl(env);
- riscv_cpu_update_mask(env);
return 0;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f0be79bb16..6b4b9a671c 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -42,9 +42,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
-/* globals for PM CSRs */
-static TCGv pm_mask;
-static TCGv pm_base;
/*
* If an operation is being performed on less than TARGET_LONG_BITS,
@@ -106,9 +103,6 @@ typedef struct DisasContext {
bool vl_eq_vlmax;
CPUState *cs;
TCGv zero;
- /* PointerMasking extension */
- bool pm_mask_enabled;
- bool pm_base_enabled;
/* Use icount trigger for native debug */
bool itrigger;
/* FRM is known to contain a valid value. */
@@ -582,14 +576,9 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_addi_tl(addr, src1, imm);
- if (ctx->pm_mask_enabled) {
- tcg_gen_andc_tl(addr, addr, pm_mask);
- } else if (get_address_xl(ctx) == MXL_RV32) {
+ if (get_address_xl(ctx) == MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
- if (ctx->pm_base_enabled) {
- tcg_gen_or_tl(addr, addr, pm_base);
- }
return addr;
}
@@ -601,14 +590,9 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_add_tl(addr, src1, offs);
- if (ctx->pm_mask_enabled) {
- tcg_gen_andc_tl(addr, addr, pm_mask);
- } else if (get_xl(ctx) == MXL_RV32) {
+ if (get_xl(ctx) == MXL_RV32) {
tcg_gen_ext32u_tl(addr, addr);
}
- if (ctx->pm_base_enabled) {
- tcg_gen_or_tl(addr, addr, pm_base);
- }
return addr;
}
@@ -1192,8 +1176,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs;
- ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
- ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
ctx->virt_inst_excp = false;
@@ -1325,9 +1307,4 @@ void riscv_translate_init(void)
"load_res");
load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
"load_val");
- /* Assign PM CSRs to tcg globals */
- pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask),
- "pmmask");
- pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase),
- "pmbase");
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index c1c3a4d1ea..8e7a8e80a0 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -94,7 +94,7 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
{
- return (addr & ~env->cur_pmmask) | env->cur_pmbase;
+ return addr;
}
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8
2024-01-03 18:57 [PATCH v3 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
@ 2024-01-03 18:57 ` Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
` (3 subsequent siblings)
5 siblings, 0 replies; 20+ messages in thread
From: Alexey Baturo @ 2024-01-03 18:57 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/cpu.h | 8 ++++++++
target/riscv/cpu_bits.h | 3 +++
target/riscv/cpu_cfg.h | 3 +++
target/riscv/csr.c | 11 +++++++++++
target/riscv/machine.c | 6 ++++--
target/riscv/pmp.c | 13 ++++++++++---
target/riscv/pmp.h | 11 ++++++-----
7 files changed, 45 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 73f7004936..bd379ee653 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -102,6 +102,14 @@ typedef enum {
EXT_STATUS_DIRTY,
} RISCVExtStatus;
+/* Enum holds PMM field values for Zjpm v0.8 extension */
+typedef enum {
+ PMM_FIELD_DISABLED = 0,
+ PMM_FIELD_RESERVED = 1,
+ PMM_FIELD_PMLEN7 = 2,
+ PMM_FIELD_PMLEN16 = 3,
+} RISCVPmPmm;
+
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 1c92458a01..7cf1049bf4 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -715,6 +715,7 @@ typedef enum RISCVException {
#define MENVCFG_CBIE (3UL << 4)
#define MENVCFG_CBCFE BIT(6)
#define MENVCFG_CBZE BIT(7)
+#define MENVCFG_PMM (3ULL << 32)
#define MENVCFG_ADUE (1ULL << 61)
#define MENVCFG_PBMTE (1ULL << 62)
#define MENVCFG_STCE (1ULL << 63)
@@ -728,11 +729,13 @@ typedef enum RISCVException {
#define SENVCFG_CBIE MENVCFG_CBIE
#define SENVCFG_CBCFE MENVCFG_CBCFE
#define SENVCFG_CBZE MENVCFG_CBZE
+#define SENVCFG_PMM MENVCFG_PMM
#define HENVCFG_FIOM MENVCFG_FIOM
#define HENVCFG_CBIE MENVCFG_CBIE
#define HENVCFG_CBCFE MENVCFG_CBCFE
#define HENVCFG_CBZE MENVCFG_CBZE
+#define HENVCFG_PMM MENVCFG_PMM
#define HENVCFG_ADUE MENVCFG_ADUE
#define HENVCFG_PBMTE MENVCFG_PBMTE
#define HENVCFG_STCE MENVCFG_STCE
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index f4605fb190..201f8af6ae 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -113,6 +113,9 @@ struct RISCVCPUConfig {
bool ext_ssaia;
bool ext_sscofpmf;
bool ext_smepmp;
+ bool ext_ssnpm;
+ bool ext_smnpm;
+ bool ext_smmpm;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ea4e1ac6ef..a67ba30494 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -527,6 +527,9 @@ static RISCVException have_mseccfg(CPURISCVState *env, int csrno)
if (riscv_cpu_cfg(env)->ext_zkr) {
return RISCV_EXCP_NONE;
}
+ if (riscv_cpu_cfg(env)->ext_smmpm) {
+ return RISCV_EXCP_NONE;
+ }
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -2030,6 +2033,10 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
(cfg->ext_sstc ? MENVCFG_STCE : 0) |
(cfg->ext_svadu ? MENVCFG_ADUE : 0);
}
+ /* Update PMM field only if the value is valid according to Zjpm v0.8 */
+ if (((val & MENVCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
+ mask |= MENVCFG_PMM;
+ }
env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
return RISCV_EXCP_NONE;
@@ -2074,6 +2081,10 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
target_ulong val)
{
uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
+ /* Update PMM field only if the value is valid according to Zjpm v0.8 */
+ if (((val & SENVCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
+ mask |= SENVCFG_PMM;
+ }
RISCVException ret;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 860fe56d43..5e9c5b43ab 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -153,9 +153,8 @@ static const VMStateDescription vmstate_vector = {
static bool pointermasking_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
- CPURISCVState *env = &cpu->env;
- return riscv_has_ext(env, RVJ);
+ return cpu->cfg.ext_ssnpm || cpu->cfg.ext_smnpm || cpu->cfg.ext_smmpm;
}
static const VMStateDescription vmstate_pointermasking = {
@@ -164,6 +163,9 @@ static const VMStateDescription vmstate_pointermasking = {
.minimum_version_id = 1,
.needed = pointermasking_needed,
.fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.mseccfg, RISCVCPU),
+ VMSTATE_UINTTL(env.senvcfg, RISCVCPU),
+ VMSTATE_UINTTL(env.menvcfg, RISCVCPU),
VMSTATE_END_OF_LIST()
}
};
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 162e88a90a..893ccd58d8 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -576,6 +576,12 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
{
int i;
+ uint64_t mask = MSECCFG_MMWP | MSECCFG_MML;
+
+ /* Update PMM field only if the value is valid according to Zjpm v0.8 */
+ if (((val & MSECCFG_PMM) >> 32) != PMM_FIELD_RESERVED) {
+ mask |= MSECCFG_PMM;
+ }
trace_mseccfg_csr_write(env->mhartid, val);
@@ -591,12 +597,13 @@ void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
if (riscv_cpu_cfg(env)->ext_smepmp) {
/* Sticky bits */
- val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
- if ((val ^ env->mseccfg) & (MSECCFG_MMWP | MSECCFG_MML)) {
+ val |= (env->mseccfg & mask);
+ if ((val ^ env->mseccfg) & mask) {
tlb_flush(env_cpu(env));
}
} else {
- val &= ~(MSECCFG_MMWP | MSECCFG_MML | MSECCFG_RLB);
+ mask |= MSECCFG_RLB;
+ val &= ~(mask);
}
env->mseccfg = val;
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 9af8614cd4..b3ca51c26d 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -40,11 +40,12 @@ typedef enum {
} pmp_am_t;
typedef enum {
- MSECCFG_MML = 1 << 0,
- MSECCFG_MMWP = 1 << 1,
- MSECCFG_RLB = 1 << 2,
- MSECCFG_USEED = 1 << 8,
- MSECCFG_SSEED = 1 << 9
+ MSECCFG_MML = 1 << 0,
+ MSECCFG_MMWP = 1 << 1,
+ MSECCFG_RLB = 1 << 2,
+ MSECCFG_USEED = 1 << 8,
+ MSECCFG_SSEED = 1 << 9,
+ MSECCFG_PMM = 3UL << 32,
} mseccfg_field_t;
typedef struct {
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
2024-01-03 18:57 [PATCH v3 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Alexey Baturo
@ 2024-01-03 18:57 ` Alexey Baturo
2024-01-05 0:46 ` Deepak Gupta
2024-01-03 18:57 ` [PATCH v3 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
` (2 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: Alexey Baturo @ 2024-01-03 18:57 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/cpu.h | 4 +++
target/riscv/cpu_helper.c | 54 +++++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bd379ee653..c607a94bba 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -672,6 +672,10 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags);
+bool riscv_cpu_bare_mode(CPURISCVState *env);
+RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env);
+int riscv_pm_get_pmlen(RISCVPmPmm pmm);
+
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index a3d477d226..4c34e12ee3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -139,6 +139,60 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
*pflags = flags;
}
+RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)
+{
+ int pmm = 0;
+#ifndef CONFIG_USER_ONLY
+ int priv_mode = cpu_address_mode(env);
+ /* Get current PMM field */
+ switch (priv_mode) {
+ case PRV_M:
+ pmm = riscv_cpu_cfg(env)->ext_smmpm ?
+ get_field(env->mseccfg, MSECCFG_PMM) : PMM_FIELD_DISABLED;
+ break;
+ case PRV_S:
+ pmm = riscv_cpu_cfg(env)->ext_smnpm ?
+ get_field(env->menvcfg, MENVCFG_PMM) : PMM_FIELD_DISABLED;
+ break;
+ case PRV_U:
+ pmm = riscv_cpu_cfg(env)->ext_ssnpm ?
+ get_field(env->senvcfg, SENVCFG_PMM) : PMM_FIELD_DISABLED;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+#endif
+ return pmm;
+}
+
+bool riscv_cpu_bare_mode(CPURISCVState *env)
+{
+ int satp_mode = 0;
+#ifndef CONFIG_USER_ONLY
+ if (riscv_cpu_mxl(env) == MXL_RV32) {
+ satp_mode = get_field(env->satp, SATP32_MODE);
+ } else {
+ satp_mode = get_field(env->satp, SATP64_MODE);
+ }
+#endif
+ return (satp_mode == VM_1_10_MBARE);
+}
+
+int riscv_pm_get_pmlen(RISCVPmPmm pmm)
+{
+ switch (pmm) {
+ case PMM_FIELD_DISABLED:
+ return 0;
+ case PMM_FIELD_PMLEN7:
+ return 7;
+ case PMM_FIELD_PMLEN16:
+ return 16;
+ default:
+ g_assert_not_reached();
+ }
+ return -1;
+}
+
#ifndef CONFIG_USER_ONLY
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 4/6] target/riscv: Add pointer masking tb flags
2024-01-03 18:57 [PATCH v3 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
` (2 preceding siblings ...)
2024-01-03 18:57 ` [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
@ 2024-01-03 18:57 ` Alexey Baturo
2024-01-03 22:08 ` Richard Henderson
2024-01-03 18:57 ` [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
5 siblings, 1 reply; 20+ messages in thread
From: Alexey Baturo @ 2024-01-03 18:57 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/cpu.h | 3 +++
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 11 +++++++++++
3 files changed, 17 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c607a94bba..4df160494f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -546,6 +546,9 @@ FIELD(TB_FLAGS, ITRIGGER, 20, 1)
FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1)
FIELD(TB_FLAGS, PRIV, 22, 2)
FIELD(TB_FLAGS, AXL, 24, 2)
+/* If pointer masking should be applied and address sign extended */
+FIELD(TB_FLAGS, PM_PMM, 26, 2)
+FIELD(TB_FLAGS, PM_SIGNEXTEND, 28, 1)
#ifdef TARGET_RISCV32
#define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 4c34e12ee3..b8d8a622f3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -68,6 +68,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
RISCVCPU *cpu = env_archcpu(env);
RISCVExtStatus fs, vs;
uint32_t flags = 0;
+ bool pm_signext = !riscv_cpu_bare_mode(env);
*pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
@@ -135,6 +136,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
+ flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
*pflags = flags;
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6b4b9a671c..8ac2819fa5 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -103,6 +103,9 @@ typedef struct DisasContext {
bool vl_eq_vlmax;
CPUState *cs;
TCGv zero;
+ /* actual address width */
+ uint8_t addr_width;
+ bool addr_signed;
/* Use icount trigger for native debug */
bool itrigger;
/* FRM is known to contain a valid value. */
@@ -1176,6 +1179,14 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs;
+ if (get_xl(ctx) == MXL_RV32) {
+ ctx->addr_width = 32;
+ ctx->addr_signed = false;
+ } else {
+ int pm_pmm = FIELD_EX32(tb_flags, TB_FLAGS, PM_PMM);
+ ctx->addr_width = 64 - riscv_pm_get_pmlen(pm_pmm);
+ ctx->addr_signed = FIELD_EX32(tb_flags, TB_FLAGS, PM_SIGNEXTEND);
+ }
ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
ctx->zero = tcg_constant_tl(0);
ctx->virt_inst_excp = false;
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking
2024-01-03 18:57 [PATCH v3 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
` (3 preceding siblings ...)
2024-01-03 18:57 ` [PATCH v3 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
@ 2024-01-03 18:57 ` Alexey Baturo
2024-01-03 22:18 ` Richard Henderson
2024-01-05 1:02 ` Deepak Gupta
2024-01-03 18:57 ` [PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
5 siblings, 2 replies; 20+ messages in thread
From: Alexey Baturo @ 2024-01-03 18:57 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/translate.c | 12 ++++++++----
target/riscv/vector_helper.c | 12 ++++++++++++
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8ac2819fa5..457de381c7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -579,8 +579,10 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_addi_tl(addr, src1, imm);
- if (get_address_xl(ctx) == MXL_RV32) {
- tcg_gen_ext32u_tl(addr, addr);
+ if (ctx->addr_signed) {
+ tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
+ } else {
+ tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
}
return addr;
@@ -593,8 +595,10 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
tcg_gen_add_tl(addr, src1, offs);
- if (get_xl(ctx) == MXL_RV32) {
- tcg_gen_ext32u_tl(addr, addr);
+ if (ctx->addr_signed) {
+ tcg_gen_sextract_tl(addr, addr, 0, ctx->addr_width);
+ } else {
+ tcg_gen_extract_tl(addr, addr, 0, ctx->addr_width);
}
return addr;
}
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8e7a8e80a0..b91c21d1f4 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -94,6 +94,18 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
{
+ RISCVPmPmm pmm = riscv_pm_get_pmm(env);
+ if (pmm == PMM_FIELD_DISABLED)
+ return addr;
+ int pmlen = riscv_pm_get_pmlen(pmm);
+ bool signext = !riscv_cpu_bare_mode(env);
+ addr = addr << pmlen;
+ /* sign/zero extend masked address by N-1 bit */
+ if (signext) {
+ addr = (target_long)addr >> pmlen;
+ } else {
+ addr = addr >> pmlen;
+ }
return addr;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension
2024-01-03 18:57 [PATCH v3 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
` (4 preceding siblings ...)
2024-01-03 18:57 ` [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
@ 2024-01-03 18:57 ` Alexey Baturo
2024-01-05 5:27 ` Alistair Francis
5 siblings, 1 reply; 20+ messages in thread
From: Alexey Baturo @ 2024-01-03 18:57 UTC (permalink / raw)
Cc: baturo.alexey, richard.henderson, zhiwei_liu, palmer,
Alistair.Francis, sagark, kbastian, qemu-devel, qemu-riscv
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/cpu.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e6571ce99..13389ddc55 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,6 +153,9 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_12_0, ext_ssnpm),
+ ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_12_0, ext_smnpm),
+ ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_12_0, ext_smmpm),
ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
@@ -1337,6 +1340,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
+ /* Zjpm v0.8 extensions */
+ MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
+ MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false),
+ MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false),
+
MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v3 4/6] target/riscv: Add pointer masking tb flags
2024-01-03 18:57 ` [PATCH v3 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
@ 2024-01-03 22:08 ` Richard Henderson
0 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2024-01-03 22:08 UTC (permalink / raw)
To: Alexey Baturo
Cc: zhiwei_liu, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
On 1/4/24 05:57, Alexey Baturo wrote:
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> ---
> target/riscv/cpu.h | 3 +++
> target/riscv/cpu_helper.c | 3 +++
> target/riscv/translate.c | 11 +++++++++++
> 3 files changed, 17 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c607a94bba..4df160494f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -546,6 +546,9 @@ FIELD(TB_FLAGS, ITRIGGER, 20, 1)
> FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1)
> FIELD(TB_FLAGS, PRIV, 22, 2)
> FIELD(TB_FLAGS, AXL, 24, 2)
> +/* If pointer masking should be applied and address sign extended */
> +FIELD(TB_FLAGS, PM_PMM, 26, 2)
> +FIELD(TB_FLAGS, PM_SIGNEXTEND, 28, 1)
>
> #ifdef TARGET_RISCV32
> #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 4c34e12ee3..b8d8a622f3 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -68,6 +68,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> RISCVCPU *cpu = env_archcpu(env);
> RISCVExtStatus fs, vs;
> uint32_t flags = 0;
> + bool pm_signext = !riscv_cpu_bare_mode(env);
>
> *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
> *cs_base = 0;
> @@ -135,6 +136,8 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
> flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
> flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
> + flags = FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env));
> + flags = FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext);
You should avoid setting these fields (i.e. leave them zero) when they won't be used...
> + if (get_xl(ctx) == MXL_RV32) {
> + ctx->addr_width = 32;
> + ctx->addr_signed = false;
... like so.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking
2024-01-03 18:57 ` [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
@ 2024-01-03 22:18 ` Richard Henderson
2024-01-05 1:02 ` Deepak Gupta
1 sibling, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2024-01-03 22:18 UTC (permalink / raw)
To: Alexey Baturo
Cc: zhiwei_liu, palmer, Alistair.Francis, sagark, kbastian,
qemu-devel, qemu-riscv
On 1/4/24 05:57, Alexey Baturo wrote:
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> ---
> target/riscv/translate.c | 12 ++++++++----
> target/riscv/vector_helper.c | 12 ++++++++++++
> 2 files changed, 20 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
2024-01-03 18:57 ` [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
@ 2024-01-05 0:46 ` Deepak Gupta
2024-01-05 7:33 ` Alexey Baturo
0 siblings, 1 reply; 20+ messages in thread
From: Deepak Gupta @ 2024-01-05 0:46 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Wed, Jan 3, 2024 at 10:59 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
> +
> +bool riscv_cpu_bare_mode(CPURISCVState *env)
> +{
> + int satp_mode = 0;
> +#ifndef CONFIG_USER_ONLY
> + if (riscv_cpu_mxl(env) == MXL_RV32) {
> + satp_mode = get_field(env->satp, SATP32_MODE);
> + } else {
> + satp_mode = get_field(env->satp, SATP64_MODE);
> + }
> +#endif
> + return (satp_mode == VM_1_10_MBARE);
> +}
> +
Assume the CPU was in S or U with satp = non-bare mode but then a
transfer to M-mode happened.
In that case, even though the CPU is in M mode, the above function
will return non-bare mode and enforce
signed extension on M mode pointer masking (if enabled).
right or am I missing something here?
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking
2024-01-03 18:57 ` [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
2024-01-03 22:18 ` Richard Henderson
@ 2024-01-05 1:02 ` Deepak Gupta
2024-01-05 7:29 ` Alexey Baturo
1 sibling, 1 reply; 20+ messages in thread
From: Deepak Gupta @ 2024-01-05 1:02 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -94,6 +94,18 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
>
> static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
> {
> + RISCVPmPmm pmm = riscv_pm_get_pmm(env);
> + if (pmm == PMM_FIELD_DISABLED)
> + return addr;
> + int pmlen = riscv_pm_get_pmlen(pmm);
> + bool signext = !riscv_cpu_bare_mode(env);
> + addr = addr << pmlen;
> + /* sign/zero extend masked address by N-1 bit */
> + if (signext) {
> + addr = (target_long)addr >> pmlen;
These look like right shift operations and not sign extensions of N-1 bit
> + } else {
> + addr = addr >> pmlen;
Same here.
> + }
> return addr;
> }
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code.
2024-01-03 18:57 ` [PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
@ 2024-01-05 5:04 ` Alistair Francis
2024-01-05 7:23 ` Alexey Baturo
0 siblings, 1 reply; 20+ messages in thread
From: Alistair Francis @ 2024-01-05 5:04 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Thu, Jan 4, 2024 at 6:33 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Zjpm v0.8 is almost frozen and it's much simplier compared to the existing one:
> The newer version doesn't allow to specify custom mask or base for masking.
> Instead it allows only certain options for masking top bits.
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> ---
> target/riscv/cpu.c | 10 --
> target/riscv/cpu.h | 32 +---
> target/riscv/cpu_bits.h | 87 ----------
> target/riscv/cpu_helper.c | 52 ------
> target/riscv/csr.c | 326 -----------------------------------
> target/riscv/machine.c | 9 -
> target/riscv/translate.c | 27 +--
> target/riscv/vector_helper.c | 2 +-
> 8 files changed, 10 insertions(+), 535 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 83c7c0cf07..1e6571ce99 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -710,13 +710,6 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> CSR_MSCRATCH,
> CSR_SSCRATCH,
> CSR_SATP,
> - CSR_MMTE,
> - CSR_UPMBASE,
> - CSR_UPMMASK,
> - CSR_SPMBASE,
> - CSR_SPMMASK,
> - CSR_MPMBASE,
> - CSR_MPMMASK,
> };
>
> for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
> @@ -891,8 +884,6 @@ static void riscv_cpu_reset_hold(Object *obj)
> }
> i++;
> }
> - /* mmte is supposed to have pm.current hardwired to 1 */
> - env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
>
> /*
> * Clear mseccfg and unlock all the PMP entries upon reset.
> @@ -906,7 +897,6 @@ static void riscv_cpu_reset_hold(Object *obj)
> pmp_unlock_entries(env);
> #endif
> env->xl = riscv_cpu_mxl(env);
> - riscv_cpu_update_mask(env);
> cs->exception_index = RISCV_EXCP_NONE;
> env->load_res = -1;
> set_default_nan_mode(1, &env->fp_status);
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d74b361be6..73f7004936 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -374,18 +374,7 @@ struct CPUArchState {
> /* True if in debugger mode. */
> bool debugger;
>
> - /*
> - * CSRs for PointerMasking extension
> - */
> - target_ulong mmte;
> - target_ulong mpmmask;
> - target_ulong mpmbase;
> - target_ulong spmmask;
> - target_ulong spmbase;
> - target_ulong upmmask;
> - target_ulong upmbase;
> -
> - /* CSRs for execution environment configuration */
> + /* CSRs for execution enviornment configuration */
> uint64_t menvcfg;
> uint64_t mstateen[SMSTATEEN_MAX_COUNT];
> uint64_t hstateen[SMSTATEEN_MAX_COUNT];
> @@ -393,8 +382,6 @@ struct CPUArchState {
> target_ulong senvcfg;
> uint64_t henvcfg;
> #endif
> - target_ulong cur_pmmask;
> - target_ulong cur_pmbase;
>
> /* Fields from here on are preserved across CPU reset. */
> QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
> @@ -543,17 +530,14 @@ FIELD(TB_FLAGS, VILL, 14, 1)
> FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
> /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */
> FIELD(TB_FLAGS, XL, 16, 2)
> -/* If PointerMasking should be applied */
> -FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
> -FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
> -FIELD(TB_FLAGS, VTA, 20, 1)
> -FIELD(TB_FLAGS, VMA, 21, 1)
> +FIELD(TB_FLAGS, VTA, 18, 1)
> +FIELD(TB_FLAGS, VMA, 19, 1)
> /* Native debug itrigger */
> -FIELD(TB_FLAGS, ITRIGGER, 22, 1)
> +FIELD(TB_FLAGS, ITRIGGER, 20, 1)
> /* Virtual mode enabled */
> -FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
> -FIELD(TB_FLAGS, PRIV, 24, 2)
> -FIELD(TB_FLAGS, AXL, 26, 2)
> +FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1)
> +FIELD(TB_FLAGS, PRIV, 22, 2)
> +FIELD(TB_FLAGS, AXL, 24, 2)
>
> #ifdef TARGET_RISCV32
> #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
> @@ -680,8 +664,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
> void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> uint64_t *cs_base, uint32_t *pflags);
>
> -void riscv_cpu_update_mask(CPURISCVState *env);
> -
> RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> target_ulong *ret_value,
> target_ulong new_value, target_ulong write_mask);
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index ebd7917d49..1c92458a01 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -491,37 +491,6 @@
> #define CSR_MHPMCOUNTER30H 0xb9e
> #define CSR_MHPMCOUNTER31H 0xb9f
>
> -/*
> - * User PointerMasking registers
> - * NB: actual CSR numbers might be changed in future
> - */
> -#define CSR_UMTE 0x4c0
> -#define CSR_UPMMASK 0x4c1
> -#define CSR_UPMBASE 0x4c2
> -
> -/*
> - * Machine PointerMasking registers
> - * NB: actual CSR numbers might be changed in future
> - */
> -#define CSR_MMTE 0x3c0
> -#define CSR_MPMMASK 0x3c1
> -#define CSR_MPMBASE 0x3c2
> -
> -/*
> - * Supervisor PointerMaster registers
> - * NB: actual CSR numbers might be changed in future
> - */
> -#define CSR_SMTE 0x1c0
> -#define CSR_SPMMASK 0x1c1
> -#define CSR_SPMBASE 0x1c2
> -
> -/*
> - * Hypervisor PointerMaster registers
> - * NB: actual CSR numbers might be changed in future
> - */
> -#define CSR_VSMTE 0x2c0
> -#define CSR_VSPMMASK 0x2c1
> -#define CSR_VSPMBASE 0x2c2
> #define CSR_SCOUNTOVF 0xda0
>
> /* Crypto Extension */
> @@ -741,11 +710,6 @@ typedef enum RISCVException {
> #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
> #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
>
> -/* General PointerMasking CSR bits */
> -#define PM_ENABLE 0x00000001ULL
> -#define PM_CURRENT 0x00000002ULL
> -#define PM_INSN 0x00000004ULL
> -
> /* Execution environment configuration bits */
> #define MENVCFG_FIOM BIT(0)
> #define MENVCFG_CBIE (3UL << 4)
> @@ -778,57 +742,6 @@ typedef enum RISCVException {
> #define HENVCFGH_PBMTE MENVCFGH_PBMTE
> #define HENVCFGH_STCE MENVCFGH_STCE
>
> -/* Offsets for every pair of control bits per each priv level */
> -#define XS_OFFSET 0ULL
> -#define U_OFFSET 2ULL
> -#define S_OFFSET 5ULL
> -#define M_OFFSET 8ULL
> -
> -#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
> -#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
> -#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
> -#define U_PM_INSN (PM_INSN << U_OFFSET)
> -#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
> -#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
> -#define S_PM_INSN (PM_INSN << S_OFFSET)
> -#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
> -#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
> -#define M_PM_INSN (PM_INSN << M_OFFSET)
> -
> -/* mmte CSR bits */
> -#define MMTE_PM_XS_BITS PM_XS_BITS
> -#define MMTE_U_PM_ENABLE U_PM_ENABLE
> -#define MMTE_U_PM_CURRENT U_PM_CURRENT
> -#define MMTE_U_PM_INSN U_PM_INSN
> -#define MMTE_S_PM_ENABLE S_PM_ENABLE
> -#define MMTE_S_PM_CURRENT S_PM_CURRENT
> -#define MMTE_S_PM_INSN S_PM_INSN
> -#define MMTE_M_PM_ENABLE M_PM_ENABLE
> -#define MMTE_M_PM_CURRENT M_PM_CURRENT
> -#define MMTE_M_PM_INSN M_PM_INSN
> -#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | MMTE_U_PM_INSN | \
> - MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | MMTE_S_PM_INSN | \
> - MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT | MMTE_M_PM_INSN | \
> - MMTE_PM_XS_BITS)
> -
> -/* (v)smte CSR bits */
> -#define SMTE_PM_XS_BITS PM_XS_BITS
> -#define SMTE_U_PM_ENABLE U_PM_ENABLE
> -#define SMTE_U_PM_CURRENT U_PM_CURRENT
> -#define SMTE_U_PM_INSN U_PM_INSN
> -#define SMTE_S_PM_ENABLE S_PM_ENABLE
> -#define SMTE_S_PM_CURRENT S_PM_CURRENT
> -#define SMTE_S_PM_INSN S_PM_INSN
> -#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | SMTE_U_PM_INSN | \
> - SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | SMTE_S_PM_INSN | \
> - SMTE_PM_XS_BITS)
> -
> -/* umte CSR bits */
> -#define UMTE_U_PM_ENABLE U_PM_ENABLE
> -#define UMTE_U_PM_CURRENT U_PM_CURRENT
> -#define UMTE_U_PM_INSN U_PM_INSN
> -#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | UMTE_U_PM_INSN)
> -
> /* MISELECT, SISELECT, and VSISELECT bits (AIA) */
> #define ISELECT_IPRIO0 0x30
> #define ISELECT_IPRIO15 0x3f
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index e7e23b34f4..a3d477d226 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -135,61 +135,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
> flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
> flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
> - if (env->cur_pmmask != 0) {
> - flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
> - }
> - if (env->cur_pmbase != 0) {
> - flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
> - }
>
> *pflags = flags;
> }
>
> -void riscv_cpu_update_mask(CPURISCVState *env)
> -{
> - target_ulong mask = 0, base = 0;
> - RISCVMXL xl = env->xl;
> - /*
> - * TODO: Current RVJ spec does not specify
> - * how the extension interacts with XLEN.
> - */
> -#ifndef CONFIG_USER_ONLY
> - int mode = cpu_address_mode(env);
> - xl = cpu_get_xl(env, mode);
> - if (riscv_has_ext(env, RVJ)) {
> - switch (mode) {
> - case PRV_M:
> - if (env->mmte & M_PM_ENABLE) {
> - mask = env->mpmmask;
> - base = env->mpmbase;
> - }
> - break;
> - case PRV_S:
> - if (env->mmte & S_PM_ENABLE) {
> - mask = env->spmmask;
> - base = env->spmbase;
> - }
> - break;
> - case PRV_U:
> - if (env->mmte & U_PM_ENABLE) {
> - mask = env->upmmask;
> - base = env->upmbase;
> - }
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - }
> -#endif
> - if (xl == MXL_RV32) {
> - env->cur_pmmask = mask & UINT32_MAX;
> - env->cur_pmbase = base & UINT32_MAX;
> - } else {
> - env->cur_pmmask = mask;
> - env->cur_pmbase = base;
> - }
> -}
> -
> #ifndef CONFIG_USER_ONLY
>
> /*
> @@ -721,7 +670,6 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
> /* tlb_flush is unnecessary as mode is contained in mmu_idx */
> env->priv = newpriv;
> env->xl = cpu_recompute_xl(env);
> - riscv_cpu_update_mask(env);
>
> /*
> * Clear the load reservation - otherwise a reservation placed in one
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index fde7ce1a53..ea4e1ac6ef 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -483,16 +483,6 @@ static RISCVException hgatp(CPURISCVState *env, int csrno)
> return hmode(env, csrno);
> }
>
> -/* Checks if PointerMasking registers could be accessed */
> -static RISCVException pointer_masking(CPURISCVState *env, int csrno)
> -{
> - /* Check if j-ext is present */
> - if (riscv_has_ext(env, RVJ)) {
> - return RISCV_EXCP_NONE;
> - }
> - return RISCV_EXCP_ILLEGAL_INST;
> -}
> -
> static int aia_hmode(CPURISCVState *env, int csrno)
> {
> if (!riscv_cpu_cfg(env)->ext_ssaia) {
> @@ -1355,7 +1345,6 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> env->xl = cpu_recompute_xl(env);
> }
>
> - riscv_cpu_update_mask(env);
> return RISCV_EXCP_NONE;
> }
>
> @@ -3900,302 +3889,6 @@ static RISCVException read_tinfo(CPURISCVState *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -/*
> - * Functions to access Pointer Masking feature registers
> - * We have to check if current priv lvl could modify
> - * csr in given mode
> - */
> -static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
> -{
> - int csr_priv = get_field(csrno, 0x300);
> - int pm_current;
> -
> - if (env->debugger) {
> - return false;
> - }
> - /*
> - * If priv lvls differ that means we're accessing csr from higher priv lvl,
> - * so allow the access
> - */
> - if (env->priv != csr_priv) {
> - return false;
> - }
> - switch (env->priv) {
> - case PRV_M:
> - pm_current = get_field(env->mmte, M_PM_CURRENT);
> - break;
> - case PRV_S:
> - pm_current = get_field(env->mmte, S_PM_CURRENT);
> - break;
> - case PRV_U:
> - pm_current = get_field(env->mmte, U_PM_CURRENT);
> - break;
> - default:
> - g_assert_not_reached();
> - }
> - /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
> - return !pm_current;
> -}
> -
> -static RISCVException read_mmte(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->mmte & MMTE_MASK;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_mmte(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> - target_ulong wpri_val = val & MMTE_MASK;
> -
> - if (val != wpri_val) {
> - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
> - TARGET_FMT_lx "\n", "MMTE: WPRI violation written 0x",
> - val, "vs expected 0x", wpri_val);
> - }
> - /* for machine mode pm.current is hardwired to 1 */
> - wpri_val |= MMTE_M_PM_CURRENT;
> -
> - /* hardwiring pm.instruction bit to 0, since it's not supported yet */
> - wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
> - env->mmte = wpri_val | EXT_STATUS_DIRTY;
> - riscv_cpu_update_mask(env);
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_smte(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->mmte & SMTE_MASK;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_smte(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - target_ulong wpri_val = val & SMTE_MASK;
> -
> - if (val != wpri_val) {
> - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
> - TARGET_FMT_lx "\n", "SMTE: WPRI violation written 0x",
> - val, "vs expected 0x", wpri_val);
> - }
> -
> - /* if pm.current==0 we can't modify current PM CSRs */
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> -
> - wpri_val |= (env->mmte & ~SMTE_MASK);
> - write_mmte(env, csrno, wpri_val);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_umte(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->mmte & UMTE_MASK;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_umte(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - target_ulong wpri_val = val & UMTE_MASK;
> -
> - if (val != wpri_val) {
> - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
> - TARGET_FMT_lx "\n", "UMTE: WPRI violation written 0x",
> - val, "vs expected 0x", wpri_val);
> - }
> -
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> -
> - wpri_val |= (env->mmte & ~UMTE_MASK);
> - write_mmte(env, csrno, wpri_val);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->mpmmask;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - env->mpmmask = val;
> - if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
> - env->cur_pmmask = val;
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_spmmask(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->spmmask;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_spmmask(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - /* if pm.current==0 we can't modify current PM CSRs */
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> - env->spmmask = val;
> - if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
> - env->cur_pmmask = val;
> - if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
> - env->cur_pmmask &= UINT32_MAX;
> - }
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_upmmask(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->upmmask;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_upmmask(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - /* if pm.current==0 we can't modify current PM CSRs */
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> - env->upmmask = val;
> - if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
> - env->cur_pmmask = val;
> - if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
> - env->cur_pmmask &= UINT32_MAX;
> - }
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->mpmbase;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - env->mpmbase = val;
> - if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
> - env->cur_pmbase = val;
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_spmbase(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->spmbase;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_spmbase(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - /* if pm.current==0 we can't modify current PM CSRs */
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> - env->spmbase = val;
> - if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
> - env->cur_pmbase = val;
> - if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
> - env->cur_pmbase &= UINT32_MAX;
> - }
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException read_upmbase(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - *val = env->upmbase;
> - return RISCV_EXCP_NONE;
> -}
> -
> -static RISCVException write_upmbase(CPURISCVState *env, int csrno,
> - target_ulong val)
> -{
> - uint64_t mstatus;
> -
> - /* if pm.current==0 we can't modify current PM CSRs */
> - if (check_pm_current_disabled(env, csrno)) {
> - return RISCV_EXCP_NONE;
> - }
> - env->upmbase = val;
> - if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
> - env->cur_pmbase = val;
> - if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
> - env->cur_pmbase &= UINT32_MAX;
> - }
> - }
> - env->mmte |= EXT_STATUS_DIRTY;
> -
> - /* Set XS and SD bits, since PM CSRs are dirty */
> - mstatus = env->mstatus | MSTATUS_XS;
> - write_mstatus(env, csrno, mstatus);
> - return RISCV_EXCP_NONE;
> -}
> -
> #endif
>
> /* Crypto Extension */
> @@ -4800,25 +4493,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
> [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore },
>
> - /* User Pointer Masking */
> - [CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
> - [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask,
> - write_upmmask },
> - [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase,
> - write_upmbase },
> - /* Machine Pointer Masking */
> - [CSR_MMTE] = { "mmte", pointer_masking, read_mmte, write_mmte },
> - [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask,
> - write_mpmmask },
> - [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase,
> - write_mpmbase },
> - /* Supervisor Pointer Masking */
> - [CSR_SMTE] = { "smte", pointer_masking, read_smte, write_smte },
> - [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask,
> - write_spmmask },
> - [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase,
> - write_spmbase },
> -
> /* Performance Counters */
> [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter },
> [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter },
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index fdde243e04..860fe56d43 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -164,14 +164,6 @@ static const VMStateDescription vmstate_pointermasking = {
> .minimum_version_id = 1,
The version_id and minimum_version_id should be bumped here
Alistair
> .needed = pointermasking_needed,
> .fields = (VMStateField[]) {
> - VMSTATE_UINTTL(env.mmte, RISCVCPU),
> - VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
> - VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
> - VMSTATE_UINTTL(env.spmmask, RISCVCPU),
> - VMSTATE_UINTTL(env.spmbase, RISCVCPU),
> - VMSTATE_UINTTL(env.upmmask, RISCVCPU),
> - VMSTATE_UINTTL(env.upmbase, RISCVCPU),
> -
> VMSTATE_END_OF_LIST()
> }
> };
> @@ -267,7 +259,6 @@ static int riscv_cpu_post_load(void *opaque, int version_id)
> CPURISCVState *env = &cpu->env;
>
> env->xl = cpu_recompute_xl(env);
> - riscv_cpu_update_mask(env);
> return 0;
> }
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index f0be79bb16..6b4b9a671c 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -42,9 +42,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
> static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
> static TCGv load_res;
> static TCGv load_val;
> -/* globals for PM CSRs */
> -static TCGv pm_mask;
> -static TCGv pm_base;
>
> /*
> * If an operation is being performed on less than TARGET_LONG_BITS,
> @@ -106,9 +103,6 @@ typedef struct DisasContext {
> bool vl_eq_vlmax;
> CPUState *cs;
> TCGv zero;
> - /* PointerMasking extension */
> - bool pm_mask_enabled;
> - bool pm_base_enabled;
> /* Use icount trigger for native debug */
> bool itrigger;
> /* FRM is known to contain a valid value. */
> @@ -582,14 +576,9 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
> TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>
> tcg_gen_addi_tl(addr, src1, imm);
> - if (ctx->pm_mask_enabled) {
> - tcg_gen_andc_tl(addr, addr, pm_mask);
> - } else if (get_address_xl(ctx) == MXL_RV32) {
> + if (get_address_xl(ctx) == MXL_RV32) {
> tcg_gen_ext32u_tl(addr, addr);
> }
> - if (ctx->pm_base_enabled) {
> - tcg_gen_or_tl(addr, addr, pm_base);
> - }
>
> return addr;
> }
> @@ -601,14 +590,9 @@ static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
> TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
>
> tcg_gen_add_tl(addr, src1, offs);
> - if (ctx->pm_mask_enabled) {
> - tcg_gen_andc_tl(addr, addr, pm_mask);
> - } else if (get_xl(ctx) == MXL_RV32) {
> + if (get_xl(ctx) == MXL_RV32) {
> tcg_gen_ext32u_tl(addr, addr);
> }
> - if (ctx->pm_base_enabled) {
> - tcg_gen_or_tl(addr, addr, pm_base);
> - }
> return addr;
> }
>
> @@ -1192,8 +1176,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
> ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
> ctx->cs = cs;
> - ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
> - ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
> ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
> ctx->zero = tcg_constant_tl(0);
> ctx->virt_inst_excp = false;
> @@ -1325,9 +1307,4 @@ void riscv_translate_init(void)
> "load_res");
> load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
> "load_val");
> - /* Assign PM CSRs to tcg globals */
> - pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask),
> - "pmmask");
> - pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase),
> - "pmbase");
> }
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index c1c3a4d1ea..8e7a8e80a0 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -94,7 +94,7 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz)
>
> static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr)
> {
> - return (addr & ~env->cur_pmmask) | env->cur_pmbase;
> + return addr;
> }
>
> /*
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension
2024-01-03 18:57 ` [PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
@ 2024-01-05 5:27 ` Alistair Francis
2024-01-05 7:23 ` Alexey Baturo
0 siblings, 1 reply; 20+ messages in thread
From: Alistair Francis @ 2024-01-05 5:27 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Thu, Jan 4, 2024 at 4:58 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> ---
> target/riscv/cpu.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1e6571ce99..13389ddc55 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -153,6 +153,9 @@ const RISCVIsaExtData isa_edata_arr[] = {
> ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> + ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_12_0, ext_ssnpm),
> + ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_12_0, ext_smnpm),
> + ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_12_0, ext_smmpm),
> ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
> ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
> @@ -1337,6 +1340,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>
> MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
>
> + /* Zjpm v0.8 extensions */
> + MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
> + MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false),
> + MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false),
What happens to the existing J property?
Alistair
> +
> MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
> MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
> MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension
2024-01-05 5:27 ` Alistair Francis
@ 2024-01-05 7:23 ` Alexey Baturo
2024-01-08 0:33 ` Alistair Francis
0 siblings, 1 reply; 20+ messages in thread
From: Alexey Baturo @ 2024-01-05 7:23 UTC (permalink / raw)
To: Alistair Francis
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
[-- Attachment #1: Type: text/plain, Size: 2099 bytes --]
I might be wrong here, but right now J in MISA is unused.
I think the J-letter extension is still a thing, but current extensions
like Zjpm and Zjid follow the Z ext scheme.
Do you think it should be removed?
пт, 5 янв. 2024 г. в 08:28, Alistair Francis <alistair23@gmail.com>:
> On Thu, Jan 4, 2024 at 4:58 AM Alexey Baturo <baturo.alexey@gmail.com>
> wrote:
> >
> > From: Alexey Baturo <baturo.alexey@gmail.com>
> >
> > Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> > ---
> > target/riscv/cpu.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 1e6571ce99..13389ddc55 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -153,6 +153,9 @@ const RISCVIsaExtData isa_edata_arr[] = {
> > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
> > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
> > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
> > + ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_12_0, ext_ssnpm),
> > + ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_12_0, ext_smnpm),
> > + ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_12_0, ext_smmpm),
> > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
> > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
> > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
> > @@ -1337,6 +1340,11 @@ const RISCVCPUMultiExtConfig
> riscv_cpu_extensions[] = {
> >
> > MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
> >
> > + /* Zjpm v0.8 extensions */
> > + MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
> > + MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false),
> > + MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false),
>
> What happens to the existing J property?
>
>
> Alistair
>
> > +
> > MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
> > MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
> > MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
> > --
> > 2.34.1
> >
> >
>
[-- Attachment #2: Type: text/html, Size: 2925 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code.
2024-01-05 5:04 ` Alistair Francis
@ 2024-01-05 7:23 ` Alexey Baturo
0 siblings, 0 replies; 20+ messages in thread
From: Alexey Baturo @ 2024-01-05 7:23 UTC (permalink / raw)
To: Alistair Francis
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
[-- Attachment #1: Type: text/plain, Size: 30343 bytes --]
Sure, I would do it in the next updated series.
пт, 5 янв. 2024 г. в 08:04, Alistair Francis <alistair23@gmail.com>:
> On Thu, Jan 4, 2024 at 6:33 AM Alexey Baturo <baturo.alexey@gmail.com>
> wrote:
> >
> > From: Alexey Baturo <baturo.alexey@gmail.com>
> >
> > Zjpm v0.8 is almost frozen and it's much simplier compared to the
> existing one:
> > The newer version doesn't allow to specify custom mask or base for
> masking.
> > Instead it allows only certain options for masking top bits.
> >
> > Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
> > ---
> > target/riscv/cpu.c | 10 --
> > target/riscv/cpu.h | 32 +---
> > target/riscv/cpu_bits.h | 87 ----------
> > target/riscv/cpu_helper.c | 52 ------
> > target/riscv/csr.c | 326 -----------------------------------
> > target/riscv/machine.c | 9 -
> > target/riscv/translate.c | 27 +--
> > target/riscv/vector_helper.c | 2 +-
> > 8 files changed, 10 insertions(+), 535 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 83c7c0cf07..1e6571ce99 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -710,13 +710,6 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE
> *f, int flags)
> > CSR_MSCRATCH,
> > CSR_SSCRATCH,
> > CSR_SATP,
> > - CSR_MMTE,
> > - CSR_UPMBASE,
> > - CSR_UPMMASK,
> > - CSR_SPMBASE,
> > - CSR_SPMMASK,
> > - CSR_MPMBASE,
> > - CSR_MPMMASK,
> > };
> >
> > for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
> > @@ -891,8 +884,6 @@ static void riscv_cpu_reset_hold(Object *obj)
> > }
> > i++;
> > }
> > - /* mmte is supposed to have pm.current hardwired to 1 */
> > - env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
> >
> > /*
> > * Clear mseccfg and unlock all the PMP entries upon reset.
> > @@ -906,7 +897,6 @@ static void riscv_cpu_reset_hold(Object *obj)
> > pmp_unlock_entries(env);
> > #endif
> > env->xl = riscv_cpu_mxl(env);
> > - riscv_cpu_update_mask(env);
> > cs->exception_index = RISCV_EXCP_NONE;
> > env->load_res = -1;
> > set_default_nan_mode(1, &env->fp_status);
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index d74b361be6..73f7004936 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -374,18 +374,7 @@ struct CPUArchState {
> > /* True if in debugger mode. */
> > bool debugger;
> >
> > - /*
> > - * CSRs for PointerMasking extension
> > - */
> > - target_ulong mmte;
> > - target_ulong mpmmask;
> > - target_ulong mpmbase;
> > - target_ulong spmmask;
> > - target_ulong spmbase;
> > - target_ulong upmmask;
> > - target_ulong upmbase;
> > -
> > - /* CSRs for execution environment configuration */
> > + /* CSRs for execution enviornment configuration */
> > uint64_t menvcfg;
> > uint64_t mstateen[SMSTATEEN_MAX_COUNT];
> > uint64_t hstateen[SMSTATEEN_MAX_COUNT];
> > @@ -393,8 +382,6 @@ struct CPUArchState {
> > target_ulong senvcfg;
> > uint64_t henvcfg;
> > #endif
> > - target_ulong cur_pmmask;
> > - target_ulong cur_pmbase;
> >
> > /* Fields from here on are preserved across CPU reset. */
> > QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
> > @@ -543,17 +530,14 @@ FIELD(TB_FLAGS, VILL, 14, 1)
> > FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1)
> > /* The combination of MXL/SXL/UXL that applies to the current cpu mode.
> */
> > FIELD(TB_FLAGS, XL, 16, 2)
> > -/* If PointerMasking should be applied */
> > -FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1)
> > -FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1)
> > -FIELD(TB_FLAGS, VTA, 20, 1)
> > -FIELD(TB_FLAGS, VMA, 21, 1)
> > +FIELD(TB_FLAGS, VTA, 18, 1)
> > +FIELD(TB_FLAGS, VMA, 19, 1)
> > /* Native debug itrigger */
> > -FIELD(TB_FLAGS, ITRIGGER, 22, 1)
> > +FIELD(TB_FLAGS, ITRIGGER, 20, 1)
> > /* Virtual mode enabled */
> > -FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1)
> > -FIELD(TB_FLAGS, PRIV, 24, 2)
> > -FIELD(TB_FLAGS, AXL, 26, 2)
> > +FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1)
> > +FIELD(TB_FLAGS, PRIV, 22, 2)
> > +FIELD(TB_FLAGS, AXL, 24, 2)
> >
> > #ifdef TARGET_RISCV32
> > #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32)
> > @@ -680,8 +664,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu,
> target_ulong vtype)
> > void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
> > uint64_t *cs_base, uint32_t *pflags);
> >
> > -void riscv_cpu_update_mask(CPURISCVState *env);
> > -
> > RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> > target_ulong *ret_value,
> > target_ulong new_value, target_ulong
> write_mask);
> > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> > index ebd7917d49..1c92458a01 100644
> > --- a/target/riscv/cpu_bits.h
> > +++ b/target/riscv/cpu_bits.h
> > @@ -491,37 +491,6 @@
> > #define CSR_MHPMCOUNTER30H 0xb9e
> > #define CSR_MHPMCOUNTER31H 0xb9f
> >
> > -/*
> > - * User PointerMasking registers
> > - * NB: actual CSR numbers might be changed in future
> > - */
> > -#define CSR_UMTE 0x4c0
> > -#define CSR_UPMMASK 0x4c1
> > -#define CSR_UPMBASE 0x4c2
> > -
> > -/*
> > - * Machine PointerMasking registers
> > - * NB: actual CSR numbers might be changed in future
> > - */
> > -#define CSR_MMTE 0x3c0
> > -#define CSR_MPMMASK 0x3c1
> > -#define CSR_MPMBASE 0x3c2
> > -
> > -/*
> > - * Supervisor PointerMaster registers
> > - * NB: actual CSR numbers might be changed in future
> > - */
> > -#define CSR_SMTE 0x1c0
> > -#define CSR_SPMMASK 0x1c1
> > -#define CSR_SPMBASE 0x1c2
> > -
> > -/*
> > - * Hypervisor PointerMaster registers
> > - * NB: actual CSR numbers might be changed in future
> > - */
> > -#define CSR_VSMTE 0x2c0
> > -#define CSR_VSPMMASK 0x2c1
> > -#define CSR_VSPMBASE 0x2c2
> > #define CSR_SCOUNTOVF 0xda0
> >
> > /* Crypto Extension */
> > @@ -741,11 +710,6 @@ typedef enum RISCVException {
> > #define VS_MODE_INTERRUPTS ((uint64_t)(MIP_VSSIP | MIP_VSTIP |
> MIP_VSEIP))
> > #define HS_MODE_INTERRUPTS ((uint64_t)(MIP_SGEIP | VS_MODE_INTERRUPTS))
> >
> > -/* General PointerMasking CSR bits */
> > -#define PM_ENABLE 0x00000001ULL
> > -#define PM_CURRENT 0x00000002ULL
> > -#define PM_INSN 0x00000004ULL
> > -
> > /* Execution environment configuration bits */
> > #define MENVCFG_FIOM BIT(0)
> > #define MENVCFG_CBIE (3UL << 4)
> > @@ -778,57 +742,6 @@ typedef enum RISCVException {
> > #define HENVCFGH_PBMTE MENVCFGH_PBMTE
> > #define HENVCFGH_STCE MENVCFGH_STCE
> >
> > -/* Offsets for every pair of control bits per each priv level */
> > -#define XS_OFFSET 0ULL
> > -#define U_OFFSET 2ULL
> > -#define S_OFFSET 5ULL
> > -#define M_OFFSET 8ULL
> > -
> > -#define PM_XS_BITS (EXT_STATUS_MASK << XS_OFFSET)
> > -#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
> > -#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
> > -#define U_PM_INSN (PM_INSN << U_OFFSET)
> > -#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
> > -#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
> > -#define S_PM_INSN (PM_INSN << S_OFFSET)
> > -#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
> > -#define M_PM_CURRENT (PM_CURRENT << M_OFFSET)
> > -#define M_PM_INSN (PM_INSN << M_OFFSET)
> > -
> > -/* mmte CSR bits */
> > -#define MMTE_PM_XS_BITS PM_XS_BITS
> > -#define MMTE_U_PM_ENABLE U_PM_ENABLE
> > -#define MMTE_U_PM_CURRENT U_PM_CURRENT
> > -#define MMTE_U_PM_INSN U_PM_INSN
> > -#define MMTE_S_PM_ENABLE S_PM_ENABLE
> > -#define MMTE_S_PM_CURRENT S_PM_CURRENT
> > -#define MMTE_S_PM_INSN S_PM_INSN
> > -#define MMTE_M_PM_ENABLE M_PM_ENABLE
> > -#define MMTE_M_PM_CURRENT M_PM_CURRENT
> > -#define MMTE_M_PM_INSN M_PM_INSN
> > -#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT |
> MMTE_U_PM_INSN | \
> > - MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT |
> MMTE_S_PM_INSN | \
> > - MMTE_M_PM_ENABLE | MMTE_M_PM_CURRENT |
> MMTE_M_PM_INSN | \
> > - MMTE_PM_XS_BITS)
> > -
> > -/* (v)smte CSR bits */
> > -#define SMTE_PM_XS_BITS PM_XS_BITS
> > -#define SMTE_U_PM_ENABLE U_PM_ENABLE
> > -#define SMTE_U_PM_CURRENT U_PM_CURRENT
> > -#define SMTE_U_PM_INSN U_PM_INSN
> > -#define SMTE_S_PM_ENABLE S_PM_ENABLE
> > -#define SMTE_S_PM_CURRENT S_PM_CURRENT
> > -#define SMTE_S_PM_INSN S_PM_INSN
> > -#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT |
> SMTE_U_PM_INSN | \
> > - SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT |
> SMTE_S_PM_INSN | \
> > - SMTE_PM_XS_BITS)
> > -
> > -/* umte CSR bits */
> > -#define UMTE_U_PM_ENABLE U_PM_ENABLE
> > -#define UMTE_U_PM_CURRENT U_PM_CURRENT
> > -#define UMTE_U_PM_INSN U_PM_INSN
> > -#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT |
> UMTE_U_PM_INSN)
> > -
> > /* MISELECT, SISELECT, and VSISELECT bits (AIA) */
> > #define ISELECT_IPRIO0 0x30
> > #define ISELECT_IPRIO15 0x3f
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index e7e23b34f4..a3d477d226 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -135,61 +135,10 @@ void cpu_get_tb_cpu_state(CPURISCVState *env,
> vaddr *pc,
> > flags = FIELD_DP32(flags, TB_FLAGS, VS, vs);
> > flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
> > flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env));
> > - if (env->cur_pmmask != 0) {
> > - flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1);
> > - }
> > - if (env->cur_pmbase != 0) {
> > - flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1);
> > - }
> >
> > *pflags = flags;
> > }
> >
> > -void riscv_cpu_update_mask(CPURISCVState *env)
> > -{
> > - target_ulong mask = 0, base = 0;
> > - RISCVMXL xl = env->xl;
> > - /*
> > - * TODO: Current RVJ spec does not specify
> > - * how the extension interacts with XLEN.
> > - */
> > -#ifndef CONFIG_USER_ONLY
> > - int mode = cpu_address_mode(env);
> > - xl = cpu_get_xl(env, mode);
> > - if (riscv_has_ext(env, RVJ)) {
> > - switch (mode) {
> > - case PRV_M:
> > - if (env->mmte & M_PM_ENABLE) {
> > - mask = env->mpmmask;
> > - base = env->mpmbase;
> > - }
> > - break;
> > - case PRV_S:
> > - if (env->mmte & S_PM_ENABLE) {
> > - mask = env->spmmask;
> > - base = env->spmbase;
> > - }
> > - break;
> > - case PRV_U:
> > - if (env->mmte & U_PM_ENABLE) {
> > - mask = env->upmmask;
> > - base = env->upmbase;
> > - }
> > - break;
> > - default:
> > - g_assert_not_reached();
> > - }
> > - }
> > -#endif
> > - if (xl == MXL_RV32) {
> > - env->cur_pmmask = mask & UINT32_MAX;
> > - env->cur_pmbase = base & UINT32_MAX;
> > - } else {
> > - env->cur_pmmask = mask;
> > - env->cur_pmbase = base;
> > - }
> > -}
> > -
> > #ifndef CONFIG_USER_ONLY
> >
> > /*
> > @@ -721,7 +670,6 @@ void riscv_cpu_set_mode(CPURISCVState *env,
> target_ulong newpriv)
> > /* tlb_flush is unnecessary as mode is contained in mmu_idx */
> > env->priv = newpriv;
> > env->xl = cpu_recompute_xl(env);
> > - riscv_cpu_update_mask(env);
> >
> > /*
> > * Clear the load reservation - otherwise a reservation placed in
> one
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index fde7ce1a53..ea4e1ac6ef 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -483,16 +483,6 @@ static RISCVException hgatp(CPURISCVState *env, int
> csrno)
> > return hmode(env, csrno);
> > }
> >
> > -/* Checks if PointerMasking registers could be accessed */
> > -static RISCVException pointer_masking(CPURISCVState *env, int csrno)
> > -{
> > - /* Check if j-ext is present */
> > - if (riscv_has_ext(env, RVJ)) {
> > - return RISCV_EXCP_NONE;
> > - }
> > - return RISCV_EXCP_ILLEGAL_INST;
> > -}
> > -
> > static int aia_hmode(CPURISCVState *env, int csrno)
> > {
> > if (!riscv_cpu_cfg(env)->ext_ssaia) {
> > @@ -1355,7 +1345,6 @@ static RISCVException write_mstatus(CPURISCVState
> *env, int csrno,
> > env->xl = cpu_recompute_xl(env);
> > }
> >
> > - riscv_cpu_update_mask(env);
> > return RISCV_EXCP_NONE;
> > }
> >
> > @@ -3900,302 +3889,6 @@ static RISCVException read_tinfo(CPURISCVState
> *env, int csrno,
> > return RISCV_EXCP_NONE;
> > }
> >
> > -/*
> > - * Functions to access Pointer Masking feature registers
> > - * We have to check if current priv lvl could modify
> > - * csr in given mode
> > - */
> > -static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
> > -{
> > - int csr_priv = get_field(csrno, 0x300);
> > - int pm_current;
> > -
> > - if (env->debugger) {
> > - return false;
> > - }
> > - /*
> > - * If priv lvls differ that means we're accessing csr from higher
> priv lvl,
> > - * so allow the access
> > - */
> > - if (env->priv != csr_priv) {
> > - return false;
> > - }
> > - switch (env->priv) {
> > - case PRV_M:
> > - pm_current = get_field(env->mmte, M_PM_CURRENT);
> > - break;
> > - case PRV_S:
> > - pm_current = get_field(env->mmte, S_PM_CURRENT);
> > - break;
> > - case PRV_U:
> > - pm_current = get_field(env->mmte, U_PM_CURRENT);
> > - break;
> > - default:
> > - g_assert_not_reached();
> > - }
> > - /* It's same priv lvl, so we allow to modify csr only if
> pm.current==1 */
> > - return !pm_current;
> > -}
> > -
> > -static RISCVException read_mmte(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > -{
> > - *val = env->mmte & MMTE_MASK;
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException write_mmte(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > -{
> > - uint64_t mstatus;
> > - target_ulong wpri_val = val & MMTE_MASK;
> > -
> > - if (val != wpri_val) {
> > - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
> > - TARGET_FMT_lx "\n", "MMTE: WPRI violation written
> 0x",
> > - val, "vs expected 0x", wpri_val);
> > - }
> > - /* for machine mode pm.current is hardwired to 1 */
> > - wpri_val |= MMTE_M_PM_CURRENT;
> > -
> > - /* hardwiring pm.instruction bit to 0, since it's not supported yet
> */
> > - wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
> > - env->mmte = wpri_val | EXT_STATUS_DIRTY;
> > - riscv_cpu_update_mask(env);
> > -
> > - /* Set XS and SD bits, since PM CSRs are dirty */
> > - mstatus = env->mstatus | MSTATUS_XS;
> > - write_mstatus(env, csrno, mstatus);
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException read_smte(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > -{
> > - *val = env->mmte & SMTE_MASK;
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException write_smte(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > -{
> > - target_ulong wpri_val = val & SMTE_MASK;
> > -
> > - if (val != wpri_val) {
> > - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
> > - TARGET_FMT_lx "\n", "SMTE: WPRI violation written
> 0x",
> > - val, "vs expected 0x", wpri_val);
> > - }
> > -
> > - /* if pm.current==0 we can't modify current PM CSRs */
> > - if (check_pm_current_disabled(env, csrno)) {
> > - return RISCV_EXCP_NONE;
> > - }
> > -
> > - wpri_val |= (env->mmte & ~SMTE_MASK);
> > - write_mmte(env, csrno, wpri_val);
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException read_umte(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > -{
> > - *val = env->mmte & UMTE_MASK;
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException write_umte(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > -{
> > - target_ulong wpri_val = val & UMTE_MASK;
> > -
> > - if (val != wpri_val) {
> > - qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s"
> > - TARGET_FMT_lx "\n", "UMTE: WPRI violation written
> 0x",
> > - val, "vs expected 0x", wpri_val);
> > - }
> > -
> > - if (check_pm_current_disabled(env, csrno)) {
> > - return RISCV_EXCP_NONE;
> > - }
> > -
> > - wpri_val |= (env->mmte & ~UMTE_MASK);
> > - write_mmte(env, csrno, wpri_val);
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > -{
> > - *val = env->mpmmask;
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > -{
> > - uint64_t mstatus;
> > -
> > - env->mpmmask = val;
> > - if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
> > - env->cur_pmmask = val;
> > - }
> > - env->mmte |= EXT_STATUS_DIRTY;
> > -
> > - /* Set XS and SD bits, since PM CSRs are dirty */
> > - mstatus = env->mstatus | MSTATUS_XS;
> > - write_mstatus(env, csrno, mstatus);
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException read_spmmask(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > -{
> > - *val = env->spmmask;
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException write_spmmask(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > -{
> > - uint64_t mstatus;
> > -
> > - /* if pm.current==0 we can't modify current PM CSRs */
> > - if (check_pm_current_disabled(env, csrno)) {
> > - return RISCV_EXCP_NONE;
> > - }
> > - env->spmmask = val;
> > - if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
> > - env->cur_pmmask = val;
> > - if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
> > - env->cur_pmmask &= UINT32_MAX;
> > - }
> > - }
> > - env->mmte |= EXT_STATUS_DIRTY;
> > -
> > - /* Set XS and SD bits, since PM CSRs are dirty */
> > - mstatus = env->mstatus | MSTATUS_XS;
> > - write_mstatus(env, csrno, mstatus);
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException read_upmmask(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > -{
> > - *val = env->upmmask;
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException write_upmmask(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > -{
> > - uint64_t mstatus;
> > -
> > - /* if pm.current==0 we can't modify current PM CSRs */
> > - if (check_pm_current_disabled(env, csrno)) {
> > - return RISCV_EXCP_NONE;
> > - }
> > - env->upmmask = val;
> > - if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
> > - env->cur_pmmask = val;
> > - if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
> > - env->cur_pmmask &= UINT32_MAX;
> > - }
> > - }
> > - env->mmte |= EXT_STATUS_DIRTY;
> > -
> > - /* Set XS and SD bits, since PM CSRs are dirty */
> > - mstatus = env->mstatus | MSTATUS_XS;
> > - write_mstatus(env, csrno, mstatus);
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > -{
> > - *val = env->mpmbase;
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > -{
> > - uint64_t mstatus;
> > -
> > - env->mpmbase = val;
> > - if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) {
> > - env->cur_pmbase = val;
> > - }
> > - env->mmte |= EXT_STATUS_DIRTY;
> > -
> > - /* Set XS and SD bits, since PM CSRs are dirty */
> > - mstatus = env->mstatus | MSTATUS_XS;
> > - write_mstatus(env, csrno, mstatus);
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException read_spmbase(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > -{
> > - *val = env->spmbase;
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException write_spmbase(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > -{
> > - uint64_t mstatus;
> > -
> > - /* if pm.current==0 we can't modify current PM CSRs */
> > - if (check_pm_current_disabled(env, csrno)) {
> > - return RISCV_EXCP_NONE;
> > - }
> > - env->spmbase = val;
> > - if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) {
> > - env->cur_pmbase = val;
> > - if (cpu_get_xl(env, PRV_S) == MXL_RV32) {
> > - env->cur_pmbase &= UINT32_MAX;
> > - }
> > - }
> > - env->mmte |= EXT_STATUS_DIRTY;
> > -
> > - /* Set XS and SD bits, since PM CSRs are dirty */
> > - mstatus = env->mstatus | MSTATUS_XS;
> > - write_mstatus(env, csrno, mstatus);
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException read_upmbase(CPURISCVState *env, int csrno,
> > - target_ulong *val)
> > -{
> > - *val = env->upmbase;
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > -static RISCVException write_upmbase(CPURISCVState *env, int csrno,
> > - target_ulong val)
> > -{
> > - uint64_t mstatus;
> > -
> > - /* if pm.current==0 we can't modify current PM CSRs */
> > - if (check_pm_current_disabled(env, csrno)) {
> > - return RISCV_EXCP_NONE;
> > - }
> > - env->upmbase = val;
> > - if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) {
> > - env->cur_pmbase = val;
> > - if (cpu_get_xl(env, PRV_U) == MXL_RV32) {
> > - env->cur_pmbase &= UINT32_MAX;
> > - }
> > - }
> > - env->mmte |= EXT_STATUS_DIRTY;
> > -
> > - /* Set XS and SD bits, since PM CSRs are dirty */
> > - mstatus = env->mstatus | MSTATUS_XS;
> > - write_mstatus(env, csrno, mstatus);
> > - return RISCV_EXCP_NONE;
> > -}
> > -
> > #endif
> >
> > /* Crypto Extension */
> > @@ -4800,25 +4493,6 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> > [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata
> },
> > [CSR_TINFO] = { "tinfo", debug, read_tinfo, write_ignore
> },
> >
> > - /* User Pointer Masking */
> > - [CSR_UMTE] = { "umte", pointer_masking, read_umte,
> write_umte },
> > - [CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask,
> > - write_upmmask
> },
> > - [CSR_UPMBASE] = { "upmbase", pointer_masking, read_upmbase,
> > - write_upmbase
> },
> > - /* Machine Pointer Masking */
> > - [CSR_MMTE] = { "mmte", pointer_masking, read_mmte,
> write_mmte },
> > - [CSR_MPMMASK] = { "mpmmask", pointer_masking, read_mpmmask,
> > - write_mpmmask
> },
> > - [CSR_MPMBASE] = { "mpmbase", pointer_masking, read_mpmbase,
> > - write_mpmbase
> },
> > - /* Supervisor Pointer Masking */
> > - [CSR_SMTE] = { "smte", pointer_masking, read_smte,
> write_smte },
> > - [CSR_SPMMASK] = { "spmmask", pointer_masking, read_spmmask,
> > - write_spmmask
> },
> > - [CSR_SPMBASE] = { "spmbase", pointer_masking, read_spmbase,
> > - write_spmbase
> },
> > -
> > /* Performance Counters */
> > [CSR_HPMCOUNTER3] = { "hpmcounter3", ctr, read_hpmcounter
> },
> > [CSR_HPMCOUNTER4] = { "hpmcounter4", ctr, read_hpmcounter
> },
> > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > index fdde243e04..860fe56d43 100644
> > --- a/target/riscv/machine.c
> > +++ b/target/riscv/machine.c
> > @@ -164,14 +164,6 @@ static const VMStateDescription
> vmstate_pointermasking = {
> > .minimum_version_id = 1,
>
> The version_id and minimum_version_id should be bumped here
>
> Alistair
>
> > .needed = pointermasking_needed,
> > .fields = (VMStateField[]) {
> > - VMSTATE_UINTTL(env.mmte, RISCVCPU),
> > - VMSTATE_UINTTL(env.mpmmask, RISCVCPU),
> > - VMSTATE_UINTTL(env.mpmbase, RISCVCPU),
> > - VMSTATE_UINTTL(env.spmmask, RISCVCPU),
> > - VMSTATE_UINTTL(env.spmbase, RISCVCPU),
> > - VMSTATE_UINTTL(env.upmmask, RISCVCPU),
> > - VMSTATE_UINTTL(env.upmbase, RISCVCPU),
> > -
> > VMSTATE_END_OF_LIST()
> > }
> > };
> > @@ -267,7 +259,6 @@ static int riscv_cpu_post_load(void *opaque, int
> version_id)
> > CPURISCVState *env = &cpu->env;
> >
> > env->xl = cpu_recompute_xl(env);
> > - riscv_cpu_update_mask(env);
> > return 0;
> > }
> >
> > diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> > index f0be79bb16..6b4b9a671c 100644
> > --- a/target/riscv/translate.c
> > +++ b/target/riscv/translate.c
> > @@ -42,9 +42,6 @@ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl,
> cpu_vstart;
> > static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
> > static TCGv load_res;
> > static TCGv load_val;
> > -/* globals for PM CSRs */
> > -static TCGv pm_mask;
> > -static TCGv pm_base;
> >
> > /*
> > * If an operation is being performed on less than TARGET_LONG_BITS,
> > @@ -106,9 +103,6 @@ typedef struct DisasContext {
> > bool vl_eq_vlmax;
> > CPUState *cs;
> > TCGv zero;
> > - /* PointerMasking extension */
> > - bool pm_mask_enabled;
> > - bool pm_base_enabled;
> > /* Use icount trigger for native debug */
> > bool itrigger;
> > /* FRM is known to contain a valid value. */
> > @@ -582,14 +576,9 @@ static TCGv get_address(DisasContext *ctx, int rs1,
> int imm)
> > TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
> >
> > tcg_gen_addi_tl(addr, src1, imm);
> > - if (ctx->pm_mask_enabled) {
> > - tcg_gen_andc_tl(addr, addr, pm_mask);
> > - } else if (get_address_xl(ctx) == MXL_RV32) {
> > + if (get_address_xl(ctx) == MXL_RV32) {
> > tcg_gen_ext32u_tl(addr, addr);
> > }
> > - if (ctx->pm_base_enabled) {
> > - tcg_gen_or_tl(addr, addr, pm_base);
> > - }
> >
> > return addr;
> > }
> > @@ -601,14 +590,9 @@ static TCGv get_address_indexed(DisasContext *ctx,
> int rs1, TCGv offs)
> > TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
> >
> > tcg_gen_add_tl(addr, src1, offs);
> > - if (ctx->pm_mask_enabled) {
> > - tcg_gen_andc_tl(addr, addr, pm_mask);
> > - } else if (get_xl(ctx) == MXL_RV32) {
> > + if (get_xl(ctx) == MXL_RV32) {
> > tcg_gen_ext32u_tl(addr, addr);
> > }
> > - if (ctx->pm_base_enabled) {
> > - tcg_gen_or_tl(addr, addr, pm_base);
> > - }
> > return addr;
> > }
> >
> > @@ -1192,8 +1176,6 @@ static void
> riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> > ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
> > ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
> > ctx->cs = cs;
> > - ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS,
> PM_MASK_ENABLED);
> > - ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS,
> PM_BASE_ENABLED);
> > ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
> > ctx->zero = tcg_constant_tl(0);
> > ctx->virt_inst_excp = false;
> > @@ -1325,9 +1307,4 @@ void riscv_translate_init(void)
> > "load_res");
> > load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState,
> load_val),
> > "load_val");
> > - /* Assign PM CSRs to tcg globals */
> > - pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState,
> cur_pmmask),
> > - "pmmask");
> > - pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState,
> cur_pmbase),
> > - "pmbase");
> > }
> > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> > index c1c3a4d1ea..8e7a8e80a0 100644
> > --- a/target/riscv/vector_helper.c
> > +++ b/target/riscv/vector_helper.c
> > @@ -94,7 +94,7 @@ static inline uint32_t vext_max_elems(uint32_t desc,
> uint32_t log2_esz)
> >
> > static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong
> addr)
> > {
> > - return (addr & ~env->cur_pmmask) | env->cur_pmbase;
> > + return addr;
> > }
> >
> > /*
> > --
> > 2.34.1
> >
> >
>
[-- Attachment #2: Type: text/html, Size: 37871 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking
2024-01-05 1:02 ` Deepak Gupta
@ 2024-01-05 7:29 ` Alexey Baturo
2024-01-05 18:07 ` Deepak Gupta
0 siblings, 1 reply; 20+ messages in thread
From: Alexey Baturo @ 2024-01-05 7:29 UTC (permalink / raw)
To: Deepak Gupta
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
[-- Attachment #1: Type: text/plain, Size: 1271 bytes --]
> + addr = addr << pmlen;
> + if (signext) {
> + addr = (target_long)addr >> pmlen;
> + } else {
> + addr = addr >> pmlen;
Could you please elaborate a bit more on your concern here?
I believe this code works as intended: https://godbolt.org/z/b9c7na13a
Thanks
пт, 5 янв. 2024 г. в 04:02, Deepak Gupta <debug@rivosinc.com>:
> > --- a/target/riscv/vector_helper.c
> > +++ b/target/riscv/vector_helper.c
> > @@ -94,6 +94,18 @@ static inline uint32_t vext_max_elems(uint32_t desc,
> uint32_t log2_esz)
> >
> > static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong
> addr)
> > {
> > + RISCVPmPmm pmm = riscv_pm_get_pmm(env);
> > + if (pmm == PMM_FIELD_DISABLED)
> > + return addr;
> > + int pmlen = riscv_pm_get_pmlen(pmm);
> > + bool signext = !riscv_cpu_bare_mode(env);
> > + addr = addr << pmlen;
> > + /* sign/zero extend masked address by N-1 bit */
> > + if (signext) {
> > + addr = (target_long)addr >> pmlen;
>
> These look like right shift operations and not sign extensions of N-1 bit
>
> > + } else {
> > + addr = addr >> pmlen;
>
> Same here.
>
> > + }
> > return addr;
> > }
> >
> > --
> > 2.34.1
> >
> >
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
2024-01-05 0:46 ` Deepak Gupta
@ 2024-01-05 7:33 ` Alexey Baturo
2024-01-05 18:13 ` Deepak Gupta
0 siblings, 1 reply; 20+ messages in thread
From: Alexey Baturo @ 2024-01-05 7:33 UTC (permalink / raw)
To: Deepak Gupta
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
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I think you're right, thanks.
I'll add a check for M-mode as well and I guess I'll have to rename the
function.
Any ideas on the proper and self-describing name?
Thanks
пт, 5 янв. 2024 г. в 03:46, Deepak Gupta <debug@rivosinc.com>:
> On Wed, Jan 3, 2024 at 10:59 AM Alexey Baturo <baturo.alexey@gmail.com>
> wrote:
> > +
> > +bool riscv_cpu_bare_mode(CPURISCVState *env)
> > +{
> > + int satp_mode = 0;
> > +#ifndef CONFIG_USER_ONLY
> > + if (riscv_cpu_mxl(env) == MXL_RV32) {
> > + satp_mode = get_field(env->satp, SATP32_MODE);
> > + } else {
> > + satp_mode = get_field(env->satp, SATP64_MODE);
> > + }
> > +#endif
> > + return (satp_mode == VM_1_10_MBARE);
> > +}
> > +
>
> Assume the CPU was in S or U with satp = non-bare mode but then a
> transfer to M-mode happened.
> In that case, even though the CPU is in M mode, the above function
> will return non-bare mode and enforce
> signed extension on M mode pointer masking (if enabled).
>
> right or am I missing something here?
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking
2024-01-05 7:29 ` Alexey Baturo
@ 2024-01-05 18:07 ` Deepak Gupta
0 siblings, 0 replies; 20+ messages in thread
From: Deepak Gupta @ 2024-01-05 18:07 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Fri, Jan 05, 2024 at 10:29:35AM +0300, Alexey Baturo wrote:
>> + addr = addr << pmlen;
>> + if (signext) {
>> + addr = (target_long)addr >> pmlen;
>> + } else {
>> + addr = addr >> pmlen;
>Could you please elaborate a bit more on your concern here?
>I believe this code works as intended: https://godbolt.org/z/b9c7na13a
Nevermind I missed this above in code.
addr = addr << pmlen;
You're good. Sorry about that.
>
>Thanks
>
>пт, 5 янв. 2024 г. в 04:02, Deepak Gupta <debug@rivosinc.com>:
>
>> > --- a/target/riscv/vector_helper.c
>> > +++ b/target/riscv/vector_helper.c
>> > @@ -94,6 +94,18 @@ static inline uint32_t vext_max_elems(uint32_t desc,
>> uint32_t log2_esz)
>> >
>> > static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong
>> addr)
>> > {
>> > + RISCVPmPmm pmm = riscv_pm_get_pmm(env);
>> > + if (pmm == PMM_FIELD_DISABLED)
>> > + return addr;
>> > + int pmlen = riscv_pm_get_pmlen(pmm);
>> > + bool signext = !riscv_cpu_bare_mode(env);
>> > + addr = addr << pmlen;
>> > + /* sign/zero extend masked address by N-1 bit */
>> > + if (signext) {
>> > + addr = (target_long)addr >> pmlen;
>>
>> These look like right shift operations and not sign extensions of N-1 bit
>>
>> > + } else {
>> > + addr = addr >> pmlen;
>>
>> Same here.
>>
>> > + }
>> > return addr;
>> > }
>> >
>> > --
>> > 2.34.1
>> >
>> >
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking
2024-01-05 7:33 ` Alexey Baturo
@ 2024-01-05 18:13 ` Deepak Gupta
0 siblings, 0 replies; 20+ messages in thread
From: Deepak Gupta @ 2024-01-05 18:13 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Fri, Jan 05, 2024 at 10:33:40AM +0300, Alexey Baturo wrote:
>I think you're right, thanks.
>I'll add a check for M-mode as well and I guess I'll have to rename the
>function.
>Any ideas on the proper and self-describing name?
Since all we care for is whether virtual memory is enabled and in effect or not.
Some suggestions below
`
bool riscv_cpu_mmu_enabled
bool riscv_cpu_paging_enabled
bool riscv_cpu_virt_mem_enabled
>
>Thanks
>
>пт, 5 янв. 2024 г. в 03:46, Deepak Gupta <debug@rivosinc.com>:
>
>> On Wed, Jan 3, 2024 at 10:59 AM Alexey Baturo <baturo.alexey@gmail.com>
>> wrote:
>> > +
>> > +bool riscv_cpu_bare_mode(CPURISCVState *env)
>> > +{
>> > + int satp_mode = 0;
>> > +#ifndef CONFIG_USER_ONLY
>> > + if (riscv_cpu_mxl(env) == MXL_RV32) {
>> > + satp_mode = get_field(env->satp, SATP32_MODE);
>> > + } else {
>> > + satp_mode = get_field(env->satp, SATP64_MODE);
>> > + }
>> > +#endif
>> > + return (satp_mode == VM_1_10_MBARE);
>> > +}
>> > +
>>
>> Assume the CPU was in S or U with satp = non-bare mode but then a
>> transfer to M-mode happened.
>> In that case, even though the CPU is in M mode, the above function
>> will return non-bare mode and enforce
>> signed extension on M mode pointer masking (if enabled).
>>
>> right or am I missing something here?
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension
2024-01-05 7:23 ` Alexey Baturo
@ 2024-01-08 0:33 ` Alistair Francis
0 siblings, 0 replies; 20+ messages in thread
From: Alistair Francis @ 2024-01-08 0:33 UTC (permalink / raw)
To: Alexey Baturo
Cc: richard.henderson, zhiwei_liu, palmer, Alistair.Francis, sagark,
kbastian, qemu-devel, qemu-riscv
On Fri, Jan 5, 2024 at 5:23 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> I might be wrong here, but right now J in MISA is unused.
I suspect you are right, it would be worth confirming though.
> I think the J-letter extension is still a thing, but current extensions like Zjpm and Zjid follow the Z ext scheme.
> Do you think it should be removed?
It sounds like it should be removed then
Alistair
>
>
> пт, 5 янв. 2024 г. в 08:28, Alistair Francis <alistair23@gmail.com>:
>>
>> On Thu, Jan 4, 2024 at 4:58 AM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>> >
>> > From: Alexey Baturo <baturo.alexey@gmail.com>
>> >
>> > Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
>> > ---
>> > target/riscv/cpu.c | 8 ++++++++
>> > 1 file changed, 8 insertions(+)
>> >
>> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> > index 1e6571ce99..13389ddc55 100644
>> > --- a/target/riscv/cpu.c
>> > +++ b/target/riscv/cpu.c
>> > @@ -153,6 +153,9 @@ const RISCVIsaExtData isa_edata_arr[] = {
>> > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
>> > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
>> > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
>> > + ISA_EXT_DATA_ENTRY(ssnpm, PRIV_VERSION_1_12_0, ext_ssnpm),
>> > + ISA_EXT_DATA_ENTRY(smnpm, PRIV_VERSION_1_12_0, ext_smnpm),
>> > + ISA_EXT_DATA_ENTRY(smmpm, PRIV_VERSION_1_12_0, ext_smmpm),
>> > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
>> > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
>> > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
>> > @@ -1337,6 +1340,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>> >
>> > MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
>> >
>> > + /* Zjpm v0.8 extensions */
>> > + MULTI_EXT_CFG_BOOL("ssnpm", ext_ssnpm, false),
>> > + MULTI_EXT_CFG_BOOL("smnpm", ext_smnpm, false),
>> > + MULTI_EXT_CFG_BOOL("smmpm", ext_smmpm, false),
>>
>> What happens to the existing J property?
>>
>>
>> Alistair
>>
>> > +
>> > MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
>> > MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
>> > MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
>> > --
>> > 2.34.1
>> >
>> >
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2024-01-08 0:35 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-01-03 18:57 [PATCH v3 0/6] Pointer Masking update for Zjpm v0.8 Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 1/6] target/riscv: Remove obsolete pointer masking extension code Alexey Baturo
2024-01-05 5:04 ` Alistair Francis
2024-01-05 7:23 ` Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 2/6] target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v0.8 Alexey Baturo
2024-01-03 18:57 ` [PATCH v3 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking Alexey Baturo
2024-01-05 0:46 ` Deepak Gupta
2024-01-05 7:33 ` Alexey Baturo
2024-01-05 18:13 ` Deepak Gupta
2024-01-03 18:57 ` [PATCH v3 4/6] target/riscv: Add pointer masking tb flags Alexey Baturo
2024-01-03 22:08 ` Richard Henderson
2024-01-03 18:57 ` [PATCH v3 5/6] target/riscv: Update address modify functions to take into account pointer masking Alexey Baturo
2024-01-03 22:18 ` Richard Henderson
2024-01-05 1:02 ` Deepak Gupta
2024-01-05 7:29 ` Alexey Baturo
2024-01-05 18:07 ` Deepak Gupta
2024-01-03 18:57 ` [PATCH v3 6/6] target/riscv: Enable updates for pointer masking variables and thus enable pointer masking extension Alexey Baturo
2024-01-05 5:27 ` Alistair Francis
2024-01-05 7:23 ` Alexey Baturo
2024-01-08 0:33 ` Alistair Francis
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