[PATCH v3 00/16] drm/i915: (stolen) memory region related fixes

[PATCH v3 00/16] drm/i915: (stolen) memory region related fixes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Attempt to fix the mess around stolen memory, especially on MTL
with it's special (and apparenly broken) not-actually-lmem stolen.

The series is made up of roughtly three parts:
1. General refactoring/debug improvement for mem regions
2. Deal with the broken BAR stuff on MTL
3. Fix initial display plane readout for MTL

v2: Try to relocate the BIOS fb to start of ggtt to make
    space for the GuC stuff at the top end of ggtt
v3: Skip ton VM guests as they won't have access to stolen directly
    Annotate more initial fb takeover failure paths
    Add the w/a numbers

Cc: Paz Zcharya <pazz@chromium.org>

Ville Syrjälä (16):
  drm/i915: Use struct resource for memory region IO as well
  drm/i915: Print memory region info during probe
  drm/i915: Remove ad-hoc lmem/stolen debugs
  drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory access
  drm/i915: Disable the "binder"
  drm/i915: Rename the DSM/GSM registers
  drm/i915: Fix PTE decode during initial plane readout
  drm/i915: Fix region start during initial plane readout
  drm/i915: Fix MTL initial plane readout
  drm/i915: s/phys_base/dma_addr/
  drm/i915: Split the smem and lmem plane readout apart
  drm/i915: Simplify intel_initial_plane_config() calling convention
  drm/i915/fbdev: Fix smem_start for LMEMBAR stolen objects
  drm/i915: Tweak BIOS fb reuse check
  drm/i915: Try to relocate the BIOS fb to the start of ggtt
  drm/i915: Annotate more of the BIOS fb takeover failure paths

 drivers/gpu/drm/i915/display/i9xx_plane.c     |  30 ++
 drivers/gpu/drm/i915/display/i9xx_plane.h     |   7 +
 drivers/gpu/drm/i915/display/intel_display.c  |   5 +
 .../gpu/drm/i915/display/intel_display_core.h |   2 +
 .../drm/i915/display/intel_display_driver.c   |   7 +-
 .../drm/i915/display/intel_display_types.h    |   2 +
 drivers/gpu/drm/i915/display/intel_fbdev_fb.c |   5 +-
 .../drm/i915/display/intel_plane_initial.c    | 257 +++++++++++++-----
 .../drm/i915/display/intel_plane_initial.h    |   4 +-
 .../drm/i915/display/skl_universal_plane.c    |  28 ++
 .../drm/i915/display/skl_universal_plane.h    |   2 +
 drivers/gpu/drm/i915/gem/i915_gem_region.c    |   2 +-
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c    |  33 ++-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c       |   8 +-
 .../drm/i915/gem/selftests/i915_gem_mman.c    |  18 +-
 drivers/gpu/drm/i915/gt/intel_ggtt.c          |  16 +-
 drivers/gpu/drm/i915/gt/intel_gtt.c           |   3 +-
 drivers/gpu/drm/i915/gt/intel_region_lmem.c   |  14 +-
 drivers/gpu/drm/i915/gt/selftest_tlb.c        |   4 +-
 drivers/gpu/drm/i915/i915_gpu_error.c         |   2 +-
 drivers/gpu/drm/i915/i915_query.c             |   2 +-
 drivers/gpu/drm/i915/i915_reg.h               |   7 +-
 drivers/gpu/drm/i915/intel_memory_region.c    |  33 ++-
 drivers/gpu/drm/i915/intel_memory_region.h    |   3 +-
 drivers/gpu/drm/i915/intel_region_ttm.c       |   8 +-
 .../drm/i915/selftests/intel_memory_region.c  |   4 +-
 26 files changed, 365 insertions(+), 141 deletions(-)

-- 
2.41.0

[PATCH v3 01/16] drm/i915: Use struct resource for memory region IO as well

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

mem->region is a struct resource, but mem->io_start and
mem->io_size are not for whatever reason. Let's unify this
and convert the io stuff into a struct resource as well.
Should make life a little less annoying when you don't have
juggle between two different approaches all the time.

Mostly done using cocci (with manual tweaks at all the
places where we mutate io_size by hand):
@@
struct intel_memory_region *M;
expression START, SIZE;
@@
- M->io_start = START;
- M->io_size = SIZE;
+ M->io = DEFINE_RES_MEM(START, SIZE);

@@
struct intel_memory_region *M;
@@
- M->io_start
+ M->io.start

@@
struct intel_memory_region M;
@@
- M.io_start
+ M.io.start

@@
expression M;
@@
- M->io_size
+ resource_size(&M->io)

@@
expression M;
@@
- M.io_size
+ resource_size(&M.io)

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbdev_fb.c  |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_region.c     |  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c     | 17 +++++++++--------
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c        |  8 ++++----
 .../gpu/drm/i915/gem/selftests/i915_gem_mman.c | 18 +++++++++---------
 drivers/gpu/drm/i915/gt/intel_region_lmem.c    | 11 +++--------
 drivers/gpu/drm/i915/gt/selftest_tlb.c         |  4 ++--
 drivers/gpu/drm/i915/i915_gpu_error.c          |  2 +-
 drivers/gpu/drm/i915/i915_query.c              |  2 +-
 drivers/gpu/drm/i915/intel_memory_region.c     | 15 +++++++--------
 drivers/gpu/drm/i915/intel_memory_region.h     |  3 +--
 drivers/gpu/drm/i915/intel_region_ttm.c        |  8 ++++----
 .../drm/i915/selftests/intel_memory_region.c   |  4 ++--
 13 files changed, 45 insertions(+), 51 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
index 717c3a3237c4..1ac05d90b2e8 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
@@ -78,7 +78,7 @@ int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info
 
 		/* Use fbdev's framebuffer from lmem for discrete */
 		info->fix.smem_start =
-			(unsigned long)(mem->io_start +
+			(unsigned long)(mem->io.start +
 					i915_gem_object_get_dma_address(obj, 0));
 		info->fix.smem_len = obj->base.size;
 	} else {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index a4fb577eceb4..b09b74a2448b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -129,7 +129,7 @@ i915_gem_object_create_region_at(struct intel_memory_region *mem,
 		return ERR_PTR(-EINVAL);
 
 	if (!(flags & I915_BO_ALLOC_GPU_ONLY) &&
-	    offset + size > mem->io_size &&
+	    offset + size > resource_size(&mem->io) &&
 	    !i915_ggtt_has_aperture(to_gt(mem->i915)->ggtt))
 		return ERR_PTR(-ENOSPC);
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 8c88075eeab2..d2440c793f84 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -541,7 +541,9 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
 
 	/* Exclude the reserved region from driver use */
 	mem->region.end = i915->dsm.reserved.start - 1;
-	mem->io_size = min(mem->io_size, resource_size(&mem->region));
+	mem->io = DEFINE_RES_MEM(mem->io.start,
+				 min(resource_size(&mem->io),
+				     resource_size(&mem->region)));
 
 	i915->dsm.usable_size = resource_size(&mem->region);
 
@@ -752,7 +754,7 @@ static int _i915_gem_object_stolen_init(struct intel_memory_region *mem,
 	 * With discrete devices, where we lack a mappable aperture there is no
 	 * possible way to ever access this memory on the CPU side.
 	 */
-	if (mem->type == INTEL_MEMORY_STOLEN_LOCAL && !mem->io_size &&
+	if (mem->type == INTEL_MEMORY_STOLEN_LOCAL && !resource_size(&mem->io) &&
 	    !(flags & I915_BO_ALLOC_GPU_ONLY))
 		return -ENOSPC;
 
@@ -838,13 +840,12 @@ static int init_stolen_lmem(struct intel_memory_region *mem)
 		return 0;
 	}
 
-	if (mem->io_size &&
-	    !io_mapping_init_wc(&mem->iomap, mem->io_start, mem->io_size))
+	if (resource_size(&mem->io) &&
+	    !io_mapping_init_wc(&mem->iomap, mem->io.start, resource_size(&mem->io)))
 		goto err_cleanup;
 
-	drm_dbg(&i915->drm, "Stolen Local memory IO start: %pa\n",
-		&mem->io_start);
-	drm_dbg(&i915->drm, "Stolen Local DSM base: %pa\n", &mem->region.start);
+	drm_dbg(&i915->drm, "Stolen Local DSM: %pR\n", &mem->region);
+	drm_dbg(&i915->drm, "Stolen Local memory IO: %pR\n", &mem->io);
 
 	return 0;
 
@@ -855,7 +856,7 @@ static int init_stolen_lmem(struct intel_memory_region *mem)
 
 static int release_stolen_lmem(struct intel_memory_region *mem)
 {
-	if (mem->io_size)
+	if (resource_size(&mem->io))
 		io_mapping_fini(&mem->iomap);
 	i915_gem_cleanup_stolen(mem->i915);
 	return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 6b69ef0cdbb4..19467ff70ca9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -144,13 +144,13 @@ i915_ttm_place_from_region(const struct intel_memory_region *mr,
 		place->fpfn = offset >> PAGE_SHIFT;
 		WARN_ON(overflows_type(place->fpfn + (size >> PAGE_SHIFT), place->lpfn));
 		place->lpfn = place->fpfn + (size >> PAGE_SHIFT);
-	} else if (mr->io_size && mr->io_size < mr->total) {
+	} else if (resource_size(&mr->io) && resource_size(&mr->io) < mr->total) {
 		if (flags & I915_BO_ALLOC_GPU_ONLY) {
 			place->flags |= TTM_PL_FLAG_TOPDOWN;
 		} else {
 			place->fpfn = 0;
-			WARN_ON(overflows_type(mr->io_size >> PAGE_SHIFT, place->lpfn));
-			place->lpfn = mr->io_size >> PAGE_SHIFT;
+			WARN_ON(overflows_type(resource_size(&mr->io) >> PAGE_SHIFT, place->lpfn));
+			place->lpfn = resource_size(&mr->io) >> PAGE_SHIFT;
 		}
 	}
 }
@@ -1090,7 +1090,7 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
 			struct intel_memory_region *mr = obj->mm.placements[i];
 			unsigned int flags;
 
-			if (!mr->io_size && mr->type != INTEL_MEMORY_SYSTEM)
+			if (!resource_size(&mr->io) && mr->type != INTEL_MEMORY_SYSTEM)
 				continue;
 
 			flags = obj->flags;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 2c51a2c452fc..99a9ade73956 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -1054,7 +1054,7 @@ static int igt_fill_mappable(struct intel_memory_region *mr,
 	int err;
 
 	total = 0;
-	size = mr->io_size;
+	size = resource_size(&mr->io);
 	do {
 		struct drm_i915_gem_object *obj;
 
@@ -1315,28 +1315,28 @@ static int igt_mmap_migrate(void *arg)
 		struct intel_memory_region *mixed[] = { mr, system };
 		struct intel_memory_region *single[] = { mr };
 		struct ttm_resource_manager *man = mr->region_private;
-		resource_size_t saved_io_size;
+		struct resource saved_io;
 		int err;
 
 		if (mr->private)
 			continue;
 
-		if (!mr->io_size)
+		if (!resource_size(&mr->io))
 			continue;
 
 		/*
 		 * For testing purposes let's force small BAR, if not already
 		 * present.
 		 */
-		saved_io_size = mr->io_size;
-		if (mr->io_size == mr->total) {
-			resource_size_t io_size = mr->io_size;
+		saved_io = mr->io;
+		if (resource_size(&mr->io) == mr->total) {
+			resource_size_t io_size = resource_size(&mr->io);
 
 			io_size = rounddown_pow_of_two(io_size >> 1);
 			if (io_size < PAGE_SIZE)
 				continue;
 
-			mr->io_size = io_size;
+			mr->io = DEFINE_RES_MEM(mr->io.start, io_size);
 			i915_ttm_buddy_man_force_visible_size(man,
 							      io_size >> PAGE_SHIFT);
 		}
@@ -1396,9 +1396,9 @@ static int igt_mmap_migrate(void *arg)
 					 IGT_MMAP_MIGRATE_FAIL_GPU |
 					 IGT_MMAP_MIGRATE_UNFAULTABLE);
 out_io_size:
-		mr->io_size = saved_io_size;
+		mr->io = saved_io;
 		i915_ttm_buddy_man_force_visible_size(man,
-						      mr->io_size >> PAGE_SHIFT);
+						      resource_size(&mr->io) >> PAGE_SHIFT);
 		if (err)
 			return err;
 	}
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index f8512aee58a8..6f96a6b70601 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -144,8 +144,8 @@ region_lmem_init(struct intel_memory_region *mem)
 	int ret;
 
 	if (!io_mapping_init_wc(&mem->iomap,
-				mem->io_start,
-				mem->io_size))
+				mem->io.start,
+				resource_size(&mem->io)))
 		return -EIO;
 
 	ret = intel_region_ttm_init(mem);
@@ -274,12 +274,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 		goto err_region_put;
 
 	drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region);
-	drm_dbg(&i915->drm, "Local memory IO start: %pa\n",
-		&mem->io_start);
-	drm_info(&i915->drm, "Local memory IO size: %pa\n",
-		 &mem->io_size);
-	drm_info(&i915->drm, "Local memory available: %pa\n",
-		 &lmem_size);
+	drm_dbg(&i915->drm, "Local memory IO: %pR\n", &mem->io);
 
 	if (io_size < lmem_size)
 		drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider enabling 'Resizable BAR' or similar, if available in the BIOS.\n",
diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 00b872b6380b..3941f2d6fa47 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -206,8 +206,8 @@ static struct drm_i915_gem_object *create_lmem(struct intel_gt *gt)
 	 * of pages. To succeed with both allocations, especially in case of Small
 	 * BAR, try to allocate no more than quarter of mappable memory.
 	 */
-	if (mr && size > mr->io_size / 4)
-		size = mr->io_size / 4;
+	if (mr && size > resource_size(&mr->io) / 4)
+		size = resource_size(&mr->io) / 4;
 
 	return i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGUOUS);
 }
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index d04660b60046..a0b784ebaddd 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1157,7 +1157,7 @@ i915_vma_coredump_create(const struct intel_gt *gt,
 			dma_addr_t offset = dma - mem->region.start;
 			void __iomem *s;
 
-			if (offset + PAGE_SIZE > mem->io_size) {
+			if (offset + PAGE_SIZE > resource_size(&mem->io)) {
 				ret = -EINVAL;
 				break;
 			}
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 00871ef99792..fa3e937ed3f5 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -502,7 +502,7 @@ static int query_memregion_info(struct drm_i915_private *i915,
 		info.probed_size = mr->total;
 
 		if (mr->type == INTEL_MEMORY_LOCAL)
-			info.probed_cpu_visible_size = mr->io_size;
+			info.probed_cpu_visible_size = resource_size(&mr->io);
 		else
 			info.probed_cpu_visible_size = mr->total;
 
diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index 60a03340bbd4..b2708f8cac2a 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -50,7 +50,7 @@ static int __iopagetest(struct intel_memory_region *mem,
 	if (memchr_inv(result, value, sizeof(result))) {
 		dev_err(mem->i915->drm.dev,
 			"Failed to read back from memory region:%pR at [%pa + %pa] for %ps; wrote %x, read (%x, %x, %x)\n",
-			&mem->region, &mem->io_start, &offset, caller,
+			&mem->region, &mem->io.start, &offset, caller,
 			value, result[0], result[1], result[2]);
 		return -EINVAL;
 	}
@@ -67,11 +67,11 @@ static int iopagetest(struct intel_memory_region *mem,
 	int err;
 	int i;
 
-	va = ioremap_wc(mem->io_start + offset, PAGE_SIZE);
+	va = ioremap_wc(mem->io.start + offset, PAGE_SIZE);
 	if (!va) {
 		dev_err(mem->i915->drm.dev,
 			"Failed to ioremap memory region [%pa + %pa] for %ps\n",
-			&mem->io_start, &offset, caller);
+			&mem->io.start, &offset, caller);
 		return -EFAULT;
 	}
 
@@ -102,10 +102,10 @@ static int iomemtest(struct intel_memory_region *mem,
 	resource_size_t last, page;
 	int err;
 
-	if (mem->io_size < PAGE_SIZE)
+	if (resource_size(&mem->io) < PAGE_SIZE)
 		return 0;
 
-	last = mem->io_size - PAGE_SIZE;
+	last = resource_size(&mem->io) - PAGE_SIZE;
 
 	/*
 	 * Quick test to check read/write access to the iomap (backing store).
@@ -207,7 +207,7 @@ static int intel_memory_region_memtest(struct intel_memory_region *mem,
 	struct drm_i915_private *i915 = mem->i915;
 	int err = 0;
 
-	if (!mem->io_start)
+	if (!mem->io.start)
 		return 0;
 
 	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) || i915->params.memtest)
@@ -252,8 +252,7 @@ intel_memory_region_create(struct drm_i915_private *i915,
 
 	mem->i915 = i915;
 	mem->region = DEFINE_RES_MEM(start, size);
-	mem->io_start = io_start;
-	mem->io_size = io_size;
+	mem->io = DEFINE_RES_MEM(io_start, io_size);
 	mem->min_page_size = min_page_size;
 	mem->ops = ops;
 	mem->total = size;
diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
index 9ba36454e51b..40810cfb3fd9 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.h
+++ b/drivers/gpu/drm/i915/intel_memory_region.h
@@ -71,8 +71,7 @@ struct intel_memory_region {
 	struct io_mapping iomap;
 	struct resource region;
 
-	resource_size_t io_start;
-	resource_size_t io_size;
+	struct resource io;
 	resource_size_t min_page_size;
 	resource_size_t total;
 
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c b/drivers/gpu/drm/i915/intel_region_ttm.c
index bf6097e7433d..04525d92bec5 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -87,7 +87,7 @@ int intel_region_ttm_init(struct intel_memory_region *mem)
 
 	ret = i915_ttm_buddy_man_init(bdev, mem_type, false,
 				      resource_size(&mem->region),
-				      mem->io_size,
+				      resource_size(&mem->io),
 				      mem->min_page_size, PAGE_SIZE);
 	if (ret)
 		return ret;
@@ -219,16 +219,16 @@ intel_region_ttm_resource_alloc(struct intel_memory_region *mem,
 			goto out;
 		}
 		place.lpfn = place.fpfn + (size >> PAGE_SHIFT);
-	} else if (mem->io_size && mem->io_size < mem->total) {
+	} else if (resource_size(&mem->io) && resource_size(&mem->io) < mem->total) {
 		if (flags & I915_BO_ALLOC_GPU_ONLY) {
 			place.flags |= TTM_PL_FLAG_TOPDOWN;
 		} else {
 			place.fpfn = 0;
-			if (WARN_ON(overflows_type(mem->io_size >> PAGE_SHIFT, place.lpfn))) {
+			if (WARN_ON(overflows_type(resource_size(&mem->io) >> PAGE_SHIFT, place.lpfn))) {
 				ret = -E2BIG;
 				goto out;
 			}
-			place.lpfn = mem->io_size >> PAGE_SHIFT;
+			place.lpfn = resource_size(&mem->io) >> PAGE_SHIFT;
 		}
 	}
 
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index d985d9bae2e8..ae6070b5bf07 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -544,8 +544,8 @@ static u64 igt_object_mappable_total(struct drm_i915_gem_object *obj)
 		u64 start = drm_buddy_block_offset(block);
 		u64 end = start + drm_buddy_block_size(mm, block);
 
-		if (start < mr->io_size)
-			total += min_t(u64, end, mr->io_size) - start;
+		if (start < resource_size(&mr->io))
+			total += min_t(u64, end, resource_size(&mr->io)) - start;
 	}
 
 	return total;
-- 
2.41.0

[PATCH v3 02/16] drm/i915: Print memory region info during probe

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Dump the details about every memory region into dmesg at probe time.
Avoids having to dig those out from random places when debugging stuff.

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_memory_region.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
index b2708f8cac2a..52d998e5c21a 100644
--- a/drivers/gpu/drm/i915/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/intel_memory_region.c
@@ -372,6 +372,24 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
 		i915->mm.regions[i] = mem;
 	}
 
+	for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
+		struct intel_memory_region *mem = i915->mm.regions[i];
+		u64 region_size, io_size;
+
+		if (!mem)
+			continue;
+
+		region_size = resource_size(&mem->region) >> 20;
+		io_size = resource_size(&mem->io) >> 20;
+
+		if (resource_size(&mem->io))
+			drm_dbg(&i915->drm, "Memory region(%d): %s: %llu MiB %pR, io: %llu MiB %pR\n",
+				mem->id, mem->name, region_size, &mem->region, io_size, &mem->io);
+		else
+			drm_dbg(&i915->drm, "Memory region(%d): %s: %llu MiB %pR, io: n/a\n",
+				mem->id, mem->name, region_size, &mem->region);
+	}
+
 	return 0;
 
 out_cleanup:
-- 
2.41.0

[PATCH v3 03/16] drm/i915: Remove ad-hoc lmem/stolen debugs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that intel_memory_regions_hw_probe() prints out each and every
memory region there's no reason to have ad-hoc debugs to do similar
things elsewhere.

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c  | 4 ----
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 3 ---
 2 files changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index d2440c793f84..ee237043c302 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -828,7 +828,6 @@ static const struct intel_memory_region_ops i915_region_stolen_smem_ops = {
 
 static int init_stolen_lmem(struct intel_memory_region *mem)
 {
-	struct drm_i915_private *i915 = mem->i915;
 	int err;
 
 	if (GEM_WARN_ON(resource_size(&mem->region) == 0))
@@ -844,9 +843,6 @@ static int init_stolen_lmem(struct intel_memory_region *mem)
 	    !io_mapping_init_wc(&mem->iomap, mem->io.start, resource_size(&mem->io)))
 		goto err_cleanup;
 
-	drm_dbg(&i915->drm, "Stolen Local DSM: %pR\n", &mem->region);
-	drm_dbg(&i915->drm, "Stolen Local memory IO: %pR\n", &mem->io);
-
 	return 0;
 
 err_cleanup:
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 6f96a6b70601..af357089da6e 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -273,9 +273,6 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 	if (err)
 		goto err_region_put;
 
-	drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region);
-	drm_dbg(&i915->drm, "Local memory IO: %pR\n", &mem->io);
-
 	if (io_size < lmem_size)
 		drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider enabling 'Resizable BAR' or similar, if available in the BIOS.\n",
 			 (u64)io_size >> 20);
-- 
2.41.0

[PATCH v3 04/16] drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory access

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On MTL accessing stolen memory via the BARs is somehow borked,
and it can hang the machine. As a workaround let's bypass the
BARs and just go straight to DSMBASE/GSMBASE instead.

Note that on every other platform this itself would hang the
machine, but on MTL the system firmware is expected to relax
the access permission guarding stolen memory to enable this
workaround, and thus direct CPU accesses should be fine.

The raw stolen memory areas won't be passed to VMs so we'll
need to risk using the BAR there for the initial setup. Once
command submission is up we should switch to MI_UPDATE_GTT
which at least shouldn't hang the whole machine.

v2: Don't use direct GSM/DSM access on guests
    Add w/a number

Cc: Paz Zcharya <pazz@chromium.org>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 14 +++++++++++++-
 drivers/gpu/drm/i915/gt/intel_ggtt.c       | 16 +++++++++++++++-
 2 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index ee237043c302..0b429f1ecd99 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -941,7 +941,19 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
 		dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
 	}
 
-	if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
+	if (IS_METEORLAKE(i915) && !i915_run_as_guest()) {
+		/*
+		 * Wa_22018444074
+		 *
+		 * Access via BAR can hang MTL, go directly to DSM,
+		 * except for VM guests which won't have access to it.
+		 *
+		 * Normally this would not work but on MTL the system firmware
+		 * should have relaxed the access permissions sufficiently.
+		 */
+		io_start = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
+		io_size = dsm_size;
+	} else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
 		io_start = 0;
 		io_size = 0;
 	} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 21a7e3191c18..7a716ff16070 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -24,6 +24,7 @@
 #include "intel_ring.h"
 #include "i915_drv.h"
 #include "i915_pci.h"
+#include "i915_reg.h"
 #include "i915_request.h"
 #include "i915_scatterlist.h"
 #include "i915_utils.h"
@@ -1152,13 +1153,26 @@ static unsigned int gen6_gttadr_offset(struct drm_i915_private *i915)
 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 {
 	struct drm_i915_private *i915 = ggtt->vm.i915;
+	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 	phys_addr_t phys_addr;
 	u32 pte_flags;
 	int ret;
 
 	GEM_WARN_ON(pci_resource_len(pdev, GEN4_GTTMMADR_BAR) != gen6_gttmmadr_size(i915));
-	phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
+	/*
+	 * Wa_22018444074
+	 *
+	 * Access via BAR can hang MTL, go directly to GSM,
+	 * except for VM guests which won't have access to it.
+	 *
+	 * Normally this would not work but on MTL the system firmware
+	 * should have relaxed the access permissions sufficiently.
+	 */
+	if (IS_METEORLAKE(i915) && !i915_run_as_guest())
+		phys_addr = intel_uncore_read64(uncore, GEN12_GSMBASE) & GEN12_BDSM_MASK;
+	else
+		phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
 
 	if (needs_wc_ggtt_mapping(i915))
 		ggtt->gsm = ioremap_wc(phys_addr, size);
-- 
2.41.0

[PATCH v3 05/16] drm/i915: Disable the "binder"

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that the GGTT PTE updates go straight to GSMBASE (bypassing
GTTMMADR) there should be no more risk of system hangs? So the
"binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
necessary, disable it.

My main worry with the MI_UPDATE_GTT are:
- only used on this one platform so very limited testing coverage
- async so more opprtunities to screw things up
- what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
  to finish?
- requires working command submission, so even getting a working
  display now depends on a lot more extra components working correctly

TODO: MI_UPDATE_GTT might be interesting as an optimization
though, so perhaps someone should look into always using it
(assuming the GPU is alive and well)?

v2: Keep using MI_UPDATE_GTT on VM guests

Cc: Paz Zcharya <pazz@chromium.org>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 86f73fe558ca..e83dabc56a14 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -24,7 +24,8 @@
 bool i915_ggtt_require_binder(struct drm_i915_private *i915)
 {
 	/* Wa_13010847436 & Wa_14019519902 */
-	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
+	return i915_run_as_guest() &&
+		MEDIA_VER_FULL(i915) == IP_VER(13, 0);
 }
 
 static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
-- 
2.41.0

[PATCH v3 06/16] drm/i915: Rename the DSM/GSM registers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

0x108100 and 0x1080c0 have been around since snb. Rename the
defines appropriately.

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c  | 4 ++--
 drivers/gpu/drm/i915/gt/intel_ggtt.c        | 2 +-
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h             | 7 ++++---
 4 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 0b429f1ecd99..ce6b860b393e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -935,7 +935,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
 		GEM_BUG_ON((dsm_base + dsm_size) > lmem_size);
 	} else {
 		/* Use DSM base address instead for stolen memory */
-		dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
+		dsm_base = intel_uncore_read64(uncore, GEN6_DSMBASE) & GEN11_BDSM_MASK;
 		if (WARN_ON(lmem_size < dsm_base))
 			return ERR_PTR(-ENODEV);
 		dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
@@ -951,7 +951,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
 		 * Normally this would not work but on MTL the system firmware
 		 * should have relaxed the access permissions sufficiently.
 		 */
-		io_start = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
+		io_start = intel_uncore_read64(uncore, GEN6_DSMBASE) & GEN11_BDSM_MASK;
 		io_size = dsm_size;
 	} else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
 		io_start = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 7a716ff16070..b87933e7671d 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1170,7 +1170,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 	 * should have relaxed the access permissions sufficiently.
 	 */
 	if (IS_METEORLAKE(i915) && !i915_run_as_guest())
-		phys_addr = intel_uncore_read64(uncore, GEN12_GSMBASE) & GEN12_BDSM_MASK;
+		phys_addr = intel_uncore_read64(uncore, GEN6_GSMBASE) & GEN11_BDSM_MASK;
 	else
 		phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index af357089da6e..51bb27e10a4f 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -240,7 +240,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 		lmem_size -= tile_stolen;
 	} else {
 		/* Stolen starts from GSMBASE without CCS */
-		lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
+		lmem_size = intel_uncore_read64(&i915->uncore, GEN6_GSMBASE);
 	}
 
 	i915_resize_lmem_bar(i915, lmem_size);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75bc08081fce..0d35173a7718 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6320,9 +6320,10 @@ enum skl_power_gate {
 #define   GMS_MASK			REG_GENMASK(15, 8)
 #define   GGMS_MASK			REG_GENMASK(7, 6)
 
-#define GEN12_GSMBASE			_MMIO(0x108100)
-#define GEN12_DSMBASE			_MMIO(0x1080C0)
-#define   GEN12_BDSM_MASK		REG_GENMASK64(63, 20)
+#define GEN6_GSMBASE			_MMIO(0x108100)
+#define GEN6_DSMBASE			_MMIO(0x1080C0)
+#define   GEN6_BDSM_MASK		REG_GENMASK64(31, 20)
+#define   GEN11_BDSM_MASK		REG_GENMASK64(63, 20)
 
 #define XEHP_CLOCK_GATE_DIS		_MMIO(0x101014)
 #define   SGSI_SIDECLK_DIS		REG_BIT(17)
-- 
2.41.0

[PATCH v3 07/16] drm/i915: Fix PTE decode during initial plane readout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When multiple pipes are enabled by the BIOS we try to read out each
in turn. But we do the readout for the second only after the inherited
vma for the first has been rebound into its original place (and thus
the PTEs have been rewritten). Unlike the BIOS we set some high caching
bits in the PTE on MTL which confuses the readout for the second plane.
Filter out the non-address bits from the PTE value appropriately to
fix this.

I suppose it might also be possible that the BIOS would already set
some caching bits as well, in which case we'd run into this same
issue already for the first plane.

TODO:
- should abstract the PTE decoding to avoid details leaking all over
- should probably do the readout for all the planes before
  we touch anything (including the PTEs) so that we truly read
  out the BIOS state

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index a55c09cbd0e4..ffc92b18fcf5 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -72,7 +72,7 @@ initial_plane_vma(struct drm_i915_private *i915,
 			return NULL;
 		}
 
-		phys_base = pte & I915_GTT_PAGE_MASK;
+		phys_base = pte & GEN12_GGTT_PTE_ADDR_MASK;
 		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
 
 		/*
-- 
2.41.0

[PATCH v3 08/16] drm/i915: Fix region start during initial plane readout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On MTL the stolen region starts at offset 8MiB from the start of
LMEMBAR. The dma addresses are thus also offset by 8MiB. However the
mm_node/etc. is zero based, and i915_pages_create_for_stolen() will
add the appropriate region.start into the sg dma address. So when
we do the readout we need to convert the dma address read from
the PTE to be zero based as well.

Note that currently we don't take this path on MTL, but we should
and thus this needs to be fixed. For lmem this works correctly
already as the lmem region.start==0.

While at it let's also make sure the address points to somewhere within
the memory region. We don't need to check the size as
i915_gem_object_create_region_at() should later fail if the object size
exceeds the region size.

Cc: Paz Zcharya <pazz@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_plane_initial.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index ffc92b18fcf5..db594ccf0323 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -79,16 +79,18 @@ initial_plane_vma(struct drm_i915_private *i915,
 		 * We don't currently expect this to ever be placed in the
 		 * stolen portion.
 		 */
-		if (phys_base >= resource_size(&mem->region)) {
+		if (phys_base < mem->region.start || phys_base > mem->region.end) {
 			drm_err(&i915->drm,
-				"Initial plane programming using invalid range, phys_base=%pa\n",
-				&phys_base);
+				"Initial plane programming using invalid range, phys_base=%pa (%s [%pa-%pa])\n",
+				&phys_base, mem->region.name, &mem->region.start, &mem->region.end);
 			return NULL;
 		}
 
 		drm_dbg(&i915->drm,
 			"Using phys_base=%pa, based on initial plane programming\n",
 			&phys_base);
+
+		phys_base -= mem->region.start;
 	} else {
 		phys_base = base;
 		mem = i915->mm.stolen_region;
-- 
2.41.0

[PATCH v3 09/16] drm/i915: Fix MTL initial plane readout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

MTL stolen memory looks more like local memory, so use the
(now fixed) lmem path when doing the initial plane readout.

Cc: Paz Zcharya <pazz@chromium.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_plane_initial.c    | 25 +++++++++++++------
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index db594ccf0323..c72d4cacf631 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -59,7 +59,7 @@ initial_plane_vma(struct drm_i915_private *i915,
 		return NULL;
 
 	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
-	if (IS_DGFX(i915)) {
+	if (IS_DGFX(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915)) {
 		gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
 		gen8_pte_t pte;
 
@@ -73,11 +73,20 @@ initial_plane_vma(struct drm_i915_private *i915,
 		}
 
 		phys_base = pte & GEN12_GGTT_PTE_ADDR_MASK;
-		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
+
+		if (IS_DGFX(i915))
+			mem = i915->mm.regions[INTEL_REGION_LMEM_0];
+		else
+			mem = i915->mm.stolen_region;
+		if (!mem) {
+			drm_dbg_kms(&i915->drm,
+				    "Initial plane memory region not initialized\n");
+			return NULL;
+		}
 
 		/*
-		 * We don't currently expect this to ever be placed in the
-		 * stolen portion.
+		 * On lmem we don't currently expect this to
+		 * ever be placed in the stolen portion.
 		 */
 		if (phys_base < mem->region.start || phys_base > mem->region.end) {
 			drm_err(&i915->drm,
@@ -94,11 +103,13 @@ initial_plane_vma(struct drm_i915_private *i915,
 	} else {
 		phys_base = base;
 		mem = i915->mm.stolen_region;
+		if (!mem) {
+			drm_dbg_kms(&i915->drm,
+				    "Initial plane memory region not initialized\n");
+			return NULL;
+		}
 	}
 
-	if (!mem)
-		return NULL;
-
 	size = round_up(plane_config->base + plane_config->size,
 			mem->min_page_size);
 	size -= base;
-- 
2.41.0

[PATCH v3 10/16] drm/i915: s/phys_base/dma_addr/

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The address we read from the PTE is a dma address, not a physical
address. Rename the variable to say so.

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../gpu/drm/i915/display/intel_plane_initial.c    | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index c72d4cacf631..48b74319f45c 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -61,6 +61,7 @@ initial_plane_vma(struct drm_i915_private *i915,
 	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
 	if (IS_DGFX(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915)) {
 		gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
+		dma_addr_t dma_addr;
 		gen8_pte_t pte;
 
 		gte += base / I915_GTT_PAGE_SIZE;
@@ -72,7 +73,7 @@ initial_plane_vma(struct drm_i915_private *i915,
 			return NULL;
 		}
 
-		phys_base = pte & GEN12_GGTT_PTE_ADDR_MASK;
+		dma_addr = pte & GEN12_GGTT_PTE_ADDR_MASK;
 
 		if (IS_DGFX(i915))
 			mem = i915->mm.regions[INTEL_REGION_LMEM_0];
@@ -88,18 +89,18 @@ initial_plane_vma(struct drm_i915_private *i915,
 		 * On lmem we don't currently expect this to
 		 * ever be placed in the stolen portion.
 		 */
-		if (phys_base < mem->region.start || phys_base > mem->region.end) {
+		if (dma_addr < mem->region.start || dma_addr > mem->region.end) {
 			drm_err(&i915->drm,
-				"Initial plane programming using invalid range, phys_base=%pa (%s [%pa-%pa])\n",
-				&phys_base, mem->region.name, &mem->region.start, &mem->region.end);
+				"Initial plane programming using invalid range, dma_addr=%pa (%s [%pa-%pa])\n",
+				&dma_addr, mem->region.name, &mem->region.start, &mem->region.end);
 			return NULL;
 		}
 
 		drm_dbg(&i915->drm,
-			"Using phys_base=%pa, based on initial plane programming\n",
-			&phys_base);
+			"Using dma_addr=%pa, based on initial plane programming\n",
+			&dma_addr);
 
-		phys_base -= mem->region.start;
+		phys_base = dma_addr - mem->region.start;
 	} else {
 		phys_base = base;
 		mem = i915->mm.stolen_region;
-- 
2.41.0

[PATCH v3 11/16] drm/i915: Split the smem and lmem plane readout apart

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Declutter initial_plane_vma() a bit by pulling the lmem and smem
readout paths into their own functions.

TODO: the smem path should still be fixed to get and validate
      the dma address from the pte as well

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_display_types.h    |   2 +
 .../drm/i915/display/intel_plane_initial.c    | 145 +++++++++++-------
 2 files changed, 95 insertions(+), 52 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ae2e8cff9d69..319ba7aed4fa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -780,6 +780,8 @@ struct intel_plane_state {
 
 struct intel_initial_plane_config {
 	struct intel_framebuffer *fb;
+	struct intel_memory_region *mem;
+	resource_size_t phys_base;
 	struct i915_vma *vma;
 	unsigned int tiling;
 	int size;
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 48b74319f45c..78bff6181ceb 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -44,6 +44,93 @@ intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
 	return false;
 }
 
+static bool
+initial_plane_phys_lmem(struct drm_i915_private *i915,
+			struct intel_initial_plane_config *plane_config)
+{
+	gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
+	struct intel_memory_region *mem;
+	dma_addr_t dma_addr;
+	gen8_pte_t pte;
+	u32 base;
+
+	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
+
+	gte += base / I915_GTT_PAGE_SIZE;
+
+	pte = ioread64(gte);
+	if (!(pte & GEN12_GGTT_PTE_LM)) {
+		drm_err(&i915->drm,
+			"Initial plane programming missing PTE_LM bit\n");
+		return false;
+	}
+
+	dma_addr = pte & GEN12_GGTT_PTE_ADDR_MASK;
+
+	if (IS_DGFX(i915))
+		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
+	else
+		mem = i915->mm.stolen_region;
+	if (!mem) {
+		drm_dbg_kms(&i915->drm,
+			    "Initial plane memory region not initialized\n");
+		return false;
+	}
+
+	/*
+	 * On lmem we don't currently expect this to
+	 * ever be placed in the stolen portion.
+	 */
+	if (dma_addr < mem->region.start || dma_addr > mem->region.end) {
+		drm_err(&i915->drm,
+			"Initial plane programming using invalid range, dma_addr=%pa (%s [%pa-%pa])\n",
+			&dma_addr, mem->region.name, &mem->region.start, &mem->region.end);
+		return false;
+	}
+
+	drm_dbg(&i915->drm,
+		"Using dma_addr=%pa, based on initial plane programming\n",
+		&dma_addr);
+
+	plane_config->phys_base = dma_addr - mem->region.start;
+	plane_config->mem = mem;
+
+	return true;
+}
+
+static bool
+initial_plane_phys_smem(struct drm_i915_private *i915,
+			struct intel_initial_plane_config *plane_config)
+{
+	struct intel_memory_region *mem;
+	u32 base;
+
+	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
+
+	mem = i915->mm.stolen_region;
+	if (!mem) {
+		drm_dbg_kms(&i915->drm,
+			    "Initial plane memory region not initialized\n");
+		return false;
+	}
+
+	/* FIXME get and validate the dma_addr from the PTE */
+	plane_config->phys_base = base;
+	plane_config->mem = mem;
+
+	return true;
+}
+
+static bool
+initial_plane_phys(struct drm_i915_private *i915,
+		   struct intel_initial_plane_config *plane_config)
+{
+	if (IS_DGFX(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915))
+		return initial_plane_phys_lmem(i915, plane_config);
+	else
+		return initial_plane_phys_smem(i915, plane_config);
+}
+
 static struct i915_vma *
 initial_plane_vma(struct drm_i915_private *i915,
 		  struct intel_initial_plane_config *plane_config)
@@ -58,59 +145,13 @@ initial_plane_vma(struct drm_i915_private *i915,
 	if (plane_config->size == 0)
 		return NULL;
 
+	if (!initial_plane_phys(i915, plane_config))
+		return NULL;
+
+	phys_base = plane_config->phys_base;
+	mem = plane_config->mem;
+
 	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
-	if (IS_DGFX(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915)) {
-		gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
-		dma_addr_t dma_addr;
-		gen8_pte_t pte;
-
-		gte += base / I915_GTT_PAGE_SIZE;
-
-		pte = ioread64(gte);
-		if (!(pte & GEN12_GGTT_PTE_LM)) {
-			drm_err(&i915->drm,
-				"Initial plane programming missing PTE_LM bit\n");
-			return NULL;
-		}
-
-		dma_addr = pte & GEN12_GGTT_PTE_ADDR_MASK;
-
-		if (IS_DGFX(i915))
-			mem = i915->mm.regions[INTEL_REGION_LMEM_0];
-		else
-			mem = i915->mm.stolen_region;
-		if (!mem) {
-			drm_dbg_kms(&i915->drm,
-				    "Initial plane memory region not initialized\n");
-			return NULL;
-		}
-
-		/*
-		 * On lmem we don't currently expect this to
-		 * ever be placed in the stolen portion.
-		 */
-		if (dma_addr < mem->region.start || dma_addr > mem->region.end) {
-			drm_err(&i915->drm,
-				"Initial plane programming using invalid range, dma_addr=%pa (%s [%pa-%pa])\n",
-				&dma_addr, mem->region.name, &mem->region.start, &mem->region.end);
-			return NULL;
-		}
-
-		drm_dbg(&i915->drm,
-			"Using dma_addr=%pa, based on initial plane programming\n",
-			&dma_addr);
-
-		phys_base = dma_addr - mem->region.start;
-	} else {
-		phys_base = base;
-		mem = i915->mm.stolen_region;
-		if (!mem) {
-			drm_dbg_kms(&i915->drm,
-				    "Initial plane memory region not initialized\n");
-			return NULL;
-		}
-	}
-
 	size = round_up(plane_config->base + plane_config->size,
 			mem->min_page_size);
 	size -= base;
-- 
2.41.0

[PATCH v3 12/16] drm/i915: Simplify intel_initial_plane_config() calling convention

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

There's no reason the caller of intel_initial_plane_config() should
have to loop over the CRTCs. Pull the loop into the function to
make life simpler for the caller.

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_display_driver.c   |  7 +---
 .../drm/i915/display/intel_plane_initial.c    | 40 +++++++++++--------
 .../drm/i915/display/intel_plane_initial.h    |  4 +-
 3 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index ecf9cb74734b..f3fe1743243b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -415,7 +415,6 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
 {
 	struct drm_device *dev = &i915->drm;
 	enum pipe pipe;
-	struct intel_crtc *crtc;
 	int ret;
 
 	if (!HAS_DISPLAY(i915))
@@ -467,11 +466,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
 	intel_acpi_assign_connector_fwnodes(i915);
 	drm_modeset_unlock_all(dev);
 
-	for_each_intel_crtc(dev, crtc) {
-		if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
-			continue;
-		intel_crtc_initial_plane_config(crtc);
-	}
+	intel_initial_plane_config(i915);
 
 	/*
 	 * Make sure hardware watermarks really match the state we read out.
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 78bff6181ceb..b7e12b60d68b 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -357,25 +357,31 @@ static void plane_config_fini(struct intel_initial_plane_config *plane_config)
 		i915_vma_put(plane_config->vma);
 }
 
-void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
+void intel_initial_plane_config(struct drm_i915_private *i915)
 {
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct intel_initial_plane_config plane_config = {};
+	struct intel_crtc *crtc;
 
-	/*
-	 * Note that reserving the BIOS fb up front prevents us
-	 * from stuffing other stolen allocations like the ring
-	 * on top.  This prevents some ugliness at boot time, and
-	 * can even allow for smooth boot transitions if the BIOS
-	 * fb is large enough for the active pipe configuration.
-	 */
-	dev_priv->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
+	for_each_intel_crtc(&i915->drm, crtc) {
+		struct intel_initial_plane_config plane_config = {};
 
-	/*
-	 * If the fb is shared between multiple heads, we'll
-	 * just get the first one.
-	 */
-	intel_find_initial_plane_obj(crtc, &plane_config);
+		if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
+			continue;
 
-	plane_config_fini(&plane_config);
+		/*
+		 * Note that reserving the BIOS fb up front prevents us
+		 * from stuffing other stolen allocations like the ring
+		 * on top.  This prevents some ugliness at boot time, and
+		 * can even allow for smooth boot transitions if the BIOS
+		 * fb is large enough for the active pipe configuration.
+		 */
+		i915->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
+
+		/*
+		 * If the fb is shared between multiple heads, we'll
+		 * just get the first one.
+		 */
+		intel_find_initial_plane_obj(crtc, &plane_config);
+
+		plane_config_fini(&plane_config);
+	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.h b/drivers/gpu/drm/i915/display/intel_plane_initial.h
index c7e35ab3182b..64ab95239cd4 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.h
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.h
@@ -6,8 +6,8 @@
 #ifndef __INTEL_PLANE_INITIAL_H__
 #define __INTEL_PLANE_INITIAL_H__
 
-struct intel_crtc;
+struct drm_i915_private;
 
-void intel_crtc_initial_plane_config(struct intel_crtc *crtc);
+void intel_initial_plane_config(struct drm_i915_private *i915);
 
 #endif
-- 
2.41.0

[PATCH v3 13/16] drm/i915/fbdev: Fix smem_start for LMEMBAR stolen objects

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The "io" address of an object is its dma address minus the
region.start. Subtract the latter to make smem_start correct.
The current code happens to work for genuine LMEM objects
as LMEM region.start==0, but for LMEMBAR stolen objects
region.start!=0.

TODO: perhaps just set smem_start=0 always as our .fb_mmap()
implementation no longer depends on it? Need to double check
it's not needed for anything else...

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbdev_fb.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
index 1ac05d90b2e8..0665f943f65f 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
@@ -79,7 +79,8 @@ int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info
 		/* Use fbdev's framebuffer from lmem for discrete */
 		info->fix.smem_start =
 			(unsigned long)(mem->io.start +
-					i915_gem_object_get_dma_address(obj, 0));
+					i915_gem_object_get_dma_address(obj, 0) -
+					mem->region.start);
 		info->fix.smem_len = obj->base.size;
 	} else {
 		struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
-- 
2.41.0

[PATCH v3 14/16] drm/i915: Tweak BIOS fb reuse check

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we assume that we bind the BIOS fb exactly into the same
ggtt address where the BIOS left it. That is about to change, and
in order to keep intel_reuse_initial_plane_obj() working as intended
we need to compare the original ggtt offset (called 'base' here)
as opposed to the actual vma ggtt offset we selected. Otherwise
the first plane could change the ggtt offset, and then subsequent
planes would no longer notice that they are in fact using the same
ggtt offset that the first plane was already using. Thus the reuse
check will fail and we proceed to turn off these subsequent planes.

TODO: would probably make more sense to do the pure readout first
for all the planes, then check for fb reuse, and only then proceed
to pin the object into the final location in the ggtt...

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 .../drm/i915/display/intel_plane_initial.c    | 34 +++++++++++--------
 1 file changed, 19 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index b7e12b60d68b..82ab98985a09 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -13,20 +13,21 @@
 #include "intel_plane_initial.h"
 
 static bool
-intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
-			      const struct intel_initial_plane_config *plane_config,
+intel_reuse_initial_plane_obj(struct intel_crtc *this,
+			      const struct intel_initial_plane_config plane_configs[],
 			      struct drm_framebuffer **fb,
 			      struct i915_vma **vma)
 {
+	struct drm_i915_private *i915 = to_i915(this->base.dev);
 	struct intel_crtc *crtc;
 
 	for_each_intel_crtc(&i915->drm, crtc) {
-		struct intel_crtc_state *crtc_state =
-			to_intel_crtc_state(crtc->base.state);
-		struct intel_plane *plane =
+		const struct intel_plane *plane =
 			to_intel_plane(crtc->base.primary);
-		struct intel_plane_state *plane_state =
+		const struct intel_plane_state *plane_state =
 			to_intel_plane_state(plane->base.state);
+		const struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc->base.state);
 
 		if (!crtc_state->uapi.active)
 			continue;
@@ -34,7 +35,7 @@ intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
 		if (!plane_state->ggtt_vma)
 			continue;
 
-		if (intel_plane_ggtt_offset(plane_state) == plane_config->base) {
+		if (plane_configs[this->pipe].base == plane_configs[crtc->pipe].base) {
 			*fb = plane_state->hw.fb;
 			*vma = plane_state->ggtt_vma;
 			return true;
@@ -265,10 +266,11 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
 
 static void
 intel_find_initial_plane_obj(struct intel_crtc *crtc,
-			     struct intel_initial_plane_config *plane_config)
+			     struct intel_initial_plane_config plane_configs[])
 {
-	struct drm_device *dev = crtc->base.dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_initial_plane_config *plane_config =
+		&plane_configs[crtc->pipe];
 	struct intel_plane *plane =
 		to_intel_plane(crtc->base.primary);
 	struct intel_plane_state *plane_state =
@@ -294,7 +296,7 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc,
 	 * Failed to alloc the obj, check to see if we should share
 	 * an fb with another CRTC instead
 	 */
-	if (intel_reuse_initial_plane_obj(dev_priv, plane_config, &fb, &vma))
+	if (intel_reuse_initial_plane_obj(crtc, plane_configs, &fb, &vma))
 		goto valid_fb;
 
 	/*
@@ -359,10 +361,12 @@ static void plane_config_fini(struct intel_initial_plane_config *plane_config)
 
 void intel_initial_plane_config(struct drm_i915_private *i915)
 {
+	struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {};
 	struct intel_crtc *crtc;
 
 	for_each_intel_crtc(&i915->drm, crtc) {
-		struct intel_initial_plane_config plane_config = {};
+		struct intel_initial_plane_config *plane_config =
+			&plane_configs[crtc->pipe];
 
 		if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
 			continue;
@@ -374,14 +378,14 @@ void intel_initial_plane_config(struct drm_i915_private *i915)
 		 * can even allow for smooth boot transitions if the BIOS
 		 * fb is large enough for the active pipe configuration.
 		 */
-		i915->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
+		i915->display.funcs.display->get_initial_plane_config(crtc, plane_config);
 
 		/*
 		 * If the fb is shared between multiple heads, we'll
 		 * just get the first one.
 		 */
-		intel_find_initial_plane_obj(crtc, &plane_config);
+		intel_find_initial_plane_obj(crtc, plane_configs);
 
-		plane_config_fini(&plane_config);
+		plane_config_fini(plane_config);
 	}
 }
-- 
2.41.0

[PATCH v3 15/16] drm/i915: Try to relocate the BIOS fb to the start of ggtt

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On MTL the GOP (for whatever reason) likes to bind its framebuffer
high up in the ggtt address space. This can conflict with whatever
ggtt_reserve_guc_top() is trying to do, and the result is that
ggtt_reserve_guc_top() fails and then we proceed to explode when
trying to tear down the driver. Thus far I haven't analyzed what
causes the actual fireworks, but it's not super important as even
if it didn't explode we'd still fail the driver load and the user
would be left with an unusable GPU.

To remedy this (without having to figure out exactly what
ggtt_reserve_guc_top() is trying to achieve) we can attempt to
relocate the BIOS framebuffer to a lower ggtt address. We can do
this at this early point in driver init because nothing else is
supposed to be clobbering the ggtt yet. So we simply change where
in the ggtt we pin the vma, the original PTEs will be left as is,
and the new PTEs will get written with the same dma addresses.
The plane will keep on scanning out from the original PTEs until
we are done with the whole process, and at that point we rewrite
the plane's surface address register to point at the new ggtt
address.

Since we don't need a specific ggtt address for the plane
(apart from needing it to land in the mappable region for
normal stolen objects) we'll just try to pin it without a fixed
offset first. It should end up at the lowest available address
(which really should be 0 at this point in the driver init).
If that fails we'll fall back to just pinning it exactly to the
origianal address.

To make sure we don't accidentlally pin it partially over the
original ggtt range (as that would corrupt the original PTEs)
we reserve the original range temporarily during this process.

v2: Try to pin explicitly to ggtt offset 0 as otherwise DG2 puts it
    even higher (atm we have no PIN_LOW flag to force it low)

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_plane.c     | 30 +++++++++++
 drivers/gpu/drm/i915/display/i9xx_plane.h     |  7 +++
 drivers/gpu/drm/i915/display/intel_display.c  |  5 ++
 .../gpu/drm/i915/display/intel_display_core.h |  2 +
 .../drm/i915/display/intel_plane_initial.c    | 53 ++++++++++++++++++-
 .../drm/i915/display/skl_universal_plane.c    | 28 ++++++++++
 .../drm/i915/display/skl_universal_plane.h    |  2 +
 7 files changed, 125 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 91f2bc405cba..0279c8aabdd1 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -1060,3 +1060,33 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
 	plane_config->fb = intel_fb;
 }
+
+bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,
+				     const struct intel_initial_plane_config *plane_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	const struct intel_plane_state *plane_state =
+		to_intel_plane_state(plane->base.state);
+	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
+	u32 base;
+
+	if (!plane_state->uapi.visible)
+		return false;
+
+	base = intel_plane_ggtt_offset(plane_state);
+
+	/*
+	 * We may have moved the surface to a different
+	 * part of ggtt, make the plane aware of that.
+	 */
+	if (plane_config->base == base)
+		return false;
+
+	if (DISPLAY_VER(dev_priv) >= 4)
+		intel_de_write(dev_priv, DSPSURF(i9xx_plane), base);
+	else
+		intel_de_write(dev_priv, DSPADDR(i9xx_plane), base);
+
+	return true;
+}
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.h b/drivers/gpu/drm/i915/display/i9xx_plane.h
index b3d724a144cb..0ca12d1e6839 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.h
@@ -26,6 +26,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe);
 
 void i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 				   struct intel_initial_plane_config *plane_config);
+bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,
+				     const struct intel_initial_plane_config *plane_config);
 #else
 static inline unsigned int i965_plane_max_stride(struct intel_plane *plane,
 						 u32 pixel_format, u64 modifier,
@@ -46,6 +48,11 @@ static inline void i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 						 struct intel_initial_plane_config *plane_config)
 {
 }
+static inline bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,
+						   const struct intel_initial_plane_config *plane_config)
+{
+	return false;
+}
 #endif
 
 #endif
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a92e959c8ac7..a07ea3352e0c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7820,6 +7820,7 @@ static const struct intel_display_funcs skl_display_funcs = {
 	.crtc_disable = hsw_crtc_disable,
 	.commit_modeset_enables = skl_commit_modeset_enables,
 	.get_initial_plane_config = skl_get_initial_plane_config,
+	.fixup_initial_plane_config = skl_fixup_initial_plane_config,
 };
 
 static const struct intel_display_funcs ddi_display_funcs = {
@@ -7828,6 +7829,7 @@ static const struct intel_display_funcs ddi_display_funcs = {
 	.crtc_disable = hsw_crtc_disable,
 	.commit_modeset_enables = intel_commit_modeset_enables,
 	.get_initial_plane_config = i9xx_get_initial_plane_config,
+	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
 };
 
 static const struct intel_display_funcs pch_split_display_funcs = {
@@ -7836,6 +7838,7 @@ static const struct intel_display_funcs pch_split_display_funcs = {
 	.crtc_disable = ilk_crtc_disable,
 	.commit_modeset_enables = intel_commit_modeset_enables,
 	.get_initial_plane_config = i9xx_get_initial_plane_config,
+	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
 };
 
 static const struct intel_display_funcs vlv_display_funcs = {
@@ -7844,6 +7847,7 @@ static const struct intel_display_funcs vlv_display_funcs = {
 	.crtc_disable = i9xx_crtc_disable,
 	.commit_modeset_enables = intel_commit_modeset_enables,
 	.get_initial_plane_config = i9xx_get_initial_plane_config,
+	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
 };
 
 static const struct intel_display_funcs i9xx_display_funcs = {
@@ -7852,6 +7856,7 @@ static const struct intel_display_funcs i9xx_display_funcs = {
 	.crtc_disable = i9xx_crtc_disable,
 	.commit_modeset_enables = intel_commit_modeset_enables,
 	.get_initial_plane_config = i9xx_get_initial_plane_config,
+	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
 };
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 8853a05dc331..26a0a23e3234 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -66,6 +66,8 @@ struct intel_display_funcs {
 				struct intel_crtc_state *);
 	void (*get_initial_plane_config)(struct intel_crtc *,
 					 struct intel_initial_plane_config *);
+	bool (*fixup_initial_plane_config)(struct intel_crtc *crtc,
+					   const struct intel_initial_plane_config *plane_config);
 	void (*crtc_enable)(struct intel_atomic_state *state,
 			    struct intel_crtc *crtc);
 	void (*crtc_disable)(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 82ab98985a09..00e194ee129a 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -3,9 +3,11 @@
  * Copyright © 2021 Intel Corporation
  */
 
+#include "gem/i915_gem_lmem.h"
 #include "gem/i915_gem_region.h"
 #include "i915_drv.h"
 #include "intel_atomic_plane.h"
+#include "intel_crtc.h"
 #include "intel_display.h"
 #include "intel_display_types.h"
 #include "intel_fb.h"
@@ -138,6 +140,7 @@ initial_plane_vma(struct drm_i915_private *i915,
 {
 	struct intel_memory_region *mem;
 	struct drm_i915_gem_object *obj;
+	struct drm_mm_node orig_mm = {};
 	struct i915_vma *vma;
 	resource_size_t phys_base;
 	u32 base, size;
@@ -195,23 +198,66 @@ initial_plane_vma(struct drm_i915_private *i915,
 		goto err_obj;
 	}
 
+	/*
+	 * MTL GOP likes to place the framebuffer high up in ggtt,
+	 * which can cause problems for ggtt_reserve_guc_top().
+	 * Try to pin it to a low ggtt address instead to avoid that.
+	 */
+	base = 0;
+
+	if (base != plane_config->base) {
+		struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
+		int ret;
+
+		/*
+		 * Make sure the original and new locations
+		 * can't overlap. That would corrupt the original
+		 * PTEs which are still being used for scanout.
+		 */
+		ret = i915_gem_gtt_reserve(&ggtt->vm, NULL, &orig_mm,
+					   size, plane_config->base,
+					   I915_COLOR_UNEVICTABLE, PIN_NOEVICT);
+		if (ret)
+			goto err_obj;
+	}
+
 	vma = i915_vma_instance(obj, &to_gt(i915)->ggtt->vm, NULL);
 	if (IS_ERR(vma))
 		goto err_obj;
 
+retry:
 	pinctl = PIN_GLOBAL | PIN_OFFSET_FIXED | base;
-	if (HAS_GMCH(i915))
+	if (!i915_gem_object_is_lmem(obj))
 		pinctl |= PIN_MAPPABLE;
-	if (i915_vma_pin(vma, 0, 0, pinctl))
+	if (i915_vma_pin(vma, 0, 0, pinctl)) {
+		if (drm_mm_node_allocated(&orig_mm)) {
+			drm_mm_remove_node(&orig_mm);
+			/*
+			 * Try again, but this time pin
+			 * it to its original location.
+			 */
+			base = plane_config->base;
+			goto retry;
+		}
 		goto err_obj;
+	}
 
 	if (i915_gem_object_is_tiled(obj) &&
 	    !i915_vma_is_map_and_fenceable(vma))
 		goto err_obj;
 
+	if (drm_mm_node_allocated(&orig_mm))
+		drm_mm_remove_node(&orig_mm);
+
+	drm_dbg_kms(&i915->drm,
+		    "Initial plane fb bound to 0x%x in the ggtt (original 0x%x)\n",
+		    i915_ggtt_offset(vma), plane_config->base);
+
 	return vma;
 
 err_obj:
+	if (drm_mm_node_allocated(&orig_mm))
+		drm_mm_remove_node(&orig_mm);
 	i915_gem_object_put(obj);
 	return NULL;
 }
@@ -386,6 +432,9 @@ void intel_initial_plane_config(struct drm_i915_private *i915)
 		 */
 		intel_find_initial_plane_obj(crtc, plane_configs);
 
+		if (i915->display.funcs.display->fixup_initial_plane_config(crtc, plane_config))
+			intel_crtc_wait_for_next_vblank(crtc);
+
 		plane_config_fini(plane_config);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 511dc1544854..392d93e97bf8 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2624,3 +2624,31 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
 error:
 	kfree(intel_fb);
 }
+
+bool skl_fixup_initial_plane_config(struct intel_crtc *crtc,
+				    const struct intel_initial_plane_config *plane_config)
+{
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	struct intel_plane *plane = to_intel_plane(crtc->base.primary);
+	const struct intel_plane_state *plane_state =
+		to_intel_plane_state(plane->base.state);
+	enum plane_id plane_id = plane->id;
+	enum pipe pipe = crtc->pipe;
+	u32 base;
+
+	if (!plane_state->uapi.visible)
+		return false;
+
+	base = intel_plane_ggtt_offset(plane_state);
+
+	/*
+	 * We may have moved the surface to a different
+	 * part of ggtt, make the plane aware of that.
+	 */
+	if (plane_config->base == base)
+		return false;
+
+	intel_de_write(i915, PLANE_SURF(pipe, plane_id), base);
+
+	return true;
+}
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h
index be64c201f9b3..e92e00c01b29 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
@@ -22,6 +22,8 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
 
 void skl_get_initial_plane_config(struct intel_crtc *crtc,
 				  struct intel_initial_plane_config *plane_config);
+bool skl_fixup_initial_plane_config(struct intel_crtc *crtc,
+				    const struct intel_initial_plane_config *plane_config);
 
 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
 
-- 
2.41.0

[PATCH v3 16/16] drm/i915: Annotate more of the BIOS fb takeover failure paths

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Annotate a few more of the failure paths on the initial
BIOS fb takeover to avoid having to guess why things
aren't working the way we expect.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_plane_initial.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 00e194ee129a..d9a356d5661b 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -167,14 +167,19 @@ initial_plane_vma(struct drm_i915_private *i915,
 	 */
 	if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
 	    mem == i915->mm.stolen_region &&
-	    size * 2 > i915->dsm.usable_size)
+	    size * 2 > i915->dsm.usable_size) {
+		drm_dbg_kms(&i915->drm, "Initial FB size exceeds half of stolen, discarding\n");
 		return NULL;
+	}
 
 	obj = i915_gem_object_create_region_at(mem, phys_base, size,
 					       I915_BO_ALLOC_USER |
 					       I915_BO_PREALLOC);
-	if (IS_ERR(obj))
+	if (IS_ERR(obj)) {
+		drm_dbg_kms(&i915->drm, "Failed to preallocate initial FB in %s\n",
+			    mem->region.name);
 		return NULL;
+	}
 
 	/*
 	 * Mark it WT ahead of time to avoid changing the
-- 
2.41.0

✗ Fi.CI.CHECKPATCH: warning for drm/i915: (stolen) memory region related fixes (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: (stolen) memory region related fixes (rev6)
URL   : https://patchwork.freedesktop.org/series/127721/
State : warning

== Summary ==

Error: dim checkpatch failed
72a9e5460135 drm/i915: Use struct resource for memory region IO as well
-:387: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#387: FILE: drivers/gpu/drm/i915/intel_region_ttm.c:227:
+			if (WARN_ON(overflows_type(resource_size(&mem->io) >> PAGE_SHIFT, place.lpfn))) {

total: 0 errors, 1 warnings, 0 checks, 281 lines checked
04c5e770efde drm/i915: Print memory region info during probe
a7d0ba6c8a13 drm/i915: Remove ad-hoc lmem/stolen debugs
29a8a9da9fa3 drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory access
516154c02d82 drm/i915: Disable the "binder"
dcd84ee46528 drm/i915: Rename the DSM/GSM registers
5d36651d103b drm/i915: Fix PTE decode during initial plane readout
c4b43d6e7c3b drm/i915: Fix region start during initial plane readout
0a52c22fa07c drm/i915: Fix MTL initial plane readout
2152a95323ef drm/i915: s/phys_base/dma_addr/
cc095e647e13 drm/i915: Split the smem and lmem plane readout apart
a36eb1e75a76 drm/i915: Simplify intel_initial_plane_config() calling convention
e66cb88c8697 drm/i915/fbdev: Fix smem_start for LMEMBAR stolen objects
90b4fdfecf0b drm/i915: Tweak BIOS fb reuse check
66f0e8965f66 drm/i915: Try to relocate the BIOS fb to the start of ggtt
-:104: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#104: FILE: drivers/gpu/drm/i915/display/i9xx_plane.h:51:
 }
+static inline bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,

-:105: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#105: FILE: drivers/gpu/drm/i915/display/i9xx_plane.h:52:
+						   const struct intel_initial_plane_config *plane_config)

total: 0 errors, 1 warnings, 1 checks, 229 lines checked
9dc34e4ff2f9 drm/i915: Annotate more of the BIOS fb takeover failure paths

✗ Fi.CI.SPARSE: warning for drm/i915: (stolen) memory region related fixes (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915: (stolen) memory region related fixes (rev6)
URL   : https://patchwork.freedesktop.org/series/127721/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ Fi.CI.BAT: failure for drm/i915: (stolen) memory region related fixes (rev6)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 11817 bytes --]

== Series Details ==

Series: drm/i915: (stolen) memory region related fixes (rev6)
URL   : https://patchwork.freedesktop.org/series/127721/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14125 -> Patchwork_127721v6
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_127721v6 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_127721v6, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/index.html

Participating hosts (39 -> 39)
------------------------------

  Additional (1): bat-dg2-8 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_127721v6:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - bat-mtlp-8:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14125/bat-mtlp-8/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-mtlp-8/igt@i915_module_load@load.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_pm:
    - {bat-rpls-3}:       [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14125/bat-rpls-3/igt@i915_selftest@live@gt_pm.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-rpls-3/igt@i915_selftest@live@gt_pm.html

  
Known issues
------------

  Here are the changes found in Patchwork_127721v6 that come from known issues:

### CI changes ###

#### Issues hit ####

  * boot:
    - fi-bsw-n3050:       [PASS][5] -> [FAIL][6] ([i915#8293])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14125/fi-bsw-n3050/boot.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/fi-bsw-n3050/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s0@lmem0:
    - bat-dg2-8:          NOTRUN -> [INCOMPLETE][7] ([i915#9275])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@gem_exec_suspend@basic-s0@lmem0.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - bat-dg2-9:          [PASS][8] -> [INCOMPLETE][9] ([i915#9275])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14125/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_exec_suspend@basic-s3@smem:
    - bat-rpls-2:         [PASS][10] -> [ABORT][11] ([i915#10096])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14125/bat-rpls-2/igt@gem_exec_suspend@basic-s3@smem.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-rpls-2/igt@gem_exec_suspend@basic-s3@smem.html

  * igt@gem_mmap@basic:
    - bat-dg2-8:          NOTRUN -> [SKIP][12] ([i915#4083])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@basic:
    - bat-dg2-8:          NOTRUN -> [SKIP][13] ([i915#4077]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@gem_mmap_gtt@basic.html

  * igt@gem_tiled_pread_basic:
    - bat-dg2-8:          NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-dg2-8:          NOTRUN -> [SKIP][15] ([i915#6621])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@gt_pm:
    - bat-adln-1:         [PASS][16] -> [DMESG-FAIL][17] ([i915#10010])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14125/bat-adln-1/igt@i915_selftest@live@gt_pm.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-adln-1/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@reset:
    - fi-apl-guc:         [PASS][18] -> [DMESG-WARN][19] ([i915#9730]) +31 other tests dmesg-warn
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14125/fi-apl-guc/igt@i915_selftest@live@reset.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/fi-apl-guc/igt@i915_selftest@live@reset.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - fi-apl-guc:         [PASS][20] -> [DMESG-WARN][21] ([i915#180])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14125/fi-apl-guc/igt@i915_suspend@basic-s2idle-without-i915.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/fi-apl-guc/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-dg2-8:          NOTRUN -> [SKIP][22] ([i915#6645])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-dg2-8:          NOTRUN -> [SKIP][23] ([i915#5190])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-dg2-8:          NOTRUN -> [SKIP][24] ([i915#4215] / [i915#5190])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_addfb_basic@framebuffer-vs-set-tiling:
    - bat-dg2-8:          NOTRUN -> [SKIP][25] ([i915#4212]) +7 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-dg2-8:          NOTRUN -> [SKIP][26] ([i915#4103] / [i915#4213]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-dg2-8:          NOTRUN -> [SKIP][27] ([fdo#109285])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-dg2-8:          NOTRUN -> [SKIP][28] ([i915#5274])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-dg2-8:          NOTRUN -> [SKIP][29] ([i915#5354])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-dg2-8:          NOTRUN -> [SKIP][30] ([i915#3555])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-dg2-8:          NOTRUN -> [SKIP][31] ([i915#3708])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-dg2-8:          NOTRUN -> [SKIP][32] ([i915#3708] / [i915#4077]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
    - bat-dg2-8:          NOTRUN -> [SKIP][33] ([i915#3291] / [i915#3708]) +2 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-dg2-8/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@vgem_basic@unload:
    - {bat-adls-6}:       [INCOMPLETE][34] ([i915#10095]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14125/bat-adls-6/igt@vgem_basic@unload.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/bat-adls-6/igt@vgem_basic@unload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#10010]: https://gitlab.freedesktop.org/drm/intel/issues/10010
  [i915#10095]: https://gitlab.freedesktop.org/drm/intel/issues/10095
  [i915#10096]: https://gitlab.freedesktop.org/drm/intel/issues/10096
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#9275]: https://gitlab.freedesktop.org/drm/intel/issues/9275
  [i915#9673]: https://gitlab.freedesktop.org/drm/intel/issues/9673
  [i915#9730]: https://gitlab.freedesktop.org/drm/intel/issues/9730
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732


Build changes
-------------

  * Linux: CI_DRM_14125 -> Patchwork_127721v6

  CI-20190529: 20190529
  CI_DRM_14125: fc429d95eec92e32db2ad6ae53f61587e3bdaf40 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7674: 7674
  Patchwork_127721v6: fc429d95eec92e32db2ad6ae53f61587e3bdaf40 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

58d111b814bc drm/i915: Annotate more of the BIOS fb takeover failure paths
d448deda76a8 drm/i915: Try to relocate the BIOS fb to the start of ggtt
57e359481075 drm/i915: Tweak BIOS fb reuse check
b54007ae7598 drm/i915/fbdev: Fix smem_start for LMEMBAR stolen objects
1e8f3155b5d3 drm/i915: Simplify intel_initial_plane_config() calling convention
ea5939af9d27 drm/i915: Split the smem and lmem plane readout apart
c53cb151af55 drm/i915: s/phys_base/dma_addr/
125dbfc67677 drm/i915: Fix MTL initial plane readout
50794c125f69 drm/i915: Fix region start during initial plane readout
c41d812ff0a5 drm/i915: Fix PTE decode during initial plane readout
c977303bac25 drm/i915: Rename the DSM/GSM registers
b3866f6af779 drm/i915: Disable the "binder"
b009f81cf0f1 drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory access
5a4d124b9688 drm/i915: Remove ad-hoc lmem/stolen debugs
8d25e0c33967 drm/i915: Print memory region info during probe
b4a6fafd2b00 drm/i915: Use struct resource for memory region IO as well

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v6/index.html

[-- Attachment #2: Type: text/html, Size: 13251 bytes --]

Re: [PATCH v3 02/16] drm/i915: Print memory region info during probe

[Nirmoy Das]

On 1/16/2024 8:56 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Dump the details about every memory region into dmesg at probe time.
> Avoids having to dig those out from random places when debugging stuff.
>
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_memory_region.c | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
> index b2708f8cac2a..52d998e5c21a 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> @@ -372,6 +372,24 @@ int intel_memory_regions_hw_probe(struct drm_i915_private *i915)
>   		i915->mm.regions[i] = mem;
>   	}
>   
> +	for (i = 0; i < ARRAY_SIZE(i915->mm.regions); i++) {
> +		struct intel_memory_region *mem = i915->mm.regions[i];
> +		u64 region_size, io_size;
> +
> +		if (!mem)
> +			continue;
> +
> +		region_size = resource_size(&mem->region) >> 20;
> +		io_size = resource_size(&mem->io) >> 20;
> +
> +		if (resource_size(&mem->io))
> +			drm_dbg(&i915->drm, "Memory region(%d): %s: %llu MiB %pR, io: %llu MiB %pR\n",
> +				mem->id, mem->name, region_size, &mem->region, io_size, &mem->io);
> +		else
> +			drm_dbg(&i915->drm, "Memory region(%d): %s: %llu MiB %pR, io: n/a\n",
> +				mem->id, mem->name, region_size, &mem->region);
> +	}
> +
>   	return 0;
>   
>   out_cleanup:

Re: [PATCH v3 01/16] drm/i915: Use struct resource for memory region IO as well

[Nirmoy Das]

On 1/16/2024 8:56 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> mem->region is a struct resource, but mem->io_start and
> mem->io_size are not for whatever reason. Let's unify this
> and convert the io stuff into a struct resource as well.
> Should make life a little less annoying when you don't have
> juggle between two different approaches all the time.
>
> Mostly done using cocci (with manual tweaks at all the
> places where we mutate io_size by hand):
> @@
> struct intel_memory_region *M;
> expression START, SIZE;
> @@
> - M->io_start = START;
> - M->io_size = SIZE;
> + M->io = DEFINE_RES_MEM(START, SIZE);
>
> @@
> struct intel_memory_region *M;
> @@
> - M->io_start
> + M->io.start
>
> @@
> struct intel_memory_region M;
> @@
> - M.io_start
> + M.io.start
>
> @@
> expression M;
> @@
> - M->io_size
> + resource_size(&M->io)
>
> @@
> expression M;
> @@
> - M.io_size
> + resource_size(&M.io)
>
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_fbdev_fb.c  |  2 +-
>   drivers/gpu/drm/i915/gem/i915_gem_region.c     |  2 +-
>   drivers/gpu/drm/i915/gem/i915_gem_stolen.c     | 17 +++++++++--------
>   drivers/gpu/drm/i915/gem/i915_gem_ttm.c        |  8 ++++----
>   .../gpu/drm/i915/gem/selftests/i915_gem_mman.c | 18 +++++++++---------
>   drivers/gpu/drm/i915/gt/intel_region_lmem.c    | 11 +++--------
>   drivers/gpu/drm/i915/gt/selftest_tlb.c         |  4 ++--
>   drivers/gpu/drm/i915/i915_gpu_error.c          |  2 +-
>   drivers/gpu/drm/i915/i915_query.c              |  2 +-
>   drivers/gpu/drm/i915/intel_memory_region.c     | 15 +++++++--------
>   drivers/gpu/drm/i915/intel_memory_region.h     |  3 +--
>   drivers/gpu/drm/i915/intel_region_ttm.c        |  8 ++++----
>   .../drm/i915/selftests/intel_memory_region.c   |  4 ++--
>   13 files changed, 45 insertions(+), 51 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
> index 717c3a3237c4..1ac05d90b2e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
> @@ -78,7 +78,7 @@ int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info
>   
>   		/* Use fbdev's framebuffer from lmem for discrete */
>   		info->fix.smem_start =
> -			(unsigned long)(mem->io_start +
> +			(unsigned long)(mem->io.start +
>   					i915_gem_object_get_dma_address(obj, 0));
>   		info->fix.smem_len = obj->base.size;
>   	} else {
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c
> index a4fb577eceb4..b09b74a2448b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
> @@ -129,7 +129,7 @@ i915_gem_object_create_region_at(struct intel_memory_region *mem,
>   		return ERR_PTR(-EINVAL);
>   
>   	if (!(flags & I915_BO_ALLOC_GPU_ONLY) &&
> -	    offset + size > mem->io_size &&
> +	    offset + size > resource_size(&mem->io) &&
>   	    !i915_ggtt_has_aperture(to_gt(mem->i915)->ggtt))
>   		return ERR_PTR(-ENOSPC);
>   
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 8c88075eeab2..d2440c793f84 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -541,7 +541,9 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
>   
>   	/* Exclude the reserved region from driver use */
>   	mem->region.end = i915->dsm.reserved.start - 1;
> -	mem->io_size = min(mem->io_size, resource_size(&mem->region));
> +	mem->io = DEFINE_RES_MEM(mem->io.start,
> +				 min(resource_size(&mem->io),
> +				     resource_size(&mem->region)));
>   
>   	i915->dsm.usable_size = resource_size(&mem->region);
>   
> @@ -752,7 +754,7 @@ static int _i915_gem_object_stolen_init(struct intel_memory_region *mem,
>   	 * With discrete devices, where we lack a mappable aperture there is no
>   	 * possible way to ever access this memory on the CPU side.
>   	 */
> -	if (mem->type == INTEL_MEMORY_STOLEN_LOCAL && !mem->io_size &&
> +	if (mem->type == INTEL_MEMORY_STOLEN_LOCAL && !resource_size(&mem->io) &&
>   	    !(flags & I915_BO_ALLOC_GPU_ONLY))
>   		return -ENOSPC;
>   
> @@ -838,13 +840,12 @@ static int init_stolen_lmem(struct intel_memory_region *mem)
>   		return 0;
>   	}
>   
> -	if (mem->io_size &&
> -	    !io_mapping_init_wc(&mem->iomap, mem->io_start, mem->io_size))
> +	if (resource_size(&mem->io) &&
> +	    !io_mapping_init_wc(&mem->iomap, mem->io.start, resource_size(&mem->io)))
>   		goto err_cleanup;
>   
> -	drm_dbg(&i915->drm, "Stolen Local memory IO start: %pa\n",
> -		&mem->io_start);
> -	drm_dbg(&i915->drm, "Stolen Local DSM base: %pa\n", &mem->region.start);
> +	drm_dbg(&i915->drm, "Stolen Local DSM: %pR\n", &mem->region);
> +	drm_dbg(&i915->drm, "Stolen Local memory IO: %pR\n", &mem->io);
>   
>   	return 0;
>   
> @@ -855,7 +856,7 @@ static int init_stolen_lmem(struct intel_memory_region *mem)
>   
>   static int release_stolen_lmem(struct intel_memory_region *mem)
>   {
> -	if (mem->io_size)
> +	if (resource_size(&mem->io))
>   		io_mapping_fini(&mem->iomap);
>   	i915_gem_cleanup_stolen(mem->i915);
>   	return 0;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> index 6b69ef0cdbb4..19467ff70ca9 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
> @@ -144,13 +144,13 @@ i915_ttm_place_from_region(const struct intel_memory_region *mr,
>   		place->fpfn = offset >> PAGE_SHIFT;
>   		WARN_ON(overflows_type(place->fpfn + (size >> PAGE_SHIFT), place->lpfn));
>   		place->lpfn = place->fpfn + (size >> PAGE_SHIFT);
> -	} else if (mr->io_size && mr->io_size < mr->total) {
> +	} else if (resource_size(&mr->io) && resource_size(&mr->io) < mr->total) {
>   		if (flags & I915_BO_ALLOC_GPU_ONLY) {
>   			place->flags |= TTM_PL_FLAG_TOPDOWN;
>   		} else {
>   			place->fpfn = 0;
> -			WARN_ON(overflows_type(mr->io_size >> PAGE_SHIFT, place->lpfn));
> -			place->lpfn = mr->io_size >> PAGE_SHIFT;
> +			WARN_ON(overflows_type(resource_size(&mr->io) >> PAGE_SHIFT, place->lpfn));
> +			place->lpfn = resource_size(&mr->io) >> PAGE_SHIFT;
>   		}
>   	}
>   }
> @@ -1090,7 +1090,7 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
>   			struct intel_memory_region *mr = obj->mm.placements[i];
>   			unsigned int flags;
>   
> -			if (!mr->io_size && mr->type != INTEL_MEMORY_SYSTEM)
> +			if (!resource_size(&mr->io) && mr->type != INTEL_MEMORY_SYSTEM)
>   				continue;
>   
>   			flags = obj->flags;
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> index 2c51a2c452fc..99a9ade73956 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
> @@ -1054,7 +1054,7 @@ static int igt_fill_mappable(struct intel_memory_region *mr,
>   	int err;
>   
>   	total = 0;
> -	size = mr->io_size;
> +	size = resource_size(&mr->io);
>   	do {
>   		struct drm_i915_gem_object *obj;
>   
> @@ -1315,28 +1315,28 @@ static int igt_mmap_migrate(void *arg)
>   		struct intel_memory_region *mixed[] = { mr, system };
>   		struct intel_memory_region *single[] = { mr };
>   		struct ttm_resource_manager *man = mr->region_private;
> -		resource_size_t saved_io_size;
> +		struct resource saved_io;
>   		int err;
>   
>   		if (mr->private)
>   			continue;
>   
> -		if (!mr->io_size)
> +		if (!resource_size(&mr->io))
>   			continue;
>   
>   		/*
>   		 * For testing purposes let's force small BAR, if not already
>   		 * present.
>   		 */
> -		saved_io_size = mr->io_size;
> -		if (mr->io_size == mr->total) {
> -			resource_size_t io_size = mr->io_size;
> +		saved_io = mr->io;
> +		if (resource_size(&mr->io) == mr->total) {
> +			resource_size_t io_size = resource_size(&mr->io);
>   
>   			io_size = rounddown_pow_of_two(io_size >> 1);
>   			if (io_size < PAGE_SIZE)
>   				continue;
>   
> -			mr->io_size = io_size;
> +			mr->io = DEFINE_RES_MEM(mr->io.start, io_size);
>   			i915_ttm_buddy_man_force_visible_size(man,
>   							      io_size >> PAGE_SHIFT);
>   		}
> @@ -1396,9 +1396,9 @@ static int igt_mmap_migrate(void *arg)
>   					 IGT_MMAP_MIGRATE_FAIL_GPU |
>   					 IGT_MMAP_MIGRATE_UNFAULTABLE);
>   out_io_size:
> -		mr->io_size = saved_io_size;
> +		mr->io = saved_io;
>   		i915_ttm_buddy_man_force_visible_size(man,
> -						      mr->io_size >> PAGE_SHIFT);
> +						      resource_size(&mr->io) >> PAGE_SHIFT);
>   		if (err)
>   			return err;
>   	}
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index f8512aee58a8..6f96a6b70601 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -144,8 +144,8 @@ region_lmem_init(struct intel_memory_region *mem)
>   	int ret;
>   
>   	if (!io_mapping_init_wc(&mem->iomap,
> -				mem->io_start,
> -				mem->io_size))
> +				mem->io.start,
> +				resource_size(&mem->io)))
>   		return -EIO;
>   
>   	ret = intel_region_ttm_init(mem);
> @@ -274,12 +274,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
>   		goto err_region_put;
>   
>   	drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region);
> -	drm_dbg(&i915->drm, "Local memory IO start: %pa\n",
> -		&mem->io_start);
> -	drm_info(&i915->drm, "Local memory IO size: %pa\n",
> -		 &mem->io_size);
> -	drm_info(&i915->drm, "Local memory available: %pa\n",
> -		 &lmem_size);
> +	drm_dbg(&i915->drm, "Local memory IO: %pR\n", &mem->io);
>   
>   	if (io_size < lmem_size)
>   		drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider enabling 'Resizable BAR' or similar, if available in the BIOS.\n",
> diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c b/drivers/gpu/drm/i915/gt/selftest_tlb.c
> index 00b872b6380b..3941f2d6fa47 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
> @@ -206,8 +206,8 @@ static struct drm_i915_gem_object *create_lmem(struct intel_gt *gt)
>   	 * of pages. To succeed with both allocations, especially in case of Small
>   	 * BAR, try to allocate no more than quarter of mappable memory.
>   	 */
> -	if (mr && size > mr->io_size / 4)
> -		size = mr->io_size / 4;
> +	if (mr && size > resource_size(&mr->io) / 4)
> +		size = resource_size(&mr->io) / 4;
>   
>   	return i915_gem_object_create_lmem(gt->i915, size, I915_BO_ALLOC_CONTIGUOUS);
>   }
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index d04660b60046..a0b784ebaddd 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -1157,7 +1157,7 @@ i915_vma_coredump_create(const struct intel_gt *gt,
>   			dma_addr_t offset = dma - mem->region.start;
>   			void __iomem *s;
>   
> -			if (offset + PAGE_SIZE > mem->io_size) {
> +			if (offset + PAGE_SIZE > resource_size(&mem->io)) {
>   				ret = -EINVAL;
>   				break;
>   			}
> diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
> index 00871ef99792..fa3e937ed3f5 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -502,7 +502,7 @@ static int query_memregion_info(struct drm_i915_private *i915,
>   		info.probed_size = mr->total;
>   
>   		if (mr->type == INTEL_MEMORY_LOCAL)
> -			info.probed_cpu_visible_size = mr->io_size;
> +			info.probed_cpu_visible_size = resource_size(&mr->io);
>   		else
>   			info.probed_cpu_visible_size = mr->total;
>   
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c
> index 60a03340bbd4..b2708f8cac2a 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/intel_memory_region.c
> @@ -50,7 +50,7 @@ static int __iopagetest(struct intel_memory_region *mem,
>   	if (memchr_inv(result, value, sizeof(result))) {
>   		dev_err(mem->i915->drm.dev,
>   			"Failed to read back from memory region:%pR at [%pa + %pa] for %ps; wrote %x, read (%x, %x, %x)\n",
> -			&mem->region, &mem->io_start, &offset, caller,
> +			&mem->region, &mem->io.start, &offset, caller,
>   			value, result[0], result[1], result[2]);
>   		return -EINVAL;
>   	}
> @@ -67,11 +67,11 @@ static int iopagetest(struct intel_memory_region *mem,
>   	int err;
>   	int i;
>   
> -	va = ioremap_wc(mem->io_start + offset, PAGE_SIZE);
> +	va = ioremap_wc(mem->io.start + offset, PAGE_SIZE);
>   	if (!va) {
>   		dev_err(mem->i915->drm.dev,
>   			"Failed to ioremap memory region [%pa + %pa] for %ps\n",
> -			&mem->io_start, &offset, caller);
> +			&mem->io.start, &offset, caller);
>   		return -EFAULT;
>   	}
>   
> @@ -102,10 +102,10 @@ static int iomemtest(struct intel_memory_region *mem,
>   	resource_size_t last, page;
>   	int err;
>   
> -	if (mem->io_size < PAGE_SIZE)
> +	if (resource_size(&mem->io) < PAGE_SIZE)
>   		return 0;
>   
> -	last = mem->io_size - PAGE_SIZE;
> +	last = resource_size(&mem->io) - PAGE_SIZE;
>   
>   	/*
>   	 * Quick test to check read/write access to the iomap (backing store).
> @@ -207,7 +207,7 @@ static int intel_memory_region_memtest(struct intel_memory_region *mem,
>   	struct drm_i915_private *i915 = mem->i915;
>   	int err = 0;
>   
> -	if (!mem->io_start)
> +	if (!mem->io.start)
>   		return 0;
>   
>   	if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM) || i915->params.memtest)
> @@ -252,8 +252,7 @@ intel_memory_region_create(struct drm_i915_private *i915,
>   
>   	mem->i915 = i915;
>   	mem->region = DEFINE_RES_MEM(start, size);
> -	mem->io_start = io_start;
> -	mem->io_size = io_size;
> +	mem->io = DEFINE_RES_MEM(io_start, io_size);
>   	mem->min_page_size = min_page_size;
>   	mem->ops = ops;
>   	mem->total = size;
> diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h
> index 9ba36454e51b..40810cfb3fd9 100644
> --- a/drivers/gpu/drm/i915/intel_memory_region.h
> +++ b/drivers/gpu/drm/i915/intel_memory_region.h
> @@ -71,8 +71,7 @@ struct intel_memory_region {
>   	struct io_mapping iomap;
>   	struct resource region;
>   
> -	resource_size_t io_start;
> -	resource_size_t io_size;
> +	struct resource io;
>   	resource_size_t min_page_size;
>   	resource_size_t total;
>   
> diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c b/drivers/gpu/drm/i915/intel_region_ttm.c
> index bf6097e7433d..04525d92bec5 100644
> --- a/drivers/gpu/drm/i915/intel_region_ttm.c
> +++ b/drivers/gpu/drm/i915/intel_region_ttm.c
> @@ -87,7 +87,7 @@ int intel_region_ttm_init(struct intel_memory_region *mem)
>   
>   	ret = i915_ttm_buddy_man_init(bdev, mem_type, false,
>   				      resource_size(&mem->region),
> -				      mem->io_size,
> +				      resource_size(&mem->io),
>   				      mem->min_page_size, PAGE_SIZE);
>   	if (ret)
>   		return ret;
> @@ -219,16 +219,16 @@ intel_region_ttm_resource_alloc(struct intel_memory_region *mem,
>   			goto out;
>   		}
>   		place.lpfn = place.fpfn + (size >> PAGE_SHIFT);
> -	} else if (mem->io_size && mem->io_size < mem->total) {
> +	} else if (resource_size(&mem->io) && resource_size(&mem->io) < mem->total) {
>   		if (flags & I915_BO_ALLOC_GPU_ONLY) {
>   			place.flags |= TTM_PL_FLAG_TOPDOWN;
>   		} else {
>   			place.fpfn = 0;
> -			if (WARN_ON(overflows_type(mem->io_size >> PAGE_SHIFT, place.lpfn))) {
> +			if (WARN_ON(overflows_type(resource_size(&mem->io) >> PAGE_SHIFT, place.lpfn))) {
>   				ret = -E2BIG;
>   				goto out;
>   			}
> -			place.lpfn = mem->io_size >> PAGE_SHIFT;
> +			place.lpfn = resource_size(&mem->io) >> PAGE_SHIFT;
>   		}
>   	}
>   
> diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> index d985d9bae2e8..ae6070b5bf07 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
> @@ -544,8 +544,8 @@ static u64 igt_object_mappable_total(struct drm_i915_gem_object *obj)
>   		u64 start = drm_buddy_block_offset(block);
>   		u64 end = start + drm_buddy_block_size(mm, block);
>   
> -		if (start < mr->io_size)
> -			total += min_t(u64, end, mr->io_size) - start;
> +		if (start < resource_size(&mr->io))
> +			total += min_t(u64, end, resource_size(&mr->io)) - start;
>   	}
>   
>   	return total;

Re: [PATCH v3 03/16] drm/i915: Remove ad-hoc lmem/stolen debugs

[Nirmoy Das]

On 1/16/2024 8:56 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that intel_memory_regions_hw_probe() prints out each and every
> memory region there's no reason to have ad-hoc debugs to do similar
> things elsewhere.
>
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   drivers/gpu/drm/i915/gem/i915_gem_stolen.c  | 4 ----
>   drivers/gpu/drm/i915/gt/intel_region_lmem.c | 3 ---
>   2 files changed, 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index d2440c793f84..ee237043c302 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -828,7 +828,6 @@ static const struct intel_memory_region_ops i915_region_stolen_smem_ops = {
>   
>   static int init_stolen_lmem(struct intel_memory_region *mem)
>   {
> -	struct drm_i915_private *i915 = mem->i915;
>   	int err;
>   
>   	if (GEM_WARN_ON(resource_size(&mem->region) == 0))
> @@ -844,9 +843,6 @@ static int init_stolen_lmem(struct intel_memory_region *mem)
>   	    !io_mapping_init_wc(&mem->iomap, mem->io.start, resource_size(&mem->io)))
>   		goto err_cleanup;
>   
> -	drm_dbg(&i915->drm, "Stolen Local DSM: %pR\n", &mem->region);
> -	drm_dbg(&i915->drm, "Stolen Local memory IO: %pR\n", &mem->io);
> -
>   	return 0;
>   
>   err_cleanup:
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index 6f96a6b70601..af357089da6e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -273,9 +273,6 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
>   	if (err)
>   		goto err_region_put;
>   
> -	drm_dbg(&i915->drm, "Local memory: %pR\n", &mem->region);
> -	drm_dbg(&i915->drm, "Local memory IO: %pR\n", &mem->io);
> -
>   	if (io_size < lmem_size)
>   		drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider enabling 'Resizable BAR' or similar, if available in the BIOS.\n",
>   			 (u64)io_size >> 20);

Re: [PATCH v3 04/16] drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory access

[Nirmoy Das]

[-- Attachment #1: Type: text/plain, Size: 4141 bytes --]


On 1/16/2024 8:56 AM, Ville Syrjala wrote:
> From: Ville Syrjälä<ville.syrjala@linux.intel.com>
>
> On MTL accessing stolen memory via the BARs is somehow borked,
> and it can hang the machine. As a workaround let's bypass the
> BARs and just go straight to DSMBASE/GSMBASE instead.
>
> Note that on every other platform this itself would hang the
> machine, but on MTL the system firmware is expected to relax
> the access permission guarding stolen memory to enable this
> workaround, and thus direct CPU accesses should be fine.
>
> The raw stolen memory areas won't be passed to VMs so we'll
> need to risk using the BAR there for the initial setup. Once
> command submission is up we should switch to MI_UPDATE_GTT
> which at least shouldn't hang the whole machine.
>
> v2: Don't use direct GSM/DSM access on guests
>      Add w/a number
>
> Cc: Paz Zcharya<pazz@chromium.org>
> Cc: Nirmoy Das<nirmoy.das@intel.com>
> Cc: Joonas Lahtinen<joonas.lahtinen@linux.intel.com>
> Reviewed-by: Andrzej Hajda<andrzej.hajda@intel.com>
> Reviewed-by: Radhakrishna Sripada<radhakrishna.sripada@intel.com>
> Signed-off-by: Ville Syrjälä<ville.syrjala@linux.intel.com>

I think i915_run_as_guest() should work.

Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>

> ---
>   drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 14 +++++++++++++-
>   drivers/gpu/drm/i915/gt/intel_ggtt.c       | 16 +++++++++++++++-
>   2 files changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index ee237043c302..0b429f1ecd99 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -941,7 +941,19 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>   		dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
>   	}
>   
> -	if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
> +	if (IS_METEORLAKE(i915) && !i915_run_as_guest()) {
> +		/*
> +		 * Wa_22018444074
> +		 *
> +		 * Access via BAR can hang MTL, go directly to DSM,
> +		 * except for VM guests which won't have access to it.
> +		 *
> +		 * Normally this would not work but on MTL the system firmware
> +		 * should have relaxed the access permissions sufficiently.
> +		 */
> +		io_start = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
> +		io_size = dsm_size;
> +	} else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
>   		io_start = 0;
>   		io_size = 0;
>   	} else {
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 21a7e3191c18..7a716ff16070 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -24,6 +24,7 @@
>   #include "intel_ring.h"
>   #include "i915_drv.h"
>   #include "i915_pci.h"
> +#include "i915_reg.h"
>   #include "i915_request.h"
>   #include "i915_scatterlist.h"
>   #include "i915_utils.h"
> @@ -1152,13 +1153,26 @@ static unsigned int gen6_gttadr_offset(struct drm_i915_private *i915)
>   static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
>   {
>   	struct drm_i915_private *i915 = ggtt->vm.i915;
> +	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
>   	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>   	phys_addr_t phys_addr;
>   	u32 pte_flags;
>   	int ret;
>   
>   	GEM_WARN_ON(pci_resource_len(pdev, GEN4_GTTMMADR_BAR) != gen6_gttmmadr_size(i915));
> -	phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
> +	/*
> +	 * Wa_22018444074
> +	 *
> +	 * Access via BAR can hang MTL, go directly to GSM,
> +	 * except for VM guests which won't have access to it.
> +	 *
> +	 * Normally this would not work but on MTL the system firmware
> +	 * should have relaxed the access permissions sufficiently.
> +	 */
> +	if (IS_METEORLAKE(i915) && !i915_run_as_guest())
> +		phys_addr = intel_uncore_read64(uncore, GEN12_GSMBASE) & GEN12_BDSM_MASK;
> +	else
> +		phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
>   
>   	if (needs_wc_ggtt_mapping(i915))
>   		ggtt->gsm = ioremap_wc(phys_addr, size);

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Re: [PATCH v3 05/16] drm/i915: Disable the "binder"

[Nirmoy Das]

On 1/16/2024 8:56 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that the GGTT PTE updates go straight to GSMBASE (bypassing
> GTTMMADR) there should be no more risk of system hangs? So the
> "binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
> necessary, disable it.
>
> My main worry with the MI_UPDATE_GTT are:
> - only used on this one platform so very limited testing coverage
> - async so more opprtunities to screw things up
> - what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
>    to finish?
> - requires working command submission, so even getting a working
>    display now depends on a lot more extra components working correctly
>
> TODO: MI_UPDATE_GTT might be interesting as an optimization
> though, so perhaps someone should look into always using it
> (assuming the GPU is alive and well)?
>
> v2: Keep using MI_UPDATE_GTT on VM guests
>
> Cc: Paz Zcharya <pazz@chromium.org>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>

> ---
>   drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 86f73fe558ca..e83dabc56a14 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -24,7 +24,8 @@
>   bool i915_ggtt_require_binder(struct drm_i915_private *i915)
>   {
>   	/* Wa_13010847436 & Wa_14019519902 */
> -	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> +	return i915_run_as_guest() &&
> +		MEDIA_VER_FULL(i915) == IP_VER(13, 0);
>   }
>   
>   static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)

Re: [PATCH v3 06/16] drm/i915: Rename the DSM/GSM registers

[Nirmoy Das]

On 1/16/2024 8:56 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> 0x108100 and 0x1080c0 have been around since snb. Rename the
> defines appropriately.
>
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   drivers/gpu/drm/i915/gem/i915_gem_stolen.c  | 4 ++--
>   drivers/gpu/drm/i915/gt/intel_ggtt.c        | 2 +-
>   drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +-
>   drivers/gpu/drm/i915/i915_reg.h             | 7 ++++---
>   4 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 0b429f1ecd99..ce6b860b393e 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -935,7 +935,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>   		GEM_BUG_ON((dsm_base + dsm_size) > lmem_size);
>   	} else {
>   		/* Use DSM base address instead for stolen memory */
> -		dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
> +		dsm_base = intel_uncore_read64(uncore, GEN6_DSMBASE) & GEN11_BDSM_MASK;
>   		if (WARN_ON(lmem_size < dsm_base))
>   			return ERR_PTR(-ENODEV);
>   		dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
> @@ -951,7 +951,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>   		 * Normally this would not work but on MTL the system firmware
>   		 * should have relaxed the access permissions sufficiently.
>   		 */
> -		io_start = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
> +		io_start = intel_uncore_read64(uncore, GEN6_DSMBASE) & GEN11_BDSM_MASK;
>   		io_size = dsm_size;
>   	} else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
>   		io_start = 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 7a716ff16070..b87933e7671d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -1170,7 +1170,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
>   	 * should have relaxed the access permissions sufficiently.
>   	 */
>   	if (IS_METEORLAKE(i915) && !i915_run_as_guest())
> -		phys_addr = intel_uncore_read64(uncore, GEN12_GSMBASE) & GEN12_BDSM_MASK;
> +		phys_addr = intel_uncore_read64(uncore, GEN6_GSMBASE) & GEN11_BDSM_MASK;
>   	else
>   		phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
>   
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index af357089da6e..51bb27e10a4f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -240,7 +240,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
>   		lmem_size -= tile_stolen;
>   	} else {
>   		/* Stolen starts from GSMBASE without CCS */
> -		lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
> +		lmem_size = intel_uncore_read64(&i915->uncore, GEN6_GSMBASE);
>   	}
>   
>   	i915_resize_lmem_bar(i915, lmem_size);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 75bc08081fce..0d35173a7718 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6320,9 +6320,10 @@ enum skl_power_gate {
>   #define   GMS_MASK			REG_GENMASK(15, 8)
>   #define   GGMS_MASK			REG_GENMASK(7, 6)
>   
> -#define GEN12_GSMBASE			_MMIO(0x108100)
> -#define GEN12_DSMBASE			_MMIO(0x1080C0)
> -#define   GEN12_BDSM_MASK		REG_GENMASK64(63, 20)
> +#define GEN6_GSMBASE			_MMIO(0x108100)
> +#define GEN6_DSMBASE			_MMIO(0x1080C0)
> +#define   GEN6_BDSM_MASK		REG_GENMASK64(31, 20)
> +#define   GEN11_BDSM_MASK		REG_GENMASK64(63, 20)
>   
>   #define XEHP_CLOCK_GATE_DIS		_MMIO(0x101014)
>   #define   SGSI_SIDECLK_DIS		REG_BIT(17)

Re: [PATCH v3 07/16] drm/i915: Fix PTE decode during initial plane readout

[Nirmoy Das]

On 1/16/2024 8:56 AM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> When multiple pipes are enabled by the BIOS we try to read out each
> in turn. But we do the readout for the second only after the inherited
> vma for the first has been rebound into its original place (and thus
> the PTEs have been rewritten). Unlike the BIOS we set some high caching
> bits in the PTE on MTL which confuses the readout for the second plane.
> Filter out the non-address bits from the PTE value appropriately to
> fix this.
>
> I suppose it might also be possible that the BIOS would already set
> some caching bits as well, in which case we'd run into this same
> issue already for the first plane.
>
> TODO:
> - should abstract the PTE decoding to avoid details leaking all over
> - should probably do the readout for all the planes before
>    we touch anything (including the PTEs) so that we truly read
>    out the BIOS state
>
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index a55c09cbd0e4..ffc92b18fcf5 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -72,7 +72,7 @@ initial_plane_vma(struct drm_i915_private *i915,
>   			return NULL;
>   		}
>   
> -		phys_base = pte & I915_GTT_PAGE_MASK;
> +		phys_base = pte & GEN12_GGTT_PTE_ADDR_MASK;
>   		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
>   
>   		/*

Re: [PATCH v3 05/16] drm/i915: Disable the "binder"

[Michał Winiarski]

On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Now that the GGTT PTE updates go straight to GSMBASE (bypassing
> GTTMMADR) there should be no more risk of system hangs? So the
> "binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
> necessary, disable it.
> 
> My main worry with the MI_UPDATE_GTT are:
> - only used on this one platform so very limited testing coverage
> - async so more opprtunities to screw things up
> - what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
>   to finish?
> - requires working command submission, so even getting a working
>   display now depends on a lot more extra components working correctly
> 
> TODO: MI_UPDATE_GTT might be interesting as an optimization
> though, so perhaps someone should look into always using it
> (assuming the GPU is alive and well)?
> 
> v2: Keep using MI_UPDATE_GTT on VM guests
> 
> Cc: Paz Zcharya <pazz@chromium.org>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 86f73fe558ca..e83dabc56a14 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -24,7 +24,8 @@
>  bool i915_ggtt_require_binder(struct drm_i915_private *i915)
>  {
>  	/* Wa_13010847436 & Wa_14019519902 */
> -	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> +	return i915_run_as_guest() &&
> +		MEDIA_VER_FULL(i915) == IP_VER(13, 0);

Note that i915_run_as_guest() is not the most reliable way to decide
whether to use MI_UPDATE_GTT or straight to GSMBASE, as it requires the
hypervisor to "opt-in" and set the X86_FEATURE_HYPERVISOR.
If it's not set - the driver will go into GSMBASE, which is not mapped
inside the guest.
Does the system firmware advertise whether GSMBASE is "open" or "closed"
to CPU access in any way?

-Michał

>  }
>  
>  static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
> -- 
> 2.41.0
> 

✗ Fi.CI.CHECKPATCH: warning for drm/i915: (stolen) memory region related fixes (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: (stolen) memory region related fixes (rev7)
URL   : https://patchwork.freedesktop.org/series/127721/
State : warning

== Summary ==

Error: dim checkpatch failed
420bd052296b drm/i915: Use struct resource for memory region IO as well
-:388: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#388: FILE: drivers/gpu/drm/i915/intel_region_ttm.c:227:
+			if (WARN_ON(overflows_type(resource_size(&mem->io) >> PAGE_SHIFT, place.lpfn))) {

total: 0 errors, 1 warnings, 0 checks, 281 lines checked
36939988182b drm/i915: Print memory region info during probe
b068f5dd348b drm/i915: Remove ad-hoc lmem/stolen debugs
5c3f5c028395 drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory access
9d4356c8b4f9 drm/i915: Disable the "binder"
eeeddbd1c219 drm/i915: Rename the DSM/GSM registers
0f97740ee08d drm/i915: Fix PTE decode during initial plane readout
3e1f008c0575 drm/i915: Fix region start during initial plane readout
376b52c85c46 drm/i915: Fix MTL initial plane readout
9d7013c0a8a2 drm/i915: s/phys_base/dma_addr/
ad263486e9a0 drm/i915: Split the smem and lmem plane readout apart
3ae104619d2c drm/i915: Simplify intel_initial_plane_config() calling convention
4fe3e6f3e4ec drm/i915/fbdev: Fix smem_start for LMEMBAR stolen objects
e1f6060ee679 drm/i915: Tweak BIOS fb reuse check
0e59c24c2a0a drm/i915: Try to relocate the BIOS fb to the start of ggtt
-:104: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#104: FILE: drivers/gpu/drm/i915/display/i9xx_plane.h:51:
 }
+static inline bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,

-:105: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#105: FILE: drivers/gpu/drm/i915/display/i9xx_plane.h:52:
+						   const struct intel_initial_plane_config *plane_config)

total: 0 errors, 1 warnings, 1 checks, 229 lines checked
d5cdc16e4e91 drm/i915: Annotate more of the BIOS fb takeover failure paths

✗ Fi.CI.SPARSE: warning for drm/i915: (stolen) memory region related fixes (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915: (stolen) memory region related fixes (rev7)
URL   : https://patchwork.freedesktop.org/series/127721/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ Fi.CI.BAT: failure for drm/i915: (stolen) memory region related fixes (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 10037 bytes --]

== Series Details ==

Series: drm/i915: (stolen) memory region related fixes (rev7)
URL   : https://patchwork.freedesktop.org/series/127721/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14132 -> Patchwork_127721v7
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_127721v7 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_127721v7, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/index.html

Participating hosts (38 -> 37)
------------------------------

  Additional (1): bat-mtlp-8 
  Missing    (2): fi-snb-2520m fi-pnv-d510 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_127721v7:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1:
    - bat-dg2-8:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14132/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-dg2-8/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-1.html

  
Known issues
------------

  Here are the changes found in Patchwork_127721v7 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-mtlp-8:         NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - bat-jsl-3:          [PASS][4] -> [INCOMPLETE][5] ([i915#9883])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14132/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-jsl-3/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-mtlp-8:         NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_mmap@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][7] ([i915#4083])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][8] ([i915#4077]) +2 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@gem_mmap_gtt@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][9] ([i915#4079]) +1 other test skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-mtlp-8:         NOTRUN -> [SKIP][10] ([i915#6621])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@i915_pm_rps@basic-api.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - fi-bsw-nick:        [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14132/fi-bsw-nick/igt@i915_suspend@basic-s2idle-without-i915.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/fi-bsw-nick/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-jsl-3:          [PASS][13] -> [FAIL][14] ([i915#10031])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14132/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-jsl-3/igt@i915_suspend@basic-s3-without-i915.html
    - bat-mtlp-8:         NOTRUN -> [SKIP][15] ([i915#6645])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][16] ([i915#5190])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@basic-y-tiled-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][17] ([i915#4212]) +8 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-mtlp-8:         NOTRUN -> [SKIP][18] ([i915#4213]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-mtlp-8:         NOTRUN -> [SKIP][19] ([i915#3555] / [i915#3840] / [i915#9159])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-mtlp-8:         NOTRUN -> [SKIP][20] ([fdo#109285])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_force_connector_basic@prune-stale-modes:
    - bat-mtlp-8:         NOTRUN -> [SKIP][21] ([i915#5274])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-mtlp-8:         NOTRUN -> [SKIP][22] ([i915#3555] / [i915#8809])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-mmap:
    - bat-mtlp-8:         NOTRUN -> [SKIP][23] ([i915#3708] / [i915#4077]) +1 other test skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
    - bat-mtlp-8:         NOTRUN -> [SKIP][24] ([i915#3708]) +2 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html

  
#### Possible fixes ####

  * igt@i915_suspend@basic-s3-without-i915:
    - bat-rpls-2:         [ABORT][25] ([i915#7978]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14132/bat-rpls-2/igt@i915_suspend@basic-s3-without-i915.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/bat-rpls-2/igt@i915_suspend@basic-s3-without-i915.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [i915#10031]: https://gitlab.freedesktop.org/drm/intel/issues/10031
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
  [i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
  [i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9688]: https://gitlab.freedesktop.org/drm/intel/issues/9688
  [i915#9883]: https://gitlab.freedesktop.org/drm/intel/issues/9883


Build changes
-------------

  * Linux: CI_DRM_14132 -> Patchwork_127721v7

  CI-20190529: 20190529
  CI_DRM_14132: b42f47ca5fff1d04fb8eb02d64520b3f338a495d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7677: 57ed393a5b5d04e985f9950a7f1546fc95f4001e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_127721v7: b42f47ca5fff1d04fb8eb02d64520b3f338a495d @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

10732511b3af drm/i915: Annotate more of the BIOS fb takeover failure paths
ed20563d80cb drm/i915: Try to relocate the BIOS fb to the start of ggtt
65075bcd22d7 drm/i915: Tweak BIOS fb reuse check
99fd51007d5e drm/i915/fbdev: Fix smem_start for LMEMBAR stolen objects
e123bb2d9cf9 drm/i915: Simplify intel_initial_plane_config() calling convention
c9343983e002 drm/i915: Split the smem and lmem plane readout apart
e9d6b14a3106 drm/i915: s/phys_base/dma_addr/
9cceedc5e40c drm/i915: Fix MTL initial plane readout
daa76d988885 drm/i915: Fix region start during initial plane readout
1915f70ada61 drm/i915: Fix PTE decode during initial plane readout
5da5d41ec987 drm/i915: Rename the DSM/GSM registers
02bebfc83861 drm/i915: Disable the "binder"
ff8bef18990f drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory access
265719f28e3c drm/i915: Remove ad-hoc lmem/stolen debugs
fbc8fa9d6405 drm/i915: Print memory region info during probe
c1f1a241f295 drm/i915: Use struct resource for memory region IO as well

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v7/index.html

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Re: [PATCH v3 05/16] drm/i915: Disable the "binder"

[Nirmoy Das]

On 1/17/2024 3:13 PM, Michał Winiarski wrote:
> On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Now that the GGTT PTE updates go straight to GSMBASE (bypassing
>> GTTMMADR) there should be no more risk of system hangs? So the
>> "binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
>> necessary, disable it.
>>
>> My main worry with the MI_UPDATE_GTT are:
>> - only used on this one platform so very limited testing coverage
>> - async so more opprtunities to screw things up
>> - what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
>>    to finish?
>> - requires working command submission, so even getting a working
>>    display now depends on a lot more extra components working correctly
>>
>> TODO: MI_UPDATE_GTT might be interesting as an optimization
>> though, so perhaps someone should look into always using it
>> (assuming the GPU is alive and well)?
>>
>> v2: Keep using MI_UPDATE_GTT on VM guests
>>
>> Cc: Paz Zcharya <pazz@chromium.org>
>> Cc: Nirmoy Das <nirmoy.das@intel.com>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> index 86f73fe558ca..e83dabc56a14 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
>> @@ -24,7 +24,8 @@
>>   bool i915_ggtt_require_binder(struct drm_i915_private *i915)
>>   {
>>   	/* Wa_13010847436 & Wa_14019519902 */
>> -	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
>> +	return i915_run_as_guest() &&
>> +		MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> Note that i915_run_as_guest() is not the most reliable way to decide
> whether to use MI_UPDATE_GTT or straight to GSMBASE, as it requires the
> hypervisor to "opt-in" and set the X86_FEATURE_HYPERVISOR.
> If it's not set - the driver will go into GSMBASE, which is not mapped
> inside the guest.
> Does the system firmware advertise whether GSMBASE is "open" or "closed"
> to CPU access in any way?

Had a chat with David from IVE team, David suggested to read 0x138914 to 
determine that.  "GOP needs to qualify the WA by reading GFX MMIO offset 
0x138914 and verify the value there is 0x1." -> as per the HSD-22018444074



Regards,

Nirmoy

>
> -Michał
>
>>   }
>>   
>>   static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
>> -- 
>> 2.41.0
>>

Re: [PATCH v3 05/16] drm/i915: Disable the "binder"

[Ville Syrjälä]

On Wed, Jan 17, 2024 at 06:46:24PM +0100, Nirmoy Das wrote:
> 
> On 1/17/2024 3:13 PM, Michał Winiarski wrote:
> > On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
> >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >>
> >> Now that the GGTT PTE updates go straight to GSMBASE (bypassing
> >> GTTMMADR) there should be no more risk of system hangs? So the
> >> "binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
> >> necessary, disable it.
> >>
> >> My main worry with the MI_UPDATE_GTT are:
> >> - only used on this one platform so very limited testing coverage
> >> - async so more opprtunities to screw things up
> >> - what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
> >>    to finish?
> >> - requires working command submission, so even getting a working
> >>    display now depends on a lot more extra components working correctly
> >>
> >> TODO: MI_UPDATE_GTT might be interesting as an optimization
> >> though, so perhaps someone should look into always using it
> >> (assuming the GPU is alive and well)?
> >>
> >> v2: Keep using MI_UPDATE_GTT on VM guests
> >>
> >> Cc: Paz Zcharya <pazz@chromium.org>
> >> Cc: Nirmoy Das <nirmoy.das@intel.com>
> >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
> >>   1 file changed, 2 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> >> index 86f73fe558ca..e83dabc56a14 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> >> @@ -24,7 +24,8 @@
> >>   bool i915_ggtt_require_binder(struct drm_i915_private *i915)
> >>   {
> >>   	/* Wa_13010847436 & Wa_14019519902 */
> >> -	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> >> +	return i915_run_as_guest() &&
> >> +		MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> > Note that i915_run_as_guest() is not the most reliable way to decide
> > whether to use MI_UPDATE_GTT or straight to GSMBASE, as it requires the
> > hypervisor to "opt-in" and set the X86_FEATURE_HYPERVISOR.
> > If it's not set - the driver will go into GSMBASE, which is not mapped
> > inside the guest.
> > Does the system firmware advertise whether GSMBASE is "open" or "closed"
> > to CPU access in any way?
> 
> Had a chat with David from IVE team, David suggested to read 0x138914 to 
> determine that.  "GOP needs to qualify the WA by reading GFX MMIO offset 
> 0x138914 and verify the value there is 0x1." -> as per the HSD-22018444074

OK, so we can confirm the firmware is on board. I suppose no real harm
in doing so even though it would clearly be a rather weird if someone
would ship some ancient firmware that doesn't handle this.

But that still won't help with the guest side handling because that
register will read the same in the guest.

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 05/16] drm/i915: Disable the "binder"

[Nirmoy Das]

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On 1/19/2024 12:12 AM, Ville Syrjälä wrote:
> On Wed, Jan 17, 2024 at 06:46:24PM +0100, Nirmoy Das wrote:
>> On 1/17/2024 3:13 PM, Michał Winiarski wrote:
>>> On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
>>>> From: Ville Syrjälä<ville.syrjala@linux.intel.com>
>>>>
>>>> Now that the GGTT PTE updates go straight to GSMBASE (bypassing
>>>> GTTMMADR) there should be no more risk of system hangs? So the
>>>> "binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
>>>> necessary, disable it.
>>>>
>>>> My main worry with the MI_UPDATE_GTT are:
>>>> - only used on this one platform so very limited testing coverage
>>>> - async so more opprtunities to screw things up
>>>> - what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
>>>>     to finish?
>>>> - requires working command submission, so even getting a working
>>>>     display now depends on a lot more extra components working correctly
>>>>
>>>> TODO: MI_UPDATE_GTT might be interesting as an optimization
>>>> though, so perhaps someone should look into always using it
>>>> (assuming the GPU is alive and well)?
>>>>
>>>> v2: Keep using MI_UPDATE_GTT on VM guests
>>>>
>>>> Cc: Paz Zcharya<pazz@chromium.org>
>>>> Cc: Nirmoy Das<nirmoy.das@intel.com>
>>>> Signed-off-by: Ville Syrjälä<ville.syrjala@linux.intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
>>>>    1 file changed, 2 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
>>>> index 86f73fe558ca..e83dabc56a14 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
>>>> @@ -24,7 +24,8 @@
>>>>    bool i915_ggtt_require_binder(struct drm_i915_private *i915)
>>>>    {
>>>>    	/* Wa_13010847436 & Wa_14019519902 */
>>>> -	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
>>>> +	return i915_run_as_guest() &&
>>>> +		MEDIA_VER_FULL(i915) == IP_VER(13, 0);
>>> Note that i915_run_as_guest() is not the most reliable way to decide
>>> whether to use MI_UPDATE_GTT or straight to GSMBASE, as it requires the
>>> hypervisor to "opt-in" and set the X86_FEATURE_HYPERVISOR.
>>> If it's not set - the driver will go into GSMBASE, which is not mapped
>>> inside the guest.
>>> Does the system firmware advertise whether GSMBASE is "open" or "closed"
>>> to CPU access in any way?
>> Had a chat with David from IVE team, David suggested to read 0x138914 to
>> determine that.  "GOP needs to qualify the WA by reading GFX MMIO offset
>> 0x138914 and verify the value there is 0x1." -> as per the HSD-22018444074
> OK, so we can confirm the firmware is on board. I suppose no real harm
> in doing so even though it would clearly be a rather weird if someone
> would ship some ancient firmware that doesn't handle this.
>
> But that still won't help with the guest side handling because that
> register will read the same in the guest.


We are back to the same question :/ How about
if (boot_cpu_has(X86_FEATURE_HYPERVISOR) && !i915_run_as_guest()

disable binder

Regards,

Nirmoy

>

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Re: [PATCH v3 05/16] drm/i915: Disable the "binder"

[Nirmoy Das]

[-- Attachment #1: Type: text/plain, Size: 3237 bytes --]


On 1/19/2024 11:47 AM, Nirmoy Das wrote:
>
>
> On 1/19/2024 12:12 AM, Ville Syrjälä wrote:
>> On Wed, Jan 17, 2024 at 06:46:24PM +0100, Nirmoy Das wrote:
>>> On 1/17/2024 3:13 PM, Michał Winiarski wrote:
>>>> On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
>>>>> From: Ville Syrjälä<ville.syrjala@linux.intel.com>
>>>>>
>>>>> Now that the GGTT PTE updates go straight to GSMBASE (bypassing
>>>>> GTTMMADR) there should be no more risk of system hangs? So the
>>>>> "binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
>>>>> necessary, disable it.
>>>>>
>>>>> My main worry with the MI_UPDATE_GTT are:
>>>>> - only used on this one platform so very limited testing coverage
>>>>> - async so more opprtunities to screw things up
>>>>> - what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
>>>>>     to finish?
>>>>> - requires working command submission, so even getting a working
>>>>>     display now depends on a lot more extra components working correctly
>>>>>
>>>>> TODO: MI_UPDATE_GTT might be interesting as an optimization
>>>>> though, so perhaps someone should look into always using it
>>>>> (assuming the GPU is alive and well)?
>>>>>
>>>>> v2: Keep using MI_UPDATE_GTT on VM guests
>>>>>
>>>>> Cc: Paz Zcharya<pazz@chromium.org>
>>>>> Cc: Nirmoy Das<nirmoy.das@intel.com>
>>>>> Signed-off-by: Ville Syrjälä<ville.syrjala@linux.intel.com>
>>>>> ---
>>>>>    drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
>>>>>    1 file changed, 2 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
>>>>> index 86f73fe558ca..e83dabc56a14 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
>>>>> @@ -24,7 +24,8 @@
>>>>>    bool i915_ggtt_require_binder(struct drm_i915_private *i915)
>>>>>    {
>>>>>    	/* Wa_13010847436 & Wa_14019519902 */
>>>>> -	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
>>>>> +	return i915_run_as_guest() &&
>>>>> +		MEDIA_VER_FULL(i915) == IP_VER(13, 0);
>>>> Note that i915_run_as_guest() is not the most reliable way to decide
>>>> whether to use MI_UPDATE_GTT or straight to GSMBASE, as it requires the
>>>> hypervisor to "opt-in" and set the X86_FEATURE_HYPERVISOR.
>>>> If it's not set - the driver will go into GSMBASE, which is not mapped
>>>> inside the guest.
>>>> Does the system firmware advertise whether GSMBASE is "open" or "closed"
>>>> to CPU access in any way?
>>> Had a chat with David from IVE team, David suggested to read 0x138914 to
>>> determine that.  "GOP needs to qualify the WA by reading GFX MMIO offset
>>> 0x138914 and verify the value there is 0x1." -> as per the HSD-22018444074
>> OK, so we can confirm the firmware is on board. I suppose no real harm
>> in doing so even though it would clearly be a rather weird if someone
>> would ship some ancient firmware that doesn't handle this.
>>
>> But that still won't help with the guest side handling because that
>> register will read the same in the guest.
>
>
> We are back to the same question :/ How about
> if (boot_cpu_has(X86_FEATURE_HYPERVISOR) && !i915_run_as_guest()
>
hmm, never mind that was stupid.


> disable binder
>
> Regards,
>
> Nirmoy
>

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RE: [PATCH v3 08/16] drm/i915: Fix region start during initial plane readout

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Tuesday, January 16, 2024 1:26 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH v3 08/16] drm/i915: Fix region start during initial plane readout
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On MTL the stolen region starts at offset 8MiB from the start of LMEMBAR. The
> dma addresses are thus also offset by 8MiB. However the mm_node/etc. is zero
> based, and i915_pages_create_for_stolen() will add the appropriate region.start
> into the sg dma address. So when we do the readout we need to convert the dma
> address read from the PTE to be zero based as well.
> 
> Note that currently we don't take this path on MTL, but we should and thus this
> needs to be fixed. For lmem this works correctly already as the lmem
> region.start==0.
> 
> While at it let's also make sure the address points to somewhere within the
> memory region. We don't need to check the size as
> i915_gem_object_create_region_at() should later fail if the object size exceeds
> the region size.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Cc: Paz Zcharya <pazz@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_plane_initial.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index ffc92b18fcf5..db594ccf0323 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -79,16 +79,18 @@ initial_plane_vma(struct drm_i915_private *i915,
>  		 * We don't currently expect this to ever be placed in the
>  		 * stolen portion.
>  		 */
> -		if (phys_base >= resource_size(&mem->region)) {
> +		if (phys_base < mem->region.start || phys_base > mem-
> >region.end) {
>  			drm_err(&i915->drm,
> -				"Initial plane programming using invalid range,
> phys_base=%pa\n",
> -				&phys_base);
> +				"Initial plane programming using invalid range,
> phys_base=%pa (%s [%pa-%pa])\n",
> +				&phys_base, mem->region.name, &mem-
> >region.start,
> +&mem->region.end);
>  			return NULL;
>  		}
> 
>  		drm_dbg(&i915->drm,
>  			"Using phys_base=%pa, based on initial plane
> programming\n",
>  			&phys_base);
> +
> +		phys_base -= mem->region.start;
>  	} else {
>  		phys_base = base;
>  		mem = i915->mm.stolen_region;
> --
> 2.41.0

RE: [PATCH v3 09/16] drm/i915: Fix MTL initial plane readout

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Tuesday, January 16, 2024 1:26 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH v3 09/16] drm/i915: Fix MTL initial plane readout
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> MTL stolen memory looks more like local memory, so use the (now fixed) lmem
> path when doing the initial plane readout.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Cc: Paz Zcharya <pazz@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../drm/i915/display/intel_plane_initial.c    | 25 +++++++++++++------
>  1 file changed, 18 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index db594ccf0323..c72d4cacf631 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -59,7 +59,7 @@ initial_plane_vma(struct drm_i915_private *i915,
>  		return NULL;
> 
>  	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
> -	if (IS_DGFX(i915)) {
> +	if (IS_DGFX(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915)) {
>  		gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
>  		gen8_pte_t pte;
> 
> @@ -73,11 +73,20 @@ initial_plane_vma(struct drm_i915_private *i915,
>  		}
> 
>  		phys_base = pte & GEN12_GGTT_PTE_ADDR_MASK;
> -		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
> +
> +		if (IS_DGFX(i915))
> +			mem = i915->mm.regions[INTEL_REGION_LMEM_0];
> +		else
> +			mem = i915->mm.stolen_region;
> +		if (!mem) {
> +			drm_dbg_kms(&i915->drm,
> +				    "Initial plane memory region not
> initialized\n");
> +			return NULL;
> +		}
> 
>  		/*
> -		 * We don't currently expect this to ever be placed in the
> -		 * stolen portion.
> +		 * On lmem we don't currently expect this to
> +		 * ever be placed in the stolen portion.
>  		 */
>  		if (phys_base < mem->region.start || phys_base > mem-
> >region.end) {
>  			drm_err(&i915->drm,
> @@ -94,11 +103,13 @@ initial_plane_vma(struct drm_i915_private *i915,
>  	} else {
>  		phys_base = base;
>  		mem = i915->mm.stolen_region;
> +		if (!mem) {
> +			drm_dbg_kms(&i915->drm,
> +				    "Initial plane memory region not
> initialized\n");
> +			return NULL;
> +		}
>  	}
> 
> -	if (!mem)
> -		return NULL;
> -
>  	size = round_up(plane_config->base + plane_config->size,
>  			mem->min_page_size);
>  	size -= base;
> --
> 2.41.0

RE: [PATCH v3 16/16] drm/i915: Annotate more of the BIOS fb takeover failure paths

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Tuesday, January 16, 2024 1:27 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [PATCH v3 16/16] drm/i915: Annotate more of the BIOS fb takeover
> failure paths
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Annotate a few more of the failure paths on the initial BIOS fb takeover to avoid
> having to guess why things aren't working the way we expect.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_plane_initial.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index 00e194ee129a..d9a356d5661b 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -167,14 +167,19 @@ initial_plane_vma(struct drm_i915_private *i915,
>  	 */
>  	if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
>  	    mem == i915->mm.stolen_region &&
> -	    size * 2 > i915->dsm.usable_size)
> +	    size * 2 > i915->dsm.usable_size) {
> +		drm_dbg_kms(&i915->drm, "Initial FB size exceeds half of stolen,
> +discarding\n");
>  		return NULL;
> +	}
> 
>  	obj = i915_gem_object_create_region_at(mem, phys_base, size,
>  					       I915_BO_ALLOC_USER |
>  					       I915_BO_PREALLOC);
> -	if (IS_ERR(obj))
> +	if (IS_ERR(obj)) {
> +		drm_dbg_kms(&i915->drm, "Failed to preallocate initial FB in
> %s\n",
> +			    mem->region.name);
>  		return NULL;
> +	}
> 
>  	/*
>  	 * Mark it WT ahead of time to avoid changing the
> --
> 2.41.0

Re: [PATCH v3 05/16] drm/i915: Disable the "binder"

[Ville Syrjälä]

On Fri, Jan 19, 2024 at 01:12:11AM +0200, Ville Syrjälä wrote:
> On Wed, Jan 17, 2024 at 06:46:24PM +0100, Nirmoy Das wrote:
> > 
> > On 1/17/2024 3:13 PM, Michał Winiarski wrote:
> > > On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
> > >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >>
> > >> Now that the GGTT PTE updates go straight to GSMBASE (bypassing
> > >> GTTMMADR) there should be no more risk of system hangs? So the
> > >> "binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
> > >> necessary, disable it.
> > >>
> > >> My main worry with the MI_UPDATE_GTT are:
> > >> - only used on this one platform so very limited testing coverage
> > >> - async so more opprtunities to screw things up
> > >> - what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
> > >>    to finish?
> > >> - requires working command submission, so even getting a working
> > >>    display now depends on a lot more extra components working correctly
> > >>
> > >> TODO: MI_UPDATE_GTT might be interesting as an optimization
> > >> though, so perhaps someone should look into always using it
> > >> (assuming the GPU is alive and well)?
> > >>
> > >> v2: Keep using MI_UPDATE_GTT on VM guests
> > >>
> > >> Cc: Paz Zcharya <pazz@chromium.org>
> > >> Cc: Nirmoy Das <nirmoy.das@intel.com>
> > >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >> ---
> > >>   drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
> > >>   1 file changed, 2 insertions(+), 1 deletion(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > >> index 86f73fe558ca..e83dabc56a14 100644
> > >> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > >> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > >> @@ -24,7 +24,8 @@
> > >>   bool i915_ggtt_require_binder(struct drm_i915_private *i915)
> > >>   {
> > >>   	/* Wa_13010847436 & Wa_14019519902 */
> > >> -	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> > >> +	return i915_run_as_guest() &&
> > >> +		MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> > > Note that i915_run_as_guest() is not the most reliable way to decide
> > > whether to use MI_UPDATE_GTT or straight to GSMBASE, as it requires the
> > > hypervisor to "opt-in" and set the X86_FEATURE_HYPERVISOR.
> > > If it's not set - the driver will go into GSMBASE, which is not mapped
> > > inside the guest.
> > > Does the system firmware advertise whether GSMBASE is "open" or "closed"
> > > to CPU access in any way?
> > 
> > Had a chat with David from IVE team, David suggested to read 0x138914 to 
> > determine that.  "GOP needs to qualify the WA by reading GFX MMIO offset 
> > 0x138914 and verify the value there is 0x1." -> as per the HSD-22018444074
> 
> OK, so we can confirm the firmware is on board. I suppose no real harm
> in doing so even though it would clearly be a rather weird if someone
> would ship some ancient firmware that doesn't handle this.
> 
> But that still won't help with the guest side handling because that
> register will read the same in the guest.

I guess we have two options here:
1) ignore non-standard vms that don't advertise themselves
2) try some other heuristics to detect them (eg. host/isa bridge PCI
   IDs/DMI/etc.)

My preference is to just go with option 1, and if someone comes across
a real world use case when the vm is hiding then we can think of some
way to handle it. Trying to come up with heuristics for that without
anything to test against would be 100% guesswork anyway.

-- 
Ville Syrjälä
Intel

[PATCH v4 04/16] drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory access

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On MTL accessing stolen memory via the BARs is somehow borked,
and it can hang the machine. As a workaround let's bypass the
BARs and just go straight to DSMBASE/GSMBASE instead.

Note that on every other platform this itself would hang the
machine, but on MTL the system firmware is expected to relax
the access permission guarding stolen memory to enable this
workaround, and thus direct CPU accesses should be fine.

The raw stolen memory areas won't be passed to VMs so we'll
need to risk using the BAR there for the initial setup. Once
command submission is up we should switch to MI_UPDATE_GTT
which at least shouldn't hang the whole machine.

v2: Don't use direct GSM/DSM access on guests
    Add w/a number
v3: Check register 0x138914 to see if pcode did its job
    Add some debug prints

Cc: Paz Zcharya <pazz@chromium.org>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c |  6 +++++-
 drivers/gpu/drm/i915/gt/intel_ggtt.c       | 10 +++++++++-
 drivers/gpu/drm/i915/i915_reg.h            |  3 +++
 drivers/gpu/drm/i915/i915_utils.c          | 17 +++++++++++++++++
 drivers/gpu/drm/i915/i915_utils.h          |  2 ++
 5 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index ee237043c302..9ddcae9b3997 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -941,7 +941,11 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
 		dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
 	}
 
-	if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
+	if (i915_direct_stolen_access(i915)) {
+		drm_dbg(&i915->drm, "Using direct DSM access\n");
+		io_start = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
+		io_size = dsm_size;
+	} else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
 		io_start = 0;
 		io_size = 0;
 	} else {
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 21a7e3191c18..bce5d8025340 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -24,6 +24,7 @@
 #include "intel_ring.h"
 #include "i915_drv.h"
 #include "i915_pci.h"
+#include "i915_reg.h"
 #include "i915_request.h"
 #include "i915_scatterlist.h"
 #include "i915_utils.h"
@@ -1152,13 +1153,20 @@ static unsigned int gen6_gttadr_offset(struct drm_i915_private *i915)
 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 {
 	struct drm_i915_private *i915 = ggtt->vm.i915;
+	struct intel_uncore *uncore = ggtt->vm.gt->uncore;
 	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 	phys_addr_t phys_addr;
 	u32 pte_flags;
 	int ret;
 
 	GEM_WARN_ON(pci_resource_len(pdev, GEN4_GTTMMADR_BAR) != gen6_gttmmadr_size(i915));
-	phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
+
+	if (i915_direct_stolen_access(i915)) {
+		drm_dbg(&i915->drm, "Using direct GSM access\n");
+		phys_addr = intel_uncore_read64(uncore, GEN12_GSMBASE) & GEN12_BDSM_MASK;
+	} else {
+		phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
+	}
 
 	if (needs_wc_ggtt_mapping(i915))
 		ggtt->gsm = ioremap_wc(phys_addr, size);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 75bc08081fce..b5f5e0bc6608 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5414,6 +5414,9 @@
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
 #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
 
+#define MTL_PCODE_STOLEN_ACCESS			_MMIO(0x138914)
+#define   STOLEN_ACCESS_ALLOWED			0x1
+
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
diff --git a/drivers/gpu/drm/i915/i915_utils.c b/drivers/gpu/drm/i915/i915_utils.c
index 29fd02bf5ea8..6f9e7b354b54 100644
--- a/drivers/gpu/drm/i915/i915_utils.c
+++ b/drivers/gpu/drm/i915/i915_utils.c
@@ -8,6 +8,7 @@
 #include <drm/drm_drv.h>
 
 #include "i915_drv.h"
+#include "i915_reg.h"
 #include "i915_utils.h"
 
 #define FDO_BUG_MSG "Please file a bug on drm/i915; see " FDO_BUG_URL " for details."
@@ -125,3 +126,19 @@ bool i915_vtd_active(struct drm_i915_private *i915)
 	/* Running as a guest, we assume the host is enforcing VT'd */
 	return i915_run_as_guest();
 }
+
+bool i915_direct_stolen_access(struct drm_i915_private *i915)
+{
+	/*
+	 * Wa_22018444074
+	 *
+	 * Access via BAR can hang MTL, go directly to GSM/DSM,
+	 * except for VM guests which won't have access to it.
+	 *
+	 * Normally this would not work but on MTL the system firmware
+	 * should have relaxed the access permissions sufficiently.
+	 * 0x138914==0x1 indicates that the firmware has done its job.
+	 */
+	return IS_METEORLAKE(i915) && !i915_run_as_guest() &&
+		intel_uncore_read(&i915->uncore, MTL_PCODE_STOLEN_ACCESS) == STOLEN_ACCESS_ALLOWED;
+}
diff --git a/drivers/gpu/drm/i915/i915_utils.h b/drivers/gpu/drm/i915/i915_utils.h
index f98577967b7f..b45ef0560611 100644
--- a/drivers/gpu/drm/i915/i915_utils.h
+++ b/drivers/gpu/drm/i915/i915_utils.h
@@ -391,4 +391,6 @@ static inline bool i915_run_as_guest(void)
 
 bool i915_vtd_active(struct drm_i915_private *i915);
 
+bool i915_direct_stolen_access(struct drm_i915_private *i915);
+
 #endif /* !__I915_UTILS_H */
-- 
2.43.0

[PATCH v4 05/16] drm/i915: Disable the "binder"

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that the GGTT PTE updates go straight to GSMBASE (bypassing
GTTMMADR) there should be no more risk of system hangs? So the
"binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
necessary, disable it.

My main worry with the MI_UPDATE_GTT are:
- only used on this one platform so very limited testing coverage
- async so more opprtunities to screw things up
- what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
  to finish?
- requires working command submission, so even getting a working
  display now depends on a lot more extra components working correctly

TODO: MI_UPDATE_GTT might be interesting as an optimization
though, so perhaps someone should look into always using it
(assuming the GPU is alive and well)?

v2: Keep using MI_UPDATE_GTT on VM guests
v3: use i915_direct_stolen_access()

Cc: Paz Zcharya <pazz@chromium.org>
Cc: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 86f73fe558ca..7811a8c9da06 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -24,7 +24,8 @@
 bool i915_ggtt_require_binder(struct drm_i915_private *i915)
 {
 	/* Wa_13010847436 & Wa_14019519902 */
-	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
+	return !i915_direct_stolen_access(i915) &&
+		MEDIA_VER_FULL(i915) == IP_VER(13, 0);
 }
 
 static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
-- 
2.43.0

[PATCH v4 06/16] drm/i915: Rename the DSM/GSM registers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

0x108100 and 0x1080c0 have been around since snb. Rename the
defines appropriately.

v2: Rebase

Cc: Paz Zcharya <pazz@chromium.org>
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c  | 4 ++--
 drivers/gpu/drm/i915/gt/intel_ggtt.c        | 2 +-
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +-
 drivers/gpu/drm/i915/i915_reg.h             | 7 ++++---
 4 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 9ddcae9b3997..ad6dd7f3259b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -935,7 +935,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
 		GEM_BUG_ON((dsm_base + dsm_size) > lmem_size);
 	} else {
 		/* Use DSM base address instead for stolen memory */
-		dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
+		dsm_base = intel_uncore_read64(uncore, GEN6_DSMBASE) & GEN11_BDSM_MASK;
 		if (WARN_ON(lmem_size < dsm_base))
 			return ERR_PTR(-ENODEV);
 		dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
@@ -943,7 +943,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
 
 	if (i915_direct_stolen_access(i915)) {
 		drm_dbg(&i915->drm, "Using direct DSM access\n");
-		io_start = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
+		io_start = intel_uncore_read64(uncore, GEN6_DSMBASE) & GEN11_BDSM_MASK;
 		io_size = dsm_size;
 	} else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
 		io_start = 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index bce5d8025340..ec1cbe229f0e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -1163,7 +1163,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
 
 	if (i915_direct_stolen_access(i915)) {
 		drm_dbg(&i915->drm, "Using direct GSM access\n");
-		phys_addr = intel_uncore_read64(uncore, GEN12_GSMBASE) & GEN12_BDSM_MASK;
+		phys_addr = intel_uncore_read64(uncore, GEN6_GSMBASE) & GEN11_BDSM_MASK;
 	} else {
 		phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
 	}
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index af357089da6e..51bb27e10a4f 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -240,7 +240,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
 		lmem_size -= tile_stolen;
 	} else {
 		/* Stolen starts from GSMBASE without CCS */
-		lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
+		lmem_size = intel_uncore_read64(&i915->uncore, GEN6_GSMBASE);
 	}
 
 	i915_resize_lmem_bar(i915, lmem_size);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b5f5e0bc6608..1ad55aafe679 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6323,9 +6323,10 @@ enum skl_power_gate {
 #define   GMS_MASK			REG_GENMASK(15, 8)
 #define   GGMS_MASK			REG_GENMASK(7, 6)
 
-#define GEN12_GSMBASE			_MMIO(0x108100)
-#define GEN12_DSMBASE			_MMIO(0x1080C0)
-#define   GEN12_BDSM_MASK		REG_GENMASK64(63, 20)
+#define GEN6_GSMBASE			_MMIO(0x108100)
+#define GEN6_DSMBASE			_MMIO(0x1080C0)
+#define   GEN6_BDSM_MASK		REG_GENMASK64(31, 20)
+#define   GEN11_BDSM_MASK		REG_GENMASK64(63, 20)
 
 #define XEHP_CLOCK_GATE_DIS		_MMIO(0x101014)
 #define   SGSI_SIDECLK_DIS		REG_BIT(17)
-- 
2.43.0

✗ Fi.CI.CHECKPATCH: warning for drm/i915: (stolen) memory region related fixes (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915: (stolen) memory region related fixes (rev10)
URL   : https://patchwork.freedesktop.org/series/127721/
State : warning

== Summary ==

Error: dim checkpatch failed
72dda2db9044 drm/i915: Use struct resource for memory region IO as well
-:388: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#388: FILE: drivers/gpu/drm/i915/intel_region_ttm.c:227:
+			if (WARN_ON(overflows_type(resource_size(&mem->io) >> PAGE_SHIFT, place.lpfn))) {

total: 0 errors, 1 warnings, 0 checks, 281 lines checked
647617023b28 drm/i915: Print memory region info during probe
d4d79a559964 drm/i915: Remove ad-hoc lmem/stolen debugs
84b6c1bef1e8 drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory access
90f743608bc4 drm/i915: Disable the "binder"
73e317aef584 drm/i915: Rename the DSM/GSM registers
5da2ebc59918 drm/i915: Fix PTE decode during initial plane readout
e8e5509729b6 drm/i915: Fix region start during initial plane readout
6b64e9796923 drm/i915: Fix MTL initial plane readout
4e682d80a189 drm/i915: s/phys_base/dma_addr/
e6116924b137 drm/i915: Split the smem and lmem plane readout apart
9914347031fe drm/i915: Simplify intel_initial_plane_config() calling convention
fc524e5b6a53 drm/i915/fbdev: Fix smem_start for LMEMBAR stolen objects
b5288e67b618 drm/i915: Tweak BIOS fb reuse check
eae214ae90cc drm/i915: Try to relocate the BIOS fb to the start of ggtt
-:104: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#104: FILE: drivers/gpu/drm/i915/display/i9xx_plane.h:51:
 }
+static inline bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc,

-:105: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#105: FILE: drivers/gpu/drm/i915/display/i9xx_plane.h:52:
+						   const struct intel_initial_plane_config *plane_config)

total: 0 errors, 1 warnings, 1 checks, 229 lines checked
f07fd3928e76 drm/i915: Annotate more of the BIOS fb takeover failure paths

✗ Fi.CI.SPARSE: warning for drm/i915: (stolen) memory region related fixes (rev10)

[Patchwork]

== Series Details ==

Series: drm/i915: (stolen) memory region related fixes (rev10)
URL   : https://patchwork.freedesktop.org/series/127721/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ Fi.CI.BAT: success for drm/i915: (stolen) memory region related fixes (rev10)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6574 bytes --]

== Series Details ==

Series: drm/i915: (stolen) memory region related fixes (rev10)
URL   : https://patchwork.freedesktop.org/series/127721/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14178 -> Patchwork_127721v10
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/index.html

Participating hosts (35 -> 25)
------------------------------

  Additional (2): bat-rpls-2 bat-kbl-2 
  Missing    (12): fi-kbl-7567u fi-skl-guc bat-dg2-9 fi-snb-2520m fi-kbl-guc fi-glk-j4005 fi-kbl-x1275 fi-pnv-d510 fi-ivb-3770 fi-elk-e7500 bat-mtlp-8 bat-mtlp-6 

Known issues
------------

  Here are the changes found in Patchwork_127721v10 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@basic-hwmon:
    - bat-rpls-2:         NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-rpls-2/igt@debugfs_test@basic-hwmon.html

  * igt@fbdev@info:
    - bat-kbl-2:          NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1849])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-kbl-2/igt@fbdev@info.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - bat-kbl-2:          NOTRUN -> [SKIP][3] ([fdo#109271]) +35 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
    - bat-rpls-2:         NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-rpls-2/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_tiled_pread_basic:
    - bat-rpls-2:         NOTRUN -> [SKIP][5] ([i915#3282])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-rpls-2/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
    - bat-rpls-2:         NOTRUN -> [SKIP][6] ([i915#6621])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-rpls-2/igt@i915_pm_rps@basic-api.html

  * igt@i915_selftest@live@gt_pm:
    - bat-rpls-2:         NOTRUN -> [DMESG-FAIL][7] ([i915#10010])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-rpls-2/igt@i915_selftest@live@gt_pm.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-rpls-2:         NOTRUN -> [SKIP][8] ([i915#4103]) +1 other test skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-rpls-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-rpls-2:         NOTRUN -> [SKIP][9] ([i915#3555] / [i915#3840] / [i915#9886])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-rpls-2/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-rpls-2:         NOTRUN -> [SKIP][10] ([fdo#109285])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-rpls-2/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-rpls-2:         NOTRUN -> [SKIP][11] ([i915#5354])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-rpls-2/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-rpls-2:         NOTRUN -> [SKIP][12] ([i915#3555])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-rpls-2/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-read:
    - bat-rpls-2:         NOTRUN -> [SKIP][13] ([fdo#109295] / [i915#3708]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/bat-rpls-2/igt@prime_vgem@basic-fence-read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#10010]: https://gitlab.freedesktop.org/drm/intel/issues/10010
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
  [i915#9886]: https://gitlab.freedesktop.org/drm/intel/issues/9886


Build changes
-------------

  * Linux: CI_DRM_14178 -> Patchwork_127721v10

  CI-20190529: 20190529
  CI_DRM_14178: cad255f28ccca6529104b9497a8d7302ae7eb88a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7691: 7691
  Patchwork_127721v10: cad255f28ccca6529104b9497a8d7302ae7eb88a @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

f1db9ae14117 drm/i915: Annotate more of the BIOS fb takeover failure paths
832e5b8b2da6 drm/i915: Try to relocate the BIOS fb to the start of ggtt
c2cb0dea56a7 drm/i915: Tweak BIOS fb reuse check
c340576cb7f5 drm/i915/fbdev: Fix smem_start for LMEMBAR stolen objects
b801673e8844 drm/i915: Simplify intel_initial_plane_config() calling convention
cdb015218ff5 drm/i915: Split the smem and lmem plane readout apart
7c742be99fd9 drm/i915: s/phys_base/dma_addr/
48f718facafc drm/i915: Fix MTL initial plane readout
8e7c9b8b2f99 drm/i915: Fix region start during initial plane readout
51ee56235a3d drm/i915: Fix PTE decode during initial plane readout
2db63d8ca25a drm/i915: Rename the DSM/GSM registers
1555fbb8f663 drm/i915: Disable the "binder"
8701c1c4cd07 drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory access
239b3569ce53 drm/i915: Remove ad-hoc lmem/stolen debugs
757640ce7194 drm/i915: Print memory region info during probe
2e8547e86f46 drm/i915: Use struct resource for memory region IO as well

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/index.html

[-- Attachment #2: Type: text/html, Size: 7663 bytes --]

✗ Fi.CI.IGT: failure for drm/i915: (stolen) memory region related fixes (rev10)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 70553 bytes --]

== Series Details ==

Series: drm/i915: (stolen) memory region related fixes (rev10)
URL   : https://patchwork.freedesktop.org/series/127721/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14178_full -> Patchwork_127721v10_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_127721v10_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_127721v10_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/index.html

Participating hosts (8 -> 8)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_127721v10_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglu:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-tglu-5/igt@kms_fbcon_fbt@fbc-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-9/igt@kms_fbcon_fbt@fbc-suspend.html

  
Known issues
------------

  Here are the changes found in Patchwork_127721v10_full that come from known issues:

### CI changes ###

#### Issues hit ####

  * boot:
    - shard-glk:          ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23]) -> ([PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], [FAIL][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42]) ([i915#8293])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk9/boot.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk9/boot.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk8/boot.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk8/boot.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk8/boot.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk8/boot.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk7/boot.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk7/boot.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk7/boot.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk5/boot.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk5/boot.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk5/boot.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk4/boot.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk4/boot.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk4/boot.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk3/boot.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk3/boot.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk3/boot.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk1/boot.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk1/boot.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk1/boot.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk9/boot.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk9/boot.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk9/boot.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk8/boot.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk8/boot.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk8/boot.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk7/boot.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk7/boot.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk5/boot.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk5/boot.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk4/boot.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk4/boot.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk4/boot.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk3/boot.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk3/boot.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk3/boot.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk1/boot.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk1/boot.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk1/boot.html

  

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-keep-cache:
    - shard-dg2:          NOTRUN -> [SKIP][43] ([i915#8411]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@api_intel_bb@blit-reloc-keep-cache.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-dg2:          NOTRUN -> [SKIP][44] ([i915#7701])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_limit:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][45] ([i915#10140])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@drm_buddy@drm_buddy@drm_test_buddy_alloc_limit.html

  * igt@drm_fdinfo@busy-idle-check-all@ccs3:
    - shard-dg2:          NOTRUN -> [SKIP][46] ([i915#8414]) +10 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@drm_fdinfo@busy-idle-check-all@ccs3.html

  * igt@drm_fdinfo@idle@rcs0:
    - shard-rkl:          [PASS][47] -> [FAIL][48] ([i915#7742])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-5/igt@drm_fdinfo@idle@rcs0.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-2/igt@drm_fdinfo@idle@rcs0.html

  * igt@drm_mm@drm_mm@drm_test_mm_init:
    - shard-glk:          NOTRUN -> [DMESG-WARN][49] ([i915#10140])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk4/igt@drm_mm@drm_mm@drm_test_mm_init.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-tglu:         NOTRUN -> [SKIP][50] ([i915#9323])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_create@create-ext-set-pat:
    - shard-dg2:          NOTRUN -> [SKIP][51] ([i915#8562])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@gem_create@create-ext-set-pat.html
    - shard-tglu:         NOTRUN -> [SKIP][52] ([i915#8562])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-4/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_freq@sysfs@gt0:
    - shard-dg2:          [PASS][53] -> [FAIL][54] ([i915#9561])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg2-1/igt@gem_ctx_freq@sysfs@gt0.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-2/igt@gem_ctx_freq@sysfs@gt0.html

  * igt@gem_ctx_param@set-priority-not-supported:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([fdo#109314])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@gem_ctx_param@set-priority-not-supported.html

  * igt@gem_ctx_persistence@heartbeat-hostile:
    - shard-dg2:          NOTRUN -> [SKIP][56] ([i915#8555]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@gem_ctx_persistence@heartbeat-hostile.html

  * igt@gem_ctx_sseu@engines:
    - shard-rkl:          NOTRUN -> [SKIP][57] ([i915#280])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@gem_ctx_sseu@engines.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#280])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@gem_ctx_sseu@invalid-sseu.html
    - shard-tglu:         NOTRUN -> [SKIP][59] ([i915#280])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_exec_balancer@sliced:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#4812]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@gem_exec_balancer@sliced.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-rkl:          NOTRUN -> [SKIP][61] ([i915#6334])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@pi@bcs0:
    - shard-dg1:          [PASS][62] -> [FAIL][63] ([i915#4475])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg1-15/igt@gem_exec_capture@pi@bcs0.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg1-12/igt@gem_exec_capture@pi@bcs0.html

  * igt@gem_exec_fair@basic-none-rrul:
    - shard-dg2:          NOTRUN -> [SKIP][64] ([i915#3539] / [i915#4852]) +4 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@gem_exec_fair@basic-none-rrul.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-glk:          [PASS][65] -> [FAIL][66] ([i915#2842]) +1 other test fail
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk7/igt@gem_exec_fair@basic-none@vcs0.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk9/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_params@secure-non-root:
    - shard-dg2:          NOTRUN -> [SKIP][67] ([fdo#112283]) +2 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@gem_exec_params@secure-non-root.html
    - shard-tglu:         NOTRUN -> [SKIP][68] ([fdo#112283])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-4/igt@gem_exec_params@secure-non-root.html

  * igt@gem_exec_reloc@basic-active:
    - shard-dg2:          NOTRUN -> [SKIP][69] ([i915#3281]) +8 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@gem_exec_reloc@basic-active.html

  * igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#3281])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html

  * igt@gem_exec_schedule@semaphore-power:
    - shard-dg2:          NOTRUN -> [SKIP][71] ([i915#4537] / [i915#4812]) +1 other test skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@gem_exec_schedule@semaphore-power.html

  * igt@gem_fence_thrash@bo-write-verify-y:
    - shard-dg2:          NOTRUN -> [SKIP][72] ([i915#4860])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@gem_fence_thrash@bo-write-verify-y.html

  * igt@gem_huc_copy@huc-copy:
    - shard-glk:          NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2190])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk4/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - shard-rkl:          NOTRUN -> [SKIP][74] ([i915#4613]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@gem_lmem_swapping@basic.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-glk:          NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#4613]) +2 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk1/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][76] ([i915#4613]) +1 other test skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-4/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html

  * igt@gem_mmap_wc@write-prefaulted:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#4083]) +4 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@gem_mmap_wc@write-prefaulted.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#3282])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-dg2:          NOTRUN -> [SKIP][79] ([i915#3282]) +8 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-glk:          NOTRUN -> [INCOMPLETE][80] ([i915#10042] / [i915#10137])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk1/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@display-protected-crc:
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#4270])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@gem_pxp@display-protected-crc.html

  * igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#4270]) +2 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-dg2:          NOTRUN -> [SKIP][83] ([i915#4079])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_tiled_partial_pwrite_pread@writes:
    - shard-dg2:          NOTRUN -> [SKIP][84] ([i915#4077]) +11 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@gem_tiled_partial_pwrite_pread@writes.html

  * igt@gem_userptr_blits@access-control:
    - shard-dg2:          NOTRUN -> [SKIP][85] ([i915#3297]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-2/igt@gem_userptr_blits@access-control.html

  * igt@gen3_mixed_blits:
    - shard-tglu:         NOTRUN -> [SKIP][86] ([fdo#109289]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-4/igt@gen3_mixed_blits.html

  * igt@gen7_exec_parse@basic-offset:
    - shard-rkl:          NOTRUN -> [SKIP][87] ([fdo#109289]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@gen7_exec_parse@basic-offset.html

  * igt@gen7_exec_parse@bitmasks:
    - shard-dg2:          NOTRUN -> [SKIP][88] ([fdo#109289]) +7 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@gen7_exec_parse@bitmasks.html

  * igt@gen9_exec_parse@bb-secure:
    - shard-tglu:         NOTRUN -> [SKIP][89] ([i915#2527] / [i915#2856])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@gen9_exec_parse@bb-secure.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-dg2:          NOTRUN -> [SKIP][90] ([i915#2856]) +2 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@i915_module_load@load:
    - shard-rkl:          NOTRUN -> [SKIP][91] ([i915#6227])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@i915_module_load@load.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [PASS][92] -> [ABORT][93] ([i915#9820])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-3/igt@i915_module_load@reload-with-fault-injection.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-5/igt@i915_module_load@reload-with-fault-injection.html
    - shard-tglu:         [PASS][94] -> [INCOMPLETE][95] ([i915#10137] / [i915#9200])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-tglu-3/igt@i915_module_load@reload-with-fault-injection.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-8/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][96] ([i915#8399])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-glk:          NOTRUN -> [SKIP][97] ([fdo#109271]) +104 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
    - shard-dg2:          NOTRUN -> [SKIP][98] ([fdo#109293] / [fdo#109506])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
    - shard-tglu:         NOTRUN -> [SKIP][99] ([fdo#109293] / [fdo#109506])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html

  * igt@i915_query@query-topology-unsupported:
    - shard-dg2:          NOTRUN -> [SKIP][100] ([fdo#109302])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@i915_query@query-topology-unsupported.html

  * igt@kms_addfb_basic@bo-too-small-due-to-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][101] ([i915#4212])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@kms_addfb_basic@bo-too-small-due-to-tiling.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-glk:          NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#1769])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][103] ([fdo#111615] / [i915#5286]) +2 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][104] ([i915#5286])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-8bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][105] ([fdo#111614] / [i915#3638])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_big_fb@linear-8bpp-rotate-90.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][106] ([fdo#111614]) +6 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
    - shard-tglu:         NOTRUN -> [SKIP][107] ([fdo#111614])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
    - shard-dg2:          NOTRUN -> [SKIP][108] ([i915#5190]) +13 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-2/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-tglu:         [PASS][109] -> [FAIL][110] ([i915#3743]) +3 other tests fail
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-tglu-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
    - shard-dg2:          NOTRUN -> [SKIP][111] ([i915#4538] / [i915#5190]) +6 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-rkl:          NOTRUN -> [SKIP][112] ([fdo#110723]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][113] ([fdo#111615]) +2 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#2705])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-2/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-yf-tiled-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][115] ([i915#5354] / [i915#6095]) +4 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-yf-tiled-ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-basic-4-tiled-dg2-mc-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#5354]) +7 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_ccs@pipe-c-crc-primary-basic-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@pipe-c-random-ccs-data-4-tiled-mtl-rc-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][117] ([i915#5354] / [i915#6095]) +14 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-4/igt@kms_ccs@pipe-c-random-ccs-data-4-tiled-mtl-rc-ccs.html

  * igt@kms_chamelium_color@degamma:
    - shard-dg2:          NOTRUN -> [SKIP][118] ([fdo#111827]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_chamelium_color@degamma.html

  * igt@kms_chamelium_color@gamma:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([fdo#111827])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_chamelium_color@gamma.html

  * igt@kms_chamelium_edid@dp-edid-read:
    - shard-dg2:          NOTRUN -> [SKIP][120] ([i915#7828]) +9 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_chamelium_edid@dp-edid-read.html

  * igt@kms_chamelium_frames@dp-frame-dump:
    - shard-rkl:          NOTRUN -> [SKIP][121] ([i915#7828]) +1 other test skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_chamelium_frames@dp-frame-dump.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][122] ([i915#7828]) +1 other test skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-4/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][123] ([i915#7118])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#3299])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-2/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@type1:
    - shard-rkl:          NOTRUN -> [SKIP][125] ([i915#7118])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][126] ([i915#3359]) +1 other test skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@kms_cursor_crc@cursor-random-512x170.html
    - shard-tglu:         NOTRUN -> [SKIP][127] ([i915#3359]) +1 other test skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][128] ([i915#3359])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-512x170.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][129] ([fdo#109274] / [i915#5354]) +4 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
    - shard-tglu:         NOTRUN -> [SKIP][130] ([fdo#109274]) +2 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][131] ([fdo#111825]) +4 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-glk:          [PASS][132] -> [FAIL][133] ([i915#2346])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-tglu:         NOTRUN -> [SKIP][134] ([i915#4103])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][135] ([i915#4103] / [i915#4213]) +1 other test skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][136] ([i915#9723])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-5/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html

  * igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][137] ([i915#9723])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg1-14/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-4.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#3555]) +7 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@kms_display_modes@extended-mode-basic.html
    - shard-tglu:         NOTRUN -> [SKIP][139] ([i915#3555])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_display_modes@mst-extended-mode-negative:
    - shard-rkl:          NOTRUN -> [SKIP][140] ([i915#8588])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_display_modes@mst-extended-mode-negative.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#3840])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
    - shard-tglu:         NOTRUN -> [SKIP][142] ([i915#3840])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-4/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-dg2:          NOTRUN -> [SKIP][143] ([i915#3555] / [i915#3840])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-rkl:          NOTRUN -> [SKIP][144] ([i915#9337])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr2:
    - shard-dg2:          NOTRUN -> [SKIP][145] ([i915#658])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-panning-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][146] ([fdo#109274]) +7 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-2/igt@kms_flip@2x-flip-vs-panning-interruptible.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-tglu:         NOTRUN -> [SKIP][147] ([fdo#109274] / [i915#3637])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1:
    - shard-glk:          [PASS][148] -> [FAIL][149] ([i915#79])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][150] ([i915#2587] / [i915#2672]) +1 other test skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][151] ([i915#2672]) +1 other test skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite:
    - shard-snb:          [PASS][152] -> [SKIP][153] ([fdo#109271]) +12 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-snb1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-dg2:          [PASS][154] -> [FAIL][155] ([i915#6880]) +1 other test fail
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-2/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][156] ([i915#5354]) +91 other tests skip
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite:
    - shard-rkl:          NOTRUN -> [SKIP][157] ([fdo#111825] / [i915#1825]) +9 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#5439])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-dg2:          NOTRUN -> [SKIP][159] ([i915#3458]) +22 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][160] ([i915#3023]) +4 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][161] ([i915#8708]) +22 other tests skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-tglu:         NOTRUN -> [SKIP][162] ([fdo#109280]) +6 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-tglu:         NOTRUN -> [SKIP][163] ([fdo#110189]) +7 other tests skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_getfb@getfb-reject-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][164] ([i915#6118])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_getfb@getfb-reject-ccs.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][165] ([i915#3555] / [i915#8228]) +2 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
    - shard-snb:          NOTRUN -> [SKIP][166] ([fdo#109271])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-snb7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-dg2:          NOTRUN -> [SKIP][167] ([i915#3555] / [i915#8806])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [FAIL][168] ([i915#8292])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-1/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][169] ([i915#9423]) +7 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg1-13/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][170] ([i915#9423]) +7 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-7/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-b-hdmi-a-3.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][171] ([i915#9423]) +7 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-1/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a-hdmi-a-2.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][172] ([i915#5176] / [i915#9423]) +1 other test skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-hdmi-a-2.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][173] ([i915#5235]) +7 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg1-13/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-hdmi-a-3.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][174] ([i915#5235]) +5 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-5/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-b-hdmi-a-1.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2:
    - shard-dg2:          NOTRUN -> [SKIP][175] ([i915#5235] / [i915#9423]) +11 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b-hdmi-a-2.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-rkl:          NOTRUN -> [SKIP][176] ([i915#9685])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][177] ([i915#9340])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg2:          NOTRUN -> [SKIP][178] ([i915#9519])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
    - shard-rkl:          [PASS][179] -> [SKIP][180] ([i915#9519]) +1 other test skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-1/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html

  * igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf:
    - shard-dg2:          NOTRUN -> [SKIP][181] ([i915#9683]) +3 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
    - shard-tglu:         NOTRUN -> [SKIP][182] ([fdo#111068] / [i915#9683])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-dg2:          NOTRUN -> [SKIP][183] ([i915#9685]) +1 other test skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][184] ([i915#4235]) +2 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_scaling_modes@scaling-mode-none:
    - shard-rkl:          NOTRUN -> [SKIP][185] ([i915#3555]) +2 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_scaling_modes@scaling-mode-none.html

  * igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_build_fourcc_list:
    - shard-glk:          NOTRUN -> [DMESG-FAIL][186] ([i915#10143])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk4/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_build_fourcc_list.html

  * igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_clip_offset:
    - shard-rkl:          [PASS][187] -> [DMESG-WARN][188] ([i915#10143])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-7/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_clip_offset.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_clip_offset.html
    - shard-glk:          NOTRUN -> [DMESG-WARN][189] ([i915#10143])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk4/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_clip_offset.html

  * igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_xrgb8888_to_argb2101010:
    - shard-dg1:          [PASS][190] -> [DMESG-WARN][191] ([i915#10143]) +1 other test dmesg-warn
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg1-13/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_xrgb8888_to_argb2101010.html
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg1-15/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_xrgb8888_to_argb2101010.html

  * igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_xrgb8888_to_xbgr8888:
    - shard-dg2:          [PASS][192] -> [DMESG-WARN][193] ([i915#10143])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg2-3/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_xrgb8888_to_xbgr8888.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-10/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_xrgb8888_to_xbgr8888.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2:          NOTRUN -> [SKIP][194] ([i915#8623])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-2/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-dg2:          NOTRUN -> [SKIP][195] ([fdo#109309])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1:
    - shard-tglu:         [PASS][196] -> [FAIL][197] ([i915#9196])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-tglu-8/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-1.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-dg2:          NOTRUN -> [SKIP][198] ([i915#2437])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-2/igt@kms_writeback@writeback-fb-id.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-glk:          NOTRUN -> [SKIP][199] ([fdo#109271] / [i915#2437])
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk4/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-rkl:          NOTRUN -> [SKIP][200] ([i915#8516])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@prime_vgem@basic-fence-mmap:
    - shard-dg2:          NOTRUN -> [SKIP][201] ([i915#3708] / [i915#4077])
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@prime_vgem@basic-fence-mmap.html

  * igt@prime_vgem@fence-write-hang:
    - shard-tglu:         NOTRUN -> [SKIP][202] ([fdo#109295])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-4/igt@prime_vgem@fence-write-hang.html
    - shard-dg2:          NOTRUN -> [SKIP][203] ([i915#3708])
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@prime_vgem@fence-write-hang.html

  * igt@runner@aborted:
    - shard-mtlp:         NOTRUN -> ([FAIL][204], [FAIL][205], [FAIL][206], [FAIL][207], [FAIL][208], [FAIL][209], [FAIL][210], [FAIL][211], [FAIL][212], [FAIL][213], [FAIL][214], [FAIL][215], [FAIL][216], [FAIL][217], [FAIL][218], [FAIL][219], [FAIL][220], [FAIL][221], [FAIL][222], [FAIL][223], [FAIL][224], [FAIL][225], [FAIL][226]) ([i915#7812])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-4/igt@runner@aborted.html
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-2/igt@runner@aborted.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-1/igt@runner@aborted.html
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-2/igt@runner@aborted.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-2/igt@runner@aborted.html
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-1/igt@runner@aborted.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-2/igt@runner@aborted.html
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-6/igt@runner@aborted.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-8/igt@runner@aborted.html
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-5/igt@runner@aborted.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-4/igt@runner@aborted.html
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-7/igt@runner@aborted.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-7/igt@runner@aborted.html
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-6/igt@runner@aborted.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-7/igt@runner@aborted.html
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-5/igt@runner@aborted.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-6/igt@runner@aborted.html
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-8/igt@runner@aborted.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-5/igt@runner@aborted.html
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-8/igt@runner@aborted.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-5/igt@runner@aborted.html
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-4/igt@runner@aborted.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-mtlp-7/igt@runner@aborted.html

  * igt@v3d/v3d_job_submission@array-job-submission:
    - shard-dg2:          NOTRUN -> [SKIP][227] ([i915#2575]) +16 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-1/igt@v3d/v3d_job_submission@array-job-submission.html

  * igt@v3d/v3d_submit_cl@bad-multisync-out-sync:
    - shard-rkl:          NOTRUN -> [SKIP][228] ([fdo#109315]) +2 other tests skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@v3d/v3d_submit_cl@bad-multisync-out-sync.html

  * igt@v3d/v3d_submit_cl@bad-multisync-pad:
    - shard-tglu:         NOTRUN -> [SKIP][229] ([fdo#109315] / [i915#2575]) +3 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@v3d/v3d_submit_cl@bad-multisync-pad.html

  * igt@vc4/vc4_create_bo@create-bo-zeroed:
    - shard-tglu:         NOTRUN -> [SKIP][230] ([i915#2575]) +1 other test skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@vc4/vc4_create_bo@create-bo-zeroed.html

  * igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained:
    - shard-dg2:          NOTRUN -> [SKIP][231] ([i915#7711]) +5 other tests skip
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-3/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-check-retained.html

  * igt@vc4/vc4_tiling@get-bad-flags:
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#7711])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@vc4/vc4_tiling@get-bad-flags.html

  
#### Possible fixes ####

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-rkl:          [FAIL][233] ([i915#6268]) -> [PASS][234]
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-7/igt@gem_ctx_exec@basic-nohangcheck.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-1/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_isolation@preservation-s3@vecs0:
    - shard-tglu:         [ABORT][235] -> [PASS][236]
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-tglu-9/igt@gem_ctx_isolation@preservation-s3@vecs0.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-4/igt@gem_ctx_isolation@preservation-s3@vecs0.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-glk:          [FAIL][237] ([i915#2842]) -> [PASS][238] +1 other test pass
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk5/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-rkl:          [FAIL][239] ([i915#2842]) -> [PASS][240] +1 other test pass
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-5/igt@gem_exec_fair@basic-none-share@rcs0.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-2/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-tglu:         [FAIL][241] ([i915#2842]) -> [PASS][242]
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-tglu-8/igt@gem_exec_fair@basic-throttle@rcs0.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg1:          [TIMEOUT][243] ([i915#5493]) -> [PASS][244]
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg1-16/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg2:          [INCOMPLETE][245] ([i915#10137] / [i915#9820] / [i915#9849]) -> [PASS][246]
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg2-1/igt@i915_module_load@reload-with-fault-injection.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
    - shard-dg1:          [FAIL][247] ([i915#3591]) -> [PASS][248] +1 other test pass
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html

  * igt@i915_suspend@debugfs-reader:
    - shard-tglu:         [ABORT][249] ([i915#8213]) -> [PASS][250]
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-tglu-9/igt@i915_suspend@debugfs-reader.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@i915_suspend@debugfs-reader.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-2:
    - shard-glk:          [FAIL][251] ([i915#2521]) -> [PASS][252]
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-glk7/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-2.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-glk5/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-hdmi-a-2.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglu:         [FAIL][253] ([i915#3743]) -> [PASS][254]
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-tglu-8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_cursor_legacy@torture-bo@pipe-a:
    - shard-dg1:          [DMESG-WARN][255] -> [PASS][256]
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg1-19/igt@kms_cursor_legacy@torture-bo@pipe-a.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg1-16/igt@kms_cursor_legacy@torture-bo@pipe-a.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-snb:          [SKIP][257] ([fdo#109271]) -> [PASS][258] +20 other tests pass
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-snb2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-snb7/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          [SKIP][259] ([i915#9519]) -> [PASS][260] +1 other test pass
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg2-3/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-10/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-rkl:          [SKIP][261] ([i915#9519]) -> [PASS][262]
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-1/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_swab:
    - shard-rkl:          [DMESG-WARN][263] ([i915#10143]) -> [PASS][264] +2 other tests pass
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-7/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_swab.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_swab.html
    - shard-dg1:          [DMESG-WARN][265] ([i915#10143]) -> [PASS][266] +1 other test pass
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg1-13/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_swab.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg1-15/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_swab.html

  * igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_xrgb8888_to_mono:
    - shard-dg2:          [DMESG-WARN][267] ([i915#10143]) -> [PASS][268]
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg2-3/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_xrgb8888_to_mono.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-10/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_xrgb8888_to_mono.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [FAIL][269] ([i915#4349]) -> [PASS][270] +3 other tests pass
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg2-2/igt@perf_pmu@busy-double-start@vecs1.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html

  
#### Warnings ####

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-dg1:          [INCOMPLETE][271] ([i915#10137] / [i915#9849]) -> [ABORT][272] ([i915#9820])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg1-17/igt@i915_module_load@reload-with-fault-injection.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg1-13/igt@i915_module_load@reload-with-fault-injection.html

  * igt@kms_content_protection@content-type-change:
    - shard-snb:          [INCOMPLETE][273] ([i915#8816]) -> [SKIP][274] ([fdo#109271])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-snb7/igt@kms_content_protection@content-type-change.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-snb5/igt@kms_content_protection@content-type-change.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          [SKIP][275] ([i915#9424]) -> [SKIP][276] ([i915#9433])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg1-17/igt@kms_content_protection@mei-interface.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg1-13/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@type1:
    - shard-snb:          [SKIP][277] ([fdo#109271]) -> [INCOMPLETE][278] ([i915#8816])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-snb2/igt@kms_content_protection@type1.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-snb7/igt@kms_content_protection@type1.html

  * igt@kms_fbcon_fbt@psr:
    - shard-rkl:          [SKIP][279] ([fdo#110189] / [i915#3955]) -> [SKIP][280] ([i915#3955])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-2/igt@kms_fbcon_fbt@psr.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_fbcon_fbt@psr.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][281] ([i915#4816]) -> [SKIP][282] ([i915#4070] / [i915#4816])
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-rkl:          [SKIP][283] ([i915#3361]) -> [FAIL][284] ([i915#9295])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-3/igt@kms_pm_dc@dc6-dpms.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_build_fourcc_list:
    - shard-rkl:          [FAIL][285] ([i915#10136]) -> [DMESG-FAIL][286] ([i915#10143])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-rkl-7/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_build_fourcc_list.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-rkl-4/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_build_fourcc_list.html
    - shard-tglu:         [FAIL][287] ([i915#10136]) -> [DMESG-FAIL][288] ([i915#10143])
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-tglu-10/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_build_fourcc_list.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-tglu-6/igt@kms_selftest@drm_format_helper@drm_format_helper_test-drm_test_fb_build_fourcc_list.html

  * igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
    - shard-dg2:          [INCOMPLETE][289] ([i915#5493]) -> [CRASH][290] ([i915#9351])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14178/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#10042]: https://gitlab.freedesktop.org/drm/intel/issues/10042
  [i915#10136]: https://gitlab.freedesktop.org/drm/intel/issues/10136
  [i915#10137]: https://gitlab.freedesktop.org/drm/intel/issues/10137
  [i915#10140]: https://gitlab.freedesktop.org/drm/intel/issues/10140
  [i915#10143]: https://gitlab.freedesktop.org/drm/intel/issues/10143
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
  [i915#4475]: https://gitlab.freedesktop.org/drm/intel/issues/4475
  [i915#4537]: https://gitlab.freedesktop.org/drm/intel/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6118]: https://gitlab.freedesktop.org/drm/intel/issues/6118
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
  [i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7812]: https://gitlab.freedesktop.org/drm/intel/issues/7812
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
  [i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
  [i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
  [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
  [i915#8399]: https://gitlab.freedesktop.org/drm/intel/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
  [i915#8516]: https://gitlab.freedesktop.org/drm/intel/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/intel/issues/8555
  [i915#8562]: https://gitlab.freedesktop.org/drm/intel/issues/8562
  [i915#8588]: https://gitlab.freedesktop.org/drm/intel/issues/8588
  [i915#8623]: https://gitlab.freedesktop.org/drm/intel/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
  [i915#8806]: https://gitlab.freedesktop.org/drm/intel/issues/8806
  [i915#8816]: https://gitlab.freedesktop.org/drm/intel/issues/8816
  [i915#9196]: https://gitlab.freedesktop.org/drm/intel/issues/9196
  [i915#9200]: https://gitlab.freedesktop.org/drm/intel/issues/9200
  [i915#9295]: https://gitlab.freedesktop.org/drm/intel/issues/9295
  [i915#9323]: https://gitlab.freedesktop.org/drm/intel/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/intel/issues/9337
  [i915#9340]: https://gitlab.freedesktop.org/drm/intel/issues/9340
  [i915#9351]: https://gitlab.freedesktop.org/drm/intel/issues/9351
  [i915#9423]: https://gitlab.freedesktop.org/drm/intel/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/intel/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/intel/issues/9433
  [i915#9519]: https://gitlab.freedesktop.org/drm/intel/issues/9519
  [i915#9561]: https://gitlab.freedesktop.org/drm/intel/issues/9561
  [i915#9683]: https://gitlab.freedesktop.org/drm/intel/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/intel/issues/9685
  [i915#9723]: https://gitlab.freedesktop.org/drm/intel/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/intel/issues/9732
  [i915#9820]: https://gitlab.freedesktop.org/drm/intel/issues/9820
  [i915#9849]: https://gitlab.freedesktop.org/drm/intel/issues/9849


Build changes
-------------

  * Linux: CI_DRM_14178 -> Patchwork_127721v10

  CI-20190529: 20190529
  CI_DRM_14178: cad255f28ccca6529104b9497a8d7302ae7eb88a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7691: 7691
  Patchwork_127721v10: cad255f28ccca6529104b9497a8d7302ae7eb88a @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_127721v10/index.html

[-- Attachment #2: Type: text/html, Size: 82633 bytes --]

Re: Re: [PATCH v3 05/16] drm/i915: Disable the "binder"

[Michał Winiarski]

On Thu, Jan 25, 2024 at 11:08:04AM +0200, Ville Syrjälä wrote:
> On Fri, Jan 19, 2024 at 01:12:11AM +0200, Ville Syrjälä wrote:
> > On Wed, Jan 17, 2024 at 06:46:24PM +0100, Nirmoy Das wrote:
> > > 
> > > On 1/17/2024 3:13 PM, Michał Winiarski wrote:
> > > > On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
> > > >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >>
> > > >> Now that the GGTT PTE updates go straight to GSMBASE (bypassing
> > > >> GTTMMADR) there should be no more risk of system hangs? So the
> > > >> "binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
> > > >> necessary, disable it.
> > > >>
> > > >> My main worry with the MI_UPDATE_GTT are:
> > > >> - only used on this one platform so very limited testing coverage
> > > >> - async so more opprtunities to screw things up
> > > >> - what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
> > > >>    to finish?
> > > >> - requires working command submission, so even getting a working
> > > >>    display now depends on a lot more extra components working correctly
> > > >>
> > > >> TODO: MI_UPDATE_GTT might be interesting as an optimization
> > > >> though, so perhaps someone should look into always using it
> > > >> (assuming the GPU is alive and well)?
> > > >>
> > > >> v2: Keep using MI_UPDATE_GTT on VM guests
> > > >>
> > > >> Cc: Paz Zcharya <pazz@chromium.org>
> > > >> Cc: Nirmoy Das <nirmoy.das@intel.com>
> > > >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > >> ---
> > > >>   drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
> > > >>   1 file changed, 2 insertions(+), 1 deletion(-)
> > > >>
> > > >> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > >> index 86f73fe558ca..e83dabc56a14 100644
> > > >> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > >> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > >> @@ -24,7 +24,8 @@
> > > >>   bool i915_ggtt_require_binder(struct drm_i915_private *i915)
> > > >>   {
> > > >>   	/* Wa_13010847436 & Wa_14019519902 */
> > > >> -	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> > > >> +	return i915_run_as_guest() &&
> > > >> +		MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> > > > Note that i915_run_as_guest() is not the most reliable way to decide
> > > > whether to use MI_UPDATE_GTT or straight to GSMBASE, as it requires the
> > > > hypervisor to "opt-in" and set the X86_FEATURE_HYPERVISOR.
> > > > If it's not set - the driver will go into GSMBASE, which is not mapped
> > > > inside the guest.
> > > > Does the system firmware advertise whether GSMBASE is "open" or "closed"
> > > > to CPU access in any way?
> > > 
> > > Had a chat with David from IVE team, David suggested to read 0x138914 to 
> > > determine that.  "GOP needs to qualify the WA by reading GFX MMIO offset 
> > > 0x138914 and verify the value there is 0x1." -> as per the HSD-22018444074
> > 
> > OK, so we can confirm the firmware is on board. I suppose no real harm
> > in doing so even though it would clearly be a rather weird if someone
> > would ship some ancient firmware that doesn't handle this.
> > 
> > But that still won't help with the guest side handling because that
> > register will read the same in the guest.
> 
> I guess we have two options here:
> 1) ignore non-standard vms that don't advertise themselves
> 2) try some other heuristics to detect them (eg. host/isa bridge PCI
>    IDs/DMI/etc.)
> 
> My preference is to just go with option 1, and if someone comes across
> a real world use case when the vm is hiding then we can think of some
> way to handle it. Trying to come up with heuristics for that without
> anything to test against would be 100% guesswork anyway.
> 
> -- 
> Ville Syrjälä
> Intel

Option 1 can work, but there is a heuristic that should work for most
cases.
If we can assume that on bare-metal, e820 memory map excludes the stolen
region (it's marked as reserved), we should be able to do something that
looks roughly like this (warning - not tested, just a pseudo-code):

static int is_reserved(struct resource *res, void *arg)
{
	return 1;
}

static bool _stolen_is_reserved(u64 addr)
{
	int ret;

	ret = walk_iomem_res_desc(IORES_DESC_RESERVED, IORESOURCE_MEM,
				  gsm, gsm + gsm_size, NULL, is_reserved)
	if (ret != 1)
		return false;

	return true;
}

if (i915_run_as_guest() || !_stolen_is_reserved(gsm, gsm_size))
	fallback_to_mi_ggtt()

Similar sanity check for stolen being reserved should probably also be
done in the regular stolen init path - currently we're creating a
resource named "Graphics Stolen Memory" somewhere in the middle of
System RAM when i915 runs inside VM with native device passthrough.

-Michał

Re: [PATCH v3 12/16] drm/i915: Simplify intel_initial_plane_config() calling convention

[kernel test robot]

Hi Ville,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.8-rc1 next-20240125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ville-Syrjala/drm-i915-Use-struct-resource-for-memory-region-IO-as-well/20240125-222947
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:    https://lore.kernel.org/r/20240116075636.6121-13-ville.syrjala%40linux.intel.com
patch subject: [PATCH v3 12/16] drm/i915: Simplify intel_initial_plane_config() calling convention
config: alpha-randconfig-r121-20240127 (https://download.01.org/0day-ci/archive/20240128/202401281233.cX62UpWx-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240128/202401281233.cX62UpWx-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202401281233.cX62UpWx-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/xe/display/xe_plane_initial.c:270:6: sparse: sparse: symbol 'intel_crtc_initial_plane_config' was not declared. Should it be static?

vim +/intel_crtc_initial_plane_config +270 drivers/gpu/drm/xe/display/xe_plane_initial.c

44e694958b9539 Maarten Lankhorst 2023-08-17  269  
44e694958b9539 Maarten Lankhorst 2023-08-17 @270  void intel_crtc_initial_plane_config(struct intel_crtc *crtc)

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v3 12/16] drm/i915: Simplify intel_initial_plane_config() calling convention

[kernel test robot]

Hi Ville,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.8-rc1 next-20240125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ville-Syrjala/drm-i915-Use-struct-resource-for-memory-region-IO-as-well/20240125-222947
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:    https://lore.kernel.org/r/20240116075636.6121-13-ville.syrjala%40linux.intel.com
patch subject: [PATCH v3 12/16] drm/i915: Simplify intel_initial_plane_config() calling convention
config: alpha-randconfig-r121-20240127 (https://download.01.org/0day-ci/archive/20240128/202401281233.cX62UpWx-lkp@intel.com/config)
compiler: alpha-linux-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20240128/202401281233.cX62UpWx-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202401281233.cX62UpWx-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/xe/display/xe_plane_initial.c:270:6: sparse: sparse: symbol 'intel_crtc_initial_plane_config' was not declared. Should it be static?

vim +/intel_crtc_initial_plane_config +270 drivers/gpu/drm/xe/display/xe_plane_initial.c

44e694958b9539 Maarten Lankhorst 2023-08-17  269  
44e694958b9539 Maarten Lankhorst 2023-08-17 @270  void intel_crtc_initial_plane_config(struct intel_crtc *crtc)

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v3 01/16] drm/i915: Use struct resource for memory region IO as well

[Paz Zcharya]

On Tue, Jan 16, 2024 at 11:23:00AM +0100, Nirmoy Das wrote:
> 
> On 1/16/2024 8:56 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > mem->region is a struct resource, but mem->io_start and
> > mem->io_size are not for whatever reason. Let's unify this
> > and convert the io stuff into a struct resource as well.
> > Should make life a little less annoying when you don't have
> > juggle between two different approaches all the time.
> > 
> > Mostly done using cocci (with manual tweaks at all the
> > places where we mutate io_size by hand):
> > @@
> > struct intel_memory_region *M;
> > expression START, SIZE;
> > @@
> > - M->io_start = START;
> > - M->io_size = SIZE;
> > + M->io = DEFINE_RES_MEM(START, SIZE);
> > 
> > @@
> > struct intel_memory_region *M;
> > @@
> > - M->io_start
> > + M->io.start
> > 
> > @@
> > struct intel_memory_region M;
> > @@
> > - M.io_start
> > + M.io.start
> > 
> > @@
> > expression M;
> > @@
> > - M->io_size
> > + resource_size(&M->io)
> > 
> > @@
> > expression M;
> > @@
> > - M.io_size
> > + resource_size(&M.io)
> > 
> > Cc: Paz Zcharya <pazz@chromium.org>
> > Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Acked-by: Nirmoy Das <nirmoy.das@intel.com>

Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

Re: [PATCH v3 02/16] drm/i915: Print memory region info during probe

[Paz Zcharya]

On Tue, Jan 16, 2024 at 11:20:37AM +0100, Nirmoy Das wrote:
> 
> On 1/16/2024 8:56 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Dump the details about every memory region into dmesg at probe time.
> > Avoids having to dig those out from random places when debugging stuff.
> > 
> > Cc: Paz Zcharya <pazz@chromium.org>
> > Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>

Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

Re: [PATCH v3 03/16] drm/i915: Remove ad-hoc lmem/stolen debugs

[Paz Zcharya]

On Tue, Jan 16, 2024 at 11:23:37AM +0100, Nirmoy Das wrote:
> 
> On 1/16/2024 8:56 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Now that intel_memory_regions_hw_probe() prints out each and every
> > memory region there's no reason to have ad-hoc debugs to do similar
> > things elsewhere.
> > 
> > Cc: Paz Zcharya <pazz@chromium.org>
> > Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>

Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

Re: [PATCH v4 04/16] drm/i915: Bypass LMEMBAR/GTTMMADR for MTL stolen memory access

[Paz Zcharya]

On Thu, Jan 25, 2024 at 12:27:14PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On MTL accessing stolen memory via the BARs is somehow borked,
> and it can hang the machine. As a workaround let's bypass the
> BARs and just go straight to DSMBASE/GSMBASE instead.
> 
> Note that on every other platform this itself would hang the
> machine, but on MTL the system firmware is expected to relax
> the access permission guarding stolen memory to enable this
> workaround, and thus direct CPU accesses should be fine.
> 
> The raw stolen memory areas won't be passed to VMs so we'll
> need to risk using the BAR there for the initial setup. Once
> command submission is up we should switch to MI_UPDATE_GTT
> which at least shouldn't hang the whole machine.
> 
> v2: Don't use direct GSM/DSM access on guests
>     Add w/a number
> v3: Check register 0x138914 to see if pcode did its job
>     Add some debug prints
> 
> Cc: Paz Zcharya <pazz@chromium.org>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

Re: [PATCH v4 05/16] drm/i915: Disable the "binder"

[Paz Zcharya]

On Thu, Jan 25, 2024 at 12:27:36PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Now that the GGTT PTE updates go straight to GSMBASE (bypassing
> GTTMMADR) there should be no more risk of system hangs? So the
> "binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
> necessary, disable it.
> 
> My main worry with the MI_UPDATE_GTT are:
> - only used on this one platform so very limited testing coverage
> - async so more opprtunities to screw things up
> - what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
>   to finish?
> - requires working command submission, so even getting a working
>   display now depends on a lot more extra components working correctly
> 
> TODO: MI_UPDATE_GTT might be interesting as an optimization
> though, so perhaps someone should look into always using it
> (assuming the GPU is alive and well)?
> 
> v2: Keep using MI_UPDATE_GTT on VM guests
> v3: use i915_direct_stolen_access()
> 
> Cc: Paz Zcharya <pazz@chromium.org>
> Cc: Nirmoy Das <nirmoy.das@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

> ---
>  drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 86f73fe558ca..7811a8c9da06 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -24,7 +24,8 @@
>  bool i915_ggtt_require_binder(struct drm_i915_private *i915)
>  {
>  	/* Wa_13010847436 & Wa_14019519902 */
> -	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> +	return !i915_direct_stolen_access(i915) &&
> +		MEDIA_VER_FULL(i915) == IP_VER(13, 0);
>  }
>  
>  static bool intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *i915)
> -- 
> 2.43.0
> 

Re: [PATCH v4 06/16] drm/i915: Rename the DSM/GSM registers

[Paz Zcharya]

On Thu, Jan 25, 2024 at 12:28:04PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> 0x108100 and 0x1080c0 have been around since snb. Rename the
> defines appropriately.
> 
> v2: Rebase
> 
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

> ---
>  drivers/gpu/drm/i915/gem/i915_gem_stolen.c  | 4 ++--
>  drivers/gpu/drm/i915/gt/intel_ggtt.c        | 2 +-
>  drivers/gpu/drm/i915/gt/intel_region_lmem.c | 2 +-
>  drivers/gpu/drm/i915/i915_reg.h             | 7 ++++---
>  4 files changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> index 9ddcae9b3997..ad6dd7f3259b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
> @@ -935,7 +935,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>  		GEM_BUG_ON((dsm_base + dsm_size) > lmem_size);
>  	} else {
>  		/* Use DSM base address instead for stolen memory */
> -		dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
> +		dsm_base = intel_uncore_read64(uncore, GEN6_DSMBASE) & GEN11_BDSM_MASK;
>  		if (WARN_ON(lmem_size < dsm_base))
>  			return ERR_PTR(-ENODEV);
>  		dsm_size = ALIGN_DOWN(lmem_size - dsm_base, SZ_1M);
> @@ -943,7 +943,7 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,
>  
>  	if (i915_direct_stolen_access(i915)) {
>  		drm_dbg(&i915->drm, "Using direct DSM access\n");
> -		io_start = intel_uncore_read64(uncore, GEN12_DSMBASE) & GEN12_BDSM_MASK;
> +		io_start = intel_uncore_read64(uncore, GEN6_DSMBASE) & GEN11_BDSM_MASK;
>  		io_size = dsm_size;
>  	} else if (pci_resource_len(pdev, GEN12_LMEM_BAR) < lmem_size) {
>  		io_start = 0;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index bce5d8025340..ec1cbe229f0e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -1163,7 +1163,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
>  
>  	if (i915_direct_stolen_access(i915)) {
>  		drm_dbg(&i915->drm, "Using direct GSM access\n");
> -		phys_addr = intel_uncore_read64(uncore, GEN12_GSMBASE) & GEN12_BDSM_MASK;
> +		phys_addr = intel_uncore_read64(uncore, GEN6_GSMBASE) & GEN11_BDSM_MASK;
>  	} else {
>  		phys_addr = pci_resource_start(pdev, GEN4_GTTMMADR_BAR) + gen6_gttadr_offset(i915);
>  	}
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index af357089da6e..51bb27e10a4f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -240,7 +240,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
>  		lmem_size -= tile_stolen;
>  	} else {
>  		/* Stolen starts from GSMBASE without CCS */
> -		lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
> +		lmem_size = intel_uncore_read64(&i915->uncore, GEN6_GSMBASE);
>  	}
>  
>  	i915_resize_lmem_bar(i915, lmem_size);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b5f5e0bc6608..1ad55aafe679 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6323,9 +6323,10 @@ enum skl_power_gate {
>  #define   GMS_MASK			REG_GENMASK(15, 8)
>  #define   GGMS_MASK			REG_GENMASK(7, 6)
>  
> -#define GEN12_GSMBASE			_MMIO(0x108100)
> -#define GEN12_DSMBASE			_MMIO(0x1080C0)
> -#define   GEN12_BDSM_MASK		REG_GENMASK64(63, 20)
> +#define GEN6_GSMBASE			_MMIO(0x108100)
> +#define GEN6_DSMBASE			_MMIO(0x1080C0)
> +#define   GEN6_BDSM_MASK		REG_GENMASK64(31, 20)
> +#define   GEN11_BDSM_MASK		REG_GENMASK64(63, 20)
>  
>  #define XEHP_CLOCK_GATE_DIS		_MMIO(0x101014)
>  #define   SGSI_SIDECLK_DIS		REG_BIT(17)
> -- 
> 2.43.0
> 

Re: [PATCH v3 07/16] drm/i915: Fix PTE decode during initial plane readout

[Paz Zcharya]

On Tue, Jan 16, 2024 at 11:46:13AM +0100, Nirmoy Das wrote:
> 
> On 1/16/2024 8:56 AM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > When multiple pipes are enabled by the BIOS we try to read out each
> > in turn. But we do the readout for the second only after the inherited
> > vma for the first has been rebound into its original place (and thus
> > the PTEs have been rewritten). Unlike the BIOS we set some high caching
> > bits in the PTE on MTL which confuses the readout for the second plane.
> > Filter out the non-address bits from the PTE value appropriately to
> > fix this.
> > 
> > I suppose it might also be possible that the BIOS would already set
> > some caching bits as well, in which case we'd run into this same
> > issue already for the first plane.
> > 
> > TODO:
> > - should abstract the PTE decoding to avoid details leaking all over
> > - should probably do the readout for all the planes before
> >    we touch anything (including the PTEs) so that we truly read
> >    out the BIOS state
> > 
> > Cc: Paz Zcharya <pazz@chromium.org>
> > Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Acked-by: Nirmoy Das <nirmoy.das@intel.com>

Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

> > ---
> >   drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > index a55c09cbd0e4..ffc92b18fcf5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > @@ -72,7 +72,7 @@ initial_plane_vma(struct drm_i915_private *i915,
> >   			return NULL;
> >   		}
> > -		phys_base = pte & I915_GTT_PAGE_MASK;
> > +		phys_base = pte & GEN12_GGTT_PTE_ADDR_MASK;
> >   		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
> >   		/*

Re: [PATCH v3 08/16] drm/i915: Fix region start during initial plane readout

[Paz Zcharya]

On Mon, Jan 22, 2024 at 03:07:52PM +0000, Shankar, Uma wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Tuesday, January 16, 2024 1:26 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH v3 08/16] drm/i915: Fix region start during initial plane readout
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On MTL the stolen region starts at offset 8MiB from the start of LMEMBAR. The
> > dma addresses are thus also offset by 8MiB. However the mm_node/etc. is zero
> > based, and i915_pages_create_for_stolen() will add the appropriate region.start
> > into the sg dma address. So when we do the readout we need to convert the dma
> > address read from the PTE to be zero based as well.
> > 
> > Note that currently we don't take this path on MTL, but we should and thus this
> > needs to be fixed. For lmem this works correctly already as the lmem
> > region.start==0.
> > 
> > While at it let's also make sure the address points to somewhere within the
> > memory region. We don't need to check the size as
> > i915_gem_object_create_region_at() should later fail if the object size exceeds
> > the region size.
> 
> Looks Good to me.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> > Cc: Paz Zcharya <pazz@chromium.org>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

> > ---
> >  drivers/gpu/drm/i915/display/intel_plane_initial.c | 8 +++++---
> >  1 file changed, 5 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > index ffc92b18fcf5..db594ccf0323 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > @@ -79,16 +79,18 @@ initial_plane_vma(struct drm_i915_private *i915,
> >  		 * We don't currently expect this to ever be placed in the
> >  		 * stolen portion.
> >  		 */
> > -		if (phys_base >= resource_size(&mem->region)) {
> > +		if (phys_base < mem->region.start || phys_base > mem-
> > >region.end) {
> >  			drm_err(&i915->drm,
> > -				"Initial plane programming using invalid range,
> > phys_base=%pa\n",
> > -				&phys_base);
> > +				"Initial plane programming using invalid range,
> > phys_base=%pa (%s [%pa-%pa])\n",
> > +				&phys_base, mem->region.name, &mem-
> > >region.start,
> > +&mem->region.end);
> >  			return NULL;
> >  		}
> > 
> >  		drm_dbg(&i915->drm,
> >  			"Using phys_base=%pa, based on initial plane
> > programming\n",
> >  			&phys_base);
> > +
> > +		phys_base -= mem->region.start;
> >  	} else {
> >  		phys_base = base;
> >  		mem = i915->mm.stolen_region;
> > --
> > 2.41.0
> 

Re: [PATCH v3 09/16] drm/i915: Fix MTL initial plane readout

[Paz Zcharya]

On Mon, Jan 22, 2024 at 03:09:23PM +0000, Shankar, Uma wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Tuesday, January 16, 2024 1:26 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH v3 09/16] drm/i915: Fix MTL initial plane readout
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > MTL stolen memory looks more like local memory, so use the (now fixed) lmem
> > path when doing the initial plane readout.
> 
> Looks Good to me.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> > Cc: Paz Zcharya <pazz@chromium.org>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

> > ---
> >  .../drm/i915/display/intel_plane_initial.c    | 25 +++++++++++++------
> >  1 file changed, 18 insertions(+), 7 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > index db594ccf0323..c72d4cacf631 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > @@ -59,7 +59,7 @@ initial_plane_vma(struct drm_i915_private *i915,
> >  		return NULL;
> > 
> >  	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
> > -	if (IS_DGFX(i915)) {
> > +	if (IS_DGFX(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915)) {
> >  		gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
> >  		gen8_pte_t pte;
> > 
> > @@ -73,11 +73,20 @@ initial_plane_vma(struct drm_i915_private *i915,
> >  		}
> > 
> >  		phys_base = pte & GEN12_GGTT_PTE_ADDR_MASK;
> > -		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
> > +
> > +		if (IS_DGFX(i915))
> > +			mem = i915->mm.regions[INTEL_REGION_LMEM_0];
> > +		else
> > +			mem = i915->mm.stolen_region;
> > +		if (!mem) {
> > +			drm_dbg_kms(&i915->drm,
> > +				    "Initial plane memory region not
> > initialized\n");
> > +			return NULL;
> > +		}
> > 
> >  		/*
> > -		 * We don't currently expect this to ever be placed in the
> > -		 * stolen portion.
> > +		 * On lmem we don't currently expect this to
> > +		 * ever be placed in the stolen portion.
> >  		 */
> >  		if (phys_base < mem->region.start || phys_base > mem-
> > >region.end) {
> >  			drm_err(&i915->drm,
> > @@ -94,11 +103,13 @@ initial_plane_vma(struct drm_i915_private *i915,
> >  	} else {
> >  		phys_base = base;
> >  		mem = i915->mm.stolen_region;
> > +		if (!mem) {
> > +			drm_dbg_kms(&i915->drm,
> > +				    "Initial plane memory region not
> > initialized\n");
> > +			return NULL;
> > +		}
> >  	}
> > 
> > -	if (!mem)
> > -		return NULL;
> > -
> >  	size = round_up(plane_config->base + plane_config->size,
> >  			mem->min_page_size);
> >  	size -= base;
> > --
> > 2.41.0
> 

Re: [PATCH v3 10/16] drm/i915: s/phys_base/dma_addr/

[Paz Zcharya]

On Tue, Jan 16, 2024 at 09:56:30AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The address we read from the PTE is a dma address, not a physical
> address. Rename the variable to say so.
> 
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

> ---
>  .../gpu/drm/i915/display/intel_plane_initial.c    | 15 ++++++++-------
>  1 file changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index c72d4cacf631..48b74319f45c 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -61,6 +61,7 @@ initial_plane_vma(struct drm_i915_private *i915,
>  	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
>  	if (IS_DGFX(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915)) {
>  		gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
> +		dma_addr_t dma_addr;
>  		gen8_pte_t pte;
>  
>  		gte += base / I915_GTT_PAGE_SIZE;
> @@ -72,7 +73,7 @@ initial_plane_vma(struct drm_i915_private *i915,
>  			return NULL;
>  		}
>  
> -		phys_base = pte & GEN12_GGTT_PTE_ADDR_MASK;
> +		dma_addr = pte & GEN12_GGTT_PTE_ADDR_MASK;
>  
>  		if (IS_DGFX(i915))
>  			mem = i915->mm.regions[INTEL_REGION_LMEM_0];
> @@ -88,18 +89,18 @@ initial_plane_vma(struct drm_i915_private *i915,
>  		 * On lmem we don't currently expect this to
>  		 * ever be placed in the stolen portion.
>  		 */
> -		if (phys_base < mem->region.start || phys_base > mem->region.end) {
> +		if (dma_addr < mem->region.start || dma_addr > mem->region.end) {
>  			drm_err(&i915->drm,
> -				"Initial plane programming using invalid range, phys_base=%pa (%s [%pa-%pa])\n",
> -				&phys_base, mem->region.name, &mem->region.start, &mem->region.end);
> +				"Initial plane programming using invalid range, dma_addr=%pa (%s [%pa-%pa])\n",
> +				&dma_addr, mem->region.name, &mem->region.start, &mem->region.end);
>  			return NULL;
>  		}
>  
>  		drm_dbg(&i915->drm,
> -			"Using phys_base=%pa, based on initial plane programming\n",
> -			&phys_base);
> +			"Using dma_addr=%pa, based on initial plane programming\n",
> +			&dma_addr);
>  
> -		phys_base -= mem->region.start;
> +		phys_base = dma_addr - mem->region.start;
>  	} else {
>  		phys_base = base;
>  		mem = i915->mm.stolen_region;
> -- 
> 2.41.0
> 

Re: [PATCH v3 11/16] drm/i915: Split the smem and lmem plane readout apart

[Paz Zcharya]

On Tue, Jan 16, 2024 at 09:56:31AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Declutter initial_plane_vma() a bit by pulling the lmem and smem
> readout paths into their own functions.
> 
> TODO: the smem path should still be fixed to get and validate
>       the dma address from the pte as well
> 
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

> ---
>  .../drm/i915/display/intel_display_types.h    |   2 +
>  .../drm/i915/display/intel_plane_initial.c    | 145 +++++++++++-------
>  2 files changed, 95 insertions(+), 52 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ae2e8cff9d69..319ba7aed4fa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -780,6 +780,8 @@ struct intel_plane_state {
>  
>  struct intel_initial_plane_config {
>  	struct intel_framebuffer *fb;
> +	struct intel_memory_region *mem;
> +	resource_size_t phys_base;
>  	struct i915_vma *vma;
>  	unsigned int tiling;
>  	int size;
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index 48b74319f45c..78bff6181ceb 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -44,6 +44,93 @@ intel_reuse_initial_plane_obj(struct drm_i915_private *i915,
>  	return false;
>  }
>  
> +static bool
> +initial_plane_phys_lmem(struct drm_i915_private *i915,
> +			struct intel_initial_plane_config *plane_config)
> +{
> +	gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
> +	struct intel_memory_region *mem;
> +	dma_addr_t dma_addr;
> +	gen8_pte_t pte;
> +	u32 base;
> +
> +	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
> +
> +	gte += base / I915_GTT_PAGE_SIZE;
> +
> +	pte = ioread64(gte);
> +	if (!(pte & GEN12_GGTT_PTE_LM)) {
> +		drm_err(&i915->drm,
> +			"Initial plane programming missing PTE_LM bit\n");
> +		return false;
> +	}
> +
> +	dma_addr = pte & GEN12_GGTT_PTE_ADDR_MASK;
> +
> +	if (IS_DGFX(i915))
> +		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
> +	else
> +		mem = i915->mm.stolen_region;
> +	if (!mem) {
> +		drm_dbg_kms(&i915->drm,
> +			    "Initial plane memory region not initialized\n");
> +		return false;
> +	}
> +
> +	/*
> +	 * On lmem we don't currently expect this to
> +	 * ever be placed in the stolen portion.
> +	 */
> +	if (dma_addr < mem->region.start || dma_addr > mem->region.end) {
> +		drm_err(&i915->drm,
> +			"Initial plane programming using invalid range, dma_addr=%pa (%s [%pa-%pa])\n",
> +			&dma_addr, mem->region.name, &mem->region.start, &mem->region.end);
> +		return false;
> +	}
> +
> +	drm_dbg(&i915->drm,
> +		"Using dma_addr=%pa, based on initial plane programming\n",
> +		&dma_addr);
> +
> +	plane_config->phys_base = dma_addr - mem->region.start;
> +	plane_config->mem = mem;
> +
> +	return true;
> +}
> +
> +static bool
> +initial_plane_phys_smem(struct drm_i915_private *i915,
> +			struct intel_initial_plane_config *plane_config)
> +{
> +	struct intel_memory_region *mem;
> +	u32 base;
> +
> +	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
> +
> +	mem = i915->mm.stolen_region;
> +	if (!mem) {
> +		drm_dbg_kms(&i915->drm,
> +			    "Initial plane memory region not initialized\n");
> +		return false;
> +	}
> +
> +	/* FIXME get and validate the dma_addr from the PTE */
> +	plane_config->phys_base = base;
> +	plane_config->mem = mem;
> +
> +	return true;
> +}
> +
> +static bool
> +initial_plane_phys(struct drm_i915_private *i915,
> +		   struct intel_initial_plane_config *plane_config)
> +{
> +	if (IS_DGFX(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915))
> +		return initial_plane_phys_lmem(i915, plane_config);
> +	else
> +		return initial_plane_phys_smem(i915, plane_config);
> +}
> +
>  static struct i915_vma *
>  initial_plane_vma(struct drm_i915_private *i915,
>  		  struct intel_initial_plane_config *plane_config)
> @@ -58,59 +145,13 @@ initial_plane_vma(struct drm_i915_private *i915,
>  	if (plane_config->size == 0)
>  		return NULL;
>  
> +	if (!initial_plane_phys(i915, plane_config))
> +		return NULL;
> +
> +	phys_base = plane_config->phys_base;
> +	mem = plane_config->mem;
> +
>  	base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
> -	if (IS_DGFX(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915)) {
> -		gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
> -		dma_addr_t dma_addr;
> -		gen8_pte_t pte;
> -
> -		gte += base / I915_GTT_PAGE_SIZE;
> -
> -		pte = ioread64(gte);
> -		if (!(pte & GEN12_GGTT_PTE_LM)) {
> -			drm_err(&i915->drm,
> -				"Initial plane programming missing PTE_LM bit\n");
> -			return NULL;
> -		}
> -
> -		dma_addr = pte & GEN12_GGTT_PTE_ADDR_MASK;
> -
> -		if (IS_DGFX(i915))
> -			mem = i915->mm.regions[INTEL_REGION_LMEM_0];
> -		else
> -			mem = i915->mm.stolen_region;
> -		if (!mem) {
> -			drm_dbg_kms(&i915->drm,
> -				    "Initial plane memory region not initialized\n");
> -			return NULL;
> -		}
> -
> -		/*
> -		 * On lmem we don't currently expect this to
> -		 * ever be placed in the stolen portion.
> -		 */
> -		if (dma_addr < mem->region.start || dma_addr > mem->region.end) {
> -			drm_err(&i915->drm,
> -				"Initial plane programming using invalid range, dma_addr=%pa (%s [%pa-%pa])\n",
> -				&dma_addr, mem->region.name, &mem->region.start, &mem->region.end);
> -			return NULL;
> -		}
> -
> -		drm_dbg(&i915->drm,
> -			"Using dma_addr=%pa, based on initial plane programming\n",
> -			&dma_addr);
> -
> -		phys_base = dma_addr - mem->region.start;
> -	} else {
> -		phys_base = base;
> -		mem = i915->mm.stolen_region;
> -		if (!mem) {
> -			drm_dbg_kms(&i915->drm,
> -				    "Initial plane memory region not initialized\n");
> -			return NULL;
> -		}
> -	}
> -
>  	size = round_up(plane_config->base + plane_config->size,
>  			mem->min_page_size);
>  	size -= base;
> -- 
> 2.41.0
> 

Re: [PATCH v3 12/16] drm/i915: Simplify intel_initial_plane_config() calling convention

[Paz Zcharya]

On Tue, Jan 16, 2024 at 09:56:32AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> There's no reason the caller of intel_initial_plane_config() should
> have to loop over the CRTCs. Pull the loop into the function to
> make life simpler for the caller.
> 
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

> ---
>  .../drm/i915/display/intel_display_driver.c   |  7 +---
>  .../drm/i915/display/intel_plane_initial.c    | 40 +++++++++++--------
>  .../drm/i915/display/intel_plane_initial.h    |  4 +-
>  3 files changed, 26 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index ecf9cb74734b..f3fe1743243b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -415,7 +415,6 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
>  {
>  	struct drm_device *dev = &i915->drm;
>  	enum pipe pipe;
> -	struct intel_crtc *crtc;
>  	int ret;
>  
>  	if (!HAS_DISPLAY(i915))
> @@ -467,11 +466,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
>  	intel_acpi_assign_connector_fwnodes(i915);
>  	drm_modeset_unlock_all(dev);
>  
> -	for_each_intel_crtc(dev, crtc) {
> -		if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
> -			continue;
> -		intel_crtc_initial_plane_config(crtc);
> -	}
> +	intel_initial_plane_config(i915);
>  
>  	/*
>  	 * Make sure hardware watermarks really match the state we read out.
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index 78bff6181ceb..b7e12b60d68b 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -357,25 +357,31 @@ static void plane_config_fini(struct intel_initial_plane_config *plane_config)
>  		i915_vma_put(plane_config->vma);
>  }
>  
> -void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
> +void intel_initial_plane_config(struct drm_i915_private *i915)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	struct intel_initial_plane_config plane_config = {};
> +	struct intel_crtc *crtc;
>  
> -	/*
> -	 * Note that reserving the BIOS fb up front prevents us
> -	 * from stuffing other stolen allocations like the ring
> -	 * on top.  This prevents some ugliness at boot time, and
> -	 * can even allow for smooth boot transitions if the BIOS
> -	 * fb is large enough for the active pipe configuration.
> -	 */
> -	dev_priv->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
> +	for_each_intel_crtc(&i915->drm, crtc) {
> +		struct intel_initial_plane_config plane_config = {};
>  
> -	/*
> -	 * If the fb is shared between multiple heads, we'll
> -	 * just get the first one.
> -	 */
> -	intel_find_initial_plane_obj(crtc, &plane_config);
> +		if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
> +			continue;
>  
> -	plane_config_fini(&plane_config);
> +		/*
> +		 * Note that reserving the BIOS fb up front prevents us
> +		 * from stuffing other stolen allocations like the ring
> +		 * on top.  This prevents some ugliness at boot time, and
> +		 * can even allow for smooth boot transitions if the BIOS
> +		 * fb is large enough for the active pipe configuration.
> +		 */
> +		i915->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
> +
> +		/*
> +		 * If the fb is shared between multiple heads, we'll
> +		 * just get the first one.
> +		 */
> +		intel_find_initial_plane_obj(crtc, &plane_config);
> +
> +		plane_config_fini(&plane_config);
> +	}
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.h b/drivers/gpu/drm/i915/display/intel_plane_initial.h
> index c7e35ab3182b..64ab95239cd4 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.h
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.h
> @@ -6,8 +6,8 @@
>  #ifndef __INTEL_PLANE_INITIAL_H__
>  #define __INTEL_PLANE_INITIAL_H__
>  
> -struct intel_crtc;
> +struct drm_i915_private;
>  
> -void intel_crtc_initial_plane_config(struct intel_crtc *crtc);
> +void intel_initial_plane_config(struct drm_i915_private *i915);
>  
>  #endif
> -- 
> 2.41.0
> 

Re: [PATCH v3 13/16] drm/i915/fbdev: Fix smem_start for LMEMBAR stolen objects

[Paz Zcharya]

On Tue, Jan 16, 2024 at 09:56:33AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The "io" address of an object is its dma address minus the
> region.start. Subtract the latter to make smem_start correct.
> The current code happens to work for genuine LMEM objects
> as LMEM region.start==0, but for LMEMBAR stolen objects
> region.start!=0.
> 
> TODO: perhaps just set smem_start=0 always as our .fb_mmap()
> implementation no longer depends on it? Need to double check
> it's not needed for anything else...
> 
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

> ---
>  drivers/gpu/drm/i915/display/intel_fbdev_fb.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
> index 1ac05d90b2e8..0665f943f65f 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c
> @@ -79,7 +79,8 @@ int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info
>  		/* Use fbdev's framebuffer from lmem for discrete */
>  		info->fix.smem_start =
>  			(unsigned long)(mem->io.start +
> -					i915_gem_object_get_dma_address(obj, 0));
> +					i915_gem_object_get_dma_address(obj, 0) -
> +					mem->region.start);
>  		info->fix.smem_len = obj->base.size;
>  	} else {
>  		struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
> -- 
> 2.41.0
> 

Re: [PATCH v3 14/16] drm/i915: Tweak BIOS fb reuse check

[Paz Zcharya]

On Tue, Jan 16, 2024 at 09:56:34AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we assume that we bind the BIOS fb exactly into the same
> ggtt address where the BIOS left it. That is about to change, and
> in order to keep intel_reuse_initial_plane_obj() working as intended
> we need to compare the original ggtt offset (called 'base' here)
> as opposed to the actual vma ggtt offset we selected. Otherwise
> the first plane could change the ggtt offset, and then subsequent
> planes would no longer notice that they are in fact using the same
> ggtt offset that the first plane was already using. Thus the reuse
> check will fail and we proceed to turn off these subsequent planes.
> 
> TODO: would probably make more sense to do the pure readout first
> for all the planes, then check for fb reuse, and only then proceed
> to pin the object into the final location in the ggtt...
> 
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

Re: [PATCH v3 15/16] drm/i915: Try to relocate the BIOS fb to the start of ggtt

[Paz Zcharya]

On Tue, Jan 16, 2024 at 09:56:35AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On MTL the GOP (for whatever reason) likes to bind its framebuffer
> high up in the ggtt address space. This can conflict with whatever
> ggtt_reserve_guc_top() is trying to do, and the result is that
> ggtt_reserve_guc_top() fails and then we proceed to explode when
> trying to tear down the driver. Thus far I haven't analyzed what
> causes the actual fireworks, but it's not super important as even
> if it didn't explode we'd still fail the driver load and the user
> would be left with an unusable GPU.
> 
> To remedy this (without having to figure out exactly what
> ggtt_reserve_guc_top() is trying to achieve) we can attempt to
> relocate the BIOS framebuffer to a lower ggtt address. We can do
> this at this early point in driver init because nothing else is
> supposed to be clobbering the ggtt yet. So we simply change where
> in the ggtt we pin the vma, the original PTEs will be left as is,
> and the new PTEs will get written with the same dma addresses.
> The plane will keep on scanning out from the original PTEs until
> we are done with the whole process, and at that point we rewrite
> the plane's surface address register to point at the new ggtt
> address.
> 
> Since we don't need a specific ggtt address for the plane
> (apart from needing it to land in the mappable region for
> normal stolen objects) we'll just try to pin it without a fixed
> offset first. It should end up at the lowest available address
> (which really should be 0 at this point in the driver init).
> If that fails we'll fall back to just pinning it exactly to the
> origianal address.
> 
> To make sure we don't accidentlally pin it partially over the
> original ggtt range (as that would corrupt the original PTEs)
> we reserve the original range temporarily during this process.
> 
> v2: Try to pin explicitly to ggtt offset 0 as otherwise DG2 puts it
>     even higher (atm we have no PIN_LOW flag to force it low)
> 
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

Re: [PATCH v3 16/16] drm/i915: Annotate more of the BIOS fb takeover failure paths

[Paz Zcharya]

On Mon, Jan 22, 2024 at 03:12:01PM +0000, Shankar, Uma wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Tuesday, January 16, 2024 1:27 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [PATCH v3 16/16] drm/i915: Annotate more of the BIOS fb takeover
> > failure paths
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Annotate a few more of the failure paths on the initial BIOS fb takeover to avoid
> > having to guess why things aren't working the way we expect.
> 
> Looks Good to me.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Hi Ville,

Thank you so much for this incredible series.
It solves the issue regarding MTL initial plane readout
that Andrzej Hajda and I worked on in
https://patchwork.freedesktop.org/patch/570811/?series=127130&rev=2
In addition, it solved the issue with the new GOP.

I tested it on two different devices with Meteor Lake and it worked perfectly:
no i915 errors, no flickers or observable issues.

Tested-by: Paz Zcharya <pazz@chromium.org>

Re: Re: [PATCH v3 05/16] drm/i915: Disable the "binder"

[Ville Syrjälä]

On Thu, Jan 25, 2024 at 03:59:36PM +0100, Michał Winiarski wrote:
> On Thu, Jan 25, 2024 at 11:08:04AM +0200, Ville Syrjälä wrote:
> > On Fri, Jan 19, 2024 at 01:12:11AM +0200, Ville Syrjälä wrote:
> > > On Wed, Jan 17, 2024 at 06:46:24PM +0100, Nirmoy Das wrote:
> > > > 
> > > > On 1/17/2024 3:13 PM, Michał Winiarski wrote:
> > > > > On Tue, Jan 16, 2024 at 09:56:25AM +0200, Ville Syrjala wrote:
> > > > >> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > >>
> > > > >> Now that the GGTT PTE updates go straight to GSMBASE (bypassing
> > > > >> GTTMMADR) there should be no more risk of system hangs? So the
> > > > >> "binder" (ie. update the PTEs via MI_UPDATE_GTT) is no longer
> > > > >> necessary, disable it.
> > > > >>
> > > > >> My main worry with the MI_UPDATE_GTT are:
> > > > >> - only used on this one platform so very limited testing coverage
> > > > >> - async so more opprtunities to screw things up
> > > > >> - what happens if the engine hangs while we're waiting for MI_UPDATE_GTT
> > > > >>    to finish?
> > > > >> - requires working command submission, so even getting a working
> > > > >>    display now depends on a lot more extra components working correctly
> > > > >>
> > > > >> TODO: MI_UPDATE_GTT might be interesting as an optimization
> > > > >> though, so perhaps someone should look into always using it
> > > > >> (assuming the GPU is alive and well)?
> > > > >>
> > > > >> v2: Keep using MI_UPDATE_GTT on VM guests
> > > > >>
> > > > >> Cc: Paz Zcharya <pazz@chromium.org>
> > > > >> Cc: Nirmoy Das <nirmoy.das@intel.com>
> > > > >> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > >> ---
> > > > >>   drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
> > > > >>   1 file changed, 2 insertions(+), 1 deletion(-)
> > > > >>
> > > > >> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > > >> index 86f73fe558ca..e83dabc56a14 100644
> > > > >> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > > >> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> > > > >> @@ -24,7 +24,8 @@
> > > > >>   bool i915_ggtt_require_binder(struct drm_i915_private *i915)
> > > > >>   {
> > > > >>   	/* Wa_13010847436 & Wa_14019519902 */
> > > > >> -	return MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> > > > >> +	return i915_run_as_guest() &&
> > > > >> +		MEDIA_VER_FULL(i915) == IP_VER(13, 0);
> > > > > Note that i915_run_as_guest() is not the most reliable way to decide
> > > > > whether to use MI_UPDATE_GTT or straight to GSMBASE, as it requires the
> > > > > hypervisor to "opt-in" and set the X86_FEATURE_HYPERVISOR.
> > > > > If it's not set - the driver will go into GSMBASE, which is not mapped
> > > > > inside the guest.
> > > > > Does the system firmware advertise whether GSMBASE is "open" or "closed"
> > > > > to CPU access in any way?
> > > > 
> > > > Had a chat with David from IVE team, David suggested to read 0x138914 to 
> > > > determine that.  "GOP needs to qualify the WA by reading GFX MMIO offset 
> > > > 0x138914 and verify the value there is 0x1." -> as per the HSD-22018444074
> > > 
> > > OK, so we can confirm the firmware is on board. I suppose no real harm
> > > in doing so even though it would clearly be a rather weird if someone
> > > would ship some ancient firmware that doesn't handle this.
> > > 
> > > But that still won't help with the guest side handling because that
> > > register will read the same in the guest.
> > 
> > I guess we have two options here:
> > 1) ignore non-standard vms that don't advertise themselves
> > 2) try some other heuristics to detect them (eg. host/isa bridge PCI
> >    IDs/DMI/etc.)
> > 
> > My preference is to just go with option 1, and if someone comes across
> > a real world use case when the vm is hiding then we can think of some
> > way to handle it. Trying to come up with heuristics for that without
> > anything to test against would be 100% guesswork anyway.
> > 
> > -- 
> > Ville Syrjälä
> > Intel
> 
> Option 1 can work, but there is a heuristic that should work for most
> cases.
> If we can assume that on bare-metal, e820 memory map excludes the stolen
> region (it's marked as reserved), we should be able to do something that
> looks roughly like this (warning - not tested, just a pseudo-code):
> 
> static int is_reserved(struct resource *res, void *arg)
> {
> 	return 1;
> }
> 
> static bool _stolen_is_reserved(u64 addr)
> {
> 	int ret;
> 
> 	ret = walk_iomem_res_desc(IORES_DESC_RESERVED, IORESOURCE_MEM,
> 				  gsm, gsm + gsm_size, NULL, is_reserved)
> 	if (ret != 1)
> 		return false;
> 
> 	return true;
> }
> 
> if (i915_run_as_guest() || !_stolen_is_reserved(gsm, gsm_size))
> 	fallback_to_mi_ggtt()
> 
> Similar sanity check for stolen being reserved should probably also be
> done in the regular stolen init path - currently we're creating a
> resource named "Graphics Stolen Memory" somewhere in the middle of
> System RAM when i915 runs inside VM with native device passthrough.

You mean request_smem_stolen()? We skip that on LMEMBAR platforms.
And we now rely on the early quirk to figure out the DSM base/size.
People didn't want to keep doing that so now I suppose we're just
relying on the BIOS to do its job right.

So if we wanted to use that we'd need to redesign it to also
work for the LMEMBAR platforms without the early quirk, and
it might also make sense to do something similar for GSM for
extra belts and suspenders.

Anyways, I guess that's a bit beside the point, and just checking
to make sure both DSM and GSM are marked as reserved could be used
to detect that we need to take the normal path instead of the
direct stolen access path. That's assuming VMs don't mark that
range as reserved, which I guess they don't based on what you're
saying?

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 12/16] drm/i915: Simplify intel_initial_plane_config() calling convention

[Jani Nikula]

On Tue, 16 Jan 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> There's no reason the caller of intel_initial_plane_config() should
> have to loop over the CRTCs. Pull the loop into the function to
> make life simpler for the caller.
>
> Cc: Paz Zcharya <pazz@chromium.org>
> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  .../drm/i915/display/intel_display_driver.c   |  7 +---
>  .../drm/i915/display/intel_plane_initial.c    | 40 +++++++++++--------
>  .../drm/i915/display/intel_plane_initial.h    |  4 +-
>  3 files changed, 26 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index ecf9cb74734b..f3fe1743243b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -415,7 +415,6 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
>  {
>  	struct drm_device *dev = &i915->drm;
>  	enum pipe pipe;
> -	struct intel_crtc *crtc;
>  	int ret;
>  
>  	if (!HAS_DISPLAY(i915))
> @@ -467,11 +466,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
>  	intel_acpi_assign_connector_fwnodes(i915);
>  	drm_modeset_unlock_all(dev);
>  
> -	for_each_intel_crtc(dev, crtc) {
> -		if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
> -			continue;
> -		intel_crtc_initial_plane_config(crtc);
> -	}
> +	intel_initial_plane_config(i915);
>  
>  	/*
>  	 * Make sure hardware watermarks really match the state we read out.
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index 78bff6181ceb..b7e12b60d68b 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -357,25 +357,31 @@ static void plane_config_fini(struct intel_initial_plane_config *plane_config)
>  		i915_vma_put(plane_config->vma);
>  }
>  
> -void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
> +void intel_initial_plane_config(struct drm_i915_private *i915)

So this fails to build on CONFIG_DRM_XE=m, because it has its own
version of intel_plane_initial.c which has
intel_crtc_initial_plane_config(), but not intel_initial_plane_config().

You'll get this as the first indication:

  CC [M]  drivers/gpu/drm/xe/display/xe_plane_initial.o
../drivers/gpu/drm/xe/display/xe_plane_initial.c:270:6: error: no previous prototype for ‘intel_crtc_initial_plane_config’ [-Werror=missing-prototypes]
  270 | void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
      |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

but if you bypass that, eventually:

  MODPOST Module.symvers
ERROR: modpost: "intel_initial_plane_config" [drivers/gpu/drm/xe/xe.ko] undefined!

Needs to be fixed before merging.

BR,
Jani.

>  {
> -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	struct intel_initial_plane_config plane_config = {};
> +	struct intel_crtc *crtc;
>  
> -	/*
> -	 * Note that reserving the BIOS fb up front prevents us
> -	 * from stuffing other stolen allocations like the ring
> -	 * on top.  This prevents some ugliness at boot time, and
> -	 * can even allow for smooth boot transitions if the BIOS
> -	 * fb is large enough for the active pipe configuration.
> -	 */
> -	dev_priv->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
> +	for_each_intel_crtc(&i915->drm, crtc) {
> +		struct intel_initial_plane_config plane_config = {};
>  
> -	/*
> -	 * If the fb is shared between multiple heads, we'll
> -	 * just get the first one.
> -	 */
> -	intel_find_initial_plane_obj(crtc, &plane_config);
> +		if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
> +			continue;
>  
> -	plane_config_fini(&plane_config);
> +		/*
> +		 * Note that reserving the BIOS fb up front prevents us
> +		 * from stuffing other stolen allocations like the ring
> +		 * on top.  This prevents some ugliness at boot time, and
> +		 * can even allow for smooth boot transitions if the BIOS
> +		 * fb is large enough for the active pipe configuration.
> +		 */
> +		i915->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
> +
> +		/*
> +		 * If the fb is shared between multiple heads, we'll
> +		 * just get the first one.
> +		 */
> +		intel_find_initial_plane_obj(crtc, &plane_config);
> +
> +		plane_config_fini(&plane_config);
> +	}
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.h b/drivers/gpu/drm/i915/display/intel_plane_initial.h
> index c7e35ab3182b..64ab95239cd4 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.h
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.h
> @@ -6,8 +6,8 @@
>  #ifndef __INTEL_PLANE_INITIAL_H__
>  #define __INTEL_PLANE_INITIAL_H__
>  
> -struct intel_crtc;
> +struct drm_i915_private;
>  
> -void intel_crtc_initial_plane_config(struct intel_crtc *crtc);
> +void intel_initial_plane_config(struct drm_i915_private *i915);
>  
>  #endif

-- 
Jani Nikula, Intel

Re: [PATCH v3 12/16] drm/i915: Simplify intel_initial_plane_config() calling convention

[Ville Syrjälä]

On Fri, Feb 02, 2024 at 05:14:37PM +0200, Jani Nikula wrote:
> On Tue, 16 Jan 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > There's no reason the caller of intel_initial_plane_config() should
> > have to loop over the CRTCs. Pull the loop into the function to
> > make life simpler for the caller.
> >
> > Cc: Paz Zcharya <pazz@chromium.org>
> > Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  .../drm/i915/display/intel_display_driver.c   |  7 +---
> >  .../drm/i915/display/intel_plane_initial.c    | 40 +++++++++++--------
> >  .../drm/i915/display/intel_plane_initial.h    |  4 +-
> >  3 files changed, 26 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > index ecf9cb74734b..f3fe1743243b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> > @@ -415,7 +415,6 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
> >  {
> >  	struct drm_device *dev = &i915->drm;
> >  	enum pipe pipe;
> > -	struct intel_crtc *crtc;
> >  	int ret;
> >  
> >  	if (!HAS_DISPLAY(i915))
> > @@ -467,11 +466,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
> >  	intel_acpi_assign_connector_fwnodes(i915);
> >  	drm_modeset_unlock_all(dev);
> >  
> > -	for_each_intel_crtc(dev, crtc) {
> > -		if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
> > -			continue;
> > -		intel_crtc_initial_plane_config(crtc);
> > -	}
> > +	intel_initial_plane_config(i915);
> >  
> >  	/*
> >  	 * Make sure hardware watermarks really match the state we read out.
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > index 78bff6181ceb..b7e12b60d68b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> > @@ -357,25 +357,31 @@ static void plane_config_fini(struct intel_initial_plane_config *plane_config)
> >  		i915_vma_put(plane_config->vma);
> >  }
> >  
> > -void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
> > +void intel_initial_plane_config(struct drm_i915_private *i915)
> 
> So this fails to build on CONFIG_DRM_XE=m, because it has its own
> version of intel_plane_initial.c which has
> intel_crtc_initial_plane_config(), but not intel_initial_plane_config().
> 
> You'll get this as the first indication:
> 
>   CC [M]  drivers/gpu/drm/xe/display/xe_plane_initial.o
> ../drivers/gpu/drm/xe/display/xe_plane_initial.c:270:6: error: no previous prototype for ‘intel_crtc_initial_plane_config’ [-Werror=missing-prototypes]
>   270 | void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
>       |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 
> but if you bypass that, eventually:
> 
>   MODPOST Module.symvers
> ERROR: modpost: "intel_initial_plane_config" [drivers/gpu/drm/xe/xe.ko] undefined!
> 
> Needs to be fixed before merging.

Can't see anything off in the CI results. Are we not at
least build testing xe in i915 CI?

> 
> BR,
> Jani.
> 
> >  {
> > -	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > -	struct intel_initial_plane_config plane_config = {};
> > +	struct intel_crtc *crtc;
> >  
> > -	/*
> > -	 * Note that reserving the BIOS fb up front prevents us
> > -	 * from stuffing other stolen allocations like the ring
> > -	 * on top.  This prevents some ugliness at boot time, and
> > -	 * can even allow for smooth boot transitions if the BIOS
> > -	 * fb is large enough for the active pipe configuration.
> > -	 */
> > -	dev_priv->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
> > +	for_each_intel_crtc(&i915->drm, crtc) {
> > +		struct intel_initial_plane_config plane_config = {};
> >  
> > -	/*
> > -	 * If the fb is shared between multiple heads, we'll
> > -	 * just get the first one.
> > -	 */
> > -	intel_find_initial_plane_obj(crtc, &plane_config);
> > +		if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
> > +			continue;
> >  
> > -	plane_config_fini(&plane_config);
> > +		/*
> > +		 * Note that reserving the BIOS fb up front prevents us
> > +		 * from stuffing other stolen allocations like the ring
> > +		 * on top.  This prevents some ugliness at boot time, and
> > +		 * can even allow for smooth boot transitions if the BIOS
> > +		 * fb is large enough for the active pipe configuration.
> > +		 */
> > +		i915->display.funcs.display->get_initial_plane_config(crtc, &plane_config);
> > +
> > +		/*
> > +		 * If the fb is shared between multiple heads, we'll
> > +		 * just get the first one.
> > +		 */
> > +		intel_find_initial_plane_obj(crtc, &plane_config);
> > +
> > +		plane_config_fini(&plane_config);
> > +	}
> >  }
> > diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.h b/drivers/gpu/drm/i915/display/intel_plane_initial.h
> > index c7e35ab3182b..64ab95239cd4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_plane_initial.h
> > +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.h
> > @@ -6,8 +6,8 @@
> >  #ifndef __INTEL_PLANE_INITIAL_H__
> >  #define __INTEL_PLANE_INITIAL_H__
> >  
> > -struct intel_crtc;
> > +struct drm_i915_private;
> >  
> > -void intel_crtc_initial_plane_config(struct intel_crtc *crtc);
> > +void intel_initial_plane_config(struct drm_i915_private *i915);
> >  
> >  #endif
> 
> -- 
> Jani Nikula, Intel

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 12/16] drm/i915: Simplify intel_initial_plane_config() calling convention

[Jani Nikula]

On Fri, 02 Feb 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Feb 02, 2024 at 05:14:37PM +0200, Jani Nikula wrote:
>> On Tue, 16 Jan 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> So this fails to build on CONFIG_DRM_XE=m, because it has its own
>> version of intel_plane_initial.c which has
>> intel_crtc_initial_plane_config(), but not intel_initial_plane_config().
>> 
>> You'll get this as the first indication:
>> 
>>   CC [M]  drivers/gpu/drm/xe/display/xe_plane_initial.o
>> ../drivers/gpu/drm/xe/display/xe_plane_initial.c:270:6: error: no previous prototype for ‘intel_crtc_initial_plane_config’ [-Werror=missing-prototypes]
>>   270 | void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
>>       |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> 
>> but if you bypass that, eventually:
>> 
>>   MODPOST Module.symvers
>> ERROR: modpost: "intel_initial_plane_config" [drivers/gpu/drm/xe/xe.ko] undefined!
>> 
>> Needs to be fixed before merging.
>
> Can't see anything off in the CI results. Are we not at
> least build testing xe in i915 CI?

We're not. It's a work in progress.

You can Cc: intel-xe mailing list to get both build and testing on
Xe. (Also a work in progress to use the same config and builds for
both. Now they're completely detached.)


BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH v3 12/16] drm/i915: Simplify intel_initial_plane_config() calling convention

[kernel test robot]

Hi Ville,

kernel test robot noticed the following build errors:

[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-intel/for-linux-next-fixes drm-tip/drm-tip linus/master v6.8-rc2 next-20240202]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Ville-Syrjala/drm-i915-Use-struct-resource-for-memory-region-IO-as-well/20240125-222947
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
patch link:    https://lore.kernel.org/r/20240116075636.6121-13-ville.syrjala%40linux.intel.com
patch subject: [PATCH v3 12/16] drm/i915: Simplify intel_initial_plane_config() calling convention
config: x86_64-randconfig-076-20240202 (https://download.01.org/0day-ci/archive/20240203/202402030704.nGzOFDCt-lkp@intel.com/config)
compiler: clang version 17.0.6 (https://github.com/llvm/llvm-project 6009708b4367171ccdbf4b5905cb6a803753fe18)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240203/202402030704.nGzOFDCt-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202402030704.nGzOFDCt-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/gpu/drm/xe/display/xe_plane_initial.c:270:6: error: no previous prototype for function 'intel_crtc_initial_plane_config' [-Werror,-Wmissing-prototypes]
     270 | void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
         |      ^
   drivers/gpu/drm/xe/display/xe_plane_initial.c:270:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
     270 | void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
         | ^
         | static 
   1 error generated.

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for DRM_I915_DEBUG_GEM
   Depends on [n]: HAS_IOMEM [=y] && DRM_I915 [=m] && EXPERT [=y] && DRM_I915_WERROR [=n]
   Selected by [m]:
   - DRM_I915_DEBUG [=y] && HAS_IOMEM [=y] && DRM_I915 [=m] && EXPERT [=y] && !COMPILE_TEST [=n]


vim +/intel_crtc_initial_plane_config +270 drivers/gpu/drm/xe/display/xe_plane_initial.c

44e694958b9539 Maarten Lankhorst 2023-08-17  269  
44e694958b9539 Maarten Lankhorst 2023-08-17 @270  void intel_crtc_initial_plane_config(struct intel_crtc *crtc)

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki