From: Leonardo Bras <leobras@redhat.com> To: "Paul E. McKenney" <paulmck@kernel.org> Cc: Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>, linux-kernel@vger.kernel.org, kernel-team@meta.com, andi.shyti@linux.intel.com, andrzej.hajda@intel.com, linux-riscv@lists.infradead.org, palmer@dabbelt.com Subject: Re: [PATCH RFC cmpxchg 8/8] riscv: Emulate one-byte and two-byte cmpxchg Date: Sat, 11 May 2024 17:44:46 -0300 [thread overview] Message-ID: <Zj_YvmjROzW6NAog@LeoBras> (raw) In-Reply-To: <9a84b94c-34ff-4c3a-ab2b-2741a5755db9@paulmck-laptop> On Sat, May 11, 2024 at 07:54:34AM -0700, Paul E. McKenney wrote: > On Sat, May 11, 2024 at 02:50:13AM -0400, Guo Ren wrote: > > On Thu, Apr 04, 2024 at 07:15:40AM -0700, Palmer Dabbelt wrote: > > > On Mon, 01 Apr 2024 14:39:50 PDT (-0700), paulmck@kernel.org wrote: > > > > Use the new cmpxchg_emu_u8() and cmpxchg_emu_u16() to emulate one-byte > > > > and two-byte cmpxchg() on riscv. > > > > > > > > [ paulmck: Apply kernel test robot feedback. ] > > > > > > I'm not entirely following the thread, but sounds like there's going to be > > > generic kernel users of this now? Before we'd said "no" to the byte/half > > > atomic emulation routines beacuse they weren't used, but if it's a generic > > > thing then I'm find adding them. > > > > > > There's a patch set over here > > > <https://lore.kernel.org/all/20240103163203.72768-2-leobras@redhat.com/> > > > that implements these more directly using LR/SC. I was sort of on the fence > > > about just taking it even with no direct users right now, as the byte/half > > > atomic extension is working its way through the spec process so we'll have > > > them for real soon. I stopped right there for the last merge window, > > > though, as I figured it was too late to be messing with the atomics... > > > > > > So > > > > > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > F.Y.I Leonardo Bras <leobras@redhat.com> Hi Guo Ren, thanks for bringing it to my attention. I am quite excited about the inclusion of my patchset on riscv/cmpxchg, and I hope it can be useful both to your qspinlock implementation and on Paul's RCU improvement. > > I am carrying this in -rcu, but only for testing purposes, not for > inclusion into mainline. Not that I know of anyone testing -rcu on > RISC-V, but still, I wouldn't want to do anything do discourage such > testing. > > The reason that this patch is no longer intended for inclusion is that it > has been obsoleted by a patch that provides native support for one-byte > and two-byte cmpxchg() operations. Which is even better! ;-) > > Thanx, Paul Thanks Paul! Months ago I have reworked cmpxchg and added those 1-byte and 2-byte {cmp,}xchg asm implementations using lr/sc, as they would be useful to Guo Ren's qspinlock, and I am thankful that you provided another use case, because it provides more proof of it's usefulness. Thanks! Leo > > > > if you guys want to take some sort of tree-wide change to make the byte/half > > > stuff be required everywhere. We'll eventually end up with arch routines > > > for the extension, so at that point we might as well also have the more > > > direct LR/SC flavors. > > > > > > If you want I can go review/merge that RISC-V patch set and then it'll have > > > time to bake for a shared tag you can pick up for all this stuff? No rush > > > on my end, just LMK. > > > > > > > Signed-off-by: Paul E. McKenney <paulmck@kernel.org> > > > > Cc: Andi Shyti <andi.shyti@linux.intel.com> > > > > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > > > > Cc: <linux-riscv@lists.infradead.org> > > > > --- > > > > arch/riscv/Kconfig | 1 + > > > > arch/riscv/include/asm/cmpxchg.h | 25 +++++++++++++++++++++++++ > > > > 2 files changed, 26 insertions(+) > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > > > index be09c8836d56b..4eaf40d0a52ec 100644 > > > > --- a/arch/riscv/Kconfig > > > > +++ b/arch/riscv/Kconfig > > > > @@ -44,6 +44,7 @@ config RISCV > > > > select ARCH_HAS_UBSAN > > > > select ARCH_HAS_VDSO_DATA > > > > select ARCH_KEEP_MEMBLOCK if ACPI > > > > + select ARCH_NEED_CMPXCHG_1_2_EMU > > > > select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX > > > > select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT > > > > select ARCH_STACKWALK > > > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > > > > index 2fee65cc84432..a5b377481785c 100644 > > > > --- a/arch/riscv/include/asm/cmpxchg.h > > > > +++ b/arch/riscv/include/asm/cmpxchg.h > > > > @@ -9,6 +9,7 @@ > > > > #include <linux/bug.h> > > > > > > > > #include <asm/fence.h> > > > > +#include <linux/cmpxchg-emu.h> > > > > > > > > #define __xchg_relaxed(ptr, new, size) \ > > > > ({ \ > > > > @@ -170,6 +171,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > "0: lr.w %0, %2\n" \ > > > > @@ -214,6 +221,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > "0: lr.w %0, %2\n" \ > > > > @@ -260,6 +273,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > RISCV_RELEASE_BARRIER \ > > > > @@ -306,6 +325,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > "0: lr.w %0, %2\n" \ > > > >
WARNING: multiple messages have this Message-ID (diff)
From: Leonardo Bras <leobras@redhat.com> To: "Paul E. McKenney" <paulmck@kernel.org> Cc: Leonardo Bras <leobras@redhat.com>, Guo Ren <guoren@kernel.org>, linux-kernel@vger.kernel.org, kernel-team@meta.com, andi.shyti@linux.intel.com, andrzej.hajda@intel.com, linux-riscv@lists.infradead.org, palmer@dabbelt.com Subject: Re: [PATCH RFC cmpxchg 8/8] riscv: Emulate one-byte and two-byte cmpxchg Date: Sat, 11 May 2024 17:44:46 -0300 [thread overview] Message-ID: <Zj_YvmjROzW6NAog@LeoBras> (raw) In-Reply-To: <9a84b94c-34ff-4c3a-ab2b-2741a5755db9@paulmck-laptop> On Sat, May 11, 2024 at 07:54:34AM -0700, Paul E. McKenney wrote: > On Sat, May 11, 2024 at 02:50:13AM -0400, Guo Ren wrote: > > On Thu, Apr 04, 2024 at 07:15:40AM -0700, Palmer Dabbelt wrote: > > > On Mon, 01 Apr 2024 14:39:50 PDT (-0700), paulmck@kernel.org wrote: > > > > Use the new cmpxchg_emu_u8() and cmpxchg_emu_u16() to emulate one-byte > > > > and two-byte cmpxchg() on riscv. > > > > > > > > [ paulmck: Apply kernel test robot feedback. ] > > > > > > I'm not entirely following the thread, but sounds like there's going to be > > > generic kernel users of this now? Before we'd said "no" to the byte/half > > > atomic emulation routines beacuse they weren't used, but if it's a generic > > > thing then I'm find adding them. > > > > > > There's a patch set over here > > > <https://lore.kernel.org/all/20240103163203.72768-2-leobras@redhat.com/> > > > that implements these more directly using LR/SC. I was sort of on the fence > > > about just taking it even with no direct users right now, as the byte/half > > > atomic extension is working its way through the spec process so we'll have > > > them for real soon. I stopped right there for the last merge window, > > > though, as I figured it was too late to be messing with the atomics... > > > > > > So > > > > > > Acked-by: Palmer Dabbelt <palmer@rivosinc.com> > > F.Y.I Leonardo Bras <leobras@redhat.com> Hi Guo Ren, thanks for bringing it to my attention. I am quite excited about the inclusion of my patchset on riscv/cmpxchg, and I hope it can be useful both to your qspinlock implementation and on Paul's RCU improvement. > > I am carrying this in -rcu, but only for testing purposes, not for > inclusion into mainline. Not that I know of anyone testing -rcu on > RISC-V, but still, I wouldn't want to do anything do discourage such > testing. > > The reason that this patch is no longer intended for inclusion is that it > has been obsoleted by a patch that provides native support for one-byte > and two-byte cmpxchg() operations. Which is even better! ;-) > > Thanx, Paul Thanks Paul! Months ago I have reworked cmpxchg and added those 1-byte and 2-byte {cmp,}xchg asm implementations using lr/sc, as they would be useful to Guo Ren's qspinlock, and I am thankful that you provided another use case, because it provides more proof of it's usefulness. Thanks! Leo > > > > if you guys want to take some sort of tree-wide change to make the byte/half > > > stuff be required everywhere. We'll eventually end up with arch routines > > > for the extension, so at that point we might as well also have the more > > > direct LR/SC flavors. > > > > > > If you want I can go review/merge that RISC-V patch set and then it'll have > > > time to bake for a shared tag you can pick up for all this stuff? No rush > > > on my end, just LMK. > > > > > > > Signed-off-by: Paul E. McKenney <paulmck@kernel.org> > > > > Cc: Andi Shyti <andi.shyti@linux.intel.com> > > > > Cc: Andrzej Hajda <andrzej.hajda@intel.com> > > > > Cc: <linux-riscv@lists.infradead.org> > > > > --- > > > > arch/riscv/Kconfig | 1 + > > > > arch/riscv/include/asm/cmpxchg.h | 25 +++++++++++++++++++++++++ > > > > 2 files changed, 26 insertions(+) > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > > > index be09c8836d56b..4eaf40d0a52ec 100644 > > > > --- a/arch/riscv/Kconfig > > > > +++ b/arch/riscv/Kconfig > > > > @@ -44,6 +44,7 @@ config RISCV > > > > select ARCH_HAS_UBSAN > > > > select ARCH_HAS_VDSO_DATA > > > > select ARCH_KEEP_MEMBLOCK if ACPI > > > > + select ARCH_NEED_CMPXCHG_1_2_EMU > > > > select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX > > > > select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT > > > > select ARCH_STACKWALK > > > > diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h > > > > index 2fee65cc84432..a5b377481785c 100644 > > > > --- a/arch/riscv/include/asm/cmpxchg.h > > > > +++ b/arch/riscv/include/asm/cmpxchg.h > > > > @@ -9,6 +9,7 @@ > > > > #include <linux/bug.h> > > > > > > > > #include <asm/fence.h> > > > > +#include <linux/cmpxchg-emu.h> > > > > > > > > #define __xchg_relaxed(ptr, new, size) \ > > > > ({ \ > > > > @@ -170,6 +171,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > "0: lr.w %0, %2\n" \ > > > > @@ -214,6 +221,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > "0: lr.w %0, %2\n" \ > > > > @@ -260,6 +273,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > RISCV_RELEASE_BARRIER \ > > > > @@ -306,6 +325,12 @@ > > > > __typeof__(*(ptr)) __ret; \ > > > > register unsigned int __rc; \ > > > > switch (size) { \ > > > > + case 1: \ > > > > + __ret = cmpxchg_emu_u8((volatile u8 *)__ptr, __old, __new); \ > > > > + break; \ > > > > + case 2: \ > > > > + break; \ > > > > + __ret = cmpxchg_emu_u16((volatile u16 *)__ptr, __old, __new); \ > > > > case 4: \ > > > > __asm__ __volatile__ ( \ > > > > "0: lr.w %0, %2\n" \ > > > > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2024-05-11 20:45 UTC|newest] Thread overview: 127+ messages / expand[flat|nested] mbox.gz Atom feed top 2024-04-01 21:39 [PATCH RFC cmpxchg 0/8] Provide emulation for one- and two-byte cmpxchg() Paul E. McKenney 2024-04-01 21:39 ` [PATCH RFC cmpxchg 1/8] lib: Add one-byte and two-byte cmpxchg() emulation functions Paul E. McKenney 2024-04-02 13:07 ` Marco Elver 2024-04-02 17:15 ` Paul E. McKenney 2024-04-01 21:39 ` [PATCH RFC cmpxchg 2/8] sparc: Emulate one-byte and two-byte cmpxchg Paul E. McKenney 2024-04-01 22:38 ` Al Viro 2024-04-01 23:58 ` Paul E. McKenney 2024-04-02 0:07 ` Al Viro 2024-04-02 3:37 ` Al Viro 2024-04-02 4:11 ` Al Viro 2024-04-02 4:18 ` Paul E. McKenney 2024-04-02 4:28 ` [PATCH 1/8] sparc32: make __cmpxchg_u32() return u32 Al Viro 2024-04-02 4:28 ` [PATCH 2/8] sparc32: make the first argument of __cmpxchg_u64() volatile u64 * Al Viro 2024-04-02 4:28 ` [PATCH 3/8] sparc32: unify __cmpxchg_u{32,64} Al Viro 2024-04-02 7:28 ` Arnd Bergmann 2024-04-02 20:02 ` Paul E. McKenney 2024-04-02 4:28 ` [PATCH 4/8] sparc32: add __cmpxchg_u{8,16}() and teach __cmpxchg() to handle those sizes Al Viro 2024-04-02 4:28 ` [PATCH 5/8] parisc: __cmpxchg_u32(): lift conversion into the callers Al Viro 2024-04-02 4:28 ` [PATCH 6/8] parisc: unify implementations of __cmpxchg_u{8,32,64} Al Viro 2024-04-02 4:28 ` [PATCH 7/8] parisc: add missing export of __cmpxchg_u8() Al Viro 2024-04-02 4:28 ` [PATCH 8/8] parisc: add u16 support to cmpxchg() Al Viro 2024-04-02 20:03 ` [PATCH 1/8] sparc32: make __cmpxchg_u32() return u32 Paul E. McKenney 2024-04-03 22:20 ` Al Viro 2024-04-04 3:09 ` Paul E. McKenney 2024-04-02 4:17 ` [PATCH RFC cmpxchg 2/8] sparc: Emulate one-byte and two-byte cmpxchg Paul E. McKenney 2024-04-01 21:39 ` [PATCH RFC cmpxchg 3/8] ARC: " Paul E. McKenney 2024-04-01 21:39 ` Paul E. McKenney 2024-04-02 8:14 ` Arnd Bergmann 2024-04-02 8:14 ` Arnd Bergmann 2024-04-02 17:06 ` Paul E. McKenney 2024-04-02 17:06 ` Paul E. McKenney 2024-04-02 20:52 ` Paul E. McKenney 2024-04-02 20:52 ` Paul E. McKenney 2024-04-04 11:57 ` Arnd Bergmann 2024-04-04 11:57 ` Arnd Bergmann 2024-04-04 14:44 ` Paul E. McKenney 2024-04-04 14:44 ` Paul E. McKenney 2024-04-04 15:06 ` Arnd Bergmann 2024-04-04 15:06 ` Arnd Bergmann 2024-04-01 21:39 ` [PATCH RFC cmpxchg 4/8] csky: " Paul E. McKenney 2024-04-01 21:39 ` [PATCH RFC cmpxchg 5/8] sh: " Paul E. McKenney 2024-04-01 21:39 ` [PATCH RFC cmpxchg 6/8] xtensa: " Paul E. McKenney 2024-04-01 21:39 ` [PATCH RFC cmpxchg 7/8] parisc: Emulate " Paul E. McKenney 2024-04-01 21:39 ` [PATCH RFC cmpxchg 8/8] riscv: Emulate one-byte and " Paul E. McKenney 2024-04-01 21:39 ` Paul E. McKenney 2024-04-04 14:15 ` Palmer Dabbelt 2024-04-04 14:15 ` Palmer Dabbelt 2024-04-04 14:50 ` Paul E. McKenney 2024-04-04 14:50 ` Paul E. McKenney 2024-05-11 6:50 ` Guo Ren 2024-05-11 6:50 ` Guo Ren 2024-05-11 14:54 ` Paul E. McKenney 2024-05-11 14:54 ` Paul E. McKenney 2024-05-11 20:44 ` Leonardo Bras [this message] 2024-05-11 20:44 ` Leonardo Bras 2024-04-08 17:47 ` [PATCH RFC cmpxchg 0/8] Provide emulation for one- and two-byte cmpxchg() Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 01/14] sparc32: make __cmpxchg_u32() return u32 Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 02/14] sparc32: make the first argument of __cmpxchg_u64() volatile u64 * Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 03/14] sparc32: unify __cmpxchg_u{32,64} Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 04/14] sparc32: add __cmpxchg_u{8,16}() and teach __cmpxchg() to handle those sizes Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 05/14] parisc: __cmpxchg_u32(): lift conversion into the callers Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 06/14] parisc: unify implementations of __cmpxchg_u{8,32,64} Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 07/14] parisc: add missing export of __cmpxchg_u8() Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 08/14] parisc: add u16 support to cmpxchg() Paul E. McKenney 2024-04-08 20:10 ` Linus Torvalds 2024-04-08 20:53 ` Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 09/14] lib: Add one-byte emulation function Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 10/14] ARC: Emulate one-byte cmpxchg Paul E. McKenney 2024-04-08 17:49 ` Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 11/14] csky: " Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 12/14] sh: " Paul E. McKenney 2024-04-18 8:04 ` Geert Uytterhoeven 2024-04-08 17:49 ` [PATCH cmpxchg 13/14] xtensa: " Paul E. McKenney 2024-04-18 8:06 ` Geert Uytterhoeven 2024-04-18 23:21 ` Paul E. McKenney 2024-04-19 5:07 ` Yujie Liu 2024-04-19 8:02 ` Geert Uytterhoeven 2024-04-20 14:03 ` Paul E. McKenney 2024-04-08 17:49 ` [PATCH cmpxchg 14/14] riscv: " Paul E. McKenney 2024-04-08 17:49 ` Paul E. McKenney 2024-04-09 17:35 ` Andrea Parri 2024-04-09 17:35 ` Andrea Parri 2024-04-09 18:08 ` Paul E. McKenney 2024-04-09 18:08 ` Paul E. McKenney 2024-05-01 22:58 ` [PATCH v2 cmpxchg 0/8] Provide emulation for one--byte cmpxchg() Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 01/13] sparc32: make __cmpxchg_u32() return u32 Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 02/13] sparc32: make the first argument of __cmpxchg_u64() volatile u64 * Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 03/13] sparc32: unify __cmpxchg_u{32,64} Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 04/13] sparc32: add __cmpxchg_u{8,16}() and teach __cmpxchg() to handle those sizes Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 05/13] parisc: __cmpxchg_u32(): lift conversion into the callers Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 06/13] parisc: unify implementations of __cmpxchg_u{8,32,64} Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 07/13] parisc: add missing export of __cmpxchg_u8() Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 08/13] parisc: add u16 support to cmpxchg() Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 09/13] lib: Add one-byte emulation function Paul E. McKenney 2024-05-13 14:44 ` Boqun Feng 2024-05-13 15:41 ` Paul E. McKenney 2024-05-13 15:57 ` Boqun Feng 2024-05-13 21:19 ` Boqun Feng 2024-05-14 14:22 ` Paul E. McKenney 2024-05-14 14:53 ` Boqun Feng 2024-05-14 15:02 ` Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 10/13] ARC: Emulate one-byte cmpxchg Paul E. McKenney 2024-05-01 23:01 ` Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 11/13] csky: " Paul E. McKenney 2024-05-11 6:42 ` Guo Ren 2024-05-11 14:49 ` Paul E. McKenney 2024-05-01 23:01 ` [PATCH v2 cmpxchg 12/13] sh: " Paul E. McKenney 2024-05-02 4:52 ` John Paul Adrian Glaubitz 2024-05-02 5:06 ` Paul E. McKenney 2024-05-02 5:11 ` John Paul Adrian Glaubitz 2024-05-02 13:33 ` Paul E. McKenney 2024-05-02 20:53 ` Al Viro 2024-05-02 21:01 ` alpha cmpxchg.h (was Re: [PATCH v2 cmpxchg 12/13] sh: Emulate one-byte cmpxchg) Al Viro 2024-05-02 22:16 ` Linus Torvalds 2024-05-02 21:18 ` [PATCH v2 cmpxchg 12/13] sh: Emulate one-byte cmpxchg Paul E. McKenney 2024-05-02 22:07 ` Al Viro 2024-05-02 23:12 ` Paul E. McKenney 2024-05-02 23:24 ` Al Viro 2024-05-02 23:45 ` Paul E. McKenney 2024-05-02 23:32 ` Linus Torvalds 2024-05-03 0:16 ` Paul E. McKenney 2024-05-02 21:50 ` Arnd Bergmann 2024-05-02 5:42 ` D. Jeff Dionne 2024-05-02 11:30 ` Arnd Bergmann 2024-05-01 23:01 ` [PATCH v2 cmpxchg 13/13] xtensa: " Paul E. McKenney 2024-05-02 20:01 ` [PATCH v2 cmpxchg 0/8] Provide emulation for one--byte cmpxchg() Al Viro 2024-05-02 21:20 ` Paul E. McKenney
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