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* [PATCH v7 0/4] phy: qcom-qmp-ufs: add symbol clocks support
@ 2022-11-10 15:17 ` Dmitry Baryshkov
  0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 15:17 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

Register UFS symbol clocks in the Qualcomm QMP PHY driver. Some of the
platforms (msm8996, sc7280, sm8350/sm8450) expect them to be defined (to
be used as GCC clock parents).

Changes since v6:
- Added bindings change (Johan, thanks for the reminder)
- Added corresponding dts changes for msm8996 and sm8350/sm8450.

Changes since v5:
- Rebased on top of phy/next

Changes since v4:
- Rebased, dropping merged clk patches
- Fixed whitespace errors
- Added linebreaks to fit into 100 chars limit

Changes since v3:
- Rewrote asm9260 clk driver to fix the TODO item by using parent index
  rather than calling of_clk_get_parent_name().

Changes since v2:
- Added error handling to phy_symbols_clk_register() (requested by
  Johan).

Changes since v1:
- Added a macro used by clk-asm9260, so that the clk-fixed-rate changes
  do not affect the driver
- Changed registered clock names to be unique (as e.g. SC8280XP will
  have two UFS PHYs).

Dmitry Baryshkov (4):
  dt-bindings: phy: qcom,*-qmp-ufs-phy: add clock-cells property
  phy: qcom-qmp-ufs: provide symbol clocks
  arm64: dts: qcom: sm8450: fix gcc clocks order to follow the schema
  arm64: dts: qcom: use UFS symbol clocks provided by PHY

Dmitry Baryshkov (4):
  dt-bindings: phy: qcom,*-qmp-ufs-phy: add clock-cells property
  phy: qcom-qmp-ufs: provide symbol clocks
  arm64: dts: qcom: sm8450: fix gcc clocks order to follow the schema
  arm64: dts: qcom: use UFS symbol clocks provided by PHY

 .../phy/qcom,msm8996-qmp-ufs-phy.yaml         |  3 +
 .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml        |  3 +
 arch/arm64/boot/dts/qcom/msm8996.dtsi         |  5 +-
 arch/arm64/boot/dts/qcom/sm8350.dtsi          | 25 ++------
 arch/arm64/boot/dts/qcom/sm8450.dtsi          | 15 ++++-
 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c       | 64 +++++++++++++++++++
 6 files changed, 91 insertions(+), 24 deletions(-)

-- 
2.35.1


^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v7 0/4] phy: qcom-qmp-ufs: add symbol clocks support
@ 2022-11-10 15:17 ` Dmitry Baryshkov
  0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 15:17 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

Register UFS symbol clocks in the Qualcomm QMP PHY driver. Some of the
platforms (msm8996, sc7280, sm8350/sm8450) expect them to be defined (to
be used as GCC clock parents).

Changes since v6:
- Added bindings change (Johan, thanks for the reminder)
- Added corresponding dts changes for msm8996 and sm8350/sm8450.

Changes since v5:
- Rebased on top of phy/next

Changes since v4:
- Rebased, dropping merged clk patches
- Fixed whitespace errors
- Added linebreaks to fit into 100 chars limit

Changes since v3:
- Rewrote asm9260 clk driver to fix the TODO item by using parent index
  rather than calling of_clk_get_parent_name().

Changes since v2:
- Added error handling to phy_symbols_clk_register() (requested by
  Johan).

Changes since v1:
- Added a macro used by clk-asm9260, so that the clk-fixed-rate changes
  do not affect the driver
- Changed registered clock names to be unique (as e.g. SC8280XP will
  have two UFS PHYs).

Dmitry Baryshkov (4):
  dt-bindings: phy: qcom,*-qmp-ufs-phy: add clock-cells property
  phy: qcom-qmp-ufs: provide symbol clocks
  arm64: dts: qcom: sm8450: fix gcc clocks order to follow the schema
  arm64: dts: qcom: use UFS symbol clocks provided by PHY

Dmitry Baryshkov (4):
  dt-bindings: phy: qcom,*-qmp-ufs-phy: add clock-cells property
  phy: qcom-qmp-ufs: provide symbol clocks
  arm64: dts: qcom: sm8450: fix gcc clocks order to follow the schema
  arm64: dts: qcom: use UFS symbol clocks provided by PHY

 .../phy/qcom,msm8996-qmp-ufs-phy.yaml         |  3 +
 .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml        |  3 +
 arch/arm64/boot/dts/qcom/msm8996.dtsi         |  5 +-
 arch/arm64/boot/dts/qcom/sm8350.dtsi          | 25 ++------
 arch/arm64/boot/dts/qcom/sm8450.dtsi          | 15 ++++-
 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c       | 64 +++++++++++++++++++
 6 files changed, 91 insertions(+), 24 deletions(-)

-- 
2.35.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 20+ messages in thread
* [PATCH v7 1/4] dt-bindings: phy: qcom,*-qmp-ufs-phy: add clock-cells property
  2022-11-10 15:17 ` Dmitry Baryshkov
@ 2022-11-10 15:17   ` Dmitry Baryshkov
  -1 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 15:17 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

Add #clock-cells property to the QMP UFS PHYs to describe them as clock
providers. The QMP PHY provides rx and tx symbol clocks for the GCC.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml      | 3 +++
 .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml     | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
index be41acbd3b6c..80a5348dbfde 100644
--- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
@@ -75,6 +75,9 @@ patternProperties:
         minItems: 3
         maxItems: 6
 
+      "#clock-cells":
+        const: 1
+
       "#phy-cells":
         const: 0
 
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index dde86a19f792..32ed1886fbae 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -43,6 +43,9 @@ properties:
 
   vdda-pll-supply: true
 
+  "#clock-cells":
+    const: 1
+
   "#phy-cells":
     const: 0
 
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v7 1/4] dt-bindings: phy: qcom,*-qmp-ufs-phy: add clock-cells property
@ 2022-11-10 15:17   ` Dmitry Baryshkov
  0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 15:17 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

Add #clock-cells property to the QMP UFS PHYs to describe them as clock
providers. The QMP PHY provides rx and tx symbol clocks for the GCC.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml      | 3 +++
 .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml     | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
index be41acbd3b6c..80a5348dbfde 100644
--- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml
@@ -75,6 +75,9 @@ patternProperties:
         minItems: 3
         maxItems: 6
 
+      "#clock-cells":
+        const: 1
+
       "#phy-cells":
         const: 0
 
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index dde86a19f792..32ed1886fbae 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -43,6 +43,9 @@ properties:
 
   vdda-pll-supply: true
 
+  "#clock-cells":
+    const: 1
+
   "#phy-cells":
     const: 0
 
-- 
2.35.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v7 2/4] phy: qcom-qmp-ufs: provide symbol clocks
  2022-11-10 15:17 ` Dmitry Baryshkov
@ 2022-11-10 15:17   ` Dmitry Baryshkov
  -1 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 15:17 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

Register three UFS symbol clocks (ufs_rx_symbol_0_clk_src,
ufs_rx_symbol_1_clk_src ufs_tx_symbol_0_clk_src). Register OF clock
provider to let other devices link these clocks through the DT.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 64 +++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 189103d1bd18..78d7daf34667 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -1023,6 +1023,66 @@ static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
 	return devm_clk_bulk_get(dev, num, qmp->clks);
 }
 
+static void phy_clk_release_provider(void *res)
+{
+	of_clk_del_provider(res);
+}
+
+#define UFS_SYMBOL_CLOCKS 3
+
+static int phy_symbols_clk_register(struct qmp_ufs *qmp, struct device_node *np)
+{
+	struct clk_hw_onecell_data *clk_data;
+	struct clk_hw *hw;
+	char name[64];
+	int ret;
+
+	clk_data = devm_kzalloc(qmp->dev,
+				struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
+				GFP_KERNEL);
+	if (!clk_data)
+		return -ENOMEM;
+
+	clk_data->num = UFS_SYMBOL_CLOCKS;
+
+	snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
+	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
+	clk_data->hws[0] = hw;
+
+	snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
+	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
+	clk_data->hws[1] = hw;
+
+	snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
+	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
+	clk_data->hws[2] = hw;
+
+	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+	if (ret)
+		return ret;
+
+	/*
+	 * Roll a devm action because the clock provider is the child node, but
+	 * the child node is not actually a device.
+	 */
+	return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
+}
+
+static const struct phy_ops qcom_qmp_ufs_ops = {
+	.power_on	= qmp_ufs_enable,
+	.power_off	= qmp_ufs_disable,
+	.owner		= THIS_MODULE,
+};
+
 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
 {
 	struct platform_device *pdev = to_platform_device(qmp->dev);
@@ -1135,6 +1195,10 @@ static int qmp_ufs_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_node_put;
 
+	ret = phy_symbols_clk_register(qmp, np);
+	if (ret)
+		goto err_node_put;
+
 	qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
 	if (IS_ERR(qmp->phy)) {
 		ret = PTR_ERR(qmp->phy);
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v7 2/4] phy: qcom-qmp-ufs: provide symbol clocks
@ 2022-11-10 15:17   ` Dmitry Baryshkov
  0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 15:17 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

Register three UFS symbol clocks (ufs_rx_symbol_0_clk_src,
ufs_rx_symbol_1_clk_src ufs_tx_symbol_0_clk_src). Register OF clock
provider to let other devices link these clocks through the DT.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 64 +++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 189103d1bd18..78d7daf34667 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -1023,6 +1023,66 @@ static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
 	return devm_clk_bulk_get(dev, num, qmp->clks);
 }
 
+static void phy_clk_release_provider(void *res)
+{
+	of_clk_del_provider(res);
+}
+
+#define UFS_SYMBOL_CLOCKS 3
+
+static int phy_symbols_clk_register(struct qmp_ufs *qmp, struct device_node *np)
+{
+	struct clk_hw_onecell_data *clk_data;
+	struct clk_hw *hw;
+	char name[64];
+	int ret;
+
+	clk_data = devm_kzalloc(qmp->dev,
+				struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
+				GFP_KERNEL);
+	if (!clk_data)
+		return -ENOMEM;
+
+	clk_data->num = UFS_SYMBOL_CLOCKS;
+
+	snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
+	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
+	clk_data->hws[0] = hw;
+
+	snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
+	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
+	clk_data->hws[1] = hw;
+
+	snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
+	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
+	if (IS_ERR(hw))
+		return PTR_ERR(hw);
+
+	clk_data->hws[2] = hw;
+
+	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
+	if (ret)
+		return ret;
+
+	/*
+	 * Roll a devm action because the clock provider is the child node, but
+	 * the child node is not actually a device.
+	 */
+	return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
+}
+
+static const struct phy_ops qcom_qmp_ufs_ops = {
+	.power_on	= qmp_ufs_enable,
+	.power_off	= qmp_ufs_disable,
+	.owner		= THIS_MODULE,
+};
+
 static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
 {
 	struct platform_device *pdev = to_platform_device(qmp->dev);
@@ -1135,6 +1195,10 @@ static int qmp_ufs_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_node_put;
 
+	ret = phy_symbols_clk_register(qmp, np);
+	if (ret)
+		goto err_node_put;
+
 	qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
 	if (IS_ERR(qmp->phy)) {
 		ret = PTR_ERR(qmp->phy);
-- 
2.35.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v7 3/4] arm64: dts: qcom: sm8450: fix gcc clocks order to follow the schema
  2022-11-10 15:17 ` Dmitry Baryshkov
@ 2022-11-10 15:17   ` Dmitry Baryshkov
  -1 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 15:17 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

Move the sleep_clk to make sure the gcc device node follows the schema.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index d32f08df743d..efb01fefe9c7 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -720,13 +720,13 @@ gcc: clock-controller@100000 {
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>,
 				 <&pcie0_lane>,
-				 <&pcie1_lane>,
-				 <&sleep_clk>;
+				 <&pcie1_lane>;
 			clock-names = "bi_tcxo",
+				      "sleep_clk",
 				      "pcie_0_pipe_clk",
-				      "pcie_1_pipe_clk",
-				      "sleep_clk";
+				      "pcie_1_pipe_clk";
 		};
 
 		gpi_dma2: dma-controller@800000 {
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v7 3/4] arm64: dts: qcom: sm8450: fix gcc clocks order to follow the schema
@ 2022-11-10 15:17   ` Dmitry Baryshkov
  0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 15:17 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

Move the sleep_clk to make sure the gcc device node follows the schema.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index d32f08df743d..efb01fefe9c7 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -720,13 +720,13 @@ gcc: clock-controller@100000 {
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
+				 <&sleep_clk>,
 				 <&pcie0_lane>,
-				 <&pcie1_lane>,
-				 <&sleep_clk>;
+				 <&pcie1_lane>;
 			clock-names = "bi_tcxo",
+				      "sleep_clk",
 				      "pcie_0_pipe_clk",
-				      "pcie_1_pipe_clk",
-				      "sleep_clk";
+				      "pcie_1_pipe_clk";
 		};
 
 		gpi_dma2: dma-controller@800000 {
-- 
2.35.1


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v7 4/4] arm64: dts: qcom: use UFS symbol clocks provided by PHY
  2022-11-10 15:17 ` Dmitry Baryshkov
@ 2022-11-10 15:17   ` Dmitry Baryshkov
  -1 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 15:17 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

Remove manually created symbol clocks and replace them with clocks
provided by PHY.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi |  5 ++++-
 arch/arm64/boot/dts/qcom/sm8350.dtsi  | 25 ++++---------------------
 arch/arm64/boot/dts/qcom/sm8450.dtsi  | 15 +++++++++++++--
 3 files changed, 21 insertions(+), 24 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c0a2baffa49d..935ba6e6bc15 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -699,7 +699,9 @@ gcc: clock-controller@300000 {
 				 <&pciephy_1>,
 				 <&pciephy_2>,
 				 <&ssusb_phy_0>,
-				 <0>, <0>, <0>;
+				 <&ufsphy_lane 0>,
+				 <&ufsphy_lane 1>,
+				 <&ufsphy_lane 2>;
 			clock-names = "cxo",
 				      "cxo2",
 				      "sleep_clk",
@@ -2019,6 +2021,7 @@ ufsphy_lane: phy@627400 {
 				reg = <0x627400 0x12c>,
 				      <0x627600 0x200>,
 				      <0x627c00 0x1b4>;
+				#clock-cells = <1>;
 				#phy-cells = <0>;
 			};
 		};
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 90a26f406bf3..51ca006dc5c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -37,24 +37,6 @@ sleep_clk: sleep-clk {
 			clock-frequency = <32000>;
 			#clock-cells = <0>;
 		};
-
-		ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
-			compatible = "fixed-clock";
-			clock-frequency = <1000>;
-			#clock-cells = <0>;
-		};
-
-		ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
-			compatible = "fixed-clock";
-			clock-frequency = <1000>;
-			#clock-cells = <0>;
-		};
-
-		ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
-			compatible = "fixed-clock";
-			clock-frequency = <1000>;
-			#clock-cells = <0>;
-		};
 	};
 
 	cpus {
@@ -661,9 +643,9 @@ gcc: clock-controller@100000 {
 				 <0>,
 				 <0>,
 				 <0>,
-				 <&ufs_phy_rx_symbol_0_clk>,
-				 <&ufs_phy_rx_symbol_1_clk>,
-				 <&ufs_phy_tx_symbol_0_clk>,
+				 <&ufs_mem_phy_lanes 0>,
+				 <&ufs_mem_phy_lanes 1>,
+				 <&ufs_mem_phy_lanes 2>,
 				 <0>,
 				 <0>;
 		};
@@ -2389,6 +2371,7 @@ ufs_mem_phy_lanes: phy@1d87400 {
 				      <0 0x01d87c00 0 0x1dc>,
 				      <0 0x01d87800 0 0x108>,
 				      <0 0x01d87a00 0 0x1e0>;
+				#clock-cells = <1>;
 				#phy-cells = <0>;
 			};
 		};
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index efb01fefe9c7..95c01391972a 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -722,11 +722,21 @@ gcc: clock-controller@100000 {
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&sleep_clk>,
 				 <&pcie0_lane>,
-				 <&pcie1_lane>;
+				 <&pcie1_lane>,
+				 <0>,
+				 <&ufs_mem_phy_lanes 0>,
+				 <&ufs_mem_phy_lanes 1>,
+				 <&ufs_mem_phy_lanes 2>,
+				 <0>;
 			clock-names = "bi_tcxo",
 				      "sleep_clk",
 				      "pcie_0_pipe_clk",
-				      "pcie_1_pipe_clk";
+				      "pcie_1_pipe_clk",
+				      "pcie_1_phy_aux_clk",
+				      "ufs_phy_rx_symbol_0_clk",
+				      "ufs_phy_rx_symbol_1_clk",
+				      "ufs_phy_tx_symbol_0_clk",
+				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 		};
 
 		gpi_dma2: dma-controller@800000 {
@@ -3166,6 +3176,7 @@ ufs_mem_phy_lanes: phy@1d87400 {
 				      <0 0x01d87c00 0 0x1dc>,
 				      <0 0x01d87800 0 0x108>,
 				      <0 0x01d87a00 0 0x1e0>;
+				#clock-cells = <1>;
 				#phy-cells = <0>;
 			};
 		};
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 20+ messages in thread
* [PATCH v7 4/4] arm64: dts: qcom: use UFS symbol clocks provided by PHY
@ 2022-11-10 15:17   ` Dmitry Baryshkov
  0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-10 15:17 UTC (permalink / raw)
  To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

Remove manually created symbol clocks and replace them with clocks
provided by PHY.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8996.dtsi |  5 ++++-
 arch/arm64/boot/dts/qcom/sm8350.dtsi  | 25 ++++---------------------
 arch/arm64/boot/dts/qcom/sm8450.dtsi  | 15 +++++++++++++--
 3 files changed, 21 insertions(+), 24 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index c0a2baffa49d..935ba6e6bc15 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -699,7 +699,9 @@ gcc: clock-controller@300000 {
 				 <&pciephy_1>,
 				 <&pciephy_2>,
 				 <&ssusb_phy_0>,
-				 <0>, <0>, <0>;
+				 <&ufsphy_lane 0>,
+				 <&ufsphy_lane 1>,
+				 <&ufsphy_lane 2>;
 			clock-names = "cxo",
 				      "cxo2",
 				      "sleep_clk",
@@ -2019,6 +2021,7 @@ ufsphy_lane: phy@627400 {
 				reg = <0x627400 0x12c>,
 				      <0x627600 0x200>,
 				      <0x627c00 0x1b4>;
+				#clock-cells = <1>;
 				#phy-cells = <0>;
 			};
 		};
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 90a26f406bf3..51ca006dc5c1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -37,24 +37,6 @@ sleep_clk: sleep-clk {
 			clock-frequency = <32000>;
 			#clock-cells = <0>;
 		};
-
-		ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
-			compatible = "fixed-clock";
-			clock-frequency = <1000>;
-			#clock-cells = <0>;
-		};
-
-		ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
-			compatible = "fixed-clock";
-			clock-frequency = <1000>;
-			#clock-cells = <0>;
-		};
-
-		ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
-			compatible = "fixed-clock";
-			clock-frequency = <1000>;
-			#clock-cells = <0>;
-		};
 	};
 
 	cpus {
@@ -661,9 +643,9 @@ gcc: clock-controller@100000 {
 				 <0>,
 				 <0>,
 				 <0>,
-				 <&ufs_phy_rx_symbol_0_clk>,
-				 <&ufs_phy_rx_symbol_1_clk>,
-				 <&ufs_phy_tx_symbol_0_clk>,
+				 <&ufs_mem_phy_lanes 0>,
+				 <&ufs_mem_phy_lanes 1>,
+				 <&ufs_mem_phy_lanes 2>,
 				 <0>,
 				 <0>;
 		};
@@ -2389,6 +2371,7 @@ ufs_mem_phy_lanes: phy@1d87400 {
 				      <0 0x01d87c00 0 0x1dc>,
 				      <0 0x01d87800 0 0x108>,
 				      <0 0x01d87a00 0 0x1e0>;
+				#clock-cells = <1>;
 				#phy-cells = <0>;
 			};
 		};
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index efb01fefe9c7..95c01391972a 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -722,11 +722,21 @@ gcc: clock-controller@100000 {
 			clocks = <&rpmhcc RPMH_CXO_CLK>,
 				 <&sleep_clk>,
 				 <&pcie0_lane>,
-				 <&pcie1_lane>;
+				 <&pcie1_lane>,
+				 <0>,
+				 <&ufs_mem_phy_lanes 0>,
+				 <&ufs_mem_phy_lanes 1>,
+				 <&ufs_mem_phy_lanes 2>,
+				 <0>;
 			clock-names = "bi_tcxo",
 				      "sleep_clk",
 				      "pcie_0_pipe_clk",
-				      "pcie_1_pipe_clk";
+				      "pcie_1_pipe_clk",
+				      "pcie_1_phy_aux_clk",
+				      "ufs_phy_rx_symbol_0_clk",
+				      "ufs_phy_rx_symbol_1_clk",
+				      "ufs_phy_tx_symbol_0_clk",
+				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
 		};
 
 		gpi_dma2: dma-controller@800000 {
@@ -3166,6 +3176,7 @@ ufs_mem_phy_lanes: phy@1d87400 {
 				      <0 0x01d87c00 0 0x1dc>,
 				      <0 0x01d87800 0 0x108>,
 				      <0 0x01d87a00 0 0x1e0>;
+				#clock-cells = <1>;
 				#phy-cells = <0>;
 			};
 		};
-- 
2.35.1


-- 
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply related	[flat|nested] 20+ messages in thread
* Re: [PATCH v7 1/4] dt-bindings: phy: qcom,*-qmp-ufs-phy: add clock-cells property
  2022-11-10 15:17   ` Dmitry Baryshkov
@ 2022-11-10 15:18     ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-10 15:18 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

On 10/11/2022 16:17, Dmitry Baryshkov wrote:
> Add #clock-cells property to the QMP UFS PHYs to describe them as clock
> providers. The QMP PHY provides rx and tx symbol clocks for the GCC.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml      | 3 +++
>  .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml     | 3 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v7 1/4] dt-bindings: phy: qcom,*-qmp-ufs-phy: add clock-cells property
@ 2022-11-10 15:18     ` Krzysztof Kozlowski
  0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-10 15:18 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Konrad Dybcio,
	Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree

On 10/11/2022 16:17, Dmitry Baryshkov wrote:
> Add #clock-cells property to the QMP UFS PHYs to describe them as clock
> providers. The QMP PHY provides rx and tx symbol clocks for the GCC.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml      | 3 +++
>  .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml     | 3 


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v7 3/4] arm64: dts: qcom: sm8450: fix gcc clocks order to follow the schema
  2022-11-10 15:17   ` Dmitry Baryshkov
@ 2022-11-10 15:21     ` Konrad Dybcio
  -1 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2022-11-10 15:21 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree



On 10/11/2022 16:17, Dmitry Baryshkov wrote:
> Move the sleep_clk to make sure the gcc device node follows the schema.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>   arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index d32f08df743d..efb01fefe9c7 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -720,13 +720,13 @@ gcc: clock-controller@100000 {
>   			#reset-cells = <1>;
>   			#power-domain-cells = <1>;
>   			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&sleep_clk>,
>   				 <&pcie0_lane>,
> -				 <&pcie1_lane>,
> -				 <&sleep_clk>;
> +				 <&pcie1_lane>;
>   			clock-names = "bi_tcxo",
> +				      "sleep_clk",
>   				      "pcie_0_pipe_clk",
> -				      "pcie_1_pipe_clk",
> -				      "sleep_clk";
> +				      "pcie_1_pipe_clk";
>   		};
>   
>   		gpi_dma2: dma-controller@800000 {

^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v7 3/4] arm64: dts: qcom: sm8450: fix gcc clocks order to follow the schema
@ 2022-11-10 15:21     ` Konrad Dybcio
  0 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2022-11-10 15:21 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree



On 10/11/2022 16:17, Dmitry Baryshkov wrote:
> Move the sleep_clk to make sure the gcc device node follows the schema.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>   arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index d32f08df743d..efb01fefe9c7 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -720,13 +720,13 @@ gcc: clock-controller@100000 {
>   			#reset-cells = <1>;
>   			#power-domain-cells = <1>;
>   			clocks = <&rpmhcc RPMH_CXO_CLK>,
> +				 <&sleep_clk>,
>   				 <&pcie0_lane>,
> -				 <&pcie1_lane>,
> -				 <&sleep_clk>;
> +				 <&pcie1_lane>;
>   			clock-names = "bi_tcxo",
> +				      "sleep_clk",
>   				      "pcie_0_pipe_clk",
> -				      "pcie_1_pipe_clk",
> -				      "sleep_clk";
> +				      "pcie_1_pipe_clk";
>   		};
>   
>   		gpi_dma2: dma-controller@800000 {

-- 
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^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v7 4/4] arm64: dts: qcom: use UFS symbol clocks provided by PHY
  2022-11-10 15:17   ` Dmitry Baryshkov
@ 2022-11-10 15:26     ` Konrad Dybcio
  -1 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2022-11-10 15:26 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree



On 10/11/2022 16:17, Dmitry Baryshkov wrote:
> Remove manually created symbol clocks and replace them with clocks
> provided by PHY.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Maybe it would be worth exporting some #defines for these incides so 
that it's less likely for the next person referencing these DTs to make 
a mistake, but that could be done in a separate patch. Something similar 
could probably be useful for DSI BYTE/PIXEL clk


Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>   arch/arm64/boot/dts/qcom/msm8996.dtsi |  5 ++++-
>   arch/arm64/boot/dts/qcom/sm8350.dtsi  | 25 ++++---------------------
>   arch/arm64/boot/dts/qcom/sm8450.dtsi  | 15 +++++++++++++--
>   3 files changed, 21 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index c0a2baffa49d..935ba6e6bc15 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -699,7 +699,9 @@ gcc: clock-controller@300000 {
>   				 <&pciephy_1>,
>   				 <&pciephy_2>,
>   				 <&ssusb_phy_0>,
> -				 <0>, <0>, <0>;
> +				 <&ufsphy_lane 0>,
> +				 <&ufsphy_lane 1>,
> +				 <&ufsphy_lane 2>;
>   			clock-names = "cxo",
>   				      "cxo2",
>   				      "sleep_clk",
> @@ -2019,6 +2021,7 @@ ufsphy_lane: phy@627400 {
>   				reg = <0x627400 0x12c>,
>   				      <0x627600 0x200>,
>   				      <0x627c00 0x1b4>;
> +				#clock-cells = <1>;
>   				#phy-cells = <0>;
>   			};
>   		};
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 90a26f406bf3..51ca006dc5c1 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -37,24 +37,6 @@ sleep_clk: sleep-clk {
>   			clock-frequency = <32000>;
>   			#clock-cells = <0>;
>   		};
> -
> -		ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
> -			compatible = "fixed-clock";
> -			clock-frequency = <1000>;
> -			#clock-cells = <0>;
> -		};
> -
> -		ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
> -			compatible = "fixed-clock";
> -			clock-frequency = <1000>;
> -			#clock-cells = <0>;
> -		};
> -
> -		ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
> -			compatible = "fixed-clock";
> -			clock-frequency = <1000>;
> -			#clock-cells = <0>;
> -		};
>   	};
>   
>   	cpus {
> @@ -661,9 +643,9 @@ gcc: clock-controller@100000 {
>   				 <0>,
>   				 <0>,
>   				 <0>,
> -				 <&ufs_phy_rx_symbol_0_clk>,
> -				 <&ufs_phy_rx_symbol_1_clk>,
> -				 <&ufs_phy_tx_symbol_0_clk>,
> +				 <&ufs_mem_phy_lanes 0>,
> +				 <&ufs_mem_phy_lanes 1>,
> +				 <&ufs_mem_phy_lanes 2>,
>   				 <0>,
>   				 <0>;
>   		};
> @@ -2389,6 +2371,7 @@ ufs_mem_phy_lanes: phy@1d87400 {
>   				      <0 0x01d87c00 0 0x1dc>,
>   				      <0 0x01d87800 0 0x108>,
>   				      <0 0x01d87a00 0 0x1e0>;
> +				#clock-cells = <1>;
>   				#phy-cells = <0>;
>   			};
>   		};
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index efb01fefe9c7..95c01391972a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -722,11 +722,21 @@ gcc: clock-controller@100000 {
>   			clocks = <&rpmhcc RPMH_CXO_CLK>,
>   				 <&sleep_clk>,
>   				 <&pcie0_lane>,
> -				 <&pcie1_lane>;
> +				 <&pcie1_lane>,
> +				 <0>,
> +				 <&ufs_mem_phy_lanes 0>,
> +				 <&ufs_mem_phy_lanes 1>,
> +				 <&ufs_mem_phy_lanes 2>,
> +				 <0>;
>   			clock-names = "bi_tcxo",
>   				      "sleep_clk",
>   				      "pcie_0_pipe_clk",
> -				      "pcie_1_pipe_clk";
> +				      "pcie_1_pipe_clk",
> +				      "pcie_1_phy_aux_clk",
> +				      "ufs_phy_rx_symbol_0_clk",
> +				      "ufs_phy_rx_symbol_1_clk",
> +				      "ufs_phy_tx_symbol_0_clk",
> +				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
>   		};
>   
>   		gpi_dma2: dma-controller@800000 {
> @@ -3166,6 +3176,7 @@ ufs_mem_phy_lanes: phy@1d87400 {
>   				      <0 0x01d87c00 0 0x1dc>,
>   				      <0 0x01d87800 0 0x108>,
>   				      <0 0x01d87a00 0 0x1e0>;
> +				#clock-cells = <1>;
>   				#phy-cells = <0>;
>   			};
>   		};

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v7 4/4] arm64: dts: qcom: use UFS symbol clocks provided by PHY
@ 2022-11-10 15:26     ` Konrad Dybcio
  0 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2022-11-10 15:26 UTC (permalink / raw)
  To: Dmitry Baryshkov, Andy Gross, Bjorn Andersson, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski
  Cc: Philipp Zabel, linux-arm-msm, linux-phy, devicetree



On 10/11/2022 16:17, Dmitry Baryshkov wrote:
> Remove manually created symbol clocks and replace them with clocks
> provided by PHY.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Maybe it would be worth exporting some #defines for these incides so 
that it's less likely for the next person referencing these DTs to make 
a mistake, but that could be done in a separate patch. Something similar 
could probably be useful for DSI BYTE/PIXEL clk


Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>   arch/arm64/boot/dts/qcom/msm8996.dtsi |  5 ++++-
>   arch/arm64/boot/dts/qcom/sm8350.dtsi  | 25 ++++---------------------
>   arch/arm64/boot/dts/qcom/sm8450.dtsi  | 15 +++++++++++++--
>   3 files changed, 21 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index c0a2baffa49d..935ba6e6bc15 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -699,7 +699,9 @@ gcc: clock-controller@300000 {
>   				 <&pciephy_1>,
>   				 <&pciephy_2>,
>   				 <&ssusb_phy_0>,
> -				 <0>, <0>, <0>;
> +				 <&ufsphy_lane 0>,
> +				 <&ufsphy_lane 1>,
> +				 <&ufsphy_lane 2>;
>   			clock-names = "cxo",
>   				      "cxo2",
>   				      "sleep_clk",
> @@ -2019,6 +2021,7 @@ ufsphy_lane: phy@627400 {
>   				reg = <0x627400 0x12c>,
>   				      <0x627600 0x200>,
>   				      <0x627c00 0x1b4>;
> +				#clock-cells = <1>;
>   				#phy-cells = <0>;
>   			};
>   		};
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 90a26f406bf3..51ca006dc5c1 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -37,24 +37,6 @@ sleep_clk: sleep-clk {
>   			clock-frequency = <32000>;
>   			#clock-cells = <0>;
>   		};
> -
> -		ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 {
> -			compatible = "fixed-clock";
> -			clock-frequency = <1000>;
> -			#clock-cells = <0>;
> -		};
> -
> -		ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 {
> -			compatible = "fixed-clock";
> -			clock-frequency = <1000>;
> -			#clock-cells = <0>;
> -		};
> -
> -		ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 {
> -			compatible = "fixed-clock";
> -			clock-frequency = <1000>;
> -			#clock-cells = <0>;
> -		};
>   	};
>   
>   	cpus {
> @@ -661,9 +643,9 @@ gcc: clock-controller@100000 {
>   				 <0>,
>   				 <0>,
>   				 <0>,
> -				 <&ufs_phy_rx_symbol_0_clk>,
> -				 <&ufs_phy_rx_symbol_1_clk>,
> -				 <&ufs_phy_tx_symbol_0_clk>,
> +				 <&ufs_mem_phy_lanes 0>,
> +				 <&ufs_mem_phy_lanes 1>,
> +				 <&ufs_mem_phy_lanes 2>,
>   				 <0>,
>   				 <0>;
>   		};
> @@ -2389,6 +2371,7 @@ ufs_mem_phy_lanes: phy@1d87400 {
>   				      <0 0x01d87c00 0 0x1dc>,
>   				      <0 0x01d87800 0 0x108>,
>   				      <0 0x01d87a00 0 0x1e0>;
> +				#clock-cells = <1>;
>   				#phy-cells = <0>;
>   			};
>   		};
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index efb01fefe9c7..95c01391972a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -722,11 +722,21 @@ gcc: clock-controller@100000 {
>   			clocks = <&rpmhcc RPMH_CXO_CLK>,
>   				 <&sleep_clk>,
>   				 <&pcie0_lane>,
> -				 <&pcie1_lane>;
> +				 <&pcie1_lane>,
> +				 <0>,
> +				 <&ufs_mem_phy_lanes 0>,
> +				 <&ufs_mem_phy_lanes 1>,
> +				 <&ufs_mem_phy_lanes 2>,
> +				 <0>;
>   			clock-names = "bi_tcxo",
>   				      "sleep_clk",
>   				      "pcie_0_pipe_clk",
> -				      "pcie_1_pipe_clk";
> +				      "pcie_1_pipe_clk",
> +				      "pcie_1_phy_aux_clk",
> +				      "ufs_phy_rx_symbol_0_clk",
> +				      "ufs_phy_rx_symbol_1_clk",
> +				      "ufs_phy_tx_symbol_0_clk",
> +				      "usb3_phy_wrapper_gcc_usb30_pipe_clk";
>   		};
>   
>   		gpi_dma2: dma-controller@800000 {
> @@ -3166,6 +3176,7 @@ ufs_mem_phy_lanes: phy@1d87400 {
>   				      <0 0x01d87c00 0 0x1dc>,
>   				      <0 0x01d87800 0 0x108>,
>   				      <0 0x01d87a00 0 0x1e0>;
> +				#clock-cells = <1>;
>   				#phy-cells = <0>;
>   			};
>   		};

^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v7 2/4] phy: qcom-qmp-ufs: provide symbol clocks
  2022-11-10 15:17   ` Dmitry Baryshkov
@ 2022-11-16 15:15     ` Johan Hovold
  -1 siblings, 0 replies; 20+ messages in thread
From: Johan Hovold @ 2022-11-16 15:15 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
	Philipp Zabel, linux-arm-msm, linux-phy, devicetree

On Thu, Nov 10, 2022 at 06:17:46PM +0300, Dmitry Baryshkov wrote:
> Register three UFS symbol clocks (ufs_rx_symbol_0_clk_src,
> ufs_rx_symbol_1_clk_src ufs_tx_symbol_0_clk_src). Register OF clock
> provider to let other devices link these clocks through the DT.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---

I was not CCed on this revision of this series either.

>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 64 +++++++++++++++++++++++++
>  1 file changed, 64 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 189103d1bd18..78d7daf34667 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -1023,6 +1023,66 @@ static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
>  	return devm_clk_bulk_get(dev, num, qmp->clks);
>  }
>  
> +static void phy_clk_release_provider(void *res)
> +{
> +	of_clk_del_provider(res);
> +}
> +
> +#define UFS_SYMBOL_CLOCKS 3
> +
> +static int phy_symbols_clk_register(struct qmp_ufs *qmp, struct device_node *np)

Since you're adding a new function, please use the common prefix and
reordering the terms and dropping the redundant "symbols" should make it
more readable:

	qmp_ufs_register_clocks()

> +{
> +	struct clk_hw_onecell_data *clk_data;
> +	struct clk_hw *hw;
> +	char name[64];
> +	int ret;
> +
> +	clk_data = devm_kzalloc(qmp->dev,
> +				struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
> +				GFP_KERNEL);
> +	if (!clk_data)
> +		return -ENOMEM;
> +
> +	clk_data->num = UFS_SYMBOL_CLOCKS;
> +
> +	snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +
> +	clk_data->hws[0] = hw;
> +
> +	snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +
> +	clk_data->hws[1] = hw;
> +
> +	snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +
> +	clk_data->hws[2] = hw;
> +
> +	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Roll a devm action because the clock provider is the child node, but
> +	 * the child node is not actually a device.
> +	 */

I know you just copied this from one of the other drivers, but perhaps
rephrase as "can be a child node". You can just drop the second clause
(no node *is* a device).

> +	return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +static const struct phy_ops qcom_qmp_ufs_ops = {
> +	.power_on	= qmp_ufs_enable,
> +	.power_off	= qmp_ufs_disable,
> +	.owner		= THIS_MODULE,
> +};

As I've already pointed out once, the above phy_ops struct hunk does not
belong in this patch and is just some left over after you rebased on
phy-next that must be removed.

>  static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
>  {
>  	struct platform_device *pdev = to_platform_device(qmp->dev);
> @@ -1135,6 +1195,10 @@ static int qmp_ufs_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto err_node_put;
>  
> +	ret = phy_symbols_clk_register(qmp, np);
> +	if (ret)
> +		goto err_node_put;
> +
>  	qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
>  	if (IS_ERR(qmp->phy)) {
>  		ret = PTR_ERR(qmp->phy);

Johan

^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v7 2/4] phy: qcom-qmp-ufs: provide symbol clocks
@ 2022-11-16 15:15     ` Johan Hovold
  0 siblings, 0 replies; 20+ messages in thread
From: Johan Hovold @ 2022-11-16 15:15 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
	Philipp Zabel, linux-arm-msm, linux-phy, devicetree

On Thu, Nov 10, 2022 at 06:17:46PM +0300, Dmitry Baryshkov wrote:
> Register three UFS symbol clocks (ufs_rx_symbol_0_clk_src,
> ufs_rx_symbol_1_clk_src ufs_tx_symbol_0_clk_src). Register OF clock
> provider to let other devices link these clocks through the DT.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---

I was not CCed on this revision of this series either.

>  drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 64 +++++++++++++++++++++++++
>  1 file changed, 64 insertions(+)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> index 189103d1bd18..78d7daf34667 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
> @@ -1023,6 +1023,66 @@ static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
>  	return devm_clk_bulk_get(dev, num, qmp->clks);
>  }
>  
> +static void phy_clk_release_provider(void *res)
> +{
> +	of_clk_del_provider(res);
> +}
> +
> +#define UFS_SYMBOL_CLOCKS 3
> +
> +static int phy_symbols_clk_register(struct qmp_ufs *qmp, struct device_node *np)

Since you're adding a new function, please use the common prefix and
reordering the terms and dropping the redundant "symbols" should make it
more readable:

	qmp_ufs_register_clocks()

> +{
> +	struct clk_hw_onecell_data *clk_data;
> +	struct clk_hw *hw;
> +	char name[64];
> +	int ret;
> +
> +	clk_data = devm_kzalloc(qmp->dev,
> +				struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
> +				GFP_KERNEL);
> +	if (!clk_data)
> +		return -ENOMEM;
> +
> +	clk_data->num = UFS_SYMBOL_CLOCKS;
> +
> +	snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +
> +	clk_data->hws[0] = hw;
> +
> +	snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +
> +	clk_data->hws[1] = hw;
> +
> +	snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
> +	if (IS_ERR(hw))
> +		return PTR_ERR(hw);
> +
> +	clk_data->hws[2] = hw;
> +
> +	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
> +	if (ret)
> +		return ret;
> +
> +	/*
> +	 * Roll a devm action because the clock provider is the child node, but
> +	 * the child node is not actually a device.
> +	 */

I know you just copied this from one of the other drivers, but perhaps
rephrase as "can be a child node". You can just drop the second clause
(no node *is* a device).

> +	return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
> +}
> +
> +static const struct phy_ops qcom_qmp_ufs_ops = {
> +	.power_on	= qmp_ufs_enable,
> +	.power_off	= qmp_ufs_disable,
> +	.owner		= THIS_MODULE,
> +};

As I've already pointed out once, the above phy_ops struct hunk does not
belong in this patch and is just some left over after you rebased on
phy-next that must be removed.

>  static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
>  {
>  	struct platform_device *pdev = to_platform_device(qmp->dev);
> @@ -1135,6 +1195,10 @@ static int qmp_ufs_probe(struct platform_device *pdev)
>  	if (ret)
>  		goto err_node_put;
>  
> +	ret = phy_symbols_clk_register(qmp, np);
> +	if (ret)
> +		goto err_node_put;
> +
>  	qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
>  	if (IS_ERR(qmp->phy)) {
>  		ret = PTR_ERR(qmp->phy);

Johan

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v7 2/4] phy: qcom-qmp-ufs: provide symbol clocks
  2022-11-16 15:15     ` Johan Hovold
@ 2022-11-16 15:21       ` Dmitry Baryshkov
  -1 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-16 15:21 UTC (permalink / raw)
  To: Johan Hovold
  Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
	Philipp Zabel, linux-arm-msm, linux-phy, devicetree

On 16/11/2022 18:15, Johan Hovold wrote:
> On Thu, Nov 10, 2022 at 06:17:46PM +0300, Dmitry Baryshkov wrote:
>> Register three UFS symbol clocks (ufs_rx_symbol_0_clk_src,
>> ufs_rx_symbol_1_clk_src ufs_tx_symbol_0_clk_src). Register OF clock
>> provider to let other devices link these clocks through the DT.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
> 
> I was not CCed on this revision of this series either.
> 
>>   drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 64 +++++++++++++++++++++++++
>>   1 file changed, 64 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> index 189103d1bd18..78d7daf34667 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> @@ -1023,6 +1023,66 @@ static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
>>   	return devm_clk_bulk_get(dev, num, qmp->clks);
>>   }
>>   
>> +static void phy_clk_release_provider(void *res)
>> +{
>> +	of_clk_del_provider(res);
>> +}
>> +
>> +#define UFS_SYMBOL_CLOCKS 3
>> +
>> +static int phy_symbols_clk_register(struct qmp_ufs *qmp, struct device_node *np)
> 
> Since you're adding a new function, please use the common prefix and
> reordering the terms and dropping the redundant "symbols" should make it
> more readable:
> 
> 	qmp_ufs_register_clocks()
> 
>> +{
>> +	struct clk_hw_onecell_data *clk_data;
>> +	struct clk_hw *hw;
>> +	char name[64];
>> +	int ret;
>> +
>> +	clk_data = devm_kzalloc(qmp->dev,
>> +				struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
>> +				GFP_KERNEL);
>> +	if (!clk_data)
>> +		return -ENOMEM;
>> +
>> +	clk_data->num = UFS_SYMBOL_CLOCKS;
>> +
>> +	snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
>> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
>> +	if (IS_ERR(hw))
>> +		return PTR_ERR(hw);
>> +
>> +	clk_data->hws[0] = hw;
>> +
>> +	snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
>> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
>> +	if (IS_ERR(hw))
>> +		return PTR_ERR(hw);
>> +
>> +	clk_data->hws[1] = hw;
>> +
>> +	snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
>> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
>> +	if (IS_ERR(hw))
>> +		return PTR_ERR(hw);
>> +
>> +	clk_data->hws[2] = hw;
>> +
>> +	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/*
>> +	 * Roll a devm action because the clock provider is the child node, but
>> +	 * the child node is not actually a device.
>> +	 */
> 
> I know you just copied this from one of the other drivers, but perhaps
> rephrase as "can be a child node". You can just drop the second clause
> (no node *is* a device).

Ack, thanks for the suggestion.

> 
>> +	return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
>> +}
>> +
>> +static const struct phy_ops qcom_qmp_ufs_ops = {
>> +	.power_on	= qmp_ufs_enable,
>> +	.power_off	= qmp_ufs_disable,
>> +	.owner		= THIS_MODULE,
>> +};
> 
> As I've already pointed out once, the above phy_ops struct hunk does not
> belong in this patch and is just some left over after you rebased on
> phy-next that must be removed.

Oops. I'll fix this during the next respin.

> 
>>   static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
>>   {
>>   	struct platform_device *pdev = to_platform_device(qmp->dev);
>> @@ -1135,6 +1195,10 @@ static int qmp_ufs_probe(struct platform_device *pdev)
>>   	if (ret)
>>   		goto err_node_put;
>>   
>> +	ret = phy_symbols_clk_register(qmp, np);
>> +	if (ret)
>> +		goto err_node_put;
>> +
>>   	qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
>>   	if (IS_ERR(qmp->phy)) {
>>   		ret = PTR_ERR(qmp->phy);
> 
> Johan

-- 
With best wishes
Dmitry


^ permalink raw reply	[flat|nested] 20+ messages in thread
* Re: [PATCH v7 2/4] phy: qcom-qmp-ufs: provide symbol clocks
@ 2022-11-16 15:21       ` Dmitry Baryshkov
  0 siblings, 0 replies; 20+ messages in thread
From: Dmitry Baryshkov @ 2022-11-16 15:21 UTC (permalink / raw)
  To: Johan Hovold
  Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
	Kishon Vijay Abraham I, Rob Herring, Krzysztof Kozlowski,
	Philipp Zabel, linux-arm-msm, linux-phy, devicetree

On 16/11/2022 18:15, Johan Hovold wrote:
> On Thu, Nov 10, 2022 at 06:17:46PM +0300, Dmitry Baryshkov wrote:
>> Register three UFS symbol clocks (ufs_rx_symbol_0_clk_src,
>> ufs_rx_symbol_1_clk_src ufs_tx_symbol_0_clk_src). Register OF clock
>> provider to let other devices link these clocks through the DT.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
> 
> I was not CCed on this revision of this series either.
> 
>>   drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 64 +++++++++++++++++++++++++
>>   1 file changed, 64 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> index 189103d1bd18..78d7daf34667 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
>> @@ -1023,6 +1023,66 @@ static int qmp_ufs_clk_init(struct qmp_ufs *qmp)
>>   	return devm_clk_bulk_get(dev, num, qmp->clks);
>>   }
>>   
>> +static void phy_clk_release_provider(void *res)
>> +{
>> +	of_clk_del_provider(res);
>> +}
>> +
>> +#define UFS_SYMBOL_CLOCKS 3
>> +
>> +static int phy_symbols_clk_register(struct qmp_ufs *qmp, struct device_node *np)
> 
> Since you're adding a new function, please use the common prefix and
> reordering the terms and dropping the redundant "symbols" should make it
> more readable:
> 
> 	qmp_ufs_register_clocks()
> 
>> +{
>> +	struct clk_hw_onecell_data *clk_data;
>> +	struct clk_hw *hw;
>> +	char name[64];
>> +	int ret;
>> +
>> +	clk_data = devm_kzalloc(qmp->dev,
>> +				struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS),
>> +				GFP_KERNEL);
>> +	if (!clk_data)
>> +		return -ENOMEM;
>> +
>> +	clk_data->num = UFS_SYMBOL_CLOCKS;
>> +
>> +	snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev));
>> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
>> +	if (IS_ERR(hw))
>> +		return PTR_ERR(hw);
>> +
>> +	clk_data->hws[0] = hw;
>> +
>> +	snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev));
>> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
>> +	if (IS_ERR(hw))
>> +		return PTR_ERR(hw);
>> +
>> +	clk_data->hws[1] = hw;
>> +
>> +	snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev));
>> +	hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0);
>> +	if (IS_ERR(hw))
>> +		return PTR_ERR(hw);
>> +
>> +	clk_data->hws[2] = hw;
>> +
>> +	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/*
>> +	 * Roll a devm action because the clock provider is the child node, but
>> +	 * the child node is not actually a device.
>> +	 */
> 
> I know you just copied this from one of the other drivers, but perhaps
> rephrase as "can be a child node". You can just drop the second clause
> (no node *is* a device).

Ack, thanks for the suggestion.

> 
>> +	return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
>> +}
>> +
>> +static const struct phy_ops qcom_qmp_ufs_ops = {
>> +	.power_on	= qmp_ufs_enable,
>> +	.power_off	= qmp_ufs_disable,
>> +	.owner		= THIS_MODULE,
>> +};
> 
> As I've already pointed out once, the above phy_ops struct hunk does not
> belong in this patch and is just some left over after you rebased on
> phy-next that must be removed.

Oops. I'll fix this during the next respin.

> 
>>   static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np)
>>   {
>>   	struct platform_device *pdev = to_platform_device(qmp->dev);
>> @@ -1135,6 +1195,10 @@ static int qmp_ufs_probe(struct platform_device *pdev)
>>   	if (ret)
>>   		goto err_node_put;
>>   
>> +	ret = phy_symbols_clk_register(qmp, np);
>> +	if (ret)
>> +		goto err_node_put;
>> +
>>   	qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops);
>>   	if (IS_ERR(qmp->phy)) {
>>   		ret = PTR_ERR(qmp->phy);
> 
> Johan

-- 
With best wishes
Dmitry


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

^ permalink raw reply	[flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-11-16 16:30 UTC | newest]

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-10 15:17 [PATCH v7 0/4] phy: qcom-qmp-ufs: add symbol clocks support Dmitry Baryshkov
2022-11-10 15:17 ` Dmitry Baryshkov
2022-11-10 15:17 ` [PATCH v7 1/4] dt-bindings: phy: qcom,*-qmp-ufs-phy: add clock-cells property Dmitry Baryshkov
2022-11-10 15:17   ` Dmitry Baryshkov
2022-11-10 15:18   ` Krzysztof Kozlowski
2022-11-10 15:18     ` Krzysztof Kozlowski
2022-11-10 15:17 ` [PATCH v7 2/4] phy: qcom-qmp-ufs: provide symbol clocks Dmitry Baryshkov
2022-11-10 15:17   ` Dmitry Baryshkov
2022-11-16 15:15   ` Johan Hovold
2022-11-16 15:15     ` Johan Hovold
2022-11-16 15:21     ` Dmitry Baryshkov
2022-11-16 15:21       ` Dmitry Baryshkov
2022-11-10 15:17 ` [PATCH v7 3/4] arm64: dts: qcom: sm8450: fix gcc clocks order to follow the schema Dmitry Baryshkov
2022-11-10 15:17   ` Dmitry Baryshkov
2022-11-10 15:21   ` Konrad Dybcio
2022-11-10 15:21     ` Konrad Dybcio
2022-11-10 15:17 ` [PATCH v7 4/4] arm64: dts: qcom: use UFS symbol clocks provided by PHY Dmitry Baryshkov
2022-11-10 15:17   ` Dmitry Baryshkov
2022-11-10 15:26   ` Konrad Dybcio
2022-11-10 15:26     ` Konrad Dybcio

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