* [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
@ 2020-08-05 8:15 Chee Hong Ang
2020-08-05 8:23 ` Marek Vasut
2020-08-14 19:23 ` Westergreen, Dalon
0 siblings, 2 replies; 10+ messages in thread
From: Chee Hong Ang @ 2020-08-05 8:15 UTC (permalink / raw)
To: u-boot
Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required
for booting up Cyclone5/Arria10.
Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
Makefile | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Makefile b/Makefile
index 2629a74..13429a0 100644
--- a/Makefile
+++ b/Makefile
@@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
ifneq ($(CONFIG_ARCH_SOCFPGA),)
quiet_cmd_socboot = SOCBOOT $@
cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
- spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
- u-boot.img > $@ || rm -f $@
+ spl/u-boot-spl.sfp \
+ spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
+ cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE
$(call if_changed,socboot)
--
2.2.0
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
2020-08-05 8:15 [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images Chee Hong Ang
@ 2020-08-05 8:23 ` Marek Vasut
2020-08-05 9:15 ` Tan, Ley Foon
2020-08-14 19:23 ` Westergreen, Dalon
1 sibling, 1 reply; 10+ messages in thread
From: Marek Vasut @ 2020-08-05 8:23 UTC (permalink / raw)
To: u-boot
On 8/5/20 10:15 AM, Chee Hong Ang wrote:
> Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required
> for booting up Cyclone5/Arria10.
>
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> ---
> Makefile | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 2629a74..13429a0 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
> ifneq ($(CONFIG_ARCH_SOCFPGA),)
> quiet_cmd_socboot = SOCBOOT $@
> cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> - u-boot.img > $@ || rm -f $@
> + spl/u-boot-spl.sfp \
> + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
> + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
Isn't that what the existing code does already ?
Also, this will I think fail on 128k erase block size NAND due to
missing padding.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
2020-08-05 8:23 ` Marek Vasut
@ 2020-08-05 9:15 ` Tan, Ley Foon
2020-08-05 9:17 ` Marek Vasut
0 siblings, 1 reply; 10+ messages in thread
From: Tan, Ley Foon @ 2020-08-05 9:15 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Wednesday, August 5, 2020 4:23 PM
> To: Ang, Chee Hong <chee.hong.ang@intel.com>; u-boot at lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Tom Rini
> <trini@konsulko.com>; See, Chin Liang <chin.liang.see@intel.com>; Tan, Ley
> Foon <ley.foon.tan@intel.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: Re: [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp
> with 4 SPL images
>
> On 8/5/20 10:15 AM, Chee Hong Ang wrote:
> > Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required
> > for booting up Cyclone5/Arria10.
> >
> > Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> > ---
> > Makefile | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/Makefile b/Makefile
> > index 2629a74..13429a0 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img
> FORCE
> > ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT $@
> > cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> > - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> > - u-boot.img > $@ || rm -f $@
> > + spl/u-boot-spl.sfp \
> > + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
> > + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
>
> Isn't that what the existing code does already ?
>
> Also, this will I think fail on 128k erase block size NAND due to missing
> padding.
This is to generate an output file (spl/u-boot-splx4.sfp) with 4 SPL images, each SPL image size is 256KB.
So, spl/u-boot-splx4.sfp is always with 1MB size (4x256KB). Shouldn't have problem for 128KB erase size NAND.
Regards
Ley Foon
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
2020-08-05 9:15 ` Tan, Ley Foon
@ 2020-08-05 9:17 ` Marek Vasut
2020-08-05 9:26 ` Tan, Ley Foon
0 siblings, 1 reply; 10+ messages in thread
From: Marek Vasut @ 2020-08-05 9:17 UTC (permalink / raw)
To: u-boot
On 8/5/20 11:15 AM, Tan, Ley Foon wrote:
[...]
>>> diff --git a/Makefile b/Makefile
>>> index 2629a74..13429a0 100644
>>> --- a/Makefile
>>> +++ b/Makefile
>>> @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img
>> FORCE
>>> ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT $@
>>> cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
>>> - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
>>> - u-boot.img > $@ || rm -f $@
>>> + spl/u-boot-spl.sfp \
>>> + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
>>> + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
>>
>> Isn't that what the existing code does already ?
>>
>> Also, this will I think fail on 128k erase block size NAND due to missing
>> padding.
> This is to generate an output file (spl/u-boot-splx4.sfp) with 4 SPL images, each SPL image size is 256KB.
> So, spl/u-boot-splx4.sfp is always with 1MB size (4x256KB). Shouldn't have problem for 128KB erase size NAND.
Isn't the SPL padded to 64 kiB each ?
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
2020-08-05 9:17 ` Marek Vasut
@ 2020-08-05 9:26 ` Tan, Ley Foon
2020-08-05 11:35 ` Marek Vasut
0 siblings, 1 reply; 10+ messages in thread
From: Tan, Ley Foon @ 2020-08-05 9:26 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Wednesday, August 5, 2020 5:18 PM
> To: Tan, Ley Foon <ley.foon.tan@intel.com>; Ang, Chee Hong
> <chee.hong.ang@intel.com>; u-boot at lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Tom Rini
> <trini@konsulko.com>; See, Chin Liang <chin.liang.see@intel.com>; Chee,
> Tien Fong <tien.fong.chee@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: Re: [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp
> with 4 SPL images
>
> On 8/5/20 11:15 AM, Tan, Ley Foon wrote:
> [...]
> >>> diff --git a/Makefile b/Makefile
> >>> index 2629a74..13429a0 100644
> >>> --- a/Makefile
> >>> +++ b/Makefile
> >>> @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img
> >> FORCE
> >>> ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT
> $@
> >>> cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> >>> - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> >>> - u-boot.img > $@ || rm -f $@
> >>> + spl/u-boot-spl.sfp \
> >>> + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
> >>> + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
> >>
> >> Isn't that what the existing code does already ?
> >>
> >> Also, this will I think fail on 128k erase block size NAND due to
> >> missing padding.
> > This is to generate an output file (spl/u-boot-splx4.sfp) with 4 SPL images,
> each SPL image size is 256KB.
> > So, spl/u-boot-splx4.sfp is always with 1MB size (4x256KB). Shouldn't have
> problem for 128KB erase size NAND.
>
> Isn't the SPL padded to 64 kiB each ?
Cyclone 5 and Arria 10 have different size.
Cyclone 5 SPL: 64KB each, spl/u-boot-splx4.sfp is 256KB
Arria 10 SPL: 256KB each, spl/u-boot-splx4.sfp is 1MB
Regards
Ley Foon
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
2020-08-05 9:26 ` Tan, Ley Foon
@ 2020-08-05 11:35 ` Marek Vasut
2020-08-06 1:50 ` Tan, Ley Foon
0 siblings, 1 reply; 10+ messages in thread
From: Marek Vasut @ 2020-08-05 11:35 UTC (permalink / raw)
To: u-boot
On 8/5/20 11:26 AM, Tan, Ley Foon wrote:
Hi,
[...]
>>>>> diff --git a/Makefile b/Makefile
>>>>> index 2629a74..13429a0 100644
>>>>> --- a/Makefile
>>>>> +++ b/Makefile
>>>>> @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img
>>>> FORCE
>>>>> ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT
>> $@
>>>>> cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
>>>>> - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
>>>>> - u-boot.img > $@ || rm -f $@
>>>>> + spl/u-boot-spl.sfp \
>>>>> + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
>>>>> + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
>>>>
>>>> Isn't that what the existing code does already ?
>>>>
>>>> Also, this will I think fail on 128k erase block size NAND due to
>>>> missing padding.
>>> This is to generate an output file (spl/u-boot-splx4.sfp) with 4 SPL images,
>> each SPL image size is 256KB.
>>> So, spl/u-boot-splx4.sfp is always with 1MB size (4x256KB). Shouldn't have
>> problem for 128KB erase size NAND.
>>
>> Isn't the SPL padded to 64 kiB each ?
> Cyclone 5 and Arria 10 have different size.
>
> Cyclone 5 SPL: 64KB each, spl/u-boot-splx4.sfp is 256KB
>
> Arria 10 SPL: 256KB each, spl/u-boot-splx4.sfp is 1MB
So are you sure this will work on NAND with 128 kiB erase blocks on
CV/AV ? I think you will run into problems with padding there. But maybe
we don't support that anyway, so add a comment and be done with it.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
2020-08-05 11:35 ` Marek Vasut
@ 2020-08-06 1:50 ` Tan, Ley Foon
2020-08-06 7:15 ` Marek Vasut
0 siblings, 1 reply; 10+ messages in thread
From: Tan, Ley Foon @ 2020-08-06 1:50 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Wednesday, August 5, 2020 7:36 PM
> To: Tan, Ley Foon <ley.foon.tan@intel.com>; Ang, Chee Hong
> <chee.hong.ang@intel.com>; u-boot at lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Tom Rini
> <trini@konsulko.com>; See, Chin Liang <chin.liang.see@intel.com>; Chee,
> Tien Fong <tien.fong.chee@intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>
> Subject: Re: [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp
> with 4 SPL images
>
> On 8/5/20 11:26 AM, Tan, Ley Foon wrote:
>
> Hi,
>
> [...]
>
> >>>>> diff --git a/Makefile b/Makefile
> >>>>> index 2629a74..13429a0 100644
> >>>>> --- a/Makefile
> >>>>> +++ b/Makefile
> >>>>> @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img
> >>>> FORCE
> >>>>> ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT
> >> $@
> >>>>> cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> >>>>> - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> >>>>> - u-boot.img > $@ || rm -f $@
> >>>>> + spl/u-boot-spl.sfp \
> >>>>> + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
> >>>>> + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
> >>>>
> >>>> Isn't that what the existing code does already ?
> >>>>
> >>>> Also, this will I think fail on 128k erase block size NAND due to
> >>>> missing padding.
> >>> This is to generate an output file (spl/u-boot-splx4.sfp) with 4 SPL
> >>> images,
> >> each SPL image size is 256KB.
> >>> So, spl/u-boot-splx4.sfp is always with 1MB size (4x256KB).
> >>> Shouldn't have
> >> problem for 128KB erase size NAND.
> >>
> >> Isn't the SPL padded to 64 kiB each ?
> > Cyclone 5 and Arria 10 have different size.
> >
> > Cyclone 5 SPL: 64KB each, spl/u-boot-splx4.sfp is 256KB
> >
> > Arria 10 SPL: 256KB each, spl/u-boot-splx4.sfp is 1MB
>
> So are you sure this will work on NAND with 128 kiB erase blocks on CV/AV ?
> I think you will run into problems with padding there. But maybe we don't
> support that anyway, so add a comment and be done with it.
If the erase block size is 128KB and we program the spl/u-boot-splx4.sfp with 256KB for Cyclone5. It consumes 2 erase block size, why do you think it will have problem?
By the way, tested spl/u-boot-splx4.sfp on Arria 10 NAND with 128KB erase block size, it is working.
Regards
Ley Foon
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
2020-08-06 1:50 ` Tan, Ley Foon
@ 2020-08-06 7:15 ` Marek Vasut
0 siblings, 0 replies; 10+ messages in thread
From: Marek Vasut @ 2020-08-06 7:15 UTC (permalink / raw)
To: u-boot
On 8/6/20 3:50 AM, Tan, Ley Foon wrote:
Hi,
>>>>>>> diff --git a/Makefile b/Makefile
>>>>>>> index 2629a74..13429a0 100644
>>>>>>> --- a/Makefile
>>>>>>> +++ b/Makefile
>>>>>>> @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img
>>>>>> FORCE
>>>>>>> ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT
>>>> $@
>>>>>>> cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
>>>>>>> - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
>>>>>>> - u-boot.img > $@ || rm -f $@
>>>>>>> + spl/u-boot-spl.sfp \
>>>>>>> + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
>>>>>>> + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
>>>>>>
>>>>>> Isn't that what the existing code does already ?
>>>>>>
>>>>>> Also, this will I think fail on 128k erase block size NAND due to
>>>>>> missing padding.
>>>>> This is to generate an output file (spl/u-boot-splx4.sfp) with 4 SPL
>>>>> images,
>>>> each SPL image size is 256KB.
>>>>> So, spl/u-boot-splx4.sfp is always with 1MB size (4x256KB).
>>>>> Shouldn't have
>>>> problem for 128KB erase size NAND.
>>>>
>>>> Isn't the SPL padded to 64 kiB each ?
>>> Cyclone 5 and Arria 10 have different size.
>>>
>>> Cyclone 5 SPL: 64KB each, spl/u-boot-splx4.sfp is 256KB
>>>
>>> Arria 10 SPL: 256KB each, spl/u-boot-splx4.sfp is 1MB
>>
>> So are you sure this will work on NAND with 128 kiB erase blocks on CV/AV ?
>> I think you will run into problems with padding there. But maybe we don't
>> support that anyway, so add a comment and be done with it.
> If the erase block size is 128KB and we program the spl/u-boot-splx4.sfp with 256KB for Cyclone5. It consumes 2 erase block size, why do you think it will have problem?
See "Figure A-7: NAND Flash Image Layout for 128 KB Memory Blocks" in
Cyclone V datasheet, appending A.
> By the way, tested spl/u-boot-splx4.sfp on Arria 10 NAND with 128KB erase block size, it is working.
Isn't that only because it picks the first SPL copy and it accidentally
works fine ? Try to write in an image with SPL 0,2,3 corrupted and only
SPL 1 valid , then it wont boot I think.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
2020-08-05 8:15 [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images Chee Hong Ang
2020-08-05 8:23 ` Marek Vasut
@ 2020-08-14 19:23 ` Westergreen, Dalon
2020-08-17 2:55 ` Tan, Ley Foon
1 sibling, 1 reply; 10+ messages in thread
From: Westergreen, Dalon @ 2020-08-14 19:23 UTC (permalink / raw)
To: u-boot
Can you explain why this x4 image is needed? the top level u-boot-with-spl.sfp
or whatever it is called already creates four spl entries. what are you
generating the x4 image for?
--dalon
On Wed, 2020-08-05 at 16:15 +0800, Chee Hong Ang wrote:
> Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required
> for booting up Cyclone5/Arria10.
>
> Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> ---
> Makefile | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 2629a74..13429a0 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
> ifneq ($(CONFIG_ARCH_SOCFPGA),)
> quiet_cmd_socboot = SOCBOOT $@
> cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> - u-boot.img > $@ || rm -f $@
> + spl/u-boot-spl.sfp \
> + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
> + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
> u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE
> $(call if_changed,socboot)
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images
2020-08-14 19:23 ` Westergreen, Dalon
@ 2020-08-17 2:55 ` Tan, Ley Foon
0 siblings, 0 replies; 10+ messages in thread
From: Tan, Ley Foon @ 2020-08-17 2:55 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Westergreen, Dalon <dalon.westergreen@intel.com>
> Sent: Saturday, August 15, 2020 3:24 AM
> To: u-boot at lists.denx.de; Ang, Chee Hong <chee.hong.ang@intel.com>
> Cc: See, Chin Liang <chin.liang.see@intel.com>; Tan, Ley Foon
> <ley.foon.tan@intel.com>; Chee, Tien Fong <tien.fong.chee@intel.com>;
> Lim, Elly Siew Chin <elly.siew.chin.lim@intel.com>
> Subject: Re: [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp
> with 4 SPL images
>
> Can you explain why this x4 image is needed? the top level u-boot-with-
> spl.sfp or whatever it is called already creates four spl entries. what are you
> generating the x4 image for?
If we put u-boot.img in FAT partition, then we don't need u-boot-with- spl.sfp. Just 4 x SPL images.
Regards
Ley Foon
>
> On Wed, 2020-08-05 at 16:15 +0800, Chee Hong Ang wrote:
> > Generate spl/u-boot-splx4.sfp which consist of 4 SPL images required
> > for booting up Cyclone5/Arria10.
> >
> > Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
> > ---
> > Makefile | 5 +++--
> > 1 file changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/Makefile b/Makefile
> > index 2629a74..13429a0 100644
> > --- a/Makefile
> > +++ b/Makefile
> > @@ -1578,8 +1578,9 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img
> FORCE
> > ifneq ($(CONFIG_ARCH_SOCFPGA),) quiet_cmd_socboot = SOCBOOT $@
> > cmd_socboot = cat spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> > - spl/u-boot-spl.sfp spl/u-boot-spl.sfp \
> > - u-boot.img > $@ || rm -f $@
> > + spl/u-boot-spl.sfp \
> > + spl/u-boot-spl.sfp > spl/u-boot-splx4.sfp ; \
> > + cat spl/u-boot-splx4.sfp u-boot.img > $@ || rm -f $@
> > u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE
> > $(call if_changed,socboot)
> >
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-08-17 2:55 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-05 8:15 [PATCH v1] Makefile: socfpga: Generate spl/u-boot-splx4.sfp with 4 SPL images Chee Hong Ang
2020-08-05 8:23 ` Marek Vasut
2020-08-05 9:15 ` Tan, Ley Foon
2020-08-05 9:17 ` Marek Vasut
2020-08-05 9:26 ` Tan, Ley Foon
2020-08-05 11:35 ` Marek Vasut
2020-08-06 1:50 ` Tan, Ley Foon
2020-08-06 7:15 ` Marek Vasut
2020-08-14 19:23 ` Westergreen, Dalon
2020-08-17 2:55 ` Tan, Ley Foon
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all data and code used by this external index.