[igt-dev] [PATCH i-g-t v5 00/12] vm_bind: Add VM_BIND validation support

[igt-dev] [PATCH i-g-t v5 00/12] vm_bind: Add VM_BIND validation support

[Niranjana Vishwanathapura]

DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM
buffer objects (BOs) or sections of a BOs at specified GPU virtual
addresses on a specified address space (VM). Multiple mappings can map
to the same physical pages of an object (aliasing). These mappings (also
referred to as persistent mappings) will be persistent across multiple
GPU submissions (execbuf calls) issued by the UMD, without user having
to provide a list of all required mappings during each submission (as
required by older execbuf mode).

The new execbuf3 ioctl (I915_GEM_EXECBUFFER3) will only work in vm_bind
mode. The vm_bind mode only works with this new execbuf3 ioctl.

Add sanity tests to validate the VM_BIND, VM_UNBIND and execbuf3 ioctls.

Add basic test to create and VM_BIND the objects and issue execbuf3 for
GPU to copy the data from a source to destination buffer.

TODOs:
* More validation support.
* Port some relevant gem_exec_* tests for execbuf3.

NOTEs:
* It is based on below VM_BIND design+uapi rfc.
  Documentation/gpu/rfc/i915_vm_bind.rst

* The i915 VM_BIND support is posted as,
  [PATCH v5 00/19] drm/i915/vm_bind: Add VM_BIND functionality

v2: Address various review comments
v3: Add gem_exec3_basic and gem_exec3_balancer tests,
    add gem_lmem_swapping@vm_bind subtest and some fixes.
v4: Add and use i915_vm_bind library functions,
    add lmem test if lmem region is present instead of skipping,
    remove helpers to create vm_private objects, instead use
    gem_create_ext() function.
v5: Use memory region's gtt_alignment, use non-recoverable faults,
    fix review comments.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>

Niranjana Vishwanathapura (12):
  include/drm-uapi: memory region gtt_alignment support
  lib/vm_bind: import uapi definitions
  lib/vm_bind: Add vm_bind/unbind and execbuf3 ioctls
  lib/vm_bind: Add vm_bind mode support for VM
  lib/vm_bind: Add vm_bind specific library functions
  lib/vm_bind: Add __prime_handle_to_fd()
  tests/i915/vm_bind: Add vm_bind sanity test
  tests/i915/vm_bind: Add basic VM_BIND test support
  tests/i915/vm_bind: Add userptr subtest
  tests/i915/vm_bind: Add gem_exec3_basic test
  tests/i915/vm_bind: Add gem_exec3_balancer test
  tests/i915/vm_bind: Add gem_lmem_swapping@vm_bind sub test

 include/drm-uapi/i915_drm.h           |  30 +-
 lib/i915/gem_context.c                |  24 +
 lib/i915/gem_context.h                |   3 +
 lib/i915/gem_vm.c                     |  31 +-
 lib/i915/gem_vm.h                     |   3 +-
 lib/i915/i915_drm_local.h             | 298 +++++++++++++
 lib/i915/i915_vm_bind.c               |  61 +++
 lib/i915/i915_vm_bind.h               |  16 +
 lib/i915/intel_memory_region.c        |   1 +
 lib/i915/intel_memory_region.h        |   1 +
 lib/ioctl_wrappers.c                  | 117 ++++-
 lib/ioctl_wrappers.h                  |   7 +
 lib/meson.build                       |   1 +
 tests/i915/gem_exec3_balancer.c       | 466 ++++++++++++++++++++
 tests/i915/gem_exec3_basic.c          | 139 ++++++
 tests/i915/gem_lmem_swapping.c        | 134 +++++-
 tests/i915/gem_pwrite.c               |  16 +-
 tests/i915/i915_vm_bind_basic.c       | 602 ++++++++++++++++++++++++++
 tests/i915/i915_vm_bind_sanity.c      | 306 +++++++++++++
 tests/intel-ci/fast-feedback.testlist |   3 +
 tests/meson.build                     |  10 +
 tests/prime_mmap.c                    |  26 +-
 22 files changed, 2243 insertions(+), 52 deletions(-)
 create mode 100644 lib/i915/i915_vm_bind.c
 create mode 100644 lib/i915/i915_vm_bind.h
 create mode 100644 tests/i915/gem_exec3_balancer.c
 create mode 100644 tests/i915/gem_exec3_basic.c
 create mode 100644 tests/i915/i915_vm_bind_basic.c
 create mode 100644 tests/i915/i915_vm_bind_sanity.c

-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 01/12] include/drm-uapi: memory region gtt_alignment support

[Niranjana Vishwanathapura]

Pull in gtt_alignment addition in drm_i915_memory_region_info
uapi and update library to include this field.

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 include/drm-uapi/i915_drm.h    | 30 ++++++++++++++++++++++++++++--
 lib/i915/intel_memory_region.c |  1 +
 lib/i915/intel_memory_region.h |  1 +
 3 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
index ae9558b3d9..b3a200fc5d 100644
--- a/include/drm-uapi/i915_drm.h
+++ b/include/drm-uapi/i915_drm.h
@@ -3215,8 +3215,34 @@ struct drm_i915_memory_region_info {
 	/** @region: The class:instance pair encoding */
 	struct drm_i915_gem_memory_class_instance region;
 
-	/** @rsvd0: MBZ */
-	__u32 rsvd0;
+	union {
+		/** @rsvd0: MBZ */
+		__u32 rsvd0;
+
+		/**
+		 * @gtt_alignment:
+		 *
+		 * The minimum required GTT alignment for this type of memory.
+		 * When allocating a GTT address it must be aligned to this
+		 * value or larger. On some platforms the kernel might opt to
+		 * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
+		 * pages can then be used if we also use 64K GTT alignment.
+		 *
+		 * NOTE: If this is zero then this must be an older
+		 * kernel which lacks support for this field.
+		 *
+		 * Side note: For larger objects (especially for
+		 * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
+		 * consider potentially bumping the GTT alignment to say 2M,
+		 * which could potentially increase the likelihood of the kernel
+		 * being able to utilise 2M GTT pages underneath, if the layout
+		 * of the physical pages allows it.  On some configurations we
+		 * can then also use a more efficient page-table layout, if we
+		 * can't use the more desirable 2M GTT page, so long as we know
+		 * that the entire page-table will be used by this object.
+		 */
+		__u32 gtt_alignment;
+	};
 
 	/**
 	 * @probed_size: Memory probed by the driver
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index 84e1bceb38..cbe27d6714 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -944,6 +944,7 @@ struct gem_memory_region *__gem_get_memory_regions(int i915)
 
 		r->ci = info->regions[i].region;
 		r->size = info->regions[i].probed_size;
+		r->gtt_alignment = info->regions[i].gtt_alignment;
 		r->cpu_size = info->regions[i].probed_cpu_visible_size;
 		if (r->size == -1ull)
 			r->size = igt_get_avail_ram_mb() << 20;
diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
index 425bda0ec7..84abb95b1a 100644
--- a/lib/i915/intel_memory_region.h
+++ b/lib/i915/intel_memory_region.h
@@ -174,6 +174,7 @@ struct gem_memory_region {
 	char *name;
 
 	struct drm_i915_gem_memory_class_instance ci;
+	uint64_t gtt_alignment;
 	uint64_t size;
 	uint64_t cpu_size;
 };
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 02/12] lib/vm_bind: import uapi definitions

[Niranjana Vishwanathapura]

Import required VM_BIND kernel uapi definitions.

DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM
buffer objects (BOs) or sections of a BOs at specified GPU virtual
addresses on a specified address space (VM). Multiple mappings can map
to the same physical pages of an object (aliasing). These mappings (also
referred to as persistent mappings) will be persistent across multiple
GPU submissions (execbuf calls) issued by the UMD, without user having
to provide a list of all required mappings during each submission (as
required by older execbuf mode).

The new execbuf3 ioctl (I915_GEM_EXECBUFFER3) will only work in vm_bind
mode. The vm_bind mode only works with this new execbuf3 ioctl.

v2: Move vm_bind uapi definitions to i915_drm-local.h
    Define HAS_64K_PAGES()
    Pull in uapi updates
v3: Remove HAS_64K_PAGES()

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 lib/i915/i915_drm_local.h | 298 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 298 insertions(+)

diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index 9a2273c4e4..fd12d1f9c9 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -23,6 +23,304 @@ extern "C" {
 
 #define DRM_I915_QUERY_GEOMETRY_SUBSLICES      6
 
+/*
+ * Signal to the kernel that the object will need to be accessed via
+ * the CPU.
+ *
+ * Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only
+ * strictly required on platforms where only some of the device memory
+ * is directly visible or mappable through the CPU, like on DG2+.
+ *
+ * One of the placements MUST also be I915_MEMORY_CLASS_SYSTEM, to
+ * ensure we can always spill the allocation to system memory, if we
+ * can't place the object in the mappable part of
+ * I915_MEMORY_CLASS_DEVICE.
+ *
+ * Without this hint, the kernel will assume that non-mappable
+ * I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the
+ * kernel can still migrate the object to the mappable part, as a last
+ * resort, if userspace ever CPU faults this object, but this might be
+ * expensive, and so ideally should be avoided.
+ */
+#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)
+
+#define DRM_I915_GEM_VM_BIND		0x3d
+#define DRM_I915_GEM_VM_UNBIND		0x3e
+#define DRM_I915_GEM_EXECBUFFER3	0x3f
+
+#define DRM_IOCTL_I915_GEM_VM_BIND	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_BIND, struct drm_i915_gem_vm_bind)
+#define DRM_IOCTL_I915_GEM_VM_UNBIND	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_UNBIND, struct drm_i915_gem_vm_unbind)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER3  DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER3, struct drm_i915_gem_execbuffer3)
+
+/*
+ * VM_BIND feature version supported.
+ *
+ * The following versions of VM_BIND have been defined:
+ *
+ * 0: No VM_BIND support.
+ *
+ * 1: In VM_UNBIND calls, the UMD must specify the exact mappings created
+ *    previously with VM_BIND, the ioctl will not support unbinding multiple
+ *    mappings or splitting them. Similarly, VM_BIND calls will not replace
+ *    any existing mappings.
+ *
+ * See struct drm_i915_gem_vm_bind and struct drm_i915_gem_vm_unbind.
+ */
+#define I915_PARAM_VM_BIND_VERSION	57
+
+#define DRM_I915_GEM_EXECBUFFER3_EXT_TIMELINE_FENCES 0
+
+/**
+ * struct drm_i915_gem_timeline_fence - An input or output timeline fence.
+ *
+ * The operation will wait for input fence to signal.
+ *
+ * The returned output fence will be signaled after the completion of the
+ * operation.
+ */
+struct drm_i915_gem_timeline_fence {
+	/** @handle: User's handle for a drm_syncobj to wait on or signal. */
+	__u32 handle;
+
+	/**
+	 * @flags: Supported flags are:
+	 *
+	 * I915_TIMELINE_FENCE_WAIT:
+	 * Wait for the input fence before the operation.
+	 *
+	 * I915_TIMELINE_FENCE_SIGNAL:
+	 * Return operation completion fence as output.
+	 */
+	__u32 flags;
+#define I915_TIMELINE_FENCE_WAIT            (1 << 0)
+#define I915_TIMELINE_FENCE_SIGNAL          (1 << 1)
+#define __I915_TIMELINE_FENCE_UNKNOWN_FLAGS (-(I915_TIMELINE_FENCE_SIGNAL << 1))
+
+	/**
+	 * @value: A point in the timeline.
+	 * Value must be 0 for a binary drm_syncobj. A Value of 0 for a
+	 * timeline drm_syncobj is invalid as it turns a drm_syncobj into a
+	 * binary one.
+	 */
+	__u64 value;
+};
+
+/**
+ * struct drm_i915_gem_execbuffer3 - Structure for DRM_I915_GEM_EXECBUFFER3
+ * ioctl.
+ *
+ * DRM_I915_GEM_EXECBUFFER3 ioctl only works in VM_BIND mode and VM_BIND mode
+ * only works with this ioctl for submission.
+ * See I915_VM_CREATE_FLAGS_USE_VM_BIND.
+ */
+struct drm_i915_gem_execbuffer3 {
+	/**
+	 * @ctx_id: Context id
+	 *
+	 * Only contexts with user engine map are allowed.
+	 */
+	__u32 ctx_id;
+
+	/**
+	 * @engine_idx: Engine index
+	 *
+	 * An index in the user engine map of the context specified by @ctx_id.
+	 */
+	__u32 engine_idx;
+
+	/**
+	 * @batch_address: Batch gpu virtual address/es.
+	 *
+	 * For normal submission, it is the gpu virtual address of the batch
+	 * buffer. For parallel submission, it is a pointer to an array of
+	 * batch buffer gpu virtual addresses with array size equal to the
+	 * number of (parallel) engines involved in that submission (See
+	 * struct i915_context_engines_parallel_submit).
+	 */
+	__u64 batch_address;
+
+	/** @flags: Currently reserved, MBZ */
+	__u64 flags;
+#define __I915_EXEC3_UNKNOWN_FLAGS (~0ull)
+
+	/** @fence_count: Number of fences in @timeline_fences array. */
+	__u64 fence_count;
+
+	/**
+	 * @timeline_fences: Pointer to an array of timeline fences.
+	 *
+	 * Timeline fences are of format struct drm_i915_gem_timeline_fence.
+	 */
+	__u64 timeline_fences;
+
+	/** @rsvd: Reserved, MBZ */
+	__u64 rsvd;
+
+	/**
+	 * @extensions: Zero-terminated chain of extensions.
+	 *
+	 * For future extensions. See struct i915_user_extension.
+	 */
+	__u64 extensions;
+};
+
+/*
+ * If I915_VM_CREATE_FLAGS_USE_VM_BIND flag is set, VM created will work in
+ * VM_BIND mode
+ */
+#define I915_VM_CREATE_FLAGS_USE_VM_BIND	(1u << 0)
+
+/*
+ * For I915_GEM_CREATE_EXT_VM_PRIVATE usage see
+ * struct drm_i915_gem_create_ext_vm_private.
+ */
+#define I915_GEM_CREATE_EXT_VM_PRIVATE 2
+
+/**
+ * struct drm_i915_gem_create_ext_vm_private - Extension to make the object
+ * private to the specified VM.
+ *
+ * See struct drm_i915_gem_create_ext.
+ *
+ * By default, BOs can be mapped on multiple VMs and can also be dma-buf
+ * exported. Hence these BOs are referred to as Shared BOs.
+ * During each execbuf3 submission, the request fence must be added to the
+ * dma-resv fence list of all shared BOs mapped on the VM.
+ *
+ * Unlike Shared BOs, these VM private BOs can only be mapped on the VM they
+ * are private to and can't be dma-buf exported. All private BOs of a VM share
+ * the dma-resv object. Hence during each execbuf3 submission, they need only
+ * one dma-resv fence list updated. Thus, the fast path (where required
+ * mappings are already bound) submission latency is O(1) w.r.t the number of
+ * VM private BOs.
+ */
+struct drm_i915_gem_create_ext_vm_private {
+	/** @base: Extension link. See struct i915_user_extension. */
+	struct i915_user_extension base;
+
+	/** @vm_id: Id of the VM to which Object is private */
+	__u32 vm_id;
+
+	/** @rsvd: Reserved, MBZ */
+	__u32 rsvd;
+};
+
+/**
+ * struct drm_i915_gem_vm_bind - VA to object mapping to bind.
+ *
+ * This structure is passed to VM_BIND ioctl and specifies the mapping of GPU
+ * virtual address (VA) range to the section of an object that should be bound
+ * in the device page table of the specified address space (VM).
+ * The VA range specified must be unique (ie., not currently bound) and can
+ * be mapped to whole object or a section of the object (partial binding).
+ * Multiple VA mappings can be created to the same section of the object
+ * (aliasing).
+ *
+ * The @start, @offset and @length must be 4K page aligned. However the DG2
+ * and XEHPSDV has 64K page size for device local memory and has compact page
+ * table. On those platforms, for binding device local-memory objects, the
+ * @start, @offset and @length must be 64K aligned.
+ *
+ * Error code -EINVAL will be returned if @start, @offset and @length are not
+ * properly aligned. In version 1 (See I915_PARAM_VM_BIND_VERSION), error code
+ * -ENOSPC will be returned if the VA range specified can't be reserved.
+ *
+ * VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently
+ * are not ordered. Furthermore, parts of the VM_BIND operation can be done
+ * asynchronously, if valid @fence is specified.
+ */
+struct drm_i915_gem_vm_bind {
+	/** @vm_id: VM (address space) id to bind */
+	__u32 vm_id;
+
+	/** @handle: Object handle */
+	__u32 handle;
+
+	/** @start: Virtual Address start to bind */
+	__u64 start;
+
+	/** @offset: Offset in object to bind */
+	__u64 offset;
+
+	/** @length: Length of mapping to bind */
+	__u64 length;
+
+	/**
+	 * @flags: Currently reserved, MBZ.
+	 *
+	 * Note that @fence carries its own flags.
+	 */
+	__u64 flags;
+
+	/**
+	 * @fence: Timeline fence for bind completion signaling.
+	 *
+	 * Timeline fence is of format struct drm_i915_gem_timeline_fence.
+	 *
+	 * It is an out fence, hence using I915_TIMELINE_FENCE_WAIT flag
+	 * is invalid, and an error will be returned.
+	 *
+	 * If I915_TIMELINE_FENCE_SIGNAL flag is not set, then out fence
+	 * is not requested and binding is completed synchronously.
+	 */
+	struct drm_i915_gem_timeline_fence fence;
+
+	/**
+	 * @extensions: Zero-terminated chain of extensions.
+	 *
+	 * For future extensions. See struct i915_user_extension.
+	 */
+	__u64 extensions;
+};
+
+/**
+ * struct drm_i915_gem_vm_unbind - VA to object mapping to unbind.
+ *
+ * This structure is passed to VM_UNBIND ioctl and specifies the GPU virtual
+ * address (VA) range that should be unbound from the device page table of the
+ * specified address space (VM). VM_UNBIND will force unbind the specified
+ * range from device page table without waiting for any GPU job to complete.
+ * It is UMDs responsibility to ensure the mapping is no longer in use before
+ * calling VM_UNBIND.
+ *
+ * If the specified mapping is not found, the ioctl will simply return without
+ * any error.
+ *
+ * VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently
+ * are not ordered. Furthermore, parts of the VM_UNBIND operation can be done
+ * asynchronously, if valid @fence is specified.
+ */
+struct drm_i915_gem_vm_unbind {
+	/** @vm_id: VM (address space) id to bind */
+	__u32 vm_id;
+
+	/** @rsvd: Reserved, MBZ */
+	__u32 rsvd;
+
+	/** @start: Virtual Address start to unbind */
+	__u64 start;
+
+	/** @length: Length of mapping to unbind */
+	__u64 length;
+
+	/**
+	 * @flags: Currently reserved, MBZ.
+	 *
+	 * Note that @fence carries its own flags.
+	 */
+	__u64 flags;
+
+	/** @rsvd2: Reserved, MBZ */
+	__u64 rsvd2[2];
+
+	/**
+	 * @extensions: Zero-terminated chain of extensions.
+	 *
+	 * For future extensions. See struct i915_user_extension.
+	 */
+	__u64 extensions;
+};
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 03/12] lib/vm_bind: Add vm_bind/unbind and execbuf3 ioctls

[Niranjana Vishwanathapura]

Add required library interfaces for new vm_bind/unbind
and execbuf3 ioctls.

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 lib/ioctl_wrappers.c | 78 ++++++++++++++++++++++++++++++++++++++++++++
 lib/ioctl_wrappers.h |  6 ++++
 2 files changed, 84 insertions(+)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index 09eb3ce7b5..ac37b6bb43 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -706,6 +706,38 @@ void gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf)
 	igt_assert_eq(__gem_execbuf_wr(fd, execbuf), 0);
 }
 
+/**
+ * __gem_execbuf3:
+ * @fd: open i915 drm file descriptor
+ * @execbuf: execbuffer data structure
+ *
+ * This wraps the EXECBUFFER3 ioctl, which submits a batchbuffer for the gpu to
+ * run. This is allowed to fail, with -errno returned.
+ */
+int __gem_execbuf3(int fd, struct drm_i915_gem_execbuffer3 *execbuf)
+{
+	int err = 0;
+	if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER3, execbuf)) {
+		err = -errno;
+		igt_assume(err != 0);
+	}
+	errno = 0;
+	return err;
+}
+
+/**
+ * gem_execbuf3:
+ * @fd: open i915 drm file descriptor
+ * @execbuf: execbuffer data structure
+ *
+ * This wraps the EXECBUFFER3 ioctl, which submits a batchbuffer for the gpu to
+ * run.
+ */
+void gem_execbuf3(int fd, struct drm_i915_gem_execbuffer3 *execbuf)
+{
+	igt_assert_eq(__gem_execbuf3(fd, execbuf), 0);
+}
+
 /**
  * gem_madvise:
  * @fd: open i915 drm file descriptor
@@ -1328,3 +1360,49 @@ bool igt_has_drm_cap(int fd, uint64_t capability)
 	igt_assert(drmIoctl(fd, DRM_IOCTL_GET_CAP, &cap) == 0);
 	return cap.value;
 }
+
+/* VM_BIND */
+
+int __gem_vm_bind(int fd, struct drm_i915_gem_vm_bind *bind)
+{
+	int err = 0;
+
+	if (drmIoctl(fd, DRM_IOCTL_I915_GEM_VM_BIND, bind))
+		err = -errno;
+	return err;
+}
+
+/**
+ * gem_vm_bind:
+ * @fd: open i915 drm file descriptor
+ * @bind: vm_bind data structure
+ *
+ * This wraps the VM_BIND ioctl to bind an address range to
+ * the specified address space.
+ */
+void gem_vm_bind(int fd, struct drm_i915_gem_vm_bind *bind)
+{
+	igt_assert_eq(__gem_vm_bind(fd, bind), 0);
+}
+
+int __gem_vm_unbind(int fd, struct drm_i915_gem_vm_unbind *unbind)
+{
+	int err = 0;
+
+	if (drmIoctl(fd, DRM_IOCTL_I915_GEM_VM_UNBIND, unbind))
+		err = -errno;
+	return err;
+}
+
+/**
+ * gem_vm_unbind:
+ * @fd: open i915 drm file descriptor
+ * @unbind: vm_unbind data structure
+ *
+ * This wraps the VM_UNBIND ioctl to unbind an address range from
+ * the specified address space.
+ */
+void gem_vm_unbind(int fd, struct drm_i915_gem_vm_unbind *unbind)
+{
+	igt_assert_eq(__gem_vm_unbind(fd, unbind), 0);
+}
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 9a897fec23..223cd9160c 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -84,6 +84,12 @@ void gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
 int __gem_execbuf_wr(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
 void gem_execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
 int __gem_execbuf(int fd, struct drm_i915_gem_execbuffer2 *execbuf);
+void gem_execbuf3(int fd, struct drm_i915_gem_execbuffer3 *execbuf);
+int __gem_execbuf3(int fd, struct drm_i915_gem_execbuffer3 *execbuf);
+int __gem_vm_bind(int fd, struct drm_i915_gem_vm_bind *bind);
+void gem_vm_bind(int fd, struct drm_i915_gem_vm_bind *bind);
+int __gem_vm_unbind(int fd, struct drm_i915_gem_vm_unbind *unbind);
+void gem_vm_unbind(int fd, struct drm_i915_gem_vm_unbind *unbind);
 
 #ifndef I915_GEM_DOMAIN_WC
 #define I915_GEM_DOMAIN_WC 0x80
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 04/12] lib/vm_bind: Add vm_bind mode support for VM

[Niranjana Vishwanathapura]

Add required library interfaces to create VM in
vm_bind mode and assign the VM to a context.

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 lib/i915/gem_context.c | 24 ++++++++++++++++++++++++
 lib/i915/gem_context.h |  3 +++
 lib/i915/gem_vm.c      | 31 ++++++++++++++++++++++++++-----
 lib/i915/gem_vm.h      |  3 ++-
 4 files changed, 55 insertions(+), 6 deletions(-)

diff --git a/lib/i915/gem_context.c b/lib/i915/gem_context.c
index fe989a8d1c..2d06b41980 100644
--- a/lib/i915/gem_context.c
+++ b/lib/i915/gem_context.c
@@ -517,3 +517,27 @@ uint32_t gem_context_create_for_class(int i915,
 	*count = i;
 	return p.ctx_id;
 }
+
+uint32_t gem_context_get_vm(int fd, uint32_t ctx_id)
+{
+	struct drm_i915_gem_context_param p = {
+		.param = I915_CONTEXT_PARAM_VM,
+		.ctx_id = ctx_id,
+	};
+
+	gem_context_get_param(fd, &p);
+	igt_assert(p.value);
+
+	return p.value;
+}
+
+void gem_context_set_vm(int fd, uint32_t ctx_id, uint32_t vm_id)
+{
+	struct drm_i915_gem_context_param p = {
+		.param = I915_CONTEXT_PARAM_VM,
+		.ctx_id = ctx_id,
+		.value = vm_id,
+	};
+
+	gem_context_set_param(fd, &p);
+}
diff --git a/lib/i915/gem_context.h b/lib/i915/gem_context.h
index 505d55724e..2a2247fe10 100644
--- a/lib/i915/gem_context.h
+++ b/lib/i915/gem_context.h
@@ -63,4 +63,7 @@ void gem_context_set_persistence(int i915, uint32_t ctx, bool state);
 
 bool gem_context_has_engine(int fd, uint32_t ctx, uint64_t engine);
 
+uint32_t gem_context_get_vm(int fd, uint32_t ctx_id);
+void gem_context_set_vm(int fd, uint32_t ctx_id, uint32_t vm_id);
+
 #endif /* GEM_CONTEXT_H */
diff --git a/lib/i915/gem_vm.c b/lib/i915/gem_vm.c
index 9a022a56c7..ee3c65d06e 100644
--- a/lib/i915/gem_vm.c
+++ b/lib/i915/gem_vm.c
@@ -48,7 +48,7 @@ bool gem_has_vm(int i915)
 {
 	uint32_t vm_id = 0;
 
-	__gem_vm_create(i915, &vm_id);
+	__gem_vm_create(i915, 0, &vm_id);
 	if (vm_id)
 		gem_vm_destroy(i915, vm_id);
 
@@ -67,9 +67,9 @@ void gem_require_vm(int i915)
 	igt_require(gem_has_vm(i915));
 }
 
-int __gem_vm_create(int i915, uint32_t *vm_id)
+int __gem_vm_create(int i915, uint32_t flags, uint32_t *vm_id)
 {
-       struct drm_i915_gem_vm_control ctl = {};
+       struct drm_i915_gem_vm_control ctl = { .flags = flags };
        int err = 0;
 
        if (igt_ioctl(i915, DRM_IOCTL_I915_GEM_VM_CREATE, &ctl) == 0) {
@@ -88,7 +88,8 @@ int __gem_vm_create(int i915, uint32_t *vm_id)
  * @i915: open i915 drm file descriptor
  *
  * This wraps the VM_CREATE ioctl, which is used to allocate a new
- * address space for use with GEM contexts.
+ * address space for use with GEM contexts, with legacy execbuff
+ * method of binding.
  *
  * Returns: The id of the allocated address space.
  */
@@ -96,7 +97,27 @@ uint32_t gem_vm_create(int i915)
 {
 	uint32_t vm_id;
 
-	igt_assert_eq(__gem_vm_create(i915, &vm_id), 0);
+	igt_assert_eq(__gem_vm_create(i915, 0, &vm_id), 0);
+	igt_assert(vm_id != 0);
+
+	return vm_id;
+}
+
+/**
+ * gem_vm_create_in_vm_bind_mode:
+ * @i915: open i915 drm file descriptor
+ *
+ * This wraps the VM_CREATE ioctl with I915_VM_CREATE_FLAGS_USE_VM_BIND,
+ * flag which is used to allocate a new address space for use with GEM contexts
+ * with vm_bind mode of binding.
+ *
+ * Returns: The id of the allocated address space.
+ */
+uint32_t gem_vm_create_in_vm_bind_mode(int i915)
+{
+	uint32_t vm_id;
+
+	igt_assert_eq(__gem_vm_create(i915, I915_VM_CREATE_FLAGS_USE_VM_BIND, &vm_id), 0);
 	igt_assert(vm_id != 0);
 
 	return vm_id;
diff --git a/lib/i915/gem_vm.h b/lib/i915/gem_vm.h
index acbb663e65..6cf46d8876 100644
--- a/lib/i915/gem_vm.h
+++ b/lib/i915/gem_vm.h
@@ -31,7 +31,8 @@ bool gem_has_vm(int i915);
 void gem_require_vm(int i915);
 
 uint32_t gem_vm_create(int i915);
-int __gem_vm_create(int i915, uint32_t *vm_id);
+uint32_t gem_vm_create_in_vm_bind_mode(int i915);
+int __gem_vm_create(int i915, uint32_t flags, uint32_t *vm_id);
 
 void gem_vm_destroy(int i915, uint32_t vm_id);
 int __gem_vm_destroy(int i915, uint32_t vm_id);
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 05/12] lib/vm_bind: Add vm_bind specific library functions

[Niranjana Vishwanathapura]

Add vm_bind specific library interfaces.

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 lib/i915/i915_vm_bind.c | 61 +++++++++++++++++++++++++++++++++++++++++
 lib/i915/i915_vm_bind.h | 16 +++++++++++
 lib/meson.build         |  1 +
 3 files changed, 78 insertions(+)
 create mode 100644 lib/i915/i915_vm_bind.c
 create mode 100644 lib/i915/i915_vm_bind.h

diff --git a/lib/i915/i915_vm_bind.c b/lib/i915/i915_vm_bind.c
new file mode 100644
index 0000000000..5624f589b5
--- /dev/null
+++ b/lib/i915/i915_vm_bind.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include <errno.h>
+#include <string.h>
+#include <sys/ioctl.h>
+
+#include "ioctl_wrappers.h"
+#include "i915_drm.h"
+#include "i915_drm_local.h"
+#include "i915_vm_bind.h"
+
+void i915_vm_bind(int i915, uint32_t vm_id, uint64_t va, uint32_t handle,
+		  uint64_t offset, uint64_t length, uint32_t syncobj,
+		  uint64_t fence_value)
+{
+	struct drm_i915_gem_vm_bind bind;
+
+	memset(&bind, 0, sizeof(bind));
+	bind.vm_id = vm_id;
+	bind.handle = handle;
+	bind.start = va;
+	bind.offset = offset;
+	bind.length = length;
+	if (syncobj) {
+		bind.fence.handle = syncobj;
+		bind.fence.value = fence_value;
+		bind.fence.flags = I915_TIMELINE_FENCE_SIGNAL;
+	}
+
+	gem_vm_bind(i915, &bind);
+}
+
+void i915_vm_unbind(int i915, uint32_t vm_id, uint64_t va, uint64_t length)
+{
+	struct drm_i915_gem_vm_unbind unbind;
+
+	memset(&unbind, 0, sizeof(unbind));
+	unbind.vm_id = vm_id;
+	unbind.start = va;
+	unbind.length = length;
+
+	gem_vm_unbind(i915, &unbind);
+}
+
+int i915_vm_bind_version(int i915)
+{
+	struct drm_i915_getparam gp;
+	int value = 0;
+
+	memset(&gp, 0, sizeof(gp));
+	gp.param = I915_PARAM_VM_BIND_VERSION;
+	gp.value = &value;
+
+	ioctl(i915, DRM_IOCTL_I915_GETPARAM, &gp, sizeof(gp));
+	errno = 0;
+
+	return value;
+}
diff --git a/lib/i915/i915_vm_bind.h b/lib/i915/i915_vm_bind.h
new file mode 100644
index 0000000000..46a382c032
--- /dev/null
+++ b/lib/i915/i915_vm_bind.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+#ifndef _I915_VM_BIND_H_
+#define _I915_VM_BIND_H_
+
+#include <stdint.h>
+
+void i915_vm_bind(int i915, uint32_t vm_id, uint64_t va, uint32_t handle,
+		  uint64_t offset, uint64_t length, uint32_t syncobj,
+		  uint64_t fence_value);
+void i915_vm_unbind(int i915, uint32_t vm_id, uint64_t va, uint64_t length);
+int i915_vm_bind_version(int i915);
+
+#endif /* _I915_VM_BIND_ */
diff --git a/lib/meson.build b/lib/meson.build
index 1fa6d6ee61..955e09ba34 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -14,6 +14,7 @@ lib_sources = [
 	'i915/intel_mocs.c',
 	'i915/i915_blt.c',
 	'i915/i915_crc.c',
+	'i915/i915_vm_bind.c',
 	'igt_collection.c',
 	'igt_color_encoding.c',
 	'igt_crc.c',
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 06/12] lib/vm_bind: Add __prime_handle_to_fd()

[Niranjana Vishwanathapura]

Make __prime_handle_to_fd() as a library interface as VM_BIND
functionality will also be using it.

v2: Rename prime_handle_to_fd_no_assert() to __prime_handle_to_fd()

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 lib/ioctl_wrappers.c    | 39 +++++++++++++++++++++++++++++++++------
 lib/ioctl_wrappers.h    |  1 +
 tests/i915/gem_pwrite.c | 16 +---------------
 tests/prime_mmap.c      | 26 ++++----------------------
 4 files changed, 39 insertions(+), 43 deletions(-)

diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index ac37b6bb43..db9cbb724c 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -1153,28 +1153,55 @@ void gem_require_mocs_registers(int fd)
 /* prime */
 
 /**
- * prime_handle_to_fd:
+ * __prime_handle_to_fd:
  * @fd: open i915 drm file descriptor
  * @handle: file-private gem buffer object handle
+ * @flags: DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl flags
+ * @fd_out: place holder for output file handle
  *
  * This wraps the PRIME_HANDLE_TO_FD ioctl, which is used to export a gem buffer
  * object into a global (i.e. potentially cross-device) dma-buf file-descriptor
  * handle.
  *
- * Returns: The created dma-buf fd handle.
+ * Returns: 0 on success, error otherwise. Upon success, it returns
+ *          the created dma-buf fd handle in fd_out.
  */
-int prime_handle_to_fd(int fd, uint32_t handle)
+int __prime_handle_to_fd(int fd, uint32_t handle, int flags, int *fd_out)
 {
 	struct drm_prime_handle args;
+	int ret;
 
 	memset(&args, 0, sizeof(args));
 	args.handle = handle;
-	args.flags = DRM_CLOEXEC;
+	args.flags = flags;
 	args.fd = -1;
 
-	do_ioctl(fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &args);
+	ret = drmIoctl(fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &args);
+	if (ret)
+		ret = -errno;
+	*fd_out = args.fd;
 
-	return args.fd;
+	return ret;
+}
+
+/**
+ * prime_handle_to_fd:
+ * @fd: open i915 drm file descriptor
+ * @handle: file-private gem buffer object handle
+ *
+ * This wraps the PRIME_HANDLE_TO_FD ioctl, which is used to export a gem buffer
+ * object into a global (i.e. potentially cross-device) dma-buf file-descriptor
+ * handle. It asserts that ioctl succeeds.
+ *
+ * Returns: The created dma-buf fd handle.
+ */
+int prime_handle_to_fd(int fd, uint32_t handle)
+{
+	int dmabuf;
+
+	igt_assert_eq(__prime_handle_to_fd(fd, handle, DRM_CLOEXEC, &dmabuf), 0);
+
+	return dmabuf;
 }
 
 /**
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 223cd9160c..66faa27551 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -143,6 +143,7 @@ struct local_dma_buf_sync {
 #define LOCAL_DMA_BUF_BASE 'b'
 #define LOCAL_DMA_BUF_IOCTL_SYNC _IOW(LOCAL_DMA_BUF_BASE, 0, struct local_dma_buf_sync)
 
+int __prime_handle_to_fd(int fd, uint32_t handle, int flags, int *fd_out);
 int prime_handle_to_fd(int fd, uint32_t handle);
 #ifndef DRM_RDWR
 #define DRM_RDWR O_RDWR
diff --git a/tests/i915/gem_pwrite.c b/tests/i915/gem_pwrite.c
index 6e3f833cd8..f4fe069caf 100644
--- a/tests/i915/gem_pwrite.c
+++ b/tests/i915/gem_pwrite.c
@@ -293,19 +293,6 @@ struct ufd_thread {
 	int err;
 };
 
-static int __prime_handle_to_fd(int fd, uint32_t handle)
-{
-	struct drm_prime_handle args;
-
-	memset(&args, 0, sizeof(args));
-	args.handle = handle;
-	args.flags = DRM_CLOEXEC;
-	args.fd = -1;
-
-	ioctl(fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &args);
-	return args.fd;
-}
-
 static uint32_t dmabuf_create_handle(int i915, int vgem)
 {
 	struct vgem_bo scratch;
@@ -317,8 +304,7 @@ static uint32_t dmabuf_create_handle(int i915, int vgem)
 	scratch.bpp = 32;
 	vgem_create(vgem, &scratch);
 
-	dmabuf = __prime_handle_to_fd(vgem, scratch.handle);
-	if (dmabuf < 0)
+	if (__prime_handle_to_fd(vgem, scratch.handle, DRM_CLOEXEC, &dmabuf))
 		return 0;
 
 	handle = prime_fd_to_handle(i915, dmabuf);
diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
index bc19f68c98..432e857631 100644
--- a/tests/prime_mmap.c
+++ b/tests/prime_mmap.c
@@ -298,24 +298,6 @@ test_dup(uint32_t region, uint64_t size)
 	close (dma_buf_fd);
 }
 
-/* Used for error case testing to avoid wrapper */
-static int prime_handle_to_fd_no_assert(uint32_t handle, int flags, int *fd_out)
-{
-	struct drm_prime_handle args;
-	int ret;
-
-	args.handle = handle;
-	args.flags = flags;
-	args.fd = -1;
-
-	ret = drmIoctl(fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &args);
-	if (ret)
-		ret = errno;
-	*fd_out = args.fd;
-
-	return ret;
-}
-
 static bool has_userptr(void)
 {
 	uint32_t handle = 0;
@@ -346,9 +328,9 @@ test_userptr(uint32_t region, uint64_t size)
 	gem_userptr(fd, (uint32_t *)ptr, size, 0, 0, &handle);
 
 	/* export userptr */
-	ret = prime_handle_to_fd_no_assert(handle, DRM_CLOEXEC, &dma_buf_fd);
+	ret = __prime_handle_to_fd(fd, handle, DRM_CLOEXEC, &dma_buf_fd);
 	if (ret) {
-		igt_assert(ret == EINVAL || ret == ENODEV);
+		igt_assert(ret == -EINVAL || ret == -ENODEV);
 		goto free_userptr;
 	} else {
 		igt_assert_eq(ret, 0);
@@ -376,7 +358,7 @@ test_errors(uint32_t region, uint64_t size)
 	/* Test for invalid flags */
 	igt_assert(__gem_create_in_memory_regions(fd, &handle, &size, region) == 0);
 	for (i = 0; i < ARRAY_SIZE(invalid_flags); i++) {
-		prime_handle_to_fd_no_assert(handle, invalid_flags[i], &dma_buf_fd);
+		__prime_handle_to_fd(fd, handle, invalid_flags[i], &dma_buf_fd);
 		igt_assert_eq(errno, EINVAL);
 		errno = 0;
 	}
@@ -386,7 +368,7 @@ test_errors(uint32_t region, uint64_t size)
 	igt_assert(__gem_create_in_memory_regions(fd, &handle, &size, region) == 0);
 	fill_bo(handle, size);
 	gem_close(fd, handle);
-	prime_handle_to_fd_no_assert(handle, DRM_CLOEXEC, &dma_buf_fd);
+	__prime_handle_to_fd(fd, handle, DRM_CLOEXEC, &dma_buf_fd);
 	igt_assert(dma_buf_fd == -1 && errno == ENOENT);
 	errno = 0;
 
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 07/12] tests/i915/vm_bind: Add vm_bind sanity test

[Niranjana Vishwanathapura]

Add sanity test to exercise vm_bind uapi.
Test for various cases with vm_bind and vm_unbind ioctls.

v2: Add more input validity tests
    Add sanity test to fast-feedback.testlist
v3: Add only basic-smem subtest to fast-feedback.testlist
v4: Use gem_create_ext to create vm private objects,
    Ensure vm private objects are only allowed in vm_bind mode,
    Use library routine i915_vm_bind_version()
v5: Add execbuf3 sanity tests, use mr->gtt_alignment,
    add non-recoverable context sanity test

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/i915/i915_vm_bind_sanity.c      | 306 ++++++++++++++++++++++++++
 tests/intel-ci/fast-feedback.testlist |   1 +
 tests/meson.build                     |   1 +
 3 files changed, 308 insertions(+)
 create mode 100644 tests/i915/i915_vm_bind_sanity.c

diff --git a/tests/i915/i915_vm_bind_sanity.c b/tests/i915/i915_vm_bind_sanity.c
new file mode 100644
index 0000000000..69455b8072
--- /dev/null
+++ b/tests/i915/i915_vm_bind_sanity.c
@@ -0,0 +1,306 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+/** @file i915_vm_bind_sanity.c
+ *
+ * This is the sanity test for VM_BIND UAPI.
+ *
+ * The goal is to test the UAPI interface.
+ */
+
+#include <errno.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+#include <sys/poll.h>
+
+#include "i915/gem.h"
+#include "i915/gem_create.h"
+#include "i915/gem_vm.h"
+#include "i915/i915_vm_bind.h"
+#include "intel_allocator.h"
+#include "igt.h"
+#include "igt_syncobj.h"
+
+#define PAGE_SIZE   4096
+#define SZ_64K      (16 * PAGE_SIZE)
+#define SZ_2M       (512 * PAGE_SIZE)
+
+IGT_TEST_DESCRIPTION("Sanity test vm_bind related interfaces");
+
+static uint64_t
+gettime_ns(void)
+{
+	struct timespec current;
+	clock_gettime(CLOCK_MONOTONIC, &current);
+	return (uint64_t)current.tv_sec * NSEC_PER_SEC + current.tv_nsec;
+}
+
+static bool syncobj_busy(int fd, uint32_t handle)
+{
+	bool result;
+	int sf;
+
+	sf = syncobj_handle_to_fd(fd, handle,
+				  DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE);
+	result = poll(&(struct pollfd){sf, POLLIN}, 1, 0) == 0;
+	close(sf);
+
+	return result;
+}
+
+static inline int
+__vm_bind(int fd, uint32_t vm_id, uint32_t handle, uint64_t start,
+	  uint64_t offset, uint64_t length, uint64_t flags,
+	  struct drm_i915_gem_timeline_fence *fence, uint64_t extensions)
+{
+	struct drm_i915_gem_vm_bind bind;
+
+	memset(&bind, 0, sizeof(bind));
+	bind.vm_id = vm_id;
+	bind.handle = handle;
+	bind.start = start;
+	bind.offset = offset;
+	bind.length = length;
+	bind.flags = flags;
+	bind.extensions = extensions;
+	if (fence)
+		bind.fence = *fence;
+
+	return __gem_vm_bind(fd, &bind);
+}
+
+static inline void
+vm_bind(int fd, uint32_t vm_id, uint32_t handle, uint64_t start,
+	uint64_t offset, uint64_t length, uint64_t flags,
+	struct drm_i915_gem_timeline_fence *fence)
+{
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, start, offset,
+				length, flags, fence, 0), 0);
+	if (fence) {
+		igt_assert(syncobj_timeline_wait(fd, &fence->handle, (uint64_t *)&fence->value,
+						 1, gettime_ns() + (2 * NSEC_PER_SEC),
+						 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
+		igt_assert(!syncobj_busy(fd, fence->handle));
+	}
+}
+
+static inline int
+__vm_unbind(int fd, uint32_t vm_id, uint64_t start, uint64_t length, uint64_t flags,
+	    uint32_t rsvd, uint64_t rsvd2_0, uint64_t rsvd2_1, uint64_t extensions)
+{
+	struct drm_i915_gem_vm_unbind unbind;
+
+	memset(&unbind, 0, sizeof(unbind));
+	unbind.vm_id = vm_id;
+	unbind.rsvd = rsvd;
+	unbind.rsvd2[0] = rsvd2_0;
+	unbind.rsvd2[1] = rsvd2_1;
+	unbind.start = start;
+	unbind.length = length;
+	unbind.flags = flags;
+	unbind.extensions = extensions;
+
+	return __gem_vm_unbind(fd, &unbind);
+}
+
+static inline void
+vm_unbind(int fd, uint32_t vm_id, uint64_t start, uint64_t length, uint64_t flags)
+{
+	igt_assert_eq(__vm_unbind(fd, vm_id, start, length, flags, 0, 0, 0, 0), 0);
+}
+
+static void basic(int fd, const struct gem_memory_region *mr)
+{
+	uint32_t vm_id, vm_id2, vm_id_exec_mode, handle;
+	struct drm_i915_gem_create_ext_memory_regions setparam_region = {
+		.base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
+		.regions = to_user_pointer(&mr->ci),
+		.num_regions = 1,
+	};
+	struct drm_i915_gem_timeline_fence fence = {
+		.handle = syncobj_create(fd, 0),
+		.flags = I915_TIMELINE_FENCE_SIGNAL,
+		.value = 0,
+	};
+	struct drm_i915_gem_create_ext_vm_private vm_priv = {
+		.base = { .name = I915_GEM_CREATE_EXT_VM_PRIVATE },
+	};
+	struct drm_i915_gem_context_param param = {
+		.param = I915_CONTEXT_PARAM_RECOVERABLE,
+		.value = 0,
+	};
+	struct drm_i915_gem_execbuffer3 execbuf3;
+	struct drm_i915_gem_execbuffer2 execbuf;
+	struct drm_i915_gem_exec_object2 obj;
+	uint64_t pg_size = mr->gtt_alignment;
+	uint64_t ahnd, va, size = pg_size * 4;
+	const intel_ctx_t *ctx;
+	int dmabuf;
+
+	ahnd = intel_allocator_open_full(fd, 1, 0, 0,
+					 INTEL_ALLOCATOR_RANDOM,
+					 ALLOC_STRATEGY_HIGH_TO_LOW,
+					 pg_size);
+
+	vm_id = gem_vm_create_in_vm_bind_mode(fd);
+	handle = gem_create_ext(fd, size, 0, &setparam_region.base);
+	va = CANONICAL(get_offset(ahnd, handle, size, 0));
+
+	/* Bind and unbind */
+	vm_bind(fd, vm_id, handle, va, 0, size, 0, NULL);
+	vm_unbind(fd, vm_id, va, size, 0);
+
+	/* Bind with out fence */
+	vm_bind(fd, vm_id, handle, va, 0, size, 0, &fence);
+	vm_unbind(fd, vm_id, va, size, 0);
+
+	/* Aliasing bind and unbind */
+	vm_bind(fd, vm_id, handle, va, 0, size, 0, NULL);
+	vm_bind(fd, vm_id, handle, va + SZ_2M, 0, size, 0, NULL);
+	vm_unbind(fd, vm_id, va, size, 0);
+	vm_unbind(fd, vm_id, va + SZ_2M, size, 0);
+
+	/* MBZ fields are not 0 */
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, 0, size, 0x10, NULL, 0), -EINVAL);
+	fence.flags |= I915_TIMELINE_FENCE_WAIT;
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, 0, size, 0x10, &fence, 0), -EINVAL);
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, 0, size, 0, NULL, to_user_pointer(&obj)), -EINVAL);
+	vm_bind(fd, vm_id, handle, va, 0, size, 0, NULL);
+	igt_assert_eq(__vm_unbind(fd, vm_id, va, size, 0x10, 0, 0, 0, 0), -EINVAL);
+	igt_assert_eq(__vm_unbind(fd, vm_id, va, size, 0, 0x10, 0, 0, 0), -EINVAL);
+	igt_assert_eq(__vm_unbind(fd, vm_id, va, size, 0, 0, 0x10, 0, 0), -EINVAL);
+	igt_assert_eq(__vm_unbind(fd, vm_id, va, size, 0, 0, 0, 0x10, 0), -EINVAL);
+	igt_assert_eq(__vm_unbind(fd, vm_id, va, size, 0, 0, 0, 0, to_user_pointer(&obj)), -EINVAL);
+	vm_unbind(fd, vm_id, va, size, 0);
+
+	/* Invalid handle */
+	igt_assert_eq(__vm_bind(fd, vm_id, handle + 10, va, 0, size, 0, NULL, 0), -ENOENT);
+
+	/* Invalid mapping range */
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, 0, 0, 0, NULL, 0), -EINVAL);
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, pg_size, size, 0, NULL, 0), -EINVAL);
+
+	/* Unaligned binds */
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va + 0x10, 0, size, 0, NULL, 0), -EINVAL);
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, pg_size / 2, pg_size, 0, NULL, 0), -EINVAL);
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, 0, pg_size / 2, 0, NULL, 0), -EINVAL);
+
+	/* range overflow binds */
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, pg_size, -pg_size, 0, NULL, 0), -EINVAL);
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, pg_size * 2, -pg_size, 0, NULL, 0), -EINVAL);
+
+	/* re-bind VA range without unbinding */
+	vm_bind(fd, vm_id, handle, va, 0, size, 0, NULL);
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, 0, size, 0, NULL, 0), -EEXIST);
+	vm_unbind(fd, vm_id, va, size, 0);
+
+	/* unbind a non-existing mapping */
+	igt_assert_eq(__vm_bind(fd, vm_id, 0, va + SZ_2M, 0, size, 0, NULL, 0), -ENOENT);
+
+	/* unbind with length mismatch */
+	vm_bind(fd, vm_id, handle, va, 0, size, 0, NULL);
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, 0, size * 2, 0, NULL, 0), -EINVAL);
+	vm_unbind(fd, vm_id, va, size, 0);
+
+	/* validate exclusivity of vm_bind & exec modes of binding */
+	vm_id_exec_mode = gem_vm_create(fd);
+	igt_assert_eq(__vm_bind(fd, vm_id_exec_mode, handle, va, 0, size, 0, NULL, 0), -EOPNOTSUPP);
+
+	/* validate vm_bind mode doesn't work with the default recoverble context */
+	ctx = intel_ctx_create_all_physical(fd);
+	gem_context_set_vm(fd, ctx->id, vm_id);
+	param.ctx_id = ctx->id;
+	igt_assert_eq(__gem_context_get_param(fd, &param), -EINVAL);
+	intel_ctx_destroy(fd, ctx);
+
+	/* create context, make it non-recoverable and assign vm_bind vm */
+	ctx = intel_ctx_create_all_physical(fd);
+	gem_context_set_param(fd, &param);
+	gem_context_set_vm(fd, ctx->id, vm_id);
+	(void)gem_context_get_vm(fd, ctx->id);
+
+	memset(&obj, 0, sizeof(obj));
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = to_user_pointer(&obj);
+	execbuf.buffer_count = 1;
+	obj.handle = handle;
+	i915_execbuffer2_set_context_id(execbuf, ctx->id);
+	igt_assert_eq(__gem_execbuf(fd, &execbuf), -EOPNOTSUPP);
+
+	memset(&execbuf3, 0, sizeof(execbuf3));
+	igt_assert_eq(__gem_execbuf3(fd, &execbuf3), -EOPNOTSUPP);
+
+	/* execbuf3 MBZ fields are not 0 */
+	execbuf3.ctx_id = ctx->id;
+	execbuf3.flags = 0x10;
+	igt_assert_eq(__gem_execbuf3(fd, &execbuf3), -EINVAL);
+	execbuf3.flags = 0;
+	execbuf3.rsvd = 0x10;
+	igt_assert_eq(__gem_execbuf3(fd, &execbuf3), -EINVAL);
+	execbuf3.rsvd = 0;
+	execbuf3.extensions = to_user_pointer(&obj);
+	igt_assert_eq(__gem_execbuf3(fd, &execbuf3), -EINVAL);
+
+	intel_ctx_destroy(fd, ctx);
+	gem_vm_destroy(fd, vm_id_exec_mode);
+	gem_close(fd, handle);
+
+	/* validate VM private objects */
+	setparam_region.base.next_extension = to_user_pointer(&vm_priv);
+	igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle,
+				       &setparam_region.base), -ENOENT);
+	vm_priv.rsvd = 0x10;
+	igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle,
+				       &setparam_region.base), -EINVAL);
+	vm_id2 = gem_vm_create(fd);
+	vm_priv.rsvd = 0;
+	vm_priv.vm_id = vm_id2;
+	igt_assert_eq(__gem_create_ext(fd, &size, 0, &handle,
+				       &setparam_region.base), -EINVAL);
+	gem_vm_destroy(fd, vm_id2);
+
+	vm_id2 = gem_vm_create_in_vm_bind_mode(fd);
+	vm_priv.vm_id = vm_id2;
+	handle = gem_create_ext(fd, size, 0, &setparam_region.base);
+
+	igt_assert_eq(__prime_handle_to_fd(fd, handle, DRM_CLOEXEC, &dmabuf), -EINVAL);
+	igt_assert_eq(__vm_bind(fd, vm_id, handle, va, 0, size, 0, NULL, 0), -EINVAL);
+	vm_bind(fd, vm_id2, handle, va, 0, size, 0, NULL);
+	vm_unbind(fd, vm_id2, va, size, 0);
+
+	gem_close(fd, handle);
+	gem_vm_destroy(fd, vm_id2);
+	gem_vm_destroy(fd, vm_id);
+	syncobj_destroy(fd, fence.handle);
+	intel_allocator_close(ahnd);
+}
+
+igt_main
+{
+	int fd;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(fd);
+		igt_require(i915_vm_bind_version(fd) == 1);
+	}
+
+	igt_describe("Basic vm_bind sanity test");
+	igt_subtest_with_dynamic("basic") {
+		for_each_memory_region(r, fd) {
+			if (r->ci.memory_instance)
+				continue;
+
+			igt_dynamic_f("%s", r->name)
+				basic(fd, r);
+		}
+	}
+
+	igt_fixture {
+		close(fd);
+	}
+
+	igt_exit();
+}
diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index bd5538a035..185c2fef54 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -53,6 +53,7 @@ igt@i915_getparams_basic@basic-eu-total
 igt@i915_getparams_basic@basic-subslice-total
 igt@i915_hangman@error-state-basic
 igt@i915_pciid
+igt@i915_vm_bind_sanity@basic
 igt@kms_addfb_basic@addfb25-bad-modifier
 igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling
 igt@kms_addfb_basic@addfb25-modifier-no-flag
diff --git a/tests/meson.build b/tests/meson.build
index 12e53e0bd2..423db3057b 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -225,6 +225,7 @@ i915_progs = [
 	'i915_query',
 	'i915_selftest',
 	'i915_suspend',
+	'i915_vm_bind_sanity',
 	'kms_big_fb',
 	'kms_big_joiner' ,
 	'kms_busy',
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 08/12] tests/i915/vm_bind: Add basic VM_BIND test support

[Niranjana Vishwanathapura]

Add basic tests for VM_BIND functionality. Bind the buffer objects in
device page table with VM_BIND calls and have GPU copy the data from a
source buffer object to destination buffer object.
Test for different buffer sizes, buffer object placement and with
multiple contexts.

v2: Add basic test to fast-feedback.testlist
v3: Run all tests for different memory types,
    pass VA instead of an array for batch_address
v4: Iterate for memory region types instead of hardcoding,
    use i915_vm_bind library functions
v5: Validate synchronous vm_bind, require blt engine,
    use mr->gtt_alignment instead of HAS_64K_PAGES,
    change info to debug messages, remove igt_collection usage,
    fix dg2 alignment issue

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/i915/i915_vm_bind_basic.c       | 559 ++++++++++++++++++++++++++
 tests/intel-ci/fast-feedback.testlist |   1 +
 tests/meson.build                     |   1 +
 3 files changed, 561 insertions(+)
 create mode 100644 tests/i915/i915_vm_bind_basic.c

diff --git a/tests/i915/i915_vm_bind_basic.c b/tests/i915/i915_vm_bind_basic.c
new file mode 100644
index 0000000000..e794f0a845
--- /dev/null
+++ b/tests/i915/i915_vm_bind_basic.c
@@ -0,0 +1,559 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+/** @file i915_vm_bind_basic.c
+ *
+ * This is the basic test for VM_BIND functionality.
+ *
+ * The goal is to ensure that basics work.
+ */
+
+#include <sys/poll.h>
+
+#include "i915/gem.h"
+#include "i915/i915_vm_bind.h"
+#include "igt.h"
+#include "igt_syncobj.h"
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <fcntl.h>
+#include <inttypes.h>
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include "drm.h"
+#include "i915/gem_vm.h"
+
+IGT_TEST_DESCRIPTION("Basic test for vm_bind functionality");
+
+#define PAGE_SIZE   4096
+#define PAGE_SHIFT  12
+
+#define GEN9_XY_FAST_COPY_BLT_CMD       (2 << 29 | 0x42 << 22)
+#define BLT_DEPTH_32                    (3 << 24)
+
+#define DEFAULT_BUFF_SIZE  (4 * PAGE_SIZE)
+#define SZ_64K             (16 * PAGE_SIZE)
+#define SZ_2M              (512 * PAGE_SIZE)
+
+#define MAX_CTXTS   2
+#define MAX_CMDS    4
+
+#define EXEC_FENCE   0
+#define BATCH_FENCE  1
+#define SRC_FENCE    2
+#define DST_FENCE    3
+#define NUM_FENCES   4
+
+enum {
+	BATCH_MAP,
+	SRC_MAP,
+	DST_MAP = SRC_MAP + MAX_CMDS,
+	MAX_MAP
+};
+
+struct mapping {
+	uint32_t  obj;
+	uint64_t  va;
+	uint64_t  offset;
+	uint64_t  length;
+	uint64_t  flags;
+};
+
+#define SET_MAP(map, _obj, _va, _offset, _length, _flags)   \
+{                                  \
+	(map).obj = _obj;          \
+	(map).va = _va;            \
+	(map).offset = _offset;	   \
+	(map).length = _length;	   \
+	(map).flags = _flags;	   \
+}
+
+#define MAX_BATCH_DWORD    64
+
+#define abs(x) ((x) >= 0 ? (x) : -(x))
+
+#define TEST_SKIP_UNBIND      BIT(0)
+#define TEST_SHARE_VM         BIT(1)
+#define TEST_SYNC_BIND        BIT(2)
+
+#define do_unbind(cfg)      (!((cfg)->flags & TEST_SKIP_UNBIND))
+#define do_share_vm(cfg)    ((cfg)->flags & TEST_SHARE_VM)
+#define do_sync_bind(cfg)   ((cfg)->flags & TEST_SYNC_BIND)
+
+struct test_cfg {
+	const char *name;
+	uint32_t size;
+	uint8_t num_cmds;
+	uint32_t num_ctxts;
+	uint32_t flags;
+};
+
+static uint64_t
+gettime_ns(void)
+{
+	struct timespec current;
+	clock_gettime(CLOCK_MONOTONIC, &current);
+	return (uint64_t)current.tv_sec * NSEC_PER_SEC + current.tv_nsec;
+}
+
+static bool syncobj_busy(int fd, uint32_t handle)
+{
+	bool result;
+	int sf;
+
+	sf = syncobj_handle_to_fd(fd, handle,
+				  DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE);
+	result = poll(&(struct pollfd){sf, POLLIN}, 1, 0) == 0;
+	close(sf);
+
+	return result;
+}
+
+static inline void vm_bind(int fd, uint32_t vm_id, struct mapping *m,
+			   struct drm_i915_gem_timeline_fence *fence)
+{
+	uint32_t syncobj = 0;
+
+	if (fence) {
+		syncobj = syncobj_create(fd, 0);
+
+		fence->handle = syncobj;
+		fence->flags = I915_TIMELINE_FENCE_WAIT;
+		fence->value = 0;
+	}
+
+	igt_debug("VM_BIND vm:0x%x h:0x%x v:0x%lx o:0x%lx l:0x%lx\n",
+		  vm_id, m->obj, m->va, m->offset, m->length);
+	i915_vm_bind(fd, vm_id, m->va, m->obj, m->offset, m->length, syncobj, 0);
+}
+
+static inline void vm_unbind(int fd, uint32_t vm_id, struct mapping *m)
+{
+	/* Object handle is not required during unbind */
+	igt_debug("VM_UNBIND vm:0x%x v:0x%lx l:0x%lx\n", vm_id, m->va, m->length);
+	i915_vm_unbind(fd, vm_id, m->va, m->length);
+}
+
+static void debug_dump_buffer(void *buf, uint32_t size,
+			      const char *str, bool full)
+{
+	uint32_t i = 0;
+
+	igt_debug("Printing %s size 0x%x\n", str, size);
+	while (i < size) {
+		uint32_t *b = buf + i;
+
+		igt_debug("\t%s[0x%04x]: 0x%08x 0x%08x 0x%08x 0x%08x %s\n",
+			  str, i, b[0], b[1], b[2], b[3], full ? "" : "...");
+		i += full ? 16 : PAGE_SIZE;
+	}
+}
+
+static int gem_linear_fast_blt(uint32_t *batch, uint64_t src,
+			       uint64_t dst, uint32_t size)
+{
+	uint32_t *cmd = batch;
+
+	*cmd++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
+	*cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
+	*cmd++ = 0;
+	*cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
+	*cmd++ = lower_32_bits(dst);
+	*cmd++ = upper_32_bits(dst);
+	*cmd++ = 0;
+	*cmd++ = PAGE_SIZE;
+	*cmd++ = lower_32_bits(src);
+	*cmd++ = upper_32_bits(src);
+
+	*cmd++ = MI_BATCH_BUFFER_END;
+	*cmd++ = 0;
+
+	return ALIGN((cmd - batch + 1) * sizeof(uint32_t), 8);
+}
+
+static void __gem_copy(int fd, uint64_t src, uint64_t dst, uint32_t size,
+		       uint32_t ctx_id, void *batch_addr, unsigned int eb_flags,
+		       struct drm_i915_gem_timeline_fence *fence,
+		       uint64_t fence_count)
+{
+	uint32_t len, buf[MAX_BATCH_DWORD] = { 0 };
+	struct drm_i915_gem_execbuffer3 execbuf;
+
+	len = gem_linear_fast_blt(buf, src, dst, size);
+
+	memcpy(batch_addr, (void *)buf, len);
+	debug_dump_buffer(buf, len, "batch", true);
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.ctx_id = ctx_id;
+	execbuf.batch_address = to_user_pointer(batch_addr);
+	execbuf.engine_idx = eb_flags;
+	execbuf.fence_count = fence_count;
+	execbuf.timeline_fences = to_user_pointer(fence);
+	gem_execbuf3(fd, &execbuf);
+}
+
+static void i915_gem_copy(int fd, uint64_t src, uint64_t dst, uint32_t va_delta,
+			  uint32_t delta, uint32_t size, const intel_ctx_t **ctx,
+			  uint32_t num_ctxts, void **batch_addr, unsigned int eb_flags,
+			  struct drm_i915_gem_timeline_fence (*fence)[NUM_FENCES],
+			  uint64_t fence_count)
+{
+	uint32_t i;
+
+	for (i = 0; i < num_ctxts; i++) {
+		igt_debug("Issuing gem copy on ctx 0x%x\n", ctx[i]->id);
+		__gem_copy(fd, src + (i * va_delta), dst + (i * va_delta), delta,
+			   ctx[i]->id, batch_addr[i], eb_flags, fence[i],  fence_count);
+	}
+}
+
+static void i915_gem_sync(int fd, const intel_ctx_t **ctx, uint32_t num_ctxts,
+			  struct drm_i915_gem_timeline_fence (*fence)[NUM_FENCES])
+{
+	uint32_t i;
+
+	for (i = 0; i < num_ctxts; i++) {
+		uint64_t fence_value = 0;
+
+		igt_assert(syncobj_timeline_wait(fd, &fence[i][EXEC_FENCE].handle,
+						 (uint64_t *)&fence_value, 1,
+						 gettime_ns() + (2 * NSEC_PER_SEC),
+						 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
+		igt_assert(!syncobj_busy(fd, fence[i][EXEC_FENCE].handle));
+		igt_debug("gem copy completed on ctx 0x%x\n", ctx[i]->id);
+	}
+}
+
+static uint32_t create_obj(int fd, struct gem_memory_region *mr, uint32_t size, void **addr)
+{
+	uint32_t handle;
+
+	handle = gem_create_in_memory_region_list(fd, size, 0, &mr->ci, 1);
+	*addr = gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
+
+	return handle;
+}
+
+static void destroy_obj(int fd, uint32_t handle, uint32_t size, void *addr)
+{
+	igt_assert(gem_munmap(addr, size) == 0);
+	gem_close(fd, handle);
+}
+
+static void create_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[],
+			    uint32_t size, uint32_t num_cmds, void *src_addr[])
+{
+	int i = 0;
+
+	if (!num_cmds)
+		return;
+
+	/* Create first src object always in memory region 'mr' */
+	src[i] = create_obj(fd, mr, size, &src_addr[i]);
+	igt_debug("Src (%s) obj 0x%x created\n", mr->name, src[i]);
+	num_cmds--;
+	i++;
+
+	if (!num_cmds)
+		return;
+
+	/* Create one src object in all other memory regions */
+	for_each_memory_region(r, fd) {
+		if (mr &&
+		    r->ci.memory_class == mr->ci.memory_class &&
+		    r->ci.memory_instance == mr->ci.memory_instance)
+			continue;
+
+		src[i] = create_obj(fd, r, size, &src_addr[i]);
+		igt_debug("Src (%s) obj 0x%x created\n", r->name, src[i]);
+		num_cmds--;
+		i++;
+	}
+
+	/* Create rest of the src objects in memory region 'mr' */
+	while (num_cmds) {
+		src[i] = create_obj(fd, mr, size, &src_addr[i]);
+		igt_debug("Src (%s) obj 0x%x created\n", mr->name, src[i]);
+		num_cmds--;
+		i++;
+	}
+}
+
+static void destroy_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[],
+			     uint32_t size, uint32_t num_cmds, void *src_addr[])
+{
+	int i;
+
+	for (i = 0; i < num_cmds; i++) {
+		igt_debug("Closing src object 0x%x\n", src[i]);
+		destroy_obj(fd, src[i], size, src_addr[i]);
+	}
+}
+
+static uint32_t create_dst_obj(int fd, struct gem_memory_region *mr, uint32_t size, void **dst_addr)
+{
+	uint32_t dst = create_obj(fd, mr, size, dst_addr);
+
+	igt_debug("Dst (%s) obj 0x%x created\n", mr->name, dst);
+	return dst;
+}
+
+static void destroy_dst_obj(int fd, struct gem_memory_region *mr, uint32_t dst,
+			    uint32_t size, void *dst_addr)
+{
+	igt_debug("Closing dst object 0x%x\n", dst);
+	destroy_obj(fd, dst, size, dst_addr);
+}
+
+static void pattern_fill_buf(void *src_addr[], uint32_t size, uint32_t num_cmds, uint32_t npages)
+{
+	uint32_t i, j;
+	void *buf;
+
+	/* Allocate buffer and fill pattern */
+	buf = malloc(size);
+	igt_require(buf);
+
+	for (i = 0; i < num_cmds; i++) {
+		for (j = 0; j < npages; j++)
+			memset(buf + j * PAGE_SIZE, i * npages + j + 1, PAGE_SIZE);
+
+		memcpy(src_addr[i], buf, size);
+	}
+
+	free(buf);
+}
+
+static void run_test(int fd, const intel_ctx_t *base_ctx, struct test_cfg *cfg,
+		     struct gem_memory_region *mr, uint32_t alignment,
+		     const struct intel_execution_engine2 *e)
+{
+	struct drm_i915_gem_timeline_fence exec_fence[MAX_CTXTS][NUM_FENCES] = { };
+	void *src_addr[MAX_CMDS] = { 0 }, *dst_addr = NULL;
+	uint32_t src[MAX_CMDS], dst, i, size = cfg->size;
+	uint32_t shared_vm_id, vm_id[MAX_CTXTS];
+	struct mapping map[MAX_CTXTS][MAX_MAP];
+	uint32_t num_ctxts = cfg->num_ctxts;
+	uint32_t num_cmds = cfg->num_cmds;
+	uint32_t npages = size / PAGE_SIZE;
+	const intel_ctx_t *ctx[MAX_CTXTS];
+	uint64_t src_va, dst_va, ahnd = 0;
+	bool share_vm = do_share_vm(cfg);
+	uint32_t delta, va_delta = SZ_2M;
+	void *batch_addr[MAX_CTXTS];
+	uint32_t batch[MAX_CTXTS];
+
+	delta = size / num_ctxts;
+	if (share_vm)
+		shared_vm_id = gem_vm_create_in_vm_bind_mode(fd);
+
+	/* Create contexts */
+	num_ctxts = min_t(num_ctxts, MAX_CTXTS, num_ctxts);
+	for (i = 0; i < num_ctxts; i++) {
+		struct drm_i915_gem_context_param param = {
+			.param = I915_CONTEXT_PARAM_RECOVERABLE,
+			.value = 0,
+		};
+		uint32_t vmid;
+
+		if (share_vm)
+			vmid = shared_vm_id;
+		else
+			vmid = gem_vm_create_in_vm_bind_mode(fd);
+
+		ctx[i] = intel_ctx_create(fd, &base_ctx->cfg);
+		param.ctx_id = ctx[i]->id;
+		gem_context_set_param(fd, &param);
+		gem_context_set_vm(fd, ctx[i]->id, vmid);
+		vm_id[i] = gem_context_get_vm(fd, ctx[i]->id);
+
+		exec_fence[i][EXEC_FENCE].handle = syncobj_create(fd, 0);
+		exec_fence[i][EXEC_FENCE].flags = I915_TIMELINE_FENCE_SIGNAL;
+		exec_fence[i][EXEC_FENCE].value = 0;
+	}
+
+	/* Create objects */
+	num_cmds = min_t(num_cmds, MAX_CMDS, num_cmds);
+	create_src_objs(fd, mr, src, size, num_cmds, src_addr);
+	dst = create_dst_obj(fd, mr, size, &dst_addr);
+
+	/*
+	 * mmap'ed addresses are PAGE_SIZE aligned. On platforms requiring
+	 * other alignment, use static addresses.
+	 */
+	if (num_cmds && (alignment == PAGE_SIZE)) {
+		src_va = to_user_pointer(src_addr[0]);
+		dst_va = to_user_pointer(dst_addr);
+	} else {
+		ahnd = intel_allocator_open_full(fd, 1, 0, 0,
+						 INTEL_ALLOCATOR_RANDOM,
+						 ALLOC_STRATEGY_HIGH_TO_LOW,
+						 alignment);
+		dst_va = CANONICAL(get_offset(ahnd, dst, size, 0));
+		if (num_cmds)
+			src_va = CANONICAL(get_offset(ahnd, src[0], size * num_cmds, 0));
+	}
+
+	pattern_fill_buf(src_addr, size, num_cmds, npages);
+
+	if (num_cmds)
+		debug_dump_buffer(src_addr[num_cmds - 1], size, "src_obj", false);
+
+	for (i = 0; i < num_ctxts; i++) {
+		batch[i] = gem_create_in_memory_regions(fd, PAGE_SIZE, REGION_SMEM);
+		igt_debug("Batch obj 0x%x created in region 0x%x:0x%x\n", batch[i],
+			  MEMORY_TYPE_FROM_REGION(REGION_SMEM), MEMORY_INSTANCE_FROM_REGION(REGION_SMEM));
+		batch_addr[i] = gem_mmap__cpu(fd, batch[i], 0, PAGE_SIZE, PROT_WRITE);
+	}
+
+	/* Create mappings */
+	for (i = 0; i < num_ctxts; i++) {
+		uint64_t va_offset = i * va_delta;
+		uint64_t offset = i * delta;
+		uint32_t j;
+
+		for (j = 0; j < num_cmds; j++)
+			SET_MAP(map[i][SRC_MAP + j], src[j], src_va + va_offset, offset, delta, 0);
+		SET_MAP(map[i][DST_MAP], dst, dst_va + va_offset, offset, delta, 0);
+		SET_MAP(map[i][BATCH_MAP], batch[i], to_user_pointer(batch_addr[i]), 0, PAGE_SIZE, 0);
+	}
+
+	/* Bind the buffers to device page table */
+	for (i = 0; i < num_ctxts; i++) {
+		vm_bind(fd, vm_id[i], &map[i][BATCH_MAP],
+			do_sync_bind(cfg) ? NULL : &exec_fence[i][BATCH_FENCE]);
+		vm_bind(fd, vm_id[i], &map[i][DST_MAP],
+			do_sync_bind(cfg) ? NULL : &exec_fence[i][DST_FENCE]);
+	}
+
+	/* Have GPU do the copy */
+	for (i = 0; i < cfg->num_cmds; i++) {
+		uint32_t j;
+
+		for (j = 0; j < num_ctxts; j++)
+			vm_bind(fd, vm_id[j], &map[j][SRC_MAP + i],
+				do_sync_bind(cfg) ? NULL : &exec_fence[j][SRC_FENCE]);
+
+		i915_gem_copy(fd, src_va, dst_va, va_delta, delta, size, ctx,
+			      num_ctxts, batch_addr, e->flags, exec_fence,
+			      do_sync_bind(cfg) ? 1 : NUM_FENCES);
+
+		i915_gem_sync(fd, ctx, num_ctxts, exec_fence);
+
+		for (j = 0; j < num_ctxts; j++) {
+			if (!do_sync_bind(cfg))
+				syncobj_destroy(fd, exec_fence[j][SRC_FENCE].handle);
+			if (do_unbind(cfg))
+				vm_unbind(fd, vm_id[j], &map[j][SRC_MAP + i]);
+		}
+	}
+	put_ahnd(ahnd);
+
+	/*
+	 * Unbind buffers from device page table.
+	 * If not, it should get unbound while freeing the buffer.
+	 */
+	for (i = 0; i < num_ctxts; i++) {
+		if (!do_sync_bind(cfg)) {
+			syncobj_destroy(fd, exec_fence[i][BATCH_FENCE].handle);
+			syncobj_destroy(fd, exec_fence[i][DST_FENCE].handle);
+		}
+		if (do_unbind(cfg)) {
+			vm_unbind(fd, vm_id[i], &map[i][BATCH_MAP]);
+			vm_unbind(fd, vm_id[i], &map[i][DST_MAP]);
+		}
+	}
+
+	/* Close batch buffers */
+	for (i = 0; i < num_ctxts; i++) {
+		syncobj_destroy(fd, exec_fence[i][EXEC_FENCE].handle);
+		gem_close(fd, batch[i]);
+	}
+
+	if (num_cmds)
+		debug_dump_buffer(dst_addr, size, "dst_obj", false);
+
+	/* Validate by comparing the last SRC with DST */
+	if (num_cmds)
+		igt_assert(memcmp(src_addr[num_cmds - 1], dst_addr, size) == 0);
+
+	/* Free the objects */
+	destroy_src_objs(fd, mr, src, size, num_cmds, src_addr);
+	destroy_dst_obj(fd, mr, dst, size, dst_addr);
+
+	/* Done with the contexts */
+	for (i = 0; i < num_ctxts; i++) {
+		igt_debug("Destroying context 0x%x\n", ctx[i]->id);
+		gem_vm_destroy(fd, vm_id[i]);
+		intel_ctx_destroy(fd, ctx[i]);
+	}
+
+	if (share_vm)
+		gem_vm_destroy(fd, shared_vm_id);
+}
+
+igt_main
+{
+	struct test_cfg *t, tests[] = {
+		{"basic", DEFAULT_BUFF_SIZE, 1, 1, 0},
+		{"multi_cmds", DEFAULT_BUFF_SIZE, MAX_CMDS, 1, 0},
+		{"skip_copy", DEFAULT_BUFF_SIZE, 0, 1, 0},
+		{"skip_unbind", DEFAULT_BUFF_SIZE, 1, 1, TEST_SKIP_UNBIND},
+		{"multi_ctxts", DEFAULT_BUFF_SIZE, 1, MAX_CTXTS, 0},
+		{"share_vm", DEFAULT_BUFF_SIZE, 1, MAX_CTXTS, TEST_SHARE_VM},
+		{"64K", SZ_64K, 1, 1, 0},
+		{"2M", SZ_2M, 1, 1, 0},
+		{"2M_sync_bind", SZ_2M, 1, 1, TEST_SYNC_BIND},
+		{ }
+	};
+	int fd;
+	struct intel_execution_engine2 *e;
+	const intel_ctx_t *ctx;
+	uint32_t alignment = 0;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(fd);
+		igt_require(gem_has_blt(fd));
+		igt_require(i915_vm_bind_version(fd) == 1);
+		ctx = intel_ctx_create_all_physical(fd);
+		/* Get copy engine */
+		for_each_ctx_engine(fd, ctx, e)
+			if (e->class == I915_ENGINE_CLASS_COPY)
+				break;
+	}
+
+	for_each_memory_region(r, fd)
+		alignment = max_t(uint32_t, alignment, r->gtt_alignment);
+
+	for (t = tests; t->name; t++) {
+		igt_describe_f("VM_BIND %s", t->name);
+		igt_subtest_with_dynamic(t->name) {
+			for_each_memory_region(r, fd) {
+				struct test_cfg cfg = *t;
+
+				if (r->ci.memory_instance)
+					continue;
+
+				cfg.size = ALIGN(cfg.size, alignment);
+				cfg.size *= cfg.num_ctxts;
+				igt_dynamic_f("%s", r->name)
+					run_test(fd, ctx, &cfg, r, alignment, e);
+			}
+		}
+	}
+
+	igt_fixture {
+		intel_ctx_destroy(fd, ctx);
+		close(fd);
+	}
+
+	igt_exit();
+}
diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index 185c2fef54..8a47eaddda 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -53,6 +53,7 @@ igt@i915_getparams_basic@basic-eu-total
 igt@i915_getparams_basic@basic-subslice-total
 igt@i915_hangman@error-state-basic
 igt@i915_pciid
+igt@i915_vm_bind_basic@basic-smem
 igt@i915_vm_bind_sanity@basic
 igt@kms_addfb_basic@addfb25-bad-modifier
 igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling
diff --git a/tests/meson.build b/tests/meson.build
index 423db3057b..63404e491b 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -225,6 +225,7 @@ i915_progs = [
 	'i915_query',
 	'i915_selftest',
 	'i915_suspend',
+	'i915_vm_bind_basic',
 	'i915_vm_bind_sanity',
 	'kms_big_fb',
 	'kms_big_joiner' ,
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 09/12] tests/i915/vm_bind: Add userptr subtest

[Niranjana Vishwanathapura]

Add userptr object type to vm_bind_basic test.

v2: Run all tests for userptr type
v3: Change info to debug messages, remove igt_collection usage

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/i915/i915_vm_bind_basic.c | 55 +++++++++++++++++++++++++++++----
 1 file changed, 49 insertions(+), 6 deletions(-)

diff --git a/tests/i915/i915_vm_bind_basic.c b/tests/i915/i915_vm_bind_basic.c
index e794f0a845..f9cbb198e6 100644
--- a/tests/i915/i915_vm_bind_basic.c
+++ b/tests/i915/i915_vm_bind_basic.c
@@ -235,16 +235,24 @@ static uint32_t create_obj(int fd, struct gem_memory_region *mr, uint32_t size,
 {
 	uint32_t handle;
 
-	handle = gem_create_in_memory_region_list(fd, size, 0, &mr->ci, 1);
-	*addr = gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
+	if (!mr) {
+		igt_assert(posix_memalign(addr, SZ_2M * MAX_CTXTS, size) == 0);
+		gem_userptr(fd, *addr, size, 0, 0, &handle);
+	} else {
+		handle = gem_create_in_memory_region_list(fd, size, 0, &mr->ci, 1);
+		*addr = gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
+	}
 
 	return handle;
 }
 
-static void destroy_obj(int fd, uint32_t handle, uint32_t size, void *addr)
+static void destroy_obj(int fd, uint32_t handle, uint32_t size, void *addr, bool is_userptr)
 {
 	igt_assert(gem_munmap(addr, size) == 0);
 	gem_close(fd, handle);
+
+	if (is_userptr)
+		free(addr);
 }
 
 static void create_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[],
@@ -255,6 +263,14 @@ static void create_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[]
 	if (!num_cmds)
 		return;
 
+	if (!mr) {
+		for (i = 0; i < num_cmds; i++) {
+			src[i] = create_obj(fd, NULL, size, &src_addr[i]);
+			igt_debug("Src (userptr) obj 0x%x created\n", src[i]);
+		}
+		return;
+	}
+
 	/* Create first src object always in memory region 'mr' */
 	src[i] = create_obj(fd, mr, size, &src_addr[i]);
 	igt_debug("Src (%s) obj 0x%x created\n", mr->name, src[i]);
@@ -293,7 +309,7 @@ static void destroy_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[
 
 	for (i = 0; i < num_cmds; i++) {
 		igt_debug("Closing src object 0x%x\n", src[i]);
-		destroy_obj(fd, src[i], size, src_addr[i]);
+		destroy_obj(fd, src[i], size, src_addr[i], !mr);
 	}
 }
 
@@ -301,7 +317,7 @@ static uint32_t create_dst_obj(int fd, struct gem_memory_region *mr, uint32_t si
 {
 	uint32_t dst = create_obj(fd, mr, size, dst_addr);
 
-	igt_debug("Dst (%s) obj 0x%x created\n", mr->name, dst);
+	igt_debug("Dst (%s) obj 0x%x created\n", mr ? mr->name : "userptr", dst);
 	return dst;
 }
 
@@ -309,7 +325,7 @@ static void destroy_dst_obj(int fd, struct gem_memory_region *mr, uint32_t dst,
 			    uint32_t size, void *dst_addr)
 {
 	igt_debug("Closing dst object 0x%x\n", dst);
-	destroy_obj(fd, dst, size, dst_addr);
+	destroy_obj(fd, dst, size, dst_addr, !mr);
 }
 
 static void pattern_fill_buf(void *src_addr[], uint32_t size, uint32_t num_cmds, uint32_t npages)
@@ -499,6 +515,25 @@ static void run_test(int fd, const intel_ctx_t *base_ctx, struct test_cfg *cfg,
 		gem_vm_destroy(fd, shared_vm_id);
 }
 
+static int has_userptr(int fd)
+{
+	uint32_t handle = 0;
+	void *ptr;
+	int ret;
+
+	assert(posix_memalign(&ptr, PAGE_SIZE, PAGE_SIZE) == 0);
+	ret = __gem_userptr(fd, ptr, PAGE_SIZE, 0, 0, &handle);
+	if (ret != 0) {
+		free(ptr);
+		return 0;
+	}
+
+	gem_close(fd, handle);
+	free(ptr);
+
+	return handle != 0;
+}
+
 igt_main
 {
 	struct test_cfg *t, tests[] = {
@@ -547,6 +582,14 @@ igt_main
 				igt_dynamic_f("%s", r->name)
 					run_test(fd, ctx, &cfg, r, alignment, e);
 			}
+
+			if (has_userptr(fd)) {
+				struct test_cfg cfg = *t;
+
+				/* Use NULL memory region for userptr */
+				igt_dynamic("userptr")
+					run_test(fd, ctx, &cfg, NULL, PAGE_SIZE, e);
+			}
 		}
 	}
 
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 10/12] tests/i915/vm_bind: Add gem_exec3_basic test

[Niranjana Vishwanathapura]

Port gem_exec_basic to a new gem_exec3_basic test which
uses the newer execbuf3 ioctl.

v2: use i915_vm_bind library functions

Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/i915/gem_exec3_basic.c          | 139 ++++++++++++++++++++++++++
 tests/intel-ci/fast-feedback.testlist |   1 +
 tests/meson.build                     |   1 +
 3 files changed, 141 insertions(+)
 create mode 100644 tests/i915/gem_exec3_basic.c

diff --git a/tests/i915/gem_exec3_basic.c b/tests/i915/gem_exec3_basic.c
new file mode 100644
index 0000000000..cbe712b751
--- /dev/null
+++ b/tests/i915/gem_exec3_basic.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+/** @file gem_exec3_basic.c
+ *
+ * Basic execbuf3 test.
+ * Ported from gem_exec_basic and made to work with
+ * vm_bind and execbuf3.
+ *
+ */
+
+#include "i915/gem.h"
+#include "i915/i915_vm_bind.h"
+#include "igt.h"
+#include "igt_collection.h"
+#include "igt_syncobj.h"
+
+#include "i915/gem_create.h"
+#include "i915/gem_vm.h"
+
+IGT_TEST_DESCRIPTION("Basic sanity check of execbuf3-ioctl rings.");
+
+#define BATCH_VA	0xa0000000
+#define PAGE_SIZE	4096
+
+static uint64_t gettime_ns(void)
+{
+	struct timespec current;
+	clock_gettime(CLOCK_MONOTONIC, &current);
+	return (uint64_t)current.tv_sec * NSEC_PER_SEC + current.tv_nsec;
+}
+
+static uint32_t batch_create(int fd, uint64_t *batch_size, uint32_t region)
+{
+	const uint32_t bbe = MI_BATCH_BUFFER_END;
+	uint32_t handle;
+
+	igt_assert(__gem_create_in_memory_regions(fd, &handle, batch_size, region) == 0);
+	gem_write(fd, handle, 0, &bbe, sizeof(bbe));
+
+	return handle;
+}
+
+igt_main
+{
+	const struct intel_execution_engine2 *e;
+	struct drm_i915_query_memory_regions *query_info;
+	struct igt_collection *regions, *set;
+	const intel_ctx_t *base_ctx, *ctx;
+	struct drm_i915_gem_context_param param = {
+		.param = I915_CONTEXT_PARAM_RECOVERABLE,
+		.value = 0,
+	};
+	uint32_t vm_id;
+	int fd = -1;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_INTEL);
+		base_ctx = intel_ctx_create_all_physical(fd);
+
+		igt_require_gem(fd);
+		igt_require(i915_vm_bind_version(fd) == 1);
+		igt_fork_hang_detector(fd);
+
+		vm_id = gem_vm_create_in_vm_bind_mode(fd);
+		ctx  = intel_ctx_create(fd, &base_ctx->cfg);
+		param.ctx_id = ctx->id;
+		gem_context_set_param(fd, &param);
+		gem_context_set_vm(fd, ctx->id, vm_id);
+
+		query_info = gem_get_query_memory_regions(fd);
+		igt_assert(query_info);
+
+		set = get_memory_region_set(query_info,
+					    I915_SYSTEM_MEMORY,
+					    I915_DEVICE_MEMORY);
+	}
+
+	igt_describe("Check basic functionality of GEM_EXECBUFFER3 ioctl on every"
+		     " ring and iterating over memory regions.");
+	igt_subtest_with_dynamic("basic") {
+		for_each_combination(regions, 1, set) {
+			struct drm_i915_gem_timeline_fence exec_fence[GEM_MAX_ENGINES][2] = { };
+			char *sub_name = memregion_dynamic_subtest_name(regions);
+			uint32_t region = igt_collection_get_value(regions, 0);
+			uint32_t bind_syncobj, exec_syncobj[GEM_MAX_ENGINES];
+			uint64_t fence_value[GEM_MAX_ENGINES] = { };
+			uint64_t batch_size = PAGE_SIZE;
+			uint32_t handle, idx = 0;
+
+			handle = batch_create(fd, &batch_size, region);
+			bind_syncobj = syncobj_create(fd, 0);
+			i915_vm_bind(fd, vm_id, BATCH_VA, handle, 0, batch_size, bind_syncobj, 0);
+
+			for_each_ctx_engine(fd, ctx, e) {
+				igt_dynamic_f("%s-%s", e->name, sub_name) {
+					struct drm_i915_gem_execbuffer3 execbuf = {
+						.ctx_id = ctx->id,
+						.batch_address = BATCH_VA,
+						.engine_idx = e->flags,
+						.fence_count = 2,
+						.timeline_fences = to_user_pointer(&exec_fence[idx]),
+					};
+
+					exec_syncobj[idx] = syncobj_create(fd, 0);
+					exec_fence[idx][0].handle = bind_syncobj;
+					exec_fence[idx][0].flags = I915_TIMELINE_FENCE_WAIT;
+					exec_fence[idx][1].handle = exec_syncobj[idx];
+					exec_fence[idx][1].flags = I915_TIMELINE_FENCE_SIGNAL;
+					idx++;
+
+					gem_execbuf3(fd, &execbuf);
+				}
+			}
+
+			igt_assert(syncobj_timeline_wait(fd, exec_syncobj, fence_value, idx,
+							 gettime_ns() + (2 * NSEC_PER_SEC),
+							 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
+			while (idx)
+				syncobj_destroy(fd, exec_syncobj[--idx]);
+			syncobj_destroy(fd, bind_syncobj);
+			i915_vm_unbind(fd, vm_id, BATCH_VA, batch_size);
+			gem_close(fd, handle);
+			free(sub_name);
+		}
+	}
+
+	igt_fixture {
+		intel_ctx_destroy(fd, ctx);
+		gem_vm_destroy(fd, vm_id);
+		free(query_info);
+		igt_collection_destroy(set);
+		igt_stop_hang_detector();
+		intel_ctx_destroy(fd, base_ctx);
+		close(fd);
+	}
+}
diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
index 8a47eaddda..c5be7e300b 100644
--- a/tests/intel-ci/fast-feedback.testlist
+++ b/tests/intel-ci/fast-feedback.testlist
@@ -27,6 +27,7 @@ igt@gem_exec_fence@nb-await
 igt@gem_exec_gttfill@basic
 igt@gem_exec_parallel@engines
 igt@gem_exec_store@basic
+igt@gem_exec3_basic@basic
 igt@gem_flink_basic@bad-flink
 igt@gem_flink_basic@bad-open
 igt@gem_flink_basic@basic
diff --git a/tests/meson.build b/tests/meson.build
index 63404e491b..915f67857a 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -148,6 +148,7 @@ i915_progs = [
 	'gem_exec_store',
 	'gem_exec_suspend',
 	'gem_exec_whisper',
+	'gem_exec3_basic',
 	'gem_fd_exhaustion',
 	'gem_fence_thrash',
 	'gem_fence_upload',
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 11/12] tests/i915/vm_bind: Add gem_exec3_balancer test

[Niranjana Vishwanathapura]

To test parallel submissions support in execbuf3, port the subtest
gem_exec_balancer@parallel-ordering to a new gem_exec3_balancer test
and switch to execbuf3 ioctl.

v2: use i915_vm_bind library functions
v3: Remove unwanted gem_set_domain()

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/i915/gem_exec3_balancer.c | 466 ++++++++++++++++++++++++++++++++
 tests/meson.build               |   7 +
 2 files changed, 473 insertions(+)
 create mode 100644 tests/i915/gem_exec3_balancer.c

diff --git a/tests/i915/gem_exec3_balancer.c b/tests/i915/gem_exec3_balancer.c
new file mode 100644
index 0000000000..1491907755
--- /dev/null
+++ b/tests/i915/gem_exec3_balancer.c
@@ -0,0 +1,466 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+/** @file gem_exec3_balancer.c
+ *
+ * Load balancer tests with execbuf3.
+ * Ported from gem_exec_balancer and made to work with
+ * vm_bind and execbuf3.
+ *
+ */
+
+#include <poll.h>
+
+#include "i915/gem.h"
+#include "i915/i915_vm_bind.h"
+#include "i915/gem_engine_topology.h"
+#include "i915/gem_create.h"
+#include "i915/gem_vm.h"
+#include "igt.h"
+#include "igt_gt.h"
+#include "igt_perf.h"
+#include "igt_syncobj.h"
+
+IGT_TEST_DESCRIPTION("Exercise in-kernel load-balancing with execbuf3");
+
+#define INSTANCE_COUNT (1 << I915_PMU_SAMPLE_INSTANCE_BITS)
+
+static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
+{
+	int fd;
+
+	fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
+	if (fd >= 0) {
+		close(fd);
+		return true;
+	}
+
+	return false;
+}
+
+static struct i915_engine_class_instance *
+list_engines(int i915, uint32_t class_mask, unsigned int *out)
+{
+	unsigned int count = 0, size = 64;
+	struct i915_engine_class_instance *engines;
+
+	engines = malloc(size * sizeof(*engines));
+	igt_assert(engines);
+
+	for (enum drm_i915_gem_engine_class class = I915_ENGINE_CLASS_RENDER;
+	     class_mask;
+	     class++, class_mask >>= 1) {
+		if (!(class_mask & 1))
+			continue;
+
+		for (unsigned int instance = 0;
+		     instance < INSTANCE_COUNT;
+		     instance++) {
+			if (!has_class_instance(i915, class, instance))
+				continue;
+
+			if (count == size) {
+				size *= 2;
+				engines = realloc(engines,
+						  size * sizeof(*engines));
+				igt_assert(engines);
+			}
+
+			engines[count++] = (struct i915_engine_class_instance){
+				.engine_class = class,
+				.engine_instance = instance,
+			};
+		}
+	}
+
+	if (!count) {
+		free(engines);
+		engines = NULL;
+	}
+
+	*out = count;
+	return engines;
+}
+
+static bool has_perf_engines(int i915)
+{
+	return i915_perf_type_id(i915);
+}
+
+static intel_ctx_cfg_t
+ctx_cfg_for_engines(const struct i915_engine_class_instance *ci,
+		    unsigned int count)
+{
+	intel_ctx_cfg_t cfg = { };
+	unsigned int i;
+
+	for (i = 0; i < count; i++)
+		cfg.engines[i] = ci[i];
+	cfg.num_engines = count;
+
+	return cfg;
+}
+
+static const intel_ctx_t *
+ctx_create_engines(int i915, const struct i915_engine_class_instance *ci,
+		   unsigned int count)
+{
+	intel_ctx_cfg_t cfg = ctx_cfg_for_engines(ci, count);
+	return intel_ctx_create(i915, &cfg);
+}
+
+static void check_bo(int i915, uint32_t handle, unsigned int expected)
+{
+	uint32_t *map;
+
+	map = gem_mmap__cpu(i915, handle, 0, 4096, PROT_READ);
+	igt_assert_eq(map[0], expected);
+	munmap(map, 4096);
+}
+
+static struct drm_i915_query_engine_info *query_engine_info(int i915)
+{
+	struct drm_i915_query_engine_info *engines;
+
+#define QUERY_SIZE	0x4000
+	engines = malloc(QUERY_SIZE);
+	igt_assert(engines);
+	memset(engines, 0, QUERY_SIZE);
+	igt_assert(!__gem_query_engines(i915, engines, QUERY_SIZE));
+#undef QUERY_SIZE
+
+	return engines;
+}
+
+/* This function only works if siblings contains all instances of a class */
+static void logical_sort_siblings(int i915,
+				  struct i915_engine_class_instance *siblings,
+				  unsigned int count)
+{
+	struct i915_engine_class_instance *sorted;
+	struct drm_i915_query_engine_info *engines;
+	unsigned int i, j;
+
+	sorted = calloc(count, sizeof(*sorted));
+	igt_assert(sorted);
+
+	engines = query_engine_info(i915);
+
+	for (j = 0; j < count; ++j) {
+		for (i = 0; i < engines->num_engines; ++i) {
+			if (siblings[j].engine_class ==
+			    engines->engines[i].engine.engine_class &&
+			    siblings[j].engine_instance ==
+			    engines->engines[i].engine.engine_instance) {
+				uint16_t logical_instance =
+					engines->engines[i].logical_instance;
+
+				igt_assert(logical_instance < count);
+				igt_assert(!sorted[logical_instance].engine_class);
+				igt_assert(!sorted[logical_instance].engine_instance);
+
+				sorted[logical_instance] = siblings[j];
+				break;
+			}
+		}
+		igt_assert(i != engines->num_engines);
+	}
+
+	memcpy(siblings, sorted, sizeof(*sorted) * count);
+	free(sorted);
+	free(engines);
+}
+
+static bool fence_busy(int fence)
+{
+	return poll(&(struct pollfd){fence, POLLIN}, 1, 0) == 0;
+}
+
+/*
+ * Always reading from engine instance 0, with GuC submission the values are the
+ * same across all instances. Execlists they may differ but quite unlikely they
+ * would be and if they are we can live with this.
+ */
+static unsigned int get_timeslice(int i915,
+				  struct i915_engine_class_instance engine)
+{
+	unsigned int val;
+
+	switch (engine.engine_class) {
+	case I915_ENGINE_CLASS_RENDER:
+		gem_engine_property_scanf(i915, "rcs0", "timeslice_duration_ms",
+					  "%d", &val);
+		break;
+	case I915_ENGINE_CLASS_COPY:
+		gem_engine_property_scanf(i915, "bcs0", "timeslice_duration_ms",
+					  "%d", &val);
+		break;
+	case I915_ENGINE_CLASS_VIDEO:
+		gem_engine_property_scanf(i915, "vcs0", "timeslice_duration_ms",
+					  "%d", &val);
+		break;
+	case I915_ENGINE_CLASS_VIDEO_ENHANCE:
+		gem_engine_property_scanf(i915, "vecs0", "timeslice_duration_ms",
+					  "%d", &val);
+		break;
+	}
+
+	return val;
+}
+
+static uint64_t gettime_ns(void)
+{
+	struct timespec current;
+	clock_gettime(CLOCK_MONOTONIC, &current);
+	return (uint64_t)current.tv_sec * NSEC_PER_SEC + current.tv_nsec;
+}
+
+static bool syncobj_busy(int i915, uint32_t handle)
+{
+	bool result;
+	int sf;
+
+	sf = syncobj_handle_to_fd(i915, handle,
+				  DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE);
+	result = poll(&(struct pollfd){sf, POLLIN}, 1, 0) == 0;
+	close(sf);
+
+	return result;
+}
+
+/*
+ * Ensure a parallel submit actually runs on HW in parallel by putting on a
+ * spinner on 1 engine, doing a parallel submit, and parallel submit is blocked
+ * behind spinner.
+ */
+static void parallel_ordering(int i915, unsigned int flags)
+{
+	uint32_t vm_id;
+	int class;
+
+	vm_id = gem_vm_create_in_vm_bind_mode(i915);
+
+	for (class = 0; class < 32; class++) {
+		struct drm_i915_gem_timeline_fence exec_fence = { };
+		const intel_ctx_t *ctx = NULL, *spin_ctx = NULL;
+		uint64_t fence_value = 0, batch_addr[32] = { };
+		struct i915_engine_class_instance *siblings;
+		uint32_t batch[16], obj[32], exec_syncobj;
+		struct drm_i915_gem_execbuffer3 execbuf;
+		struct drm_i915_gem_context_param param = {
+			.param = I915_CONTEXT_PARAM_RECOVERABLE,
+			.value = 0,
+		};
+		intel_ctx_cfg_t cfg;
+		unsigned int count;
+		igt_spin_t *spin;
+		uint64_t ahnd;
+		int i = 0;
+
+		siblings = list_engines(i915, 1u << class, &count);
+		if (!siblings)
+			continue;
+
+		if (count < 2) {
+			free(siblings);
+			continue;
+		}
+
+		logical_sort_siblings(i915, siblings, count);
+
+		memset(&cfg, 0, sizeof(cfg));
+		cfg.parallel = true;
+		cfg.num_engines = 1;
+		cfg.width = count;
+		memcpy(cfg.engines, siblings, sizeof(*siblings) * count);
+
+		if (__intel_ctx_create(i915, &cfg, &ctx)) {
+			free(siblings);
+			continue;
+		}
+		param.ctx_id = ctx->id;
+		gem_context_set_param(i915, &param);
+		gem_context_set_vm(i915, ctx->id, vm_id);
+
+		batch[i] = MI_ATOMIC | MI_ATOMIC_INC;
+#define TARGET_BO_OFFSET	(0x1 << 16)
+		batch[++i] = TARGET_BO_OFFSET;
+		batch[++i] = 0;
+		batch[++i] = MI_BATCH_BUFFER_END;
+
+		obj[0] = gem_create(i915, 4096);
+		i915_vm_bind(i915, vm_id, TARGET_BO_OFFSET, obj[0], 0, 4096, 0, 0);
+
+		for (i = 1; i < count + 1; ++i) {
+			obj[i] = gem_create(i915, 4096);
+			gem_write(i915, obj[i], 0, batch, sizeof(batch));
+
+			batch_addr[i - 1] = TARGET_BO_OFFSET * (i + 1);
+			i915_vm_bind(i915, vm_id, batch_addr[i - 1], obj[i], 0, 4096, 0, 0);
+		}
+
+		exec_syncobj = syncobj_create(i915, 0);
+		exec_fence.handle = exec_syncobj;
+		exec_fence.flags = I915_TIMELINE_FENCE_SIGNAL;
+
+		memset(&execbuf, 0, sizeof(execbuf));
+		execbuf.ctx_id = ctx->id,
+		execbuf.batch_address = to_user_pointer(batch_addr),
+		execbuf.fence_count = 1,
+		execbuf.timeline_fences = to_user_pointer(&exec_fence),
+
+		/* Block parallel submission */
+		spin_ctx = ctx_create_engines(i915, siblings, count);
+		ahnd = get_simple_ahnd(i915, spin_ctx->id);
+		spin = __igt_spin_new(i915,
+				      .ahnd = ahnd,
+				      .ctx = spin_ctx,
+				      .engine = 0,
+				      .flags = IGT_SPIN_FENCE_OUT |
+				      IGT_SPIN_NO_PREEMPTION);
+
+		/* Wait for spinners to start */
+		usleep(5 * 10000);
+		igt_assert(fence_busy(spin->out_fence));
+
+		/* Submit parallel execbuf */
+		gem_execbuf3(i915, &execbuf);
+
+		/*
+		 * Wait long enough for timeslcing to kick in but not
+		 * preemption. Spinner + parallel execbuf should be
+		 * active. Assuming default timeslice / preemption values, if
+		 * these are changed it is possible for the test to fail.
+		 */
+		usleep(get_timeslice(i915, siblings[0]) * 2);
+		igt_assert(fence_busy(spin->out_fence));
+		igt_assert(syncobj_busy(i915, exec_syncobj));
+		check_bo(i915, obj[0], 0);
+
+		/*
+		 * End spinner and wait for spinner + parallel execbuf
+		 * to compelte.
+		 */
+		igt_spin_end(spin);
+		igt_assert(syncobj_timeline_wait(i915, &exec_syncobj, &fence_value, 1,
+						 gettime_ns() + (2 * NSEC_PER_SEC),
+						 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
+		igt_assert(!syncobj_busy(i915, exec_syncobj));
+		syncobj_destroy(i915, exec_syncobj);
+		check_bo(i915, obj[0], count);
+
+		/* Clean up */
+		intel_ctx_destroy(i915, ctx);
+		intel_ctx_destroy(i915, spin_ctx);
+		i915_vm_unbind(i915, vm_id, TARGET_BO_OFFSET, 4096);
+		for (i = 1; i < count + 1; ++i)
+			i915_vm_unbind(i915, vm_id, batch_addr[i - 1], 4096);
+
+		for (i = 0; i < count + 1; ++i)
+			gem_close(i915, obj[i]);
+		free(siblings);
+		igt_spin_free(i915, spin);
+		put_ahnd(ahnd);
+	}
+
+	gem_vm_destroy(i915, vm_id);
+}
+
+static bool has_load_balancer(int i915)
+{
+	const intel_ctx_cfg_t cfg = {
+		.load_balance = true,
+		.num_engines = 1,
+	};
+	const intel_ctx_t *ctx = NULL;
+	int err;
+
+	err = __intel_ctx_create(i915, &cfg, &ctx);
+	intel_ctx_destroy(i915, ctx);
+
+	return err == 0;
+}
+
+static bool has_logical_mapping(int i915)
+{
+	struct drm_i915_query_engine_info *engines;
+	unsigned int i;
+
+	engines = query_engine_info(i915);
+
+	for (i = 0; i < engines->num_engines; ++i)
+		if (!(engines->engines[i].flags &
+		     I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE)) {
+			free(engines);
+			return false;
+		}
+
+	free(engines);
+	return true;
+}
+
+static bool has_parallel_execbuf(int i915)
+{
+	intel_ctx_cfg_t cfg = {
+		.parallel = true,
+		.num_engines = 1,
+	};
+	const intel_ctx_t *ctx = NULL;
+	int err;
+
+	for (int class = 0; class < 32; class++) {
+		struct i915_engine_class_instance *siblings;
+		unsigned int count;
+
+		siblings = list_engines(i915, 1u << class, &count);
+		if (!siblings)
+			continue;
+
+		if (count < 2) {
+			free(siblings);
+			continue;
+		}
+
+		logical_sort_siblings(i915, siblings, count);
+
+		cfg.width = count;
+		memcpy(cfg.engines, siblings, sizeof(*siblings) * count);
+		free(siblings);
+
+		err = __intel_ctx_create(i915, &cfg, &ctx);
+		intel_ctx_destroy(i915, ctx);
+
+		return err == 0;
+	}
+
+	return false;
+}
+
+igt_main
+{
+	int i915 = -1;
+
+	igt_fixture {
+		i915 = drm_open_driver(DRIVER_INTEL);
+		igt_require_gem(i915);
+
+		gem_require_contexts(i915);
+		igt_require(i915_vm_bind_version(i915) == 1);
+		igt_require(gem_has_engine_topology(i915));
+		igt_require(has_load_balancer(i915));
+		igt_require(has_perf_engines(i915));
+	}
+
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(has_logical_mapping(i915));
+			igt_require(has_parallel_execbuf(i915));
+		}
+
+		igt_describe("Ensure a parallel submit actually runs in parallel");
+		igt_subtest("parallel-ordering")
+			parallel_ordering(i915, 0);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 915f67857a..7402dbdb86 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -375,6 +375,13 @@ test_executables += executable('gem_exec_balancer', 'i915/gem_exec_balancer.c',
 	   install : true)
 test_list += 'gem_exec_balancer'
 
+test_executables += executable('gem_exec3_balancer', 'i915/gem_exec3_balancer.c',
+	   dependencies : test_deps + [ lib_igt_perf ],
+	   install_dir : libexecdir,
+	   install_rpath : libexecdir_rpathdir,
+	   install : true)
+test_list += 'gem_exec3_balancer'
+
 test_executables += executable('gem_mmap_offset',
 	   join_paths('i915', 'gem_mmap_offset.c'),
 	   dependencies : test_deps + [ libatomic ],
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] [PATCH i-g-t v5 12/12] tests/i915/vm_bind: Add gem_lmem_swapping@vm_bind sub test

[Niranjana Vishwanathapura]

Validate eviction of objects with persistent mappings and
check persistent mappings are properly rebound upon subsequent
execbuf3 call.

TODO: Add a new swapping test with just vm_bind mode
      (without legacy execbuf).

v2: use i915_vm_bind library functions
v3: fix dg2 alignment issue

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
---
 tests/i915/gem_lmem_swapping.c | 134 ++++++++++++++++++++++++++++++++-
 1 file changed, 133 insertions(+), 1 deletion(-)

diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
index cccdb3195b..cb1c86e03c 100644
--- a/tests/i915/gem_lmem_swapping.c
+++ b/tests/i915/gem_lmem_swapping.c
@@ -3,12 +3,16 @@
  * Copyright © 2021 Intel Corporation
  */
 
+#include <poll.h>
+
 #include "i915/gem.h"
 #include "i915/gem_create.h"
 #include "i915/gem_vm.h"
 #include "i915/intel_memory_region.h"
+#include "i915/i915_vm_bind.h"
 #include "igt.h"
 #include "igt_kmod.h"
+#include "igt_syncobj.h"
 #include <unistd.h>
 #include <stdlib.h>
 #include <stdint.h>
@@ -54,6 +58,7 @@ struct params {
 		uint64_t max;
 	} size;
 	unsigned int count;
+	unsigned int vm_bind_count;
 	unsigned int loops;
 	unsigned int mem_limit;
 #define TEST_VERIFY	(1 << 0)
@@ -64,15 +69,18 @@ struct params {
 #define TEST_MULTI	(1 << 5)
 #define TEST_CCS	(1 << 6)
 #define TEST_MASSIVE	(1 << 7)
+#define TEST_VM_BIND	(1 << 8)
 	unsigned int flags;
 	unsigned int seed;
 	bool oom_test;
+	uint64_t va;
 };
 
 struct object {
 	uint64_t size;
 	uint32_t seed;
 	uint32_t handle;
+	uint64_t va;
 	struct blt_copy_object *blt_obj;
 };
 
@@ -278,6 +286,86 @@ verify_object_ccs(int i915, const struct object *obj,
 	free(cmd);
 }
 
+#define BATCH_VA       0xa00000
+
+static uint64_t gettime_ns(void)
+{
+	struct timespec current;
+	clock_gettime(CLOCK_MONOTONIC, &current);
+	return (uint64_t)current.tv_sec * NSEC_PER_SEC + current.tv_nsec;
+}
+
+static void vm_bind(int i915, struct object *list, unsigned int num, uint64_t *va,
+		    uint32_t batch, uint64_t batch_size, uint32_t vm_id)
+{
+	uint32_t *bind_syncobj;
+	uint64_t *fence_value;
+	unsigned int i;
+
+	bind_syncobj = calloc(num + 1, sizeof(*bind_syncobj));
+	igt_assert(bind_syncobj);
+
+	fence_value = calloc(num + 1, sizeof(*fence_value));
+	igt_assert(fence_value);
+
+	for (i = 0; i < num; i++) {
+		list[i].va = *va;
+		bind_syncobj[i] = syncobj_create(i915, 0);
+		i915_vm_bind(i915, vm_id, *va, list[i].handle, 0, list[i].size, bind_syncobj[i], 0);
+		*va += list[i].size;
+	}
+	bind_syncobj[i] = syncobj_create(i915, 0);
+	i915_vm_bind(i915, vm_id, BATCH_VA, batch, 0, batch_size, bind_syncobj[i], 0);
+
+	igt_assert(syncobj_timeline_wait(i915, bind_syncobj, fence_value, num + 1,
+					 gettime_ns() + (2 * NSEC_PER_SEC),
+					 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
+	for (i = 0; i <= num; i++)
+		syncobj_destroy(i915, bind_syncobj[i]);
+}
+
+static void vm_unbind(int i915, struct object *list, unsigned int num,
+		      uint64_t batch_size, uint32_t vm_id)
+{
+	unsigned int i;
+
+	i915_vm_unbind(i915, vm_id, BATCH_VA, batch_size);
+	for (i = 0; i < num; i++)
+		i915_vm_unbind(i915, vm_id, list[i].va, list[i].size);
+}
+
+static void move_to_lmem_execbuf3(int i915,
+				  const intel_ctx_t *ctx,
+				  unsigned int engine,
+				  bool do_oom_test)
+{
+	uint32_t exec_syncobj = syncobj_create(i915, 0);
+	struct drm_i915_gem_timeline_fence exec_fence = {
+		.handle = exec_syncobj,
+		.flags = I915_TIMELINE_FENCE_SIGNAL
+	};
+	struct drm_i915_gem_execbuffer3 eb = {
+		.ctx_id = ctx->id,
+		.batch_address = BATCH_VA,
+		.engine_idx = engine,
+		.fence_count = 1,
+		.timeline_fences = to_user_pointer(&exec_fence),
+	};
+	uint64_t fence_value = 0;
+	int ret;
+
+retry:
+	ret = __gem_execbuf3(i915, &eb);
+	if (do_oom_test && (ret == -ENOMEM || ret == -ENXIO))
+		goto retry;
+	igt_assert_eq(ret, 0);
+
+	igt_assert(syncobj_timeline_wait(i915, &exec_syncobj, &fence_value, 1,
+					 gettime_ns() + (2 * NSEC_PER_SEC),
+					 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
+	syncobj_destroy(i915, exec_syncobj);
+}
+
 static void move_to_lmem(int i915,
 			 const intel_ctx_t *ctx,
 			 struct object *list,
@@ -325,14 +413,16 @@ static void __do_evict(int i915,
 	uint32_t region_id = INTEL_MEMORY_REGION_ID(region->memory_class,
 						    region->memory_instance);
 	const unsigned int max_swap_in = params->count / 100 + 1;
+	uint64_t size, ahnd, batch_size = SZ_64K;
 	struct object *objects, *obj, *list;
 	const uint32_t bpp = 32;
 	uint32_t width, height, stride;
+	const intel_ctx_t *vm_bind_ctx;
 	const intel_ctx_t *blt_ctx;
 	struct blt_copy_object *tmp;
 	unsigned int engine = 0;
+	uint32_t batch, vm_id;
 	unsigned int i, l;
-	uint64_t size, ahnd;
 	struct timespec t = {};
 	unsigned int num;
 
@@ -416,6 +506,26 @@ static void __do_evict(int i915,
 		  readable_size(params->size.max), readable_unit(params->size.max),
 		  params->count, seed);
 
+	/* VM_BIND the specified subset of objects (as persistent mappings) */
+	if (params->flags & TEST_VM_BIND) {
+		const uint32_t bbe = MI_BATCH_BUFFER_END;
+		struct drm_i915_gem_context_param param = {
+			.param = I915_CONTEXT_PARAM_RECOVERABLE,
+			.value = 0,
+		};
+
+		batch = gem_create_from_pool(i915, &batch_size, region_id);
+		gem_write(i915, batch, 0, &bbe, sizeof(bbe));
+
+		vm_id = gem_vm_create_in_vm_bind_mode(i915);
+		vm_bind_ctx = intel_ctx_create(i915, &ctx->cfg);
+		param.ctx_id = vm_bind_ctx->id;
+		gem_context_set_param(i915, &param);
+		gem_context_set_vm(i915, vm_bind_ctx->id, vm_id);
+		vm_bind(i915, objects, params->vm_bind_count, &params->va,
+			batch, batch_size, vm_id);
+	}
+
 	/*
 	 * Move random objects back into lmem.
 	 * For TEST_MULTI runs, make each object counts a loop to
@@ -454,6 +564,15 @@ static void __do_evict(int i915,
 		}
 	}
 
+	/* Rebind persistent mappings to ensure they are swapped back in */
+	if (params->flags & TEST_VM_BIND) {
+		move_to_lmem_execbuf3(i915, vm_bind_ctx, engine, params->oom_test);
+
+		vm_unbind(i915, objects, params->vm_bind_count, batch_size, vm_id);
+		intel_ctx_destroy(i915, vm_bind_ctx);
+		gem_vm_destroy(i915, vm_id);
+	}
+
 	for (i = 0; i < params->count; i++) {
 		gem_close(i915, objects[i].handle);
 		free(objects[i].blt_obj);
@@ -553,6 +672,15 @@ static void fill_params(int i915, struct params *params,
 	if (flags & TEST_HEAVY)
 		params->loops = params->loops / 2 + 1;
 
+	/*
+	 * Set vm_bind_count and ensure it doesn't over-subscribe LMEM.
+	 * Set va range to ensure it is big enough for all bindings in a VM.
+	 */
+	if (flags & TEST_VM_BIND) {
+		params->vm_bind_count = params->count * 50 / ((flags & TEST_HEAVY) ? 300 : 150);
+		params->va = (uint64_t)params->vm_bind_count * size * 4;
+	}
+
 	params->flags = flags;
 	params->oom_test = do_oom_test;
 
@@ -583,6 +711,9 @@ static void test_evict(int i915,
 	if (flags & TEST_CCS)
 		igt_require(IS_DG2(intel_get_drm_devid(i915)));
 
+	if (flags & TEST_VM_BIND)
+		igt_require(i915_vm_bind_version(i915) == 1);
+
 	fill_params(i915, &params, region, flags, nproc, false);
 
 	if (flags & TEST_PARALLEL) {
@@ -764,6 +895,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
 		{ "heavy-verify-random-ccs", TEST_CCS | TEST_RANDOM | TEST_HEAVY },
 		{ "heavy-verify-multi-ccs", TEST_CCS | TEST_RANDOM | TEST_HEAVY | TEST_ENGINES | TEST_MULTI },
 		{ "parallel-random-verify-ccs", TEST_PARALLEL | TEST_RANDOM | TEST_CCS },
+		{ "vm_bind", TEST_VM_BIND },
 		{ }
 	};
 	const intel_ctx_t *ctx;
-- 
2.21.0.rc0.32.g243a4c7e27

[igt-dev] ✗ GitLab.Pipeline: warning for vm_bind: Add VM_BIND validation support (rev9)

[Patchwork]

== Series Details ==

Series: vm_bind: Add VM_BIND validation support (rev9)
URL   : https://patchwork.freedesktop.org/series/105881/
State : warning

== Summary ==

Pipeline status: FAILED.

see https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/720549 for the overview.

test:ninja-test has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/30371993):
  334/338 assembler test/rnde-intsrc              OK       0.02 s 
  335/338 assembler test/rndz                     OK       0.03 s 
  336/338 assembler test/lzd                      OK       0.04 s 
  337/338 assembler test/not                      OK       0.03 s 
  338/338 assembler test/immediate                OK       0.02 s 
  
  Ok:                  333
  Expected Fail:         4
  Fail:                  1
  Unexpected Pass:       0
  Skipped:               0
  Timeout:               0
  
  Full log written to /builds/gfx-ci/igt-ci-tags/build/meson-logs/testlog.txt
  section_end:1666683185:step_script
  section_start:1666683185:cleanup_file_variables
  Cleaning up project directory and file based variables
  section_end:1666683186:cleanup_file_variables
  ERROR: Job failed: exit code 1
  

test:ninja-test-clang has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/30371994):
  334/338 assembler test/rnde-intsrc              OK       0.05 s 
  335/338 assembler test/rndz                     OK       0.05 s 
  336/338 assembler test/lzd                      OK       0.02 s 
  337/338 assembler test/not                      OK       0.04 s 
  338/338 assembler test/immediate                OK       0.04 s 
  
  Ok:                  333
  Expected Fail:         4
  Fail:                  1
  Unexpected Pass:       0
  Skipped:               0
  Timeout:               0
  
  Full log written to /builds/gfx-ci/igt-ci-tags/build/meson-logs/testlog.txt
  section_end:1666683361:step_script
  section_start:1666683361:cleanup_file_variables
  Cleaning up project directory and file based variables
  section_end:1666683361:cleanup_file_variables
  ERROR: Job failed: exit code 1
  

test:ninja-test-mips has failed (https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/jobs/30372592):
  Ok:                  319
  Expected Fail:         4
  Fail:                  1
  Unexpected Pass:       0
  Skipped:               0
  Timeout:               0
  
  Full log written to /builds/gfx-ci/igt-ci-tags/build/meson-logs/testlog.txt
  section_end:1666684040:step_script
  section_start:1666684040:upload_artifacts_on_failure
  Uploading artifacts for failed job
  Uploading artifacts...
  build: found 1816 matching files and directories   
  Uploading artifacts as "archive" to coordinator... 201 Created  id=30372592 responseStatus=201 Created token=_hpHWzYx
  section_end:1666684052:upload_artifacts_on_failure
  section_start:1666684052:cleanup_file_variables
  Cleaning up project directory and file based variables
  section_end:1666684053:cleanup_file_variables
  ERROR: Job failed: exit code 1

== Logs ==

For more details see: https://gitlab.freedesktop.org/gfx-ci/igt-ci-tags/-/pipelines/720549

[igt-dev] ✓ Fi.CI.BAT: success for vm_bind: Add VM_BIND validation support (rev9)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 21093 bytes --]

== Series Details ==

Series: vm_bind: Add VM_BIND validation support (rev9)
URL   : https://patchwork.freedesktop.org/series/105881/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12289 -> IGTPW_7999
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/index.html

Participating hosts (39 -> 39)
------------------------------

  Additional (3): fi-hsw-4770 fi-rkl-11600 bat-adlp-6 
  Missing    (3): fi-ctg-p8600 fi-bdw-samus fi-tgl-dsi 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_7999:

### IGT changes ###

#### Possible regressions ####

  * {igt@gem_exec3_basic@basic} (NEW):
    - {bat-dg2-11}:       NOTRUN -> [SKIP][1] +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-dg2-11/igt@gem_exec3_basic@basic.html

  * {igt@i915_vm_bind_basic@basic-smem} (NEW):
    - {bat-adln-1}:       NOTRUN -> [SKIP][2] +2 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-adln-1/igt@i915_vm_bind_basic@basic-smem.html
    - {bat-adlm-1}:       NOTRUN -> [SKIP][3] +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-adlm-1/igt@i915_vm_bind_basic@basic-smem.html
    - {bat-rplp-1}:       NOTRUN -> [SKIP][4] +2 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-rplp-1/igt@i915_vm_bind_basic@basic-smem.html
    - fi-rkl-11600:       NOTRUN -> [SKIP][5] +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@i915_vm_bind_basic@basic-smem.html
    - fi-adl-ddr5:        NOTRUN -> [SKIP][6] +2 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-adl-ddr5/igt@i915_vm_bind_basic@basic-smem.html
    - {bat-dg2-9}:        NOTRUN -> [SKIP][7] +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-dg2-9/igt@i915_vm_bind_basic@basic-smem.html
    - bat-adlp-4:         NOTRUN -> [SKIP][8] +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-adlp-4/igt@i915_vm_bind_basic@basic-smem.html
    - {bat-dg2-8}:        NOTRUN -> [SKIP][9] +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-dg2-8/igt@i915_vm_bind_basic@basic-smem.html
    - {bat-rpls-1}:       NOTRUN -> [SKIP][10] +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-rpls-1/igt@i915_vm_bind_basic@basic-smem.html
    - {fi-ehl-2}:         NOTRUN -> [SKIP][11] +2 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-ehl-2/igt@i915_vm_bind_basic@basic-smem.html

  * {igt@i915_vm_bind_sanity@basic} (NEW):
    - {bat-rpls-2}:       NOTRUN -> [SKIP][12] +2 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-rpls-2/igt@i915_vm_bind_sanity@basic.html
    - fi-rkl-guc:         NOTRUN -> [SKIP][13] +2 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-guc/igt@i915_vm_bind_sanity@basic.html
    - {bat-adlp-6}:       NOTRUN -> [SKIP][14] +2 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-adlp-6/igt@i915_vm_bind_sanity@basic.html
    - fi-icl-u2:          NOTRUN -> [SKIP][15] +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-icl-u2/igt@i915_vm_bind_sanity@basic.html
    - {bat-jsl-1}:        NOTRUN -> [SKIP][16] +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-jsl-1/igt@i915_vm_bind_sanity@basic.html
    - {fi-jsl-1}:         NOTRUN -> [SKIP][17] +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-jsl-1/igt@i915_vm_bind_sanity@basic.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@migrate:
    - {bat-adlp-6}:       NOTRUN -> [INCOMPLETE][18]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-adlp-6/igt@i915_selftest@live@migrate.html

  
New tests
---------

  New tests have been introduced between CI_DRM_12289 and IGTPW_7999:

### New IGT tests (3) ###

  * igt@gem_exec3_basic@basic:
    - Statuses : 39 skip(s)
    - Exec time: [0.0] s

  * igt@i915_vm_bind_basic@basic-smem:
    - Statuses : 39 skip(s)
    - Exec time: [0.0] s

  * igt@i915_vm_bind_sanity@basic:
    - Statuses : 39 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_7999 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * {igt@gem_exec3_basic@basic} (NEW):
    - fi-pnv-d510:        NOTRUN -> [SKIP][19] ([fdo#109271]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-pnv-d510/igt@gem_exec3_basic@basic.html
    - fi-skl-6700k2:      NOTRUN -> [SKIP][20] ([fdo#109271]) +2 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-skl-6700k2/igt@gem_exec3_basic@basic.html

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [PASS][21] -> [FAIL][22] ([i915#7229])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@gem_huc_copy@huc-copy:
    - fi-rkl-11600:       NOTRUN -> [SKIP][23] ([i915#2190])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-bsw-nick:        NOTRUN -> [SKIP][24] ([fdo#109271]) +41 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-bsw-nick/igt@gem_lmem_swapping@parallel-random-engines.html
    - fi-rkl-11600:       NOTRUN -> [SKIP][25] ([i915#4613]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_tiled_pread_basic:
    - fi-rkl-11600:       NOTRUN -> [SKIP][26] ([i915#3282])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_backlight@basic-brightness:
    - fi-rkl-11600:       NOTRUN -> [SKIP][27] ([i915#3012])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
    - fi-hsw-4770:        NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3012])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-hsw-4770/igt@i915_pm_backlight@basic-brightness.html

  * igt@i915_selftest@live@hugepages:
    - fi-glk-j4005:       [PASS][29] -> [DMESG-FAIL][30] ([i915#7311])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/fi-glk-j4005/igt@i915_selftest@live@hugepages.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-glk-j4005/igt@i915_selftest@live@hugepages.html
    - fi-skl-guc:         [PASS][31] -> [DMESG-FAIL][32] ([i915#7311])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/fi-skl-guc/igt@i915_selftest@live@hugepages.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-skl-guc/igt@i915_selftest@live@hugepages.html
    - fi-rkl-11600:       NOTRUN -> [DMESG-FAIL][33] ([i915#7311])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@i915_selftest@live@hugepages.html

  * {igt@i915_vm_bind_basic@basic-smem} (NEW):
    - fi-kbl-7567u:       NOTRUN -> [SKIP][34] ([fdo#109271]) +2 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-kbl-7567u/igt@i915_vm_bind_basic@basic-smem.html
    - fi-cfl-8700k:       NOTRUN -> [SKIP][35] ([fdo#109271]) +2 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-cfl-8700k/igt@i915_vm_bind_basic@basic-smem.html
    - fi-kbl-8809g:       NOTRUN -> [SKIP][36] ([fdo#109271]) +2 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-kbl-8809g/igt@i915_vm_bind_basic@basic-smem.html
    - fi-elk-e7500:       NOTRUN -> [SKIP][37] ([fdo#109271]) +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-elk-e7500/igt@i915_vm_bind_basic@basic-smem.html
    - fi-hsw-g3258:       NOTRUN -> [SKIP][38] ([fdo#109271]) +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-hsw-g3258/igt@i915_vm_bind_basic@basic-smem.html
    - fi-bsw-kefka:       NOTRUN -> [SKIP][39] ([fdo#109271]) +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-bsw-kefka/igt@i915_vm_bind_basic@basic-smem.html
    - fi-cfl-guc:         NOTRUN -> [SKIP][40] ([fdo#109271]) +2 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-cfl-guc/igt@i915_vm_bind_basic@basic-smem.html
    - fi-kbl-x1275:       NOTRUN -> [SKIP][41] ([fdo#109271]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-kbl-x1275/igt@i915_vm_bind_basic@basic-smem.html
    - fi-bdw-5557u:       NOTRUN -> [SKIP][42] ([fdo#109271]) +2 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-bdw-5557u/igt@i915_vm_bind_basic@basic-smem.html
    - fi-cfl-8109u:       NOTRUN -> [SKIP][43] ([fdo#109271]) +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-cfl-8109u/igt@i915_vm_bind_basic@basic-smem.html
    - fi-ivb-3770:        NOTRUN -> [SKIP][44] ([fdo#109271]) +2 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-ivb-3770/igt@i915_vm_bind_basic@basic-smem.html
    - fi-ilk-650:         NOTRUN -> [SKIP][45] ([fdo#109271]) +2 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-ilk-650/igt@i915_vm_bind_basic@basic-smem.html
    - {bat-jsl-1}:        NOTRUN -> [SKIP][46] ([fdo#112080])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-jsl-1/igt@i915_vm_bind_basic@basic-smem.html
    - {fi-jsl-1}:         NOTRUN -> [SKIP][47] ([fdo#112080])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-jsl-1/igt@i915_vm_bind_basic@basic-smem.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][48] ([fdo#109271]) +2 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-skl-6600u/igt@i915_vm_bind_basic@basic-smem.html

  * {igt@i915_vm_bind_sanity@basic} (NEW):
    - fi-snb-2520m:       NOTRUN -> [SKIP][49] ([fdo#109271]) +2 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-snb-2520m/igt@i915_vm_bind_sanity@basic.html
    - fi-glk-j4005:       NOTRUN -> [SKIP][50] ([fdo#109271]) +2 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-glk-j4005/igt@i915_vm_bind_sanity@basic.html
    - fi-skl-guc:         NOTRUN -> [SKIP][51] ([fdo#109271]) +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-skl-guc/igt@i915_vm_bind_sanity@basic.html
    - fi-blb-e6850:       NOTRUN -> [SKIP][52] ([fdo#109271]) +2 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-blb-e6850/igt@i915_vm_bind_sanity@basic.html
    - fi-apl-guc:         NOTRUN -> [SKIP][53] ([fdo#109271]) +2 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-apl-guc/igt@i915_vm_bind_sanity@basic.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - fi-hsw-4770:        NOTRUN -> [SKIP][54] ([fdo#109271]) +12 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-hsw-4770/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-bsw-kefka:       NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-bsw-kefka/igt@kms_chamelium@common-hpd-after-suspend.html
    - fi-icl-u2:          NOTRUN -> [SKIP][56] ([fdo#111827])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-hsw-4770:        NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-hsw-4770/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-bsw-nick:        NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-bsw-nick/igt@kms_chamelium@hdmi-hpd-fast.html
    - fi-rkl-11600:       NOTRUN -> [SKIP][59] ([fdo#111827]) +7 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
    - fi-rkl-11600:       NOTRUN -> [SKIP][60] ([i915#4103])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-rkl-11600:       NOTRUN -> [SKIP][61] ([fdo#109285] / [i915#4098])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_psr@sprite_plane_onoff:
    - fi-rkl-11600:       NOTRUN -> [SKIP][62] ([i915#1072]) +3 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@kms_psr@sprite_plane_onoff.html
    - fi-hsw-4770:        NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#1072]) +3 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-rkl-11600:       NOTRUN -> [SKIP][64] ([i915#3555] / [i915#4098])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-read:
    - fi-rkl-11600:       NOTRUN -> [SKIP][65] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@basic-userptr:
    - fi-rkl-11600:       NOTRUN -> [SKIP][66] ([fdo#109295] / [i915#3301] / [i915#3708])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-glk-j4005:       NOTRUN -> [FAIL][67] ([i915#4312])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-glk-j4005/igt@runner@aborted.html
    - fi-skl-guc:         NOTRUN -> [FAIL][68] ([i915#4312])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-skl-guc/igt@runner@aborted.html
    - fi-rkl-11600:       NOTRUN -> [FAIL][69] ([i915#4312])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-rkl-11600/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s0@smem:
    - {bat-adlm-1}:       [DMESG-WARN][70] ([i915#2867]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@i915_pm_rpm@basic-rte:
    - {bat-rplp-1}:       [DMESG-WARN][72] ([i915#7077]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-rplp-1/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_pm_rpm@module-reload:
    - {bat-rpls-2}:       [DMESG-WARN][74] ([i915#5537]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/bat-rpls-2/igt@i915_pm_rpm@module-reload.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-rpls-2/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-kefka:       [INCOMPLETE][76] ([i915#2940]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-bsw-kefka/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@hugepages:
    - fi-icl-u2:          [DMESG-FAIL][78] ([i915#7311]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/fi-icl-u2/igt@i915_selftest@live@hugepages.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-icl-u2/igt@i915_selftest@live@hugepages.html

  * igt@i915_selftest@live@reset:
    - {bat-rpls-1}:       [DMESG-FAIL][80] ([i915#4983]) -> [PASS][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/bat-rpls-1/igt@i915_selftest@live@reset.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-rpls-1/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@slpc:
    - {bat-adln-1}:       [DMESG-FAIL][82] ([i915#6997]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/bat-adln-1/igt@i915_selftest@live@slpc.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-adln-1/igt@i915_selftest@live@slpc.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
    - fi-bsw-kefka:       [FAIL][84] ([i915#6298]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html

  * igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-3:
    - {bat-dg2-11}:       [FAIL][86] ([i915#6818]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-3.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc@pipe-d-dp-3.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
  [i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
  [i915#5828]: https://gitlab.freedesktop.org/drm/intel/issues/5828
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6818]: https://gitlab.freedesktop.org/drm/intel/issues/6818
  [i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
  [i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
  [i915#7311]: https://gitlab.freedesktop.org/drm/intel/issues/7311


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7026 -> IGTPW_7999

  CI-20190529: 20190529
  CI_DRM_12289: 0bcfcba620c5d57661249e762a04254ed9274ab3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_7999: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/index.html
  IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git


Testlist changes
----------------

+igt@gem_exec3_balancer@parallel-ordering
+igt@gem_exec3_basic@basic
+igt@gem_lmem_swapping@vm_bind
+igt@i915_vm_bind_sanity@basic

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/index.html

[-- Attachment #2: Type: text/html, Size: 25597 bytes --]

Re: [igt-dev] [PATCH i-g-t v5 08/12] tests/i915/vm_bind: Add basic VM_BIND test support

[Petri Latvala]

On Mon, Oct 24, 2022 at 11:59:37PM -0700, Niranjana Vishwanathapura wrote:
> Add basic tests for VM_BIND functionality. Bind the buffer objects in
> device page table with VM_BIND calls and have GPU copy the data from a
> source buffer object to destination buffer object.
> Test for different buffer sizes, buffer object placement and with
> multiple contexts.
> 
> v2: Add basic test to fast-feedback.testlist
> v3: Run all tests for different memory types,
>     pass VA instead of an array for batch_address
> v4: Iterate for memory region types instead of hardcoding,
>     use i915_vm_bind library functions
> v5: Validate synchronous vm_bind, require blt engine,
>     use mr->gtt_alignment instead of HAS_64K_PAGES,
>     change info to debug messages, remove igt_collection usage,
>     fix dg2 alignment issue
> 
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> ---
>  tests/i915/i915_vm_bind_basic.c       | 559 ++++++++++++++++++++++++++
>  tests/intel-ci/fast-feedback.testlist |   1 +
>  tests/meson.build                     |   1 +
>  3 files changed, 561 insertions(+)
>  create mode 100644 tests/i915/i915_vm_bind_basic.c
> 
> diff --git a/tests/i915/i915_vm_bind_basic.c b/tests/i915/i915_vm_bind_basic.c
> new file mode 100644
> index 0000000000..e794f0a845
> --- /dev/null
> +++ b/tests/i915/i915_vm_bind_basic.c
> @@ -0,0 +1,559 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +/** @file i915_vm_bind_basic.c
> + *
> + * This is the basic test for VM_BIND functionality.
> + *
> + * The goal is to ensure that basics work.
> + */
> +
> +#include <sys/poll.h>
> +
> +#include "i915/gem.h"
> +#include "i915/i915_vm_bind.h"
> +#include "igt.h"
> +#include "igt_syncobj.h"
> +#include <unistd.h>
> +#include <stdlib.h>
> +#include <stdint.h>
> +#include <stdio.h>
> +#include <string.h>
> +#include <fcntl.h>
> +#include <inttypes.h>
> +#include <errno.h>
> +#include <sys/stat.h>
> +#include <sys/ioctl.h>
> +#include "drm.h"
> +#include "i915/gem_vm.h"
> +
> +IGT_TEST_DESCRIPTION("Basic test for vm_bind functionality");
> +
> +#define PAGE_SIZE   4096
> +#define PAGE_SHIFT  12
> +
> +#define GEN9_XY_FAST_COPY_BLT_CMD       (2 << 29 | 0x42 << 22)
> +#define BLT_DEPTH_32                    (3 << 24)
> +
> +#define DEFAULT_BUFF_SIZE  (4 * PAGE_SIZE)
> +#define SZ_64K             (16 * PAGE_SIZE)
> +#define SZ_2M              (512 * PAGE_SIZE)
> +
> +#define MAX_CTXTS   2
> +#define MAX_CMDS    4
> +
> +#define EXEC_FENCE   0
> +#define BATCH_FENCE  1
> +#define SRC_FENCE    2
> +#define DST_FENCE    3
> +#define NUM_FENCES   4
> +
> +enum {
> +	BATCH_MAP,
> +	SRC_MAP,
> +	DST_MAP = SRC_MAP + MAX_CMDS,
> +	MAX_MAP
> +};
> +
> +struct mapping {
> +	uint32_t  obj;
> +	uint64_t  va;
> +	uint64_t  offset;
> +	uint64_t  length;
> +	uint64_t  flags;
> +};
> +
> +#define SET_MAP(map, _obj, _va, _offset, _length, _flags)   \
> +{                                  \
> +	(map).obj = _obj;          \
> +	(map).va = _va;            \
> +	(map).offset = _offset;	   \
> +	(map).length = _length;	   \
> +	(map).flags = _flags;	   \
> +}
> +
> +#define MAX_BATCH_DWORD    64
> +
> +#define abs(x) ((x) >= 0 ? (x) : -(x))
> +
> +#define TEST_SKIP_UNBIND      BIT(0)
> +#define TEST_SHARE_VM         BIT(1)
> +#define TEST_SYNC_BIND        BIT(2)
> +
> +#define do_unbind(cfg)      (!((cfg)->flags & TEST_SKIP_UNBIND))
> +#define do_share_vm(cfg)    ((cfg)->flags & TEST_SHARE_VM)
> +#define do_sync_bind(cfg)   ((cfg)->flags & TEST_SYNC_BIND)
> +
> +struct test_cfg {
> +	const char *name;
> +	uint32_t size;
> +	uint8_t num_cmds;
> +	uint32_t num_ctxts;
> +	uint32_t flags;
> +};
> +
> +static uint64_t
> +gettime_ns(void)
> +{
> +	struct timespec current;
> +	clock_gettime(CLOCK_MONOTONIC, &current);
> +	return (uint64_t)current.tv_sec * NSEC_PER_SEC + current.tv_nsec;
> +}
> +
> +static bool syncobj_busy(int fd, uint32_t handle)
> +{
> +	bool result;
> +	int sf;
> +
> +	sf = syncobj_handle_to_fd(fd, handle,
> +				  DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE);
> +	result = poll(&(struct pollfd){sf, POLLIN}, 1, 0) == 0;
> +	close(sf);
> +
> +	return result;
> +}
> +
> +static inline void vm_bind(int fd, uint32_t vm_id, struct mapping *m,
> +			   struct drm_i915_gem_timeline_fence *fence)
> +{
> +	uint32_t syncobj = 0;
> +
> +	if (fence) {
> +		syncobj = syncobj_create(fd, 0);
> +
> +		fence->handle = syncobj;
> +		fence->flags = I915_TIMELINE_FENCE_WAIT;
> +		fence->value = 0;
> +	}
> +
> +	igt_debug("VM_BIND vm:0x%x h:0x%x v:0x%lx o:0x%lx l:0x%lx\n",
> +		  vm_id, m->obj, m->va, m->offset, m->length);
> +	i915_vm_bind(fd, vm_id, m->va, m->obj, m->offset, m->length, syncobj, 0);
> +}
> +
> +static inline void vm_unbind(int fd, uint32_t vm_id, struct mapping *m)
> +{
> +	/* Object handle is not required during unbind */
> +	igt_debug("VM_UNBIND vm:0x%x v:0x%lx l:0x%lx\n", vm_id, m->va, m->length);
> +	i915_vm_unbind(fd, vm_id, m->va, m->length);
> +}
> +
> +static void debug_dump_buffer(void *buf, uint32_t size,
> +			      const char *str, bool full)
> +{
> +	uint32_t i = 0;
> +
> +	igt_debug("Printing %s size 0x%x\n", str, size);
> +	while (i < size) {
> +		uint32_t *b = buf + i;
> +
> +		igt_debug("\t%s[0x%04x]: 0x%08x 0x%08x 0x%08x 0x%08x %s\n",
> +			  str, i, b[0], b[1], b[2], b[3], full ? "" : "...");
> +		i += full ? 16 : PAGE_SIZE;
> +	}
> +}
> +
> +static int gem_linear_fast_blt(uint32_t *batch, uint64_t src,
> +			       uint64_t dst, uint32_t size)
> +{
> +	uint32_t *cmd = batch;
> +
> +	*cmd++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
> +	*cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
> +	*cmd++ = 0;
> +	*cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
> +	*cmd++ = lower_32_bits(dst);
> +	*cmd++ = upper_32_bits(dst);
> +	*cmd++ = 0;
> +	*cmd++ = PAGE_SIZE;
> +	*cmd++ = lower_32_bits(src);
> +	*cmd++ = upper_32_bits(src);
> +
> +	*cmd++ = MI_BATCH_BUFFER_END;
> +	*cmd++ = 0;
> +
> +	return ALIGN((cmd - batch + 1) * sizeof(uint32_t), 8);
> +}
> +
> +static void __gem_copy(int fd, uint64_t src, uint64_t dst, uint32_t size,
> +		       uint32_t ctx_id, void *batch_addr, unsigned int eb_flags,
> +		       struct drm_i915_gem_timeline_fence *fence,
> +		       uint64_t fence_count)
> +{
> +	uint32_t len, buf[MAX_BATCH_DWORD] = { 0 };
> +	struct drm_i915_gem_execbuffer3 execbuf;
> +
> +	len = gem_linear_fast_blt(buf, src, dst, size);
> +
> +	memcpy(batch_addr, (void *)buf, len);
> +	debug_dump_buffer(buf, len, "batch", true);
> +
> +	memset(&execbuf, 0, sizeof(execbuf));
> +	execbuf.ctx_id = ctx_id;
> +	execbuf.batch_address = to_user_pointer(batch_addr);
> +	execbuf.engine_idx = eb_flags;
> +	execbuf.fence_count = fence_count;
> +	execbuf.timeline_fences = to_user_pointer(fence);
> +	gem_execbuf3(fd, &execbuf);
> +}
> +
> +static void i915_gem_copy(int fd, uint64_t src, uint64_t dst, uint32_t va_delta,
> +			  uint32_t delta, uint32_t size, const intel_ctx_t **ctx,
> +			  uint32_t num_ctxts, void **batch_addr, unsigned int eb_flags,
> +			  struct drm_i915_gem_timeline_fence (*fence)[NUM_FENCES],
> +			  uint64_t fence_count)
> +{
> +	uint32_t i;
> +
> +	for (i = 0; i < num_ctxts; i++) {
> +		igt_debug("Issuing gem copy on ctx 0x%x\n", ctx[i]->id);
> +		__gem_copy(fd, src + (i * va_delta), dst + (i * va_delta), delta,
> +			   ctx[i]->id, batch_addr[i], eb_flags, fence[i],  fence_count);
> +	}
> +}
> +
> +static void i915_gem_sync(int fd, const intel_ctx_t **ctx, uint32_t num_ctxts,
> +			  struct drm_i915_gem_timeline_fence (*fence)[NUM_FENCES])
> +{
> +	uint32_t i;
> +
> +	for (i = 0; i < num_ctxts; i++) {
> +		uint64_t fence_value = 0;
> +
> +		igt_assert(syncobj_timeline_wait(fd, &fence[i][EXEC_FENCE].handle,
> +						 (uint64_t *)&fence_value, 1,
> +						 gettime_ns() + (2 * NSEC_PER_SEC),
> +						 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
> +		igt_assert(!syncobj_busy(fd, fence[i][EXEC_FENCE].handle));
> +		igt_debug("gem copy completed on ctx 0x%x\n", ctx[i]->id);
> +	}
> +}
> +
> +static uint32_t create_obj(int fd, struct gem_memory_region *mr, uint32_t size, void **addr)
> +{
> +	uint32_t handle;
> +
> +	handle = gem_create_in_memory_region_list(fd, size, 0, &mr->ci, 1);
> +	*addr = gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
> +
> +	return handle;
> +}
> +
> +static void destroy_obj(int fd, uint32_t handle, uint32_t size, void *addr)
> +{
> +	igt_assert(gem_munmap(addr, size) == 0);
> +	gem_close(fd, handle);
> +}
> +
> +static void create_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[],
> +			    uint32_t size, uint32_t num_cmds, void *src_addr[])
> +{
> +	int i = 0;
> +
> +	if (!num_cmds)
> +		return;
> +
> +	/* Create first src object always in memory region 'mr' */
> +	src[i] = create_obj(fd, mr, size, &src_addr[i]);
> +	igt_debug("Src (%s) obj 0x%x created\n", mr->name, src[i]);
> +	num_cmds--;
> +	i++;
> +
> +	if (!num_cmds)
> +		return;
> +
> +	/* Create one src object in all other memory regions */
> +	for_each_memory_region(r, fd) {
> +		if (mr &&
> +		    r->ci.memory_class == mr->ci.memory_class &&
> +		    r->ci.memory_instance == mr->ci.memory_instance)
> +			continue;
> +
> +		src[i] = create_obj(fd, r, size, &src_addr[i]);
> +		igt_debug("Src (%s) obj 0x%x created\n", r->name, src[i]);
> +		num_cmds--;
> +		i++;
> +	}
> +
> +	/* Create rest of the src objects in memory region 'mr' */
> +	while (num_cmds) {
> +		src[i] = create_obj(fd, mr, size, &src_addr[i]);
> +		igt_debug("Src (%s) obj 0x%x created\n", mr->name, src[i]);
> +		num_cmds--;
> +		i++;
> +	}
> +}
> +
> +static void destroy_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[],
> +			     uint32_t size, uint32_t num_cmds, void *src_addr[])
> +{
> +	int i;
> +
> +	for (i = 0; i < num_cmds; i++) {
> +		igt_debug("Closing src object 0x%x\n", src[i]);
> +		destroy_obj(fd, src[i], size, src_addr[i]);
> +	}
> +}
> +
> +static uint32_t create_dst_obj(int fd, struct gem_memory_region *mr, uint32_t size, void **dst_addr)
> +{
> +	uint32_t dst = create_obj(fd, mr, size, dst_addr);
> +
> +	igt_debug("Dst (%s) obj 0x%x created\n", mr->name, dst);
> +	return dst;
> +}
> +
> +static void destroy_dst_obj(int fd, struct gem_memory_region *mr, uint32_t dst,
> +			    uint32_t size, void *dst_addr)
> +{
> +	igt_debug("Closing dst object 0x%x\n", dst);
> +	destroy_obj(fd, dst, size, dst_addr);
> +}
> +
> +static void pattern_fill_buf(void *src_addr[], uint32_t size, uint32_t num_cmds, uint32_t npages)
> +{
> +	uint32_t i, j;
> +	void *buf;
> +
> +	/* Allocate buffer and fill pattern */
> +	buf = malloc(size);
> +	igt_require(buf);
> +
> +	for (i = 0; i < num_cmds; i++) {
> +		for (j = 0; j < npages; j++)
> +			memset(buf + j * PAGE_SIZE, i * npages + j + 1, PAGE_SIZE);
> +
> +		memcpy(src_addr[i], buf, size);
> +	}
> +
> +	free(buf);
> +}
> +
> +static void run_test(int fd, const intel_ctx_t *base_ctx, struct test_cfg *cfg,
> +		     struct gem_memory_region *mr, uint32_t alignment,
> +		     const struct intel_execution_engine2 *e)
> +{
> +	struct drm_i915_gem_timeline_fence exec_fence[MAX_CTXTS][NUM_FENCES] = { };
> +	void *src_addr[MAX_CMDS] = { 0 }, *dst_addr = NULL;
> +	uint32_t src[MAX_CMDS], dst, i, size = cfg->size;
> +	uint32_t shared_vm_id, vm_id[MAX_CTXTS];
> +	struct mapping map[MAX_CTXTS][MAX_MAP];
> +	uint32_t num_ctxts = cfg->num_ctxts;
> +	uint32_t num_cmds = cfg->num_cmds;
> +	uint32_t npages = size / PAGE_SIZE;
> +	const intel_ctx_t *ctx[MAX_CTXTS];
> +	uint64_t src_va, dst_va, ahnd = 0;
> +	bool share_vm = do_share_vm(cfg);
> +	uint32_t delta, va_delta = SZ_2M;
> +	void *batch_addr[MAX_CTXTS];
> +	uint32_t batch[MAX_CTXTS];
> +
> +	delta = size / num_ctxts;
> +	if (share_vm)
> +		shared_vm_id = gem_vm_create_in_vm_bind_mode(fd);
> +
> +	/* Create contexts */
> +	num_ctxts = min_t(num_ctxts, MAX_CTXTS, num_ctxts);
> +	for (i = 0; i < num_ctxts; i++) {
> +		struct drm_i915_gem_context_param param = {
> +			.param = I915_CONTEXT_PARAM_RECOVERABLE,
> +			.value = 0,
> +		};
> +		uint32_t vmid;
> +
> +		if (share_vm)
> +			vmid = shared_vm_id;
> +		else
> +			vmid = gem_vm_create_in_vm_bind_mode(fd);
> +
> +		ctx[i] = intel_ctx_create(fd, &base_ctx->cfg);
> +		param.ctx_id = ctx[i]->id;
> +		gem_context_set_param(fd, &param);
> +		gem_context_set_vm(fd, ctx[i]->id, vmid);
> +		vm_id[i] = gem_context_get_vm(fd, ctx[i]->id);
> +
> +		exec_fence[i][EXEC_FENCE].handle = syncobj_create(fd, 0);
> +		exec_fence[i][EXEC_FENCE].flags = I915_TIMELINE_FENCE_SIGNAL;
> +		exec_fence[i][EXEC_FENCE].value = 0;
> +	}
> +
> +	/* Create objects */
> +	num_cmds = min_t(num_cmds, MAX_CMDS, num_cmds);
> +	create_src_objs(fd, mr, src, size, num_cmds, src_addr);
> +	dst = create_dst_obj(fd, mr, size, &dst_addr);
> +
> +	/*
> +	 * mmap'ed addresses are PAGE_SIZE aligned. On platforms requiring
> +	 * other alignment, use static addresses.
> +	 */
> +	if (num_cmds && (alignment == PAGE_SIZE)) {
> +		src_va = to_user_pointer(src_addr[0]);
> +		dst_va = to_user_pointer(dst_addr);
> +	} else {
> +		ahnd = intel_allocator_open_full(fd, 1, 0, 0,
> +						 INTEL_ALLOCATOR_RANDOM,
> +						 ALLOC_STRATEGY_HIGH_TO_LOW,
> +						 alignment);
> +		dst_va = CANONICAL(get_offset(ahnd, dst, size, 0));
> +		if (num_cmds)
> +			src_va = CANONICAL(get_offset(ahnd, src[0], size * num_cmds, 0));
> +	}
> +
> +	pattern_fill_buf(src_addr, size, num_cmds, npages);
> +
> +	if (num_cmds)
> +		debug_dump_buffer(src_addr[num_cmds - 1], size, "src_obj", false);
> +
> +	for (i = 0; i < num_ctxts; i++) {
> +		batch[i] = gem_create_in_memory_regions(fd, PAGE_SIZE, REGION_SMEM);
> +		igt_debug("Batch obj 0x%x created in region 0x%x:0x%x\n", batch[i],
> +			  MEMORY_TYPE_FROM_REGION(REGION_SMEM), MEMORY_INSTANCE_FROM_REGION(REGION_SMEM));
> +		batch_addr[i] = gem_mmap__cpu(fd, batch[i], 0, PAGE_SIZE, PROT_WRITE);
> +	}
> +
> +	/* Create mappings */
> +	for (i = 0; i < num_ctxts; i++) {
> +		uint64_t va_offset = i * va_delta;
> +		uint64_t offset = i * delta;
> +		uint32_t j;
> +
> +		for (j = 0; j < num_cmds; j++)
> +			SET_MAP(map[i][SRC_MAP + j], src[j], src_va + va_offset, offset, delta, 0);
> +		SET_MAP(map[i][DST_MAP], dst, dst_va + va_offset, offset, delta, 0);
> +		SET_MAP(map[i][BATCH_MAP], batch[i], to_user_pointer(batch_addr[i]), 0, PAGE_SIZE, 0);
> +	}
> +
> +	/* Bind the buffers to device page table */
> +	for (i = 0; i < num_ctxts; i++) {
> +		vm_bind(fd, vm_id[i], &map[i][BATCH_MAP],
> +			do_sync_bind(cfg) ? NULL : &exec_fence[i][BATCH_FENCE]);
> +		vm_bind(fd, vm_id[i], &map[i][DST_MAP],
> +			do_sync_bind(cfg) ? NULL : &exec_fence[i][DST_FENCE]);
> +	}
> +
> +	/* Have GPU do the copy */
> +	for (i = 0; i < cfg->num_cmds; i++) {
> +		uint32_t j;
> +
> +		for (j = 0; j < num_ctxts; j++)
> +			vm_bind(fd, vm_id[j], &map[j][SRC_MAP + i],
> +				do_sync_bind(cfg) ? NULL : &exec_fence[j][SRC_FENCE]);
> +
> +		i915_gem_copy(fd, src_va, dst_va, va_delta, delta, size, ctx,
> +			      num_ctxts, batch_addr, e->flags, exec_fence,
> +			      do_sync_bind(cfg) ? 1 : NUM_FENCES);
> +
> +		i915_gem_sync(fd, ctx, num_ctxts, exec_fence);
> +
> +		for (j = 0; j < num_ctxts; j++) {
> +			if (!do_sync_bind(cfg))
> +				syncobj_destroy(fd, exec_fence[j][SRC_FENCE].handle);
> +			if (do_unbind(cfg))
> +				vm_unbind(fd, vm_id[j], &map[j][SRC_MAP + i]);
> +		}
> +	}
> +	put_ahnd(ahnd);
> +
> +	/*
> +	 * Unbind buffers from device page table.
> +	 * If not, it should get unbound while freeing the buffer.
> +	 */
> +	for (i = 0; i < num_ctxts; i++) {
> +		if (!do_sync_bind(cfg)) {
> +			syncobj_destroy(fd, exec_fence[i][BATCH_FENCE].handle);
> +			syncobj_destroy(fd, exec_fence[i][DST_FENCE].handle);
> +		}
> +		if (do_unbind(cfg)) {
> +			vm_unbind(fd, vm_id[i], &map[i][BATCH_MAP]);
> +			vm_unbind(fd, vm_id[i], &map[i][DST_MAP]);
> +		}
> +	}
> +
> +	/* Close batch buffers */
> +	for (i = 0; i < num_ctxts; i++) {
> +		syncobj_destroy(fd, exec_fence[i][EXEC_FENCE].handle);
> +		gem_close(fd, batch[i]);
> +	}
> +
> +	if (num_cmds)
> +		debug_dump_buffer(dst_addr, size, "dst_obj", false);
> +
> +	/* Validate by comparing the last SRC with DST */
> +	if (num_cmds)
> +		igt_assert(memcmp(src_addr[num_cmds - 1], dst_addr, size) == 0);
> +
> +	/* Free the objects */
> +	destroy_src_objs(fd, mr, src, size, num_cmds, src_addr);
> +	destroy_dst_obj(fd, mr, dst, size, dst_addr);
> +
> +	/* Done with the contexts */
> +	for (i = 0; i < num_ctxts; i++) {
> +		igt_debug("Destroying context 0x%x\n", ctx[i]->id);
> +		gem_vm_destroy(fd, vm_id[i]);
> +		intel_ctx_destroy(fd, ctx[i]);
> +	}
> +
> +	if (share_vm)
> +		gem_vm_destroy(fd, shared_vm_id);
> +}
> +
> +igt_main
> +{
> +	struct test_cfg *t, tests[] = {
> +		{"basic", DEFAULT_BUFF_SIZE, 1, 1, 0},
> +		{"multi_cmds", DEFAULT_BUFF_SIZE, MAX_CMDS, 1, 0},
> +		{"skip_copy", DEFAULT_BUFF_SIZE, 0, 1, 0},
> +		{"skip_unbind", DEFAULT_BUFF_SIZE, 1, 1, TEST_SKIP_UNBIND},
> +		{"multi_ctxts", DEFAULT_BUFF_SIZE, 1, MAX_CTXTS, 0},
> +		{"share_vm", DEFAULT_BUFF_SIZE, 1, MAX_CTXTS, TEST_SHARE_VM},
> +		{"64K", SZ_64K, 1, 1, 0},
> +		{"2M", SZ_2M, 1, 1, 0},
> +		{"2M_sync_bind", SZ_2M, 1, 1, TEST_SYNC_BIND},
> +		{ }
> +	};
> +	int fd;
> +	struct intel_execution_engine2 *e;
> +	const intel_ctx_t *ctx;
> +	uint32_t alignment = 0;
> +
> +	igt_fixture {
> +		fd = drm_open_driver(DRIVER_INTEL);
> +		igt_require_gem(fd);
> +		igt_require(gem_has_blt(fd));
> +		igt_require(i915_vm_bind_version(fd) == 1);
> +		ctx = intel_ctx_create_all_physical(fd);
> +		/* Get copy engine */
> +		for_each_ctx_engine(fd, ctx, e)
> +			if (e->class == I915_ENGINE_CLASS_COPY)
> +				break;
> +	}
> +
> +	for_each_memory_region(r, fd)
> +		alignment = max_t(uint32_t, alignment, r->gtt_alignment);

In case you're wondering about the failure from gitlab pipeline:

You can't use for_each_memory_region outside of igt_fixture or
igt_subtest.

To reproduce the error,

ninja -C build test

(assuming your build directory is called 'build')


-- 
Petri Latvala


> +
> +	for (t = tests; t->name; t++) {
> +		igt_describe_f("VM_BIND %s", t->name);
> +		igt_subtest_with_dynamic(t->name) {
> +			for_each_memory_region(r, fd) {
> +				struct test_cfg cfg = *t;
> +
> +				if (r->ci.memory_instance)
> +					continue;
> +
> +				cfg.size = ALIGN(cfg.size, alignment);
> +				cfg.size *= cfg.num_ctxts;
> +				igt_dynamic_f("%s", r->name)
> +					run_test(fd, ctx, &cfg, r, alignment, e);
> +			}
> +		}
> +	}
> +
> +	igt_fixture {
> +		intel_ctx_destroy(fd, ctx);
> +		close(fd);
> +	}
> +
> +	igt_exit();
> +}
> diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
> index 185c2fef54..8a47eaddda 100644
> --- a/tests/intel-ci/fast-feedback.testlist
> +++ b/tests/intel-ci/fast-feedback.testlist
> @@ -53,6 +53,7 @@ igt@i915_getparams_basic@basic-eu-total
>  igt@i915_getparams_basic@basic-subslice-total
>  igt@i915_hangman@error-state-basic
>  igt@i915_pciid
> +igt@i915_vm_bind_basic@basic-smem
>  igt@i915_vm_bind_sanity@basic
>  igt@kms_addfb_basic@addfb25-bad-modifier
>  igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling
> diff --git a/tests/meson.build b/tests/meson.build
> index 423db3057b..63404e491b 100644
> --- a/tests/meson.build
> +++ b/tests/meson.build
> @@ -225,6 +225,7 @@ i915_progs = [
>  	'i915_query',
>  	'i915_selftest',
>  	'i915_suspend',
> +	'i915_vm_bind_basic',
>  	'i915_vm_bind_sanity',
>  	'kms_big_fb',
>  	'kms_big_joiner' ,
> -- 
> 2.21.0.rc0.32.g243a4c7e27
> 

[igt-dev] ✗ Fi.CI.IGT: failure for vm_bind: Add VM_BIND validation support (rev9)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 59903 bytes --]

== Series Details ==

Series: vm_bind: Add VM_BIND validation support (rev9)
URL   : https://patchwork.freedesktop.org/series/105881/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_12289_full -> IGTPW_7999_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_7999_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_7999_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/index.html

Participating hosts (11 -> 8)
------------------------------

  Missing    (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_7999_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@gem_exec3_balancer@parallel-ordering} (NEW):
    - {shard-rkl}:        NOTRUN -> [SKIP][1] +3 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-1/igt@gem_exec3_balancer@parallel-ordering.html

  * {igt@gem_lmem_swapping@vm_bind} (NEW):
    - shard-tglb:         NOTRUN -> [SKIP][2] +2 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb6/igt@gem_lmem_swapping@vm_bind.html

  * {igt@gem_lmem_swapping@vm_bind@lmem0} (NEW):
    - {shard-dg1}:        NOTRUN -> [SKIP][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-dg1-13/igt@gem_lmem_swapping@vm_bind@lmem0.html

  * igt@gem_pread@exhaustion:
    - shard-apl:          NOTRUN -> [INCOMPLETE][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl3/igt@gem_pread@exhaustion.html
    - shard-tglb:         NOTRUN -> [INCOMPLETE][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb2/igt@gem_pread@exhaustion.html
    - shard-glk:          NOTRUN -> [INCOMPLETE][6]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk7/igt@gem_pread@exhaustion.html

  * {igt@i915_vm_bind_sanity@basic} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][7] +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb6/igt@i915_vm_bind_sanity@basic.html

  
New tests
---------

  New tests have been introduced between CI_DRM_12289_full and IGTPW_7999_full:

### New IGT tests (5) ###

  * igt@gem_exec3_balancer@parallel-ordering:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@gem_exec3_basic@basic:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@gem_lmem_swapping@vm_bind:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  * igt@gem_lmem_swapping@vm_bind@lmem0:
    - Statuses : 1 skip(s)
    - Exec time: [0.0] s

  * igt@i915_vm_bind_sanity@basic:
    - Statuses : 6 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_7999_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@crc32:
    - shard-iclb:         NOTRUN -> [SKIP][8] ([i915#6230])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb5/igt@api_intel_bb@crc32.html
    - shard-tglb:         NOTRUN -> [SKIP][9] ([i915#6230])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb5/igt@api_intel_bb@crc32.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-iclb:         NOTRUN -> [SKIP][10] ([i915#6335])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - shard-tglb:         [PASS][11] -> [FAIL][12] ([i915#6268])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-tglb6/igt@gem_ctx_exec@basic-nohangcheck.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb6/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_ctx_persistence@engines-hang:
    - shard-snb:          NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#1099])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-snb4/igt@gem_ctx_persistence@engines-hang.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-tglb:         NOTRUN -> [SKIP][14] ([i915#280])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb5/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_exec_balancer@parallel:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([i915#4525])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb2/igt@gem_exec_balancer@parallel.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb7/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-tglb:         NOTRUN -> [FAIL][17] ([i915#6117])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb5/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-iclb:         NOTRUN -> [SKIP][18] ([i915#6334])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@gem_exec_capture@capture-invisible@smem0.html
    - shard-tglb:         NOTRUN -> [SKIP][19] ([i915#6334])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb1/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-tglb:         NOTRUN -> [SKIP][20] ([i915#6344])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb6/igt@gem_exec_capture@capture-recoverable.html
    - shard-iclb:         NOTRUN -> [SKIP][21] ([i915#6344])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb1/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-glk:          [PASS][22] -> [FAIL][23] ([i915#2842])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_flush@basic-batch-kernel-default-cmd:
    - shard-tglb:         NOTRUN -> [SKIP][24] ([fdo#109313])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-iclb:         NOTRUN -> [SKIP][25] ([i915#4613]) +3 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb8/igt@gem_lmem_swapping@heavy-multi.html
    - shard-apl:          NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#4613]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl6/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#4613]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb7/igt@gem_lmem_swapping@heavy-random.html
    - shard-glk:          NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#4613]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk7/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_media_vme:
    - shard-tglb:         NOTRUN -> [SKIP][29] ([i915#284])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb5/igt@gem_media_vme.html

  * igt@gem_mmap@big-bo:
    - shard-iclb:         NOTRUN -> [DMESG-WARN][30] ([i915#7311])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@gem_mmap@big-bo.html

  * igt@gem_pread@exhaustion:
    - shard-snb:          NOTRUN -> [WARN][31] ([i915#2658])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-snb6/igt@gem_pread@exhaustion.html
    - shard-iclb:         NOTRUN -> [WARN][32] ([i915#2658])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb5/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-tglb:         NOTRUN -> [INCOMPLETE][33] ([i915#7311])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb3/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - shard-snb:          NOTRUN -> [SKIP][34] ([fdo#109271]) +139 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-snb5/igt@gem_pxp@reject-modify-context-protection-off-3.html
    - shard-tglb:         NOTRUN -> [SKIP][35] ([i915#4270]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb1/igt@gem_pxp@reject-modify-context-protection-off-3.html
    - shard-iclb:         NOTRUN -> [SKIP][36] ([i915#4270])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@gem_pxp@reject-modify-context-protection-off-3.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][37] ([i915#768]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb6/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_softpin@evict-single-offset:
    - shard-apl:          NOTRUN -> [FAIL][38] ([i915#4171])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl3/igt@gem_softpin@evict-single-offset.html

  * igt@gem_softpin@evict-snoop:
    - shard-tglb:         NOTRUN -> [SKIP][39] ([fdo#109312])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb6/igt@gem_softpin@evict-snoop.html
    - shard-iclb:         NOTRUN -> [SKIP][40] ([fdo#109312])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb1/igt@gem_softpin@evict-snoop.html

  * igt@gem_userptr_blits@readonly-pwrite-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][41] ([i915#3297]) +2 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb2/igt@gem_userptr_blits@readonly-pwrite-unsync.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-iclb:         NOTRUN -> [SKIP][42] ([i915#3297]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb5/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gen3_render_tiledx_blits:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([fdo#109289]) +5 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@gen3_render_tiledx_blits.html

  * igt@gen7_exec_parse@basic-allowed:
    - shard-tglb:         NOTRUN -> [SKIP][44] ([fdo#109289]) +5 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb3/igt@gen7_exec_parse@basic-allowed.html

  * igt@gen9_exec_parse@basic-rejected:
    - shard-tglb:         NOTRUN -> [SKIP][45] ([i915#2527] / [i915#2856]) +3 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb7/igt@gen9_exec_parse@basic-rejected.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-iclb:         NOTRUN -> [SKIP][46] ([i915#2856]) +2 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb7/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         NOTRUN -> [FAIL][47] ([i915#3989] / [i915#454])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb7/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_query@hwconfig_table:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([i915#6245])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb5/igt@i915_query@hwconfig_table.html
    - shard-iclb:         NOTRUN -> [SKIP][49] ([i915#6245])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb5/igt@i915_query@hwconfig_table.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-tglb:         NOTRUN -> [SKIP][50] ([i915#3826])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb7/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
    - shard-iclb:         NOTRUN -> [SKIP][51] ([i915#3826])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb8/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@alternate-sync-async-flip@pipe-a-vga-1:
    - shard-snb:          [PASS][52] -> [FAIL][53] ([i915#2521])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-snb4/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-vga-1.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-snb7/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-vga-1.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-iclb:         NOTRUN -> [SKIP][54] ([i915#404])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-tglb:         NOTRUN -> [SKIP][55] ([i915#5286]) +6 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb8/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-iclb:         NOTRUN -> [SKIP][56] ([i915#5286]) +3 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][57] ([fdo#111614]) +4 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb1/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
    - shard-iclb:         NOTRUN -> [SKIP][58] ([fdo#110725] / [fdo#111614]) +3 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][59] ([fdo#110723]) +2 similar issues
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb5/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-tglb:         NOTRUN -> [SKIP][60] ([fdo#111615]) +6 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_joiner@invalid-modeset:
    - shard-tglb:         NOTRUN -> [SKIP][61] ([i915#2705])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb5/igt@kms_big_joiner@invalid-modeset.html
    - shard-iclb:         NOTRUN -> [SKIP][62] ([i915#2705])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@kms_big_joiner@invalid-modeset.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#3886]) +8 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl7/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][64] ([i915#3689] / [i915#3886]) +4 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb2/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_dg2_rc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][65] ([i915#3689] / [i915#6095]) +3 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb2/igt@kms_ccs@pipe-a-random-ccs-data-4_tiled_dg2_rc_ccs.html

  * igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][66] ([fdo#111615] / [i915#3689]) +4 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb6/igt@kms_ccs@pipe-b-bad-aux-stride-yf_tiled_ccs.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][67] ([fdo#109278] / [i915#3886]) +6 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#3886]) +6 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk3/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][69] ([fdo#109278]) +30 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb1/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][70] ([i915#6095]) +3 similar issues
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb7/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-4_tiled_dg2_rc_ccs.html

  * igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][71] ([i915#3689]) +8 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb1/igt@kms_ccs@pipe-d-random-ccs-data-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@dp-crc-multiple:
    - shard-tglb:         NOTRUN -> [SKIP][72] ([fdo#109284] / [fdo#111827]) +11 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb8/igt@kms_chamelium@dp-crc-multiple.html

  * igt@kms_chamelium@dp-crc-single:
    - shard-snb:          NOTRUN -> [SKIP][73] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-snb2/igt@kms_chamelium@dp-crc-single.html
    - shard-apl:          NOTRUN -> [SKIP][74] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl2/igt@kms_chamelium@dp-crc-single.html

  * igt@kms_chamelium@dp-edid-read:
    - shard-glk:          NOTRUN -> [SKIP][75] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk6/igt@kms_chamelium@dp-edid-read.html

  * igt@kms_chamelium@hdmi-crc-single:
    - shard-iclb:         NOTRUN -> [SKIP][76] ([fdo#109284] / [fdo#111827]) +8 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb8/igt@kms_chamelium@hdmi-crc-single.html

  * igt@kms_color@ctm-0-75@pipe-a-edp-1:
    - shard-iclb:         NOTRUN -> [FAIL][77] ([i915#315] / [i915#6946]) +2 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb1/igt@kms_color@ctm-0-75@pipe-a-edp-1.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][78] ([i915#7118])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb2/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-1:
    - shard-apl:          NOTRUN -> [INCOMPLETE][79] ([i915#7121] / [i915#7173])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl7/igt@kms_content_protection@atomic-dpms@pipe-a-dp-1.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-tglb:         NOTRUN -> [SKIP][80] ([i915#3116] / [i915#3299])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb2/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@lic:
    - shard-iclb:         NOTRUN -> [SKIP][81] ([i915#7118]) +1 similar issue
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb1/igt@kms_content_protection@lic.html

  * igt@kms_cursor_crc@cursor-offscreen-32x10:
    - shard-iclb:         NOTRUN -> [SKIP][82] ([i915#3555]) +5 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb5/igt@kms_cursor_crc@cursor-offscreen-32x10.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-iclb:         NOTRUN -> [SKIP][83] ([fdo#109279] / [i915#3359])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb6/igt@kms_cursor_crc@cursor-onscreen-512x170.html
    - shard-tglb:         NOTRUN -> [SKIP][84] ([fdo#109279] / [i915#3359])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb8/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-32x10:
    - shard-tglb:         NOTRUN -> [SKIP][85] ([i915#3555]) +4 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb7/igt@kms_cursor_crc@cursor-random-32x10.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-iclb:         NOTRUN -> [SKIP][86] ([i915#3359]) +1 similar issue
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x512:
    - shard-tglb:         NOTRUN -> [SKIP][87] ([i915#3359]) +2 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb5/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb@atomic:
    - shard-tglb:         NOTRUN -> [SKIP][88] ([fdo#109274] / [fdo#111825]) +7 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb1/igt@kms_cursor_legacy@cursorb-vs-flipb@atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
    - shard-glk:          [PASS][89] -> [FAIL][90] ([i915#2346]) +1 similar issue
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-iclb:         NOTRUN -> [SKIP][91] ([i915#3840])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_flip@2x-flip-vs-absolute-wf_vblank:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([fdo#109274] / [fdo#111825] / [i915#3637]) +1 similar issue
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb3/igt@kms_flip@2x-flip-vs-absolute-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][93] -> [FAIL][94] ([i915#79]) +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-flip-vs-panning:
    - shard-iclb:         NOTRUN -> [SKIP][95] ([fdo#109274]) +7 similar issues
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@kms_flip@2x-flip-vs-panning.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][96] ([i915#2672]) +5 similar issues
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode:
    - shard-iclb:         NOTRUN -> [SKIP][97] ([i915#6375])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-tglb:         NOTRUN -> [SKIP][98] ([i915#2587] / [i915#2672]) +5 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-iclb:         NOTRUN -> [SKIP][99] ([i915#2587] / [i915#2672]) +4 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb7/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render:
    - shard-glk:          [PASS][100] -> [FAIL][101] ([i915#2546]) +1 similar issue
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-tglb:         NOTRUN -> [SKIP][102] ([fdo#109280] / [fdo#111825]) +31 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt:
    - shard-iclb:         NOTRUN -> [SKIP][103] ([fdo#109280]) +30 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy:
    - shard-tglb:         NOTRUN -> [SKIP][104] ([i915#6497]) +12 similar issues
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-modesetfrombusy.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-glk:          NOTRUN -> [SKIP][105] ([fdo#109271]) +127 similar issues
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
    - shard-iclb:         NOTRUN -> [FAIL][106] ([i915#2546])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render:
    - shard-apl:          NOTRUN -> [SKIP][107] ([fdo#109271]) +174 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-tglb:         [PASS][108] -> [SKIP][109] ([i915#433])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-tglb1/igt@kms_hdmi_inject@inject-audio.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb8/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_plane_alpha_blend@constant-alpha-max@pipe-b-dp-1:
    - shard-apl:          NOTRUN -> [FAIL][110] ([i915#4573]) +2 similar issues
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl6/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-b-dp-1.html

  * igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][111] ([i915#4573]) +2 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk2/igt@kms_plane_alpha_blend@constant-alpha-max@pipe-c-hdmi-a-1.html

  * igt@kms_plane_lowres@tiling-4:
    - shard-tglb:         NOTRUN -> [SKIP][112] ([fdo#112054] / [i915#5288]) +1 similar issue
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb7/igt@kms_plane_lowres@tiling-4.html

  * igt@kms_plane_lowres@tiling-yf@pipe-b-edp-1:
    - shard-iclb:         NOTRUN -> [SKIP][113] ([i915#3536]) +2 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb7/igt@kms_plane_lowres@tiling-yf@pipe-b-edp-1.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1:
    - shard-iclb:         [PASS][114] -> [SKIP][115] ([i915#5235]) +2 similar issues
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb7/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-iclb:         NOTRUN -> [SKIP][116] ([i915#6524])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb6/igt@kms_prime@basic-crc-hybrid.html
    - shard-tglb:         NOTRUN -> [SKIP][117] ([i915#6524])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb8/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
    - shard-apl:          NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#658]) +1 similar issue
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl2/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
    - shard-tglb:         NOTRUN -> [SKIP][119] ([i915#2920]) +2 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb5/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
    - shard-iclb:         NOTRUN -> [SKIP][120] ([i915#658]) +1 similar issue
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#658]) +1 similar issue
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
    - shard-iclb:         NOTRUN -> [SKIP][122] ([fdo#111068] / [i915#658])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1:
    - shard-iclb:         NOTRUN -> [FAIL][123] ([i915#5939]) +2 similar issues
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@kms_psr2_su@page_flip-p010@pipe-b-edp-1.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][124] -> [SKIP][125] ([fdo#109441]) +1 similar issue
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb1/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         NOTRUN -> [SKIP][126] ([fdo#109441]) +2 similar issues
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb7/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-tglb:         NOTRUN -> [FAIL][127] ([i915#132] / [i915#3467]) +3 similar issues
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb1/igt@kms_psr@psr2_sprite_render.html

  * igt@kms_tv_load_detect@load-detect:
    - shard-tglb:         NOTRUN -> [SKIP][128] ([fdo#109309])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb2/igt@kms_tv_load_detect@load-detect.html
    - shard-iclb:         NOTRUN -> [SKIP][129] ([fdo#109309])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@kms_tv_load_detect@load-detect.html

  * igt@kms_vblank@pipe-b-accuracy-idle:
    - shard-glk:          [PASS][130] -> [FAIL][131] ([i915#43])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-glk1/igt@kms_vblank@pipe-b-accuracy-idle.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk3/igt@kms_vblank@pipe-b-accuracy-idle.html

  * igt@kms_writeback@writeback-check-output:
    - shard-iclb:         NOTRUN -> [SKIP][132] ([i915#2437])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@kms_writeback@writeback-check-output.html
    - shard-apl:          NOTRUN -> [SKIP][133] ([fdo#109271] / [i915#2437])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl2/igt@kms_writeback@writeback-check-output.html
    - shard-tglb:         NOTRUN -> [SKIP][134] ([i915#2437])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb1/igt@kms_writeback@writeback-check-output.html
    - shard-glk:          NOTRUN -> [SKIP][135] ([fdo#109271] / [i915#2437])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk5/igt@kms_writeback@writeback-check-output.html

  * igt@prime_vgem@coherency-gtt:
    - shard-iclb:         NOTRUN -> [SKIP][136] ([fdo#109292] / [fdo#109295])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb5/igt@prime_vgem@coherency-gtt.html
    - shard-tglb:         NOTRUN -> [SKIP][137] ([fdo#109295] / [fdo#111656])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb2/igt@prime_vgem@coherency-gtt.html

  * igt@sysfs_clients@fair-3:
    - shard-apl:          NOTRUN -> [SKIP][138] ([fdo#109271] / [i915#2994]) +2 similar issues
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl6/igt@sysfs_clients@fair-3.html
    - shard-tglb:         NOTRUN -> [SKIP][139] ([i915#2994]) +3 similar issues
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb7/igt@sysfs_clients@fair-3.html

  * igt@sysfs_clients@sema-10:
    - shard-glk:          NOTRUN -> [SKIP][140] ([fdo#109271] / [i915#2994]) +2 similar issues
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk3/igt@sysfs_clients@sema-10.html

  * igt@sysfs_clients@split-25:
    - shard-iclb:         NOTRUN -> [SKIP][141] ([i915#2994]) +2 similar issues
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb6/igt@sysfs_clients@split-25.html

  
#### Possible fixes ####

  * igt@gem_ctx_persistence@legacy-engines-hang@blt:
    - {shard-rkl}:        [SKIP][142] ([i915#6252]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-5/igt@gem_ctx_persistence@legacy-engines-hang@blt.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-6/igt@gem_ctx_persistence@legacy-engines-hang@blt.html

  * igt@gem_eio@in-flight-suspend:
    - {shard-rkl}:        [FAIL][144] ([fdo#103375]) -> [PASS][145] +4 similar issues
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-3/igt@gem_eio@in-flight-suspend.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-5/igt@gem_eio@in-flight-suspend.html

  * igt@gem_eio@unwedge-stress:
    - {shard-dg1}:        [FAIL][146] ([i915#5784]) -> [PASS][147] +1 similar issue
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-dg1-18/igt@gem_eio@unwedge-stress.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-dg1-16/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - {shard-rkl}:        [FAIL][148] ([i915#2846]) -> [PASS][149]
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-6/igt@gem_exec_fair@basic-deadline.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-4/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [FAIL][150] ([i915#2842]) -> [PASS][151]
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-tglb2/igt@gem_exec_fair@basic-flow@rcs0.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - {shard-rkl}:        [FAIL][152] ([i915#2842]) -> [PASS][153]
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-1/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_reloc@basic-gtt-read-noreloc:
    - {shard-rkl}:        [SKIP][154] ([i915#3281]) -> [PASS][155] +14 similar issues
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-read-noreloc.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-read-noreloc.html

  * igt@gem_exec_schedule@semaphore-power:
    - {shard-rkl}:        [SKIP][156] ([i915#7276]) -> [PASS][157]
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-4/igt@gem_exec_schedule@semaphore-power.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-5/igt@gem_exec_schedule@semaphore-power.html

  * igt@gem_mmap_gtt@big-bo-tiledx:
    - shard-tglb:         [DMESG-WARN][158] ([i915#7311]) -> [PASS][159]
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-tglb2/igt@gem_mmap_gtt@big-bo-tiledx.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb3/igt@gem_mmap_gtt@big-bo-tiledx.html

  * igt@gem_pread@snoop:
    - {shard-rkl}:        [SKIP][160] ([i915#3282]) -> [PASS][161] +3 similar issues
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-6/igt@gem_pread@snoop.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-5/igt@gem_pread@snoop.html

  * igt@gem_softpin@evict-single-offset:
    - shard-tglb:         [FAIL][162] ([i915#4171]) -> [PASS][163]
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-tglb5/igt@gem_softpin@evict-single-offset.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb3/igt@gem_softpin@evict-single-offset.html

  * igt@gen9_exec_parse@valid-registers:
    - {shard-rkl}:        [SKIP][164] ([i915#2527]) -> [PASS][165] +1 similar issue
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-3/igt@gen9_exec_parse@valid-registers.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-5/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_pm_dc@dc5-psr:
    - {shard-rkl}:        [SKIP][166] ([i915#658]) -> [PASS][167]
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-4/igt@i915_pm_dc@dc5-psr.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-6/igt@i915_pm_dc@dc5-psr.html

  * igt@i915_pm_rpm@pm-tiling:
    - {shard-rkl}:        [SKIP][168] ([fdo#109308]) -> [PASS][169]
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-4/igt@i915_pm_rpm@pm-tiling.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-6/igt@i915_pm_rpm@pm-tiling.html

  * igt@i915_selftest@live@hugepages:
    - shard-tglb:         [DMESG-FAIL][170] ([i915#7311]) -> [PASS][171]
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-tglb2/igt@i915_selftest@live@hugepages.html
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb5/igt@i915_selftest@live@hugepages.html
    - shard-iclb:         [DMESG-FAIL][172] ([i915#7311]) -> [PASS][173]
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb5/igt@i915_selftest@live@hugepages.html
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@i915_selftest@live@hugepages.html

  * igt@i915_selftest@perf@request:
    - shard-iclb:         [DMESG-WARN][174] ([i915#2867] / [i915#4391]) -> [PASS][175] +1 similar issue
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb7/igt@i915_selftest@perf@request.html
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@i915_selftest@perf@request.html

  * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - {shard-rkl}:        [SKIP][176] ([i915#1845] / [i915#4098]) -> [PASS][177] +16 similar issues
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-1/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-180:
    - shard-glk:          [DMESG-FAIL][178] ([i915#118] / [i915#5138]) -> [PASS][179]
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-glk5/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk1/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html

  * igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1:
    - shard-glk:          [FAIL][180] ([i915#79]) -> [PASS][181]
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@c-edp1:
    - shard-iclb:         [DMESG-WARN][182] ([i915#2867]) -> [PASS][183]
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb7/igt@kms_flip@flip-vs-suspend@c-edp1.html
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb1/igt@kms_flip@flip-vs-suspend@c-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc:
    - {shard-rkl}:        [SKIP][184] ([i915#1849] / [i915#4098]) -> [PASS][185] +7 similar issues
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
    - shard-tglb:         [INCOMPLETE][186] -> [PASS][187]
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
    - shard-iclb:         [FAIL][188] ([i915#2546]) -> [PASS][189] +1 similar issue
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [FAIL][190] -> [PASS][191]
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_psr@cursor_mmap_cpu:
    - {shard-rkl}:        [SKIP][192] ([i915#1072]) -> [PASS][193] +2 similar issues
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-4/igt@kms_psr@cursor_mmap_cpu.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-6/igt@kms_psr@cursor_mmap_cpu.html

  * igt@kms_psr@psr2_sprite_render:
    - shard-iclb:         [SKIP][194] ([fdo#109441]) -> [PASS][195]
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb5/igt@kms_psr@psr2_sprite_render.html
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@kms_psr@psr2_sprite_render.html

  * igt@perf@polling-parameterized:
    - {shard-rkl}:        [FAIL][196] ([i915#5639]) -> [PASS][197]
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-rkl-1/igt@perf@polling-parameterized.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-rkl-5/igt@perf@polling-parameterized.html

  * igt@perf_pmu@rc6-suspend:
    - shard-apl:          [DMESG-WARN][198] ([i915#180]) -> [PASS][199] +1 similar issue
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-apl6/igt@perf_pmu@rc6-suspend.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl6/igt@perf_pmu@rc6-suspend.html

  * igt@syncobj_basic@bad-destroy:
    - shard-iclb:         [DMESG-WARN][200] ([i915#4391]) -> [PASS][201] +1 similar issue
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb7/igt@syncobj_basic@bad-destroy.html
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb5/igt@syncobj_basic@bad-destroy.html

  * igt@sysfs_heartbeat_interval@precise@vecs0:
    - shard-apl:          [FAIL][202] ([i915#1755]) -> [PASS][203]
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-apl8/igt@sysfs_heartbeat_interval@precise@vecs0.html
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl7/igt@sysfs_heartbeat_interval@precise@vecs0.html

  
#### Warnings ####

  * igt@kms_psr2_sf@plane-move-sf-dmg-area:
    - shard-iclb:         [SKIP][204] ([fdo#111068] / [i915#658]) -> [SKIP][205] ([i915#2920])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb5/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
    - shard-iclb:         [SKIP][206] ([i915#2920]) -> [SKIP][207] ([fdo#111068] / [i915#658])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html

  * igt@runner@aborted:
    - shard-apl:          ([FAIL][208], [FAIL][209], [FAIL][210], [FAIL][211], [FAIL][212], [FAIL][213], [FAIL][214], [FAIL][215], [FAIL][216]) ([i915#180] / [i915#3002] / [i915#4312]) -> ([FAIL][217], [FAIL][218], [FAIL][219], [FAIL][220], [FAIL][221], [FAIL][222], [FAIL][223]) ([i915#3002] / [i915#4312])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-apl1/igt@runner@aborted.html
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-apl1/igt@runner@aborted.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-apl7/igt@runner@aborted.html
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-apl7/igt@runner@aborted.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-apl8/igt@runner@aborted.html
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-apl8/igt@runner@aborted.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-apl3/igt@runner@aborted.html
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-apl6/igt@runner@aborted.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12289/shard-apl6/igt@runner@aborted.html
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl2/igt@runner@aborted.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl8/igt@runner@aborted.html
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl3/igt@runner@aborted.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl3/igt@runner@aborted.html
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl1/igt@runner@aborted.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl8/igt@runner@aborted.html
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/shard-apl3/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109292]: https://bugs.freedesktop.org/show_bug.cgi?id=109292
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
  [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
  [i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
  [i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
  [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
  [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3938]: https://gitlab.freedesktop.org/drm/intel/issues/3938
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
  [i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
  [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
  [i915#4573]: https://gitlab.freedesktop.org/drm/intel/issues/4573
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
  [i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
  [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
  [i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
  [i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
  [i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
  [i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
  [i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
  [i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
  [i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
  [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
  [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
  [i915#6375]: https://gitlab.freedesktop.org/drm/intel/issues/6375
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7121]: https://gitlab.freedesktop.org/drm/intel/issues/7121
  [i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
  [i915#7276]: https://gitlab.freedesktop.org/drm/intel/issues/7276
  [i915#7311]: https://gitlab.freedesktop.org/drm/intel/issues/7311
  [i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_7026 -> IGTPW_7999
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_12289: 0bcfcba620c5d57661249e762a04254ed9274ab3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_7999: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/index.html
  IGT_7026: ce0f97e7e0aa54c40049a8365b3d61773c92e588 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7999/index.html

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Re: [igt-dev] [PATCH i-g-t v5 01/12] include/drm-uapi: memory region gtt_alignment support

[Matthew Auld]

On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:
> Pull in gtt_alignment addition in drm_i915_memory_region_info
> uapi and update library to include this field.
> 
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> ---
>   include/drm-uapi/i915_drm.h    | 30 ++++++++++++++++++++++++++++--
>   lib/i915/intel_memory_region.c |  1 +
>   lib/i915/intel_memory_region.h |  1 +
>   3 files changed, 30 insertions(+), 2 deletions(-)
> 
> diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
> index ae9558b3d9..b3a200fc5d 100644
> --- a/include/drm-uapi/i915_drm.h
> +++ b/include/drm-uapi/i915_drm.h
> @@ -3215,8 +3215,34 @@ struct drm_i915_memory_region_info {
>   	/** @region: The class:instance pair encoding */
>   	struct drm_i915_gem_memory_class_instance region;
>   
> -	/** @rsvd0: MBZ */
> -	__u32 rsvd0;
> +	union {
> +		/** @rsvd0: MBZ */
> +		__u32 rsvd0;
> +
> +		/**
> +		 * @gtt_alignment:
> +		 *
> +		 * The minimum required GTT alignment for this type of memory.
> +		 * When allocating a GTT address it must be aligned to this
> +		 * value or larger. On some platforms the kernel might opt to
> +		 * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
> +		 * pages can then be used if we also use 64K GTT alignment.
> +		 *
> +		 * NOTE: If this is zero then this must be an older
> +		 * kernel which lacks support for this field.
> +		 *
> +		 * Side note: For larger objects (especially for
> +		 * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
> +		 * consider potentially bumping the GTT alignment to say 2M,
> +		 * which could potentially increase the likelihood of the kernel
> +		 * being able to utilise 2M GTT pages underneath, if the layout
> +		 * of the physical pages allows it.  On some configurations we
> +		 * can then also use a more efficient page-table layout, if we
> +		 * can't use the more desirable 2M GTT page, so long as we know
> +		 * that the entire page-table will be used by this object.
> +		 */
> +		__u32 gtt_alignment;
> +	};
>   
>   	/**
>   	 * @probed_size: Memory probed by the driver
> diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
> index 84e1bceb38..cbe27d6714 100644
> --- a/lib/i915/intel_memory_region.c
> +++ b/lib/i915/intel_memory_region.c
> @@ -944,6 +944,7 @@ struct gem_memory_region *__gem_get_memory_regions(int i915)
>   
>   		r->ci = info->regions[i].region;
>   		r->size = info->regions[i].probed_size;
> +		r->gtt_alignment = info->regions[i].gtt_alignment;

I made a big mess here since this change needs to be temporarily 
reverted[1]. Sorry about that. For now we could maybe just do something 
like:

gtt_alignment = HAS_64K_PAGES() && ci.memory_type == DEVICE ? 64K : 4K;

I can then fix this up when adding back the gtt_alignment, if your 
series is merged first.

[1] https://patchwork.freedesktop.org/series/110041/

>   		r->cpu_size = info->regions[i].probed_cpu_visible_size;
>   		if (r->size == -1ull)
>   			r->size = igt_get_avail_ram_mb() << 20;
> diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
> index 425bda0ec7..84abb95b1a 100644
> --- a/lib/i915/intel_memory_region.h
> +++ b/lib/i915/intel_memory_region.h
> @@ -174,6 +174,7 @@ struct gem_memory_region {
>   	char *name;
>   
>   	struct drm_i915_gem_memory_class_instance ci;
> +	uint64_t gtt_alignment;
>   	uint64_t size;
>   	uint64_t cpu_size;
>   };

Re: [igt-dev] [PATCH i-g-t v5 08/12] tests/i915/vm_bind: Add basic VM_BIND test support

[Niranjana Vishwanathapura]

On Tue, Oct 25, 2022 at 11:16:25AM +0300, Petri Latvala wrote:
>On Mon, Oct 24, 2022 at 11:59:37PM -0700, Niranjana Vishwanathapura wrote:
>> Add basic tests for VM_BIND functionality. Bind the buffer objects in
>> device page table with VM_BIND calls and have GPU copy the data from a
>> source buffer object to destination buffer object.
>> Test for different buffer sizes, buffer object placement and with
>> multiple contexts.
>>
>> v2: Add basic test to fast-feedback.testlist
>> v3: Run all tests for different memory types,
>>     pass VA instead of an array for batch_address
>> v4: Iterate for memory region types instead of hardcoding,
>>     use i915_vm_bind library functions
>> v5: Validate synchronous vm_bind, require blt engine,
>>     use mr->gtt_alignment instead of HAS_64K_PAGES,
>>     change info to debug messages, remove igt_collection usage,
>>     fix dg2 alignment issue
>>
>> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
>> ---
>>  tests/i915/i915_vm_bind_basic.c       | 559 ++++++++++++++++++++++++++
>>  tests/intel-ci/fast-feedback.testlist |   1 +
>>  tests/meson.build                     |   1 +
>>  3 files changed, 561 insertions(+)
>>  create mode 100644 tests/i915/i915_vm_bind_basic.c
>>
>> diff --git a/tests/i915/i915_vm_bind_basic.c b/tests/i915/i915_vm_bind_basic.c
>> new file mode 100644
>> index 0000000000..e794f0a845
>> --- /dev/null
>> +++ b/tests/i915/i915_vm_bind_basic.c
>> @@ -0,0 +1,559 @@
>> +// SPDX-License-Identifier: MIT
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +/** @file i915_vm_bind_basic.c
>> + *
>> + * This is the basic test for VM_BIND functionality.
>> + *
>> + * The goal is to ensure that basics work.
>> + */
>> +
>> +#include <sys/poll.h>
>> +
>> +#include "i915/gem.h"
>> +#include "i915/i915_vm_bind.h"
>> +#include "igt.h"
>> +#include "igt_syncobj.h"
>> +#include <unistd.h>
>> +#include <stdlib.h>
>> +#include <stdint.h>
>> +#include <stdio.h>
>> +#include <string.h>
>> +#include <fcntl.h>
>> +#include <inttypes.h>
>> +#include <errno.h>
>> +#include <sys/stat.h>
>> +#include <sys/ioctl.h>
>> +#include "drm.h"
>> +#include "i915/gem_vm.h"
>> +
>> +IGT_TEST_DESCRIPTION("Basic test for vm_bind functionality");
>> +
>> +#define PAGE_SIZE   4096
>> +#define PAGE_SHIFT  12
>> +
>> +#define GEN9_XY_FAST_COPY_BLT_CMD       (2 << 29 | 0x42 << 22)
>> +#define BLT_DEPTH_32                    (3 << 24)
>> +
>> +#define DEFAULT_BUFF_SIZE  (4 * PAGE_SIZE)
>> +#define SZ_64K             (16 * PAGE_SIZE)
>> +#define SZ_2M              (512 * PAGE_SIZE)
>> +
>> +#define MAX_CTXTS   2
>> +#define MAX_CMDS    4
>> +
>> +#define EXEC_FENCE   0
>> +#define BATCH_FENCE  1
>> +#define SRC_FENCE    2
>> +#define DST_FENCE    3
>> +#define NUM_FENCES   4
>> +
>> +enum {
>> +	BATCH_MAP,
>> +	SRC_MAP,
>> +	DST_MAP = SRC_MAP + MAX_CMDS,
>> +	MAX_MAP
>> +};
>> +
>> +struct mapping {
>> +	uint32_t  obj;
>> +	uint64_t  va;
>> +	uint64_t  offset;
>> +	uint64_t  length;
>> +	uint64_t  flags;
>> +};
>> +
>> +#define SET_MAP(map, _obj, _va, _offset, _length, _flags)   \
>> +{                                  \
>> +	(map).obj = _obj;          \
>> +	(map).va = _va;            \
>> +	(map).offset = _offset;	   \
>> +	(map).length = _length;	   \
>> +	(map).flags = _flags;	   \
>> +}
>> +
>> +#define MAX_BATCH_DWORD    64
>> +
>> +#define abs(x) ((x) >= 0 ? (x) : -(x))
>> +
>> +#define TEST_SKIP_UNBIND      BIT(0)
>> +#define TEST_SHARE_VM         BIT(1)
>> +#define TEST_SYNC_BIND        BIT(2)
>> +
>> +#define do_unbind(cfg)      (!((cfg)->flags & TEST_SKIP_UNBIND))
>> +#define do_share_vm(cfg)    ((cfg)->flags & TEST_SHARE_VM)
>> +#define do_sync_bind(cfg)   ((cfg)->flags & TEST_SYNC_BIND)
>> +
>> +struct test_cfg {
>> +	const char *name;
>> +	uint32_t size;
>> +	uint8_t num_cmds;
>> +	uint32_t num_ctxts;
>> +	uint32_t flags;
>> +};
>> +
>> +static uint64_t
>> +gettime_ns(void)
>> +{
>> +	struct timespec current;
>> +	clock_gettime(CLOCK_MONOTONIC, &current);
>> +	return (uint64_t)current.tv_sec * NSEC_PER_SEC + current.tv_nsec;
>> +}
>> +
>> +static bool syncobj_busy(int fd, uint32_t handle)
>> +{
>> +	bool result;
>> +	int sf;
>> +
>> +	sf = syncobj_handle_to_fd(fd, handle,
>> +				  DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE);
>> +	result = poll(&(struct pollfd){sf, POLLIN}, 1, 0) == 0;
>> +	close(sf);
>> +
>> +	return result;
>> +}
>> +
>> +static inline void vm_bind(int fd, uint32_t vm_id, struct mapping *m,
>> +			   struct drm_i915_gem_timeline_fence *fence)
>> +{
>> +	uint32_t syncobj = 0;
>> +
>> +	if (fence) {
>> +		syncobj = syncobj_create(fd, 0);
>> +
>> +		fence->handle = syncobj;
>> +		fence->flags = I915_TIMELINE_FENCE_WAIT;
>> +		fence->value = 0;
>> +	}
>> +
>> +	igt_debug("VM_BIND vm:0x%x h:0x%x v:0x%lx o:0x%lx l:0x%lx\n",
>> +		  vm_id, m->obj, m->va, m->offset, m->length);
>> +	i915_vm_bind(fd, vm_id, m->va, m->obj, m->offset, m->length, syncobj, 0);
>> +}
>> +
>> +static inline void vm_unbind(int fd, uint32_t vm_id, struct mapping *m)
>> +{
>> +	/* Object handle is not required during unbind */
>> +	igt_debug("VM_UNBIND vm:0x%x v:0x%lx l:0x%lx\n", vm_id, m->va, m->length);
>> +	i915_vm_unbind(fd, vm_id, m->va, m->length);
>> +}
>> +
>> +static void debug_dump_buffer(void *buf, uint32_t size,
>> +			      const char *str, bool full)
>> +{
>> +	uint32_t i = 0;
>> +
>> +	igt_debug("Printing %s size 0x%x\n", str, size);
>> +	while (i < size) {
>> +		uint32_t *b = buf + i;
>> +
>> +		igt_debug("\t%s[0x%04x]: 0x%08x 0x%08x 0x%08x 0x%08x %s\n",
>> +			  str, i, b[0], b[1], b[2], b[3], full ? "" : "...");
>> +		i += full ? 16 : PAGE_SIZE;
>> +	}
>> +}
>> +
>> +static int gem_linear_fast_blt(uint32_t *batch, uint64_t src,
>> +			       uint64_t dst, uint32_t size)
>> +{
>> +	uint32_t *cmd = batch;
>> +
>> +	*cmd++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2);
>> +	*cmd++ = BLT_DEPTH_32 | PAGE_SIZE;
>> +	*cmd++ = 0;
>> +	*cmd++ = size >> PAGE_SHIFT << 16 | PAGE_SIZE / 4;
>> +	*cmd++ = lower_32_bits(dst);
>> +	*cmd++ = upper_32_bits(dst);
>> +	*cmd++ = 0;
>> +	*cmd++ = PAGE_SIZE;
>> +	*cmd++ = lower_32_bits(src);
>> +	*cmd++ = upper_32_bits(src);
>> +
>> +	*cmd++ = MI_BATCH_BUFFER_END;
>> +	*cmd++ = 0;
>> +
>> +	return ALIGN((cmd - batch + 1) * sizeof(uint32_t), 8);
>> +}
>> +
>> +static void __gem_copy(int fd, uint64_t src, uint64_t dst, uint32_t size,
>> +		       uint32_t ctx_id, void *batch_addr, unsigned int eb_flags,
>> +		       struct drm_i915_gem_timeline_fence *fence,
>> +		       uint64_t fence_count)
>> +{
>> +	uint32_t len, buf[MAX_BATCH_DWORD] = { 0 };
>> +	struct drm_i915_gem_execbuffer3 execbuf;
>> +
>> +	len = gem_linear_fast_blt(buf, src, dst, size);
>> +
>> +	memcpy(batch_addr, (void *)buf, len);
>> +	debug_dump_buffer(buf, len, "batch", true);
>> +
>> +	memset(&execbuf, 0, sizeof(execbuf));
>> +	execbuf.ctx_id = ctx_id;
>> +	execbuf.batch_address = to_user_pointer(batch_addr);
>> +	execbuf.engine_idx = eb_flags;
>> +	execbuf.fence_count = fence_count;
>> +	execbuf.timeline_fences = to_user_pointer(fence);
>> +	gem_execbuf3(fd, &execbuf);
>> +}
>> +
>> +static void i915_gem_copy(int fd, uint64_t src, uint64_t dst, uint32_t va_delta,
>> +			  uint32_t delta, uint32_t size, const intel_ctx_t **ctx,
>> +			  uint32_t num_ctxts, void **batch_addr, unsigned int eb_flags,
>> +			  struct drm_i915_gem_timeline_fence (*fence)[NUM_FENCES],
>> +			  uint64_t fence_count)
>> +{
>> +	uint32_t i;
>> +
>> +	for (i = 0; i < num_ctxts; i++) {
>> +		igt_debug("Issuing gem copy on ctx 0x%x\n", ctx[i]->id);
>> +		__gem_copy(fd, src + (i * va_delta), dst + (i * va_delta), delta,
>> +			   ctx[i]->id, batch_addr[i], eb_flags, fence[i],  fence_count);
>> +	}
>> +}
>> +
>> +static void i915_gem_sync(int fd, const intel_ctx_t **ctx, uint32_t num_ctxts,
>> +			  struct drm_i915_gem_timeline_fence (*fence)[NUM_FENCES])
>> +{
>> +	uint32_t i;
>> +
>> +	for (i = 0; i < num_ctxts; i++) {
>> +		uint64_t fence_value = 0;
>> +
>> +		igt_assert(syncobj_timeline_wait(fd, &fence[i][EXEC_FENCE].handle,
>> +						 (uint64_t *)&fence_value, 1,
>> +						 gettime_ns() + (2 * NSEC_PER_SEC),
>> +						 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
>> +		igt_assert(!syncobj_busy(fd, fence[i][EXEC_FENCE].handle));
>> +		igt_debug("gem copy completed on ctx 0x%x\n", ctx[i]->id);
>> +	}
>> +}
>> +
>> +static uint32_t create_obj(int fd, struct gem_memory_region *mr, uint32_t size, void **addr)
>> +{
>> +	uint32_t handle;
>> +
>> +	handle = gem_create_in_memory_region_list(fd, size, 0, &mr->ci, 1);
>> +	*addr = gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
>> +
>> +	return handle;
>> +}
>> +
>> +static void destroy_obj(int fd, uint32_t handle, uint32_t size, void *addr)
>> +{
>> +	igt_assert(gem_munmap(addr, size) == 0);
>> +	gem_close(fd, handle);
>> +}
>> +
>> +static void create_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[],
>> +			    uint32_t size, uint32_t num_cmds, void *src_addr[])
>> +{
>> +	int i = 0;
>> +
>> +	if (!num_cmds)
>> +		return;
>> +
>> +	/* Create first src object always in memory region 'mr' */
>> +	src[i] = create_obj(fd, mr, size, &src_addr[i]);
>> +	igt_debug("Src (%s) obj 0x%x created\n", mr->name, src[i]);
>> +	num_cmds--;
>> +	i++;
>> +
>> +	if (!num_cmds)
>> +		return;
>> +
>> +	/* Create one src object in all other memory regions */
>> +	for_each_memory_region(r, fd) {
>> +		if (mr &&
>> +		    r->ci.memory_class == mr->ci.memory_class &&
>> +		    r->ci.memory_instance == mr->ci.memory_instance)
>> +			continue;
>> +
>> +		src[i] = create_obj(fd, r, size, &src_addr[i]);
>> +		igt_debug("Src (%s) obj 0x%x created\n", r->name, src[i]);
>> +		num_cmds--;
>> +		i++;
>> +	}
>> +
>> +	/* Create rest of the src objects in memory region 'mr' */
>> +	while (num_cmds) {
>> +		src[i] = create_obj(fd, mr, size, &src_addr[i]);
>> +		igt_debug("Src (%s) obj 0x%x created\n", mr->name, src[i]);
>> +		num_cmds--;
>> +		i++;
>> +	}
>> +}
>> +
>> +static void destroy_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[],
>> +			     uint32_t size, uint32_t num_cmds, void *src_addr[])
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < num_cmds; i++) {
>> +		igt_debug("Closing src object 0x%x\n", src[i]);
>> +		destroy_obj(fd, src[i], size, src_addr[i]);
>> +	}
>> +}
>> +
>> +static uint32_t create_dst_obj(int fd, struct gem_memory_region *mr, uint32_t size, void **dst_addr)
>> +{
>> +	uint32_t dst = create_obj(fd, mr, size, dst_addr);
>> +
>> +	igt_debug("Dst (%s) obj 0x%x created\n", mr->name, dst);
>> +	return dst;
>> +}
>> +
>> +static void destroy_dst_obj(int fd, struct gem_memory_region *mr, uint32_t dst,
>> +			    uint32_t size, void *dst_addr)
>> +{
>> +	igt_debug("Closing dst object 0x%x\n", dst);
>> +	destroy_obj(fd, dst, size, dst_addr);
>> +}
>> +
>> +static void pattern_fill_buf(void *src_addr[], uint32_t size, uint32_t num_cmds, uint32_t npages)
>> +{
>> +	uint32_t i, j;
>> +	void *buf;
>> +
>> +	/* Allocate buffer and fill pattern */
>> +	buf = malloc(size);
>> +	igt_require(buf);
>> +
>> +	for (i = 0; i < num_cmds; i++) {
>> +		for (j = 0; j < npages; j++)
>> +			memset(buf + j * PAGE_SIZE, i * npages + j + 1, PAGE_SIZE);
>> +
>> +		memcpy(src_addr[i], buf, size);
>> +	}
>> +
>> +	free(buf);
>> +}
>> +
>> +static void run_test(int fd, const intel_ctx_t *base_ctx, struct test_cfg *cfg,
>> +		     struct gem_memory_region *mr, uint32_t alignment,
>> +		     const struct intel_execution_engine2 *e)
>> +{
>> +	struct drm_i915_gem_timeline_fence exec_fence[MAX_CTXTS][NUM_FENCES] = { };
>> +	void *src_addr[MAX_CMDS] = { 0 }, *dst_addr = NULL;
>> +	uint32_t src[MAX_CMDS], dst, i, size = cfg->size;
>> +	uint32_t shared_vm_id, vm_id[MAX_CTXTS];
>> +	struct mapping map[MAX_CTXTS][MAX_MAP];
>> +	uint32_t num_ctxts = cfg->num_ctxts;
>> +	uint32_t num_cmds = cfg->num_cmds;
>> +	uint32_t npages = size / PAGE_SIZE;
>> +	const intel_ctx_t *ctx[MAX_CTXTS];
>> +	uint64_t src_va, dst_va, ahnd = 0;
>> +	bool share_vm = do_share_vm(cfg);
>> +	uint32_t delta, va_delta = SZ_2M;
>> +	void *batch_addr[MAX_CTXTS];
>> +	uint32_t batch[MAX_CTXTS];
>> +
>> +	delta = size / num_ctxts;
>> +	if (share_vm)
>> +		shared_vm_id = gem_vm_create_in_vm_bind_mode(fd);
>> +
>> +	/* Create contexts */
>> +	num_ctxts = min_t(num_ctxts, MAX_CTXTS, num_ctxts);
>> +	for (i = 0; i < num_ctxts; i++) {
>> +		struct drm_i915_gem_context_param param = {
>> +			.param = I915_CONTEXT_PARAM_RECOVERABLE,
>> +			.value = 0,
>> +		};
>> +		uint32_t vmid;
>> +
>> +		if (share_vm)
>> +			vmid = shared_vm_id;
>> +		else
>> +			vmid = gem_vm_create_in_vm_bind_mode(fd);
>> +
>> +		ctx[i] = intel_ctx_create(fd, &base_ctx->cfg);
>> +		param.ctx_id = ctx[i]->id;
>> +		gem_context_set_param(fd, &param);
>> +		gem_context_set_vm(fd, ctx[i]->id, vmid);
>> +		vm_id[i] = gem_context_get_vm(fd, ctx[i]->id);
>> +
>> +		exec_fence[i][EXEC_FENCE].handle = syncobj_create(fd, 0);
>> +		exec_fence[i][EXEC_FENCE].flags = I915_TIMELINE_FENCE_SIGNAL;
>> +		exec_fence[i][EXEC_FENCE].value = 0;
>> +	}
>> +
>> +	/* Create objects */
>> +	num_cmds = min_t(num_cmds, MAX_CMDS, num_cmds);
>> +	create_src_objs(fd, mr, src, size, num_cmds, src_addr);
>> +	dst = create_dst_obj(fd, mr, size, &dst_addr);
>> +
>> +	/*
>> +	 * mmap'ed addresses are PAGE_SIZE aligned. On platforms requiring
>> +	 * other alignment, use static addresses.
>> +	 */
>> +	if (num_cmds && (alignment == PAGE_SIZE)) {
>> +		src_va = to_user_pointer(src_addr[0]);
>> +		dst_va = to_user_pointer(dst_addr);
>> +	} else {
>> +		ahnd = intel_allocator_open_full(fd, 1, 0, 0,
>> +						 INTEL_ALLOCATOR_RANDOM,
>> +						 ALLOC_STRATEGY_HIGH_TO_LOW,
>> +						 alignment);
>> +		dst_va = CANONICAL(get_offset(ahnd, dst, size, 0));
>> +		if (num_cmds)
>> +			src_va = CANONICAL(get_offset(ahnd, src[0], size * num_cmds, 0));
>> +	}
>> +
>> +	pattern_fill_buf(src_addr, size, num_cmds, npages);
>> +
>> +	if (num_cmds)
>> +		debug_dump_buffer(src_addr[num_cmds - 1], size, "src_obj", false);
>> +
>> +	for (i = 0; i < num_ctxts; i++) {
>> +		batch[i] = gem_create_in_memory_regions(fd, PAGE_SIZE, REGION_SMEM);
>> +		igt_debug("Batch obj 0x%x created in region 0x%x:0x%x\n", batch[i],
>> +			  MEMORY_TYPE_FROM_REGION(REGION_SMEM), MEMORY_INSTANCE_FROM_REGION(REGION_SMEM));
>> +		batch_addr[i] = gem_mmap__cpu(fd, batch[i], 0, PAGE_SIZE, PROT_WRITE);
>> +	}
>> +
>> +	/* Create mappings */
>> +	for (i = 0; i < num_ctxts; i++) {
>> +		uint64_t va_offset = i * va_delta;
>> +		uint64_t offset = i * delta;
>> +		uint32_t j;
>> +
>> +		for (j = 0; j < num_cmds; j++)
>> +			SET_MAP(map[i][SRC_MAP + j], src[j], src_va + va_offset, offset, delta, 0);
>> +		SET_MAP(map[i][DST_MAP], dst, dst_va + va_offset, offset, delta, 0);
>> +		SET_MAP(map[i][BATCH_MAP], batch[i], to_user_pointer(batch_addr[i]), 0, PAGE_SIZE, 0);
>> +	}
>> +
>> +	/* Bind the buffers to device page table */
>> +	for (i = 0; i < num_ctxts; i++) {
>> +		vm_bind(fd, vm_id[i], &map[i][BATCH_MAP],
>> +			do_sync_bind(cfg) ? NULL : &exec_fence[i][BATCH_FENCE]);
>> +		vm_bind(fd, vm_id[i], &map[i][DST_MAP],
>> +			do_sync_bind(cfg) ? NULL : &exec_fence[i][DST_FENCE]);
>> +	}
>> +
>> +	/* Have GPU do the copy */
>> +	for (i = 0; i < cfg->num_cmds; i++) {
>> +		uint32_t j;
>> +
>> +		for (j = 0; j < num_ctxts; j++)
>> +			vm_bind(fd, vm_id[j], &map[j][SRC_MAP + i],
>> +				do_sync_bind(cfg) ? NULL : &exec_fence[j][SRC_FENCE]);
>> +
>> +		i915_gem_copy(fd, src_va, dst_va, va_delta, delta, size, ctx,
>> +			      num_ctxts, batch_addr, e->flags, exec_fence,
>> +			      do_sync_bind(cfg) ? 1 : NUM_FENCES);
>> +
>> +		i915_gem_sync(fd, ctx, num_ctxts, exec_fence);
>> +
>> +		for (j = 0; j < num_ctxts; j++) {
>> +			if (!do_sync_bind(cfg))
>> +				syncobj_destroy(fd, exec_fence[j][SRC_FENCE].handle);
>> +			if (do_unbind(cfg))
>> +				vm_unbind(fd, vm_id[j], &map[j][SRC_MAP + i]);
>> +		}
>> +	}
>> +	put_ahnd(ahnd);
>> +
>> +	/*
>> +	 * Unbind buffers from device page table.
>> +	 * If not, it should get unbound while freeing the buffer.
>> +	 */
>> +	for (i = 0; i < num_ctxts; i++) {
>> +		if (!do_sync_bind(cfg)) {
>> +			syncobj_destroy(fd, exec_fence[i][BATCH_FENCE].handle);
>> +			syncobj_destroy(fd, exec_fence[i][DST_FENCE].handle);
>> +		}
>> +		if (do_unbind(cfg)) {
>> +			vm_unbind(fd, vm_id[i], &map[i][BATCH_MAP]);
>> +			vm_unbind(fd, vm_id[i], &map[i][DST_MAP]);
>> +		}
>> +	}
>> +
>> +	/* Close batch buffers */
>> +	for (i = 0; i < num_ctxts; i++) {
>> +		syncobj_destroy(fd, exec_fence[i][EXEC_FENCE].handle);
>> +		gem_close(fd, batch[i]);
>> +	}
>> +
>> +	if (num_cmds)
>> +		debug_dump_buffer(dst_addr, size, "dst_obj", false);
>> +
>> +	/* Validate by comparing the last SRC with DST */
>> +	if (num_cmds)
>> +		igt_assert(memcmp(src_addr[num_cmds - 1], dst_addr, size) == 0);
>> +
>> +	/* Free the objects */
>> +	destroy_src_objs(fd, mr, src, size, num_cmds, src_addr);
>> +	destroy_dst_obj(fd, mr, dst, size, dst_addr);
>> +
>> +	/* Done with the contexts */
>> +	for (i = 0; i < num_ctxts; i++) {
>> +		igt_debug("Destroying context 0x%x\n", ctx[i]->id);
>> +		gem_vm_destroy(fd, vm_id[i]);
>> +		intel_ctx_destroy(fd, ctx[i]);
>> +	}
>> +
>> +	if (share_vm)
>> +		gem_vm_destroy(fd, shared_vm_id);
>> +}
>> +
>> +igt_main
>> +{
>> +	struct test_cfg *t, tests[] = {
>> +		{"basic", DEFAULT_BUFF_SIZE, 1, 1, 0},
>> +		{"multi_cmds", DEFAULT_BUFF_SIZE, MAX_CMDS, 1, 0},
>> +		{"skip_copy", DEFAULT_BUFF_SIZE, 0, 1, 0},
>> +		{"skip_unbind", DEFAULT_BUFF_SIZE, 1, 1, TEST_SKIP_UNBIND},
>> +		{"multi_ctxts", DEFAULT_BUFF_SIZE, 1, MAX_CTXTS, 0},
>> +		{"share_vm", DEFAULT_BUFF_SIZE, 1, MAX_CTXTS, TEST_SHARE_VM},
>> +		{"64K", SZ_64K, 1, 1, 0},
>> +		{"2M", SZ_2M, 1, 1, 0},
>> +		{"2M_sync_bind", SZ_2M, 1, 1, TEST_SYNC_BIND},
>> +		{ }
>> +	};
>> +	int fd;
>> +	struct intel_execution_engine2 *e;
>> +	const intel_ctx_t *ctx;
>> +	uint32_t alignment = 0;
>> +
>> +	igt_fixture {
>> +		fd = drm_open_driver(DRIVER_INTEL);
>> +		igt_require_gem(fd);
>> +		igt_require(gem_has_blt(fd));
>> +		igt_require(i915_vm_bind_version(fd) == 1);
>> +		ctx = intel_ctx_create_all_physical(fd);
>> +		/* Get copy engine */
>> +		for_each_ctx_engine(fd, ctx, e)
>> +			if (e->class == I915_ENGINE_CLASS_COPY)
>> +				break;
>> +	}
>> +
>> +	for_each_memory_region(r, fd)
>> +		alignment = max_t(uint32_t, alignment, r->gtt_alignment);
>
>In case you're wondering about the failure from gitlab pipeline:
>
>You can't use for_each_memory_region outside of igt_fixture or
>igt_subtest.
>
>To reproduce the error,
>
>ninja -C build test
>
>(assuming your build directory is called 'build')
>

Ok I did not see that, thanks, will move it under igt_fixture above.

Niranjana

>
>-- 
>Petri Latvala
>
>
>> +
>> +	for (t = tests; t->name; t++) {
>> +		igt_describe_f("VM_BIND %s", t->name);
>> +		igt_subtest_with_dynamic(t->name) {
>> +			for_each_memory_region(r, fd) {
>> +				struct test_cfg cfg = *t;
>> +
>> +				if (r->ci.memory_instance)
>> +					continue;
>> +
>> +				cfg.size = ALIGN(cfg.size, alignment);
>> +				cfg.size *= cfg.num_ctxts;
>> +				igt_dynamic_f("%s", r->name)
>> +					run_test(fd, ctx, &cfg, r, alignment, e);
>> +			}
>> +		}
>> +	}
>> +
>> +	igt_fixture {
>> +		intel_ctx_destroy(fd, ctx);
>> +		close(fd);
>> +	}
>> +
>> +	igt_exit();
>> +}
>> diff --git a/tests/intel-ci/fast-feedback.testlist b/tests/intel-ci/fast-feedback.testlist
>> index 185c2fef54..8a47eaddda 100644
>> --- a/tests/intel-ci/fast-feedback.testlist
>> +++ b/tests/intel-ci/fast-feedback.testlist
>> @@ -53,6 +53,7 @@ igt@i915_getparams_basic@basic-eu-total
>>  igt@i915_getparams_basic@basic-subslice-total
>>  igt@i915_hangman@error-state-basic
>>  igt@i915_pciid
>> +igt@i915_vm_bind_basic@basic-smem
>>  igt@i915_vm_bind_sanity@basic
>>  igt@kms_addfb_basic@addfb25-bad-modifier
>>  igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling
>> diff --git a/tests/meson.build b/tests/meson.build
>> index 423db3057b..63404e491b 100644
>> --- a/tests/meson.build
>> +++ b/tests/meson.build
>> @@ -225,6 +225,7 @@ i915_progs = [
>>  	'i915_query',
>>  	'i915_selftest',
>>  	'i915_suspend',
>> +	'i915_vm_bind_basic',
>>  	'i915_vm_bind_sanity',
>>  	'kms_big_fb',
>>  	'kms_big_joiner' ,
>> --
>> 2.21.0.rc0.32.g243a4c7e27
>>

Re: [igt-dev] [PATCH i-g-t v5 01/12] include/drm-uapi: memory region gtt_alignment support

[Niranjana Vishwanathapura]

On Wed, Oct 26, 2022 at 06:29:43PM +0100, Matthew Auld wrote:
>On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:
>>Pull in gtt_alignment addition in drm_i915_memory_region_info
>>uapi and update library to include this field.
>>
>>Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
>>---
>>  include/drm-uapi/i915_drm.h    | 30 ++++++++++++++++++++++++++++--
>>  lib/i915/intel_memory_region.c |  1 +
>>  lib/i915/intel_memory_region.h |  1 +
>>  3 files changed, 30 insertions(+), 2 deletions(-)
>>
>>diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h
>>index ae9558b3d9..b3a200fc5d 100644
>>--- a/include/drm-uapi/i915_drm.h
>>+++ b/include/drm-uapi/i915_drm.h
>>@@ -3215,8 +3215,34 @@ struct drm_i915_memory_region_info {
>>  	/** @region: The class:instance pair encoding */
>>  	struct drm_i915_gem_memory_class_instance region;
>>-	/** @rsvd0: MBZ */
>>-	__u32 rsvd0;
>>+	union {
>>+		/** @rsvd0: MBZ */
>>+		__u32 rsvd0;
>>+
>>+		/**
>>+		 * @gtt_alignment:
>>+		 *
>>+		 * The minimum required GTT alignment for this type of memory.
>>+		 * When allocating a GTT address it must be aligned to this
>>+		 * value or larger. On some platforms the kernel might opt to
>>+		 * using 64K pages for I915_MEMORY_CLASS_DEVICE, where 64K GTT
>>+		 * pages can then be used if we also use 64K GTT alignment.
>>+		 *
>>+		 * NOTE: If this is zero then this must be an older
>>+		 * kernel which lacks support for this field.
>>+		 *
>>+		 * Side note: For larger objects (especially for
>>+		 * I915_MEMORY_CLASS_DEVICE), like 2M+ in size, userspace should
>>+		 * consider potentially bumping the GTT alignment to say 2M,
>>+		 * which could potentially increase the likelihood of the kernel
>>+		 * being able to utilise 2M GTT pages underneath, if the layout
>>+		 * of the physical pages allows it.  On some configurations we
>>+		 * can then also use a more efficient page-table layout, if we
>>+		 * can't use the more desirable 2M GTT page, so long as we know
>>+		 * that the entire page-table will be used by this object.
>>+		 */
>>+		__u32 gtt_alignment;
>>+	};
>>  	/**
>>  	 * @probed_size: Memory probed by the driver
>>diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
>>index 84e1bceb38..cbe27d6714 100644
>>--- a/lib/i915/intel_memory_region.c
>>+++ b/lib/i915/intel_memory_region.c
>>@@ -944,6 +944,7 @@ struct gem_memory_region *__gem_get_memory_regions(int i915)
>>  		r->ci = info->regions[i].region;
>>  		r->size = info->regions[i].probed_size;
>>+		r->gtt_alignment = info->regions[i].gtt_alignment;
>
>I made a big mess here since this change needs to be temporarily 
>reverted[1]. Sorry about that. For now we could maybe just do 
>something like:
>
>gtt_alignment = HAS_64K_PAGES() && ci.memory_type == DEVICE ? 64K : 4K;
>
>I can then fix this up when adding back the gtt_alignment, if your 
>series is merged first.
>
>[1] https://patchwork.freedesktop.org/series/110041/

Ok, will do.

Thanks,
Niranjana

>
>>  		r->cpu_size = info->regions[i].probed_cpu_visible_size;
>>  		if (r->size == -1ull)
>>  			r->size = igt_get_avail_ram_mb() << 20;
>>diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
>>index 425bda0ec7..84abb95b1a 100644
>>--- a/lib/i915/intel_memory_region.h
>>+++ b/lib/i915/intel_memory_region.h
>>@@ -174,6 +174,7 @@ struct gem_memory_region {
>>  	char *name;
>>  	struct drm_i915_gem_memory_class_instance ci;
>>+	uint64_t gtt_alignment;
>>  	uint64_t size;
>>  	uint64_t cpu_size;
>>  };

Re: [igt-dev] [PATCH i-g-t v5 11/12] tests/i915/vm_bind: Add gem_exec3_balancer test

[Matthew Auld]

On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:
> To test parallel submissions support in execbuf3, port the subtest
> gem_exec_balancer@parallel-ordering to a new gem_exec3_balancer test
> and switch to execbuf3 ioctl.
> 
> v2: use i915_vm_bind library functions
> v3: Remove unwanted gem_set_domain()
> 
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>

Re: [igt-dev] [PATCH i-g-t v5 12/12] tests/i915/vm_bind: Add gem_lmem_swapping@vm_bind sub test

[Matthew Auld]

On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:
> Validate eviction of objects with persistent mappings and
> check persistent mappings are properly rebound upon subsequent
> execbuf3 call.
> 
> TODO: Add a new swapping test with just vm_bind mode
>        (without legacy execbuf).
> 
> v2: use i915_vm_bind library functions
> v3: fix dg2 alignment issue
> 
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
> ---
>   tests/i915/gem_lmem_swapping.c | 134 ++++++++++++++++++++++++++++++++-
>   1 file changed, 133 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
> index cccdb3195b..cb1c86e03c 100644
> --- a/tests/i915/gem_lmem_swapping.c
> +++ b/tests/i915/gem_lmem_swapping.c
> @@ -3,12 +3,16 @@
>    * Copyright © 2021 Intel Corporation
>    */
>   
> +#include <poll.h>
> +
>   #include "i915/gem.h"
>   #include "i915/gem_create.h"
>   #include "i915/gem_vm.h"
>   #include "i915/intel_memory_region.h"
> +#include "i915/i915_vm_bind.h"
>   #include "igt.h"
>   #include "igt_kmod.h"
> +#include "igt_syncobj.h"
>   #include <unistd.h>
>   #include <stdlib.h>
>   #include <stdint.h>
> @@ -54,6 +58,7 @@ struct params {
>   		uint64_t max;
>   	} size;
>   	unsigned int count;
> +	unsigned int vm_bind_count;
>   	unsigned int loops;
>   	unsigned int mem_limit;
>   #define TEST_VERIFY	(1 << 0)
> @@ -64,15 +69,18 @@ struct params {
>   #define TEST_MULTI	(1 << 5)
>   #define TEST_CCS	(1 << 6)
>   #define TEST_MASSIVE	(1 << 7)
> +#define TEST_VM_BIND	(1 << 8)
>   	unsigned int flags;
>   	unsigned int seed;
>   	bool oom_test;
> +	uint64_t va;
>   };
>   
>   struct object {
>   	uint64_t size;
>   	uint32_t seed;
>   	uint32_t handle;
> +	uint64_t va;
>   	struct blt_copy_object *blt_obj;
>   };
>   
> @@ -278,6 +286,86 @@ verify_object_ccs(int i915, const struct object *obj,
>   	free(cmd);
>   }
>   
> +#define BATCH_VA       0xa00000
> +
> +static uint64_t gettime_ns(void)
> +{
> +	struct timespec current;
> +	clock_gettime(CLOCK_MONOTONIC, &current);
> +	return (uint64_t)current.tv_sec * NSEC_PER_SEC + current.tv_nsec;
> +}
> +
> +static void vm_bind(int i915, struct object *list, unsigned int num, uint64_t *va,
> +		    uint32_t batch, uint64_t batch_size, uint32_t vm_id)
> +{
> +	uint32_t *bind_syncobj;
> +	uint64_t *fence_value;
> +	unsigned int i;
> +
> +	bind_syncobj = calloc(num + 1, sizeof(*bind_syncobj));
> +	igt_assert(bind_syncobj);
> +
> +	fence_value = calloc(num + 1, sizeof(*fence_value));
> +	igt_assert(fence_value);
> +
> +	for (i = 0; i < num; i++) {
> +		list[i].va = *va;
> +		bind_syncobj[i] = syncobj_create(i915, 0);
> +		i915_vm_bind(i915, vm_id, *va, list[i].handle, 0, list[i].size, bind_syncobj[i], 0);
> +		*va += list[i].size;
> +	}
> +	bind_syncobj[i] = syncobj_create(i915, 0);
> +	i915_vm_bind(i915, vm_id, BATCH_VA, batch, 0, batch_size, bind_syncobj[i], 0);
> +
> +	igt_assert(syncobj_timeline_wait(i915, bind_syncobj, fence_value, num + 1,
> +					 gettime_ns() + (2 * NSEC_PER_SEC),
> +					 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
> +	for (i = 0; i <= num; i++)
> +		syncobj_destroy(i915, bind_syncobj[i]);
> +}
> +
> +static void vm_unbind(int i915, struct object *list, unsigned int num,
> +		      uint64_t batch_size, uint32_t vm_id)
> +{
> +	unsigned int i;
> +
> +	i915_vm_unbind(i915, vm_id, BATCH_VA, batch_size);
> +	for (i = 0; i < num; i++)
> +		i915_vm_unbind(i915, vm_id, list[i].va, list[i].size);
> +}
> +
> +static void move_to_lmem_execbuf3(int i915,
> +				  const intel_ctx_t *ctx,
> +				  unsigned int engine,
> +				  bool do_oom_test)
> +{
> +	uint32_t exec_syncobj = syncobj_create(i915, 0);
> +	struct drm_i915_gem_timeline_fence exec_fence = {
> +		.handle = exec_syncobj,
> +		.flags = I915_TIMELINE_FENCE_SIGNAL
> +	};
> +	struct drm_i915_gem_execbuffer3 eb = {
> +		.ctx_id = ctx->id,
> +		.batch_address = BATCH_VA,
> +		.engine_idx = engine,
> +		.fence_count = 1,
> +		.timeline_fences = to_user_pointer(&exec_fence),
> +	};
> +	uint64_t fence_value = 0;
> +	int ret;
> +
> +retry:
> +	ret = __gem_execbuf3(i915, &eb);
> +	if (do_oom_test && (ret == -ENOMEM || ret == -ENXIO))
> +		goto retry;
> +	igt_assert_eq(ret, 0);
> +
> +	igt_assert(syncobj_timeline_wait(i915, &exec_syncobj, &fence_value, 1,
> +					 gettime_ns() + (2 * NSEC_PER_SEC),
> +					 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
> +	syncobj_destroy(i915, exec_syncobj);
> +}
> +
>   static void move_to_lmem(int i915,
>   			 const intel_ctx_t *ctx,
>   			 struct object *list,
> @@ -325,14 +413,16 @@ static void __do_evict(int i915,
>   	uint32_t region_id = INTEL_MEMORY_REGION_ID(region->memory_class,
>   						    region->memory_instance);
>   	const unsigned int max_swap_in = params->count / 100 + 1;
> +	uint64_t size, ahnd, batch_size = SZ_64K;
>   	struct object *objects, *obj, *list;
>   	const uint32_t bpp = 32;
>   	uint32_t width, height, stride;
> +	const intel_ctx_t *vm_bind_ctx;
>   	const intel_ctx_t *blt_ctx;
>   	struct blt_copy_object *tmp;
>   	unsigned int engine = 0;
> +	uint32_t batch, vm_id;
>   	unsigned int i, l;
> -	uint64_t size, ahnd;
>   	struct timespec t = {};
>   	unsigned int num;
>   
> @@ -416,6 +506,26 @@ static void __do_evict(int i915,
>   		  readable_size(params->size.max), readable_unit(params->size.max),
>   		  params->count, seed);
>   
> +	/* VM_BIND the specified subset of objects (as persistent mappings) */
> +	if (params->flags & TEST_VM_BIND) {
> +		const uint32_t bbe = MI_BATCH_BUFFER_END;
> +		struct drm_i915_gem_context_param param = {
> +			.param = I915_CONTEXT_PARAM_RECOVERABLE,
> +			.value = 0,
> +		};
> +
> +		batch = gem_create_from_pool(i915, &batch_size, region_id);
> +		gem_write(i915, batch, 0, &bbe, sizeof(bbe));
> +
> +		vm_id = gem_vm_create_in_vm_bind_mode(i915);
> +		vm_bind_ctx = intel_ctx_create(i915, &ctx->cfg);
> +		param.ctx_id = vm_bind_ctx->id;
> +		gem_context_set_param(i915, &param);
> +		gem_context_set_vm(i915, vm_bind_ctx->id, vm_id);
> +		vm_bind(i915, objects, params->vm_bind_count, &params->va,
> +			batch, batch_size, vm_id);
> +	}
> +
>   	/*
>   	 * Move random objects back into lmem.
>   	 * For TEST_MULTI runs, make each object counts a loop to
> @@ -454,6 +564,15 @@ static void __do_evict(int i915,
>   		}
>   	}
>   
> +	/* Rebind persistent mappings to ensure they are swapped back in */
> +	if (params->flags & TEST_VM_BIND) {
> +		move_to_lmem_execbuf3(i915, vm_bind_ctx, engine, params->oom_test);
> +
> +		vm_unbind(i915, objects, params->vm_bind_count, batch_size, vm_id);
> +		intel_ctx_destroy(i915, vm_bind_ctx);
> +		gem_vm_destroy(i915, vm_id);
> +	}
> +
>   	for (i = 0; i < params->count; i++) {
>   		gem_close(i915, objects[i].handle);
>   		free(objects[i].blt_obj);
> @@ -553,6 +672,15 @@ static void fill_params(int i915, struct params *params,
>   	if (flags & TEST_HEAVY)
>   		params->loops = params->loops / 2 + 1;
>   
> +	/*
> +	 * Set vm_bind_count and ensure it doesn't over-subscribe LMEM.
> +	 * Set va range to ensure it is big enough for all bindings in a VM.
> +	 */
> +	if (flags & TEST_VM_BIND) {
> +		params->vm_bind_count = params->count * 50 / ((flags & TEST_HEAVY) ? 300 : 150);
> +		params->va = (uint64_t)params->vm_bind_count * size * 4;

How did we arrive at these numbers? Maybe some comments would be helpful?

Reviewed-by: Matthew Auld <matthew.auld@intel.com>

> +	}
> +
>   	params->flags = flags;
>   	params->oom_test = do_oom_test;
>   
> @@ -583,6 +711,9 @@ static void test_evict(int i915,
>   	if (flags & TEST_CCS)
>   		igt_require(IS_DG2(intel_get_drm_devid(i915)));
>   
> +	if (flags & TEST_VM_BIND)
> +		igt_require(i915_vm_bind_version(i915) == 1);
> +
>   	fill_params(i915, &params, region, flags, nproc, false);
>   
>   	if (flags & TEST_PARALLEL) {
> @@ -764,6 +895,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
>   		{ "heavy-verify-random-ccs", TEST_CCS | TEST_RANDOM | TEST_HEAVY },
>   		{ "heavy-verify-multi-ccs", TEST_CCS | TEST_RANDOM | TEST_HEAVY | TEST_ENGINES | TEST_MULTI },
>   		{ "parallel-random-verify-ccs", TEST_PARALLEL | TEST_RANDOM | TEST_CCS },
> +		{ "vm_bind", TEST_VM_BIND },
>   		{ }
>   	};
>   	const intel_ctx_t *ctx;

Re: [igt-dev] [PATCH i-g-t v5 12/12] tests/i915/vm_bind: Add gem_lmem_swapping@vm_bind sub test

[Niranjana Vishwanathapura]

On Fri, Oct 28, 2022 at 06:40:44PM +0100, Matthew Auld wrote:
>On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:
>>Validate eviction of objects with persistent mappings and
>>check persistent mappings are properly rebound upon subsequent
>>execbuf3 call.
>>
>>TODO: Add a new swapping test with just vm_bind mode
>>       (without legacy execbuf).
>>
>>v2: use i915_vm_bind library functions
>>v3: fix dg2 alignment issue
>>
>>Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
>>---
>>  tests/i915/gem_lmem_swapping.c | 134 ++++++++++++++++++++++++++++++++-
>>  1 file changed, 133 insertions(+), 1 deletion(-)
>>
>>diff --git a/tests/i915/gem_lmem_swapping.c b/tests/i915/gem_lmem_swapping.c
>>index cccdb3195b..cb1c86e03c 100644
>>--- a/tests/i915/gem_lmem_swapping.c
>>+++ b/tests/i915/gem_lmem_swapping.c
>>@@ -3,12 +3,16 @@
>>   * Copyright © 2021 Intel Corporation
>>   */
>>+#include <poll.h>
>>+
>>  #include "i915/gem.h"
>>  #include "i915/gem_create.h"
>>  #include "i915/gem_vm.h"
>>  #include "i915/intel_memory_region.h"
>>+#include "i915/i915_vm_bind.h"
>>  #include "igt.h"
>>  #include "igt_kmod.h"
>>+#include "igt_syncobj.h"
>>  #include <unistd.h>
>>  #include <stdlib.h>
>>  #include <stdint.h>
>>@@ -54,6 +58,7 @@ struct params {
>>  		uint64_t max;
>>  	} size;
>>  	unsigned int count;
>>+	unsigned int vm_bind_count;
>>  	unsigned int loops;
>>  	unsigned int mem_limit;
>>  #define TEST_VERIFY	(1 << 0)
>>@@ -64,15 +69,18 @@ struct params {
>>  #define TEST_MULTI	(1 << 5)
>>  #define TEST_CCS	(1 << 6)
>>  #define TEST_MASSIVE	(1 << 7)
>>+#define TEST_VM_BIND	(1 << 8)
>>  	unsigned int flags;
>>  	unsigned int seed;
>>  	bool oom_test;
>>+	uint64_t va;
>>  };
>>  struct object {
>>  	uint64_t size;
>>  	uint32_t seed;
>>  	uint32_t handle;
>>+	uint64_t va;
>>  	struct blt_copy_object *blt_obj;
>>  };
>>@@ -278,6 +286,86 @@ verify_object_ccs(int i915, const struct object *obj,
>>  	free(cmd);
>>  }
>>+#define BATCH_VA       0xa00000
>>+
>>+static uint64_t gettime_ns(void)
>>+{
>>+	struct timespec current;
>>+	clock_gettime(CLOCK_MONOTONIC, &current);
>>+	return (uint64_t)current.tv_sec * NSEC_PER_SEC + current.tv_nsec;
>>+}
>>+
>>+static void vm_bind(int i915, struct object *list, unsigned int num, uint64_t *va,
>>+		    uint32_t batch, uint64_t batch_size, uint32_t vm_id)
>>+{
>>+	uint32_t *bind_syncobj;
>>+	uint64_t *fence_value;
>>+	unsigned int i;
>>+
>>+	bind_syncobj = calloc(num + 1, sizeof(*bind_syncobj));
>>+	igt_assert(bind_syncobj);
>>+
>>+	fence_value = calloc(num + 1, sizeof(*fence_value));
>>+	igt_assert(fence_value);
>>+
>>+	for (i = 0; i < num; i++) {
>>+		list[i].va = *va;
>>+		bind_syncobj[i] = syncobj_create(i915, 0);
>>+		i915_vm_bind(i915, vm_id, *va, list[i].handle, 0, list[i].size, bind_syncobj[i], 0);
>>+		*va += list[i].size;
>>+	}
>>+	bind_syncobj[i] = syncobj_create(i915, 0);
>>+	i915_vm_bind(i915, vm_id, BATCH_VA, batch, 0, batch_size, bind_syncobj[i], 0);
>>+
>>+	igt_assert(syncobj_timeline_wait(i915, bind_syncobj, fence_value, num + 1,
>>+					 gettime_ns() + (2 * NSEC_PER_SEC),
>>+					 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
>>+	for (i = 0; i <= num; i++)
>>+		syncobj_destroy(i915, bind_syncobj[i]);
>>+}
>>+
>>+static void vm_unbind(int i915, struct object *list, unsigned int num,
>>+		      uint64_t batch_size, uint32_t vm_id)
>>+{
>>+	unsigned int i;
>>+
>>+	i915_vm_unbind(i915, vm_id, BATCH_VA, batch_size);
>>+	for (i = 0; i < num; i++)
>>+		i915_vm_unbind(i915, vm_id, list[i].va, list[i].size);
>>+}
>>+
>>+static void move_to_lmem_execbuf3(int i915,
>>+				  const intel_ctx_t *ctx,
>>+				  unsigned int engine,
>>+				  bool do_oom_test)
>>+{
>>+	uint32_t exec_syncobj = syncobj_create(i915, 0);
>>+	struct drm_i915_gem_timeline_fence exec_fence = {
>>+		.handle = exec_syncobj,
>>+		.flags = I915_TIMELINE_FENCE_SIGNAL
>>+	};
>>+	struct drm_i915_gem_execbuffer3 eb = {
>>+		.ctx_id = ctx->id,
>>+		.batch_address = BATCH_VA,
>>+		.engine_idx = engine,
>>+		.fence_count = 1,
>>+		.timeline_fences = to_user_pointer(&exec_fence),
>>+	};
>>+	uint64_t fence_value = 0;
>>+	int ret;
>>+
>>+retry:
>>+	ret = __gem_execbuf3(i915, &eb);
>>+	if (do_oom_test && (ret == -ENOMEM || ret == -ENXIO))
>>+		goto retry;
>>+	igt_assert_eq(ret, 0);
>>+
>>+	igt_assert(syncobj_timeline_wait(i915, &exec_syncobj, &fence_value, 1,
>>+					 gettime_ns() + (2 * NSEC_PER_SEC),
>>+					 DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, NULL));
>>+	syncobj_destroy(i915, exec_syncobj);
>>+}
>>+
>>  static void move_to_lmem(int i915,
>>  			 const intel_ctx_t *ctx,
>>  			 struct object *list,
>>@@ -325,14 +413,16 @@ static void __do_evict(int i915,
>>  	uint32_t region_id = INTEL_MEMORY_REGION_ID(region->memory_class,
>>  						    region->memory_instance);
>>  	const unsigned int max_swap_in = params->count / 100 + 1;
>>+	uint64_t size, ahnd, batch_size = SZ_64K;
>>  	struct object *objects, *obj, *list;
>>  	const uint32_t bpp = 32;
>>  	uint32_t width, height, stride;
>>+	const intel_ctx_t *vm_bind_ctx;
>>  	const intel_ctx_t *blt_ctx;
>>  	struct blt_copy_object *tmp;
>>  	unsigned int engine = 0;
>>+	uint32_t batch, vm_id;
>>  	unsigned int i, l;
>>-	uint64_t size, ahnd;
>>  	struct timespec t = {};
>>  	unsigned int num;
>>@@ -416,6 +506,26 @@ static void __do_evict(int i915,
>>  		  readable_size(params->size.max), readable_unit(params->size.max),
>>  		  params->count, seed);
>>+	/* VM_BIND the specified subset of objects (as persistent mappings) */
>>+	if (params->flags & TEST_VM_BIND) {
>>+		const uint32_t bbe = MI_BATCH_BUFFER_END;
>>+		struct drm_i915_gem_context_param param = {
>>+			.param = I915_CONTEXT_PARAM_RECOVERABLE,
>>+			.value = 0,
>>+		};
>>+
>>+		batch = gem_create_from_pool(i915, &batch_size, region_id);
>>+		gem_write(i915, batch, 0, &bbe, sizeof(bbe));
>>+
>>+		vm_id = gem_vm_create_in_vm_bind_mode(i915);
>>+		vm_bind_ctx = intel_ctx_create(i915, &ctx->cfg);
>>+		param.ctx_id = vm_bind_ctx->id;
>>+		gem_context_set_param(i915, &param);
>>+		gem_context_set_vm(i915, vm_bind_ctx->id, vm_id);
>>+		vm_bind(i915, objects, params->vm_bind_count, &params->va,
>>+			batch, batch_size, vm_id);
>>+	}
>>+
>>  	/*
>>  	 * Move random objects back into lmem.
>>  	 * For TEST_MULTI runs, make each object counts a loop to
>>@@ -454,6 +564,15 @@ static void __do_evict(int i915,
>>  		}
>>  	}
>>+	/* Rebind persistent mappings to ensure they are swapped back in */
>>+	if (params->flags & TEST_VM_BIND) {
>>+		move_to_lmem_execbuf3(i915, vm_bind_ctx, engine, params->oom_test);
>>+
>>+		vm_unbind(i915, objects, params->vm_bind_count, batch_size, vm_id);
>>+		intel_ctx_destroy(i915, vm_bind_ctx);
>>+		gem_vm_destroy(i915, vm_id);
>>+	}
>>+
>>  	for (i = 0; i < params->count; i++) {
>>  		gem_close(i915, objects[i].handle);
>>  		free(objects[i].blt_obj);
>>@@ -553,6 +672,15 @@ static void fill_params(int i915, struct params *params,
>>  	if (flags & TEST_HEAVY)
>>  		params->loops = params->loops / 2 + 1;
>>+	/*
>>+	 * Set vm_bind_count and ensure it doesn't over-subscribe LMEM.
>>+	 * Set va range to ensure it is big enough for all bindings in a VM.
>>+	 */
>>+	if (flags & TEST_VM_BIND) {
>>+		params->vm_bind_count = params->count * 50 / ((flags & TEST_HEAVY) ? 300 : 150);
>>+		params->va = (uint64_t)params->vm_bind_count * size * 4;
>
>How did we arrive at these numbers? Maybe some comments would be helpful?
>

It just needs to be some subset of params->count and should not oversubscribe LMEM.
1/3 sounded good with good amount of evictions. i will simply the logic here and
just make it params->count / 3.

>Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>

Thanks,
Niranjana

>>+	}
>>+
>>  	params->flags = flags;
>>  	params->oom_test = do_oom_test;
>>@@ -583,6 +711,9 @@ static void test_evict(int i915,
>>  	if (flags & TEST_CCS)
>>  		igt_require(IS_DG2(intel_get_drm_devid(i915)));
>>+	if (flags & TEST_VM_BIND)
>>+		igt_require(i915_vm_bind_version(i915) == 1);
>>+
>>  	fill_params(i915, &params, region, flags, nproc, false);
>>  	if (flags & TEST_PARALLEL) {
>>@@ -764,6 +895,7 @@ igt_main_args("", long_options, help_str, opt_handler, NULL)
>>  		{ "heavy-verify-random-ccs", TEST_CCS | TEST_RANDOM | TEST_HEAVY },
>>  		{ "heavy-verify-multi-ccs", TEST_CCS | TEST_RANDOM | TEST_HEAVY | TEST_ENGINES | TEST_MULTI },
>>  		{ "parallel-random-verify-ccs", TEST_PARALLEL | TEST_RANDOM | TEST_CCS },
>>+		{ "vm_bind", TEST_VM_BIND },
>>  		{ }
>>  	};
>>  	const intel_ctx_t *ctx;

Re: [igt-dev] [PATCH i-g-t v5 08/12] tests/i915/vm_bind: Add basic VM_BIND test support

[Matthew Auld]

On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:
> Add basic tests for VM_BIND functionality. Bind the buffer objects in
> device page table with VM_BIND calls and have GPU copy the data from a
> source buffer object to destination buffer object.
> Test for different buffer sizes, buffer object placement and with
> multiple contexts.
> 
> v2: Add basic test to fast-feedback.testlist
> v3: Run all tests for different memory types,
>      pass VA instead of an array for batch_address
> v4: Iterate for memory region types instead of hardcoding,
>      use i915_vm_bind library functions
> v5: Validate synchronous vm_bind, require blt engine,
>      use mr->gtt_alignment instead of HAS_64K_PAGES,
>      change info to debug messages, remove igt_collection usage,
>      fix dg2 alignment issue
> 
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>

With the comment from Petri addressed,
Reviewed-by: Matthew Auld <matthew.auld@intel.com>

Re: [igt-dev] [PATCH i-g-t v5 09/12] tests/i915/vm_bind: Add userptr subtest

[Matthew Auld]

On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:
> Add userptr object type to vm_bind_basic test.
> 
> v2: Run all tests for userptr type
> v3: Change info to debug messages, remove igt_collection usage
> 
> Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>

> ---
>   tests/i915/i915_vm_bind_basic.c | 55 +++++++++++++++++++++++++++++----
>   1 file changed, 49 insertions(+), 6 deletions(-)
> 
> diff --git a/tests/i915/i915_vm_bind_basic.c b/tests/i915/i915_vm_bind_basic.c
> index e794f0a845..f9cbb198e6 100644
> --- a/tests/i915/i915_vm_bind_basic.c
> +++ b/tests/i915/i915_vm_bind_basic.c
> @@ -235,16 +235,24 @@ static uint32_t create_obj(int fd, struct gem_memory_region *mr, uint32_t size,
>   {
>   	uint32_t handle;
>   
> -	handle = gem_create_in_memory_region_list(fd, size, 0, &mr->ci, 1);
> -	*addr = gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
> +	if (!mr) {
> +		igt_assert(posix_memalign(addr, SZ_2M * MAX_CTXTS, size) == 0);
> +		gem_userptr(fd, *addr, size, 0, 0, &handle);
> +	} else {
> +		handle = gem_create_in_memory_region_list(fd, size, 0, &mr->ci, 1);
> +		*addr = gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
> +	}
>   
>   	return handle;
>   }
>   
> -static void destroy_obj(int fd, uint32_t handle, uint32_t size, void *addr)
> +static void destroy_obj(int fd, uint32_t handle, uint32_t size, void *addr, bool is_userptr)
>   {
>   	igt_assert(gem_munmap(addr, size) == 0);
>   	gem_close(fd, handle);
> +
> +	if (is_userptr)
> +		free(addr);
>   }
>   
>   static void create_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[],
> @@ -255,6 +263,14 @@ static void create_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[]
>   	if (!num_cmds)
>   		return;
>   
> +	if (!mr) {
> +		for (i = 0; i < num_cmds; i++) {
> +			src[i] = create_obj(fd, NULL, size, &src_addr[i]);
> +			igt_debug("Src (userptr) obj 0x%x created\n", src[i]);
> +		}
> +		return;
> +	}
> +
>   	/* Create first src object always in memory region 'mr' */
>   	src[i] = create_obj(fd, mr, size, &src_addr[i]);
>   	igt_debug("Src (%s) obj 0x%x created\n", mr->name, src[i]);
> @@ -293,7 +309,7 @@ static void destroy_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[
>   
>   	for (i = 0; i < num_cmds; i++) {
>   		igt_debug("Closing src object 0x%x\n", src[i]);
> -		destroy_obj(fd, src[i], size, src_addr[i]);
> +		destroy_obj(fd, src[i], size, src_addr[i], !mr);
>   	}
>   }
>   
> @@ -301,7 +317,7 @@ static uint32_t create_dst_obj(int fd, struct gem_memory_region *mr, uint32_t si
>   {
>   	uint32_t dst = create_obj(fd, mr, size, dst_addr);
>   
> -	igt_debug("Dst (%s) obj 0x%x created\n", mr->name, dst);
> +	igt_debug("Dst (%s) obj 0x%x created\n", mr ? mr->name : "userptr", dst);
>   	return dst;
>   }
>   
> @@ -309,7 +325,7 @@ static void destroy_dst_obj(int fd, struct gem_memory_region *mr, uint32_t dst,
>   			    uint32_t size, void *dst_addr)
>   {
>   	igt_debug("Closing dst object 0x%x\n", dst);
> -	destroy_obj(fd, dst, size, dst_addr);
> +	destroy_obj(fd, dst, size, dst_addr, !mr);
>   }
>   
>   static void pattern_fill_buf(void *src_addr[], uint32_t size, uint32_t num_cmds, uint32_t npages)
> @@ -499,6 +515,25 @@ static void run_test(int fd, const intel_ctx_t *base_ctx, struct test_cfg *cfg,
>   		gem_vm_destroy(fd, shared_vm_id);
>   }
>   
> +static int has_userptr(int fd)
> +{
> +	uint32_t handle = 0;
> +	void *ptr;
> +	int ret;
> +
> +	assert(posix_memalign(&ptr, PAGE_SIZE, PAGE_SIZE) == 0);
> +	ret = __gem_userptr(fd, ptr, PAGE_SIZE, 0, 0, &handle);
> +	if (ret != 0) {
> +		free(ptr);
> +		return 0;
> +	}
> +
> +	gem_close(fd, handle);
> +	free(ptr);
> +
> +	return handle != 0;
> +}
> +
>   igt_main
>   {
>   	struct test_cfg *t, tests[] = {
> @@ -547,6 +582,14 @@ igt_main
>   				igt_dynamic_f("%s", r->name)
>   					run_test(fd, ctx, &cfg, r, alignment, e);
>   			}
> +
> +			if (has_userptr(fd)) {

It's probably fair to assume vm_bind support also means we have userptr? 
  But I guess can't hurt to check.

Reviewed-by: Matthew Auld <matthew.auld@intel.com>

> +				struct test_cfg cfg = *t;
> +
> +				/* Use NULL memory region for userptr */
> +				igt_dynamic("userptr")
> +					run_test(fd, ctx, &cfg, NULL, PAGE_SIZE, e);
> +			}
>   		}
>   	}
>   

Re: [igt-dev] [PATCH i-g-t v5 09/12] tests/i915/vm_bind: Add userptr subtest

[Niranjana Vishwanathapura]

On Mon, Oct 31, 2022 at 03:46:10PM +0000, Matthew Auld wrote:
>On 25/10/2022 07:59, Niranjana Vishwanathapura wrote:
>>Add userptr object type to vm_bind_basic test.
>>
>>v2: Run all tests for userptr type
>>v3: Change info to debug messages, remove igt_collection usage
>>
>>Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
>
>>---
>>  tests/i915/i915_vm_bind_basic.c | 55 +++++++++++++++++++++++++++++----
>>  1 file changed, 49 insertions(+), 6 deletions(-)
>>
>>diff --git a/tests/i915/i915_vm_bind_basic.c b/tests/i915/i915_vm_bind_basic.c
>>index e794f0a845..f9cbb198e6 100644
>>--- a/tests/i915/i915_vm_bind_basic.c
>>+++ b/tests/i915/i915_vm_bind_basic.c
>>@@ -235,16 +235,24 @@ static uint32_t create_obj(int fd, struct gem_memory_region *mr, uint32_t size,
>>  {
>>  	uint32_t handle;
>>-	handle = gem_create_in_memory_region_list(fd, size, 0, &mr->ci, 1);
>>-	*addr = gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
>>+	if (!mr) {
>>+		igt_assert(posix_memalign(addr, SZ_2M * MAX_CTXTS, size) == 0);
>>+		gem_userptr(fd, *addr, size, 0, 0, &handle);
>>+	} else {
>>+		handle = gem_create_in_memory_region_list(fd, size, 0, &mr->ci, 1);
>>+		*addr = gem_mmap__cpu(fd, handle, 0, size, PROT_WRITE);
>>+	}
>>  	return handle;
>>  }
>>-static void destroy_obj(int fd, uint32_t handle, uint32_t size, void *addr)
>>+static void destroy_obj(int fd, uint32_t handle, uint32_t size, void *addr, bool is_userptr)
>>  {
>>  	igt_assert(gem_munmap(addr, size) == 0);
>>  	gem_close(fd, handle);
>>+
>>+	if (is_userptr)
>>+		free(addr);
>>  }
>>  static void create_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[],
>>@@ -255,6 +263,14 @@ static void create_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[]
>>  	if (!num_cmds)
>>  		return;
>>+	if (!mr) {
>>+		for (i = 0; i < num_cmds; i++) {
>>+			src[i] = create_obj(fd, NULL, size, &src_addr[i]);
>>+			igt_debug("Src (userptr) obj 0x%x created\n", src[i]);
>>+		}
>>+		return;
>>+	}
>>+
>>  	/* Create first src object always in memory region 'mr' */
>>  	src[i] = create_obj(fd, mr, size, &src_addr[i]);
>>  	igt_debug("Src (%s) obj 0x%x created\n", mr->name, src[i]);
>>@@ -293,7 +309,7 @@ static void destroy_src_objs(int fd, struct gem_memory_region *mr, uint32_t src[
>>  	for (i = 0; i < num_cmds; i++) {
>>  		igt_debug("Closing src object 0x%x\n", src[i]);
>>-		destroy_obj(fd, src[i], size, src_addr[i]);
>>+		destroy_obj(fd, src[i], size, src_addr[i], !mr);
>>  	}
>>  }
>>@@ -301,7 +317,7 @@ static uint32_t create_dst_obj(int fd, struct gem_memory_region *mr, uint32_t si
>>  {
>>  	uint32_t dst = create_obj(fd, mr, size, dst_addr);
>>-	igt_debug("Dst (%s) obj 0x%x created\n", mr->name, dst);
>>+	igt_debug("Dst (%s) obj 0x%x created\n", mr ? mr->name : "userptr", dst);
>>  	return dst;
>>  }
>>@@ -309,7 +325,7 @@ static void destroy_dst_obj(int fd, struct gem_memory_region *mr, uint32_t dst,
>>  			    uint32_t size, void *dst_addr)
>>  {
>>  	igt_debug("Closing dst object 0x%x\n", dst);
>>-	destroy_obj(fd, dst, size, dst_addr);
>>+	destroy_obj(fd, dst, size, dst_addr, !mr);
>>  }
>>  static void pattern_fill_buf(void *src_addr[], uint32_t size, uint32_t num_cmds, uint32_t npages)
>>@@ -499,6 +515,25 @@ static void run_test(int fd, const intel_ctx_t *base_ctx, struct test_cfg *cfg,
>>  		gem_vm_destroy(fd, shared_vm_id);
>>  }
>>+static int has_userptr(int fd)
>>+{
>>+	uint32_t handle = 0;
>>+	void *ptr;
>>+	int ret;
>>+
>>+	assert(posix_memalign(&ptr, PAGE_SIZE, PAGE_SIZE) == 0);
>>+	ret = __gem_userptr(fd, ptr, PAGE_SIZE, 0, 0, &handle);
>>+	if (ret != 0) {
>>+		free(ptr);
>>+		return 0;
>>+	}
>>+
>>+	gem_close(fd, handle);
>>+	free(ptr);
>>+
>>+	return handle != 0;
>>+}
>>+
>>  igt_main
>>  {
>>  	struct test_cfg *t, tests[] = {
>>@@ -547,6 +582,14 @@ igt_main
>>  				igt_dynamic_f("%s", r->name)
>>  					run_test(fd, ctx, &cfg, r, alignment, e);
>>  			}
>>+
>>+			if (has_userptr(fd)) {
>
>It's probably fair to assume vm_bind support also means we have 
>userptr?  But I guess can't hurt to check.
>

Yah, I think so, but yah it doesn't hurt to check in case for somereason
we disable userptr.

>Reviewed-by: Matthew Auld <matthew.auld@intel.com>

Thanks,
Niranjana

>
>>+				struct test_cfg cfg = *t;
>>+
>>+				/* Use NULL memory region for userptr */
>>+				igt_dynamic("userptr")
>>+					run_test(fd, ctx, &cfg, NULL, PAGE_SIZE, e);
>>+			}
>>  		}
>>  	}