* [Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar
@ 2022-06-15 5:43 priyanka.dandamudi
2022-06-15 5:43 ` [Intel-gfx] [PATCH 1/2] drm/i915: " priyanka.dandamudi
` (5 more replies)
0 siblings, 6 replies; 20+ messages in thread
From: priyanka.dandamudi @ 2022-06-15 5:43 UTC (permalink / raw)
To: priyanka.dandamudi, matthew.auld, intel-gfx
From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
Added support to resize the bar to maximum supported,
only when bar is not set to maximum by default.
Also, added new modparam lmem_bar_size which can resize the bar
provided if it is among the supported sizes.
Akeem G Abodunrin (1):
drm/i915: Add support for LMEM PCIe resizable bar
Priyanka Dandamudi (1):
drm/i915: Add lmem_bar_size modparam
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 3 +
drivers/gpu/drm/i915/i915_driver.c | 126 ++++++++++++++++++++
drivers/gpu/drm/i915/i915_params.c | 2 +
drivers/gpu/drm/i915/i915_params.h | 1 +
4 files changed, 132 insertions(+)
--
2.27.0
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
2022-06-15 5:43 [Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar priyanka.dandamudi
@ 2022-06-15 5:43 ` priyanka.dandamudi
2022-06-15 10:51 ` Matthew Auld
2022-06-15 5:43 ` [Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam priyanka.dandamudi
` (4 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: priyanka.dandamudi @ 2022-06-15 5:43 UTC (permalink / raw)
To: priyanka.dandamudi, matthew.auld, intel-gfx
From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
This patch adds support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.
Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
---
drivers/gpu/drm/i915/i915_driver.c | 103 +++++++++++++++++++++++++++++
1 file changed, 103 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index b47746152d97..8d33a6a31675 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -303,6 +303,106 @@ static void sanitize_gpu(struct drm_i915_private *i915)
__intel_gt_reset(to_gt(i915), ALL_ENGINES);
}
+static void __release_bars(struct pci_dev *pdev)
+{
+ int resno;
+
+ for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+ if (pci_resource_len(pdev, resno))
+ pci_release_resource(pdev, resno);
+ }
+}
+
+static void
+__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ int bar_size = pci_rebar_bytes_to_size(size);
+ int ret;
+
+ __release_bars(pdev);
+
+ ret = pci_resize_resource(pdev, resno, bar_size);
+ if (ret) {
+ drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+ resno, 1 << bar_size, ERR_PTR(ret));
+ return;
+ }
+
+ drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/* BAR size starts from 1MB - 2^20 */
+#define BAR_SIZE_SHIFT 20
+static resource_size_t
+__lmem_rebar_size(struct drm_i915_private *i915, int resno)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
+ resource_size_t size;
+
+ if (!rebar)
+ return 0;
+
+ size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
+
+ if (size <= pci_resource_len(pdev, resno))
+ return 0;
+
+ return size;
+}
+
+/**
+ * i915_resize_lmem_bar - resize local memory BAR
+ * @i915: device private
+ *
+ * This function will attempt to resize LMEM bar to make all memory accessible.
+ * Whether it will be successful depends on both device and platform
+ * capabilities. Any errors are non-critical, even if resize fails, we go back
+ * to the previous configuration.
+ */
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct pci_bus *root = pdev->bus;
+ struct resource *root_res;
+ resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
+ u32 pci_cmd;
+ int i;
+
+ if (!rebar_size)
+ return;
+
+ /* Find out if root bus contains 64bit memory addressing */
+ while (root->parent)
+ root = root->parent;
+
+ pci_bus_for_each_resource(root, root_res, i) {
+ if (root_res &&
+ root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
+ root_res->start > 0x100000000ull)
+ break;
+ }
+
+ /* pci_resize_resource will fail anyways */
+ if (!root_res) {
+ drm_info(&i915->drm,
+ "Can't resize LMEM BAR - platform support is missing\n");
+ return;
+ }
+
+ /* First disable PCI memory decoding references */
+ pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+ pci_write_config_dword(pdev, PCI_COMMAND,
+ pci_cmd & ~PCI_COMMAND_MEMORY);
+
+ __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+ pci_assign_unassigned_bus_resources(pdev->bus);
+ pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
/**
* i915_driver_early_probe - setup state not requiring device access
* @dev_priv: device private
@@ -836,6 +936,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
disable_rpm_wakeref_asserts(&i915->runtime_pm);
+ if (HAS_LMEM(i915))
+ i915_resize_lmem_bar(i915);
+
intel_vgpu_detect(i915);
ret = intel_gt_probe_all(i915);
--
2.27.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam
2022-06-15 5:43 [Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar priyanka.dandamudi
2022-06-15 5:43 ` [Intel-gfx] [PATCH 1/2] drm/i915: " priyanka.dandamudi
@ 2022-06-15 5:43 ` priyanka.dandamudi
2022-06-15 10:17 ` Matthew Auld
2022-06-15 9:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for LMEM PCIe resizable bar Patchwork
` (3 subsequent siblings)
5 siblings, 1 reply; 20+ messages in thread
From: priyanka.dandamudi @ 2022-06-15 5:43 UTC (permalink / raw)
To: priyanka.dandamudi, matthew.auld, intel-gfx
From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
lmem_bar_size is used to resize lmem bar.
It sets to only one of the supported sizes.
Setting this param will be in MB unit.
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 3 +++
drivers/gpu/drm/i915/i915_driver.c | 25 ++++++++++++++++++++-
drivers/gpu/drm/i915/i915_params.c | 2 ++
drivers/gpu/drm/i915/i915_params.h | 1 +
4 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 119e53f5d9b1..d73d8b2adfa2 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -132,6 +132,9 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
mul_u32_u32(i915->params.lmem_size, SZ_1M));
}
+ if (i915->params.lmem_bar_size > 0)
+ lmem_size = pci_resource_len(pdev, 2);
+
io_start = pci_resource_start(pdev, 2);
io_size = min(pci_resource_len(pdev, 2), lmem_size);
if (!io_size)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 8d33a6a31675..2f5d7a1f1a7b 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -371,7 +371,30 @@ static void i915_resize_lmem_bar(struct drm_i915_private *i915)
u32 pci_cmd;
int i;
- if (!rebar_size)
+ if (i915->params.lmem_bar_size > 0) {
+ u32 lmem_bar_size;
+ u32 set_bit;
+ u32 rebar;
+ u32 msb;
+ int k;
+
+ lmem_bar_size = i915->params.lmem_bar_size;
+ rebar = pci_rebar_get_possible_sizes(pdev, LMEM_BAR_NUM);
+ msb = __fls(rebar);
+
+ for (k = msb; k >= 0; k--) {
+ set_bit = (1 << k);
+
+ if (set_bit & rebar)
+ if (set_bit == lmem_bar_size) {
+ rebar_size = 1ULL << (__fls(lmem_bar_size) + BAR_SIZE_SHIFT);
+
+ if (rebar_size == pci_resource_len(pdev, LMEM_BAR_NUM))
+ return;
+ break;
+ }
+ }
+ } else if (!rebar_size)
return;
/* Find out if root bus contains 64bit memory addressing */
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 701fbc98afa0..6fc475a5db61 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
i915_param_named_unsafe(lmem_size, uint, 0400,
"Set the lmem size(in MiB) for each region. (default: 0, all memory)");
+i915_param_named_unsafe(lmem_bar_size, uint, 0400,
+ "Set the lmem bar size(in MiB).");
static __always_inline void _print_param(struct drm_printer *p,
const char *name,
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index b5e7ea45d191..2733cb6cfe09 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -74,6 +74,7 @@ struct drm_printer;
param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
param(unsigned int, request_timeout_ms, CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
param(unsigned int, lmem_size, 0, 0400) \
+ param(unsigned int, lmem_bar_size, 0, 0400) \
/* leave bools at the end to not create holes */ \
param(bool, enable_hangcheck, true, 0600) \
param(bool, load_detect_test, false, 0600) \
--
2.27.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for LMEM PCIe resizable bar
2022-06-15 5:43 [Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar priyanka.dandamudi
2022-06-15 5:43 ` [Intel-gfx] [PATCH 1/2] drm/i915: " priyanka.dandamudi
2022-06-15 5:43 ` [Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam priyanka.dandamudi
@ 2022-06-15 9:26 ` Patchwork
2022-06-15 9:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-06-15 9:26 UTC (permalink / raw)
To: priyanka.dandamudi; +Cc: intel-gfx
== Series Details ==
Series: Add support for LMEM PCIe resizable bar
URL : https://patchwork.freedesktop.org/series/105142/
State : warning
== Summary ==
Error: dim checkpatch failed
a4fabe36823d drm/i915: Add support for LMEM PCIe resizable bar
-:110: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#110: FILE: drivers/gpu/drm/i915/i915_driver.c:383:
+ if (root_res &&
+ root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
-:118: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#118: FILE: drivers/gpu/drm/i915/i915_driver.c:391:
+ drm_info(&i915->drm,
+ "Can't resize LMEM BAR - platform support is missing\n");
total: 0 errors, 0 warnings, 2 checks, 115 lines checked
17bbf04fb92b drm/i915: Add lmem_bar_size modparam
-:36: CHECK:BRACES: braces {} should be used on all arms of this statement
#36: FILE: drivers/gpu/drm/i915/i915_driver.c:374:
+ if (i915->params.lmem_bar_size > 0) {
[...]
+ } else if (!rebar_size)
[...]
-:52: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#52: FILE: drivers/gpu/drm/i915/i915_driver.c:390:
+ rebar_size = 1ULL << (__fls(lmem_bar_size) + BAR_SIZE_SHIFT);
total: 0 errors, 1 warnings, 1 checks, 55 lines checked
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add support for LMEM PCIe resizable bar
2022-06-15 5:43 [Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar priyanka.dandamudi
` (2 preceding siblings ...)
2022-06-15 9:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for LMEM PCIe resizable bar Patchwork
@ 2022-06-15 9:26 ` Patchwork
2022-06-15 9:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-15 14:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-06-15 9:26 UTC (permalink / raw)
To: priyanka.dandamudi; +Cc: intel-gfx
== Series Details ==
Series: Add support for LMEM PCIe resizable bar
URL : https://patchwork.freedesktop.org/series/105142/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Add support for LMEM PCIe resizable bar
2022-06-15 5:43 [Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar priyanka.dandamudi
` (3 preceding siblings ...)
2022-06-15 9:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-06-15 9:49 ` Patchwork
2022-06-15 14:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-06-15 9:49 UTC (permalink / raw)
To: priyanka.dandamudi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 8630 bytes --]
== Series Details ==
Series: Add support for LMEM PCIe resizable bar
URL : https://patchwork.freedesktop.org/series/105142/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11759 -> Patchwork_105142v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/index.html
Participating hosts (44 -> 41)
------------------------------
Additional (1): bat-dg2-8
Missing (4): fi-kbl-soraka fi-bdw-samus bat-jsl-2 fi-apl-guc
Known issues
------------
Here are the changes found in Patchwork_105142v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [PASS][1] -> [DMESG-FAIL][2] ([i915#62])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-5: [PASS][3] -> [INCOMPLETE][4] ([i915#4418])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/bat-dg1-5/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gt_mocs:
- fi-rkl-guc: [PASS][5] -> [DMESG-WARN][6] ([i915#5790])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-rkl-guc/igt@i915_selftest@live@gt_mocs.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/fi-rkl-guc/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [PASS][7] -> [DMESG-FAIL][8] ([i915#4494] / [i915#4957])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@late_gt_pm:
- fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#5904]) +11 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/fi-cfl-8109u/igt@i915_selftest@live@late_gt_pm.html
* igt@i915_selftest@live@mman:
- fi-bdw-5557u: [PASS][11] -> [INCOMPLETE][12] ([i915#5704])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-bdw-5557u/igt@i915_selftest@live@mman.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/fi-bdw-5557u/igt@i915_selftest@live@mman.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-cfl-8109u: [PASS][13] -> [DMESG-WARN][14] ([i915#5904] / [i915#62])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/fi-cfl-8109u/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-blb-e6850: NOTRUN -> [SKIP][15] ([fdo#109271])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/fi-blb-e6850/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cfl-8109u: [PASS][16] -> [DMESG-WARN][17] ([i915#62]) +15 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- bat-adlp-4: [DMESG-WARN][18] ([i915#3576]) -> [PASS][19] +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/bat-adlp-4/igt@i915_pm_rpm@module-reload.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/bat-adlp-4/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-cfl-guc: [DMESG-FAIL][20] ([i915#5334]) -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/fi-cfl-guc/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [DMESG-FAIL][22] ([i915#4528]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/fi-blb-e6850/igt@i915_selftest@live@requests.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- {bat-dg2-9}: [DMESG-WARN][24] ([i915#5763]) -> [PASS][25] +4 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/bat-dg2-9/igt@i915_selftest@live@slpc.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/bat-dg2-9/igt@i915_selftest@live@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5704]: https://gitlab.freedesktop.org/drm/intel/issues/5704
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5790]: https://gitlab.freedesktop.org/drm/intel/issues/5790
[i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
[i915#5886]: https://gitlab.freedesktop.org/drm/intel/issues/5886
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
Build changes
-------------
* Linux: CI_DRM_11759 -> Patchwork_105142v1
CI-20190529: 20190529
CI_DRM_11759: fa66b647ce886c01bbe1e9f3017a141e90d87539 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6529: b96bf5a0307fc0bdbf6c8e86872817306e102883 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_105142v1: fa66b647ce886c01bbe1e9f3017a141e90d87539 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
8c03352b983f drm/i915: Add lmem_bar_size modparam
b8d4b6c063c7 drm/i915: Add support for LMEM PCIe resizable bar
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/index.html
[-- Attachment #2: Type: text/html, Size: 7936 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam
2022-06-15 5:43 ` [Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam priyanka.dandamudi
@ 2022-06-15 10:17 ` Matthew Auld
0 siblings, 0 replies; 20+ messages in thread
From: Matthew Auld @ 2022-06-15 10:17 UTC (permalink / raw)
To: priyanka.dandamudi, intel-gfx
On 15/06/2022 06:43, priyanka.dandamudi@intel.com wrote:
> From: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>
> lmem_bar_size is used to resize lmem bar.
> It sets to only one of the supported sizes.
> Setting this param will be in MB unit.
Maybe add some more information here for why we want to add this?
Something like:
"For testing purposes, support forcing the lmem_bar size through a new
modparam. In CI we only have a limited number of configurations for DG2,
but we still need to be reasonably sure we get a usable device (also
verifying we report the correct values for things like
probed_cpu_visible_size etc) with all the potential lmem_bar sizes that
we might expect see in the wild."
?
>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_region_lmem.c | 3 +++
> drivers/gpu/drm/i915/i915_driver.c | 25 ++++++++++++++++++++-
> drivers/gpu/drm/i915/i915_params.c | 2 ++
> drivers/gpu/drm/i915/i915_params.h | 1 +
> 4 files changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index 119e53f5d9b1..d73d8b2adfa2 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -132,6 +132,9 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
> mul_u32_u32(i915->params.lmem_size, SZ_1M));
> }
>
> + if (i915->params.lmem_bar_size > 0)
> + lmem_size = pci_resource_len(pdev, 2);
This is just a temporary hack until we have all the small-bar stuff
landed, right? If so, maybe annotate with:
/* XXX: remove once we land small-bar uapi bits */
So we don't forget to remove this.
> +
> io_start = pci_resource_start(pdev, 2);
> io_size = min(pci_resource_len(pdev, 2), lmem_size);
> if (!io_size)
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 8d33a6a31675..2f5d7a1f1a7b 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -371,7 +371,30 @@ static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> u32 pci_cmd;
> int i;
>
> - if (!rebar_size)
> + if (i915->params.lmem_bar_size > 0) {
> + u32 lmem_bar_size;
> + u32 set_bit;
> + u32 rebar;
> + u32 msb;
> + int k;
> +
> + lmem_bar_size = i915->params.lmem_bar_size;
> + rebar = pci_rebar_get_possible_sizes(pdev, LMEM_BAR_NUM);
> + msb = __fls(rebar);
> +
> + for (k = msb; k >= 0; k--) {
> + set_bit = (1 << k);
> +
> + if (set_bit & rebar)
> + if (set_bit == lmem_bar_size) {
> + rebar_size = 1ULL << (__fls(lmem_bar_size) + BAR_SIZE_SHIFT);
> +
> + if (rebar_size == pci_resource_len(pdev, LMEM_BAR_NUM))
> + return;
> + break;
> + }
> + }
> + } else if (!rebar_size)
> return;
>
> /* Find out if root bus contains 64bit memory addressing */
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 701fbc98afa0..6fc475a5db61 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -204,6 +204,8 @@ i915_param_named_unsafe(request_timeout_ms, uint, 0600,
>
> i915_param_named_unsafe(lmem_size, uint, 0400,
> "Set the lmem size(in MiB) for each region. (default: 0, all memory)");
> +i915_param_named_unsafe(lmem_bar_size, uint, 0400,
> + "Set the lmem bar size(in MiB).");
>
> static __always_inline void _print_param(struct drm_printer *p,
> const char *name,
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index b5e7ea45d191..2733cb6cfe09 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -74,6 +74,7 @@ struct drm_printer;
> param(char *, force_probe, CONFIG_DRM_I915_FORCE_PROBE, 0400) \
> param(unsigned int, request_timeout_ms, CONFIG_DRM_I915_REQUEST_TIMEOUT, CONFIG_DRM_I915_REQUEST_TIMEOUT ? 0600 : 0) \
> param(unsigned int, lmem_size, 0, 0400) \
> + param(unsigned int, lmem_bar_size, 0, 0400) \
> /* leave bools at the end to not create holes */ \
> param(bool, enable_hangcheck, true, 0600) \
> param(bool, load_detect_test, false, 0600) \
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
2022-06-15 5:43 ` [Intel-gfx] [PATCH 1/2] drm/i915: " priyanka.dandamudi
@ 2022-06-15 10:51 ` Matthew Auld
0 siblings, 0 replies; 20+ messages in thread
From: Matthew Auld @ 2022-06-15 10:51 UTC (permalink / raw)
To: priyanka.dandamudi, intel-gfx
On 15/06/2022 06:43, priyanka.dandamudi@intel.com wrote:
> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>
> This patch adds support for the local memory PICe resizable bar, so that
> local memory can be resized to the maximum size supported by the device,
> and mapped correctly to the PCIe memory bar. It is usual that GPU
> devices expose only 256MB BARs primarily to be compatible with 32-bit
> systems. So, those devices cannot claim larger memory BAR windows size due
> to the system BIOS limitation. With this change, it would be possible to
> reprogram the windows of the bridge directly above the requesting device
> on the same BAR type.
>
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_driver.c | 103 +++++++++++++++++++++++++++++
> 1 file changed, 103 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index b47746152d97..8d33a6a31675 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -303,6 +303,106 @@ static void sanitize_gpu(struct drm_i915_private *i915)
> __intel_gt_reset(to_gt(i915), ALL_ENGINES);
> }
>
> +static void __release_bars(struct pci_dev *pdev)
> +{
> + int resno;
> +
> + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
> + if (pci_resource_len(pdev, resno))
> + pci_release_resource(pdev, resno);
> + }
> +}
> +
> +static void
> +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + int bar_size = pci_rebar_bytes_to_size(size);
> + int ret;
> +
> + __release_bars(pdev);
> +
> + ret = pci_resize_resource(pdev, resno, bar_size);
> + if (ret) {
> + drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
> + resno, 1 << bar_size, ERR_PTR(ret));
> + return;
> + }
> +
> + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> +}
> +
> +/* BAR size starts from 1MB - 2^20 */
> +#define BAR_SIZE_SHIFT 20
> +static resource_size_t
> +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> + resource_size_t size;
> +
> + if (!rebar)
> + return 0;
> +
> + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> +
> + if (size <= pci_resource_len(pdev, resno))
> + return 0;
> +
> + return size;
> +}
> +
> +/**
> + * i915_resize_lmem_bar - resize local memory BAR
> + * @i915: device private
We don't normally add kernel-doc for static functions.
There are also some checkpatch warnings that need to be fixed, but
otherwise this looks reasonable to me, and the flow seems to closely
match what amdgpu is already doing with their bar resizing stuff,
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> + *
> + * This function will attempt to resize LMEM bar to make all memory accessible.
> + * Whether it will be successful depends on both device and platform
> + * capabilities. Any errors are non-critical, even if resize fails, we go back
> + * to the previous configuration.
> + */
> +#define LMEM_BAR_NUM 2
> +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct pci_bus *root = pdev->bus;
> + struct resource *root_res;
> + resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
> + u32 pci_cmd;
> + int i;
> +
> + if (!rebar_size)
> + return;
> +
> + /* Find out if root bus contains 64bit memory addressing */
> + while (root->parent)
> + root = root->parent;
> +
> + pci_bus_for_each_resource(root, root_res, i) {
> + if (root_res &&
> + root_res->flags & (IORESOURCE_MEM | IORESOURCE_MEM_64) &&
> + root_res->start > 0x100000000ull)
> + break;
> + }
> +
> + /* pci_resize_resource will fail anyways */
> + if (!root_res) {
> + drm_info(&i915->drm,
> + "Can't resize LMEM BAR - platform support is missing\n");
> + return;
> + }
> +
> + /* First disable PCI memory decoding references */
> + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> + pci_write_config_dword(pdev, PCI_COMMAND,
> + pci_cmd & ~PCI_COMMAND_MEMORY);
> +
> + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> +
> + pci_assign_unassigned_bus_resources(pdev->bus);
> + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> +}
> +
> /**
> * i915_driver_early_probe - setup state not requiring device access
> * @dev_priv: device private
> @@ -836,6 +936,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>
> disable_rpm_wakeref_asserts(&i915->runtime_pm);
>
> + if (HAS_LMEM(i915))
> + i915_resize_lmem_bar(i915);
> +
> intel_vgpu_detect(i915);
>
> ret = intel_gt_probe_all(i915);
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Add support for LMEM PCIe resizable bar
2022-06-15 5:43 [Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar priyanka.dandamudi
` (4 preceding siblings ...)
2022-06-15 9:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-06-15 14:20 ` Patchwork
5 siblings, 0 replies; 20+ messages in thread
From: Patchwork @ 2022-06-15 14:20 UTC (permalink / raw)
To: Dandamudi, Priyanka; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 33545 bytes --]
== Series Details ==
Series: Add support for LMEM PCIe resizable bar
URL : https://patchwork.freedesktop.org/series/105142/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11759_full -> Patchwork_105142v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 13)
------------------------------
Additional (3): shard-rkl shard-dg1 shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_105142v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_cursor_edge_walk@top-edge:
- {shard-dg1}: NOTRUN -> [SKIP][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-dg1-13/igt@kms_cursor_edge_walk@top-edge.html
* igt@kms_cursor_legacy@all-pipes-single-bo:
- {shard-dg1}: NOTRUN -> [WARN][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-dg1-13/igt@kms_cursor_legacy@all-pipes-single-bo.html
* {igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1}:
- {shard-tglu}: NOTRUN -> [SKIP][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-tglu-2/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled:
- {shard-dg1}: NOTRUN -> [FAIL][4] +8 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-dg1-13/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled.html
* {igt@kms_plane_lowres@tiling-y@pipe-a-edp-1}:
- {shard-rkl}: NOTRUN -> [SKIP][5] +5 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-rkl-6/igt@kms_plane_lowres@tiling-y@pipe-a-edp-1.html
Known issues
------------
Here are the changes found in Patchwork_105142v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@unbind-reset-rebind:
- shard-skl: NOTRUN -> [DMESG-WARN][6] ([i915#1982])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl1/igt@device_reset@unbind-reset-rebind.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-iclb: [PASS][7] -> [TIMEOUT][8] ([i915#3070])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb5/igt@gem_eio@in-flight-contexts-10ms.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb4/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-iclb: [PASS][9] -> [SKIP][10] ([i915#4525]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb1/igt@gem_exec_balancer@parallel-keep-in-fence.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb8/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-tglb2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [PASS][13] -> [FAIL][14] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-apl7/igt@gem_exec_fair@basic-pace-share@rcs0.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-apl7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl3/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl3/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_pread@exhaustion:
- shard-skl: NOTRUN -> [WARN][17] ([i915#2658])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl1/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-kbl: NOTRUN -> [WARN][18] ([i915#2658])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl3/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_userptr_blits@input-checking:
- shard-skl: NOTRUN -> [DMESG-WARN][19] ([i915#4991])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl2/igt@gem_userptr_blits@input-checking.html
* igt@gen9_exec_parse@allowed-single:
- shard-glk: [PASS][20] -> [DMESG-WARN][21] ([i915#5566] / [i915#716])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-glk3/igt@gen9_exec_parse@allowed-single.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-glk3/igt@gen9_exec_parse@allowed-single.html
* igt@i915_module_load@load:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#6227])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl4/igt@i915_module_load@load.html
* igt@i915_pm_dc@dc9-dpms:
- shard-skl: NOTRUN -> [INCOMPLETE][23] ([i915#5961])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl4/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
- shard-skl: NOTRUN -> [FAIL][24] ([i915#2521])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl1/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
* igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3886]) +4 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl4/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3886]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-apl6/igt@kms_ccs@pipe-c-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#3886])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl3/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_color_chamelium@pipe-a-ctm-negative:
- shard-kbl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +3 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl3/igt@kms_color_chamelium@pipe-a-ctm-negative.html
* igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-apl6/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +3 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl2/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_content_protection@lic:
- shard-kbl: NOTRUN -> [TIMEOUT][31] ([i915#1319])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl3/igt@kms_content_protection@lic.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271]) +51 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-32x32-random:
- shard-apl: NOTRUN -> [SKIP][33] ([fdo#109271]) +65 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-apl6/igt@kms_cursor_crc@pipe-d-cursor-32x32-random.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-kbl: [PASS][34] -> [DMESG-WARN][35] ([i915#180]) +13 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-skl: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#3701])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
- shard-glk: [PASS][37] -> [FAIL][38] ([i915#4911]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-glk1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-iclb: [PASS][39] -> [SKIP][40] ([i915#3701])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][41] ([fdo#109271]) +86 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl9/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-kbl: NOTRUN -> [FAIL][42] ([i915#1188])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl3/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-apl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#533])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-apl6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-apl: [PASS][44] -> [DMESG-WARN][45] ([i915#180]) +5 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][46] ([fdo#108145] / [i915#265])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl3/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-skl: NOTRUN -> [FAIL][47] ([fdo#108145] / [i915#265])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][48] ([i915#265])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-skl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#658]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl9/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-apl: NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#658]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-apl6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@kms_psr@psr2_sprite_blt:
- shard-iclb: [PASS][51] -> [SKIP][52] ([fdo#109441]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb1/igt@kms_psr@psr2_sprite_blt.html
* igt@sw_sync@sync_multi_timeline_wait:
- shard-kbl: NOTRUN -> [FAIL][53] ([i915#6140])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl3/igt@sw_sync@sync_multi_timeline_wait.html
* igt@sysfs_clients@fair-1:
- shard-skl: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#2994])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl1/igt@sysfs_clients@fair-1.html
* igt@sysfs_clients@pidname:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#2994])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-apl6/igt@sysfs_clients@pidname.html
#### Possible fixes ####
* igt@gem_exec_balancer@bonded-sync:
- shard-skl: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-skl3/igt@gem_exec_balancer@bonded-sync.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl9/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [SKIP][58] ([i915#4525]) -> [PASS][59] +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb3/igt@gem_exec_balancer@parallel-out-fence.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb1/igt@gem_exec_balancer@parallel-out-fence.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][60] ([i915#454]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][62] ([i915#180]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-apl6/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1:
- shard-apl: [FAIL][64] ([i915#79]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-apl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [DMESG-WARN][66] ([i915#180]) -> [PASS][67] +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-apl8/igt@kms_flip@flip-vs-suspend@a-dp1.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-apl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling:
- shard-iclb: [SKIP][68] ([i915#3701]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
- shard-glk: [FAIL][70] ([i915#4911]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-glk6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][72] ([i915#180]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-skl: [INCOMPLETE][74] ([i915#4939]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-skl10/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-skl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][76] ([fdo#109441]) -> [PASS][77] +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb4/igt@kms_psr@psr2_cursor_blt.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
#### Warnings ####
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][78] ([i915#2852]) -> [FAIL][79] ([i915#2842])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb3/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][80] ([i915#588]) -> [SKIP][81] ([i915#658])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][82] ([i915#658]) -> [SKIP][83] ([i915#2920])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb4/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-iclb: [SKIP][84] ([i915#2920]) -> [SKIP][85] ([fdo#111068] / [i915#658]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb5/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][86] ([fdo#111068] / [i915#658]) -> [SKIP][87] ([i915#2920])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11759/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3070]: https://gitlab.freedesktop.org/drm/intel/issues/3070
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3810]: https://gitlab.freedesktop.org/drm/intel/issues/3810
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4241]: https://gitlab.freedesktop.org/drm/intel/issues/4241
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4818]: https://gitlab.freedesktop.org/drm/intel/issues/4818
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4904]: https://gitlab.freedesktop.org/drm/intel/issues/4904
[i915#4911]: https://gitlab.freedesktop.org/drm/intel/issues/4911
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5264]: https://gitlab.freedesktop.org/drm/intel/issues/5264
[i915#5266]: https://gitlab.freedesktop.org/drm/intel/issues/5266
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5303]: https://gitlab.freedesktop.org/drm/intel/issues/5303
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5507]: https://gitlab.freedesktop.org/drm/intel/issues/5507
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5721]: https://gitlab.freedesktop.org/drm/intel/issues/5721
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#5961]: https://gitlab.freedesktop.org/drm/intel/issues/5961
[i915#5971]: https://gitlab.freedesktop.org/drm/intel/issues/5971
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6140]: https://gitlab.freedesktop.org/drm/intel/issues/6140
[i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11759 -> Patchwork_105142v1
CI-20190529: 20190529
CI_DRM_11759: fa66b647ce886c01bbe1e9f3017a141e90d87539 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6529: b96bf5a0307fc0bdbf6c8e86872817306e102883 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_105142v1: fa66b647ce886c01bbe1e9f3017a141e90d87539 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_105142v1/index.html
[-- Attachment #2: Type: text/html, Size: 28223 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
2022-06-24 4:02 ` Dandamudi, Priyanka
(?)
@ 2022-06-29 6:00 ` Thomas Hellström (Intel)
-1 siblings, 0 replies; 20+ messages in thread
From: Thomas Hellström (Intel) @ 2022-06-29 6:00 UTC (permalink / raw)
To: Dandamudi, Priyanka, Christian König, De Marchi, Lucas,
Bjorn Helgaas
Cc: linux-pci, intel-gfx, Sergei Miroshnichenko, linux-kernel, Auld,
Matthew, Bjorn Helgaas
Hi,
On 6/24/22 06:02, Dandamudi, Priyanka wrote:
>
>> -----Original Message-----
>> From: Christian König <christian.koenig@amd.com>
>> Sent: 18 June 2022 08:45 PM
>> To: De Marchi, Lucas <lucas.demarchi@intel.com>; Bjorn Helgaas
>> <helgaas@kernel.org>
>> Cc: linux-pci@vger.kernel.org; intel-gfx@lists.freedesktop.org; Sergei
>> Miroshnichenko <s.miroshnichenko@yadro.com>; linux-
>> kernel@vger.kernel.org; Dandamudi, Priyanka
>> <priyanka.dandamudi@intel.com>; Auld, Matthew
>> <matthew.auld@intel.com>; Bjorn Helgaas <bhelgaas@google.com>
>> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe
>> resizable bar
>>
>> Am 17.06.22 um 23:27 schrieb Lucas De Marchi:
>>> On Fri, Jun 17, 2022 at 03:32:52PM -0500, Bjorn Helgaas wrote:
>>>> [+cc Christian, author of pci_resize_resource(), Sergei, author of
>>>> rebalancing patches]
>>>>
>>>> Hi Lucas,
>>>>
>>>> On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
>>>>> Cc'ing intel-pci, lkml, Bjorn
>>>>>
>>>>> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
>>>>>> On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
>>>>>>> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>>>>>>>
>>>>>>> Add support for the local memory PICe resizable bar, so that
>>>>>>> local memory can be resized to the maximum size supported by the
>>>>> device,
>>>>>>> and mapped correctly to the PCIe memory bar. It is usual that
>>>>>>> GPU devices expose only 256MB BARs primarily to be compatible
>>>>>>> with
>>>>> 32-bit
>>>>>>> systems. So, those devices cannot claim larger memory BAR
>>>>> windows size due
>>>>>>> to the system BIOS limitation. With this change, it would be
>>>>> possible to
>>>>>>> reprogram the windows of the bridge directly above the
>>>>> requesting device
>>>>>>> on the same BAR type.
>>>>> There is a big caveat here that this may be too late as other
>>>>> drivers may have already mapped their BARs - so probably too late in
>>>>> the pci scan for it to be effective. In fact, after using this for a
>>>>> while, it seems to fail too often, particularly on CFL systems.
>>>> Help me understand the "too late" part. Do you mean that there is
>>>> enough available space for the max BAR size, but it's fragmented and
>>>> therefore not usable? And that if we could do something earlier,
>>>> before drivers have claimed their devices, we might be able to
>>>> compact the BARs of other devices to make a larger contiguous available
>> space?
>>> yes. I will dig some logs I had in the past to confirm.
>>>
>>>
>>>> That is theoretically possible, but I think the current
>>>> pci_resize_resource() only supports resizing of the specified BAR and
>>>> any upstream bridge windows. I don't think it supports moving BARs
>>>> of other devices.
>>>>
>>>> Sergei did some nice work that might help with this situation because
>>>> it can move BARs around more generally. It hasn't quite achieved
>>>> critical mass yet, but maybe this would help get there:
>>>>
>>>>
>>>>
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flor
>>>> e.kernel.org%2Flinux-pci%2F20201218174011.340514-1-
>> s.miroshnichenko%4
>> 0yadro.com%2F&data=05%7C01%7Cchristian.koenig%40amd.com%7C8
>> 096027
>> f68484d0656b108da50a82e7d%7C3dd8961fe4884e608e11a82d994e183d%7C
>> 0%7C0%
>> 7C637910980509199388%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA
>> wMDAiLCJQ
>> IjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&
>> sdata=
>> %2FfntE2FTQ8wmLnz4wnzk94R0GMLEwVs7Mj18%2B9Q6PJk%3D&reser
>> ved=0
>>> oh... I hadn't thought about pause/ioremap/unpause. That looks rad :).
>>> So it seems this would integrate neatly with
>>> pci_resize_resource() (what this patch is doing), as long as drivers
>>> for devices affected implement
>>> .bar_fixed()/.rescan_prepare()/.rescan_done(). That seems it would
>>> solve our issues too.
>> Well we never ran into any of the issues you describe with PCIe BAR resize
>> for GPUs so there must be something you do differently to AMD hardware
>> regarding this.
>>
>> Additional to that keep in mind that you can't resize the BAR before kicking
>> out vgacon/efifb or otherwise it can happen that the just released 256MiB
>> window is still used while you try to resize it. When you do that you usually
>> end up with a hard lockup of the system.
>>
>> Regards,
>> Christian.
>>
>>> thanks
>>> Lucas De Marchi
>>>
>>>> If I understand Sergei's series correctly, this rebalancing actually
>>>> cannot be done during enumeration because we only move BARs if a
>>>> driver for the device indicates that it supports it, so there would
>>>> be no requirement to do this early.
>>>>
>>>>> Do we have any alternative to be done in the PCI subsystem during
>>>>> the scan? There is other work in progress to allow i915 to use the
>>>>> rest of the device memory even with a smaller BAR, but it would be
>>>>> better if we can improve our chances of succeeding the resize.
>>>>>>> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>>>>>>> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
>>>>>>> Cc: Stuart Summers <stuart.summers@intel.com>
>>>>>>> Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
>>>>>>> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>>>>>>> Signed-off-by: Priyanka Dandamudi
>> <priyanka.dandamudi@intel.com>
>>>>>>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>>>>>> Please see
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flo
>> re.kernel.org%2Fr%2F87pmj8vesm.fsf%40intel.com&data=05%7C01%7C
>> ch
>> ristian.koenig%40amd.com%7C8096027f68484d0656b108da50a82e7d%7C3d
>> d896
>> 1fe4884e608e11a82d994e183d%7C0%7C0%7C637910980509199388%7CUnk
>> nown%7C
>> TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL
>> CJX
>> VCI6Mn0%3D%7C3000%7C%7C%7C&sdata=d4cf7HQ6t7y1Xobwjdt8im%
>> 2Fh0E5IZ
>>>>> sXgzQDpsB2vCU4%3D&reserved=0
>>>>>>> ---
>>>>>>> drivers/gpu/drm/i915/i915_driver.c | 92
>>>>> ++++++++++++++++++++++++++++++
>>>>>>> 1 file changed, 92 insertions(+)
>>>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/i915/i915_driver.c
>>>>> b/drivers/gpu/drm/i915/i915_driver.c
>>>>>>> index d26dcca7e654..4bdb471cb2e2 100644
>>>>>>> --- a/drivers/gpu/drm/i915/i915_driver.c
>>>>>>> +++ b/drivers/gpu/drm/i915/i915_driver.c
>>>>>>> @@ -303,6 +303,95 @@ static void sanitize_gpu(struct
>>>>> drm_i915_private *i915)
>>>>>>> __intel_gt_reset(to_gt(i915), ALL_ENGINES);
>>>>>>> }
>>>>>>>
>>>>>>> +static void __release_bars(struct pci_dev *pdev) {
>>>>>>> + int resno;
>>>>>>> +
>>>>>>> + for (resno = PCI_STD_RESOURCES; resno <
>>>>> PCI_STD_RESOURCE_END; resno++) {
>>>>>>> + if (pci_resource_len(pdev, resno))
>>>>>>> + pci_release_resource(pdev, resno);
>>>>>>> + }
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void
>>>>>>> +__resize_bar(struct drm_i915_private *i915, int resno,
>>>>> resource_size_t size)
>>>>>>> +{
>>>>>>> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>>>>>> + int bar_size = pci_rebar_bytes_to_size(size);
>>>>>>> + int ret;
>>>>>>> +
>>>>>>> + __release_bars(pdev);
>>>>>>> +
>>>>>>> + ret = pci_resize_resource(pdev, resno, bar_size);
>>>>>>> + if (ret) {
>>>>>>> + drm_info(&i915->drm, "Failed to resize BAR%d to %dM
>>>>> (%pe)\n",
>>>>>>> + resno, 1 << bar_size, ERR_PTR(ret));
>>>>>>> + return;
>>>>>>> + }
>>>>>>> +
>>>>>>> + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 <<
>>>>> bar_size);
>>>>>>> +}
>>>>>>> +
>>>>>>> +/* BAR size starts from 1MB - 2^20 */ #define BAR_SIZE_SHIFT 20
>>>>>>> +static resource_size_t __lmem_rebar_size(struct
>>>>>>> +drm_i915_private *i915, int resno) {
>>>>>>> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>>>>>> + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
>>>>>>> + resource_size_t size;
>>>>>>> +
>>>>>>> + if (!rebar)
>>>>>>> + return 0;
>>>>>>> +
>>>>>>> + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
>>>>>>> +
>>>>>>> + if (size <= pci_resource_len(pdev, resno))
>>>>>>> + return 0;
>>>>>>> +
>>>>>>> + return size;
>>>>>>> +}
>>>>>>> +
>>>>>>> +#define LMEM_BAR_NUM 2
>>>>>>> +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
>>>>>>> +{
>>>>>>> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>>>>>> + struct pci_bus *root = pdev->bus;
>>>>>>> + struct resource *root_res;
>>>>>>> + resource_size_t rebar_size = __lmem_rebar_size(i915,
>>>>> LMEM_BAR_NUM);
>>>>>>> + u32 pci_cmd;
>>>>>>> + int i;
>>>>>>> +
>>>>>>> + if (!rebar_size)
>>>>>>> + return;
>>>>>>> +
>>>>>>> + /* Find out if root bus contains 64bit memory addressing */
>>>>>>> + while (root->parent)
>>>>>>> + root = root->parent;
>>>>>>> +
>>>>>>> + pci_bus_for_each_resource(root, root_res, i) {
>>>>>>> + if (root_res && root_res->flags & (IORESOURCE_MEM |
>>>>>>> + IORESOURCE_MEM_64) && root_res->start >
>>>>> 0x100000000ull)
>>>>>>> + break;
>>>>>>> + }
>>>>>>> +
>>>>>>> + /* pci_resize_resource will fail anyways */
>>>>>>> + if (!root_res) {
>>>>>>> + drm_info(&i915->drm, "Can't resize LMEM BAR - platform
>>>>> support is missing\n");
>>>>>>> + return;
>>>>>>> + }
>>>>>>> +
>>>>>>> + /* First disable PCI memory decoding references */
>>>>>>> + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
>>>>>>> + pci_write_config_dword(pdev, PCI_COMMAND,
>>>>>>> + pci_cmd & ~PCI_COMMAND_MEMORY);
>>>>>>> +
>>>>>>> + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
>>>>>>> +
>>>>>>> + pci_assign_unassigned_bus_resources(pdev->bus);
>>>>>>> + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); }
>>>>>>> +
>>>>>>> /**
>>>>>>> * i915_driver_early_probe - setup state not requiring device
>>>>> access
>>>>>>> * @dev_priv: device private
>>>>>>> @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev,
>>>>> const struct pci_device_id *ent)
>>>>>>> disable_rpm_wakeref_asserts(&i915->runtime_pm);
>>>>>>>
>>>>>>> + if (HAS_LMEM(i915))
>>>>>>> + i915_resize_lmem_bar(i915);
>>>>>>> +
>>>>>>> intel_vgpu_detect(i915);
>>>>>>>
>>>>>>> ret = intel_gt_probe_all(i915);
>>>>>> --
>>>>>> Jani Nikula, Intel Open Source Graphics Center
> [Dandamudi, Priyanka]
> @De Marchi, Lucas
> Can I proceed with the current approach or is there anything I need to add to it?
IMO we should be good to go. From my understanding, the problem that
Lucas brings up doesn't yet have a solution other than WIP, so if we end
up not being able to resize, we'd fall back to using the small BAR with
Matthew's work.
That said, If we keep hitting errors when resizing, we should, as
Christian says, compare with AMD (since they are not seeing this) and
see what, if anything, can be done differently.
Thanks,
Thomas
^ permalink raw reply [flat|nested] 20+ messages in thread
* RE: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
2022-06-18 15:14 ` Christian König
@ 2022-06-24 4:02 ` Dandamudi, Priyanka
0 siblings, 0 replies; 20+ messages in thread
From: Dandamudi, Priyanka @ 2022-06-24 4:02 UTC (permalink / raw)
To: Christian König, De Marchi, Lucas, Bjorn Helgaas
Cc: linux-pci, intel-gfx, Sergei Miroshnichenko, linux-kernel, Auld,
Matthew, Bjorn Helgaas
> -----Original Message-----
> From: Christian König <christian.koenig@amd.com>
> Sent: 18 June 2022 08:45 PM
> To: De Marchi, Lucas <lucas.demarchi@intel.com>; Bjorn Helgaas
> <helgaas@kernel.org>
> Cc: linux-pci@vger.kernel.org; intel-gfx@lists.freedesktop.org; Sergei
> Miroshnichenko <s.miroshnichenko@yadro.com>; linux-
> kernel@vger.kernel.org; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>; Auld, Matthew
> <matthew.auld@intel.com>; Bjorn Helgaas <bhelgaas@google.com>
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe
> resizable bar
>
> Am 17.06.22 um 23:27 schrieb Lucas De Marchi:
> > On Fri, Jun 17, 2022 at 03:32:52PM -0500, Bjorn Helgaas wrote:
> >> [+cc Christian, author of pci_resize_resource(), Sergei, author of
> >> rebalancing patches]
> >>
> >> Hi Lucas,
> >>
> >> On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
> >>> Cc'ing intel-pci, lkml, Bjorn
> >>>
> >>> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
> >>> > On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
> >>> > > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> >>> > >
> >>> > > Add support for the local memory PICe resizable bar, so that
> >>> > > local memory can be resized to the maximum size supported by the
> >>> device,
> >>> > > and mapped correctly to the PCIe memory bar. It is usual that
> >>> > > GPU devices expose only 256MB BARs primarily to be compatible
> >>> > > with
> >>> 32-bit
> >>> > > systems. So, those devices cannot claim larger memory BAR
> >>> windows size due
> >>> > > to the system BIOS limitation. With this change, it would be
> >>> possible to
> >>> > > reprogram the windows of the bridge directly above the
> >>> requesting device
> >>> > > on the same BAR type.
> >>>
> >>> There is a big caveat here that this may be too late as other
> >>> drivers may have already mapped their BARs - so probably too late in
> >>> the pci scan for it to be effective. In fact, after using this for a
> >>> while, it seems to fail too often, particularly on CFL systems.
> >>
> >> Help me understand the "too late" part. Do you mean that there is
> >> enough available space for the max BAR size, but it's fragmented and
> >> therefore not usable? And that if we could do something earlier,
> >> before drivers have claimed their devices, we might be able to
> >> compact the BARs of other devices to make a larger contiguous available
> space?
> >
> > yes. I will dig some logs I had in the past to confirm.
> >
> >
> >> That is theoretically possible, but I think the current
> >> pci_resize_resource() only supports resizing of the specified BAR and
> >> any upstream bridge windows. I don't think it supports moving BARs
> >> of other devices.
> >>
> >> Sergei did some nice work that might help with this situation because
> >> it can move BARs around more generally. It hasn't quite achieved
> >> critical mass yet, but maybe this would help get there:
> >>
> >>
> >>
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flor
> >> e.kernel.org%2Flinux-pci%2F20201218174011.340514-1-
> s.miroshnichenko%4
> >>
> 0yadro.com%2F&data=05%7C01%7Cchristian.koenig%40amd.com%7C8
> 096027
> >>
> f68484d0656b108da50a82e7d%7C3dd8961fe4884e608e11a82d994e183d%7C
> 0%7C0%
> >>
> 7C637910980509199388%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA
> wMDAiLCJQ
> >>
> IjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&
> sdata=
> >>
> %2FfntE2FTQ8wmLnz4wnzk94R0GMLEwVs7Mj18%2B9Q6PJk%3D&reser
> ved=0
> >>
> >
> > oh... I hadn't thought about pause/ioremap/unpause. That looks rad :).
> > So it seems this would integrate neatly with
> > pci_resize_resource() (what this patch is doing), as long as drivers
> > for devices affected implement
> > .bar_fixed()/.rescan_prepare()/.rescan_done(). That seems it would
> > solve our issues too.
>
> Well we never ran into any of the issues you describe with PCIe BAR resize
> for GPUs so there must be something you do differently to AMD hardware
> regarding this.
>
> Additional to that keep in mind that you can't resize the BAR before kicking
> out vgacon/efifb or otherwise it can happen that the just released 256MiB
> window is still used while you try to resize it. When you do that you usually
> end up with a hard lockup of the system.
>
> Regards,
> Christian.
>
> >
> > thanks
> > Lucas De Marchi
> >
> >>
> >> If I understand Sergei's series correctly, this rebalancing actually
> >> cannot be done during enumeration because we only move BARs if a
> >> driver for the device indicates that it supports it, so there would
> >> be no requirement to do this early.
> >>
> >>> Do we have any alternative to be done in the PCI subsystem during
> >>> the scan? There is other work in progress to allow i915 to use the
> >>> rest of the device memory even with a smaller BAR, but it would be
> >>> better if we can improve our chances of succeeding the resize.
> >>
> >>> > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> >>> > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> >>> > > Cc: Stuart Summers <stuart.summers@intel.com>
> >>> > > Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
> >>> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> >>> > > Signed-off-by: Priyanka Dandamudi
> <priyanka.dandamudi@intel.com>
> >>> > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> >>> >
> >>> > Please see
> >>>
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flo
> >>>
> re.kernel.org%2Fr%2F87pmj8vesm.fsf%40intel.com&data=05%7C01%7C
> ch
> >>>
> ristian.koenig%40amd.com%7C8096027f68484d0656b108da50a82e7d%7C3d
> d896
> >>>
> 1fe4884e608e11a82d994e183d%7C0%7C0%7C637910980509199388%7CUnk
> nown%7C
> >>>
> TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL
> CJX
> >>>
> VCI6Mn0%3D%7C3000%7C%7C%7C&sdata=d4cf7HQ6t7y1Xobwjdt8im%
> 2Fh0E5IZ
> >>> sXgzQDpsB2vCU4%3D&reserved=0
> >>> >
> >>> > > ---
> >>> > > drivers/gpu/drm/i915/i915_driver.c | 92
> >>> ++++++++++++++++++++++++++++++
> >>> > > 1 file changed, 92 insertions(+)
> >>> > >
> >>> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> >>> b/drivers/gpu/drm/i915/i915_driver.c
> >>> > > index d26dcca7e654..4bdb471cb2e2 100644
> >>> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> >>> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> >>> > > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct
> >>> drm_i915_private *i915)
> >>> > > __intel_gt_reset(to_gt(i915), ALL_ENGINES);
> >>> > > }
> >>> > >
> >>> > > +static void __release_bars(struct pci_dev *pdev) {
> >>> > > + int resno;
> >>> > > +
> >>> > > + for (resno = PCI_STD_RESOURCES; resno <
> >>> PCI_STD_RESOURCE_END; resno++) {
> >>> > > + if (pci_resource_len(pdev, resno))
> >>> > > + pci_release_resource(pdev, resno);
> >>> > > + }
> >>> > > +}
> >>> > > +
> >>> > > +static void
> >>> > > +__resize_bar(struct drm_i915_private *i915, int resno,
> >>> resource_size_t size)
> >>> > > +{
> >>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> >>> > > + int bar_size = pci_rebar_bytes_to_size(size);
> >>> > > + int ret;
> >>> > > +
> >>> > > + __release_bars(pdev);
> >>> > > +
> >>> > > + ret = pci_resize_resource(pdev, resno, bar_size);
> >>> > > + if (ret) {
> >>> > > + drm_info(&i915->drm, "Failed to resize BAR%d to %dM
> >>> (%pe)\n",
> >>> > > + resno, 1 << bar_size, ERR_PTR(ret));
> >>> > > + return;
> >>> > > + }
> >>> > > +
> >>> > > + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 <<
> >>> bar_size);
> >>> > > +}
> >>> > > +
> >>> > > +/* BAR size starts from 1MB - 2^20 */ #define BAR_SIZE_SHIFT 20
> >>> > > +static resource_size_t __lmem_rebar_size(struct
> >>> > > +drm_i915_private *i915, int resno) {
> >>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> >>> > > + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> >>> > > + resource_size_t size;
> >>> > > +
> >>> > > + if (!rebar)
> >>> > > + return 0;
> >>> > > +
> >>> > > + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> >>> > > +
> >>> > > + if (size <= pci_resource_len(pdev, resno))
> >>> > > + return 0;
> >>> > > +
> >>> > > + return size;
> >>> > > +}
> >>> > > +
> >>> > > +#define LMEM_BAR_NUM 2
> >>> > > +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> >>> > > +{
> >>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> >>> > > + struct pci_bus *root = pdev->bus;
> >>> > > + struct resource *root_res;
> >>> > > + resource_size_t rebar_size = __lmem_rebar_size(i915,
> >>> LMEM_BAR_NUM);
> >>> > > + u32 pci_cmd;
> >>> > > + int i;
> >>> > > +
> >>> > > + if (!rebar_size)
> >>> > > + return;
> >>> > > +
> >>> > > + /* Find out if root bus contains 64bit memory addressing */
> >>> > > + while (root->parent)
> >>> > > + root = root->parent;
> >>> > > +
> >>> > > + pci_bus_for_each_resource(root, root_res, i) {
> >>> > > + if (root_res && root_res->flags & (IORESOURCE_MEM |
> >>> > > + IORESOURCE_MEM_64) && root_res->start >
> >>> 0x100000000ull)
> >>> > > + break;
> >>> > > + }
> >>> > > +
> >>> > > + /* pci_resize_resource will fail anyways */
> >>> > > + if (!root_res) {
> >>> > > + drm_info(&i915->drm, "Can't resize LMEM BAR - platform
> >>> support is missing\n");
> >>> > > + return;
> >>> > > + }
> >>> > > +
> >>> > > + /* First disable PCI memory decoding references */
> >>> > > + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> >>> > > + pci_write_config_dword(pdev, PCI_COMMAND,
> >>> > > + pci_cmd & ~PCI_COMMAND_MEMORY);
> >>> > > +
> >>> > > + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> >>> > > +
> >>> > > + pci_assign_unassigned_bus_resources(pdev->bus);
> >>> > > + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); }
> >>> > > +
> >>> > > /**
> >>> > > * i915_driver_early_probe - setup state not requiring device
> >>> access
> >>> > > * @dev_priv: device private
> >>> > > @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev,
> >>> const struct pci_device_id *ent)
> >>> > >
> >>> > > disable_rpm_wakeref_asserts(&i915->runtime_pm);
> >>> > >
> >>> > > + if (HAS_LMEM(i915))
> >>> > > + i915_resize_lmem_bar(i915);
> >>> > > +
> >>> > > intel_vgpu_detect(i915);
> >>> > >
> >>> > > ret = intel_gt_probe_all(i915);
> >>> >
> >>> > --
> >>> > Jani Nikula, Intel Open Source Graphics Center
[Dandamudi, Priyanka]
@De Marchi, Lucas
Can I proceed with the current approach or is there anything I need to add to it?
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
@ 2022-06-24 4:02 ` Dandamudi, Priyanka
0 siblings, 0 replies; 20+ messages in thread
From: Dandamudi, Priyanka @ 2022-06-24 4:02 UTC (permalink / raw)
To: Christian König, De Marchi, Lucas, Bjorn Helgaas
Cc: linux-pci, intel-gfx, Sergei Miroshnichenko, linux-kernel, Auld,
Matthew, Bjorn Helgaas
> -----Original Message-----
> From: Christian König <christian.koenig@amd.com>
> Sent: 18 June 2022 08:45 PM
> To: De Marchi, Lucas <lucas.demarchi@intel.com>; Bjorn Helgaas
> <helgaas@kernel.org>
> Cc: linux-pci@vger.kernel.org; intel-gfx@lists.freedesktop.org; Sergei
> Miroshnichenko <s.miroshnichenko@yadro.com>; linux-
> kernel@vger.kernel.org; Dandamudi, Priyanka
> <priyanka.dandamudi@intel.com>; Auld, Matthew
> <matthew.auld@intel.com>; Bjorn Helgaas <bhelgaas@google.com>
> Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe
> resizable bar
>
> Am 17.06.22 um 23:27 schrieb Lucas De Marchi:
> > On Fri, Jun 17, 2022 at 03:32:52PM -0500, Bjorn Helgaas wrote:
> >> [+cc Christian, author of pci_resize_resource(), Sergei, author of
> >> rebalancing patches]
> >>
> >> Hi Lucas,
> >>
> >> On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
> >>> Cc'ing intel-pci, lkml, Bjorn
> >>>
> >>> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
> >>> > On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
> >>> > > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> >>> > >
> >>> > > Add support for the local memory PICe resizable bar, so that
> >>> > > local memory can be resized to the maximum size supported by the
> >>> device,
> >>> > > and mapped correctly to the PCIe memory bar. It is usual that
> >>> > > GPU devices expose only 256MB BARs primarily to be compatible
> >>> > > with
> >>> 32-bit
> >>> > > systems. So, those devices cannot claim larger memory BAR
> >>> windows size due
> >>> > > to the system BIOS limitation. With this change, it would be
> >>> possible to
> >>> > > reprogram the windows of the bridge directly above the
> >>> requesting device
> >>> > > on the same BAR type.
> >>>
> >>> There is a big caveat here that this may be too late as other
> >>> drivers may have already mapped their BARs - so probably too late in
> >>> the pci scan for it to be effective. In fact, after using this for a
> >>> while, it seems to fail too often, particularly on CFL systems.
> >>
> >> Help me understand the "too late" part. Do you mean that there is
> >> enough available space for the max BAR size, but it's fragmented and
> >> therefore not usable? And that if we could do something earlier,
> >> before drivers have claimed their devices, we might be able to
> >> compact the BARs of other devices to make a larger contiguous available
> space?
> >
> > yes. I will dig some logs I had in the past to confirm.
> >
> >
> >> That is theoretically possible, but I think the current
> >> pci_resize_resource() only supports resizing of the specified BAR and
> >> any upstream bridge windows. I don't think it supports moving BARs
> >> of other devices.
> >>
> >> Sergei did some nice work that might help with this situation because
> >> it can move BARs around more generally. It hasn't quite achieved
> >> critical mass yet, but maybe this would help get there:
> >>
> >>
> >>
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flor
> >> e.kernel.org%2Flinux-pci%2F20201218174011.340514-1-
> s.miroshnichenko%4
> >>
> 0yadro.com%2F&data=05%7C01%7Cchristian.koenig%40amd.com%7C8
> 096027
> >>
> f68484d0656b108da50a82e7d%7C3dd8961fe4884e608e11a82d994e183d%7C
> 0%7C0%
> >>
> 7C637910980509199388%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA
> wMDAiLCJQ
> >>
> IjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&
> sdata=
> >>
> %2FfntE2FTQ8wmLnz4wnzk94R0GMLEwVs7Mj18%2B9Q6PJk%3D&reser
> ved=0
> >>
> >
> > oh... I hadn't thought about pause/ioremap/unpause. That looks rad :).
> > So it seems this would integrate neatly with
> > pci_resize_resource() (what this patch is doing), as long as drivers
> > for devices affected implement
> > .bar_fixed()/.rescan_prepare()/.rescan_done(). That seems it would
> > solve our issues too.
>
> Well we never ran into any of the issues you describe with PCIe BAR resize
> for GPUs so there must be something you do differently to AMD hardware
> regarding this.
>
> Additional to that keep in mind that you can't resize the BAR before kicking
> out vgacon/efifb or otherwise it can happen that the just released 256MiB
> window is still used while you try to resize it. When you do that you usually
> end up with a hard lockup of the system.
>
> Regards,
> Christian.
>
> >
> > thanks
> > Lucas De Marchi
> >
> >>
> >> If I understand Sergei's series correctly, this rebalancing actually
> >> cannot be done during enumeration because we only move BARs if a
> >> driver for the device indicates that it supports it, so there would
> >> be no requirement to do this early.
> >>
> >>> Do we have any alternative to be done in the PCI subsystem during
> >>> the scan? There is other work in progress to allow i915 to use the
> >>> rest of the device memory even with a smaller BAR, but it would be
> >>> better if we can improve our chances of succeeding the resize.
> >>
> >>> > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> >>> > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> >>> > > Cc: Stuart Summers <stuart.summers@intel.com>
> >>> > > Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
> >>> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> >>> > > Signed-off-by: Priyanka Dandamudi
> <priyanka.dandamudi@intel.com>
> >>> > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> >>> >
> >>> > Please see
> >>>
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flo
> >>>
> re.kernel.org%2Fr%2F87pmj8vesm.fsf%40intel.com&data=05%7C01%7C
> ch
> >>>
> ristian.koenig%40amd.com%7C8096027f68484d0656b108da50a82e7d%7C3d
> d896
> >>>
> 1fe4884e608e11a82d994e183d%7C0%7C0%7C637910980509199388%7CUnk
> nown%7C
> >>>
> TWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiL
> CJX
> >>>
> VCI6Mn0%3D%7C3000%7C%7C%7C&sdata=d4cf7HQ6t7y1Xobwjdt8im%
> 2Fh0E5IZ
> >>> sXgzQDpsB2vCU4%3D&reserved=0
> >>> >
> >>> > > ---
> >>> > > drivers/gpu/drm/i915/i915_driver.c | 92
> >>> ++++++++++++++++++++++++++++++
> >>> > > 1 file changed, 92 insertions(+)
> >>> > >
> >>> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c
> >>> b/drivers/gpu/drm/i915/i915_driver.c
> >>> > > index d26dcca7e654..4bdb471cb2e2 100644
> >>> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> >>> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> >>> > > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct
> >>> drm_i915_private *i915)
> >>> > > __intel_gt_reset(to_gt(i915), ALL_ENGINES);
> >>> > > }
> >>> > >
> >>> > > +static void __release_bars(struct pci_dev *pdev) {
> >>> > > + int resno;
> >>> > > +
> >>> > > + for (resno = PCI_STD_RESOURCES; resno <
> >>> PCI_STD_RESOURCE_END; resno++) {
> >>> > > + if (pci_resource_len(pdev, resno))
> >>> > > + pci_release_resource(pdev, resno);
> >>> > > + }
> >>> > > +}
> >>> > > +
> >>> > > +static void
> >>> > > +__resize_bar(struct drm_i915_private *i915, int resno,
> >>> resource_size_t size)
> >>> > > +{
> >>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> >>> > > + int bar_size = pci_rebar_bytes_to_size(size);
> >>> > > + int ret;
> >>> > > +
> >>> > > + __release_bars(pdev);
> >>> > > +
> >>> > > + ret = pci_resize_resource(pdev, resno, bar_size);
> >>> > > + if (ret) {
> >>> > > + drm_info(&i915->drm, "Failed to resize BAR%d to %dM
> >>> (%pe)\n",
> >>> > > + resno, 1 << bar_size, ERR_PTR(ret));
> >>> > > + return;
> >>> > > + }
> >>> > > +
> >>> > > + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 <<
> >>> bar_size);
> >>> > > +}
> >>> > > +
> >>> > > +/* BAR size starts from 1MB - 2^20 */ #define BAR_SIZE_SHIFT 20
> >>> > > +static resource_size_t __lmem_rebar_size(struct
> >>> > > +drm_i915_private *i915, int resno) {
> >>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> >>> > > + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> >>> > > + resource_size_t size;
> >>> > > +
> >>> > > + if (!rebar)
> >>> > > + return 0;
> >>> > > +
> >>> > > + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> >>> > > +
> >>> > > + if (size <= pci_resource_len(pdev, resno))
> >>> > > + return 0;
> >>> > > +
> >>> > > + return size;
> >>> > > +}
> >>> > > +
> >>> > > +#define LMEM_BAR_NUM 2
> >>> > > +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> >>> > > +{
> >>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> >>> > > + struct pci_bus *root = pdev->bus;
> >>> > > + struct resource *root_res;
> >>> > > + resource_size_t rebar_size = __lmem_rebar_size(i915,
> >>> LMEM_BAR_NUM);
> >>> > > + u32 pci_cmd;
> >>> > > + int i;
> >>> > > +
> >>> > > + if (!rebar_size)
> >>> > > + return;
> >>> > > +
> >>> > > + /* Find out if root bus contains 64bit memory addressing */
> >>> > > + while (root->parent)
> >>> > > + root = root->parent;
> >>> > > +
> >>> > > + pci_bus_for_each_resource(root, root_res, i) {
> >>> > > + if (root_res && root_res->flags & (IORESOURCE_MEM |
> >>> > > + IORESOURCE_MEM_64) && root_res->start >
> >>> 0x100000000ull)
> >>> > > + break;
> >>> > > + }
> >>> > > +
> >>> > > + /* pci_resize_resource will fail anyways */
> >>> > > + if (!root_res) {
> >>> > > + drm_info(&i915->drm, "Can't resize LMEM BAR - platform
> >>> support is missing\n");
> >>> > > + return;
> >>> > > + }
> >>> > > +
> >>> > > + /* First disable PCI memory decoding references */
> >>> > > + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> >>> > > + pci_write_config_dword(pdev, PCI_COMMAND,
> >>> > > + pci_cmd & ~PCI_COMMAND_MEMORY);
> >>> > > +
> >>> > > + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> >>> > > +
> >>> > > + pci_assign_unassigned_bus_resources(pdev->bus);
> >>> > > + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd); }
> >>> > > +
> >>> > > /**
> >>> > > * i915_driver_early_probe - setup state not requiring device
> >>> access
> >>> > > * @dev_priv: device private
> >>> > > @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev,
> >>> const struct pci_device_id *ent)
> >>> > >
> >>> > > disable_rpm_wakeref_asserts(&i915->runtime_pm);
> >>> > >
> >>> > > + if (HAS_LMEM(i915))
> >>> > > + i915_resize_lmem_bar(i915);
> >>> > > +
> >>> > > intel_vgpu_detect(i915);
> >>> > >
> >>> > > ret = intel_gt_probe_all(i915);
> >>> >
> >>> > --
> >>> > Jani Nikula, Intel Open Source Graphics Center
[Dandamudi, Priyanka]
@De Marchi, Lucas
Can I proceed with the current approach or is there anything I need to add to it?
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
2022-06-17 21:27 ` Lucas De Marchi
@ 2022-06-18 15:14 ` Christian König
2022-06-24 4:02 ` Dandamudi, Priyanka
0 siblings, 1 reply; 20+ messages in thread
From: Christian König @ 2022-06-18 15:14 UTC (permalink / raw)
To: Lucas De Marchi, Bjorn Helgaas
Cc: linux-pci, intel-gfx, Sergei Miroshnichenko, linux-kernel,
priyanka.dandamudi, matthew.auld, Bjorn Helgaas
Am 17.06.22 um 23:27 schrieb Lucas De Marchi:
> On Fri, Jun 17, 2022 at 03:32:52PM -0500, Bjorn Helgaas wrote:
>> [+cc Christian, author of pci_resize_resource(), Sergei, author of
>> rebalancing patches]
>>
>> Hi Lucas,
>>
>> On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
>>> Cc'ing intel-pci, lkml, Bjorn
>>>
>>> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
>>> > On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
>>> > > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>>> > >
>>> > > Add support for the local memory PICe resizable bar, so that
>>> > > local memory can be resized to the maximum size supported by the
>>> device,
>>> > > and mapped correctly to the PCIe memory bar. It is usual that GPU
>>> > > devices expose only 256MB BARs primarily to be compatible with
>>> 32-bit
>>> > > systems. So, those devices cannot claim larger memory BAR
>>> windows size due
>>> > > to the system BIOS limitation. With this change, it would be
>>> possible to
>>> > > reprogram the windows of the bridge directly above the
>>> requesting device
>>> > > on the same BAR type.
>>>
>>> There is a big caveat here that this may be too late as other drivers
>>> may have already mapped their BARs - so probably too late in the pci
>>> scan
>>> for it to be effective. In fact, after using this for a while, it seems
>>> to fail too often, particularly on CFL systems.
>>
>> Help me understand the "too late" part. Do you mean that there is
>> enough available space for the max BAR size, but it's fragmented and
>> therefore not usable? And that if we could do something earlier,
>> before drivers have claimed their devices, we might be able to compact
>> the BARs of other devices to make a larger contiguous available space?
>
> yes. I will dig some logs I had in the past to confirm.
>
>
>> That is theoretically possible, but I think the current
>> pci_resize_resource() only supports resizing of the specified BAR and
>> any upstream bridge windows. I don't think it supports moving BARs of
>> other devices.
>>
>> Sergei did some nice work that might help with this situation because
>> it can move BARs around more generally. It hasn't quite achieved
>> critical mass yet, but maybe this would help get there:
>>
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Flinux-pci%2F20201218174011.340514-1-s.miroshnichenko%40yadro.com%2F&data=05%7C01%7Cchristian.koenig%40amd.com%7C8096027f68484d0656b108da50a82e7d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637910980509199388%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=%2FfntE2FTQ8wmLnz4wnzk94R0GMLEwVs7Mj18%2B9Q6PJk%3D&reserved=0
>>
>
> oh... I hadn't thought about pause/ioremap/unpause. That looks rad :).
> So it seems this would integrate neatly with
> pci_resize_resource() (what this patch is doing), as long as drivers for
> devices affected implement
> .bar_fixed()/.rescan_prepare()/.rescan_done(). That seems it would solve
> our issues too.
Well we never ran into any of the issues you describe with PCIe BAR
resize for GPUs so there must be something you do differently to AMD
hardware regarding this.
Additional to that keep in mind that you can't resize the BAR before
kicking out vgacon/efifb or otherwise it can happen that the just
released 256MiB window is still used while you try to resize it. When
you do that you usually end up with a hard lockup of the system.
Regards,
Christian.
>
> thanks
> Lucas De Marchi
>
>>
>> If I understand Sergei's series correctly, this rebalancing actually
>> cannot be done during enumeration because we only move BARs if a
>> driver for the device indicates that it supports it, so there would be
>> no requirement to do this early.
>>
>>> Do we have any alternative to be done in the PCI subsystem during the
>>> scan? There is other work in progress to allow i915 to use the rest of
>>> the device memory even with a smaller BAR, but it would be better if we
>>> can improve our chances of succeeding the resize.
>>
>>> > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>>> > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
>>> > > Cc: Stuart Summers <stuart.summers@intel.com>
>>> > > Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
>>> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>>> > > Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>>> > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>>> >
>>> > Please see
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fr%2F87pmj8vesm.fsf%40intel.com&data=05%7C01%7Cchristian.koenig%40amd.com%7C8096027f68484d0656b108da50a82e7d%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637910980509199388%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=d4cf7HQ6t7y1Xobwjdt8im%2Fh0E5IZsXgzQDpsB2vCU4%3D&reserved=0
>>> >
>>> > > ---
>>> > > drivers/gpu/drm/i915/i915_driver.c | 92
>>> ++++++++++++++++++++++++++++++
>>> > > 1 file changed, 92 insertions(+)
>>> > >
>>> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c
>>> b/drivers/gpu/drm/i915/i915_driver.c
>>> > > index d26dcca7e654..4bdb471cb2e2 100644
>>> > > --- a/drivers/gpu/drm/i915/i915_driver.c
>>> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
>>> > > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct
>>> drm_i915_private *i915)
>>> > > __intel_gt_reset(to_gt(i915), ALL_ENGINES);
>>> > > }
>>> > >
>>> > > +static void __release_bars(struct pci_dev *pdev)
>>> > > +{
>>> > > + int resno;
>>> > > +
>>> > > + for (resno = PCI_STD_RESOURCES; resno <
>>> PCI_STD_RESOURCE_END; resno++) {
>>> > > + if (pci_resource_len(pdev, resno))
>>> > > + pci_release_resource(pdev, resno);
>>> > > + }
>>> > > +}
>>> > > +
>>> > > +static void
>>> > > +__resize_bar(struct drm_i915_private *i915, int resno,
>>> resource_size_t size)
>>> > > +{
>>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>> > > + int bar_size = pci_rebar_bytes_to_size(size);
>>> > > + int ret;
>>> > > +
>>> > > + __release_bars(pdev);
>>> > > +
>>> > > + ret = pci_resize_resource(pdev, resno, bar_size);
>>> > > + if (ret) {
>>> > > + drm_info(&i915->drm, "Failed to resize BAR%d to %dM
>>> (%pe)\n",
>>> > > + resno, 1 << bar_size, ERR_PTR(ret));
>>> > > + return;
>>> > > + }
>>> > > +
>>> > > + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 <<
>>> bar_size);
>>> > > +}
>>> > > +
>>> > > +/* BAR size starts from 1MB - 2^20 */
>>> > > +#define BAR_SIZE_SHIFT 20
>>> > > +static resource_size_t
>>> > > +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
>>> > > +{
>>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>> > > + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
>>> > > + resource_size_t size;
>>> > > +
>>> > > + if (!rebar)
>>> > > + return 0;
>>> > > +
>>> > > + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
>>> > > +
>>> > > + if (size <= pci_resource_len(pdev, resno))
>>> > > + return 0;
>>> > > +
>>> > > + return size;
>>> > > +}
>>> > > +
>>> > > +#define LMEM_BAR_NUM 2
>>> > > +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
>>> > > +{
>>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>>> > > + struct pci_bus *root = pdev->bus;
>>> > > + struct resource *root_res;
>>> > > + resource_size_t rebar_size = __lmem_rebar_size(i915,
>>> LMEM_BAR_NUM);
>>> > > + u32 pci_cmd;
>>> > > + int i;
>>> > > +
>>> > > + if (!rebar_size)
>>> > > + return;
>>> > > +
>>> > > + /* Find out if root bus contains 64bit memory addressing */
>>> > > + while (root->parent)
>>> > > + root = root->parent;
>>> > > +
>>> > > + pci_bus_for_each_resource(root, root_res, i) {
>>> > > + if (root_res && root_res->flags & (IORESOURCE_MEM |
>>> > > + IORESOURCE_MEM_64) && root_res->start >
>>> 0x100000000ull)
>>> > > + break;
>>> > > + }
>>> > > +
>>> > > + /* pci_resize_resource will fail anyways */
>>> > > + if (!root_res) {
>>> > > + drm_info(&i915->drm, "Can't resize LMEM BAR - platform
>>> support is missing\n");
>>> > > + return;
>>> > > + }
>>> > > +
>>> > > + /* First disable PCI memory decoding references */
>>> > > + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
>>> > > + pci_write_config_dword(pdev, PCI_COMMAND,
>>> > > + pci_cmd & ~PCI_COMMAND_MEMORY);
>>> > > +
>>> > > + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
>>> > > +
>>> > > + pci_assign_unassigned_bus_resources(pdev->bus);
>>> > > + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
>>> > > +}
>>> > > +
>>> > > /**
>>> > > * i915_driver_early_probe - setup state not requiring device
>>> access
>>> > > * @dev_priv: device private
>>> > > @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev,
>>> const struct pci_device_id *ent)
>>> > >
>>> > > disable_rpm_wakeref_asserts(&i915->runtime_pm);
>>> > >
>>> > > + if (HAS_LMEM(i915))
>>> > > + i915_resize_lmem_bar(i915);
>>> > > +
>>> > > intel_vgpu_detect(i915);
>>> > >
>>> > > ret = intel_gt_probe_all(i915);
>>> >
>>> > --
>>> > Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
2022-06-17 20:32 ` Bjorn Helgaas
(?)
@ 2022-06-17 21:27 ` Lucas De Marchi
2022-06-18 15:14 ` Christian König
-1 siblings, 1 reply; 20+ messages in thread
From: Lucas De Marchi @ 2022-06-17 21:27 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-pci, intel-gfx, Sergei Miroshnichenko, linux-kernel,
priyanka.dandamudi, matthew.auld, Bjorn Helgaas,
Christian König
On Fri, Jun 17, 2022 at 03:32:52PM -0500, Bjorn Helgaas wrote:
>[+cc Christian, author of pci_resize_resource(), Sergei, author of
>rebalancing patches]
>
>Hi Lucas,
>
>On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
>> Cc'ing intel-pci, lkml, Bjorn
>>
>> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
>> > On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
>> > > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>> > >
>> > > Add support for the local memory PICe resizable bar, so that
>> > > local memory can be resized to the maximum size supported by the device,
>> > > and mapped correctly to the PCIe memory bar. It is usual that GPU
>> > > devices expose only 256MB BARs primarily to be compatible with 32-bit
>> > > systems. So, those devices cannot claim larger memory BAR windows size due
>> > > to the system BIOS limitation. With this change, it would be possible to
>> > > reprogram the windows of the bridge directly above the requesting device
>> > > on the same BAR type.
>>
>> There is a big caveat here that this may be too late as other drivers
>> may have already mapped their BARs - so probably too late in the pci scan
>> for it to be effective. In fact, after using this for a while, it seems
>> to fail too often, particularly on CFL systems.
>
>Help me understand the "too late" part. Do you mean that there is
>enough available space for the max BAR size, but it's fragmented and
>therefore not usable? And that if we could do something earlier,
>before drivers have claimed their devices, we might be able to compact
>the BARs of other devices to make a larger contiguous available space?
yes. I will dig some logs I had in the past to confirm.
>That is theoretically possible, but I think the current
>pci_resize_resource() only supports resizing of the specified BAR and
>any upstream bridge windows. I don't think it supports moving BARs of
>other devices.
>
>Sergei did some nice work that might help with this situation because
>it can move BARs around more generally. It hasn't quite achieved
>critical mass yet, but maybe this would help get there:
>
> https://lore.kernel.org/linux-pci/20201218174011.340514-1-s.miroshnichenko@yadro.com/
oh... I hadn't thought about pause/ioremap/unpause. That looks rad :).
So it seems this would integrate neatly with
pci_resize_resource() (what this patch is doing), as long as drivers for
devices affected implement
.bar_fixed()/.rescan_prepare()/.rescan_done(). That seems it would solve
our issues too.
thanks
Lucas De Marchi
>
>If I understand Sergei's series correctly, this rebalancing actually
>cannot be done during enumeration because we only move BARs if a
>driver for the device indicates that it supports it, so there would be
>no requirement to do this early.
>
>> Do we have any alternative to be done in the PCI subsystem during the
>> scan? There is other work in progress to allow i915 to use the rest of
>> the device memory even with a smaller BAR, but it would be better if we
>> can improve our chances of succeeding the resize.
>
>> > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>> > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
>> > > Cc: Stuart Summers <stuart.summers@intel.com>
>> > > Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
>> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>> > > Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>> > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>> >
>> > Please see https://lore.kernel.org/r/87pmj8vesm.fsf@intel.com
>> >
>> > > ---
>> > > drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
>> > > 1 file changed, 92 insertions(+)
>> > >
>> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
>> > > index d26dcca7e654..4bdb471cb2e2 100644
>> > > --- a/drivers/gpu/drm/i915/i915_driver.c
>> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
>> > > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
>> > > __intel_gt_reset(to_gt(i915), ALL_ENGINES);
>> > > }
>> > >
>> > > +static void __release_bars(struct pci_dev *pdev)
>> > > +{
>> > > + int resno;
>> > > +
>> > > + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
>> > > + if (pci_resource_len(pdev, resno))
>> > > + pci_release_resource(pdev, resno);
>> > > + }
>> > > +}
>> > > +
>> > > +static void
>> > > +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
>> > > +{
>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> > > + int bar_size = pci_rebar_bytes_to_size(size);
>> > > + int ret;
>> > > +
>> > > + __release_bars(pdev);
>> > > +
>> > > + ret = pci_resize_resource(pdev, resno, bar_size);
>> > > + if (ret) {
>> > > + drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
>> > > + resno, 1 << bar_size, ERR_PTR(ret));
>> > > + return;
>> > > + }
>> > > +
>> > > + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
>> > > +}
>> > > +
>> > > +/* BAR size starts from 1MB - 2^20 */
>> > > +#define BAR_SIZE_SHIFT 20
>> > > +static resource_size_t
>> > > +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
>> > > +{
>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> > > + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
>> > > + resource_size_t size;
>> > > +
>> > > + if (!rebar)
>> > > + return 0;
>> > > +
>> > > + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
>> > > +
>> > > + if (size <= pci_resource_len(pdev, resno))
>> > > + return 0;
>> > > +
>> > > + return size;
>> > > +}
>> > > +
>> > > +#define LMEM_BAR_NUM 2
>> > > +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
>> > > +{
>> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> > > + struct pci_bus *root = pdev->bus;
>> > > + struct resource *root_res;
>> > > + resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
>> > > + u32 pci_cmd;
>> > > + int i;
>> > > +
>> > > + if (!rebar_size)
>> > > + return;
>> > > +
>> > > + /* Find out if root bus contains 64bit memory addressing */
>> > > + while (root->parent)
>> > > + root = root->parent;
>> > > +
>> > > + pci_bus_for_each_resource(root, root_res, i) {
>> > > + if (root_res && root_res->flags & (IORESOURCE_MEM |
>> > > + IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
>> > > + break;
>> > > + }
>> > > +
>> > > + /* pci_resize_resource will fail anyways */
>> > > + if (!root_res) {
>> > > + drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
>> > > + return;
>> > > + }
>> > > +
>> > > + /* First disable PCI memory decoding references */
>> > > + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
>> > > + pci_write_config_dword(pdev, PCI_COMMAND,
>> > > + pci_cmd & ~PCI_COMMAND_MEMORY);
>> > > +
>> > > + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
>> > > +
>> > > + pci_assign_unassigned_bus_resources(pdev->bus);
>> > > + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
>> > > +}
>> > > +
>> > > /**
>> > > * i915_driver_early_probe - setup state not requiring device access
>> > > * @dev_priv: device private
>> > > @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>> > >
>> > > disable_rpm_wakeref_asserts(&i915->runtime_pm);
>> > >
>> > > + if (HAS_LMEM(i915))
>> > > + i915_resize_lmem_bar(i915);
>> > > +
>> > > intel_vgpu_detect(i915);
>> > >
>> > > ret = intel_gt_probe_all(i915);
>> >
>> > --
>> > Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
2022-06-17 18:44 ` Lucas De Marchi
@ 2022-06-17 20:32 ` Bjorn Helgaas
-1 siblings, 0 replies; 20+ messages in thread
From: Bjorn Helgaas @ 2022-06-17 20:32 UTC (permalink / raw)
To: Lucas De Marchi
Cc: Jani Nikula, linux-pci, intel-gfx, linux-kernel,
priyanka.dandamudi, matthew.auld, Bjorn Helgaas,
Christian König, Sergei Miroshnichenko
[+cc Christian, author of pci_resize_resource(), Sergei, author of
rebalancing patches]
Hi Lucas,
On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
> Cc'ing intel-pci, lkml, Bjorn
>
> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
> > On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
> > > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> > >
> > > Add support for the local memory PICe resizable bar, so that
> > > local memory can be resized to the maximum size supported by the device,
> > > and mapped correctly to the PCIe memory bar. It is usual that GPU
> > > devices expose only 256MB BARs primarily to be compatible with 32-bit
> > > systems. So, those devices cannot claim larger memory BAR windows size due
> > > to the system BIOS limitation. With this change, it would be possible to
> > > reprogram the windows of the bridge directly above the requesting device
> > > on the same BAR type.
>
> There is a big caveat here that this may be too late as other drivers
> may have already mapped their BARs - so probably too late in the pci scan
> for it to be effective. In fact, after using this for a while, it seems
> to fail too often, particularly on CFL systems.
Help me understand the "too late" part. Do you mean that there is
enough available space for the max BAR size, but it's fragmented and
therefore not usable? And that if we could do something earlier,
before drivers have claimed their devices, we might be able to compact
the BARs of other devices to make a larger contiguous available space?
That is theoretically possible, but I think the current
pci_resize_resource() only supports resizing of the specified BAR and
any upstream bridge windows. I don't think it supports moving BARs of
other devices.
Sergei did some nice work that might help with this situation because
it can move BARs around more generally. It hasn't quite achieved
critical mass yet, but maybe this would help get there:
https://lore.kernel.org/linux-pci/20201218174011.340514-1-s.miroshnichenko@yadro.com/
If I understand Sergei's series correctly, this rebalancing actually
cannot be done during enumeration because we only move BARs if a
driver for the device indicates that it supports it, so there would be
no requirement to do this early.
> Do we have any alternative to be done in the PCI subsystem during the
> scan? There is other work in progress to allow i915 to use the rest of
> the device memory even with a smaller BAR, but it would be better if we
> can improve our chances of succeeding the resize.
> > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> > > Cc: Stuart Summers <stuart.summers@intel.com>
> > > Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> > > Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> >
> > Please see https://lore.kernel.org/r/87pmj8vesm.fsf@intel.com
> >
> > > ---
> > > drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
> > > 1 file changed, 92 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > > index d26dcca7e654..4bdb471cb2e2 100644
> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
> > > __intel_gt_reset(to_gt(i915), ALL_ENGINES);
> > > }
> > >
> > > +static void __release_bars(struct pci_dev *pdev)
> > > +{
> > > + int resno;
> > > +
> > > + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
> > > + if (pci_resource_len(pdev, resno))
> > > + pci_release_resource(pdev, resno);
> > > + }
> > > +}
> > > +
> > > +static void
> > > +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
> > > +{
> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > + int bar_size = pci_rebar_bytes_to_size(size);
> > > + int ret;
> > > +
> > > + __release_bars(pdev);
> > > +
> > > + ret = pci_resize_resource(pdev, resno, bar_size);
> > > + if (ret) {
> > > + drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
> > > + resno, 1 << bar_size, ERR_PTR(ret));
> > > + return;
> > > + }
> > > +
> > > + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> > > +}
> > > +
> > > +/* BAR size starts from 1MB - 2^20 */
> > > +#define BAR_SIZE_SHIFT 20
> > > +static resource_size_t
> > > +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
> > > +{
> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> > > + resource_size_t size;
> > > +
> > > + if (!rebar)
> > > + return 0;
> > > +
> > > + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> > > +
> > > + if (size <= pci_resource_len(pdev, resno))
> > > + return 0;
> > > +
> > > + return size;
> > > +}
> > > +
> > > +#define LMEM_BAR_NUM 2
> > > +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> > > +{
> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > + struct pci_bus *root = pdev->bus;
> > > + struct resource *root_res;
> > > + resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
> > > + u32 pci_cmd;
> > > + int i;
> > > +
> > > + if (!rebar_size)
> > > + return;
> > > +
> > > + /* Find out if root bus contains 64bit memory addressing */
> > > + while (root->parent)
> > > + root = root->parent;
> > > +
> > > + pci_bus_for_each_resource(root, root_res, i) {
> > > + if (root_res && root_res->flags & (IORESOURCE_MEM |
> > > + IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
> > > + break;
> > > + }
> > > +
> > > + /* pci_resize_resource will fail anyways */
> > > + if (!root_res) {
> > > + drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
> > > + return;
> > > + }
> > > +
> > > + /* First disable PCI memory decoding references */
> > > + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> > > + pci_write_config_dword(pdev, PCI_COMMAND,
> > > + pci_cmd & ~PCI_COMMAND_MEMORY);
> > > +
> > > + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> > > +
> > > + pci_assign_unassigned_bus_resources(pdev->bus);
> > > + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> > > +}
> > > +
> > > /**
> > > * i915_driver_early_probe - setup state not requiring device access
> > > * @dev_priv: device private
> > > @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> > >
> > > disable_rpm_wakeref_asserts(&i915->runtime_pm);
> > >
> > > + if (HAS_LMEM(i915))
> > > + i915_resize_lmem_bar(i915);
> > > +
> > > intel_vgpu_detect(i915);
> > >
> > > ret = intel_gt_probe_all(i915);
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
@ 2022-06-17 20:32 ` Bjorn Helgaas
0 siblings, 0 replies; 20+ messages in thread
From: Bjorn Helgaas @ 2022-06-17 20:32 UTC (permalink / raw)
To: Lucas De Marchi
Cc: linux-pci, intel-gfx, Sergei Miroshnichenko, linux-kernel,
priyanka.dandamudi, matthew.auld, Bjorn Helgaas,
Christian König
[+cc Christian, author of pci_resize_resource(), Sergei, author of
rebalancing patches]
Hi Lucas,
On Fri, Jun 17, 2022 at 11:44:41AM -0700, Lucas De Marchi wrote:
> Cc'ing intel-pci, lkml, Bjorn
>
> On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
> > On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
> > > From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> > >
> > > Add support for the local memory PICe resizable bar, so that
> > > local memory can be resized to the maximum size supported by the device,
> > > and mapped correctly to the PCIe memory bar. It is usual that GPU
> > > devices expose only 256MB BARs primarily to be compatible with 32-bit
> > > systems. So, those devices cannot claim larger memory BAR windows size due
> > > to the system BIOS limitation. With this change, it would be possible to
> > > reprogram the windows of the bridge directly above the requesting device
> > > on the same BAR type.
>
> There is a big caveat here that this may be too late as other drivers
> may have already mapped their BARs - so probably too late in the pci scan
> for it to be effective. In fact, after using this for a while, it seems
> to fail too often, particularly on CFL systems.
Help me understand the "too late" part. Do you mean that there is
enough available space for the max BAR size, but it's fragmented and
therefore not usable? And that if we could do something earlier,
before drivers have claimed their devices, we might be able to compact
the BARs of other devices to make a larger contiguous available space?
That is theoretically possible, but I think the current
pci_resize_resource() only supports resizing of the specified BAR and
any upstream bridge windows. I don't think it supports moving BARs of
other devices.
Sergei did some nice work that might help with this situation because
it can move BARs around more generally. It hasn't quite achieved
critical mass yet, but maybe this would help get there:
https://lore.kernel.org/linux-pci/20201218174011.340514-1-s.miroshnichenko@yadro.com/
If I understand Sergei's series correctly, this rebalancing actually
cannot be done during enumeration because we only move BARs if a
driver for the device indicates that it supports it, so there would be
no requirement to do this early.
> Do we have any alternative to be done in the PCI subsystem during the
> scan? There is other work in progress to allow i915 to use the rest of
> the device memory even with a smaller BAR, but it would be better if we
> can improve our chances of succeeding the resize.
> > > Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> > > Cc: Stuart Summers <stuart.summers@intel.com>
> > > Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
> > > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> > > Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> > > Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> >
> > Please see https://lore.kernel.org/r/87pmj8vesm.fsf@intel.com
> >
> > > ---
> > > drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
> > > 1 file changed, 92 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> > > index d26dcca7e654..4bdb471cb2e2 100644
> > > --- a/drivers/gpu/drm/i915/i915_driver.c
> > > +++ b/drivers/gpu/drm/i915/i915_driver.c
> > > @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
> > > __intel_gt_reset(to_gt(i915), ALL_ENGINES);
> > > }
> > >
> > > +static void __release_bars(struct pci_dev *pdev)
> > > +{
> > > + int resno;
> > > +
> > > + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
> > > + if (pci_resource_len(pdev, resno))
> > > + pci_release_resource(pdev, resno);
> > > + }
> > > +}
> > > +
> > > +static void
> > > +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
> > > +{
> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > + int bar_size = pci_rebar_bytes_to_size(size);
> > > + int ret;
> > > +
> > > + __release_bars(pdev);
> > > +
> > > + ret = pci_resize_resource(pdev, resno, bar_size);
> > > + if (ret) {
> > > + drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
> > > + resno, 1 << bar_size, ERR_PTR(ret));
> > > + return;
> > > + }
> > > +
> > > + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> > > +}
> > > +
> > > +/* BAR size starts from 1MB - 2^20 */
> > > +#define BAR_SIZE_SHIFT 20
> > > +static resource_size_t
> > > +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
> > > +{
> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> > > + resource_size_t size;
> > > +
> > > + if (!rebar)
> > > + return 0;
> > > +
> > > + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> > > +
> > > + if (size <= pci_resource_len(pdev, resno))
> > > + return 0;
> > > +
> > > + return size;
> > > +}
> > > +
> > > +#define LMEM_BAR_NUM 2
> > > +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> > > +{
> > > + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> > > + struct pci_bus *root = pdev->bus;
> > > + struct resource *root_res;
> > > + resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
> > > + u32 pci_cmd;
> > > + int i;
> > > +
> > > + if (!rebar_size)
> > > + return;
> > > +
> > > + /* Find out if root bus contains 64bit memory addressing */
> > > + while (root->parent)
> > > + root = root->parent;
> > > +
> > > + pci_bus_for_each_resource(root, root_res, i) {
> > > + if (root_res && root_res->flags & (IORESOURCE_MEM |
> > > + IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
> > > + break;
> > > + }
> > > +
> > > + /* pci_resize_resource will fail anyways */
> > > + if (!root_res) {
> > > + drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
> > > + return;
> > > + }
> > > +
> > > + /* First disable PCI memory decoding references */
> > > + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> > > + pci_write_config_dword(pdev, PCI_COMMAND,
> > > + pci_cmd & ~PCI_COMMAND_MEMORY);
> > > +
> > > + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> > > +
> > > + pci_assign_unassigned_bus_resources(pdev->bus);
> > > + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> > > +}
> > > +
> > > /**
> > > * i915_driver_early_probe - setup state not requiring device access
> > > * @dev_priv: device private
> > > @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
> > >
> > > disable_rpm_wakeref_asserts(&i915->runtime_pm);
> > >
> > > + if (HAS_LMEM(i915))
> > > + i915_resize_lmem_bar(i915);
> > > +
> > > intel_vgpu_detect(i915);
> > >
> > > ret = intel_gt_probe_all(i915);
> >
> > --
> > Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
2022-06-17 8:32 ` Jani Nikula
@ 2022-06-17 18:44 ` Lucas De Marchi
0 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-06-17 18:44 UTC (permalink / raw)
To: Jani Nikula
Cc: priyanka.dandamudi, matthew.auld, intel-gfx, linux-pci,
linux-kernel, Bjorn Helgaas
Cc'ing intel-pci, lkml, Bjorn
On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
>On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
>> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>>
>> Add support for the local memory PICe resizable bar, so that
>> local memory can be resized to the maximum size supported by the device,
>> and mapped correctly to the PCIe memory bar. It is usual that GPU
>> devices expose only 256MB BARs primarily to be compatible with 32-bit
>> systems. So, those devices cannot claim larger memory BAR windows size due
>> to the system BIOS limitation. With this change, it would be possible to
>> reprogram the windows of the bridge directly above the requesting device
>> on the same BAR type.
There is a big caveat here that this may be too late as other drivers
may have already mapped their BARs - so probably too late in the pci scan
for it to be effective. In fact, after using this for a while, it seems
to fail too often, particularly on CFL systems.
Do we have any alternative to be done in the PCI subsystem during the
scan? There is other work in progress to allow i915 to use the rest of
the device memory even with a smaller BAR, but it would be better if we
can improve our chances of succeeding the resize.
thanks
Lucas De Marchi
>>
>> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
>> Cc: Stuart Summers <stuart.summers@intel.com>
>> Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
>> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>
>Please see https://lore.kernel.org/r/87pmj8vesm.fsf@intel.com
>
>> ---
>> drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
>> 1 file changed, 92 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
>> index d26dcca7e654..4bdb471cb2e2 100644
>> --- a/drivers/gpu/drm/i915/i915_driver.c
>> +++ b/drivers/gpu/drm/i915/i915_driver.c
>> @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
>> __intel_gt_reset(to_gt(i915), ALL_ENGINES);
>> }
>>
>> +static void __release_bars(struct pci_dev *pdev)
>> +{
>> + int resno;
>> +
>> + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
>> + if (pci_resource_len(pdev, resno))
>> + pci_release_resource(pdev, resno);
>> + }
>> +}
>> +
>> +static void
>> +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
>> +{
>> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> + int bar_size = pci_rebar_bytes_to_size(size);
>> + int ret;
>> +
>> + __release_bars(pdev);
>> +
>> + ret = pci_resize_resource(pdev, resno, bar_size);
>> + if (ret) {
>> + drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
>> + resno, 1 << bar_size, ERR_PTR(ret));
>> + return;
>> + }
>> +
>> + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
>> +}
>> +
>> +/* BAR size starts from 1MB - 2^20 */
>> +#define BAR_SIZE_SHIFT 20
>> +static resource_size_t
>> +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
>> +{
>> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
>> + resource_size_t size;
>> +
>> + if (!rebar)
>> + return 0;
>> +
>> + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
>> +
>> + if (size <= pci_resource_len(pdev, resno))
>> + return 0;
>> +
>> + return size;
>> +}
>> +
>> +#define LMEM_BAR_NUM 2
>> +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
>> +{
>> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> + struct pci_bus *root = pdev->bus;
>> + struct resource *root_res;
>> + resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
>> + u32 pci_cmd;
>> + int i;
>> +
>> + if (!rebar_size)
>> + return;
>> +
>> + /* Find out if root bus contains 64bit memory addressing */
>> + while (root->parent)
>> + root = root->parent;
>> +
>> + pci_bus_for_each_resource(root, root_res, i) {
>> + if (root_res && root_res->flags & (IORESOURCE_MEM |
>> + IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
>> + break;
>> + }
>> +
>> + /* pci_resize_resource will fail anyways */
>> + if (!root_res) {
>> + drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
>> + return;
>> + }
>> +
>> + /* First disable PCI memory decoding references */
>> + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
>> + pci_write_config_dword(pdev, PCI_COMMAND,
>> + pci_cmd & ~PCI_COMMAND_MEMORY);
>> +
>> + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
>> +
>> + pci_assign_unassigned_bus_resources(pdev->bus);
>> + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
>> +}
>> +
>> /**
>> * i915_driver_early_probe - setup state not requiring device access
>> * @dev_priv: device private
>> @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>>
>> disable_rpm_wakeref_asserts(&i915->runtime_pm);
>>
>> + if (HAS_LMEM(i915))
>> + i915_resize_lmem_bar(i915);
>> +
>> intel_vgpu_detect(i915);
>>
>> ret = intel_gt_probe_all(i915);
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
@ 2022-06-17 18:44 ` Lucas De Marchi
0 siblings, 0 replies; 20+ messages in thread
From: Lucas De Marchi @ 2022-06-17 18:44 UTC (permalink / raw)
To: Jani Nikula
Cc: linux-pci, intel-gfx, linux-kernel, priyanka.dandamudi,
matthew.auld, Bjorn Helgaas
Cc'ing intel-pci, lkml, Bjorn
On Fri, Jun 17, 2022 at 11:32:37AM +0300, Jani Nikula wrote:
>On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
>> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>>
>> Add support for the local memory PICe resizable bar, so that
>> local memory can be resized to the maximum size supported by the device,
>> and mapped correctly to the PCIe memory bar. It is usual that GPU
>> devices expose only 256MB BARs primarily to be compatible with 32-bit
>> systems. So, those devices cannot claim larger memory BAR windows size due
>> to the system BIOS limitation. With this change, it would be possible to
>> reprogram the windows of the bridge directly above the requesting device
>> on the same BAR type.
There is a big caveat here that this may be too late as other drivers
may have already mapped their BARs - so probably too late in the pci scan
for it to be effective. In fact, after using this for a while, it seems
to fail too often, particularly on CFL systems.
Do we have any alternative to be done in the PCI subsystem during the
scan? There is other work in progress to allow i915 to use the rest of
the device memory even with a smaller BAR, but it would be better if we
can improve our chances of succeeding the resize.
thanks
Lucas De Marchi
>>
>> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
>> Cc: Stuart Summers <stuart.summers@intel.com>
>> Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
>> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
>> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>
>Please see https://lore.kernel.org/r/87pmj8vesm.fsf@intel.com
>
>> ---
>> drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
>> 1 file changed, 92 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
>> index d26dcca7e654..4bdb471cb2e2 100644
>> --- a/drivers/gpu/drm/i915/i915_driver.c
>> +++ b/drivers/gpu/drm/i915/i915_driver.c
>> @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
>> __intel_gt_reset(to_gt(i915), ALL_ENGINES);
>> }
>>
>> +static void __release_bars(struct pci_dev *pdev)
>> +{
>> + int resno;
>> +
>> + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
>> + if (pci_resource_len(pdev, resno))
>> + pci_release_resource(pdev, resno);
>> + }
>> +}
>> +
>> +static void
>> +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
>> +{
>> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> + int bar_size = pci_rebar_bytes_to_size(size);
>> + int ret;
>> +
>> + __release_bars(pdev);
>> +
>> + ret = pci_resize_resource(pdev, resno, bar_size);
>> + if (ret) {
>> + drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
>> + resno, 1 << bar_size, ERR_PTR(ret));
>> + return;
>> + }
>> +
>> + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
>> +}
>> +
>> +/* BAR size starts from 1MB - 2^20 */
>> +#define BAR_SIZE_SHIFT 20
>> +static resource_size_t
>> +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
>> +{
>> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
>> + resource_size_t size;
>> +
>> + if (!rebar)
>> + return 0;
>> +
>> + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
>> +
>> + if (size <= pci_resource_len(pdev, resno))
>> + return 0;
>> +
>> + return size;
>> +}
>> +
>> +#define LMEM_BAR_NUM 2
>> +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
>> +{
>> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
>> + struct pci_bus *root = pdev->bus;
>> + struct resource *root_res;
>> + resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
>> + u32 pci_cmd;
>> + int i;
>> +
>> + if (!rebar_size)
>> + return;
>> +
>> + /* Find out if root bus contains 64bit memory addressing */
>> + while (root->parent)
>> + root = root->parent;
>> +
>> + pci_bus_for_each_resource(root, root_res, i) {
>> + if (root_res && root_res->flags & (IORESOURCE_MEM |
>> + IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
>> + break;
>> + }
>> +
>> + /* pci_resize_resource will fail anyways */
>> + if (!root_res) {
>> + drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
>> + return;
>> + }
>> +
>> + /* First disable PCI memory decoding references */
>> + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
>> + pci_write_config_dword(pdev, PCI_COMMAND,
>> + pci_cmd & ~PCI_COMMAND_MEMORY);
>> +
>> + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
>> +
>> + pci_assign_unassigned_bus_resources(pdev->bus);
>> + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
>> +}
>> +
>> /**
>> * i915_driver_early_probe - setup state not requiring device access
>> * @dev_priv: device private
>> @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>>
>> disable_rpm_wakeref_asserts(&i915->runtime_pm);
>>
>> + if (HAS_LMEM(i915))
>> + i915_resize_lmem_bar(i915);
>> +
>> intel_vgpu_detect(i915);
>>
>> ret = intel_gt_probe_all(i915);
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
2022-06-16 15:12 ` [Intel-gfx] [PATCH 1/2] drm/i915: " priyanka.dandamudi
@ 2022-06-17 8:32 ` Jani Nikula
2022-06-17 18:44 ` Lucas De Marchi
0 siblings, 1 reply; 20+ messages in thread
From: Jani Nikula @ 2022-06-17 8:32 UTC (permalink / raw)
To: priyanka.dandamudi, priyanka.dandamudi, matthew.auld, intel-gfx
On Thu, 16 Jun 2022, priyanka.dandamudi@intel.com wrote:
> From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
>
> Add support for the local memory PICe resizable bar, so that
> local memory can be resized to the maximum size supported by the device,
> and mapped correctly to the PCIe memory bar. It is usual that GPU
> devices expose only 256MB BARs primarily to be compatible with 32-bit
> systems. So, those devices cannot claim larger memory BAR windows size due
> to the system BIOS limitation. With this change, it would be possible to
> reprogram the windows of the bridge directly above the requesting device
> on the same BAR type.
>
> Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
> Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
> Cc: Stuart Summers <stuart.summers@intel.com>
> Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
> Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Please see https://lore.kernel.org/r/87pmj8vesm.fsf@intel.com
> ---
> drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index d26dcca7e654..4bdb471cb2e2 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
> __intel_gt_reset(to_gt(i915), ALL_ENGINES);
> }
>
> +static void __release_bars(struct pci_dev *pdev)
> +{
> + int resno;
> +
> + for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
> + if (pci_resource_len(pdev, resno))
> + pci_release_resource(pdev, resno);
> + }
> +}
> +
> +static void
> +__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + int bar_size = pci_rebar_bytes_to_size(size);
> + int ret;
> +
> + __release_bars(pdev);
> +
> + ret = pci_resize_resource(pdev, resno, bar_size);
> + if (ret) {
> + drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
> + resno, 1 << bar_size, ERR_PTR(ret));
> + return;
> + }
> +
> + drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> +}
> +
> +/* BAR size starts from 1MB - 2^20 */
> +#define BAR_SIZE_SHIFT 20
> +static resource_size_t
> +__lmem_rebar_size(struct drm_i915_private *i915, int resno)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
> + resource_size_t size;
> +
> + if (!rebar)
> + return 0;
> +
> + size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
> +
> + if (size <= pci_resource_len(pdev, resno))
> + return 0;
> +
> + return size;
> +}
> +
> +#define LMEM_BAR_NUM 2
> +static void i915_resize_lmem_bar(struct drm_i915_private *i915)
> +{
> + struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct pci_bus *root = pdev->bus;
> + struct resource *root_res;
> + resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
> + u32 pci_cmd;
> + int i;
> +
> + if (!rebar_size)
> + return;
> +
> + /* Find out if root bus contains 64bit memory addressing */
> + while (root->parent)
> + root = root->parent;
> +
> + pci_bus_for_each_resource(root, root_res, i) {
> + if (root_res && root_res->flags & (IORESOURCE_MEM |
> + IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
> + break;
> + }
> +
> + /* pci_resize_resource will fail anyways */
> + if (!root_res) {
> + drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
> + return;
> + }
> +
> + /* First disable PCI memory decoding references */
> + pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> + pci_write_config_dword(pdev, PCI_COMMAND,
> + pci_cmd & ~PCI_COMMAND_MEMORY);
> +
> + __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> +
> + pci_assign_unassigned_bus_resources(pdev->bus);
> + pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> +}
> +
> /**
> * i915_driver_early_probe - setup state not requiring device access
> * @dev_priv: device private
> @@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
>
> disable_rpm_wakeref_asserts(&i915->runtime_pm);
>
> + if (HAS_LMEM(i915))
> + i915_resize_lmem_bar(i915);
> +
> intel_vgpu_detect(i915);
>
> ret = intel_gt_probe_all(i915);
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915: Add support for LMEM PCIe resizable bar
2022-06-16 15:12 [Intel-gfx] [PATCH 0/2] " priyanka.dandamudi
@ 2022-06-16 15:12 ` priyanka.dandamudi
2022-06-17 8:32 ` Jani Nikula
0 siblings, 1 reply; 20+ messages in thread
From: priyanka.dandamudi @ 2022-06-16 15:12 UTC (permalink / raw)
To: priyanka.dandamudi, matthew.auld, intel-gfx
From: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Add support for the local memory PICe resizable bar, so that
local memory can be resized to the maximum size supported by the device,
and mapped correctly to the PCIe memory bar. It is usual that GPU
devices expose only 256MB BARs primarily to be compatible with 32-bit
systems. So, those devices cannot claim larger memory BAR windows size due
to the system BIOS limitation. With this change, it would be possible to
reprogram the windows of the bridge directly above the requesting device
on the same BAR type.
Signed-off-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Michael J Ruhl <michael.j.ruhl@intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Signed-off-by: Priyanka Dandamudi <priyanka.dandamudi@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/i915_driver.c | 92 ++++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..4bdb471cb2e2 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -303,6 +303,95 @@ static void sanitize_gpu(struct drm_i915_private *i915)
__intel_gt_reset(to_gt(i915), ALL_ENGINES);
}
+static void __release_bars(struct pci_dev *pdev)
+{
+ int resno;
+
+ for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
+ if (pci_resource_len(pdev, resno))
+ pci_release_resource(pdev, resno);
+ }
+}
+
+static void
+__resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ int bar_size = pci_rebar_bytes_to_size(size);
+ int ret;
+
+ __release_bars(pdev);
+
+ ret = pci_resize_resource(pdev, resno, bar_size);
+ if (ret) {
+ drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
+ resno, 1 << bar_size, ERR_PTR(ret));
+ return;
+ }
+
+ drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
+}
+
+/* BAR size starts from 1MB - 2^20 */
+#define BAR_SIZE_SHIFT 20
+static resource_size_t
+__lmem_rebar_size(struct drm_i915_private *i915, int resno)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ u32 rebar = pci_rebar_get_possible_sizes(pdev, resno);
+ resource_size_t size;
+
+ if (!rebar)
+ return 0;
+
+ size = 1ULL << (__fls(rebar) + BAR_SIZE_SHIFT);
+
+ if (size <= pci_resource_len(pdev, resno))
+ return 0;
+
+ return size;
+}
+
+#define LMEM_BAR_NUM 2
+static void i915_resize_lmem_bar(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct pci_bus *root = pdev->bus;
+ struct resource *root_res;
+ resource_size_t rebar_size = __lmem_rebar_size(i915, LMEM_BAR_NUM);
+ u32 pci_cmd;
+ int i;
+
+ if (!rebar_size)
+ return;
+
+ /* Find out if root bus contains 64bit memory addressing */
+ while (root->parent)
+ root = root->parent;
+
+ pci_bus_for_each_resource(root, root_res, i) {
+ if (root_res && root_res->flags & (IORESOURCE_MEM |
+ IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
+ break;
+ }
+
+ /* pci_resize_resource will fail anyways */
+ if (!root_res) {
+ drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
+ return;
+ }
+
+ /* First disable PCI memory decoding references */
+ pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
+ pci_write_config_dword(pdev, PCI_COMMAND,
+ pci_cmd & ~PCI_COMMAND_MEMORY);
+
+ __resize_bar(i915, LMEM_BAR_NUM, rebar_size);
+
+ pci_assign_unassigned_bus_resources(pdev->bus);
+ pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
+}
+
/**
* i915_driver_early_probe - setup state not requiring device access
* @dev_priv: device private
@@ -852,6 +941,9 @@ int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
disable_rpm_wakeref_asserts(&i915->runtime_pm);
+ if (HAS_LMEM(i915))
+ i915_resize_lmem_bar(i915);
+
intel_vgpu_detect(i915);
ret = intel_gt_probe_all(i915);
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
end of thread, other threads:[~2022-06-29 6:00 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-15 5:43 [Intel-gfx] [PATCH 0/2] Add support for LMEM PCIe resizable bar priyanka.dandamudi
2022-06-15 5:43 ` [Intel-gfx] [PATCH 1/2] drm/i915: " priyanka.dandamudi
2022-06-15 10:51 ` Matthew Auld
2022-06-15 5:43 ` [Intel-gfx] [PATCH 2/2] drm/i915: Add lmem_bar_size modparam priyanka.dandamudi
2022-06-15 10:17 ` Matthew Auld
2022-06-15 9:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add support for LMEM PCIe resizable bar Patchwork
2022-06-15 9:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-06-15 9:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-15 14:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-06-16 15:12 [Intel-gfx] [PATCH 0/2] " priyanka.dandamudi
2022-06-16 15:12 ` [Intel-gfx] [PATCH 1/2] drm/i915: " priyanka.dandamudi
2022-06-17 8:32 ` Jani Nikula
2022-06-17 18:44 ` Lucas De Marchi
2022-06-17 18:44 ` Lucas De Marchi
2022-06-17 20:32 ` Bjorn Helgaas
2022-06-17 20:32 ` Bjorn Helgaas
2022-06-17 21:27 ` Lucas De Marchi
2022-06-18 15:14 ` Christian König
2022-06-24 4:02 ` Dandamudi, Priyanka
2022-06-24 4:02 ` Dandamudi, Priyanka
2022-06-29 6:00 ` Thomas Hellström (Intel)
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