* [Intel-gfx] [PATCH 0/7] Commit early to GuC
@ 2020-01-15 1:31 Daniele Ceraolo Spurio
2020-01-15 1:31 ` [Intel-gfx] [PATCH 1/7] drm/i915/guc: Kill USES_GUC macro Daniele Ceraolo Spurio
` (11 more replies)
0 siblings, 12 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-15 1:31 UTC (permalink / raw)
To: intel-gfx
We currently wait until we attempt to load the GuC to confirm if we're
in GuC mode or not, at which point a lot of the engine setup has already
happened and needs to be updated for GuC submission. To allow us to get
the setup done directly into GuC mode, we need to commit to using GuC
as soon as possible. Currently, if GuC is enabled via modparam on a
platform that supports it, the main issue that can cause us to fall-back
to non-GuC mode is the lack of blobs on the system. It is not safe to
fall back to non-GuC after attempting to load the blobs (see
__uc_check_hw) and all the functions in the GuC paths between the fetch
and the load can only fail if something is fundamentally wrong with the
system (e.g. allocation failure). Therefore, committing to using the GuC
after the fetch is successful seems like a reasonable compromise between
early setup and fall-back options.
To better track this, this series splits the uC init status in 3 steps,
with the last one meaning we're locked in and can't fall back anymore:
- supported: HW supports the microcontroller
- wanted: supported and selected in modparam
- used: wanted and blob found on the system
(Suggestions for better naming are welcome)
The last patch in the series starts using the early commitment to setup
the GuC submission back-end instead of the execlists one, instead of
always setting up the latter and then taking over. This is just an
higher level change for now as the GuC code calls the execlists one
internally, but I plan to follow with more changes while we switch to
the new interface.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Anusha Srivatsa (1):
HAX: force enable_guc=2
Daniele Ceraolo Spurio (6):
drm/i915/guc: Kill USES_GUC macro
drm/i915/guc: Kill USES_GUC_SUBMISSION macro
drm/i915/uc: Improve tracking of uC init status
drm/i915/uc: Abort early on uc_init failure
drm/i915/guc: Apply new uC status tracking to GuC submission as well
drm/i915/guc: Start considering GuC submission a proper back-end
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 ++-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 42 +++++++------
drivers/gpu/drm/i915/gt/intel_lrc.h | 2 +
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 10 +--
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 14 ++---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 25 ++++++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 56 +++++++++++------
.../gpu/drm/i915/gt/uc/intel_guc_submission.h | 4 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 8 ++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 59 +++++++++++-------
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 61 +++++++++++--------
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 3 +-
drivers/gpu/drm/i915/i915_debugfs.c | 25 ++++----
drivers/gpu/drm/i915/i915_drv.h | 10 ---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_gvt.c | 2 +-
24 files changed, 212 insertions(+), 139 deletions(-)
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 1/7] drm/i915/guc: Kill USES_GUC macro
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
@ 2020-01-15 1:31 ` Daniele Ceraolo Spurio
2020-01-16 19:42 ` Michal Wajdeczko
2020-01-15 1:31 ` [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro Daniele Ceraolo Spurio
` (10 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-15 1:31 UTC (permalink / raw)
To: intel-gfx
use intel_uc_uses_guc() directly instead, to be consistent in the way we
check what we want to do with the GuC.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 19 ++++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 1 -
3 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 79096722ce16..bb4aa923dbd9 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -462,7 +462,7 @@ static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
u64 size;
int ret;
- if (!USES_GUC(ggtt->vm.i915))
+ if (!intel_uc_uses_guc(&ggtt->vm.gt->uc))
return 0;
GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index d5a9b8a964c2..c2f480defc71 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1752,10 +1752,8 @@ stringify_guc_log_type(enum guc_log_buffer_type type)
return "";
}
-static void i915_guc_log_info(struct seq_file *m,
- struct drm_i915_private *dev_priv)
+static void i915_guc_log_info(struct seq_file *m, struct intel_guc_log *log)
{
- struct intel_guc_log *log = &dev_priv->gt.uc.guc.log;
enum guc_log_buffer_type type;
if (!intel_guc_log_relay_created(log)) {
@@ -1779,11 +1777,12 @@ static void i915_guc_log_info(struct seq_file *m,
static int i915_guc_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ struct intel_uc *uc = &dev_priv->gt.uc;
- if (!USES_GUC(dev_priv))
+ if (!intel_uc_uses_guc(uc))
return -ENODEV;
- i915_guc_log_info(m, dev_priv);
+ i915_guc_log_info(m, &uc->guc.log);
/* Add more as required ... */
@@ -1884,11 +1883,12 @@ static int i915_guc_log_dump(struct seq_file *m, void *data)
static int i915_guc_log_level_get(void *data, u64 *val)
{
struct drm_i915_private *dev_priv = data;
+ struct intel_uc *uc = &dev_priv->gt.uc;
- if (!USES_GUC(dev_priv))
+ if (!intel_uc_uses_guc(uc))
return -ENODEV;
- *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log);
+ *val = intel_guc_log_get_level(&uc->guc.log);
return 0;
}
@@ -1896,11 +1896,12 @@ static int i915_guc_log_level_get(void *data, u64 *val)
static int i915_guc_log_level_set(void *data, u64 val)
{
struct drm_i915_private *dev_priv = data;
+ struct intel_uc *uc = &dev_priv->gt.uc;
- if (!USES_GUC(dev_priv))
+ if (!intel_uc_uses_guc(uc))
return -ENODEV;
- return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val);
+ return intel_guc_log_set_level(&uc->guc.log, val);
}
DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 077af22b8340..ad0019cd2604 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1719,7 +1719,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
/* Having GuC is not the same as using GuC */
-#define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc)
#define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
2020-01-15 1:31 ` [Intel-gfx] [PATCH 1/7] drm/i915/guc: Kill USES_GUC macro Daniele Ceraolo Spurio
@ 2020-01-15 1:31 ` Daniele Ceraolo Spurio
2020-01-16 19:49 ` Michal Wajdeczko
2020-01-27 3:00 ` kbuild test robot
2020-01-15 1:31 ` [Intel-gfx] [PATCH 3/7] drm/i915/uc: Improve tracking of uC init status Daniele Ceraolo Spurio
` (9 subsequent siblings)
11 siblings, 2 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-15 1:31 UTC (permalink / raw)
To: intel-gfx
use intel_uc_uses_guc_submission() directly instead, to be consistent in
the way we check what we want to do with the GuC.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_lrc.c | 10 +++++-----
drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 3 ++-
drivers/gpu/drm/i915/i915_debugfs.c | 6 +++---
drivers/gpu/drm/i915/i915_drv.h | 3 ---
drivers/gpu/drm/i915/intel_gvt.c | 2 +-
8 files changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index a2e57e62af30..415e2d5e934b 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1454,7 +1454,7 @@ set_engines__load_balance(struct i915_user_extension __user *base, void *data)
if (!HAS_EXECLISTS(set->ctx->i915))
return -ENODEV;
- if (USES_GUC_SUBMISSION(set->ctx->i915))
+ if (intel_uc_uses_guc_submission(&set->ctx->vm->gt->uc))
return -ENODEV; /* not implement yet */
if (get_user(idx, &ext->engine_index))
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 3e5e6c86e843..c3514ec7b8db 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1640,7 +1640,7 @@ static int igt_reset_engines_atomic(void *arg)
if (!intel_has_reset_engine(gt))
return 0;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
igt_global_reset_lock(gt);
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 15cda024e3e4..b1c677b0d5ad 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -1555,7 +1555,7 @@ static int live_suppress_self_preempt(void *arg)
if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
return 0;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0; /* presume black blox */
if (intel_vgpu_active(gt->i915))
@@ -2781,7 +2781,7 @@ static int live_virtual_engine(void *arg)
unsigned int class, inst;
int err;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
for_each_engine(engine, gt, id) {
@@ -2914,7 +2914,7 @@ static int live_virtual_mask(void *arg)
unsigned int class, inst;
int err;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
@@ -3052,7 +3052,7 @@ static int live_virtual_preserved(void *arg)
* are preserved.
*/
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
/* As we use CS_GPR we cannot run before they existed on all engines. */
@@ -3276,7 +3276,7 @@ static int live_virtual_bond(void *arg)
unsigned int class, inst;
int err;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 6ad6aca315f6..35406ecdf0b2 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -115,7 +115,7 @@ static int igt_atomic_engine_reset(void *arg)
if (!intel_has_reset_engine(gt))
return 0;
- if (USES_GUC_SUBMISSION(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
return 0;
intel_gt_pm_get(gt);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 685d1e04a5ff..5fe00ee6bd1b 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1246,7 +1246,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
ce->vm = i915_vm_get(&ppgtt->vm);
intel_context_set_single_submission(ce);
- if (!USES_GUC_SUBMISSION(i915)) { /* Max ring buffer size */
+ /* Max ring buffer size */
+ if (!intel_uc_uses_guc_submission(&engine->gt->uc)) {
const unsigned int ring_size = 512 * SZ_4K;
ce->ring = __intel_context_ring_size(ring_size);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c2f480defc71..823a033ffcd0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1792,11 +1792,11 @@ static int i915_guc_info(struct seq_file *m, void *data)
static int i915_guc_stage_pool(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
- const struct intel_guc *guc = &dev_priv->gt.uc.guc;
- struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
+ struct intel_uc *uc = &dev_priv->gt.uc;
+ struct guc_stage_desc *desc = uc->guc.stage_desc_pool_vaddr;
int index;
- if (!USES_GUC_SUBMISSION(dev_priv))
+ if (!intel_uc_uses_guc_submission(uc))
return -ENODEV;
for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ad0019cd2604..24d581c63667 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1718,9 +1718,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
-/* Having GuC is not the same as using GuC */
-#define USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
-
#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
#define HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index 2b6c016387c2..481c6de9f4d6 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -103,7 +103,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return 0;
}
- if (USES_GUC_SUBMISSION(dev_priv)) {
+ if (intel_uc_uses_guc_submission(&dev_priv->gt.uc)) {
DRM_ERROR("i915 GVT-g loading failed due to Graphics virtualization is not yet supported with GuC submission\n");
return -EIO;
}
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 3/7] drm/i915/uc: Improve tracking of uC init status
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
2020-01-15 1:31 ` [Intel-gfx] [PATCH 1/7] drm/i915/guc: Kill USES_GUC macro Daniele Ceraolo Spurio
2020-01-15 1:31 ` [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro Daniele Ceraolo Spurio
@ 2020-01-15 1:31 ` Daniele Ceraolo Spurio
2020-01-27 23:57 ` Fernando Pacheco
2020-01-15 1:31 ` [Intel-gfx] [PATCH 4/7] drm/i915/uc: Abort early on uc_init failure Daniele Ceraolo Spurio
` (8 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-15 1:31 UTC (permalink / raw)
To: intel-gfx
To be able to setup GuC submission functions during engine init we need
to commit to using GuC as soon as possible.
Currently, the only thing that can stop us from using the
microcontrollers once we've fetched the blobs is a fundamental
error (e.g. OOM); given that if we hit such an error we can't really
fall-back to anything, we can "officialize" the FW fetching completion
as the moment at which we're committing to using GuC.
To better differentiate this case, the uses_guc check, which indicates
that GuC is supported and was selected in modparam, is renamed to
wants_guc and a new uses_guc is introduced to represent the case were
we're committed to using the GuC. Note that uses_guc does still not imply
that the blob is actually loaded on the HW (is_running is the check for
that). Also, since we need to have attempted the fetch for the result
of uses_guc to be meaningful, we need to make sure we've moved away
from INTEL_UC_FIRMWARE_SELECTED.
All the GuC changes have been mirrored on the HuC for coherency.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 8 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 8 +++-
drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 23 +++++-----
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 52 +++++++++++++++--------
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
6 files changed, 64 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 910d49590068..f9e0be843992 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -143,11 +143,17 @@ static inline bool intel_guc_is_supported(struct intel_guc *guc)
return intel_uc_fw_is_supported(&guc->fw);
}
-static inline bool intel_guc_is_enabled(struct intel_guc *guc)
+static inline bool intel_guc_is_wanted(struct intel_guc *guc)
{
return intel_uc_fw_is_enabled(&guc->fw);
}
+static inline bool intel_guc_is_used(struct intel_guc *guc)
+{
+ GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) == INTEL_UC_FIRMWARE_SELECTED);
+ return intel_uc_fw_is_available(&guc->fw);
+}
+
static inline bool intel_guc_is_running(struct intel_guc *guc)
{
return intel_uc_fw_is_running(&guc->fw);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
index 644c059fe01d..a40b9cfc6c22 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
@@ -41,11 +41,17 @@ static inline bool intel_huc_is_supported(struct intel_huc *huc)
return intel_uc_fw_is_supported(&huc->fw);
}
-static inline bool intel_huc_is_enabled(struct intel_huc *huc)
+static inline bool intel_huc_is_wanted(struct intel_huc *huc)
{
return intel_uc_fw_is_enabled(&huc->fw);
}
+static inline bool intel_huc_is_used(struct intel_huc *huc)
+{
+ GEM_BUG_ON(__intel_uc_fw_status(&huc->fw) == INTEL_UC_FIRMWARE_SELECTED);
+ return intel_uc_fw_is_available(&huc->fw);
+}
+
static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
{
return intel_uc_fw_is_running(&huc->fw);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index eee193bf2cc4..fd7d04690ded 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -20,7 +20,7 @@ void intel_huc_fw_init_early(struct intel_huc *huc)
struct drm_i915_private *i915 = gt->i915;
intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC,
- intel_uc_uses_guc(uc),
+ intel_uc_supports_guc(uc),
INTEL_INFO(i915)->platform, INTEL_REVID(i915));
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 64934a876a50..8843d4f16a7f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -48,17 +48,17 @@ static void __confirm_options(struct intel_uc *uc)
DRM_DEV_DEBUG_DRIVER(i915->drm.dev,
"enable_guc=%d (guc:%s submission:%s huc:%s)\n",
i915_modparams.enable_guc,
- yesno(intel_uc_uses_guc(uc)),
+ yesno(intel_uc_wants_guc(uc)),
yesno(intel_uc_uses_guc_submission(uc)),
- yesno(intel_uc_uses_huc(uc)));
+ yesno(intel_uc_wants_huc(uc)));
if (i915_modparams.enable_guc == -1)
return;
if (i915_modparams.enable_guc == 0) {
- GEM_BUG_ON(intel_uc_uses_guc(uc));
+ GEM_BUG_ON(intel_uc_wants_guc(uc));
GEM_BUG_ON(intel_uc_uses_guc_submission(uc));
- GEM_BUG_ON(intel_uc_uses_huc(uc));
+ GEM_BUG_ON(intel_uc_wants_huc(uc));
return;
}
@@ -93,7 +93,7 @@ void intel_uc_init_early(struct intel_uc *uc)
__confirm_options(uc);
- if (intel_uc_uses_guc(uc))
+ if (intel_uc_wants_guc(uc))
uc->ops = &uc_ops_on;
else
uc->ops = &uc_ops_off;
@@ -257,13 +257,13 @@ static void __uc_fetch_firmwares(struct intel_uc *uc)
{
int err;
- GEM_BUG_ON(!intel_uc_uses_guc(uc));
+ GEM_BUG_ON(!intel_uc_wants_guc(uc));
err = intel_uc_fw_fetch(&uc->guc.fw);
if (err)
return;
- if (intel_uc_uses_huc(uc))
+ if (intel_uc_wants_huc(uc))
intel_uc_fw_fetch(&uc->huc.fw);
}
@@ -279,7 +279,10 @@ static void __uc_init(struct intel_uc *uc)
struct intel_huc *huc = &uc->huc;
int ret;
- GEM_BUG_ON(!intel_uc_uses_guc(uc));
+ GEM_BUG_ON(!intel_uc_wants_guc(uc));
+
+ if (!intel_uc_uses_guc(uc))
+ return;
/* XXX: GuC submission is unavailable for now */
GEM_BUG_ON(intel_uc_supports_guc_submission(uc));
@@ -322,7 +325,7 @@ static int uc_init_wopcm(struct intel_uc *uc)
struct intel_uncore *uncore = gt->uncore;
u32 base = intel_wopcm_guc_base(>->i915->wopcm);
u32 size = intel_wopcm_guc_size(>->i915->wopcm);
- u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
+ u32 huc_agent = intel_uc_wants_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
u32 mask;
int err;
@@ -402,7 +405,7 @@ static int __uc_init_hw(struct intel_uc *uc)
int ret, attempts;
GEM_BUG_ON(!intel_uc_supports_guc(uc));
- GEM_BUG_ON(!intel_uc_uses_guc(uc));
+ GEM_BUG_ON(!intel_uc_wants_guc(uc));
if (!intel_uc_fw_is_available(&guc->fw)) {
ret = __uc_check_hw(uc) ||
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index 49c913524686..f2f7351ff22a 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -40,16 +40,44 @@ void intel_uc_runtime_suspend(struct intel_uc *uc);
int intel_uc_resume(struct intel_uc *uc);
int intel_uc_runtime_resume(struct intel_uc *uc);
-static inline bool intel_uc_supports_guc(struct intel_uc *uc)
-{
- return intel_guc_is_supported(&uc->guc);
-}
+/*
+ * We need to know as early as possible if we're going to use GuC or not to
+ * take the correct setup paths. Additionally, once we've started loading the
+ * GuC, it is unsafe to keep executing without it because some parts of the HW,
+ * a subset of which is not cleaned on GT reset, will start expecting the GuC FW
+ * to be running.
+ * To solve both these requirements, we commit to using the microcontrollers if
+ * the relevant modparam is set and the blobs are found on the system. At this
+ * stage, the only thing that can stop us from attempting to load the blobs on
+ * the HW and use them is a fundamental issue (e.g. no memory for our
+ * structures); if we hit such a problem during driver load we're broken even
+ * without GuC, so there is no point in trying to fall back.
+ *
+ * Given the above, we can be in one of 4 states, with the last one implying
+ * we're committed to using the microcontroller:
+ * - Not supported: not available in HW and/or firmware not defined.
+ * - Supported: available in HW and firmware defined.
+ * - Wanted: supported and enabled in modparam.
+ * - In use: wanted and firmware found on the system.
+ */
-static inline bool intel_uc_uses_guc(struct intel_uc *uc)
-{
- return intel_guc_is_enabled(&uc->guc);
+#define __uc_state_checker(x, state, required) \
+static inline bool intel_uc_##state##_##x(struct intel_uc *uc) \
+{ \
+ return intel_##x##_is_##required(&uc->x); \
}
+#define uc_state_checkers(x) \
+__uc_state_checker(x, supports, supported) \
+__uc_state_checker(x, wants, wanted) \
+__uc_state_checker(x, uses, used)
+
+uc_state_checkers(guc);
+uc_state_checkers(huc);
+
+#undef uc_state_checkers
+#undef __uc_state_checker
+
static inline bool intel_uc_supports_guc_submission(struct intel_uc *uc)
{
return intel_guc_is_submission_supported(&uc->guc);
@@ -60,16 +88,6 @@ static inline bool intel_uc_uses_guc_submission(struct intel_uc *uc)
return intel_guc_is_submission_supported(&uc->guc);
}
-static inline bool intel_uc_supports_huc(struct intel_uc *uc)
-{
- return intel_uc_supports_guc(uc);
-}
-
-static inline bool intel_uc_uses_huc(struct intel_uc *uc)
-{
- return intel_huc_is_enabled(&uc->huc);
-}
-
#define intel_uc_ops_function(_NAME, _OPS, _TYPE, _RET) \
static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \
{ \
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index 8ee0a0c7f447..c9c094a73399 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -279,7 +279,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
err = i915_inject_probe_error(i915, -ENXIO);
if (err)
- return err;
+ goto fail;
__force_fw_fetch_failures(uc_fw, -EINVAL);
__force_fw_fetch_failures(uc_fw, -ESTALE);
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 4/7] drm/i915/uc: Abort early on uc_init failure
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
` (2 preceding siblings ...)
2020-01-15 1:31 ` [Intel-gfx] [PATCH 3/7] drm/i915/uc: Improve tracking of uC init status Daniele Ceraolo Spurio
@ 2020-01-15 1:31 ` Daniele Ceraolo Spurio
2020-01-27 23:57 ` Fernando Pacheco
2020-01-15 1:31 ` [Intel-gfx] [PATCH 5/7] drm/i915/guc: Apply new uC status tracking to GuC submission as well Daniele Ceraolo Spurio
` (7 subsequent siblings)
11 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-15 1:31 UTC (permalink / raw)
To: intel-gfx
Now that we can differentiate wants vs uses GuC/HuC, intel_uc_init is
restricted to running only if we have successfully fetched the required
blob(s) and are committed to using the microcontroller(s).
The only remaining thing that can go wrong in uc_init is the allocation
of GuC/HuC related objects; if we get such a failure better to bail out
immediately instead of wedging later, like we do for e.g.
intel_engines_init, since without objects we can't use the HW, including
not being able to attempt the firmware load.
While at it, remove the unneeded fw_cleanup call (this is handled
outside of gt_init) and add a probe failure injection point for testing.
Also, update the logs for <g/h>uc_init failures to probe_failure() since
they will cause the driver load to fail.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 24 +++++++++++++++++-------
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 4 ++--
5 files changed, 24 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index da2b6e2ae692..85f21f18c785 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -584,7 +584,9 @@ int intel_gt_init(struct intel_gt *gt)
if (err)
goto err_engines;
- intel_uc_init(>->uc);
+ err = intel_uc_init(>->uc);
+ if (err)
+ goto err_engines;
err = intel_gt_resume(gt);
if (err)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 5d00a3b2d914..c46f5ae77348 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -376,7 +376,7 @@ int intel_guc_init(struct intel_guc *guc)
intel_uc_fw_fini(&guc->fw);
err_fetch:
intel_uc_fw_cleanup_fetch(&guc->fw);
- DRM_DEV_DEBUG_DRIVER(gt->i915->drm.dev, "failed with %d\n", ret);
+ i915_probe_error(gt->i915, "failed with %d\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
index 32a069841c14..5f448d0e360b 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
@@ -127,7 +127,7 @@ int intel_huc_init(struct intel_huc *huc)
intel_uc_fw_fini(&huc->fw);
out:
intel_uc_fw_cleanup_fetch(&huc->fw);
- DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "failed with %d\n", err);
+ i915_probe_error(i915, "failed with %d\n", err);
return err;
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 8843d4f16a7f..d57b731952ef 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -273,7 +273,7 @@ static void __uc_cleanup_firmwares(struct intel_uc *uc)
intel_uc_fw_cleanup_fetch(&uc->guc.fw);
}
-static void __uc_init(struct intel_uc *uc)
+static int __uc_init(struct intel_uc *uc)
{
struct intel_guc *guc = &uc->guc;
struct intel_huc *huc = &uc->huc;
@@ -282,19 +282,29 @@ static void __uc_init(struct intel_uc *uc)
GEM_BUG_ON(!intel_uc_wants_guc(uc));
if (!intel_uc_uses_guc(uc))
- return;
+ return 0;
+
+ if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
+ return -ENOMEM;
/* XXX: GuC submission is unavailable for now */
GEM_BUG_ON(intel_uc_supports_guc_submission(uc));
ret = intel_guc_init(guc);
- if (ret) {
- intel_uc_fw_cleanup_fetch(&huc->fw);
- return;
+ if (ret)
+ return ret;
+
+ if (intel_uc_uses_huc(uc)) {
+ ret = intel_huc_init(huc);
+ if (ret)
+ goto out_guc;
}
- if (intel_uc_uses_huc(uc))
- intel_huc_init(huc);
+ return 0;
+
+out_guc:
+ intel_guc_fini(guc);
+ return ret;
}
static void __uc_fini(struct intel_uc *uc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index f2f7351ff22a..2d9f17196761 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -16,7 +16,7 @@ struct intel_uc_ops {
int (*sanitize)(struct intel_uc *uc);
void (*init_fw)(struct intel_uc *uc);
void (*fini_fw)(struct intel_uc *uc);
- void (*init)(struct intel_uc *uc);
+ int (*init)(struct intel_uc *uc);
void (*fini)(struct intel_uc *uc);
int (*init_hw)(struct intel_uc *uc);
void (*fini_hw)(struct intel_uc *uc);
@@ -98,7 +98,7 @@ static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \
intel_uc_ops_function(sanitize, sanitize, int, 0);
intel_uc_ops_function(fetch_firmwares, init_fw, void, );
intel_uc_ops_function(cleanup_firmwares, fini_fw, void, );
-intel_uc_ops_function(init, init, void, );
+intel_uc_ops_function(init, init, int, 0);
intel_uc_ops_function(fini, fini, void, );
intel_uc_ops_function(init_hw, init_hw, int, 0);
intel_uc_ops_function(fini_hw, fini_hw, void, );
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 5/7] drm/i915/guc: Apply new uC status tracking to GuC submission as well
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
` (3 preceding siblings ...)
2020-01-15 1:31 ` [Intel-gfx] [PATCH 4/7] drm/i915/uc: Abort early on uc_init failure Daniele Ceraolo Spurio
@ 2020-01-15 1:31 ` Daniele Ceraolo Spurio
2020-01-15 1:31 ` [Intel-gfx] [PATCH 6/7] drm/i915/guc: Start considering GuC submission a proper back-end Daniele Ceraolo Spurio
` (6 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-15 1:31 UTC (permalink / raw)
To: intel-gfx
To be able to differentiate the before and after of our commitment to
GuC submission, which will be used in follow-up patches to early set-up
the submission structures.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 12 ++++----
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 17 +++++++++--
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 9 ++----
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 14 ++++-----
drivers/gpu/drm/i915/gt/uc/intel_uc.h | 29 +++++++------------
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 6 ----
drivers/gpu/drm/i915/intel_gvt.c | 2 +-
8 files changed, 42 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index c46f5ae77348..58884e06e548 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -207,7 +207,7 @@ static u32 guc_ctl_feature_flags(struct intel_guc *guc)
{
u32 flags = 0;
- if (!intel_guc_is_submission_supported(guc))
+ if (!intel_guc_submission_is_used(guc))
flags |= GUC_CTL_DISABLE_SCHEDULER;
return flags;
@@ -217,7 +217,7 @@ static u32 guc_ctl_ctxinfo_flags(struct intel_guc *guc)
{
u32 flags = 0;
- if (intel_guc_is_submission_supported(guc)) {
+ if (intel_guc_submission_is_used(guc)) {
u32 ctxnum, base;
base = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
@@ -348,7 +348,7 @@ int intel_guc_init(struct intel_guc *guc)
if (ret)
goto err_ads;
- if (intel_guc_is_submission_supported(guc)) {
+ if (intel_guc_submission_is_used(guc)) {
/*
* This is stuff we need to have available at fw load time
* if we are planning to enable submission later
@@ -389,7 +389,7 @@ void intel_guc_fini(struct intel_guc *guc)
i915_ggtt_disable_guc(gt->ggtt);
- if (intel_guc_is_submission_supported(guc))
+ if (intel_guc_submission_is_used(guc))
intel_guc_submission_fini(guc);
intel_guc_ct_fini(&guc->ct);
@@ -544,7 +544,7 @@ int intel_guc_suspend(struct intel_guc *guc)
* If GuC communication is enabled but submission is not supported,
* we do not need to suspend the GuC.
*/
- if (!intel_guc_submission_is_enabled(guc))
+ if (!intel_guc_submission_is_used(guc) || !intel_guc_is_running(guc))
return 0;
/*
@@ -609,7 +609,7 @@ int intel_guc_resume(struct intel_guc *guc)
* we do not need to resume the GuC but we do need to enable the
* GuC communication on resume (above).
*/
- if (!intel_guc_submission_is_enabled(guc))
+ if (!intel_guc_submission_is_used(guc) || !intel_guc_is_running(guc))
return 0;
return intel_guc_send(guc, action, ARRAY_SIZE(action));
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index f9e0be843992..1ad446f4a022 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -39,7 +39,7 @@ struct intel_guc {
void (*disable)(struct intel_guc *guc);
} interrupts;
- bool submission_supported;
+ bool submission_selected;
struct i915_vma *ads_vma;
struct __guc_ads_blob *ads_blob;
@@ -167,9 +167,20 @@ static inline int intel_guc_sanitize(struct intel_guc *guc)
return 0;
}
-static inline bool intel_guc_is_submission_supported(struct intel_guc *guc)
+static inline bool intel_guc_submission_is_supported(struct intel_guc *guc)
{
- return guc->submission_supported;
+ /* XXX: GuC submission is unavailable for now */
+ return false;
+}
+
+static inline bool intel_guc_submission_is_wanted(struct intel_guc *guc)
+{
+ return guc->submission_selected;
+}
+
+static inline bool intel_guc_submission_is_used(struct intel_guc *guc)
+{
+ return intel_guc_is_used(guc) && intel_guc_submission_is_wanted(guc);
}
static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 9e42324fdecd..1beaa77f9bb6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -660,12 +660,9 @@ void intel_guc_submission_disable(struct intel_guc *guc)
guc_proc_desc_fini(guc);
}
-static bool __guc_submission_support(struct intel_guc *guc)
+static bool __guc_submission_selected(struct intel_guc *guc)
{
- /* XXX: GuC submission is unavailable for now */
- return false;
-
- if (!intel_guc_is_supported(guc))
+ if (!intel_guc_submission_is_supported(guc))
return false;
return i915_modparams.enable_guc & ENABLE_GUC_SUBMISSION;
@@ -673,7 +670,7 @@ static bool __guc_submission_support(struct intel_guc *guc)
void intel_guc_submission_init_early(struct intel_guc *guc)
{
- guc->submission_supported = __guc_submission_support(guc);
+ guc->submission_selected = __guc_submission_selected(guc);
}
bool intel_engine_in_guc_submission_mode(const struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index d57b731952ef..7e112d4ebdc5 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -49,7 +49,7 @@ static void __confirm_options(struct intel_uc *uc)
"enable_guc=%d (guc:%s submission:%s huc:%s)\n",
i915_modparams.enable_guc,
yesno(intel_uc_wants_guc(uc)),
- yesno(intel_uc_uses_guc_submission(uc)),
+ yesno(intel_uc_wants_guc_submission(uc)),
yesno(intel_uc_wants_huc(uc)));
if (i915_modparams.enable_guc == -1)
@@ -57,7 +57,7 @@ static void __confirm_options(struct intel_uc *uc)
if (i915_modparams.enable_guc == 0) {
GEM_BUG_ON(intel_uc_wants_guc(uc));
- GEM_BUG_ON(intel_uc_uses_guc_submission(uc));
+ GEM_BUG_ON(intel_uc_wants_guc_submission(uc));
GEM_BUG_ON(intel_uc_wants_huc(uc));
return;
}
@@ -288,7 +288,7 @@ static int __uc_init(struct intel_uc *uc)
return -ENOMEM;
/* XXX: GuC submission is unavailable for now */
- GEM_BUG_ON(intel_uc_supports_guc_submission(uc));
+ GEM_BUG_ON(intel_uc_uses_guc_submission(uc));
ret = intel_guc_init(guc);
if (ret)
@@ -420,7 +420,7 @@ static int __uc_init_hw(struct intel_uc *uc)
if (!intel_uc_fw_is_available(&guc->fw)) {
ret = __uc_check_hw(uc) ||
intel_uc_fw_is_overridden(&guc->fw) ||
- intel_uc_supports_guc_submission(uc) ?
+ intel_uc_wants_guc_submission(uc) ?
intel_uc_fw_status_to_error(guc->fw.status) : 0;
goto err_out;
}
@@ -472,14 +472,14 @@ static int __uc_init_hw(struct intel_uc *uc)
if (ret)
goto err_communication;
- if (intel_uc_supports_guc_submission(uc))
+ if (intel_uc_uses_guc_submission(uc))
intel_guc_submission_enable(guc);
dev_info(i915->drm.dev, "%s firmware %s version %u.%u %s:%s\n",
intel_uc_fw_type_repr(INTEL_UC_FW_TYPE_GUC), guc->fw.path,
guc->fw.major_ver_found, guc->fw.minor_ver_found,
"submission",
- enableddisabled(intel_uc_supports_guc_submission(uc)));
+ enableddisabled(intel_uc_uses_guc_submission(uc)));
if (intel_uc_uses_huc(uc)) {
dev_info(i915->drm.dev, "%s firmware %s version %u.%u %s:%s\n",
@@ -521,7 +521,7 @@ static void __uc_fini_hw(struct intel_uc *uc)
if (!intel_guc_is_running(guc))
return;
- if (intel_uc_supports_guc_submission(uc))
+ if (intel_uc_uses_guc_submission(uc))
intel_guc_submission_disable(guc);
if (guc_communication_enabled(guc))
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
index 2d9f17196761..78350cdc2d63 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
@@ -61,33 +61,24 @@ int intel_uc_runtime_resume(struct intel_uc *uc);
* - In use: wanted and firmware found on the system.
*/
-#define __uc_state_checker(x, state, required) \
-static inline bool intel_uc_##state##_##x(struct intel_uc *uc) \
+#define __uc_state_checker(x, func, state, required) \
+static inline bool intel_uc_##state##_##func(struct intel_uc *uc) \
{ \
- return intel_##x##_is_##required(&uc->x); \
+ return intel_##func##_is_##required(&uc->x); \
}
-#define uc_state_checkers(x) \
-__uc_state_checker(x, supports, supported) \
-__uc_state_checker(x, wants, wanted) \
-__uc_state_checker(x, uses, used)
+#define uc_state_checkers(x, func) \
+__uc_state_checker(x, func, supports, supported) \
+__uc_state_checker(x, func, wants, wanted) \
+__uc_state_checker(x, func, uses, used)
-uc_state_checkers(guc);
-uc_state_checkers(huc);
+uc_state_checkers(guc, guc);
+uc_state_checkers(huc, huc);
+uc_state_checkers(guc, guc_submission);
#undef uc_state_checkers
#undef __uc_state_checker
-static inline bool intel_uc_supports_guc_submission(struct intel_uc *uc)
-{
- return intel_guc_is_submission_supported(&uc->guc);
-}
-
-static inline bool intel_uc_uses_guc_submission(struct intel_uc *uc)
-{
- return intel_guc_is_submission_supported(&uc->guc);
-}
-
#define intel_uc_ops_function(_NAME, _OPS, _TYPE, _RET) \
static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \
{ \
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 5fe00ee6bd1b..e8c0885df978 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1247,7 +1247,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
intel_context_set_single_submission(ce);
/* Max ring buffer size */
- if (!intel_uc_uses_guc_submission(&engine->gt->uc)) {
+ if (!intel_uc_wants_guc_submission(&engine->gt->uc)) {
const unsigned int ring_size = 512 * SZ_4K;
ce->ring = __intel_context_ring_size(ring_size);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 24d581c63667..b1469625c85a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2042,10 +2042,4 @@ i915_coherent_map_type(struct drm_i915_private *i915)
return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
}
-static inline bool intel_guc_submission_is_enabled(struct intel_guc *guc)
-{
- return intel_guc_is_submission_supported(guc) &&
- intel_guc_is_running(guc);
-}
-
#endif
diff --git a/drivers/gpu/drm/i915/intel_gvt.c b/drivers/gpu/drm/i915/intel_gvt.c
index 481c6de9f4d6..8f1ed15c0ed8 100644
--- a/drivers/gpu/drm/i915/intel_gvt.c
+++ b/drivers/gpu/drm/i915/intel_gvt.c
@@ -103,7 +103,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
return 0;
}
- if (intel_uc_uses_guc_submission(&dev_priv->gt.uc)) {
+ if (intel_uc_wants_guc_submission(&dev_priv->gt.uc)) {
DRM_ERROR("i915 GVT-g loading failed due to Graphics virtualization is not yet supported with GuC submission\n");
return -EIO;
}
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 6/7] drm/i915/guc: Start considering GuC submission a proper back-end
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
` (4 preceding siblings ...)
2020-01-15 1:31 ` [Intel-gfx] [PATCH 5/7] drm/i915/guc: Apply new uC status tracking to GuC submission as well Daniele Ceraolo Spurio
@ 2020-01-15 1:31 ` Daniele Ceraolo Spurio
2020-01-15 1:31 ` [Intel-gfx] [PATCH 7/7] HAX: force enable_guc=2 Daniele Ceraolo Spurio
` (5 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-15 1:31 UTC (permalink / raw)
To: intel-gfx
Now that we commit early to using GuC, we can start setting up the
engine for GuC submission during engine_init, instead of initializing it
for execlists submission first and updating it later. Note that the
change is still mostly cosmetic, since the new GuC submission setup
function internally calls execlists code, with the only differences being
part of the execlists-only setup being skipped and a different irq mask.
The GuC submission setup is expect to change and diverge from the
execlists one with the new GuC interface.
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 10 +++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 42 ++++++++++-------
drivers/gpu/drm/i915/gt/intel_lrc.h | 2 +
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 47 ++++++++++++++-----
.../gpu/drm/i915/gt/uc/intel_guc_submission.h | 4 +-
5 files changed, 71 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index f451ef376548..3e05d7b8c8a6 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -39,6 +39,8 @@
#include "intel_reset.h"
#include "intel_ring.h"
+#include "uc/intel_guc_submission.h"
+
/* Haswell does have the CXT_SIZE register however it does not appear to be
* valid. Now, docs explain in dwords what is in the context object. The full
* size is 70720 bytes, however, the power context and execlist context will
@@ -766,7 +768,9 @@ int intel_engines_init(struct intel_gt *gt)
enum intel_engine_id id;
int err;
- if (HAS_EXECLISTS(gt->i915))
+ if (intel_uc_uses_guc_submission(>->uc))
+ setup = intel_guc_submission_setup;
+ else if (HAS_EXECLISTS(gt->i915))
setup = intel_execlists_submission_setup;
else
setup = intel_ring_submission_setup;
@@ -1303,7 +1307,9 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
}
- if (HAS_EXECLISTS(dev_priv)) {
+ if (intel_engine_in_guc_submission_mode(engine)) {
+ /* nothing to print yet */
+ } else if (HAS_EXECLISTS(dev_priv)) {
struct i915_request * const *port, *rq;
const u32 *hws =
&engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 9e430590fb3a..ffb61e513c51 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2941,7 +2941,7 @@ static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
-static int intel_init_workaround_bb(struct intel_engine_cs *engine)
+void intel_logical_ring_init_workaround_bb(struct intel_engine_cs *engine)
{
struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
@@ -2953,12 +2953,12 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
int ret;
if (engine->class != RENDER_CLASS)
- return 0;
+ return;
switch (INTEL_GEN(engine->i915)) {
case 12:
case 11:
- return 0;
+ return;
case 10:
wa_bb_fn[0] = gen10_init_indirectctx_bb;
wa_bb_fn[1] = NULL;
@@ -2973,13 +2973,13 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
break;
default:
MISSING_CASE(INTEL_GEN(engine->i915));
- return 0;
+ return;
}
ret = lrc_setup_wa_ctx(engine);
if (ret) {
DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
- return ret;
+ goto out;
}
page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
@@ -3008,7 +3008,16 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
if (ret)
lrc_destroy_wa_ctx(engine);
- return ret;
+out:
+ /*
+ * We continue even if we fail to initialize WA batch
+ * because we only expect rare glitches but nothing
+ * critical to prevent us from using GPU
+ */
+ if (ret)
+ DRM_ERROR("WA batch buffer initialization failed\n");
+
+ return;
}
static void enable_execlists(struct intel_engine_cs *engine)
@@ -3974,6 +3983,14 @@ static void rcs_submission_override(struct intel_engine_cs *engine)
}
}
+void intel_execlists_submission_vfuncs(struct intel_engine_cs *engine)
+{
+ logical_ring_default_vfuncs(engine);
+
+ if (engine->class == RENDER_CLASS)
+ rcs_submission_override(engine);
+}
+
int intel_execlists_submission_setup(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -3986,19 +4003,10 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
timer_setup(&engine->execlists.timer, execlists_timeslice, 0);
timer_setup(&engine->execlists.preempt, execlists_preempt, 0);
- logical_ring_default_vfuncs(engine);
+ intel_execlists_submission_vfuncs(engine);
logical_ring_default_irqs(engine);
- if (engine->class == RENDER_CLASS)
- rcs_submission_override(engine);
-
- if (intel_init_workaround_bb(engine))
- /*
- * We continue even if we fail to initialize WA batch
- * because we only expect rare glitches but nothing
- * critical to prevent us from using GPU
- */
- DRM_ERROR("WA batch buffer initialization failed\n");
+ intel_logical_ring_init_workaround_bb(engine);
if (HAS_LOGICAL_RING_ELSQ(i915)) {
execlists->submit_reg = uncore->regs +
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
index dfbc214e14f5..354bb900da68 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.h
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
@@ -80,9 +80,11 @@ enum {
};
/* Logical Rings */
+void intel_logical_ring_init_workaround_bb(struct intel_engine_cs *engine);
void intel_logical_ring_cleanup(struct intel_engine_cs *engine);
int intel_execlists_submission_setup(struct intel_engine_cs *engine);
+void intel_execlists_submission_vfuncs(struct intel_engine_cs *engine);
/* Logical Ring Contexts */
/* At the start of the context image is its per-process HWS page */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 1beaa77f9bb6..b6fecead9697 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -605,21 +605,47 @@ static void guc_set_default_submission(struct intel_engine_cs *engine)
engine->flags &= ~I915_ENGINE_SUPPORTS_STATS;
engine->flags |= I915_ENGINE_NEEDS_BREADCRUMB_TASKLET;
+}
+
+static inline void guc_default_irqs(struct intel_engine_cs *engine)
+{
+ /*
+ * Pre-gen11 irqs share registers across engines and therefore need a
+ * shift, but we don't support GuC submission pre-gen11 so we don't
+ * bother.
+ */
+ GEM_BUG_ON(INTEL_GEN(engine->i915) < 11);
/*
- * For the breadcrumb irq to work we need the interrupts to stay
- * enabled. However, on all platforms on which we'll have support for
- * GuC submission we don't allow disabling the interrupts at runtime, so
- * we're always safe with the current flow.
+ * We're emulating execlists but we don't get the ctx switch interrupt,
+ * so we instead use the user interrupt to re-schedule the tasklet and
+ * therefore need to keep it enabled.
+ * We should be able to drop this with the new interface after we remove
+ * the execlists emulation.
*/
- GEM_BUG_ON(engine->irq_enable || engine->irq_disable);
+ engine->irq_keep_mask = GT_RENDER_USER_INTERRUPT;
+}
+
+int intel_guc_submission_setup(struct intel_engine_cs *engine)
+{
+ GEM_BUG_ON(!intel_uc_uses_guc_submission(&engine->gt->uc));
+
+ tasklet_init(&engine->execlists.tasklet,
+ guc_submission_tasklet, (unsigned long)engine);
+
+ /* XXX: still mirroring execlists. Will diverge with new interface */
+ intel_execlists_submission_vfuncs(engine);
+ engine->set_default_submission = guc_set_default_submission;
+
+ guc_default_irqs(engine);
+ intel_logical_ring_init_workaround_bb(engine);
+
+ return 0;
}
void intel_guc_submission_enable(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
- struct intel_engine_cs *engine;
- enum intel_engine_id id;
/*
* We're using GuC work items for submitting work through GuC. Since
@@ -630,7 +656,7 @@ void intel_guc_submission_enable(struct intel_guc *guc)
* and it is guaranteed that it will remove the work item from the
* queue before our request is completed.
*/
- BUILD_BUG_ON(ARRAY_SIZE(engine->execlists.inflight) *
+ BUILD_BUG_ON(EXECLIST_MAX_PORTS *
sizeof(struct guc_wq_item) *
I915_NUM_ENGINES > GUC_WQ_SIZE);
@@ -639,11 +665,6 @@ void intel_guc_submission_enable(struct intel_guc *guc)
/* Take over from manual control of ELSP (execlists) */
guc_interrupts_capture(gt);
-
- for_each_engine(engine, gt, id) {
- engine->set_default_submission = guc_set_default_submission;
- engine->set_default_submission(engine);
- }
}
void intel_guc_submission_disable(struct intel_guc *guc)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
index e402a2932592..696b03e3c515 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h
@@ -16,8 +16,8 @@ int intel_guc_submission_init(struct intel_guc *guc);
void intel_guc_submission_enable(struct intel_guc *guc);
void intel_guc_submission_disable(struct intel_guc *guc);
void intel_guc_submission_fini(struct intel_guc *guc);
-int intel_guc_preempt_work_create(struct intel_guc *guc);
-void intel_guc_preempt_work_destroy(struct intel_guc *guc);
+
+int intel_guc_submission_setup(struct intel_engine_cs *engine);
bool intel_engine_in_guc_submission_mode(const struct intel_engine_cs *engine);
#endif
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH 7/7] HAX: force enable_guc=2
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
` (5 preceding siblings ...)
2020-01-15 1:31 ` [Intel-gfx] [PATCH 6/7] drm/i915/guc: Start considering GuC submission a proper back-end Daniele Ceraolo Spurio
@ 2020-01-15 1:31 ` Daniele Ceraolo Spurio
2020-01-15 2:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Commit early to GuC Patchwork
` (4 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-15 1:31 UTC (permalink / raw)
To: intel-gfx
From: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 31b88f297fbc..acda9f2a1207 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,7 +54,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, 2) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
--
2.24.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Commit early to GuC
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
` (6 preceding siblings ...)
2020-01-15 1:31 ` [Intel-gfx] [PATCH 7/7] HAX: force enable_guc=2 Daniele Ceraolo Spurio
@ 2020-01-15 2:09 ` Patchwork
2020-01-15 2:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-01-15 2:09 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Commit early to GuC
URL : https://patchwork.freedesktop.org/series/72031/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c114a4a8e211 drm/i915/guc: Kill USES_GUC macro
033b28e648f2 drm/i915/guc: Kill USES_GUC_SUBMISSION macro
4eb628448c92 drm/i915/uc: Improve tracking of uC init status
-:208: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#208: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc.h:64:
+#define __uc_state_checker(x, state, required) \
+static inline bool intel_uc_##state##_##x(struct intel_uc *uc) \
+{ \
+ return intel_##x##_is_##required(&uc->x); \
}
-:214: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#214: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc.h:70:
+#define uc_state_checkers(x) \
+__uc_state_checker(x, supports, supported) \
+__uc_state_checker(x, wants, wanted) \
+__uc_state_checker(x, uses, used)
-:214: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#214: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc.h:70:
+#define uc_state_checkers(x) \
+__uc_state_checker(x, supports, supported) \
+__uc_state_checker(x, wants, wanted) \
+__uc_state_checker(x, uses, used)
total: 1 errors, 0 warnings, 2 checks, 190 lines checked
827bb05aa73b drm/i915/uc: Abort early on uc_init failure
e46e55860fda drm/i915/guc: Apply new uC status tracking to GuC submission as well
-:211: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'x' may be better as '(x)' to avoid precedence issues
#211: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc.h:64:
+#define __uc_state_checker(x, func, state, required) \
+static inline bool intel_uc_##state##_##func(struct intel_uc *uc) \
{ \
+ return intel_##func##_is_##required(&uc->x); \
}
-:222: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#222: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc.h:70:
+#define uc_state_checkers(x, func) \
+__uc_state_checker(x, func, supports, supported) \
+__uc_state_checker(x, func, wants, wanted) \
+__uc_state_checker(x, func, uses, used)
-:222: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'x' - possible side-effects?
#222: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc.h:70:
+#define uc_state_checkers(x, func) \
+__uc_state_checker(x, func, supports, supported) \
+__uc_state_checker(x, func, wants, wanted) \
+__uc_state_checker(x, func, uses, used)
-:222: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'func' - possible side-effects?
#222: FILE: drivers/gpu/drm/i915/gt/uc/intel_uc.h:70:
+#define uc_state_checkers(x, func) \
+__uc_state_checker(x, func, supports, supported) \
+__uc_state_checker(x, func, wants, wanted) \
+__uc_state_checker(x, func, uses, used)
total: 1 errors, 0 warnings, 3 checks, 225 lines checked
6e76e718c238 drm/i915/guc: Start considering GuC submission a proper back-end
522c1abc9b0b HAX: force enable_guc=2
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 8 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Commit early to GuC
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
` (7 preceding siblings ...)
2020-01-15 2:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Commit early to GuC Patchwork
@ 2020-01-15 2:29 ` Patchwork
2020-01-15 2:29 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-01-15 2:29 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Commit early to GuC
URL : https://patchwork.freedesktop.org/series/72031/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7746 -> Patchwork_16103
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/index.html
Known issues
------------
Here are the changes found in Patchwork_16103 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][1] -> [FAIL][2] ([fdo#111096] / [i915#323])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_close_race@basic-threads:
- fi-byt-n2820: [TIMEOUT][3] ([fdo#112271] / [i915#816]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/fi-byt-n2820/igt@gem_close_race@basic-threads.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/fi-byt-n2820/igt@gem_close_race@basic-threads.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770: [DMESG-FAIL][5] ([i915#770]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/fi-hsw-4770/igt@i915_selftest@live_blt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-icl-u2: [FAIL][7] ([fdo#109635]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
#### Warnings ####
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-icl-u2: [DMESG-WARN][9] ([IGT#4] / [i915#263]) -> [FAIL][10] ([i915#217])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#4]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/4
[fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
[i915#263]: https://gitlab.freedesktop.org/drm/intel/issues/263
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#770]: https://gitlab.freedesktop.org/drm/intel/issues/770
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
[i915#937]: https://gitlab.freedesktop.org/drm/intel/issues/937
Participating hosts (42 -> 39)
------------------------------
Additional (8): fi-bsw-kefka fi-elk-e7500 fi-pnv-d510 fi-icl-y fi-icl-guc fi-icl-dsi fi-bsw-nick fi-snb-2600
Missing (11): fi-kbl-soraka fi-hsw-4770r fi-ilk-m540 fi-hsw-4200u fi-skl-6770hq fi-byt-squawks fi-bsw-cyan fi-gdg-551 fi-skl-lmem fi-tgl-y fi-kbl-r
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7746 -> Patchwork_16103
CI-20190529: 20190529
CI_DRM_7746: 84d16aa256204bccaaf382504a69fe0822e67ba0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5365: e9ec0ed63b25c86861ffac3c8601cc4d1b910b65 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16103: 522c1abc9b0b19d9d332e20848cdde8f4a27839d @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_16103/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 122 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:93: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1282: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
522c1abc9b0b HAX: force enable_guc=2
6e76e718c238 drm/i915/guc: Start considering GuC submission a proper back-end
e46e55860fda drm/i915/guc: Apply new uC status tracking to GuC submission as well
827bb05aa73b drm/i915/uc: Abort early on uc_init failure
4eb628448c92 drm/i915/uc: Improve tracking of uC init status
033b28e648f2 drm/i915/guc: Kill USES_GUC_SUBMISSION macro
c114a4a8e211 drm/i915/guc: Kill USES_GUC macro
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: warning for Commit early to GuC
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
` (8 preceding siblings ...)
2020-01-15 2:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-01-15 2:29 ` Patchwork
2020-01-15 8:40 ` [Intel-gfx] [PATCH 0/7] " Chris Wilson
2020-01-17 8:38 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
11 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-01-15 2:29 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Commit early to GuC
URL : https://patchwork.freedesktop.org/series/72031/
State : warning
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 122 modules
ERROR: "__udivdi3" [drivers/gpu/drm/amd/amdgpu/amdgpu.ko] undefined!
scripts/Makefile.modpost:93: recipe for target '__modpost' failed
make[1]: *** [__modpost] Error 1
Makefile:1282: recipe for target 'modules' failed
make: *** [modules] Error 2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/build_32bit.log
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 0/7] Commit early to GuC
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
` (9 preceding siblings ...)
2020-01-15 2:29 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
@ 2020-01-15 8:40 ` Chris Wilson
2020-01-15 15:57 ` Daniele Ceraolo Spurio
2020-01-17 8:38 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
11 siblings, 1 reply; 26+ messages in thread
From: Chris Wilson @ 2020-01-15 8:40 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Quoting Daniele Ceraolo Spurio (2020-01-15 01:31:36)
> We currently wait until we attempt to load the GuC to confirm if we're
> in GuC mode or not, at which point a lot of the engine setup has already
> happened and needs to be updated for GuC submission. To allow us to get
> the setup done directly into GuC mode, we need to commit to using GuC
> as soon as possible.
I think this is the wrong direction; as I thought the goal was to allow
delayed loading of firmware, even going as far as allowing the system to
run a browser for the user to get the firmware first. I may be
completely wrong about that, but imho I never want to have to build
firmware images into the kernel.
The transition from execlists to guc could be just set-wedged; delete
old engines, build guc engines. [This should also work for guc -> guc.]
Throwing away context state is ugly, but simple enough.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 0/7] Commit early to GuC
2020-01-15 8:40 ` [Intel-gfx] [PATCH 0/7] " Chris Wilson
@ 2020-01-15 15:57 ` Daniele Ceraolo Spurio
2020-01-15 16:18 ` Chris Wilson
0 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-15 15:57 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 1/15/2020 12:40 AM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2020-01-15 01:31:36)
>> We currently wait until we attempt to load the GuC to confirm if we're
>> in GuC mode or not, at which point a lot of the engine setup has already
>> happened and needs to be updated for GuC submission. To allow us to get
>> the setup done directly into GuC mode, we need to commit to using GuC
>> as soon as possible.
> I think this is the wrong direction; as I thought the goal was to allow
> delayed loading of firmware, even going as far as allowing the system to
> run a browser for the user to get the firmware first. I may be
We do indeed want to keep supporting execlists mode even as some HW
features move to the GuC to allow the user to get to the binaries, but
we don't want to switch between the 2 modes without a reboot. Switching
between the 2 modes is not a HW capability that we're committed to; the
guc->elsp transition is already not possible, while the elsp->guc one
still seems to work, but who knows for how long it will?
This series is also not really changing the commitment at the
implementation level, just making it "official" and acting based on
that. Even without these patches, if the blobs are on the system we will
attempt to get into GuC mode unless we get an allocation failure or
something similar, in which case it is extremely likely that the
fall-back to non-guc will not work either.
> completely wrong about that, but imho I never want to have to build
> firmware images into the kernel.
I do 100% agree with this statement, although I'm not sure how this
relates to the series. Are you planning to pull some of the engine setup
to an even earlier point?
>
> The transition from execlists to guc could be just set-wedged; delete
> old engines, build guc engines. [This should also work for guc -> guc.]
> Throwing away context state is ugly, but simple enough.
As mentioned above, we can't switch between elsp and GuC modes so this
transition would have to be done before the first submission to HW. Why
not go directly in GuC mode then?
Daniele
> -Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 0/7] Commit early to GuC
2020-01-15 15:57 ` Daniele Ceraolo Spurio
@ 2020-01-15 16:18 ` Chris Wilson
2020-01-15 20:46 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 26+ messages in thread
From: Chris Wilson @ 2020-01-15 16:18 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
Quoting Daniele Ceraolo Spurio (2020-01-15 15:57:27)
>
>
> On 1/15/2020 12:40 AM, Chris Wilson wrote:
> > Quoting Daniele Ceraolo Spurio (2020-01-15 01:31:36)
> >> We currently wait until we attempt to load the GuC to confirm if we're
> >> in GuC mode or not, at which point a lot of the engine setup has already
> >> happened and needs to be updated for GuC submission. To allow us to get
> >> the setup done directly into GuC mode, we need to commit to using GuC
> >> as soon as possible.
> > I think this is the wrong direction; as I thought the goal was to allow
> > delayed loading of firmware, even going as far as allowing the system to
> > run a browser for the user to get the firmware first. I may be
>
> We do indeed want to keep supporting execlists mode even as some HW
> features move to the GuC to allow the user to get to the binaries, but
> we don't want to switch between the 2 modes without a reboot. Switching
> between the 2 modes is not a HW capability that we're committed to; the
> guc->elsp transition is already not possible, while the elsp->guc one
> still seems to work, but who knows for how long it will?
>
> This series is also not really changing the commitment at the
> implementation level, just making it "official" and acting based on
> that. Even without these patches, if the blobs are on the system we will
> attempt to get into GuC mode unless we get an allocation failure or
> something similar, in which case it is extremely likely that the
> fall-back to non-guc will not work either.
>
> > completely wrong about that, but imho I never want to have to build
> > firmware images into the kernel.
>
> I do 100% agree with this statement, although I'm not sure how this
> relates to the series. Are you planning to pull some of the engine setup
> to an even earlier point?
>
> >
> > The transition from execlists to guc could be just set-wedged; delete
> > old engines, build guc engines. [This should also work for guc -> guc.]
> > Throwing away context state is ugly, but simple enough.
>
> As mentioned above, we can't switch between elsp and GuC modes so this
> transition would have to be done before the first submission to HW. Why
> not go directly in GuC mode then?
So the problem is if we can't freely switch (we can never power down the
guc, that seems unlikely?) then we can't make a decision on which mode
to run (and which engines to initialise) until userspace is active and
has committed to supplying or not supplying a fw image. Which puts us in
a catch-22 of wanting to register the driver with userspace before we
have finalized initialisation.
If the transition is impossible, it seems like you have no choice but to
require the fw image at initialisation. I do not understand why it has
to be that way, seems such a hindrance.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 0/7] Commit early to GuC
2020-01-15 16:18 ` Chris Wilson
@ 2020-01-15 20:46 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-15 20:46 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 1/15/20 8:18 AM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2020-01-15 15:57:27)
>>
>>
>> On 1/15/2020 12:40 AM, Chris Wilson wrote:
>>> Quoting Daniele Ceraolo Spurio (2020-01-15 01:31:36)
>>>> We currently wait until we attempt to load the GuC to confirm if we're
>>>> in GuC mode or not, at which point a lot of the engine setup has already
>>>> happened and needs to be updated for GuC submission. To allow us to get
>>>> the setup done directly into GuC mode, we need to commit to using GuC
>>>> as soon as possible.
>>> I think this is the wrong direction; as I thought the goal was to allow
>>> delayed loading of firmware, even going as far as allowing the system to
>>> run a browser for the user to get the firmware first. I may be
>>
>> We do indeed want to keep supporting execlists mode even as some HW
>> features move to the GuC to allow the user to get to the binaries, but
>> we don't want to switch between the 2 modes without a reboot. Switching
>> between the 2 modes is not a HW capability that we're committed to; the
>> guc->elsp transition is already not possible, while the elsp->guc one
>> still seems to work, but who knows for how long it will?
>>
>> This series is also not really changing the commitment at the
>> implementation level, just making it "official" and acting based on
>> that. Even without these patches, if the blobs are on the system we will
>> attempt to get into GuC mode unless we get an allocation failure or
>> something similar, in which case it is extremely likely that the
>> fall-back to non-guc will not work either.
>>
>>> completely wrong about that, but imho I never want to have to build
>>> firmware images into the kernel.
>>
>> I do 100% agree with this statement, although I'm not sure how this
>> relates to the series. Are you planning to pull some of the engine setup
>> to an even earlier point?
>>
>>>
>>> The transition from execlists to guc could be just set-wedged; delete
>>> old engines, build guc engines. [This should also work for guc -> guc.]
>>> Throwing away context state is ugly, but simple enough.
>>
>> As mentioned above, we can't switch between elsp and GuC modes so this
>> transition would have to be done before the first submission to HW. Why
>> not go directly in GuC mode then?
>
> So the problem is if we can't freely switch (we can never power down the
> guc, that seems unlikely?) then we can't make a decision on which mode
AFAIU it's not the GuC itself that's the issue, but some of the other
units, some of which outside the GT, that can get locked in one mode
without being resettable (like what happens for the WOPCM regs for example).
> to run (and which engines to initialise) until userspace is active and
> has committed to supplying or not supplying a fw image. Which puts us in
> a catch-22 of wanting to register the driver with userspace before we
> have finalized initialisation.
I think this is the bit I'm missing. Why do you want userspace to
directly provide the firmware instead of fetching it from /lib/firmware
like we do now? The distros should pack the correct firmware in their
linux-firmware packages and it seems reasonable to me to expect the
system to be rebooted after fetching a binary by hand. We can move the
fetch to an earlier point in time if we need the info earlier, since it
does not require the HW to be ready.
>
> If the transition is impossible, it seems like you have no choice but to
> require the fw image at initialisation. I do not understand why it has
> to be that way, seems such a hindrance.
My understanding from the talk I had with the HW team when we realized
that the guc->elsp transition was broken on gen11 is that the HW expects
SW to pick a mode and stick to that. The elsp->guc transition seem to
still work, but there is no guarantee it will keep doing so in the
future and therefore it doesn't seem like a good idea to build on that.
Daniele
> -Chris
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915/guc: Kill USES_GUC macro
2020-01-15 1:31 ` [Intel-gfx] [PATCH 1/7] drm/i915/guc: Kill USES_GUC macro Daniele Ceraolo Spurio
@ 2020-01-16 19:42 ` Michal Wajdeczko
2020-01-16 20:24 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 26+ messages in thread
From: Michal Wajdeczko @ 2020-01-16 19:42 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 15 Jan 2020 02:31:37 +0100, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> use intel_uc_uses_guc() directly instead, to be consistent in the way we
> check what we want to do with the GuC.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 19 ++++++++++---------
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> 3 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 79096722ce16..bb4aa923dbd9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -462,7 +462,7 @@ static int ggtt_reserve_guc_top(struct i915_ggtt
> *ggtt)
> u64 size;
> int ret;
> - if (!USES_GUC(ggtt->vm.i915))
> + if (!intel_uc_uses_guc(&ggtt->vm.gt->uc))
> return 0;
> GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index d5a9b8a964c2..c2f480defc71 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1752,10 +1752,8 @@ stringify_guc_log_type(enum guc_log_buffer_type
> type)
> return "";
> }
> -static void i915_guc_log_info(struct seq_file *m,
> - struct drm_i915_private *dev_priv)
> +static void i915_guc_log_info(struct seq_file *m, struct intel_guc_log
hmm, s/dev_priv/guc_log changes look unrelated to main topic
can you move these changes to separate patch ?
> *log)
> {
> - struct intel_guc_log *log = &dev_priv->gt.uc.guc.log;
> enum guc_log_buffer_type type;
> if (!intel_guc_log_relay_created(log)) {
> @@ -1779,11 +1777,12 @@ static void i915_guc_log_info(struct seq_file *m,
> static int i915_guc_info(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> + struct intel_uc *uc = &dev_priv->gt.uc;
> - if (!USES_GUC(dev_priv))
> + if (!intel_uc_uses_guc(uc))
> return -ENODEV;
> - i915_guc_log_info(m, dev_priv);
> + i915_guc_log_info(m, &uc->guc.log);
> /* Add more as required ... */
> @@ -1884,11 +1883,12 @@ static int i915_guc_log_dump(struct seq_file *m,
> void *data)
> static int i915_guc_log_level_get(void *data, u64 *val)
> {
> struct drm_i915_private *dev_priv = data;
> + struct intel_uc *uc = &dev_priv->gt.uc;
> - if (!USES_GUC(dev_priv))
> + if (!intel_uc_uses_guc(uc))
> return -ENODEV;
> - *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log);
> + *val = intel_guc_log_get_level(&uc->guc.log);
> return 0;
> }
> @@ -1896,11 +1896,12 @@ static int i915_guc_log_level_get(void *data,
> u64 *val)
> static int i915_guc_log_level_set(void *data, u64 val)
> {
> struct drm_i915_private *dev_priv = data;
> + struct intel_uc *uc = &dev_priv->gt.uc;
> - if (!USES_GUC(dev_priv))
> + if (!intel_uc_uses_guc(uc))
> return -ENODEV;
> - return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val);
> + return intel_guc_log_set_level(&uc->guc.log, val);
> }
> DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index 077af22b8340..ad0019cd2604 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1719,7 +1719,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
> /* Having GuC is not the same as using GuC */
> -#define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc)
> #define
> USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
> #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro
2020-01-15 1:31 ` [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro Daniele Ceraolo Spurio
@ 2020-01-16 19:49 ` Michal Wajdeczko
2020-01-16 20:42 ` Daniele Ceraolo Spurio
2020-01-27 3:00 ` kbuild test robot
1 sibling, 1 reply; 26+ messages in thread
From: Michal Wajdeczko @ 2020-01-16 19:49 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
On Wed, 15 Jan 2020 02:31:38 +0100, Daniele Ceraolo Spurio
<daniele.ceraolospurio@intel.com> wrote:
> use intel_uc_uses_guc_submission() directly instead, to be consistent in
> the way we check what we want to do with the GuC.
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
with one small nit below
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 10 +++++-----
> drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
> drivers/gpu/drm/i915/gvt/scheduler.c | 3 ++-
> drivers/gpu/drm/i915/i915_debugfs.c | 6 +++---
> drivers/gpu/drm/i915/i915_drv.h | 3 ---
> drivers/gpu/drm/i915/intel_gvt.c | 2 +-
> 8 files changed, 14 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index a2e57e62af30..415e2d5e934b 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1454,7 +1454,7 @@ set_engines__load_balance(struct
> i915_user_extension __user *base, void *data)
> if (!HAS_EXECLISTS(set->ctx->i915))
> return -ENODEV;
> - if (USES_GUC_SUBMISSION(set->ctx->i915))
> + if (intel_uc_uses_guc_submission(&set->ctx->vm->gt->uc))
> return -ENODEV; /* not implement yet */
> if (get_user(idx, &ext->engine_index))
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index 3e5e6c86e843..c3514ec7b8db 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -1640,7 +1640,7 @@ static int igt_reset_engines_atomic(void *arg)
> if (!intel_has_reset_engine(gt))
> return 0;
> - if (USES_GUC_SUBMISSION(gt->i915))
> + if (intel_uc_uses_guc_submission(>->uc))
> return 0;
> igt_global_reset_lock(gt);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index 15cda024e3e4..b1c677b0d5ad 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -1555,7 +1555,7 @@ static int live_suppress_self_preempt(void *arg)
> if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
> return 0;
> - if (USES_GUC_SUBMISSION(gt->i915))
> + if (intel_uc_uses_guc_submission(>->uc))
> return 0; /* presume black blox */
> if (intel_vgpu_active(gt->i915))
> @@ -2781,7 +2781,7 @@ static int live_virtual_engine(void *arg)
> unsigned int class, inst;
> int err;
> - if (USES_GUC_SUBMISSION(gt->i915))
> + if (intel_uc_uses_guc_submission(>->uc))
> return 0;
> for_each_engine(engine, gt, id) {
> @@ -2914,7 +2914,7 @@ static int live_virtual_mask(void *arg)
> unsigned int class, inst;
> int err;
> - if (USES_GUC_SUBMISSION(gt->i915))
> + if (intel_uc_uses_guc_submission(>->uc))
> return 0;
> for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
> @@ -3052,7 +3052,7 @@ static int live_virtual_preserved(void *arg)
> * are preserved.
> */
> - if (USES_GUC_SUBMISSION(gt->i915))
> + if (intel_uc_uses_guc_submission(>->uc))
> return 0;
> /* As we use CS_GPR we cannot run before they existed on all engines. */
> @@ -3276,7 +3276,7 @@ static int live_virtual_bond(void *arg)
> unsigned int class, inst;
> int err;
> - if (USES_GUC_SUBMISSION(gt->i915))
> + if (intel_uc_uses_guc_submission(>->uc))
> return 0;
> for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
> diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c
> b/drivers/gpu/drm/i915/gt/selftest_reset.c
> index 6ad6aca315f6..35406ecdf0b2 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_reset.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
> @@ -115,7 +115,7 @@ static int igt_atomic_engine_reset(void *arg)
> if (!intel_has_reset_engine(gt))
> return 0;
> - if (USES_GUC_SUBMISSION(gt->i915))
> + if (intel_uc_uses_guc_submission(>->uc))
> return 0;
> intel_gt_pm_get(gt);
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
> b/drivers/gpu/drm/i915/gvt/scheduler.c
> index 685d1e04a5ff..5fe00ee6bd1b 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -1246,7 +1246,8 @@ int intel_vgpu_setup_submission(struct intel_vgpu
> *vgpu)
> ce->vm = i915_vm_get(&ppgtt->vm);
> intel_context_set_single_submission(ce);
> - if (!USES_GUC_SUBMISSION(i915)) { /* Max ring buffer size */
> + /* Max ring buffer size */
> + if (!intel_uc_uses_guc_submission(&engine->gt->uc)) {
> const unsigned int ring_size = 512 * SZ_4K;
> ce->ring = __intel_context_ring_size(ring_size);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index c2f480defc71..823a033ffcd0 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1792,11 +1792,11 @@ static int i915_guc_info(struct seq_file *m,
> void *data)
> static int i915_guc_stage_pool(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - const struct intel_guc *guc = &dev_priv->gt.uc.guc;
> - struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
> + struct intel_uc *uc = &dev_priv->gt.uc;
> + struct guc_stage_desc *desc = uc->guc.stage_desc_pool_vaddr;
> int index;
> - if (!USES_GUC_SUBMISSION(dev_priv))
> + if (!intel_uc_uses_guc_submission(uc))
> return -ENODEV;
> for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index ad0019cd2604..24d581c63667 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1718,9 +1718,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
> -/* Having GuC is not the same as using GuC */
> -#define
> USES_GUC_SUBMISSION(dev_priv) intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
> -
> #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
> #define
> HAS_GLOBAL_MOCS_REGISTERS(dev_priv) (INTEL_INFO(dev_priv)->has_global_mocs)
> diff --git a/drivers/gpu/drm/i915/intel_gvt.c
> b/drivers/gpu/drm/i915/intel_gvt.c
> index 2b6c016387c2..481c6de9f4d6 100644
> --- a/drivers/gpu/drm/i915/intel_gvt.c
> +++ b/drivers/gpu/drm/i915/intel_gvt.c
> @@ -103,7 +103,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
> return 0;
> }
> - if (USES_GUC_SUBMISSION(dev_priv)) {
> + if (intel_uc_uses_guc_submission(&dev_priv->gt.uc)) {
nit: that old macro was helpful exactly in cases where only dev_priv
is known and component might have no idea where to find uc
maybe we should have helper like:
#define to_intel_uc(i915) (&(i915)->gt.uc)
(but likely Jani will complain)
> DRM_ERROR("i915 GVT-g loading failed due to Graphics virtualization
> is not yet supported with GuC submission\n");
> return -EIO;
> }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 1/7] drm/i915/guc: Kill USES_GUC macro
2020-01-16 19:42 ` Michal Wajdeczko
@ 2020-01-16 20:24 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-16 20:24 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
On 1/16/20 11:42 AM, Michal Wajdeczko wrote:
> On Wed, 15 Jan 2020 02:31:37 +0100, Daniele Ceraolo Spurio
> <daniele.ceraolospurio@intel.com> wrote:
>
>> use intel_uc_uses_guc() directly instead, to be consistent in the way we
>> check what we want to do with the GuC.
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: John Harrison <John.C.Harrison@Intel.com>
>> Cc: Matthew Brost <matthew.brost@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
>> drivers/gpu/drm/i915/i915_debugfs.c | 19 ++++++++++---------
>> drivers/gpu/drm/i915/i915_drv.h | 1 -
>> 3 files changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> index 79096722ce16..bb4aa923dbd9 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> @@ -462,7 +462,7 @@ static int ggtt_reserve_guc_top(struct i915_ggtt
>> *ggtt)
>> u64 size;
>> int ret;
>> - if (!USES_GUC(ggtt->vm.i915))
>> + if (!intel_uc_uses_guc(&ggtt->vm.gt->uc))
>> return 0;
>> GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index d5a9b8a964c2..c2f480defc71 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1752,10 +1752,8 @@ stringify_guc_log_type(enum guc_log_buffer_type
>> type)
>> return "";
>> }
>> -static void i915_guc_log_info(struct seq_file *m,
>> - struct drm_i915_private *dev_priv)
>> +static void i915_guc_log_info(struct seq_file *m, struct intel_guc_log
>
> hmm, s/dev_priv/guc_log changes look unrelated to main topic
> can you move these changes to separate patch ?
It made sense to me to do the changes since I now had the uc variable at
hand, but I can easily split them as a prep patch.
Daniele
>
>> *log)
>> {
>> - struct intel_guc_log *log = &dev_priv->gt.uc.guc.log;
>> enum guc_log_buffer_type type;
>> if (!intel_guc_log_relay_created(log)) {
>> @@ -1779,11 +1777,12 @@ static void i915_guc_log_info(struct seq_file *m,
>> static int i915_guc_info(struct seq_file *m, void *data)
>> {
>> struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> + struct intel_uc *uc = &dev_priv->gt.uc;
>> - if (!USES_GUC(dev_priv))
>> + if (!intel_uc_uses_guc(uc))
>> return -ENODEV;
>> - i915_guc_log_info(m, dev_priv);
>> + i915_guc_log_info(m, &uc->guc.log);
>> /* Add more as required ... */
>> @@ -1884,11 +1883,12 @@ static int i915_guc_log_dump(struct seq_file
>> *m, void *data)
>> static int i915_guc_log_level_get(void *data, u64 *val)
>> {
>> struct drm_i915_private *dev_priv = data;
>> + struct intel_uc *uc = &dev_priv->gt.uc;
>> - if (!USES_GUC(dev_priv))
>> + if (!intel_uc_uses_guc(uc))
>> return -ENODEV;
>> - *val = intel_guc_log_get_level(&dev_priv->gt.uc.guc.log);
>> + *val = intel_guc_log_get_level(&uc->guc.log);
>> return 0;
>> }
>> @@ -1896,11 +1896,12 @@ static int i915_guc_log_level_get(void *data,
>> u64 *val)
>> static int i915_guc_log_level_set(void *data, u64 val)
>> {
>> struct drm_i915_private *dev_priv = data;
>> + struct intel_uc *uc = &dev_priv->gt.uc;
>> - if (!USES_GUC(dev_priv))
>> + if (!intel_uc_uses_guc(uc))
>> return -ENODEV;
>> - return intel_guc_log_set_level(&dev_priv->gt.uc.guc.log, val);
>> + return intel_guc_log_set_level(&uc->guc.log, val);
>> }
>> DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_level_fops,
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 077af22b8340..ad0019cd2604 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1719,7 +1719,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
>> /* Having GuC is not the same as using GuC */
>> -#define USES_GUC(dev_priv) intel_uc_uses_guc(&(dev_priv)->gt.uc)
>> #define USES_GUC_SUBMISSION(dev_priv)
>> intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
>> #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro
2020-01-16 19:49 ` Michal Wajdeczko
@ 2020-01-16 20:42 ` Daniele Ceraolo Spurio
2020-01-16 22:49 ` Michal Wajdeczko
0 siblings, 1 reply; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-16 20:42 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
On 1/16/20 11:49 AM, Michal Wajdeczko wrote:
> On Wed, 15 Jan 2020 02:31:38 +0100, Daniele Ceraolo Spurio
> <daniele.ceraolospurio@intel.com> wrote:
>
>> use intel_uc_uses_guc_submission() directly instead, to be consistent in
>> the way we check what we want to do with the GuC.
>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: John Harrison <John.C.Harrison@Intel.com>
>> Cc: Matthew Brost <matthew.brost@intel.com>
>
> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>
> with one small nit below
>
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +-
>> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
>> drivers/gpu/drm/i915/gt/selftest_lrc.c | 10 +++++-----
>> drivers/gpu/drm/i915/gt/selftest_reset.c | 2 +-
>> drivers/gpu/drm/i915/gvt/scheduler.c | 3 ++-
>> drivers/gpu/drm/i915/i915_debugfs.c | 6 +++---
>> drivers/gpu/drm/i915/i915_drv.h | 3 ---
>> drivers/gpu/drm/i915/intel_gvt.c | 2 +-
>> 8 files changed, 14 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> index a2e57e62af30..415e2d5e934b 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> @@ -1454,7 +1454,7 @@ set_engines__load_balance(struct
>> i915_user_extension __user *base, void *data)
>> if (!HAS_EXECLISTS(set->ctx->i915))
>> return -ENODEV;
>> - if (USES_GUC_SUBMISSION(set->ctx->i915))
>> + if (intel_uc_uses_guc_submission(&set->ctx->vm->gt->uc))
>> return -ENODEV; /* not implement yet */
>> if (get_user(idx, &ext->engine_index))
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> index 3e5e6c86e843..c3514ec7b8db 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
>> @@ -1640,7 +1640,7 @@ static int igt_reset_engines_atomic(void *arg)
>> if (!intel_has_reset_engine(gt))
>> return 0;
>> - if (USES_GUC_SUBMISSION(gt->i915))
>> + if (intel_uc_uses_guc_submission(>->uc))
>> return 0;
>> igt_global_reset_lock(gt);
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> b/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> index 15cda024e3e4..b1c677b0d5ad 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
>> @@ -1555,7 +1555,7 @@ static int live_suppress_self_preempt(void *arg)
>> if (!HAS_LOGICAL_RING_PREEMPTION(gt->i915))
>> return 0;
>> - if (USES_GUC_SUBMISSION(gt->i915))
>> + if (intel_uc_uses_guc_submission(>->uc))
>> return 0; /* presume black blox */
>> if (intel_vgpu_active(gt->i915))
>> @@ -2781,7 +2781,7 @@ static int live_virtual_engine(void *arg)
>> unsigned int class, inst;
>> int err;
>> - if (USES_GUC_SUBMISSION(gt->i915))
>> + if (intel_uc_uses_guc_submission(>->uc))
>> return 0;
>> for_each_engine(engine, gt, id) {
>> @@ -2914,7 +2914,7 @@ static int live_virtual_mask(void *arg)
>> unsigned int class, inst;
>> int err;
>> - if (USES_GUC_SUBMISSION(gt->i915))
>> + if (intel_uc_uses_guc_submission(>->uc))
>> return 0;
>> for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
>> @@ -3052,7 +3052,7 @@ static int live_virtual_preserved(void *arg)
>> * are preserved.
>> */
>> - if (USES_GUC_SUBMISSION(gt->i915))
>> + if (intel_uc_uses_guc_submission(>->uc))
>> return 0;
>> /* As we use CS_GPR we cannot run before they existed on all
>> engines. */
>> @@ -3276,7 +3276,7 @@ static int live_virtual_bond(void *arg)
>> unsigned int class, inst;
>> int err;
>> - if (USES_GUC_SUBMISSION(gt->i915))
>> + if (intel_uc_uses_guc_submission(>->uc))
>> return 0;
>> for (class = 0; class <= MAX_ENGINE_CLASS; class++) {
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c
>> b/drivers/gpu/drm/i915/gt/selftest_reset.c
>> index 6ad6aca315f6..35406ecdf0b2 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_reset.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
>> @@ -115,7 +115,7 @@ static int igt_atomic_engine_reset(void *arg)
>> if (!intel_has_reset_engine(gt))
>> return 0;
>> - if (USES_GUC_SUBMISSION(gt->i915))
>> + if (intel_uc_uses_guc_submission(>->uc))
>> return 0;
>> intel_gt_pm_get(gt);
>> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
>> b/drivers/gpu/drm/i915/gvt/scheduler.c
>> index 685d1e04a5ff..5fe00ee6bd1b 100644
>> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
>> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
>> @@ -1246,7 +1246,8 @@ int intel_vgpu_setup_submission(struct
>> intel_vgpu *vgpu)
>> ce->vm = i915_vm_get(&ppgtt->vm);
>> intel_context_set_single_submission(ce);
>> - if (!USES_GUC_SUBMISSION(i915)) { /* Max ring buffer size */
>> + /* Max ring buffer size */
>> + if (!intel_uc_uses_guc_submission(&engine->gt->uc)) {
>> const unsigned int ring_size = 512 * SZ_4K;
>> ce->ring = __intel_context_ring_size(ring_size);
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index c2f480defc71..823a033ffcd0 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1792,11 +1792,11 @@ static int i915_guc_info(struct seq_file *m,
>> void *data)
>> static int i915_guc_stage_pool(struct seq_file *m, void *data)
>> {
>> struct drm_i915_private *dev_priv = node_to_i915(m->private);
>> - const struct intel_guc *guc = &dev_priv->gt.uc.guc;
>> - struct guc_stage_desc *desc = guc->stage_desc_pool_vaddr;
>> + struct intel_uc *uc = &dev_priv->gt.uc;
>> + struct guc_stage_desc *desc = uc->guc.stage_desc_pool_vaddr;
>> int index;
>> - if (!USES_GUC_SUBMISSION(dev_priv))
>> + if (!intel_uc_uses_guc_submission(uc))
>> return -ENODEV;
>> for (index = 0; index < GUC_MAX_STAGE_DESCRIPTORS; index++, desc++) {
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index ad0019cd2604..24d581c63667 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1718,9 +1718,6 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>> #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc)
>> -/* Having GuC is not the same as using GuC */
>> -#define USES_GUC_SUBMISSION(dev_priv)
>> intel_uc_uses_guc_submission(&(dev_priv)->gt.uc)
>> -
>> #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
>> #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)
>> (INTEL_INFO(dev_priv)->has_global_mocs)
>> diff --git a/drivers/gpu/drm/i915/intel_gvt.c
>> b/drivers/gpu/drm/i915/intel_gvt.c
>> index 2b6c016387c2..481c6de9f4d6 100644
>> --- a/drivers/gpu/drm/i915/intel_gvt.c
>> +++ b/drivers/gpu/drm/i915/intel_gvt.c
>> @@ -103,7 +103,7 @@ int intel_gvt_init(struct drm_i915_private *dev_priv)
>> return 0;
>> }
>> - if (USES_GUC_SUBMISSION(dev_priv)) {
>> + if (intel_uc_uses_guc_submission(&dev_priv->gt.uc)) {
>
> nit: that old macro was helpful exactly in cases where only dev_priv
> is known and component might have no idea where to find uc
>
> maybe we should have helper like:
>
> #define to_intel_uc(i915) (&(i915)->gt.uc)
>
> (but likely Jani will complain)
>
IMO the problem here is that we shouldn't really be going down to the uc
from the dev_priv level, as intel_uc is now a subfeature of the GT.
We've already removed a lot of the existing checks at the dev_priv level
and this series gets rid of a few more; I guess once they're reduced
enough in number we can consider replacing them with a check at the GT
level.
Daniele
>> DRM_ERROR("i915 GVT-g loading failed due to Graphics
>> virtualization is not yet supported with GuC submission\n");
>> return -EIO;
>> }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro
2020-01-16 20:42 ` Daniele Ceraolo Spurio
@ 2020-01-16 22:49 ` Michal Wajdeczko
2020-01-16 23:09 ` Daniele Ceraolo Spurio
0 siblings, 1 reply; 26+ messages in thread
From: Michal Wajdeczko @ 2020-01-16 22:49 UTC (permalink / raw)
To: intel-gfx, Daniele Ceraolo Spurio
>>> - if (USES_GUC_SUBMISSION(dev_priv)) {
>>> + if (intel_uc_uses_guc_submission(&dev_priv->gt.uc)) {
>> nit: that old macro was helpful exactly in cases where only dev_priv
>> is known and component might have no idea where to find uc
>> maybe we should have helper like:
>> #define to_intel_uc(i915) (&(i915)->gt.uc)
>> (but likely Jani will complain)
>>
>
> IMO the problem here is that we shouldn't really be going down to the uc
> from the dev_priv level, as intel_uc is now a subfeature of the GT.
> We've already removed a lot of the existing checks at the dev_priv level
> and this series gets rid of a few more; I guess once they're reduced
> enough in number we can consider replacing them with a check at the GT
> level.
so maybe we should introduce right now:
static inline bool intel_gt_uses_guc_submission(struct intel_gt *gt)
{
return intel_uc_uses_guc_submission(>->uc);
}
and use it where we operate at gt level
Michal
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro
2020-01-16 22:49 ` Michal Wajdeczko
@ 2020-01-16 23:09 ` Daniele Ceraolo Spurio
0 siblings, 0 replies; 26+ messages in thread
From: Daniele Ceraolo Spurio @ 2020-01-16 23:09 UTC (permalink / raw)
To: Michal Wajdeczko, intel-gfx
On 1/16/20 2:49 PM, Michal Wajdeczko wrote:
>>>> - if (USES_GUC_SUBMISSION(dev_priv)) {
>>>> + if (intel_uc_uses_guc_submission(&dev_priv->gt.uc)) {
>>> nit: that old macro was helpful exactly in cases where only dev_priv
>>> is known and component might have no idea where to find uc
>>> maybe we should have helper like:
>>> #define to_intel_uc(i915) (&(i915)->gt.uc)
>>> (but likely Jani will complain)
>>>
>>
>> IMO the problem here is that we shouldn't really be going down to the
>> uc from the dev_priv level, as intel_uc is now a subfeature of the GT.
>> We've already removed a lot of the existing checks at the dev_priv
>> level and this series gets rid of a few more; I guess once they're
>> reduced enough in number we can consider replacing them with a check
>> at the GT level.
>
> so maybe we should introduce right now:
>
> static inline bool intel_gt_uses_guc_submission(struct intel_gt *gt)
> {
> return intel_uc_uses_guc_submission(>->uc);
> }
>
> and use it where we operate at gt level
>
The problem is that with the gvt code is actually initialized before we
commit to using GuC submission and patch 3 changes the check from uses
to wants, so that's quite a specific case which I'm not sure is worth
the helper yet. That's why I wanted to wait until things settle down a
bit more to understand what was left before adding a high-level "wants"
helper, which IMO is not the best suited for a GT level check.
Daniele
> Michal
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Commit early to GuC
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
` (10 preceding siblings ...)
2020-01-15 8:40 ` [Intel-gfx] [PATCH 0/7] " Chris Wilson
@ 2020-01-17 8:38 ` Patchwork
11 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2020-01-17 8:38 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx
== Series Details ==
Series: Commit early to GuC
URL : https://patchwork.freedesktop.org/series/72031/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7746_full -> Patchwork_16103_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_16103_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries_display_on:
- shard-skl: [PASS][1] -> [DMESG-WARN][2] ([i915#109]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-skl2/igt@debugfs_test@read_all_entries_display_on.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-skl7/igt@debugfs_test@read_all_entries_display_on.html
* igt@gem_ctx_create@basic-files:
- shard-tglb: [PASS][3] -> [INCOMPLETE][4] ([fdo#111735])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb2/igt@gem_ctx_create@basic-files.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb3/igt@gem_ctx_create@basic-files.html
* igt@gem_ctx_persistence@processes:
- shard-iclb: [PASS][5] -> [FAIL][6] ([i915#570])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb8/igt@gem_ctx_persistence@processes.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb2/igt@gem_ctx_persistence@processes.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb8/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_ctx_persistence@vecs0-mixed-process:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#679])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-glk3/igt@gem_ctx_persistence@vecs0-mixed-process.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-glk5/igt@gem_ctx_persistence@vecs0-mixed-process.html
* igt@gem_eio@reset-stress:
- shard-tglb: [PASS][11] -> [INCOMPLETE][12] ([i915#470])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb6/igt@gem_eio@reset-stress.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb8/igt@gem_eio@reset-stress.html
* igt@gem_eio@unwedge-stress:
- shard-snb: [PASS][13] -> [FAIL][14] ([i915#232])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-snb5/igt@gem_eio@unwedge-stress.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-snb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][15] -> [SKIP][16] ([fdo#110854])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb4/igt@gem_exec_balancer@smoke.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb6/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@pi-common-bsd:
- shard-iclb: [PASS][17] -> [SKIP][18] ([i915#677]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb8/igt@gem_exec_schedule@pi-common-bsd.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb2/igt@gem_exec_schedule@pi-common-bsd.html
* igt@gem_exec_schedule@preempt-queue-contexts-bsd2:
- shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([fdo#111606] / [fdo#111677] / [i915#472])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb7/igt@gem_exec_schedule@preempt-queue-contexts-bsd2.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-bsd2.html
* igt@gem_exec_schedule@preempt-queue-vebox:
- shard-tglb: [PASS][21] -> [INCOMPLETE][22] ([fdo#111677] / [i915#472])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb3/igt@gem_exec_schedule@preempt-queue-vebox.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb3/igt@gem_exec_schedule@preempt-queue-vebox.html
* igt@gem_exec_schedule@smoketest-blt:
- shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([i915#470] / [i915#472])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb5/igt@gem_exec_schedule@smoketest-blt.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb3/igt@gem_exec_schedule@smoketest-blt.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#112146]) +5 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb8/igt@gem_exec_schedule@wide-bsd.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
- shard-kbl: [PASS][27] -> [TIMEOUT][28] ([fdo#112271] / [i915#530])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-kbl6/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-apl: [PASS][29] -> [TIMEOUT][30] ([fdo#112271] / [i915#530])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-apl1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-apl6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
- shard-hsw: [PASS][31] -> [TIMEOUT][32] ([fdo#112271] / [i915#530])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-tglb: [PASS][33] -> [FAIL][34] ([i915#520])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb6/igt@gem_persistent_relocs@forked-thrashing.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb8/igt@gem_persistent_relocs@forked-thrashing.html
- shard-kbl: [PASS][35] -> [INCOMPLETE][36] ([fdo#103665] / [i915#530])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-kbl1/igt@gem_persistent_relocs@forked-thrashing.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-kbl6/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_pipe_control_store_loop@reused-buffer:
- shard-tglb: [PASS][37] -> [INCOMPLETE][38] ([i915#707] / [i915#796])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb2/igt@gem_pipe_control_store_loop@reused-buffer.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb3/igt@gem_pipe_control_store_loop@reused-buffer.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [PASS][39] -> [DMESG-WARN][40] ([i915#180])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-apl1/igt@gem_softpin@noreloc-s3.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-apl1/igt@gem_softpin@noreloc-s3.html
* igt@gem_sync@basic-store-all:
- shard-tglb: [PASS][41] -> [INCOMPLETE][42] ([i915#472])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb7/igt@gem_sync@basic-store-all.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb6/igt@gem_sync@basic-store-all.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-tglb: [PASS][43] -> [FAIL][44] ([i915#49]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: [PASS][45] -> [DMESG-WARN][46] ([i915#180])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [PASS][47] -> [FAIL][48] ([fdo#108145]) +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][49] -> [SKIP][50] ([fdo#109642] / [fdo#111068])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb1/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][51] -> [SKIP][52] ([fdo#109441]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb1/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][53] -> [FAIL][54] ([i915#31])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-apl6/igt@kms_setmode@basic.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-apl7/igt@kms_setmode@basic.html
* igt@perf_pmu@init-busy-vcs1:
- shard-iclb: [PASS][55] -> [SKIP][56] ([fdo#112080]) +8 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb2/igt@perf_pmu@init-busy-vcs1.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb8/igt@perf_pmu@init-busy-vcs1.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [PASS][57] -> [SKIP][58] ([fdo#109276]) +16 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb4/igt@prime_busy@hang-bsd2.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb8/igt@prime_busy@hang-bsd2.html
#### Possible fixes ####
* igt@gem_busy@close-race:
- shard-hsw: [TIMEOUT][59] ([fdo#112271]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-hsw5/igt@gem_busy@close-race.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-hsw2/igt@gem_busy@close-race.html
* igt@gem_ctx_persistence@bcs0-mixed-process:
- shard-apl: [FAIL][61] ([i915#679]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-apl3/igt@gem_ctx_persistence@bcs0-mixed-process.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-apl2/igt@gem_ctx_persistence@bcs0-mixed-process.html
- shard-skl: [FAIL][63] ([i915#679]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-skl9/igt@gem_ctx_persistence@bcs0-mixed-process.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-skl2/igt@gem_ctx_persistence@bcs0-mixed-process.html
* igt@gem_ctx_persistence@vcs1-mixed-process:
- shard-iclb: [SKIP][65] ([fdo#109276] / [fdo#112080]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb8/igt@gem_ctx_persistence@vcs1-mixed-process.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb2/igt@gem_ctx_persistence@vcs1-mixed-process.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][67] ([fdo#110841]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_exec_nop@basic-sequential:
- shard-tglb: [INCOMPLETE][69] ([i915#472]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb6/igt@gem_exec_nop@basic-sequential.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb5/igt@gem_exec_nop@basic-sequential.html
* igt@gem_exec_parallel@contexts:
- shard-tglb: [INCOMPLETE][71] ([i915#470] / [i915#472]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb8/igt@gem_exec_parallel@contexts.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb4/igt@gem_exec_parallel@contexts.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [SKIP][73] ([fdo#112080]) -> [PASS][74] +9 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb8/igt@gem_exec_parallel@vcs1-fds.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb2/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [SKIP][75] ([i915#677]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb8/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][77] ([fdo#112146]) -> [PASS][78] +4 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_schedule@preempt-queue-chain-blt:
- shard-tglb: [INCOMPLETE][79] ([fdo#111606] / [fdo#111677] / [i915#472]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-blt.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb7/igt@gem_exec_schedule@preempt-queue-chain-blt.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [SKIP][81] ([fdo#109276]) -> [PASS][82] +23 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb6/igt@gem_exec_schedule@promotion-bsd1.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [DMESG-WARN][83] ([i915#180]) -> [PASS][84] +6 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-kbl6/igt@gem_exec_suspend@basic-s3.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-kbl2/igt@gem_exec_suspend@basic-s3.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing:
- shard-apl: [TIMEOUT][85] ([fdo#112271] / [i915#530]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-apl2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-apl7/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrashing.html
* igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
- shard-hsw: [TIMEOUT][87] ([fdo#112271] / [i915#530]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-hsw7/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-skl: [TIMEOUT][89] ([fdo#112271] / [i915#530]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-skl5/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-skl4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
- shard-tglb: [FAIL][91] ([i915#520]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb3/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [FAIL][93] ([i915#644]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-apl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-apl7/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_sync@basic-each:
- shard-tglb: [INCOMPLETE][95] ([i915#472] / [i915#707]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb7/igt@gem_sync@basic-each.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb1/igt@gem_sync@basic-each.html
* igt@i915_selftest@live_hangcheck:
- shard-tglb: [INCOMPLETE][97] -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb5/igt@i915_selftest@live_hangcheck.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb7/igt@i915_selftest@live_hangcheck.html
* igt@kms_color@pipe-b-ctm-0-75:
- shard-skl: [DMESG-WARN][99] ([i915#109]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-skl4/igt@kms_color@pipe-b-ctm-0-75.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-skl1/igt@kms_color@pipe-b-ctm-0-75.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [FAIL][101] ([i915#72]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][103] ([i915#79]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][105] ([i915#79]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-skl4/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-glk: [INCOMPLETE][107] ([i915#58] / [k.org#198133]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-glk8/igt@kms_flip@flip-vs-suspend-interruptible.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-glk7/igt@kms_flip@flip-vs-suspend-interruptible.html
- shard-apl: [DMESG-WARN][109] ([i915#180]) -> [PASS][110] +4 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt:
- shard-tglb: [FAIL][111] ([i915#49]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [FAIL][113] ([fdo#108145]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [SKIP][115] ([fdo#109441]) -> [PASS][116] +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb6/igt@kms_psr@psr2_cursor_plane_move.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv-switch:
- shard-iclb: [FAIL][117] ([IGT#28]) -> [SKIP][118] ([fdo#109276] / [fdo#112080])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [DMESG-WARN][119] ([fdo#107724]) -> [SKIP][120] ([fdo#109349])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-iclb1/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_vblank@pipe-c-ts-continuation-suspend:
- shard-kbl: [DMESG-WARN][121] ([i915#180]) -> [INCOMPLETE][122] ([fdo#103665])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7746/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/shard-kbl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
[fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520
[i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
[i915#570]: https://gitlab.freedesktop.org/drm/intel/issues/570
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679
[i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#796]: https://gitlab.freedesktop.org/drm/intel/issues/796
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7746 -> Patchwork_16103
CI-20190529: 20190529
CI_DRM_7746: 84d16aa256204bccaaf382504a69fe0822e67ba0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5365: e9ec0ed63b25c86861ffac3c8601cc4d1b910b65 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16103: 522c1abc9b0b19d9d332e20848cdde8f4a27839d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16103/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro
2020-01-15 1:31 ` [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro Daniele Ceraolo Spurio
@ 2020-01-27 3:00 ` kbuild test robot
2020-01-27 3:00 ` kbuild test robot
1 sibling, 0 replies; 26+ messages in thread
From: kbuild test robot @ 2020-01-27 3:00 UTC (permalink / raw)
To: Daniele Ceraolo Spurio; +Cc: intel-gfx, kbuild-all
Hi Daniele,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.5-rc7 next-20200124]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Daniele-Ceraolo-Spurio/Commit-early-to-GuC/20200116-112105
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-153-g47b6dfef-dirty
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/gem/i915_gem_context.c:1457:51: sparse: sparse: dereference of noderef expression
vim +1457 drivers/gpu/drm/i915/gem/i915_gem_context.c
1440
1441 static int
1442 set_engines__load_balance(struct i915_user_extension __user *base, void *data)
1443 {
1444 struct i915_context_engines_load_balance __user *ext =
1445 container_of_user(base, typeof(*ext), base);
1446 const struct set_engines *set = data;
1447 struct intel_engine_cs *stack[16];
1448 struct intel_engine_cs **siblings;
1449 struct intel_context *ce;
1450 u16 num_siblings, idx;
1451 unsigned int n;
1452 int err;
1453
1454 if (!HAS_EXECLISTS(set->ctx->i915))
1455 return -ENODEV;
1456
> 1457 if (intel_uc_uses_guc_submission(&set->ctx->vm->gt->uc))
1458 return -ENODEV; /* not implement yet */
1459
1460 if (get_user(idx, &ext->engine_index))
1461 return -EFAULT;
1462
1463 if (idx >= set->engines->num_engines) {
1464 DRM_DEBUG("Invalid placement value, %d >= %d\n",
1465 idx, set->engines->num_engines);
1466 return -EINVAL;
1467 }
1468
1469 idx = array_index_nospec(idx, set->engines->num_engines);
1470 if (set->engines->engines[idx]) {
1471 DRM_DEBUG("Invalid placement[%d], already occupied\n", idx);
1472 return -EEXIST;
1473 }
1474
1475 if (get_user(num_siblings, &ext->num_siblings))
1476 return -EFAULT;
1477
1478 err = check_user_mbz(&ext->flags);
1479 if (err)
1480 return err;
1481
1482 err = check_user_mbz(&ext->mbz64);
1483 if (err)
1484 return err;
1485
1486 siblings = stack;
1487 if (num_siblings > ARRAY_SIZE(stack)) {
1488 siblings = kmalloc_array(num_siblings,
1489 sizeof(*siblings),
1490 GFP_KERNEL);
1491 if (!siblings)
1492 return -ENOMEM;
1493 }
1494
1495 for (n = 0; n < num_siblings; n++) {
1496 struct i915_engine_class_instance ci;
1497
1498 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
1499 err = -EFAULT;
1500 goto out_siblings;
1501 }
1502
1503 siblings[n] = intel_engine_lookup_user(set->ctx->i915,
1504 ci.engine_class,
1505 ci.engine_instance);
1506 if (!siblings[n]) {
1507 DRM_DEBUG("Invalid sibling[%d]: { class:%d, inst:%d }\n",
1508 n, ci.engine_class, ci.engine_instance);
1509 err = -EINVAL;
1510 goto out_siblings;
1511 }
1512 }
1513
1514 ce = intel_execlists_create_virtual(siblings, n);
1515 if (IS_ERR(ce)) {
1516 err = PTR_ERR(ce);
1517 goto out_siblings;
1518 }
1519
1520 intel_context_set_gem(ce, set->ctx);
1521
1522 if (cmpxchg(&set->engines->engines[idx], NULL, ce)) {
1523 intel_context_put(ce);
1524 err = -EEXIST;
1525 goto out_siblings;
1526 }
1527
1528 out_siblings:
1529 if (siblings != stack)
1530 kfree(siblings);
1531
1532 return err;
1533 }
1534
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro
@ 2020-01-27 3:00 ` kbuild test robot
0 siblings, 0 replies; 26+ messages in thread
From: kbuild test robot @ 2020-01-27 3:00 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 4185 bytes --]
Hi Daniele,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[cannot apply to drm-tip/drm-tip v5.5-rc7 next-20200124]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Daniele-Ceraolo-Spurio/Commit-early-to-GuC/20200116-112105
base: git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-153-g47b6dfef-dirty
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/i915/gem/i915_gem_context.c:1457:51: sparse: sparse: dereference of noderef expression
vim +1457 drivers/gpu/drm/i915/gem/i915_gem_context.c
1440
1441 static int
1442 set_engines__load_balance(struct i915_user_extension __user *base, void *data)
1443 {
1444 struct i915_context_engines_load_balance __user *ext =
1445 container_of_user(base, typeof(*ext), base);
1446 const struct set_engines *set = data;
1447 struct intel_engine_cs *stack[16];
1448 struct intel_engine_cs **siblings;
1449 struct intel_context *ce;
1450 u16 num_siblings, idx;
1451 unsigned int n;
1452 int err;
1453
1454 if (!HAS_EXECLISTS(set->ctx->i915))
1455 return -ENODEV;
1456
> 1457 if (intel_uc_uses_guc_submission(&set->ctx->vm->gt->uc))
1458 return -ENODEV; /* not implement yet */
1459
1460 if (get_user(idx, &ext->engine_index))
1461 return -EFAULT;
1462
1463 if (idx >= set->engines->num_engines) {
1464 DRM_DEBUG("Invalid placement value, %d >= %d\n",
1465 idx, set->engines->num_engines);
1466 return -EINVAL;
1467 }
1468
1469 idx = array_index_nospec(idx, set->engines->num_engines);
1470 if (set->engines->engines[idx]) {
1471 DRM_DEBUG("Invalid placement[%d], already occupied\n", idx);
1472 return -EEXIST;
1473 }
1474
1475 if (get_user(num_siblings, &ext->num_siblings))
1476 return -EFAULT;
1477
1478 err = check_user_mbz(&ext->flags);
1479 if (err)
1480 return err;
1481
1482 err = check_user_mbz(&ext->mbz64);
1483 if (err)
1484 return err;
1485
1486 siblings = stack;
1487 if (num_siblings > ARRAY_SIZE(stack)) {
1488 siblings = kmalloc_array(num_siblings,
1489 sizeof(*siblings),
1490 GFP_KERNEL);
1491 if (!siblings)
1492 return -ENOMEM;
1493 }
1494
1495 for (n = 0; n < num_siblings; n++) {
1496 struct i915_engine_class_instance ci;
1497
1498 if (copy_from_user(&ci, &ext->engines[n], sizeof(ci))) {
1499 err = -EFAULT;
1500 goto out_siblings;
1501 }
1502
1503 siblings[n] = intel_engine_lookup_user(set->ctx->i915,
1504 ci.engine_class,
1505 ci.engine_instance);
1506 if (!siblings[n]) {
1507 DRM_DEBUG("Invalid sibling[%d]: { class:%d, inst:%d }\n",
1508 n, ci.engine_class, ci.engine_instance);
1509 err = -EINVAL;
1510 goto out_siblings;
1511 }
1512 }
1513
1514 ce = intel_execlists_create_virtual(siblings, n);
1515 if (IS_ERR(ce)) {
1516 err = PTR_ERR(ce);
1517 goto out_siblings;
1518 }
1519
1520 intel_context_set_gem(ce, set->ctx);
1521
1522 if (cmpxchg(&set->engines->engines[idx], NULL, ce)) {
1523 intel_context_put(ce);
1524 err = -EEXIST;
1525 goto out_siblings;
1526 }
1527
1528 out_siblings:
1529 if (siblings != stack)
1530 kfree(siblings);
1531
1532 return err;
1533 }
1534
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org Intel Corporation
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 3/7] drm/i915/uc: Improve tracking of uC init status
2020-01-15 1:31 ` [Intel-gfx] [PATCH 3/7] drm/i915/uc: Improve tracking of uC init status Daniele Ceraolo Spurio
@ 2020-01-27 23:57 ` Fernando Pacheco
0 siblings, 0 replies; 26+ messages in thread
From: Fernando Pacheco @ 2020-01-27 23:57 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
On 1/14/20 5:31 PM, Daniele Ceraolo Spurio wrote:
> To be able to setup GuC submission functions during engine init we need
> to commit to using GuC as soon as possible.
> Currently, the only thing that can stop us from using the
> microcontrollers once we've fetched the blobs is a fundamental
> error (e.g. OOM); given that if we hit such an error we can't really
> fall-back to anything, we can "officialize" the FW fetching completion
> as the moment at which we're committing to using GuC.
>
> To better differentiate this case, the uses_guc check, which indicates
> that GuC is supported and was selected in modparam, is renamed to
> wants_guc and a new uses_guc is introduced to represent the case were
> we're committed to using the GuC. Note that uses_guc does still not imply
> that the blob is actually loaded on the HW (is_running is the check for
> that). Also, since we need to have attempted the fetch for the result
> of uses_guc to be meaningful, we need to make sure we've moved away
> from INTEL_UC_FIRMWARE_SELECTED.
>
> All the GuC changes have been mirrored on the HuC for coherency.
Reviewed-by: Fernando Pacheco <fernando.pacheco@intel.com>
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 8 +++-
> drivers/gpu/drm/i915/gt/uc/intel_huc.h | 8 +++-
> drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 23 +++++-----
> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 52 +++++++++++++++--------
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
> 6 files changed, 64 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 910d49590068..f9e0be843992 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -143,11 +143,17 @@ static inline bool intel_guc_is_supported(struct intel_guc *guc)
> return intel_uc_fw_is_supported(&guc->fw);
> }
>
> -static inline bool intel_guc_is_enabled(struct intel_guc *guc)
> +static inline bool intel_guc_is_wanted(struct intel_guc *guc)
> {
> return intel_uc_fw_is_enabled(&guc->fw);
> }
>
> +static inline bool intel_guc_is_used(struct intel_guc *guc)
> +{
> + GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) == INTEL_UC_FIRMWARE_SELECTED);
> + return intel_uc_fw_is_available(&guc->fw);
> +}
> +
> static inline bool intel_guc_is_running(struct intel_guc *guc)
> {
> return intel_uc_fw_is_running(&guc->fw);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> index 644c059fe01d..a40b9cfc6c22 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> @@ -41,11 +41,17 @@ static inline bool intel_huc_is_supported(struct intel_huc *huc)
> return intel_uc_fw_is_supported(&huc->fw);
> }
>
> -static inline bool intel_huc_is_enabled(struct intel_huc *huc)
> +static inline bool intel_huc_is_wanted(struct intel_huc *huc)
> {
> return intel_uc_fw_is_enabled(&huc->fw);
> }
>
> +static inline bool intel_huc_is_used(struct intel_huc *huc)
> +{
> + GEM_BUG_ON(__intel_uc_fw_status(&huc->fw) == INTEL_UC_FIRMWARE_SELECTED);
> + return intel_uc_fw_is_available(&huc->fw);
> +}
> +
> static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
> {
> return intel_uc_fw_is_running(&huc->fw);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> index eee193bf2cc4..fd7d04690ded 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> @@ -20,7 +20,7 @@ void intel_huc_fw_init_early(struct intel_huc *huc)
> struct drm_i915_private *i915 = gt->i915;
>
> intel_uc_fw_init_early(&huc->fw, INTEL_UC_FW_TYPE_HUC,
> - intel_uc_uses_guc(uc),
> + intel_uc_supports_guc(uc),
> INTEL_INFO(i915)->platform, INTEL_REVID(i915));
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 64934a876a50..8843d4f16a7f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -48,17 +48,17 @@ static void __confirm_options(struct intel_uc *uc)
> DRM_DEV_DEBUG_DRIVER(i915->drm.dev,
> "enable_guc=%d (guc:%s submission:%s huc:%s)\n",
> i915_modparams.enable_guc,
> - yesno(intel_uc_uses_guc(uc)),
> + yesno(intel_uc_wants_guc(uc)),
> yesno(intel_uc_uses_guc_submission(uc)),
> - yesno(intel_uc_uses_huc(uc)));
> + yesno(intel_uc_wants_huc(uc)));
>
> if (i915_modparams.enable_guc == -1)
> return;
>
> if (i915_modparams.enable_guc == 0) {
> - GEM_BUG_ON(intel_uc_uses_guc(uc));
> + GEM_BUG_ON(intel_uc_wants_guc(uc));
> GEM_BUG_ON(intel_uc_uses_guc_submission(uc));
> - GEM_BUG_ON(intel_uc_uses_huc(uc));
> + GEM_BUG_ON(intel_uc_wants_huc(uc));
> return;
> }
>
> @@ -93,7 +93,7 @@ void intel_uc_init_early(struct intel_uc *uc)
>
> __confirm_options(uc);
>
> - if (intel_uc_uses_guc(uc))
> + if (intel_uc_wants_guc(uc))
> uc->ops = &uc_ops_on;
> else
> uc->ops = &uc_ops_off;
> @@ -257,13 +257,13 @@ static void __uc_fetch_firmwares(struct intel_uc *uc)
> {
> int err;
>
> - GEM_BUG_ON(!intel_uc_uses_guc(uc));
> + GEM_BUG_ON(!intel_uc_wants_guc(uc));
>
> err = intel_uc_fw_fetch(&uc->guc.fw);
> if (err)
> return;
>
> - if (intel_uc_uses_huc(uc))
> + if (intel_uc_wants_huc(uc))
> intel_uc_fw_fetch(&uc->huc.fw);
> }
>
> @@ -279,7 +279,10 @@ static void __uc_init(struct intel_uc *uc)
> struct intel_huc *huc = &uc->huc;
> int ret;
>
> - GEM_BUG_ON(!intel_uc_uses_guc(uc));
> + GEM_BUG_ON(!intel_uc_wants_guc(uc));
> +
> + if (!intel_uc_uses_guc(uc))
> + return;
>
> /* XXX: GuC submission is unavailable for now */
> GEM_BUG_ON(intel_uc_supports_guc_submission(uc));
> @@ -322,7 +325,7 @@ static int uc_init_wopcm(struct intel_uc *uc)
> struct intel_uncore *uncore = gt->uncore;
> u32 base = intel_wopcm_guc_base(>->i915->wopcm);
> u32 size = intel_wopcm_guc_size(>->i915->wopcm);
> - u32 huc_agent = intel_uc_uses_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
> + u32 huc_agent = intel_uc_wants_huc(uc) ? HUC_LOADING_AGENT_GUC : 0;
> u32 mask;
> int err;
>
> @@ -402,7 +405,7 @@ static int __uc_init_hw(struct intel_uc *uc)
> int ret, attempts;
>
> GEM_BUG_ON(!intel_uc_supports_guc(uc));
> - GEM_BUG_ON(!intel_uc_uses_guc(uc));
> + GEM_BUG_ON(!intel_uc_wants_guc(uc));
>
> if (!intel_uc_fw_is_available(&guc->fw)) {
> ret = __uc_check_hw(uc) ||
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> index 49c913524686..f2f7351ff22a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> @@ -40,16 +40,44 @@ void intel_uc_runtime_suspend(struct intel_uc *uc);
> int intel_uc_resume(struct intel_uc *uc);
> int intel_uc_runtime_resume(struct intel_uc *uc);
>
> -static inline bool intel_uc_supports_guc(struct intel_uc *uc)
> -{
> - return intel_guc_is_supported(&uc->guc);
> -}
> +/*
> + * We need to know as early as possible if we're going to use GuC or not to
> + * take the correct setup paths. Additionally, once we've started loading the
> + * GuC, it is unsafe to keep executing without it because some parts of the HW,
> + * a subset of which is not cleaned on GT reset, will start expecting the GuC FW
> + * to be running.
> + * To solve both these requirements, we commit to using the microcontrollers if
> + * the relevant modparam is set and the blobs are found on the system. At this
> + * stage, the only thing that can stop us from attempting to load the blobs on
> + * the HW and use them is a fundamental issue (e.g. no memory for our
> + * structures); if we hit such a problem during driver load we're broken even
> + * without GuC, so there is no point in trying to fall back.
> + *
> + * Given the above, we can be in one of 4 states, with the last one implying
> + * we're committed to using the microcontroller:
> + * - Not supported: not available in HW and/or firmware not defined.
> + * - Supported: available in HW and firmware defined.
> + * - Wanted: supported and enabled in modparam.
> + * - In use: wanted and firmware found on the system.
> + */
>
> -static inline bool intel_uc_uses_guc(struct intel_uc *uc)
> -{
> - return intel_guc_is_enabled(&uc->guc);
> +#define __uc_state_checker(x, state, required) \
> +static inline bool intel_uc_##state##_##x(struct intel_uc *uc) \
> +{ \
> + return intel_##x##_is_##required(&uc->x); \
> }
>
> +#define uc_state_checkers(x) \
> +__uc_state_checker(x, supports, supported) \
> +__uc_state_checker(x, wants, wanted) \
> +__uc_state_checker(x, uses, used)
> +
> +uc_state_checkers(guc);
> +uc_state_checkers(huc);
> +
> +#undef uc_state_checkers
> +#undef __uc_state_checker
> +
> static inline bool intel_uc_supports_guc_submission(struct intel_uc *uc)
> {
> return intel_guc_is_submission_supported(&uc->guc);
> @@ -60,16 +88,6 @@ static inline bool intel_uc_uses_guc_submission(struct intel_uc *uc)
> return intel_guc_is_submission_supported(&uc->guc);
> }
>
> -static inline bool intel_uc_supports_huc(struct intel_uc *uc)
> -{
> - return intel_uc_supports_guc(uc);
> -}
> -
> -static inline bool intel_uc_uses_huc(struct intel_uc *uc)
> -{
> - return intel_huc_is_enabled(&uc->huc);
> -}
> -
> #define intel_uc_ops_function(_NAME, _OPS, _TYPE, _RET) \
> static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \
> { \
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index 8ee0a0c7f447..c9c094a73399 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -279,7 +279,7 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
>
> err = i915_inject_probe_error(i915, -ENXIO);
> if (err)
> - return err;
> + goto fail;
>
> __force_fw_fetch_failures(uc_fw, -EINVAL);
> __force_fw_fetch_failures(uc_fw, -ESTALE);
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH 4/7] drm/i915/uc: Abort early on uc_init failure
2020-01-15 1:31 ` [Intel-gfx] [PATCH 4/7] drm/i915/uc: Abort early on uc_init failure Daniele Ceraolo Spurio
@ 2020-01-27 23:57 ` Fernando Pacheco
0 siblings, 0 replies; 26+ messages in thread
From: Fernando Pacheco @ 2020-01-27 23:57 UTC (permalink / raw)
To: Daniele Ceraolo Spurio, intel-gfx
On 1/14/20 5:31 PM, Daniele Ceraolo Spurio wrote:
> Now that we can differentiate wants vs uses GuC/HuC, intel_uc_init is
> restricted to running only if we have successfully fetched the required
> blob(s) and are committed to using the microcontroller(s).
> The only remaining thing that can go wrong in uc_init is the allocation
> of GuC/HuC related objects; if we get such a failure better to bail out
> immediately instead of wedging later, like we do for e.g.
> intel_engines_init, since without objects we can't use the HW, including
> not being able to attempt the firmware load.
>
> While at it, remove the unneeded fw_cleanup call (this is handled
> outside of gt_init) and add a probe failure injection point for testing.
> Also, update the logs for <g/h>uc_init failures to probe_failure() since
> they will cause the driver load to fail.
Reviewed-by: Fernando Pacheco <fernando.pacheco@intel.com>
>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> Cc: John Harrison <John.C.Harrison@Intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++-
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_huc.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 24 +++++++++++++++++-------
> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 4 ++--
> 5 files changed, 24 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index da2b6e2ae692..85f21f18c785 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -584,7 +584,9 @@ int intel_gt_init(struct intel_gt *gt)
> if (err)
> goto err_engines;
>
> - intel_uc_init(>->uc);
> + err = intel_uc_init(>->uc);
> + if (err)
> + goto err_engines;
>
> err = intel_gt_resume(gt);
> if (err)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 5d00a3b2d914..c46f5ae77348 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -376,7 +376,7 @@ int intel_guc_init(struct intel_guc *guc)
> intel_uc_fw_fini(&guc->fw);
> err_fetch:
> intel_uc_fw_cleanup_fetch(&guc->fw);
> - DRM_DEV_DEBUG_DRIVER(gt->i915->drm.dev, "failed with %d\n", ret);
> + i915_probe_error(gt->i915, "failed with %d\n", ret);
> return ret;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index 32a069841c14..5f448d0e360b 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -127,7 +127,7 @@ int intel_huc_init(struct intel_huc *huc)
> intel_uc_fw_fini(&huc->fw);
> out:
> intel_uc_fw_cleanup_fetch(&huc->fw);
> - DRM_DEV_DEBUG_DRIVER(i915->drm.dev, "failed with %d\n", err);
> + i915_probe_error(i915, "failed with %d\n", err);
> return err;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 8843d4f16a7f..d57b731952ef 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -273,7 +273,7 @@ static void __uc_cleanup_firmwares(struct intel_uc *uc)
> intel_uc_fw_cleanup_fetch(&uc->guc.fw);
> }
>
> -static void __uc_init(struct intel_uc *uc)
> +static int __uc_init(struct intel_uc *uc)
> {
> struct intel_guc *guc = &uc->guc;
> struct intel_huc *huc = &uc->huc;
> @@ -282,19 +282,29 @@ static void __uc_init(struct intel_uc *uc)
> GEM_BUG_ON(!intel_uc_wants_guc(uc));
>
> if (!intel_uc_uses_guc(uc))
> - return;
> + return 0;
> +
> + if (i915_inject_probe_failure(uc_to_gt(uc)->i915))
> + return -ENOMEM;
>
> /* XXX: GuC submission is unavailable for now */
> GEM_BUG_ON(intel_uc_supports_guc_submission(uc));
>
> ret = intel_guc_init(guc);
> - if (ret) {
> - intel_uc_fw_cleanup_fetch(&huc->fw);
> - return;
> + if (ret)
> + return ret;
> +
> + if (intel_uc_uses_huc(uc)) {
> + ret = intel_huc_init(huc);
> + if (ret)
> + goto out_guc;
> }
>
> - if (intel_uc_uses_huc(uc))
> - intel_huc_init(huc);
> + return 0;
> +
> +out_guc:
> + intel_guc_fini(guc);
> + return ret;
> }
>
> static void __uc_fini(struct intel_uc *uc)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> index f2f7351ff22a..2d9f17196761 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> @@ -16,7 +16,7 @@ struct intel_uc_ops {
> int (*sanitize)(struct intel_uc *uc);
> void (*init_fw)(struct intel_uc *uc);
> void (*fini_fw)(struct intel_uc *uc);
> - void (*init)(struct intel_uc *uc);
> + int (*init)(struct intel_uc *uc);
> void (*fini)(struct intel_uc *uc);
> int (*init_hw)(struct intel_uc *uc);
> void (*fini_hw)(struct intel_uc *uc);
> @@ -98,7 +98,7 @@ static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \
> intel_uc_ops_function(sanitize, sanitize, int, 0);
> intel_uc_ops_function(fetch_firmwares, init_fw, void, );
> intel_uc_ops_function(cleanup_firmwares, fini_fw, void, );
> -intel_uc_ops_function(init, init, void, );
> +intel_uc_ops_function(init, init, int, 0);
> intel_uc_ops_function(fini, fini, void, );
> intel_uc_ops_function(init_hw, init_hw, int, 0);
> intel_uc_ops_function(fini_hw, fini_hw, void, );
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2020-01-27 23:57 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-15 1:31 [Intel-gfx] [PATCH 0/7] Commit early to GuC Daniele Ceraolo Spurio
2020-01-15 1:31 ` [Intel-gfx] [PATCH 1/7] drm/i915/guc: Kill USES_GUC macro Daniele Ceraolo Spurio
2020-01-16 19:42 ` Michal Wajdeczko
2020-01-16 20:24 ` Daniele Ceraolo Spurio
2020-01-15 1:31 ` [Intel-gfx] [PATCH 2/7] drm/i915/guc: Kill USES_GUC_SUBMISSION macro Daniele Ceraolo Spurio
2020-01-16 19:49 ` Michal Wajdeczko
2020-01-16 20:42 ` Daniele Ceraolo Spurio
2020-01-16 22:49 ` Michal Wajdeczko
2020-01-16 23:09 ` Daniele Ceraolo Spurio
2020-01-27 3:00 ` kbuild test robot
2020-01-27 3:00 ` kbuild test robot
2020-01-15 1:31 ` [Intel-gfx] [PATCH 3/7] drm/i915/uc: Improve tracking of uC init status Daniele Ceraolo Spurio
2020-01-27 23:57 ` Fernando Pacheco
2020-01-15 1:31 ` [Intel-gfx] [PATCH 4/7] drm/i915/uc: Abort early on uc_init failure Daniele Ceraolo Spurio
2020-01-27 23:57 ` Fernando Pacheco
2020-01-15 1:31 ` [Intel-gfx] [PATCH 5/7] drm/i915/guc: Apply new uC status tracking to GuC submission as well Daniele Ceraolo Spurio
2020-01-15 1:31 ` [Intel-gfx] [PATCH 6/7] drm/i915/guc: Start considering GuC submission a proper back-end Daniele Ceraolo Spurio
2020-01-15 1:31 ` [Intel-gfx] [PATCH 7/7] HAX: force enable_guc=2 Daniele Ceraolo Spurio
2020-01-15 2:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Commit early to GuC Patchwork
2020-01-15 2:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-15 2:29 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
2020-01-15 8:40 ` [Intel-gfx] [PATCH 0/7] " Chris Wilson
2020-01-15 15:57 ` Daniele Ceraolo Spurio
2020-01-15 16:18 ` Chris Wilson
2020-01-15 20:46 ` Daniele Ceraolo Spurio
2020-01-17 8:38 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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