* [Qemu-devel] scsi patch
@ 2007-03-10 14:03 王成業
2007-03-11 4:27 ` 王成業
2007-03-14 15:15 ` 王成業
0 siblings, 2 replies; 7+ messages in thread
From: 王成業 @ 2007-03-10 14:03 UTC (permalink / raw)
To: qemu-devel
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--- ../../tmp/qemu-0.9.0/hw/lsi53c895a.c 2007-02-06 07:01:
54.000000000 +0800
+++ lsi53c895a.c 2007-03-08 20:50:03.094098835 +0800
@@ -251,7 +251,7 @@
uint32_t ia;
uint32_t sbc;
uint32_t csbc;
- uint32_t scratch[13]; /* SCRATCHA-SCRATCHR */
+ uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
/* Script ram is stored as 32-bit words in host byteorder. */
uint32_t script_ram[2048];
@@ -1038,7 +1038,7 @@
op0 |= op1;
break;
case 3: /* XOR */
- op0 |= op1;
+ op0 ^= op1;
break;
case 4: /* AND */
op0 &= op1;
@@ -1765,7 +1765,7 @@
lsi_reg_writeb(s, addr, val & 0xff);
lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
- lsi_reg_writeb(s, addr + 2, (val >> 24) & 0xff);
+ lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
}
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] scsi patch
2007-03-10 14:03 [Qemu-devel] scsi patch 王成業
@ 2007-03-11 4:27 ` 王成業
2007-03-14 15:15 ` 王成業
1 sibling, 0 replies; 7+ messages in thread
From: 王成業 @ 2007-03-11 4:27 UTC (permalink / raw)
To: qemu-devel
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--- ../../tmp/qemu-0.9.0/hw/lsi53c895a.c 2007-02-06 07:01:
54.000000000 +0800
+++ lsi53c895a.c 2007-03-08 20:50:03.094098835 +0800
@@ -251,7 +251,7 @@
uint32_t ia;
uint32_t sbc;
uint32_t csbc;
- uint32_t scratch[13]; /* SCRATCHA-SCRATCHR */
+ uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
/* Script ram is stored as 32-bit words in host byteorder. */
uint32_t script_ram[2048];
@@ -1038,7 +1038,7 @@
op0 |= op1;
break;
case 3: /* XOR */
- op0 |= op1;
+ op0 ^= op1;
break;
case 4: /* AND */
op0 &= op1;
@@ -1765,7 +1765,7 @@
lsi_reg_writeb(s, addr, val & 0xff);
lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
- lsi_reg_writeb(s, addr + 2, (val >> 24) & 0xff);
+ lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
}
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] scsi patch
2007-03-10 14:03 [Qemu-devel] scsi patch 王成業
2007-03-11 4:27 ` 王成業
@ 2007-03-14 15:15 ` 王成業
2007-03-19 12:42 ` Thiemo Seufer
1 sibling, 1 reply; 7+ messages in thread
From: 王成業 @ 2007-03-14 15:15 UTC (permalink / raw)
To: qemu-devel
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--- ../../tmp/qemu-0.9.0/hw/lsi53c895a.c 2007-02-06 07:01:
54.000000000 +0800
+++ lsi53c895a.c 2007-03-08 20:50:03.094098835 +0800
@@ -251,7 +251,7 @@
uint32_t ia;
uint32_t sbc;
uint32_t csbc;
- uint32_t scratch[13]; /* SCRATCHA-SCRATCHR */
+ uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
/* Script ram is stored as 32-bit words in host byteorder. */
uint32_t script_ram[2048];
@@ -1038,7 +1038,7 @@
op0 |= op1;
break;
case 3: /* XOR */
- op0 |= op1;
+ op0 ^= op1;
break;
case 4: /* AND */
op0 &= op1;
@@ -1765,7 +1765,7 @@
lsi_reg_writeb(s, addr, val & 0xff);
lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
- lsi_reg_writeb(s, addr + 2, (val >> 24) & 0xff);
+ lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
}
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] scsi patch
2007-03-14 15:15 ` 王成業
@ 2007-03-19 12:42 ` Thiemo Seufer
2007-03-19 14:37 ` Wang Cheng Yeh
0 siblings, 1 reply; 7+ messages in thread
From: Thiemo Seufer @ 2007-03-19 12:42 UTC (permalink / raw)
To: ?????????; +Cc: qemu-devel
????????? wrote:
> --- ../../tmp/qemu-0.9.0/hw/lsi53c895a.c 2007-02-06 07:01:
> 54.000000000 +0800
> +++ lsi53c895a.c 2007-03-08 20:50:03.094098835 +0800
> @@ -251,7 +251,7 @@
> uint32_t ia;
> uint32_t sbc;
> uint32_t csbc;
> - uint32_t scratch[13]; /* SCRATCHA-SCRATCHR */
> + uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
This still looks inconsistent. SCRATCHR suggests 18 available
registers, but the code below handles only 17 scratch registers.
Could you check what's the right thing there?
Otherwise the patch looks good.
Thiemo
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] scsi patch
2007-03-19 12:42 ` Thiemo Seufer
@ 2007-03-19 14:37 ` Wang Cheng Yeh
0 siblings, 0 replies; 7+ messages in thread
From: Wang Cheng Yeh @ 2007-03-19 14:37 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: qemu-devel
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because
(1) address of SCRATCHA is 0x34
(2) address from SCRATCHB to SCRATCHR are 0x5c ~ 0x9f
you just see the code about part (2).
I think the access code is right.
2007/3/19, Thiemo Seufer <ths@networkno.de>:
>
> ????????? wrote:
> > --- ../../tmp/qemu-0.9.0/hw/lsi53c895a.c 2007-02-06 07:01:
> > 54.000000000 +0800
> > +++ lsi53c895a.c 2007-03-08 20:50:03.094098835 +0800
> > @@ -251,7 +251,7 @@
> > uint32_t ia;
> > uint32_t sbc;
> > uint32_t csbc;
> > - uint32_t scratch[13]; /* SCRATCHA-SCRATCHR */
> > + uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
>
> This still looks inconsistent. SCRATCHR suggests 18 available
> registers, but the code below handles only 17 scratch registers.
>
> Could you check what's the right thing there?
> Otherwise the patch looks good.
>
>
> Thiemo
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] scsi patch
2007-04-25 5:48 Wang Cheng Yeh
@ 2007-04-26 19:26 ` Blue Swirl
0 siblings, 0 replies; 7+ messages in thread
From: Blue Swirl @ 2007-04-26 19:26 UTC (permalink / raw)
To: qemu-devel
On 4/25/07, Wang Cheng Yeh <cywang.eda@gmail.com> wrote:
> scsi.tex patch reduces unnecessary mismatch.
>
> lsi.txt corrects mismatch condition.
> When the mismatch happens, register ia saves the instruction address.
> However, QEMU call lsi_bad_phase first, update new dsp and
> then save it into register ia.
> The patch correct this problem.
> Another fix is in the table indirect addressing.
> s->rbc is the same as s->dbc in direct, indirect, and table indirect mode.
>
> I test 25 times debian installation automatically and there is no problem in
> scsi.
>
> The steps follow
> http://www.aurel32.net/info/debian_arm_qemu.php
> will work well !!!
I tested the scsi-disk part on Sparc, seems to be fine.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] scsi patch
@ 2007-04-25 5:48 Wang Cheng Yeh
2007-04-26 19:26 ` Blue Swirl
0 siblings, 1 reply; 7+ messages in thread
From: Wang Cheng Yeh @ 2007-04-25 5:48 UTC (permalink / raw)
To: qemu-devel
[-- Attachment #1.1: Type: text/plain, Size: 568 bytes --]
scsi.tex patch reduces unnecessary mismatch.
lsi.txt corrects mismatch condition.
When the mismatch happens, register ia saves the instruction address.
However, QEMU call lsi_bad_phase first, update new dsp and
then save it into register ia.
The patch correct this problem.
Another fix is in the table indirect addressing.
s->rbc is the same as s->dbc in direct, indirect, and table indirect mode.
I test 25 times debian installation automatically and there is no problem in
scsi.
The steps follow http://www.aurel32.net/info/debian_arm_qemu.php
will work well !!!
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[-- Attachment #2: scsi.txt --]
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Index: hw/scsi-disk.c
===================================================================
RCS file: /sources/qemu/qemu/hw/scsi-disk.c,v
retrieving revision 1.13
diff -u -p -r1.13 scsi-disk.c
--- hw/scsi-disk.c 29 Aug 2006 04:52:16 -0000 1.13
+++ hw/scsi-disk.c 25 Apr 2007 04:55:11 -0000
@@ -345,7 +345,7 @@ int32_t scsi_send_command(SCSIDevice *s,
DPRINTF("Request Sense (len %d)\n", len);
if (len < 4)
goto fail;
- memset(buf, 0, 4);
+ memset(outbuf, 0, 4);
outbuf[0] = 0xf0;
outbuf[1] = 0;
outbuf[2] = s->sense;
@@ -371,7 +371,7 @@ int32_t scsi_send_command(SCSIDevice *s,
Some later commands are also implemented. */
outbuf[2] = 3;
outbuf[3] = 2; /* Format 2 */
- outbuf[4] = 32;
+ outbuf[4] = 31;
/* Sync data transfer and TCQ. */
outbuf[7] = 0x10 | (s->tcq ? 0x02 : 0);
r->buf_len = 36;
@@ -404,10 +404,11 @@ int32_t scsi_send_command(SCSIDevice *s,
p += 4;
if ((page == 8 || page == 0x3f)) {
/* Caching page. */
+ memset(p,0,20);
p[0] = 8;
p[1] = 0x12;
p[2] = 4; /* WCE */
- p += 19;
+ p += 20;
}
if ((page == 0x3f || page == 0x2a)
&& (bdrv_get_type_hint(s->bdrv) == BDRV_TYPE_CDROM)) {
@@ -437,7 +438,7 @@ int32_t scsi_send_command(SCSIDevice *s,
p[19] = (16 * 176) & 0xff;
p[20] = (16 * 176) >> 8; // 16x write speed current
p[21] = (16 * 176) & 0xff;
- p += 21;
+ p += 22;
}
r->buf_len = p - outbuf;
outbuf[0] = r->buf_len - 4;
[-- Attachment #3: lsi.txt --]
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Index: hw/lsi53c895a.c
===================================================================
RCS file: /sources/qemu/qemu/hw/lsi53c895a.c,v
retrieving revision 1.8
diff -u -p -r1.8 lsi53c895a.c
--- hw/lsi53c895a.c 22 Apr 2007 17:18:38 -0000 1.8
+++ hw/lsi53c895a.c 25 Apr 2007 04:55:11 -0000
@@ -855,6 +855,7 @@ again:
offset = sxt24(addr);
cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
s->dbc = cpu_to_le32(buf[0]);
+ s->rbc = s->dbc;
addr = cpu_to_le32(buf[1]);
}
if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
@@ -864,6 +865,8 @@ again:
break;
}
s->dnad = addr;
+ /* ??? Set ESA. */
+ s->ia = s->dsp - 8;
switch (s->sstat1 & 0x7) {
case PHASE_DO:
s->waiting = 2;
@@ -898,8 +901,6 @@ again:
s->sbc = s->dbc;
s->rbc -= s->dbc;
s->ua = addr + s->dbc;
- /* ??? Set ESA. */
- s->ia = s->dsp - 8;
break;
case 1: /* IO or Read/Write instruction. */
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2007-04-26 19:32 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2007-03-10 14:03 [Qemu-devel] scsi patch 王成業
2007-03-11 4:27 ` 王成業
2007-03-14 15:15 ` 王成業
2007-03-19 12:42 ` Thiemo Seufer
2007-03-19 14:37 ` Wang Cheng Yeh
2007-04-25 5:48 Wang Cheng Yeh
2007-04-26 19:26 ` Blue Swirl
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