* ✗ Fi.CI.CHECKPATCH: warning for Add support for Gen 11 pipe color features
2018-10-23 20:40 [PATCH 0/3] Add support for Gen 11 pipe color features Uma Shankar
@ 2018-10-23 20:39 ` Patchwork
2018-10-23 20:40 ` [PATCH 1/3] drm/i915/icl: Add degamma and gamma lut size to gen11 caps Uma Shankar
` (4 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-10-23 20:39 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Add support for Gen 11 pipe color features
URL : https://patchwork.freedesktop.org/series/51408/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2b3c9d4383c7 drm/i915/icl: Add degamma and gamma lut size to gen11 caps
e24af21b0a53 drm/i915/icl: Add icl pipe degamma and gamma support
-:69: CHECK:SPACING: No space is necessary after a cast
#69: FILE: drivers/gpu/drm/i915/intel_color.c:549:
+ (struct drm_color_lut *) state->degamma_lut->data;
total: 0 errors, 0 warnings, 1 checks, 114 lines checked
290861ec59f1 drm/i915/icl: Enable ICL Pipe CSC block
-:34: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#34: FILE: drivers/gpu/drm/i915/intel_color.c:244:
+ I915_WRITE(PIPE_CSC_MODE(pipe),
+ I915_READ(PIPE_CSC_MODE(pipe)) | CSC_ENABLE);
total: 0 errors, 0 warnings, 1 checks, 26 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 0/3] Add support for Gen 11 pipe color features
@ 2018-10-23 20:40 Uma Shankar
2018-10-23 20:39 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (5 more replies)
0 siblings, 6 replies; 13+ messages in thread
From: Uma Shankar @ 2018-10-23 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
This patch series adds support for Gen11 pipe degamma, CSC
and gamma hardware blocks.
CRC checks are not working for 10bit gamma but works for 8bit
pallete modes which seems to be due to some rounding errors in pipe.
ToDo: Support for Multi Segmented Gamma will be added later.
Uma Shankar (3):
drm/i915/icl: Add degamma and gamma lut size to gen11 caps
drm/i915/icl: Add icl pipe degamma and gamma support
drm/i915/icl: Enable ICL Pipe CSC block
drivers/gpu/drm/i915/i915_pci.c | 3 +-
drivers/gpu/drm/i915/i915_reg.h | 4 ++
drivers/gpu/drm/i915/intel_color.c | 82 +++++++++++++++++++++++++++++++++++++-
3 files changed, 87 insertions(+), 2 deletions(-)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/3] drm/i915/icl: Add degamma and gamma lut size to gen11 caps
2018-10-23 20:40 [PATCH 0/3] Add support for Gen 11 pipe color features Uma Shankar
2018-10-23 20:39 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2018-10-23 20:40 ` Uma Shankar
2018-10-24 13:18 ` Maarten Lankhorst
2018-10-23 20:40 ` [PATCH 2/3] drm/i915/icl: Add icl pipe degamma and gamma support Uma Shankar
` (3 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Uma Shankar @ 2018-10-23 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
Add the degamma and gamma lut sizes to gen11 capability
structure.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 44e7459..3c18ea2 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -603,7 +603,8 @@
TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
GEN(11), \
.ddb_size = 2048, \
- .has_logical_ring_elsq = 1
+ .has_logical_ring_elsq = 1, \
+ .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
static const struct intel_device_info intel_icelake_11_info = {
GEN11_FEATURES,
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/3] drm/i915/icl: Add icl pipe degamma and gamma support
2018-10-23 20:40 [PATCH 0/3] Add support for Gen 11 pipe color features Uma Shankar
2018-10-23 20:39 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-10-23 20:40 ` [PATCH 1/3] drm/i915/icl: Add degamma and gamma lut size to gen11 caps Uma Shankar
@ 2018-10-23 20:40 ` Uma Shankar
2018-10-24 13:33 ` Maarten Lankhorst
2018-10-23 20:40 ` [PATCH 3/3] drm/i915/icl: Enable ICL Pipe CSC block Uma Shankar
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Uma Shankar @ 2018-10-23 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
Add support for icl pipe degamma and gamma.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gpu/drm/i915/intel_color.c | 75 ++++++++++++++++++++++++++++++++++++++
2 files changed, 78 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8bd61f9..dd0514e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6965,6 +6965,9 @@ enum {
#define GAMMA_MODE_MODE_12BIT (2 << 0)
#define GAMMA_MODE_MODE_SPLIT (3 << 0)
+#define PRE_CSC_GAMMA_ENABLE (1 << 31)
+#define POST_CSC_GAMMA_ENABLE (1 << 31)
+
/* DMC/CSR */
#define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 5127da2..7860244 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -424,6 +424,7 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ uint32_t tmp;
WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
@@ -464,6 +465,11 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
}
+
+ if (IS_ICELAKE(dev_priv)) {
+ tmp = I915_READ(GAMMA_MODE(pipe));
+ I915_WRITE(GAMMA_MODE(pipe), tmp | POST_CSC_GAMMA_ENABLE);
+ }
}
/* Loads the palette/gamma unit for the CRTC on Broadwell+. */
@@ -523,6 +529,50 @@ static void glk_load_degamma_lut(struct drm_crtc_state *state)
I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
}
+static void icl_load_degamma_lut(struct drm_crtc_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
+ enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
+ const uint32_t lut_size = 33;
+ uint32_t tmp, i;
+
+ /*
+ * When setting the auto-increment bit, the hardware seems to
+ * ignore the index bits, so we need to reset it to index 0
+ * separately.
+ */
+ I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
+ I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
+
+ if (state->degamma_lut) {
+ struct drm_color_lut *lut =
+ (struct drm_color_lut *) state->degamma_lut->data;
+ for (i = 0; i < lut_size; i++) {
+ /*
+ * Currently Clamp input to 1.0.
+ * ToDo: Extend to max 7.0.
+ */
+ uint32_t word =
+ drm_color_lut_extract(lut[i].red, 16);
+ I915_WRITE(PRE_CSC_GAMC_DATA(pipe), word);
+ }
+ } else {
+ /* load a linear table. */
+ for (i = 0; i < lut_size; i++) {
+ uint32_t v = (i * (1 << 16)) / (lut_size - 1);
+
+ I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
+ }
+ }
+
+ tmp = I915_READ(GAMMA_MODE(pipe));
+ I915_WRITE(GAMMA_MODE(pipe), tmp | PRE_CSC_GAMMA_ENABLE);
+
+ /* Clamp values > 1.0. */
+ while (i++ < 35)
+ I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
+}
+
static void glk_load_luts(struct drm_crtc_state *state)
{
struct drm_crtc *crtc = state->crtc;
@@ -606,6 +656,29 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
}
+static void icl_load_luts(struct drm_crtc_state *state)
+{
+ struct drm_crtc *crtc = state->crtc;
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+
+ icl_load_degamma_lut(state);
+
+ if (crtc_state_is_legacy_gamma(state)) {
+ haswell_load_luts(state);
+ return;
+ }
+
+ bdw_load_gamma_lut(state, 0);
+ intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
+
+ I915_WRITE(GAMMA_MODE(pipe), I915_READ(GAMMA_MODE(pipe)) |
+ intel_state->gamma_mode);
+ POSTING_READ(GAMMA_MODE(pipe));
+}
+
void intel_color_load_luts(struct drm_crtc_state *crtc_state)
{
struct drm_device *dev = crtc_state->crtc->dev;
@@ -662,6 +735,8 @@ void intel_color_init(struct drm_crtc *crtc)
} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
dev_priv->display.load_luts = glk_load_luts;
+ } else if (IS_ICELAKE(dev_priv)) {
+ dev_priv->display.load_luts = icl_load_luts;
} else {
dev_priv->display.load_luts = i9xx_load_luts;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/3] drm/i915/icl: Enable ICL Pipe CSC block
2018-10-23 20:40 [PATCH 0/3] Add support for Gen 11 pipe color features Uma Shankar
` (2 preceding siblings ...)
2018-10-23 20:40 ` [PATCH 2/3] drm/i915/icl: Add icl pipe degamma and gamma support Uma Shankar
@ 2018-10-23 20:40 ` Uma Shankar
2018-10-24 13:38 ` Maarten Lankhorst
2018-10-23 20:55 ` ✓ Fi.CI.BAT: success for Add support for Gen 11 pipe color features Patchwork
2018-10-24 0:49 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 1 reply; 13+ messages in thread
From: Uma Shankar @ 2018-10-23 20:40 UTC (permalink / raw)
To: intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
Enable ICL pipe csc hardware. CSC block is enabled
in CSC_MODE register instead of PLANE_COLOR_CTL.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 7 ++++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dd0514e..0178761 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9700,6 +9700,7 @@ enum skl_power_gate {
#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
#define _PIPE_A_CSC_COEFF_BV 0x49024
#define _PIPE_A_CSC_MODE 0x49028
+#define CSC_ENABLE (1 << 31)
#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
#define CSC_MODE_YUV_TO_RGB (1 << 0)
diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
index 7860244..2ebfe3a 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -239,7 +239,11 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
- I915_WRITE(PIPE_CSC_MODE(pipe), 0);
+ if (INTEL_GEN(dev_priv) >= 11)
+ I915_WRITE(PIPE_CSC_MODE(pipe),
+ I915_READ(PIPE_CSC_MODE(pipe)) | CSC_ENABLE);
+ else
+ I915_WRITE(PIPE_CSC_MODE(pipe), 0);
} else {
uint32_t mode = CSC_MODE_YUV_TO_RGB;
@@ -736,6 +740,7 @@ void intel_color_init(struct drm_crtc *crtc)
dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
dev_priv->display.load_luts = glk_load_luts;
} else if (IS_ICELAKE(dev_priv)) {
+ dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
dev_priv->display.load_luts = icl_load_luts;
} else {
dev_priv->display.load_luts = i9xx_load_luts;
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 13+ messages in thread
* ✓ Fi.CI.BAT: success for Add support for Gen 11 pipe color features
2018-10-23 20:40 [PATCH 0/3] Add support for Gen 11 pipe color features Uma Shankar
` (3 preceding siblings ...)
2018-10-23 20:40 ` [PATCH 3/3] drm/i915/icl: Enable ICL Pipe CSC block Uma Shankar
@ 2018-10-23 20:55 ` Patchwork
2018-10-24 0:49 ` ✓ Fi.CI.IGT: " Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-10-23 20:55 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Add support for Gen 11 pipe color features
URL : https://patchwork.freedesktop.org/series/51408/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10553 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51408/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10553 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@amdgpu/amd_basic@cs-compute:
fi-kbl-8809g: NOTRUN -> FAIL (fdo#108094)
igt@amdgpu/amd_prime@amd-to-i915:
fi-kbl-8809g: NOTRUN -> FAIL (fdo#107341)
igt@drv_selftest@live_hangcheck:
fi-kbl-7560u: NOTRUN -> INCOMPLETE (fdo#108044)
igt@kms_flip@basic-flip-vs-dpms:
fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-blb-e6850: NOTRUN -> INCOMPLETE (fdo#107718)
==== Possible fixes ====
igt@drv_selftest@live_execlists:
fi-apl-guc: INCOMPLETE (fdo#106693) -> PASS
igt@gem_ctx_switch@basic-default:
fi-icl-u: DMESG-FAIL -> PASS
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
igt@kms_frontbuffer_tracking@basic:
fi-byt-clapper: FAIL (fdo#103167) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-a:
fi-byt-clapper: FAIL (fdo#107362) -> PASS
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#106693 https://bugs.freedesktop.org/show_bug.cgi?id=106693
fdo#107341 https://bugs.freedesktop.org/show_bug.cgi?id=107341
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044
fdo#108094 https://bugs.freedesktop.org/show_bug.cgi?id=108094
== Participating hosts (49 -> 44) ==
Additional (1): fi-kbl-7560u
Missing (6): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_5023 -> Patchwork_10553
CI_DRM_5023: 166bc98d7b77005943ab670506f164783cdc3f56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4688: fa6dbf8c048961356fd642df047cb58ab49309b2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10553: 290861ec59f1641b5e4bfb192cceb28ba3d03002 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
290861ec59f1 drm/i915/icl: Enable ICL Pipe CSC block
e24af21b0a53 drm/i915/icl: Add icl pipe degamma and gamma support
2b3c9d4383c7 drm/i915/icl: Add degamma and gamma lut size to gen11 caps
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10553/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
* ✓ Fi.CI.IGT: success for Add support for Gen 11 pipe color features
2018-10-23 20:40 [PATCH 0/3] Add support for Gen 11 pipe color features Uma Shankar
` (4 preceding siblings ...)
2018-10-23 20:55 ` ✓ Fi.CI.BAT: success for Add support for Gen 11 pipe color features Patchwork
@ 2018-10-24 0:49 ` Patchwork
5 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-10-24 0:49 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
== Series Details ==
Series: Add support for Gen 11 pipe color features
URL : https://patchwork.freedesktop.org/series/51408/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023_full -> Patchwork_10553_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10553_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_available_modes_crc@available_mode_test_crc:
shard-apl: PASS -> FAIL (fdo#106641)
igt@kms_busy@extended-pageflip-hang-newfb-render-b:
shard-apl: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
shard-snb: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_color@pipe-b-degamma:
shard-apl: PASS -> FAIL (fdo#104782)
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-apl: PASS -> FAIL (fdo#103232, fdo#103191)
igt@kms_cursor_crc@cursor-256x85-onscreen:
shard-glk: PASS -> FAIL (fdo#103232) +2
igt@kms_cursor_crc@cursor-64x21-onscreen:
shard-apl: PASS -> FAIL (fdo#103232) +1
igt@kms_flip@basic-flip-vs-modeset:
shard-hsw: PASS -> DMESG-WARN (fdo#102614)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-wc:
shard-glk: PASS -> FAIL (fdo#103167) +2
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-glk: PASS -> FAIL (fdo#103166) +2
igt@kms_plane@plane-position-covered-pipe-c-planes:
shard-apl: PASS -> FAIL (fdo#103166)
igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
shard-glk: PASS -> FAIL (fdo#108145)
igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
shard-skl: NOTRUN -> FAIL (fdo#108146)
igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
shard-apl: PASS -> FAIL (fdo#108145)
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
shard-snb: NOTRUN -> FAIL (fdo#99912)
igt@kms_vblank@pipe-c-ts-continuation-idle-hang:
shard-apl: PASS -> DMESG-WARN (fdo#103558, fdo#105602) +11
igt@pm_rpm@basic-rte:
shard-skl: PASS -> INCOMPLETE (fdo#107807)
==== Possible fixes ====
igt@kms_busy@extended-modeset-hang-newfb-render-a:
shard-snb: DMESG-WARN (fdo#107956) -> PASS
igt@kms_busy@extended-modeset-hang-newfb-render-b:
shard-skl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
shard-hsw: DMESG-WARN (fdo#107956) -> PASS
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-a:
shard-apl: DMESG-WARN (fdo#107956) -> PASS
igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
shard-glk: FAIL (fdo#108145) -> PASS +1
igt@kms_cursor_crc@cursor-256x256-sliding:
shard-glk: FAIL (fdo#103232) -> PASS +1
igt@kms_cursor_crc@cursor-64x21-offscreen:
shard-skl: FAIL (fdo#103232) -> PASS
igt@kms_flip@busy-flip-interruptible:
shard-skl: FAIL (fdo#103257) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-skl: FAIL (fdo#105363) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
shard-apl: FAIL (fdo#103167) -> PASS +2
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
shard-glk: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
shard-skl: FAIL (fdo#103167) -> PASS +1
igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
shard-skl: INCOMPLETE (fdo#104108, fdo#107773) -> PASS
igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
shard-apl: FAIL (fdo#103166) -> PASS +1
igt@kms_rotation_crc@sprite-rotation-180:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@kms_setmode@basic:
shard-hsw: FAIL (fdo#99912) -> PASS
igt@perf@short-reads:
shard-skl: FAIL (fdo#103183) -> PASS
igt@pm_rpm@legacy-planes-dpms:
shard-skl: INCOMPLETE (fdo#105959, fdo#107807) -> PASS
igt@syncobj_wait@single-wait-for-submit-unsubmitted:
shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS
==== Warnings ====
igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu:
shard-snb: INCOMPLETE (fdo#105411) -> DMESG-WARN (fdo#107469)
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103183 https://bugs.freedesktop.org/show_bug.cgi?id=103183
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103257 https://bugs.freedesktop.org/show_bug.cgi?id=103257
fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#105959 https://bugs.freedesktop.org/show_bug.cgi?id=105959
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
fdo#107469 https://bugs.freedesktop.org/show_bug.cgi?id=107469
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#108146 https://bugs.freedesktop.org/show_bug.cgi?id=108146
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_5023 -> Patchwork_10553
CI_DRM_5023: 166bc98d7b77005943ab670506f164783cdc3f56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4688: fa6dbf8c048961356fd642df047cb58ab49309b2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10553: 290861ec59f1641b5e4bfb192cceb28ba3d03002 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10553/shards.html
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] drm/i915/icl: Add degamma and gamma lut size to gen11 caps
2018-10-23 20:40 ` [PATCH 1/3] drm/i915/icl: Add degamma and gamma lut size to gen11 caps Uma Shankar
@ 2018-10-24 13:18 ` Maarten Lankhorst
2018-10-24 13:50 ` Shankar, Uma
0 siblings, 1 reply; 13+ messages in thread
From: Maarten Lankhorst @ 2018-10-24 13:18 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
Op 23-10-18 om 22:40 schreef Uma Shankar:
> Add the degamma and gamma lut sizes to gen11 capability
> structure.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 44e7459..3c18ea2 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -603,7 +603,8 @@
> TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \
> GEN(11), \
> .ddb_size = 2048, \
> - .has_logical_ring_elsq = 1
> + .has_logical_ring_elsq = 1, \
> + .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
>
> static const struct intel_device_info intel_icelake_11_info = {
> GEN11_FEATURES,
This patch should probably be after patch 3/3..
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/3] drm/i915/icl: Add icl pipe degamma and gamma support
2018-10-23 20:40 ` [PATCH 2/3] drm/i915/icl: Add icl pipe degamma and gamma support Uma Shankar
@ 2018-10-24 13:33 ` Maarten Lankhorst
2018-10-24 13:47 ` Shankar, Uma
0 siblings, 1 reply; 13+ messages in thread
From: Maarten Lankhorst @ 2018-10-24 13:33 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
Op 23-10-18 om 22:40 schreef Uma Shankar:
> Add support for icl pipe degamma and gamma.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ++
> drivers/gpu/drm/i915/intel_color.c | 75 ++++++++++++++++++++++++++++++++++++++
> 2 files changed, 78 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8bd61f9..dd0514e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6965,6 +6965,9 @@ enum {
> #define GAMMA_MODE_MODE_12BIT (2 << 0)
> #define GAMMA_MODE_MODE_SPLIT (3 << 0)
>
> +#define PRE_CSC_GAMMA_ENABLE (1 << 31)
> +#define POST_CSC_GAMMA_ENABLE (1 << 31)
? This can't be right.
> /* DMC/CSR */
> #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
> #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 5127da2..7860244 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -424,6 +424,7 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
> struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> + uint32_t tmp;
>
> WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
>
> @@ -464,6 +465,11 @@ static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset)
> I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
> I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
> }
> +
> + if (IS_ICELAKE(dev_priv)) {
> + tmp = I915_READ(GAMMA_MODE(pipe));
> + I915_WRITE(GAMMA_MODE(pipe), tmp | POST_CSC_GAMMA_ENABLE);
> + }
Could we just program the bits we care about, instead of doing this read?
> }
>
> /* Loads the palette/gamma unit for the CRTC on Broadwell+. */
> @@ -523,6 +529,50 @@ static void glk_load_degamma_lut(struct drm_crtc_state *state)
> I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
> }
>
> +static void icl_load_degamma_lut(struct drm_crtc_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
> + enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
> + const uint32_t lut_size = 33;
> + uint32_t tmp, i;
> +
> + /*
> + * When setting the auto-increment bit, the hardware seems to
> + * ignore the index bits, so we need to reset it to index 0
> + * separately.
> + */
> + I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
> + I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), PRE_CSC_GAMC_AUTO_INCREMENT);
> +
> + if (state->degamma_lut) {
> + struct drm_color_lut *lut =
> + (struct drm_color_lut *) state->degamma_lut->data;
> + for (i = 0; i < lut_size; i++) {
> + /*
> + * Currently Clamp input to 1.0.
> + * ToDo: Extend to max 7.0.
> + */
> + uint32_t word =
> + drm_color_lut_extract(lut[i].red, 16);
> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), word);
> + }
> + } else {
> + /* load a linear table. */
> + for (i = 0; i < lut_size; i++) {
> + uint32_t v = (i * (1 << 16)) / (lut_size - 1);
> +
> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
> + }
> + }
> +
> + tmp = I915_READ(GAMMA_MODE(pipe));
> + I915_WRITE(GAMMA_MODE(pipe), tmp | PRE_CSC_GAMMA_ENABLE);
Same here.. we know what gamma mode should be.
> +
> + /* Clamp values > 1.0. */
> + while (i++ < 35)
> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16));
> +}
> +
> static void glk_load_luts(struct drm_crtc_state *state)
> {
> struct drm_crtc *crtc = state->crtc;
> @@ -606,6 +656,29 @@ static void cherryview_load_luts(struct drm_crtc_state *state)
> i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state));
> }
>
> +static void icl_load_luts(struct drm_crtc_state *state)
> +{
> + struct drm_crtc *crtc = state->crtc;
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +
> + icl_load_degamma_lut(state);
> +
> + if (crtc_state_is_legacy_gamma(state)) {
> + haswell_load_luts(state);
> + return;
> + }
> +
> + bdw_load_gamma_lut(state, 0);
> + intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
> +
> + I915_WRITE(GAMMA_MODE(pipe), I915_READ(GAMMA_MODE(pipe)) |
> + intel_state->gamma_mode);
> + POSTING_READ(GAMMA_MODE(pipe));
Posting read can be removed.
> +}
> +
> void intel_color_load_luts(struct drm_crtc_state *crtc_state)
> {
> struct drm_device *dev = crtc_state->crtc->dev;
> @@ -662,6 +735,8 @@ void intel_color_init(struct drm_crtc *crtc)
> } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
> dev_priv->display.load_luts = glk_load_luts;
> + } else if (IS_ICELAKE(dev_priv)) {
> + dev_priv->display.load_luts = icl_load_luts;
> } else {
> dev_priv->display.load_luts = i9xx_load_luts;
> }
Just curious, how was this tested if we wrongly defined the Post CSC gamma bit?
~Maarten
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] drm/i915/icl: Enable ICL Pipe CSC block
2018-10-23 20:40 ` [PATCH 3/3] drm/i915/icl: Enable ICL Pipe CSC block Uma Shankar
@ 2018-10-24 13:38 ` Maarten Lankhorst
2018-10-24 14:00 ` Shankar, Uma
0 siblings, 1 reply; 13+ messages in thread
From: Maarten Lankhorst @ 2018-10-24 13:38 UTC (permalink / raw)
To: Uma Shankar, intel-gfx; +Cc: ville.syrjala, maarten.lankhorst
Op 23-10-18 om 22:40 schreef Uma Shankar:
> Enable ICL pipe csc hardware. CSC block is enabled
> in CSC_MODE register instead of PLANE_COLOR_CTL.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_color.c | 7 ++++++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dd0514e..0178761 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9700,6 +9700,7 @@ enum skl_power_gate {
> #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
> #define _PIPE_A_CSC_COEFF_BV 0x49024
> #define _PIPE_A_CSC_MODE 0x49028
> +#define CSC_ENABLE (1 << 31)
> #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
> #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
> #define CSC_MODE_YUV_TO_RGB (1 << 0)
> diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c
> index 7860244..2ebfe3a 100644
> --- a/drivers/gpu/drm/i915/intel_color.c
> +++ b/drivers/gpu/drm/i915/intel_color.c
> @@ -239,7 +239,11 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state)
> I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
> I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
>
> - I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> + if (INTEL_GEN(dev_priv) >= 11)
> + I915_WRITE(PIPE_CSC_MODE(pipe),
> + I915_READ(PIPE_CSC_MODE(pipe)) | CSC_ENABLE);
Just write CSC_ENABLE here, I think.
> + else
> + I915_WRITE(PIPE_CSC_MODE(pipe), 0);
> } else {
> uint32_t mode = CSC_MODE_YUV_TO_RGB;
Should there be a case in ilk_load_ycbcr_conversion_matrix as well?
Though it seems wrong that function ignore crtc_state->ctm in that case.
> @@ -736,6 +740,7 @@ void intel_color_init(struct drm_crtc *crtc)
> dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
> dev_priv->display.load_luts = glk_load_luts;
> } else if (IS_ICELAKE(dev_priv)) {
> + dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
> dev_priv->display.load_luts = icl_load_luts;
> } else {
> dev_priv->display.load_luts = i9xx_load_luts;
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/3] drm/i915/icl: Add icl pipe degamma and gamma support
2018-10-24 13:33 ` Maarten Lankhorst
@ 2018-10-24 13:47 ` Shankar, Uma
0 siblings, 0 replies; 13+ messages in thread
From: Shankar, Uma @ 2018-10-24 13:47 UTC (permalink / raw)
To: Maarten Lankhorst, intel-gfx; +Cc: Syrjala, Ville, Lankhorst, Maarten
>-----Original Message-----
>From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
>Sent: Wednesday, October 24, 2018 7:04 PM
>To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville <ville.syrjala@intel.com>; Lankhorst, Maarten
><maarten.lankhorst@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Add icl pipe degamma and
>gamma support
>
>Op 23-10-18 om 22:40 schreef Uma Shankar:
>> Add support for icl pipe degamma and gamma.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 3 ++
>> drivers/gpu/drm/i915/intel_color.c | 75
>> ++++++++++++++++++++++++++++++++++++++
>> 2 files changed, 78 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index 8bd61f9..dd0514e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6965,6 +6965,9 @@ enum {
>> #define GAMMA_MODE_MODE_12BIT (2 << 0)
>> #define GAMMA_MODE_MODE_SPLIT (3 << 0)
>>
>> +#define PRE_CSC_GAMMA_ENABLE (1 << 31)
>> +#define POST_CSC_GAMMA_ENABLE (1 << 31)
>? This can't be right.
Ah, My Bad. I tested with directly putting (1 << 30) in driver and while
publishing to external tried to add a macro. Late in the night :(
Thanks for catching this (it was correct in our internal review)
>> /* DMC/CSR */
>> #define CSR_PROGRAM(i) _MMIO(0x80000 + (i) * 4)
>> #define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 5127da2..7860244 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -424,6 +424,7 @@ static void bdw_load_gamma_lut(struct drm_crtc_state
>*state, u32 offset)
>> struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
>> enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
>> uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>> + uint32_t tmp;
>>
>> WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK);
>>
>> @@ -464,6 +465,11 @@ static void bdw_load_gamma_lut(struct
>drm_crtc_state *state, u32 offset)
>> I915_WRITE(PREC_PAL_GC_MAX(pipe, 1), (1 << 16) - 1);
>> I915_WRITE(PREC_PAL_GC_MAX(pipe, 2), (1 << 16) - 1);
>> }
>> +
>> + if (IS_ICELAKE(dev_priv)) {
>> + tmp = I915_READ(GAMMA_MODE(pipe));
>> + I915_WRITE(GAMMA_MODE(pipe), tmp |
>POST_CSC_GAMMA_ENABLE);
>> + }
>Could we just program the bits we care about, instead of doing this read?
Didn't want to disturb the existing "gamma mode" selected (degamma or gamma),
hence just appended to what was already there in the register. At a time, both
gamma and de-gamma can get called and selected in this registers.
>> }
>>
>> /* Loads the palette/gamma unit for the CRTC on Broadwell+. */ @@
>> -523,6 +529,50 @@ static void glk_load_degamma_lut(struct drm_crtc_state
>*state)
>> I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16)); }
>>
>> +static void icl_load_degamma_lut(struct drm_crtc_state *state) {
>> + struct drm_i915_private *dev_priv = to_i915(state->crtc->dev);
>> + enum pipe pipe = to_intel_crtc(state->crtc)->pipe;
>> + const uint32_t lut_size = 33;
>> + uint32_t tmp, i;
>> +
>> + /*
>> + * When setting the auto-increment bit, the hardware seems to
>> + * ignore the index bits, so we need to reset it to index 0
>> + * separately.
>> + */
>> + I915_WRITE(PRE_CSC_GAMC_INDEX(pipe), 0);
>> + I915_WRITE(PRE_CSC_GAMC_INDEX(pipe),
>PRE_CSC_GAMC_AUTO_INCREMENT);
>> +
>> + if (state->degamma_lut) {
>> + struct drm_color_lut *lut =
>> + (struct drm_color_lut *) state->degamma_lut->data;
>> + for (i = 0; i < lut_size; i++) {
>> + /*
>> + * Currently Clamp input to 1.0.
>> + * ToDo: Extend to max 7.0.
>> + */
>> + uint32_t word =
>> + drm_color_lut_extract(lut[i].red, 16);
>> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), word);
>> + }
>> + } else {
>> + /* load a linear table. */
>> + for (i = 0; i < lut_size; i++) {
>> + uint32_t v = (i * (1 << 16)) / (lut_size - 1);
>> +
>> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), v);
>> + }
>> + }
>> +
>> + tmp = I915_READ(GAMMA_MODE(pipe));
>> + I915_WRITE(GAMMA_MODE(pipe), tmp | PRE_CSC_GAMMA_ENABLE);
>Same here.. we know what gamma mode should be.
>> +
>> + /* Clamp values > 1.0. */
>> + while (i++ < 35)
>> + I915_WRITE(PRE_CSC_GAMC_DATA(pipe), (1 << 16)); }
>> +
>> static void glk_load_luts(struct drm_crtc_state *state) {
>> struct drm_crtc *crtc = state->crtc; @@ -606,6 +656,29 @@ static
>> void cherryview_load_luts(struct drm_crtc_state *state)
>> i9xx_load_luts_internal(crtc, NULL, to_intel_crtc_state(state)); }
>>
>> +static void icl_load_luts(struct drm_crtc_state *state) {
>> + struct drm_crtc *crtc = state->crtc;
>> + struct drm_device *dev = crtc->dev;
>> + struct drm_i915_private *dev_priv = to_i915(dev);
>> + struct intel_crtc_state *intel_state = to_intel_crtc_state(state);
>> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> +
>> + icl_load_degamma_lut(state);
>> +
>> + if (crtc_state_is_legacy_gamma(state)) {
>> + haswell_load_luts(state);
>> + return;
>> + }
>> +
>> + bdw_load_gamma_lut(state, 0);
>> + intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT;
>> +
>> + I915_WRITE(GAMMA_MODE(pipe), I915_READ(GAMMA_MODE(pipe)) |
>> + intel_state->gamma_mode);
>> + POSTING_READ(GAMMA_MODE(pipe));
>Posting read can be removed.
Ok Sure, will update that.
>> +}
>> +
>> void intel_color_load_luts(struct drm_crtc_state *crtc_state) {
>> struct drm_device *dev = crtc_state->crtc->dev; @@ -662,6 +735,8 @@
>> void intel_color_init(struct drm_crtc *crtc)
>> } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>> dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>> dev_priv->display.load_luts = glk_load_luts;
>> + } else if (IS_ICELAKE(dev_priv)) {
>> + dev_priv->display.load_luts = icl_load_luts;
>> } else {
>> dev_priv->display.load_luts = i9xx_load_luts;
>> }
>
>Just curious, how was this tested if we wrongly defined the Post CSC gamma bit?
As mentioned above, this was just a macro fumble while pushing for external :(
Regards,
Uma Shankar
>~Maarten
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/3] drm/i915/icl: Add degamma and gamma lut size to gen11 caps
2018-10-24 13:18 ` Maarten Lankhorst
@ 2018-10-24 13:50 ` Shankar, Uma
0 siblings, 0 replies; 13+ messages in thread
From: Shankar, Uma @ 2018-10-24 13:50 UTC (permalink / raw)
To: Maarten Lankhorst, intel-gfx; +Cc: Syrjala, Ville, Lankhorst, Maarten
>-----Original Message-----
>From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
>Sent: Wednesday, October 24, 2018 6:49 PM
>To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville <ville.syrjala@intel.com>; Lankhorst, Maarten
><maarten.lankhorst@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/icl: Add degamma and gamma lut
>size to gen11 caps
>
>Op 23-10-18 om 22:40 schreef Uma Shankar:
>> Add the degamma and gamma lut sizes to gen11 capability structure.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_pci.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c
>> b/drivers/gpu/drm/i915/i915_pci.c index 44e7459..3c18ea2 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -603,7 +603,8 @@
>> TRANSCODER_DSI0_OFFSET,
>TRANSCODER_DSI1_OFFSET}, \
>> GEN(11), \
>> .ddb_size = 2048, \
>> - .has_logical_ring_elsq = 1
>> + .has_logical_ring_elsq = 1, \
>> + .color = { .degamma_lut_size = 33, .gamma_lut_size = 1024 }
>>
>> static const struct intel_device_info intel_icelake_11_info = {
>> GEN11_FEATURES,
>
>This patch should probably be after patch 3/3..
Ok, will change the order. Thank You !!!
Regards,
Uma Shankar
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/3] drm/i915/icl: Enable ICL Pipe CSC block
2018-10-24 13:38 ` Maarten Lankhorst
@ 2018-10-24 14:00 ` Shankar, Uma
0 siblings, 0 replies; 13+ messages in thread
From: Shankar, Uma @ 2018-10-24 14:00 UTC (permalink / raw)
To: Maarten Lankhorst, intel-gfx; +Cc: Syrjala, Ville, Lankhorst, Maarten
>-----Original Message-----
>From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
>Sent: Wednesday, October 24, 2018 7:08 PM
>To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville <ville.syrjala@intel.com>; Lankhorst, Maarten
><maarten.lankhorst@intel.com>
>Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915/icl: Enable ICL Pipe CSC block
>
>Op 23-10-18 om 22:40 schreef Uma Shankar:
>> Enable ICL pipe csc hardware. CSC block is enabled in CSC_MODE
>> register instead of PLANE_COLOR_CTL.
>>
>> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> drivers/gpu/drm/i915/intel_color.c | 7 ++++++-
>> 2 files changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h index dd0514e..0178761 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -9700,6 +9700,7 @@ enum skl_power_gate {
>> #define _PIPE_A_CSC_COEFF_RV_GV 0x49020
>> #define _PIPE_A_CSC_COEFF_BV 0x49024
>> #define _PIPE_A_CSC_MODE 0x49028
>> +#define CSC_ENABLE (1 << 31)
>> #define CSC_BLACK_SCREEN_OFFSET (1 << 2)
>> #define CSC_POSITION_BEFORE_GAMMA (1 << 1)
>> #define CSC_MODE_YUV_TO_RGB (1 << 0)
>> diff --git a/drivers/gpu/drm/i915/intel_color.c
>> b/drivers/gpu/drm/i915/intel_color.c
>> index 7860244..2ebfe3a 100644
>> --- a/drivers/gpu/drm/i915/intel_color.c
>> +++ b/drivers/gpu/drm/i915/intel_color.c
>> @@ -239,7 +239,11 @@ static void ilk_load_csc_matrix(struct drm_crtc_state
>*crtc_state)
>> I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
>> I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
>>
>> - I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>> + if (INTEL_GEN(dev_priv) >= 11)
>> + I915_WRITE(PIPE_CSC_MODE(pipe),
>> + I915_READ(PIPE_CSC_MODE(pipe)) |
>CSC_ENABLE);
>Just write CSC_ENABLE here, I think.
Yes, this could be done as of now since PIPE OUTPUT CSC is not enabled.
Was keeping it as a failsafe for future once that feature gets enabled, this
may start overwriting that and will cause some bug and debug to hunt where
the value got overwritten :)
>> + else
>> + I915_WRITE(PIPE_CSC_MODE(pipe), 0);
>> } else {
>> uint32_t mode = CSC_MODE_YUV_TO_RGB;
>Should there be a case in ilk_load_ycbcr_conversion_matrix as well?
>Though it seems wrong that function ignore crtc_state->ctm in that case.
This is a good catch and it should be added there as well. Since this was a case
of hardcoded co-efficients, I believe it doesn't bother about userspace LUT blob,
so that should be ok.
Thanks Maarten for the review and very useful comments. I will update the patches
and refloat.
Regards,
Uma Shankar
>> @@ -736,6 +740,7 @@ void intel_color_init(struct drm_crtc *crtc)
>> dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>> dev_priv->display.load_luts = glk_load_luts;
>> } else if (IS_ICELAKE(dev_priv)) {
>> + dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>> dev_priv->display.load_luts = icl_load_luts;
>> } else {
>> dev_priv->display.load_luts = i9xx_load_luts;
>
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2018-10-24 14:00 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-23 20:40 [PATCH 0/3] Add support for Gen 11 pipe color features Uma Shankar
2018-10-23 20:39 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-10-23 20:40 ` [PATCH 1/3] drm/i915/icl: Add degamma and gamma lut size to gen11 caps Uma Shankar
2018-10-24 13:18 ` Maarten Lankhorst
2018-10-24 13:50 ` Shankar, Uma
2018-10-23 20:40 ` [PATCH 2/3] drm/i915/icl: Add icl pipe degamma and gamma support Uma Shankar
2018-10-24 13:33 ` Maarten Lankhorst
2018-10-24 13:47 ` Shankar, Uma
2018-10-23 20:40 ` [PATCH 3/3] drm/i915/icl: Enable ICL Pipe CSC block Uma Shankar
2018-10-24 13:38 ` Maarten Lankhorst
2018-10-24 14:00 ` Shankar, Uma
2018-10-23 20:55 ` ✓ Fi.CI.BAT: success for Add support for Gen 11 pipe color features Patchwork
2018-10-24 0:49 ` ✓ Fi.CI.IGT: " Patchwork
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