* [U-Boot] [PATCH v1] arm: socfpga: Enable Stratix10 SMMU access
@ 2019-11-15 17:20 thor.thayer at linux.intel.com
2019-11-16 11:09 ` Marek Vasut
0 siblings, 1 reply; 6+ messages in thread
From: thor.thayer at linux.intel.com @ 2019-11-15 17:20 UTC (permalink / raw)
To: u-boot
From: Thor Thayer <thor.thayer@linux.intel.com>
Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
---
arch/arm/mach-socfpga/include/mach/firewall_s10.h | 7 +++++++
drivers/ddr/altera/sdram_s10.c | 14 ++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
index b96f779f1487..d698e4b9e2a1 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
@@ -95,6 +95,13 @@ struct socfpga_firwall_l4_sys {
#define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE0 0x2c520
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A 0x2c540
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B 0x2c560
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C 0x2c580
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D 0x2c5a0
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E 0x2c5c0
+
#define CCU_ADMASK_P_MASK BIT(0)
#define CCU_ADMASK_NS_MASK BIT(1)
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 56cbbac9fe1f..bc027c478452 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -323,6 +323,20 @@ static int sdram_mmr_init_full(struct udevice *dev)
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
CCU_ADBASE_DI_MASK);
+ /* Enable access to DDR from TCU */
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
+ CCU_ADBASE_DI_MASK);
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
+ CCU_ADBASE_DI_MASK);
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
+ CCU_ADBASE_DI_MASK);
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
+ CCU_ADBASE_DI_MASK);
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
+ CCU_ADBASE_DI_MASK);
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
+ CCU_ADBASE_DI_MASK);
+
/* this enables nonsecure access to DDR */
/* mpuregion0addr_limit */
FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH v1] arm: socfpga: Enable Stratix10 SMMU access
2019-11-15 17:20 [U-Boot] [PATCH v1] arm: socfpga: Enable Stratix10 SMMU access thor.thayer at linux.intel.com
@ 2019-11-16 11:09 ` Marek Vasut
2019-11-18 2:46 ` Tan, Ley Foon
0 siblings, 1 reply; 6+ messages in thread
From: Marek Vasut @ 2019-11-16 11:09 UTC (permalink / raw)
To: u-boot
On 11/15/19 6:20 PM, Thor Thayer wrote:
>
> Enable TCU access through the Stratix10 CCU so that the
> SMMU can access the SDRAM.
>
[...]
Looks good to me. Ley, can you take a look?
Thanks!
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v1] arm: socfpga: Enable Stratix10 SMMU access
2019-11-16 11:09 ` Marek Vasut
@ 2019-11-18 2:46 ` Tan, Ley Foon
2019-11-18 7:27 ` Marek Vasut
0 siblings, 1 reply; 6+ messages in thread
From: Tan, Ley Foon @ 2019-11-18 2:46 UTC (permalink / raw)
To: u-boot
> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, November 16, 2019 7:10 PM
> To: thor.thayer at linux.intel.com; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>
> Cc: u-boot at lists.denx.de; Albert Aribaud <albert.u.boot@aribaud.net>; Tan,
> Ley Foon <ley.foon.tan@intel.com>; Dinh Nguyen <dinguyen@kernel.org>;
> Tom Rini <trini@konsulko.com>; Westergreen, Dalon
> <dalon.westergreen@intel.com>
> Subject: Re: [PATCH v1] arm: socfpga: Enable Stratix10 SMMU access
>
> On 11/15/19 6:20 PM, Thor Thayer wrote:
> >
> > Enable TCU access through the Stratix10 CCU so that the SMMU can
> > access the SDRAM.
> >
>
> [...]
>
> Looks good to me. Ley, can you take a look?
> Thanks!
Looks good to me too.
But, if this patch plan to apply after Agilex patch series, then need to rebase on top of it.
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v1] arm: socfpga: Enable Stratix10 SMMU access
2019-11-18 2:46 ` Tan, Ley Foon
@ 2019-11-18 7:27 ` Marek Vasut
2019-11-18 18:14 ` Thor Thayer
0 siblings, 1 reply; 6+ messages in thread
From: Marek Vasut @ 2019-11-18 7:27 UTC (permalink / raw)
To: u-boot
On 11/18/19 3:46 AM, Tan, Ley Foon wrote:
[...]
>>
>> On 11/15/19 6:20 PM, Thor Thayer wrote:
>>>
>>> Enable TCU access through the Stratix10 CCU so that the SMMU can
>>> access the SDRAM.
>>>
>>
>> [...]
>>
>> Looks good to me. Ley, can you take a look?
>> Thanks!
> Looks good to me too.
> But, if this patch plan to apply after Agilex patch series, then need to rebase on top of it.
Is this a fix or a feature ?
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v1] arm: socfpga: Enable Stratix10 SMMU access
2019-11-18 7:27 ` Marek Vasut
@ 2019-11-18 18:14 ` Thor Thayer
2019-11-18 18:25 ` Marek Vasut
0 siblings, 1 reply; 6+ messages in thread
From: Thor Thayer @ 2019-11-18 18:14 UTC (permalink / raw)
To: u-boot
On 11/18/19 1:27 AM, Marek Vasut wrote:
> On 11/18/19 3:46 AM, Tan, Ley Foon wrote:
> [...]
>
>>>
>>> On 11/15/19 6:20 PM, Thor Thayer wrote:
>>>>
>>>> Enable TCU access through the Stratix10 CCU so that the SMMU can
>>>> access the SDRAM.
>>>>
>>>
>>> [...]
>>>
>>> Looks good to me. Ley, can you take a look?
>>> Thanks!
>> Looks good to me too.
>> But, if this patch plan to apply after Agilex patch series, then need to rebase on top of it.
>
> Is this a fix or a feature ?
>
This is a feature.
I didn't realize there was a refactoring. I will coordinate with Ley
Foon. Thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH v1] arm: socfpga: Enable Stratix10 SMMU access
2019-11-18 18:14 ` Thor Thayer
@ 2019-11-18 18:25 ` Marek Vasut
0 siblings, 0 replies; 6+ messages in thread
From: Marek Vasut @ 2019-11-18 18:25 UTC (permalink / raw)
To: u-boot
On 11/18/19 7:14 PM, Thor Thayer wrote:
> On 11/18/19 1:27 AM, Marek Vasut wrote:
>> On 11/18/19 3:46 AM, Tan, Ley Foon wrote:
>> [...]
>>
>>>>
>>>> On 11/15/19 6:20 PM, Thor Thayer wrote:
>>>>>
>>>>> Enable TCU access through the Stratix10 CCU so that the SMMU can
>>>>> access the SDRAM.
>>>>>
>>>>
>>>> [...]
>>>>
>>>> Looks good to me. Ley, can you take a look?
>>>> Thanks!
>>> Looks good to me too.
>>> But, if this patch plan to apply after Agilex patch series, then need
>>> to rebase on top of it.
>>
>> Is this a fix or a feature ?
>>
> This is a feature.
>
> I didn't realize there was a refactoring. I will coordinate with Ley
> Foon. Thanks.
OK, sounds good, thanks.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-11-18 18:25 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-15 17:20 [U-Boot] [PATCH v1] arm: socfpga: Enable Stratix10 SMMU access thor.thayer at linux.intel.com
2019-11-16 11:09 ` Marek Vasut
2019-11-18 2:46 ` Tan, Ley Foon
2019-11-18 7:27 ` Marek Vasut
2019-11-18 18:14 ` Thor Thayer
2019-11-18 18:25 ` Marek Vasut
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