* [PATCH 0/2] interconnect: qcom: rpmh: sm8550: mask to send as vote
@ 2023-06-19 8:24 Neil Armstrong
2023-06-19 8:24 ` [PATCH 1/2] interconnect: qcom: rpmh: add optional " Neil Armstrong
2023-06-19 8:24 ` [PATCH 2/2] interconnect: qcom: sm8550: add enable_mask for bcm nodes Neil Armstrong
0 siblings, 2 replies; 8+ messages in thread
From: Neil Armstrong @ 2023-06-19 8:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel, Neil Armstrong
On the SM8550 SoC, some nodes requires a specific bit mark
instead of a bandwidth when voting.
Add an enable_mask variable to be used instead of bandwidth.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Neil Armstrong (2):
interconnect: qcom: rpmh: add optional mask to send as vote
interconnect: qcom: sm8550: add enable_mask for bcm nodes
drivers/interconnect/qcom/bcm-voter.c | 5 +++++
drivers/interconnect/qcom/icc-rpmh.h | 2 ++
drivers/interconnect/qcom/sm8550.c | 17 +++++++++++++++++
3 files changed, 24 insertions(+)
---
base-commit: 47045630bc409ce6606d97b790895210dd1d517d
change-id: 20230619-topic-sm8550-upstream-interconnect-mask-vote-96aa20355158
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 1/2] interconnect: qcom: rpmh: add optional mask to send as vote
2023-06-19 8:24 [PATCH 0/2] interconnect: qcom: rpmh: sm8550: mask to send as vote Neil Armstrong
@ 2023-06-19 8:24 ` Neil Armstrong
2023-06-19 9:45 ` Konrad Dybcio
2023-06-19 8:24 ` [PATCH 2/2] interconnect: qcom: sm8550: add enable_mask for bcm nodes Neil Armstrong
1 sibling, 1 reply; 8+ messages in thread
From: Neil Armstrong @ 2023-06-19 8:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel, Neil Armstrong
On the SM8550 SoC, some nodes requires a specific bit mark
instead of a bandwidth when voting.
Add an enable_mask variable to be used to vote when a node
is enabled in an aggregate loop.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/interconnect/qcom/bcm-voter.c | 5 +++++
drivers/interconnect/qcom/icc-rpmh.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c
index 8f385f9c2dd3..d5f2a6b5376b 100644
--- a/drivers/interconnect/qcom/bcm-voter.c
+++ b/drivers/interconnect/qcom/bcm-voter.c
@@ -83,6 +83,11 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
temp = agg_peak[bucket] * bcm->vote_scale;
bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit);
+
+ if (bcm->enable_mask && (bcm->vote_x[bucket] || bcm->vote_y[bucket])) {
+ bcm->vote_x[bucket] = 0;
+ bcm->vote_y[bucket] = bcm->enable_mask;
+ }
}
if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
index 04391c1ba465..7843d8864d6b 100644
--- a/drivers/interconnect/qcom/icc-rpmh.h
+++ b/drivers/interconnect/qcom/icc-rpmh.h
@@ -81,6 +81,7 @@ struct qcom_icc_node {
* @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
* @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm
* @vote_scale: scaling factor for vote_x and vote_y
+ * @enable_mask: optional mask to send as vote instead of vote_x/vote_y
* @dirty: flag used to indicate whether the bcm needs to be committed
* @keepalive: flag used to indicate whether a keepalive is required
* @aux_data: auxiliary data used when calculating threshold values and
@@ -97,6 +98,7 @@ struct qcom_icc_bcm {
u64 vote_x[QCOM_ICC_NUM_BUCKETS];
u64 vote_y[QCOM_ICC_NUM_BUCKETS];
u64 vote_scale;
+ u32 enable_mask;
bool dirty;
bool keepalive;
struct bcm_db aux_data;
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] interconnect: qcom: sm8550: add enable_mask for bcm nodes
2023-06-19 8:24 [PATCH 0/2] interconnect: qcom: rpmh: sm8550: mask to send as vote Neil Armstrong
2023-06-19 8:24 ` [PATCH 1/2] interconnect: qcom: rpmh: add optional " Neil Armstrong
@ 2023-06-19 8:24 ` Neil Armstrong
2023-06-19 9:55 ` Konrad Dybcio
1 sibling, 1 reply; 8+ messages in thread
From: Neil Armstrong @ 2023-06-19 8:24 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel, Neil Armstrong
Set the proper enable_mask to needs requiring such value
to be used instead of a bandwidth when voting.
The masks were copied from the downstream implementation at [1].
[1] https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.15.r1-rel/drivers/interconnect/qcom/kalama.c
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
drivers/interconnect/qcom/sm8550.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c
index d823ba988ef6..0864ed285375 100644
--- a/drivers/interconnect/qcom/sm8550.c
+++ b/drivers/interconnect/qcom/sm8550.c
@@ -1473,6 +1473,7 @@ static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
+ .enable_mask = 0x8,
.num_nodes = 1,
.nodes = { &ebi },
};
@@ -1485,6 +1486,7 @@ static struct qcom_icc_bcm bcm_ce0 = {
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
+ .enable_mask = 0x1,
.keepalive = true,
.num_nodes = 54,
.nodes = { &qsm_cfg, &qhs_ahb2phy0,
@@ -1524,6 +1526,7 @@ static struct qcom_icc_bcm bcm_cn1 = {
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
+ .enable_mask = 0x1,
.num_nodes = 2,
.nodes = { &qxm_nsp, &qns_nsp_gemnoc },
};
@@ -1549,6 +1552,7 @@ static struct qcom_icc_bcm bcm_mm0 = {
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
+ .enable_mask = 0x1,
.num_nodes = 8,
.nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
&qnm_camnoc_sf, &qnm_vapss_hcp,
@@ -1589,6 +1593,7 @@ static struct qcom_icc_bcm bcm_sh0 = {
static struct qcom_icc_bcm bcm_sh1 = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 13,
.nodes = { &alm_gpu_tcu, &alm_sys_tcu,
&chm_apps, &qnm_gpu,
@@ -1608,6 +1613,7 @@ static struct qcom_icc_bcm bcm_sn0 = {
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
+ .enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qhm_gic, &xm_gic,
&qns_gemnoc_gc },
@@ -1633,6 +1639,7 @@ static struct qcom_icc_bcm bcm_sn7 = {
static struct qcom_icc_bcm bcm_acv_disp = {
.name = "ACV",
+ .enable_mask = 0x1,
.num_nodes = 1,
.nodes = { &ebi_disp },
};
@@ -1657,12 +1664,14 @@ static struct qcom_icc_bcm bcm_sh0_disp = {
static struct qcom_icc_bcm bcm_sh1_disp = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 2,
.nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
};
static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
.name = "ACV",
+ .enable_mask = 0x0,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_0 },
};
@@ -1681,6 +1690,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
.name = "MM1",
+ .enable_mask = 0x1,
.num_nodes = 4,
.nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
&qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
@@ -1694,6 +1704,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
&qnm_pcie_cam_ife_0 },
@@ -1701,6 +1712,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
.name = "ACV",
+ .enable_mask = 0x0,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_1 },
};
@@ -1719,6 +1731,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
.name = "MM1",
+ .enable_mask = 0x1,
.num_nodes = 4,
.nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
&qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
@@ -1732,6 +1745,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
&qnm_pcie_cam_ife_1 },
@@ -1739,6 +1753,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
.name = "ACV",
+ .enable_mask = 0x0,
.num_nodes = 1,
.nodes = { &ebi_cam_ife_2 },
};
@@ -1757,6 +1772,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
.name = "MM1",
+ .enable_mask = 0x1,
.num_nodes = 4,
.nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
&qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
@@ -1770,6 +1786,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
.name = "SH1",
+ .enable_mask = 0x1,
.num_nodes = 3,
.nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
&qnm_pcie_cam_ife_2 },
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] interconnect: qcom: rpmh: add optional mask to send as vote
2023-06-19 8:24 ` [PATCH 1/2] interconnect: qcom: rpmh: add optional " Neil Armstrong
@ 2023-06-19 9:45 ` Konrad Dybcio
2023-06-19 9:47 ` Neil Armstrong
0 siblings, 1 reply; 8+ messages in thread
From: Konrad Dybcio @ 2023-06-19 9:45 UTC (permalink / raw)
To: Neil Armstrong, Andy Gross, Bjorn Andersson, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel
On 19.06.2023 10:24, Neil Armstrong wrote:
> On the SM8550 SoC, some nodes requires a specific bit mark
> instead of a bandwidth when voting.
>
> Add an enable_mask variable to be used to vote when a node
> is enabled in an aggregate loop.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
Would be nice to mention that it's literally this commit:
https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/commit/2d1573e0206998151b342e6b52a4c0f7234d7e36
For the code:
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/interconnect/qcom/bcm-voter.c | 5 +++++
> drivers/interconnect/qcom/icc-rpmh.h | 2 ++
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c
> index 8f385f9c2dd3..d5f2a6b5376b 100644
> --- a/drivers/interconnect/qcom/bcm-voter.c
> +++ b/drivers/interconnect/qcom/bcm-voter.c
> @@ -83,6 +83,11 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
>
> temp = agg_peak[bucket] * bcm->vote_scale;
> bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit);
> +
> + if (bcm->enable_mask && (bcm->vote_x[bucket] || bcm->vote_y[bucket])) {
> + bcm->vote_x[bucket] = 0;
> + bcm->vote_y[bucket] = bcm->enable_mask;
> + }
> }
>
> if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
> diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
> index 04391c1ba465..7843d8864d6b 100644
> --- a/drivers/interconnect/qcom/icc-rpmh.h
> +++ b/drivers/interconnect/qcom/icc-rpmh.h
> @@ -81,6 +81,7 @@ struct qcom_icc_node {
> * @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
> * @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm
> * @vote_scale: scaling factor for vote_x and vote_y
> + * @enable_mask: optional mask to send as vote instead of vote_x/vote_y
> * @dirty: flag used to indicate whether the bcm needs to be committed
> * @keepalive: flag used to indicate whether a keepalive is required
> * @aux_data: auxiliary data used when calculating threshold values and
> @@ -97,6 +98,7 @@ struct qcom_icc_bcm {
> u64 vote_x[QCOM_ICC_NUM_BUCKETS];
> u64 vote_y[QCOM_ICC_NUM_BUCKETS];
> u64 vote_scale;
> + u32 enable_mask;
> bool dirty;
> bool keepalive;
> struct bcm_db aux_data;
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] interconnect: qcom: rpmh: add optional mask to send as vote
2023-06-19 9:45 ` Konrad Dybcio
@ 2023-06-19 9:47 ` Neil Armstrong
2023-06-19 12:59 ` Dmitry Baryshkov
0 siblings, 1 reply; 8+ messages in thread
From: Neil Armstrong @ 2023-06-19 9:47 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel
Hi,
On 19/06/2023 11:45, Konrad Dybcio wrote:
> On 19.06.2023 10:24, Neil Armstrong wrote:
>> On the SM8550 SoC, some nodes requires a specific bit mark
>> instead of a bandwidth when voting.
>>
>> Add an enable_mask variable to be used to vote when a node
>> is enabled in an aggregate loop.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
> Would be nice to mention that it's literally this commit:
>
> https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/commit/2d1573e0206998151b342e6b52a4c0f7234d7e36
Good catch, I just copied the bits but yeah in fine it's the same...
I'll refer to it in a v2.
>
> For the code:
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Thanks,
Neil
>
> Konrad
>> drivers/interconnect/qcom/bcm-voter.c | 5 +++++
>> drivers/interconnect/qcom/icc-rpmh.h | 2 ++
>> 2 files changed, 7 insertions(+)
>>
>> diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c
>> index 8f385f9c2dd3..d5f2a6b5376b 100644
>> --- a/drivers/interconnect/qcom/bcm-voter.c
>> +++ b/drivers/interconnect/qcom/bcm-voter.c
>> @@ -83,6 +83,11 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
>>
>> temp = agg_peak[bucket] * bcm->vote_scale;
>> bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit);
>> +
>> + if (bcm->enable_mask && (bcm->vote_x[bucket] || bcm->vote_y[bucket])) {
>> + bcm->vote_x[bucket] = 0;
>> + bcm->vote_y[bucket] = bcm->enable_mask;
>> + }
>> }
>>
>> if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
>> diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
>> index 04391c1ba465..7843d8864d6b 100644
>> --- a/drivers/interconnect/qcom/icc-rpmh.h
>> +++ b/drivers/interconnect/qcom/icc-rpmh.h
>> @@ -81,6 +81,7 @@ struct qcom_icc_node {
>> * @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
>> * @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm
>> * @vote_scale: scaling factor for vote_x and vote_y
>> + * @enable_mask: optional mask to send as vote instead of vote_x/vote_y
>> * @dirty: flag used to indicate whether the bcm needs to be committed
>> * @keepalive: flag used to indicate whether a keepalive is required
>> * @aux_data: auxiliary data used when calculating threshold values and
>> @@ -97,6 +98,7 @@ struct qcom_icc_bcm {
>> u64 vote_x[QCOM_ICC_NUM_BUCKETS];
>> u64 vote_y[QCOM_ICC_NUM_BUCKETS];
>> u64 vote_scale;
>> + u32 enable_mask;
>> bool dirty;
>> bool keepalive;
>> struct bcm_db aux_data;
>>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] interconnect: qcom: sm8550: add enable_mask for bcm nodes
2023-06-19 8:24 ` [PATCH 2/2] interconnect: qcom: sm8550: add enable_mask for bcm nodes Neil Armstrong
@ 2023-06-19 9:55 ` Konrad Dybcio
2023-06-19 10:09 ` Neil Armstrong
0 siblings, 1 reply; 8+ messages in thread
From: Konrad Dybcio @ 2023-06-19 9:55 UTC (permalink / raw)
To: Neil Armstrong, Andy Gross, Bjorn Andersson, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel
On 19.06.2023 10:24, Neil Armstrong wrote:
> Set the proper enable_mask to needs requiring such value
> to be used instead of a bandwidth when voting.
>
> The masks were copied from the downstream implementation at [1].
>
> [1] https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.15.r1-rel/drivers/interconnect/qcom/kalama.c
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
The values match downstream, so:
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Since you're already touching this code, may I turn your interest to:
1. Adding enable_mask-s to 8450 and 8775
2. Porting https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/commit/d5edeca085f4
3. Adding the default perf settings for 8450 and 8550
Konrad
> drivers/interconnect/qcom/sm8550.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c
> index d823ba988ef6..0864ed285375 100644
> --- a/drivers/interconnect/qcom/sm8550.c
> +++ b/drivers/interconnect/qcom/sm8550.c
> @@ -1473,6 +1473,7 @@ static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
>
> static struct qcom_icc_bcm bcm_acv = {
> .name = "ACV",
> + .enable_mask = 0x8,
> .num_nodes = 1,
> .nodes = { &ebi },
> };
> @@ -1485,6 +1486,7 @@ static struct qcom_icc_bcm bcm_ce0 = {
>
> static struct qcom_icc_bcm bcm_cn0 = {
> .name = "CN0",
> + .enable_mask = 0x1,
> .keepalive = true,
> .num_nodes = 54,
> .nodes = { &qsm_cfg, &qhs_ahb2phy0,
> @@ -1524,6 +1526,7 @@ static struct qcom_icc_bcm bcm_cn1 = {
>
> static struct qcom_icc_bcm bcm_co0 = {
> .name = "CO0",
> + .enable_mask = 0x1,
> .num_nodes = 2,
> .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
> };
> @@ -1549,6 +1552,7 @@ static struct qcom_icc_bcm bcm_mm0 = {
>
> static struct qcom_icc_bcm bcm_mm1 = {
> .name = "MM1",
> + .enable_mask = 0x1,
> .num_nodes = 8,
> .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
> &qnm_camnoc_sf, &qnm_vapss_hcp,
> @@ -1589,6 +1593,7 @@ static struct qcom_icc_bcm bcm_sh0 = {
>
> static struct qcom_icc_bcm bcm_sh1 = {
> .name = "SH1",
> + .enable_mask = 0x1,
> .num_nodes = 13,
> .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
> &chm_apps, &qnm_gpu,
> @@ -1608,6 +1613,7 @@ static struct qcom_icc_bcm bcm_sn0 = {
>
> static struct qcom_icc_bcm bcm_sn1 = {
> .name = "SN1",
> + .enable_mask = 0x1,
> .num_nodes = 3,
> .nodes = { &qhm_gic, &xm_gic,
> &qns_gemnoc_gc },
> @@ -1633,6 +1639,7 @@ static struct qcom_icc_bcm bcm_sn7 = {
>
> static struct qcom_icc_bcm bcm_acv_disp = {
> .name = "ACV",
> + .enable_mask = 0x1,
> .num_nodes = 1,
> .nodes = { &ebi_disp },
> };
> @@ -1657,12 +1664,14 @@ static struct qcom_icc_bcm bcm_sh0_disp = {
>
> static struct qcom_icc_bcm bcm_sh1_disp = {
> .name = "SH1",
> + .enable_mask = 0x1,
> .num_nodes = 2,
> .nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
> };
>
> static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
> .name = "ACV",
> + .enable_mask = 0x0,
> .num_nodes = 1,
> .nodes = { &ebi_cam_ife_0 },
> };
> @@ -1681,6 +1690,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
>
> static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
> .name = "MM1",
> + .enable_mask = 0x1,
> .num_nodes = 4,
> .nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
> &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
> @@ -1694,6 +1704,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
>
> static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
> .name = "SH1",
> + .enable_mask = 0x1,
> .num_nodes = 3,
> .nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
> &qnm_pcie_cam_ife_0 },
> @@ -1701,6 +1712,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
>
> static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
> .name = "ACV",
> + .enable_mask = 0x0,
> .num_nodes = 1,
> .nodes = { &ebi_cam_ife_1 },
> };
> @@ -1719,6 +1731,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
>
> static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
> .name = "MM1",
> + .enable_mask = 0x1,
> .num_nodes = 4,
> .nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
> &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
> @@ -1732,6 +1745,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
>
> static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
> .name = "SH1",
> + .enable_mask = 0x1,
> .num_nodes = 3,
> .nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
> &qnm_pcie_cam_ife_1 },
> @@ -1739,6 +1753,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
>
> static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
> .name = "ACV",
> + .enable_mask = 0x0,
> .num_nodes = 1,
> .nodes = { &ebi_cam_ife_2 },
> };
> @@ -1757,6 +1772,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
>
> static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
> .name = "MM1",
> + .enable_mask = 0x1,
> .num_nodes = 4,
> .nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
> &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
> @@ -1770,6 +1786,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
>
> static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
> .name = "SH1",
> + .enable_mask = 0x1,
> .num_nodes = 3,
> .nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
> &qnm_pcie_cam_ife_2 },
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] interconnect: qcom: sm8550: add enable_mask for bcm nodes
2023-06-19 9:55 ` Konrad Dybcio
@ 2023-06-19 10:09 ` Neil Armstrong
0 siblings, 0 replies; 8+ messages in thread
From: Neil Armstrong @ 2023-06-19 10:09 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Georgi Djakov
Cc: linux-arm-msm, linux-pm, linux-kernel
On 19/06/2023 11:55, Konrad Dybcio wrote:
> On 19.06.2023 10:24, Neil Armstrong wrote:
>> Set the proper enable_mask to needs requiring such value
>> to be used instead of a bandwidth when voting.
>>
>> The masks were copied from the downstream implementation at [1].
>>
>> [1] https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.15.r1-rel/drivers/interconnect/qcom/kalama.c
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
> The values match downstream, so:
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Since you're already touching this code, may I turn your interest to:
>
> 1. Adding enable_mask-s to 8450 and 8775
>
> 2. Porting https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/commit/d5edeca085f4
>
> 3. Adding the default perf settings for 8450 and 8550
Yep this would be the next steps.
Neil
>
> Konrad
>
>> drivers/interconnect/qcom/sm8550.c | 17 +++++++++++++++++
>> 1 file changed, 17 insertions(+)
>>
>> diff --git a/drivers/interconnect/qcom/sm8550.c b/drivers/interconnect/qcom/sm8550.c
>> index d823ba988ef6..0864ed285375 100644
>> --- a/drivers/interconnect/qcom/sm8550.c
>> +++ b/drivers/interconnect/qcom/sm8550.c
>> @@ -1473,6 +1473,7 @@ static struct qcom_icc_node qns_mem_noc_sf_cam_ife_2 = {
>>
>> static struct qcom_icc_bcm bcm_acv = {
>> .name = "ACV",
>> + .enable_mask = 0x8,
>> .num_nodes = 1,
>> .nodes = { &ebi },
>> };
>> @@ -1485,6 +1486,7 @@ static struct qcom_icc_bcm bcm_ce0 = {
>>
>> static struct qcom_icc_bcm bcm_cn0 = {
>> .name = "CN0",
>> + .enable_mask = 0x1,
>> .keepalive = true,
>> .num_nodes = 54,
>> .nodes = { &qsm_cfg, &qhs_ahb2phy0,
>> @@ -1524,6 +1526,7 @@ static struct qcom_icc_bcm bcm_cn1 = {
>>
>> static struct qcom_icc_bcm bcm_co0 = {
>> .name = "CO0",
>> + .enable_mask = 0x1,
>> .num_nodes = 2,
>> .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
>> };
>> @@ -1549,6 +1552,7 @@ static struct qcom_icc_bcm bcm_mm0 = {
>>
>> static struct qcom_icc_bcm bcm_mm1 = {
>> .name = "MM1",
>> + .enable_mask = 0x1,
>> .num_nodes = 8,
>> .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
>> &qnm_camnoc_sf, &qnm_vapss_hcp,
>> @@ -1589,6 +1593,7 @@ static struct qcom_icc_bcm bcm_sh0 = {
>>
>> static struct qcom_icc_bcm bcm_sh1 = {
>> .name = "SH1",
>> + .enable_mask = 0x1,
>> .num_nodes = 13,
>> .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
>> &chm_apps, &qnm_gpu,
>> @@ -1608,6 +1613,7 @@ static struct qcom_icc_bcm bcm_sn0 = {
>>
>> static struct qcom_icc_bcm bcm_sn1 = {
>> .name = "SN1",
>> + .enable_mask = 0x1,
>> .num_nodes = 3,
>> .nodes = { &qhm_gic, &xm_gic,
>> &qns_gemnoc_gc },
>> @@ -1633,6 +1639,7 @@ static struct qcom_icc_bcm bcm_sn7 = {
>>
>> static struct qcom_icc_bcm bcm_acv_disp = {
>> .name = "ACV",
>> + .enable_mask = 0x1,
>> .num_nodes = 1,
>> .nodes = { &ebi_disp },
>> };
>> @@ -1657,12 +1664,14 @@ static struct qcom_icc_bcm bcm_sh0_disp = {
>>
>> static struct qcom_icc_bcm bcm_sh1_disp = {
>> .name = "SH1",
>> + .enable_mask = 0x1,
>> .num_nodes = 2,
>> .nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp },
>> };
>>
>> static struct qcom_icc_bcm bcm_acv_cam_ife_0 = {
>> .name = "ACV",
>> + .enable_mask = 0x0,
>> .num_nodes = 1,
>> .nodes = { &ebi_cam_ife_0 },
>> };
>> @@ -1681,6 +1690,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_0 = {
>>
>> static struct qcom_icc_bcm bcm_mm1_cam_ife_0 = {
>> .name = "MM1",
>> + .enable_mask = 0x1,
>> .num_nodes = 4,
>> .nodes = { &qnm_camnoc_hf_cam_ife_0, &qnm_camnoc_icp_cam_ife_0,
>> &qnm_camnoc_sf_cam_ife_0, &qns_mem_noc_sf_cam_ife_0 },
>> @@ -1694,6 +1704,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_0 = {
>>
>> static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
>> .name = "SH1",
>> + .enable_mask = 0x1,
>> .num_nodes = 3,
>> .nodes = { &qnm_mnoc_hf_cam_ife_0, &qnm_mnoc_sf_cam_ife_0,
>> &qnm_pcie_cam_ife_0 },
>> @@ -1701,6 +1712,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_0 = {
>>
>> static struct qcom_icc_bcm bcm_acv_cam_ife_1 = {
>> .name = "ACV",
>> + .enable_mask = 0x0,
>> .num_nodes = 1,
>> .nodes = { &ebi_cam_ife_1 },
>> };
>> @@ -1719,6 +1731,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_1 = {
>>
>> static struct qcom_icc_bcm bcm_mm1_cam_ife_1 = {
>> .name = "MM1",
>> + .enable_mask = 0x1,
>> .num_nodes = 4,
>> .nodes = { &qnm_camnoc_hf_cam_ife_1, &qnm_camnoc_icp_cam_ife_1,
>> &qnm_camnoc_sf_cam_ife_1, &qns_mem_noc_sf_cam_ife_1 },
>> @@ -1732,6 +1745,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_1 = {
>>
>> static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
>> .name = "SH1",
>> + .enable_mask = 0x1,
>> .num_nodes = 3,
>> .nodes = { &qnm_mnoc_hf_cam_ife_1, &qnm_mnoc_sf_cam_ife_1,
>> &qnm_pcie_cam_ife_1 },
>> @@ -1739,6 +1753,7 @@ static struct qcom_icc_bcm bcm_sh1_cam_ife_1 = {
>>
>> static struct qcom_icc_bcm bcm_acv_cam_ife_2 = {
>> .name = "ACV",
>> + .enable_mask = 0x0,
>> .num_nodes = 1,
>> .nodes = { &ebi_cam_ife_2 },
>> };
>> @@ -1757,6 +1772,7 @@ static struct qcom_icc_bcm bcm_mm0_cam_ife_2 = {
>>
>> static struct qcom_icc_bcm bcm_mm1_cam_ife_2 = {
>> .name = "MM1",
>> + .enable_mask = 0x1,
>> .num_nodes = 4,
>> .nodes = { &qnm_camnoc_hf_cam_ife_2, &qnm_camnoc_icp_cam_ife_2,
>> &qnm_camnoc_sf_cam_ife_2, &qns_mem_noc_sf_cam_ife_2 },
>> @@ -1770,6 +1786,7 @@ static struct qcom_icc_bcm bcm_sh0_cam_ife_2 = {
>>
>> static struct qcom_icc_bcm bcm_sh1_cam_ife_2 = {
>> .name = "SH1",
>> + .enable_mask = 0x1,
>> .num_nodes = 3,
>> .nodes = { &qnm_mnoc_hf_cam_ife_2, &qnm_mnoc_sf_cam_ife_2,
>> &qnm_pcie_cam_ife_2 },
>>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] interconnect: qcom: rpmh: add optional mask to send as vote
2023-06-19 9:47 ` Neil Armstrong
@ 2023-06-19 12:59 ` Dmitry Baryshkov
0 siblings, 0 replies; 8+ messages in thread
From: Dmitry Baryshkov @ 2023-06-19 12:59 UTC (permalink / raw)
To: neil.armstrong
Cc: Konrad Dybcio, Andy Gross, Bjorn Andersson, Georgi Djakov,
linux-arm-msm, linux-pm, linux-kernel
On Mon, 19 Jun 2023 at 12:47, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>
> Hi,
>
> On 19/06/2023 11:45, Konrad Dybcio wrote:
> > On 19.06.2023 10:24, Neil Armstrong wrote:
> >> On the SM8550 SoC, some nodes requires a specific bit mark
> >> instead of a bandwidth when voting.
> >>
> >> Add an enable_mask variable to be used to vote when a node
> >> is enabled in an aggregate loop.
> >>
> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> >> ---
> > Would be nice to mention that it's literally this commit:
> >
> > https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/commit/2d1573e0206998151b342e6b52a4c0f7234d7e36
>
> Good catch, I just copied the bits but yeah in fine it's the same...
And probably it also requires copying SoB (and Author?) from the
original commit.
>
> I'll refer to it in a v2.
>
> >
> > For the code:
> >
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>
> Thanks,
> Neil
>
> >
> > Konrad
> >> drivers/interconnect/qcom/bcm-voter.c | 5 +++++
> >> drivers/interconnect/qcom/icc-rpmh.h | 2 ++
> >> 2 files changed, 7 insertions(+)
> >>
> >> diff --git a/drivers/interconnect/qcom/bcm-voter.c b/drivers/interconnect/qcom/bcm-voter.c
> >> index 8f385f9c2dd3..d5f2a6b5376b 100644
> >> --- a/drivers/interconnect/qcom/bcm-voter.c
> >> +++ b/drivers/interconnect/qcom/bcm-voter.c
> >> @@ -83,6 +83,11 @@ static void bcm_aggregate(struct qcom_icc_bcm *bcm)
> >>
> >> temp = agg_peak[bucket] * bcm->vote_scale;
> >> bcm->vote_y[bucket] = bcm_div(temp, bcm->aux_data.unit);
> >> +
> >> + if (bcm->enable_mask && (bcm->vote_x[bucket] || bcm->vote_y[bucket])) {
> >> + bcm->vote_x[bucket] = 0;
> >> + bcm->vote_y[bucket] = bcm->enable_mask;
> >> + }
> >> }
> >>
> >> if (bcm->keepalive && bcm->vote_x[QCOM_ICC_BUCKET_AMC] == 0 &&
> >> diff --git a/drivers/interconnect/qcom/icc-rpmh.h b/drivers/interconnect/qcom/icc-rpmh.h
> >> index 04391c1ba465..7843d8864d6b 100644
> >> --- a/drivers/interconnect/qcom/icc-rpmh.h
> >> +++ b/drivers/interconnect/qcom/icc-rpmh.h
> >> @@ -81,6 +81,7 @@ struct qcom_icc_node {
> >> * @vote_x: aggregated threshold values, represents sum_bw when @type is bw bcm
> >> * @vote_y: aggregated threshold values, represents peak_bw when @type is bw bcm
> >> * @vote_scale: scaling factor for vote_x and vote_y
> >> + * @enable_mask: optional mask to send as vote instead of vote_x/vote_y
> >> * @dirty: flag used to indicate whether the bcm needs to be committed
> >> * @keepalive: flag used to indicate whether a keepalive is required
> >> * @aux_data: auxiliary data used when calculating threshold values and
> >> @@ -97,6 +98,7 @@ struct qcom_icc_bcm {
> >> u64 vote_x[QCOM_ICC_NUM_BUCKETS];
> >> u64 vote_y[QCOM_ICC_NUM_BUCKETS];
> >> u64 vote_scale;
> >> + u32 enable_mask;
> >> bool dirty;
> >> bool keepalive;
> >> struct bcm_db aux_data;
> >>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-06-19 13:00 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-06-19 8:24 [PATCH 0/2] interconnect: qcom: rpmh: sm8550: mask to send as vote Neil Armstrong
2023-06-19 8:24 ` [PATCH 1/2] interconnect: qcom: rpmh: add optional " Neil Armstrong
2023-06-19 9:45 ` Konrad Dybcio
2023-06-19 9:47 ` Neil Armstrong
2023-06-19 12:59 ` Dmitry Baryshkov
2023-06-19 8:24 ` [PATCH 2/2] interconnect: qcom: sm8550: add enable_mask for bcm nodes Neil Armstrong
2023-06-19 9:55 ` Konrad Dybcio
2023-06-19 10:09 ` Neil Armstrong
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