* [PATCH v3 1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 2:53 ` Lyude Paul
0 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 2:53 UTC (permalink / raw)
To: intel-gfx
Cc: Imre Deak, Rodrigo Vivi, Tejas Upadhyay, Matt Roper, Jani Nikula,
Joonas Lahtinen, David Airlie, Daniel Vetter,
open list:DRM DRIVERS, open list
From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.
v2:
* Move Wa_14010685332 into it's own function - vsyrjala
* Add TODO comment about figuring out if we can move this workaround - imre
v3:
* Rename cnp_irq_post_reset() to cnp_display_clock_wa()
* Add TODO item mentioning we need to clarify which platforms this
workaround applies to
* Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
functionally equivalent on gen9 bc to the code v2 added
* Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
more or less identical to spt_hpd_irq_setup() minus additionally enabling
one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
separate patch.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 52 +++++++++++++++++++++------------
1 file changed, 33 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98145a7f28a4..f86b147f588f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
+static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ /*
+ * Wa_14010685332:icl+
+ * TODO: Clarify which platforms this applies to
+ * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
+ * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
+ */
+ if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
+ SBCLK_RUN_REFCLK_DIS);
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
+ }
+}
+
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3061,8 +3079,9 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
GEN3_IRQ_RESET(uncore, GEN8_PCU_);
- if (HAS_PCH_SPLIT(dev_priv))
- ibx_irq_reset(dev_priv);
+ ibx_irq_reset(dev_priv);
+
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3104,15 +3123,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
- /* Wa_14010685332:cnp/cmp,tgp,adp */
- if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
- INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, 0);
- }
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
@@ -3764,9 +3775,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
}
}
+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 mask = SDE_GMBUS_ICP;
+
+ GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+}
+
static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_postinstall(dev_priv);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);
gen8_gt_irq_postinstall(&dev_priv->gt);
@@ -3775,13 +3796,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
gen8_master_intr_enable(dev_priv->uncore.regs);
}
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- u32 mask = SDE_GMBUS_ICP;
-
- GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
-}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
--
2.29.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 2:53 ` Lyude Paul
0 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 2:53 UTC (permalink / raw)
To: intel-gfx
Cc: David Airlie, open list, open list:DRM DRIVERS, Rodrigo Vivi,
Tejas Upadhyay
From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.
v2:
* Move Wa_14010685332 into it's own function - vsyrjala
* Add TODO comment about figuring out if we can move this workaround - imre
v3:
* Rename cnp_irq_post_reset() to cnp_display_clock_wa()
* Add TODO item mentioning we need to clarify which platforms this
workaround applies to
* Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
functionally equivalent on gen9 bc to the code v2 added
* Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
more or less identical to spt_hpd_irq_setup() minus additionally enabling
one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
separate patch.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 52 +++++++++++++++++++++------------
1 file changed, 33 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98145a7f28a4..f86b147f588f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
+static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ /*
+ * Wa_14010685332:icl+
+ * TODO: Clarify which platforms this applies to
+ * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
+ * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
+ */
+ if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
+ SBCLK_RUN_REFCLK_DIS);
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
+ }
+}
+
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3061,8 +3079,9 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
GEN3_IRQ_RESET(uncore, GEN8_PCU_);
- if (HAS_PCH_SPLIT(dev_priv))
- ibx_irq_reset(dev_priv);
+ ibx_irq_reset(dev_priv);
+
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3104,15 +3123,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
- /* Wa_14010685332:cnp/cmp,tgp,adp */
- if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
- INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, 0);
- }
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
@@ -3764,9 +3775,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
}
}
+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 mask = SDE_GMBUS_ICP;
+
+ GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+}
+
static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_postinstall(dev_priv);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);
gen8_gt_irq_postinstall(&dev_priv->gt);
@@ -3775,13 +3796,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
gen8_master_intr_enable(dev_priv->uncore.regs);
}
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- u32 mask = SDE_GMBUS_ICP;
-
- GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
-}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
--
2.29.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH v3 1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 2:53 ` Lyude Paul
0 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 2:53 UTC (permalink / raw)
To: intel-gfx; +Cc: David Airlie, open list, open list:DRM DRIVERS
From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.
v2:
* Move Wa_14010685332 into it's own function - vsyrjala
* Add TODO comment about figuring out if we can move this workaround - imre
v3:
* Rename cnp_irq_post_reset() to cnp_display_clock_wa()
* Add TODO item mentioning we need to clarify which platforms this
workaround applies to
* Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
functionally equivalent on gen9 bc to the code v2 added
* Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
more or less identical to spt_hpd_irq_setup() minus additionally enabling
one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
separate patch.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 52 +++++++++++++++++++++------------
1 file changed, 33 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98145a7f28a4..f86b147f588f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
+static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ /*
+ * Wa_14010685332:icl+
+ * TODO: Clarify which platforms this applies to
+ * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
+ * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
+ */
+ if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
+ SBCLK_RUN_REFCLK_DIS);
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
+ }
+}
+
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3061,8 +3079,9 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
GEN3_IRQ_RESET(uncore, GEN8_PCU_);
- if (HAS_PCH_SPLIT(dev_priv))
- ibx_irq_reset(dev_priv);
+ ibx_irq_reset(dev_priv);
+
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3104,15 +3123,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
- /* Wa_14010685332:cnp/cmp,tgp,adp */
- if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
- INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, 0);
- }
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
@@ -3764,9 +3775,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
}
}
+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 mask = SDE_GMBUS_ICP;
+
+ GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+}
+
static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_postinstall(dev_priv);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);
gen8_gt_irq_postinstall(&dev_priv->gt);
@@ -3775,13 +3796,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
gen8_master_intr_enable(dev_priv->uncore.regs);
}
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- u32 mask = SDE_GMBUS_ICP;
-
- GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
-}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 2/2] drm/i915/icp+: Use icp_hpd_irq_setup() instead of spt_hpd_irq_setup()
2021-02-17 2:53 ` Lyude Paul
(?)
@ 2021-02-17 2:53 ` Lyude Paul
-1 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 2:53 UTC (permalink / raw)
To: intel-gfx
Cc: Imre Deak, Rodrigo Vivi, Tejas Upadhyay, Jani Nikula,
Joonas Lahtinen, David Airlie, Daniel Vetter,
open list:DRM DRIVERS, open list
While reviewing patches for handling workarounds related to gen9 bc, Imre
from Intel discovered that we're using spt_hpd_irq_setup() on ICP+ PCHs
despite it being almost the same as icp_hpd_irq_setup(). Since we need to
be calling icp_hpd_irq_setup() to ensure that CML-S/TGP platforms function
correctly anyway, let's move platforms using PCH_ICP which aren't handled
by gen11_hpd_irq_setup() over to icp_hpd_irq_setup().
Cc: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f86b147f588f..7ec61187a315 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4320,6 +4320,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
else if (IS_GEN9_LP(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
else
--
2.29.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v3 2/2] drm/i915/icp+: Use icp_hpd_irq_setup() instead of spt_hpd_irq_setup()
@ 2021-02-17 2:53 ` Lyude Paul
0 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 2:53 UTC (permalink / raw)
To: intel-gfx
Cc: David Airlie, open list, open list:DRM DRIVERS, Rodrigo Vivi,
Tejas Upadhyay
While reviewing patches for handling workarounds related to gen9 bc, Imre
from Intel discovered that we're using spt_hpd_irq_setup() on ICP+ PCHs
despite it being almost the same as icp_hpd_irq_setup(). Since we need to
be calling icp_hpd_irq_setup() to ensure that CML-S/TGP platforms function
correctly anyway, let's move platforms using PCH_ICP which aren't handled
by gen11_hpd_irq_setup() over to icp_hpd_irq_setup().
Cc: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f86b147f588f..7ec61187a315 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4320,6 +4320,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
else if (IS_GEN9_LP(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
else
--
2.29.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH v3 2/2] drm/i915/icp+: Use icp_hpd_irq_setup() instead of spt_hpd_irq_setup()
@ 2021-02-17 2:53 ` Lyude Paul
0 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 2:53 UTC (permalink / raw)
To: intel-gfx; +Cc: David Airlie, open list, open list:DRM DRIVERS
While reviewing patches for handling workarounds related to gen9 bc, Imre
from Intel discovered that we're using spt_hpd_irq_setup() on ICP+ PCHs
despite it being almost the same as icp_hpd_irq_setup(). Since we need to
be calling icp_hpd_irq_setup() to ensure that CML-S/TGP platforms function
correctly anyway, let's move platforms using PCH_ICP which aren't handled
by gen11_hpd_irq_setup() over to icp_hpd_irq_setup().
Cc: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f86b147f588f..7ec61187a315 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4320,6 +4320,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
else if (IS_GEN9_LP(dev_priv))
dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
else
--
2.29.2
_______________________________________________
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* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
2021-02-17 2:53 ` Lyude Paul
` (2 preceding siblings ...)
(?)
@ 2021-02-17 3:45 ` Patchwork
-1 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-02-17 3:45 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 4643 bytes --]
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
URL : https://patchwork.freedesktop.org/series/87148/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9779 -> Patchwork_19689
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_19689:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@uncore:
- {fi-ehl-1}: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/fi-ehl-1/igt@i915_selftest@live@uncore.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/fi-ehl-1/igt@i915_selftest@live@uncore.html
Known issues
------------
Here are the changes found in Patchwork_19689 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-tgl-y: NOTRUN -> [SKIP][3] ([fdo#109315] / [i915#2575])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/fi-tgl-y/igt@amdgpu/amd_basic@query-info.html
* igt@i915_getparams_basic@basic-subslice-total:
- fi-tgl-y: [PASS][4] -> [DMESG-WARN][5] ([i915#402]) +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/fi-tgl-y/igt@i915_getparams_basic@basic-subslice-total.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/fi-tgl-y/igt@i915_getparams_basic@basic-subslice-total.html
* igt@runner@aborted:
- fi-glk-dsi: NOTRUN -> [FAIL][6] ([i915#2295] / [k.org#202321])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/fi-glk-dsi/igt@runner@aborted.html
- fi-bxt-dsi: NOTRUN -> [FAIL][7] ([i915#2295])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/fi-bxt-dsi/igt@runner@aborted.html
#### Possible fixes ####
* igt@prime_vgem@basic-fence-flip:
- fi-tgl-y: [DMESG-WARN][8] ([i915#402]) -> [PASS][9] +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
#### Warnings ####
* igt@runner@aborted:
- fi-apl-guc: [FAIL][10] ([i915#2426]) -> [FAIL][11] ([i915#1610] / [i915#2295])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/fi-apl-guc/igt@runner@aborted.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/fi-apl-guc/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#2089]: https://gitlab.freedesktop.org/drm/intel/issues/2089
[i915#2295]: https://gitlab.freedesktop.org/drm/intel/issues/2295
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2505]: https://gitlab.freedesktop.org/drm/intel/issues/2505
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2724]: https://gitlab.freedesktop.org/drm/intel/issues/2724
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (45 -> 37)
------------------------------
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-ehl-2 fi-bdw-samus fi-hsw-gt1
Build changes
-------------
* Linux: CI_DRM_9779 -> Patchwork_19689
CI-20190529: 20190529
CI_DRM_9779: 775dbe8d5e041442fcadf63894468a63582a87a2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6004: fe9ac2aeffc1828c6d61763a611a44fbd450aa96 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19689: 54805526a9f1e6f32f6a779997a377b2d97ff32b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
54805526a9f1 drm/i915/icp+: Use icp_hpd_irq_setup() instead of spt_hpd_irq_setup()
38bc44895ab6 drm/i915/gen9bc: Handle TGP PCH during suspend/resume
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/index.html
[-- Attachment #1.2: Type: text/html, Size: 5333 bytes --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v3,1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
2021-02-17 2:53 ` Lyude Paul
` (3 preceding siblings ...)
(?)
@ 2021-02-17 4:57 ` Patchwork
-1 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-02-17 4:57 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30306 bytes --]
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
URL : https://patchwork.freedesktop.org/series/87148/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9779_full -> Patchwork_19689_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_19689_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@psr2:
- shard-iclb: [PASS][1] -> [SKIP][2] ([i915#658])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb2/igt@feature_discovery@psr2.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb3/igt@feature_discovery@psr2.html
* igt@gem_ctx_persistence@engines-hostile:
- shard-hsw: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-hsw8/igt@gem_ctx_persistence@engines-hostile.html
* igt@gem_ctx_persistence@engines-persistence:
- shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-snb6/igt@gem_ctx_persistence@engines-persistence.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#2369])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl3/igt@gem_exec_capture@pi@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl6/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: NOTRUN -> [FAIL][7] ([i915#2846])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][8] ([i915#2842]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-tglb2/igt@gem_exec_fair@basic-pace@vcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-tglb7/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_huc_copy@huc-copy:
- shard-kbl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#2190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl1/igt@gem_huc_copy@huc-copy.html
* igt@gem_pwrite@basic-exhaustion:
- shard-iclb: NOTRUN -> [WARN][14] ([i915#2658])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb3/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [PASS][15] -> [DMESG-WARN][16] ([i915#180])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-kbl4/igt@gem_softpin@noreloc-s3.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl4/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][17] ([i915#3002])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl2/igt@gem_userptr_blits@input-checking.html
* igt@gen7_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][18] ([fdo#109289])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-tglb1/igt@gen7_exec_parse@cmd-crossing-page.html
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109289])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb6/igt@gen7_exec_parse@cmd-crossing-page.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][20] -> [DMESG-WARN][21] ([i915#1436] / [i915#716])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl8/igt@gen9_exec_parse@allowed-single.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl5/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: NOTRUN -> [FAIL][22] ([i915#454])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl1/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [PASS][23] -> [FAIL][24] ([i915#2597])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-tglb2/igt@kms_async_flips@test-time-stamp.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-tglb5/igt@kms_async_flips@test-time-stamp.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][25] ([fdo#111614])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-tglb1/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
- shard-iclb: NOTRUN -> [SKIP][26] ([fdo#110725] / [fdo#111614])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb6/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
* igt@kms_big_joiner@basic:
- shard-kbl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#2705])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl6/igt@kms_big_joiner@basic.html
* igt@kms_chamelium@dp-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +8 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl4/igt@kms_chamelium@dp-hpd-storm-disable.html
* igt@kms_chamelium@vga-edid-read:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109284] / [fdo#111827]) +2 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb6/igt@kms_chamelium@vga-edid-read.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-snb: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +6 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-snb6/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +19 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl7/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109284] / [fdo#111827]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-tglb1/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-gamma:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb6/igt@kms_color_chamelium@pipe-d-gamma.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][34] ([i915#1319]) +3 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl7/igt@kms_content_protection@atomic.html
* igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding:
- shard-kbl: NOTRUN -> [SKIP][35] ([fdo#109271]) +194 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen:
- shard-skl: [PASS][36] -> [FAIL][37] ([i915#54]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-256x85-random:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109278]) +2 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb6/igt@kms_cursor_crc@pipe-d-cursor-256x85-random.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge:
- shard-skl: [PASS][39] -> [DMESG-WARN][40] ([i915#1982])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl6/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl7/igt@kms_cursor_edge_walk@pipe-a-256x256-right-edge.html
* igt@kms_cursor_edge_walk@pipe-d-64x64-top-edge:
- shard-hsw: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#533]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-hsw8/igt@kms_cursor_edge_walk@pipe-d-64x64-top-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-skl: [PASS][42] -> [FAIL][43] ([i915#2346])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#533]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl6/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-iclb: NOTRUN -> [SKIP][45] ([fdo#109274])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb3/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-kbl: NOTRUN -> [FAIL][46] ([i915#2641])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#2642])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109280]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
- shard-tglb: NOTRUN -> [SKIP][49] ([fdo#111825]) +2 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff:
- shard-skl: NOTRUN -> [SKIP][50] ([fdo#109271]) +51 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff:
- shard-snb: NOTRUN -> [SKIP][51] ([fdo#109271]) +112 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-snb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-onoff.html
* igt@kms_hdr@static-swap:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#1187])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-tglb1/igt@kms_hdr@static-swap.html
- shard-iclb: NOTRUN -> [SKIP][53] ([i915#1187])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb6/igt@kms_hdr@static-swap.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-skl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][55] ([fdo#108145] / [i915#265]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_lowres@pipe-b-tiling-yf:
- shard-hsw: NOTRUN -> [SKIP][56] ([fdo#109271]) +13 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-hsw8/igt@kms_plane_lowres@pipe-b-tiling-yf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658]) +4 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-1:
- shard-skl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#658])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl4/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html
* igt@kms_psr@primary_page_flip:
- shard-hsw: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#1072])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-hsw8/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][60] -> [SKIP][61] ([fdo#109441]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb4/igt@kms_psr@psr2_no_drrs.html
* igt@kms_writeback@writeback-fb-id:
- shard-kbl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#2437])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl1/igt@kms_writeback@writeback-fb-id.html
* igt@nouveau_crc@ctx-flip-threshold-reset-after-capture:
- shard-iclb: NOTRUN -> [SKIP][63] ([i915#2530])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb3/igt@nouveau_crc@ctx-flip-threshold-reset-after-capture.html
* igt@sysfs_clients@recycle:
- shard-iclb: [PASS][64] -> [FAIL][65] ([i915#3028])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb5/igt@sysfs_clients@recycle.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb2/igt@sysfs_clients@recycle.html
- shard-kbl: NOTRUN -> [FAIL][66] ([i915#3028])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl1/igt@sysfs_clients@recycle.html
* igt@sysfs_clients@split-10@vcs0:
- shard-skl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#3026]) +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl4/igt@sysfs_clients@split-10@vcs0.html
* igt@sysfs_timeslice_duration@timeout@vecs0:
- shard-skl: [PASS][68] -> [FAIL][69] ([i915#2825])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl5/igt@sysfs_timeslice_duration@timeout@vecs0.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl1/igt@sysfs_timeslice_duration@timeout@vecs0.html
#### Possible fixes ####
* igt@gem_exec_balancer@hang:
- shard-iclb: [INCOMPLETE][70] ([i915#1895] / [i915#2295]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb2/igt@gem_exec_balancer@hang.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb3/igt@gem_exec_balancer@hang.html
* igt@gem_exec_schedule@u-fairslice@bcs0:
- shard-tglb: [DMESG-WARN][72] ([i915#2803]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-tglb8/igt@gem_exec_schedule@u-fairslice@bcs0.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-tglb1/igt@gem_exec_schedule@u-fairslice@bcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-skl: [DMESG-WARN][74] ([i915#1610] / [i915#2803]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl6/igt@gem_exec_schedule@u-fairslice@rcs0.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl7/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vcs0:
- shard-iclb: [DMESG-WARN][76] ([i915#2803]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb4/igt@gem_exec_schedule@u-fairslice@vcs0.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb6/igt@gem_exec_schedule@u-fairslice@vcs0.html
* igt@i915_selftest@live@hangcheck:
- shard-hsw: [INCOMPLETE][78] ([i915#2782]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-hsw4/igt@i915_selftest@live@hangcheck.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-hsw8/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
- shard-skl: [FAIL][80] ([i915#54]) -> [PASS][81] +11 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-tglb: [FAIL][82] ([i915#2598]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-tglb5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-tglb7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [FAIL][84] ([i915#2122]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
- shard-skl: [DMESG-WARN][86] ([i915#1982]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl7/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl8/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][88] ([i915#1188]) -> [PASS][89] +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl3/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][90] ([i915#180]) -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][92] ([fdo#109441]) -> [PASS][93] +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb8/igt@kms_psr@psr2_cursor_render.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@perf@polling-parameterized:
- shard-iclb: [FAIL][94] ([i915#1542]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb5/igt@perf@polling-parameterized.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb7/igt@perf@polling-parameterized.html
* igt@sysfs_clients@busy@vcs0:
- shard-iclb: [FAIL][96] ([i915#3019]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb8/igt@sysfs_clients@busy@vcs0.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb2/igt@sysfs_clients@busy@vcs0.html
* igt@sysfs_clients@recycle:
- shard-hsw: [FAIL][98] ([i915#3028]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-hsw1/igt@sysfs_clients@recycle.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-hsw8/igt@sysfs_clients@recycle.html
- shard-tglb: [FAIL][100] ([i915#3028]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-tglb1/igt@sysfs_clients@recycle.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-tglb3/igt@sysfs_clients@recycle.html
* {igt@sysfs_clients@recycle-many}:
- shard-iclb: [FAIL][102] ([i915#3028]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb5/igt@sysfs_clients@recycle-many.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb5/igt@sysfs_clients@recycle-many.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][104] ([i915#588]) -> [SKIP][105] ([i915#658])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb3/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][106] ([i915#2684]) -> [WARN][107] ([i915#1804] / [i915#2684])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][108] ([fdo#109349]) -> [DMESG-WARN][109] ([i915#1226])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb8/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-1:
- shard-iclb: [SKIP][110] ([i915#658]) -> [SKIP][111] ([i915#2920])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb8/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb2/igt@kms_psr2_sf@plane-move-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-iclb: [SKIP][112] ([i915#2920]) -> [SKIP][113] ([i915#658]) +3 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@nouveau_crc@pipe-a-ctx-flip-detection:
- shard-skl: [INCOMPLETE][114] -> [SKIP][115] ([fdo#109271])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-skl10/igt@nouveau_crc@pipe-a-ctx-flip-detection.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-skl5/igt@nouveau_crc@pipe-a-ctx-flip-detection.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123]) ([i915#1436] / [i915#1814] / [i915#2295] / [i915#602]) -> ([FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128]) ([i915#1814] / [i915#2295] / [i915#3002])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-kbl2/igt@runner@aborted.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-kbl4/igt@runner@aborted.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-kbl2/igt@runner@aborted.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-kbl4/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-kbl4/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-kbl7/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-kbl2/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-kbl4/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl2/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl2/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl4/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl2/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-kbl4/igt@runner@aborted.html
- shard-iclb: ([FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132]) ([i915#2295] / [i915#2426] / [i915#2724] / [i915#3002]) -> ([FAIL][133], [FAIL][134], [FAIL][135]) ([i915#2295] / [i915#2724] / [i915#3002])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb4/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb7/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb1/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-iclb4/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb3/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb8/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-iclb6/igt@runner@aborted.html
- shard-apl: ([FAIL][136], [FAIL][137], [FAIL][138]) ([i915#1610] / [i915#2295] / [i915#2426] / [i915#3002]) -> ([FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159]) ([i915#1610] / [i915#2295])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-apl7/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-apl7/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-apl7/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl2/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl6/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl6/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl7/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl6/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl6/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl7/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl1/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl3/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl3/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl1/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl8/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl3/igt@runner@aborted.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl7/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl8/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl2/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl7/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl2/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl2/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-apl8/igt@runner@aborted.html
- shard-glk: ([FAIL][160], [FAIL][161], [FAIL][162]) ([i915#2295] / [i915#3002] / [k.org#202321]) -> ([FAIL][163], [FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169], [FAIL][170], [FAIL][171], [FAIL][172], [FAIL][173], [FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177], [FAIL][178], [FAIL][179], [FAIL][180], [FAIL][181], [FAIL][182], [FAIL][183], [FAIL][184], [FAIL][185], [FAIL][186], [FAIL][187]) ([i915#2295] / [k.org#202321])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-glk4/igt@runner@aborted.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-glk5/igt@runner@aborted.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9779/shard-glk9/igt@runner@aborted.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-glk6/igt@runner@aborted.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/shard-glk3/igt@runner@aborted.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchw
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19689/index.html
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v3 1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
2021-02-17 2:53 ` Lyude Paul
(?)
@ 2021-02-17 8:02 ` Imre Deak
-1 siblings, 0 replies; 28+ messages in thread
From: Imre Deak @ 2021-02-17 8:02 UTC (permalink / raw)
To: Lyude Paul
Cc: intel-gfx, Rodrigo Vivi, Tejas Upadhyay, Matt Roper, Jani Nikula,
Joonas Lahtinen, David Airlie, Daniel Vetter,
open list:DRM DRIVERS, open list
On Tue, Feb 16, 2021 at 09:53:36PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaround - imre
> v3:
> * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> * Add TODO item mentioning we need to clarify which platforms this
> workaround applies to
> * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> functionally equivalent on gen9 bc to the code v2 added
> * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
> more or less identical to spt_hpd_irq_setup() minus additionally enabling
> one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> separate patch.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 52 +++++++++++++++++++++------------
> 1 file changed, 33 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 98145a7f28a4..f86b147f588f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> +
> + /*
> + * Wa_14010685332:icl+
For now let's keep this matching the code:
Wa_14010685332:cnp/cmp,tgp,adp
> + * TODO: Clarify which platforms this applies to
> + * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
> + * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
> + */
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> + SBCLK_RUN_REFCLK_DIS);
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> + }
> +}
> +
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3061,8 +3079,9 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> GEN3_IRQ_RESET(uncore, GEN8_PCU_);
>
> - if (HAS_PCH_SPLIT(dev_priv))
> - ibx_irq_reset(dev_priv);
> + ibx_irq_reset(dev_priv);
The above shouldn't be changed to account for !PCH platforms as well.
> +
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3104,15 +3123,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:cnp/cmp,tgp,adp */
> - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, 0);
> - }
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3764,9 +3775,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> + u32 mask = SDE_GMBUS_ICP;
> +
> + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> +}
> +
> static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_irq_postinstall(dev_priv);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_postinstall(dev_priv);
>
> gen8_gt_irq_postinstall(&dev_priv->gt);
> @@ -3775,13 +3796,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> gen8_master_intr_enable(dev_priv->uncore.regs);
> }
>
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u32 mask = SDE_GMBUS_ICP;
> -
> - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> -}
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> --
> 2.29.2
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v3 1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 8:02 ` Imre Deak
0 siblings, 0 replies; 28+ messages in thread
From: Imre Deak @ 2021-02-17 8:02 UTC (permalink / raw)
To: Lyude Paul
Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS,
Rodrigo Vivi, Tejas Upadhyay
On Tue, Feb 16, 2021 at 09:53:36PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaround - imre
> v3:
> * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> * Add TODO item mentioning we need to clarify which platforms this
> workaround applies to
> * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> functionally equivalent on gen9 bc to the code v2 added
> * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
> more or less identical to spt_hpd_irq_setup() minus additionally enabling
> one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> separate patch.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 52 +++++++++++++++++++++------------
> 1 file changed, 33 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 98145a7f28a4..f86b147f588f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> +
> + /*
> + * Wa_14010685332:icl+
For now let's keep this matching the code:
Wa_14010685332:cnp/cmp,tgp,adp
> + * TODO: Clarify which platforms this applies to
> + * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
> + * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
> + */
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> + SBCLK_RUN_REFCLK_DIS);
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> + }
> +}
> +
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3061,8 +3079,9 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> GEN3_IRQ_RESET(uncore, GEN8_PCU_);
>
> - if (HAS_PCH_SPLIT(dev_priv))
> - ibx_irq_reset(dev_priv);
> + ibx_irq_reset(dev_priv);
The above shouldn't be changed to account for !PCH platforms as well.
> +
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3104,15 +3123,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:cnp/cmp,tgp,adp */
> - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, 0);
> - }
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3764,9 +3775,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> + u32 mask = SDE_GMBUS_ICP;
> +
> + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> +}
> +
> static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_irq_postinstall(dev_priv);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_postinstall(dev_priv);
>
> gen8_gt_irq_postinstall(&dev_priv->gt);
> @@ -3775,13 +3796,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> gen8_master_intr_enable(dev_priv->uncore.regs);
> }
>
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u32 mask = SDE_GMBUS_ICP;
> -
> - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> -}
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> --
> 2.29.2
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 8:02 ` Imre Deak
0 siblings, 0 replies; 28+ messages in thread
From: Imre Deak @ 2021-02-17 8:02 UTC (permalink / raw)
To: Lyude Paul; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
On Tue, Feb 16, 2021 at 09:53:36PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaround - imre
> v3:
> * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> * Add TODO item mentioning we need to clarify which platforms this
> workaround applies to
> * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> functionally equivalent on gen9 bc to the code v2 added
> * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
> more or less identical to spt_hpd_irq_setup() minus additionally enabling
> one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> separate patch.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 52 +++++++++++++++++++++------------
> 1 file changed, 33 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 98145a7f28a4..f86b147f588f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> +
> + /*
> + * Wa_14010685332:icl+
For now let's keep this matching the code:
Wa_14010685332:cnp/cmp,tgp,adp
> + * TODO: Clarify which platforms this applies to
> + * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
> + * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
> + */
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> + SBCLK_RUN_REFCLK_DIS);
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> + }
> +}
> +
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3061,8 +3079,9 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
> GEN3_IRQ_RESET(uncore, GEN8_PCU_);
>
> - if (HAS_PCH_SPLIT(dev_priv))
> - ibx_irq_reset(dev_priv);
> + ibx_irq_reset(dev_priv);
The above shouldn't be changed to account for !PCH platforms as well.
> +
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3104,15 +3123,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:cnp/cmp,tgp,adp */
> - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, 0);
> - }
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3764,9 +3775,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> + u32 mask = SDE_GMBUS_ICP;
> +
> + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> +}
> +
> static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_irq_postinstall(dev_priv);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_postinstall(dev_priv);
>
> gen8_gt_irq_postinstall(&dev_priv->gt);
> @@ -3775,13 +3796,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> gen8_master_intr_enable(dev_priv->uncore.regs);
> }
>
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u32 mask = SDE_GMBUS_ICP;
> -
> - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> -}
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> --
> 2.29.2
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
2021-02-17 2:53 ` Lyude Paul
(?)
@ 2021-02-17 18:00 ` Lyude Paul
-1 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 18:00 UTC (permalink / raw)
To: intel-gfx, Imre Deak
Cc: Tejas Upadhyay, Matt Roper, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, David Airlie, Daniel Vetter, open list:DRM DRIVERS,
open list
From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.
v2:
* Move Wa_14010685332 into it's own function - vsyrjala
* Add TODO comment about figuring out if we can move this workaround - imre
v3:
* Rename cnp_irq_post_reset() to cnp_display_clock_wa()
* Add TODO item mentioning we need to clarify which platforms this
workaround applies to
* Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
functionally equivalent on gen9 bc to the code v2 added
* Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
more or less identical to spt_hpd_irq_setup() minus additionally enabling
one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
separate patch.
v4:
* Revert Wa_14010685332 system list in comments to how it was before
* Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
1 file changed, 32 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98145a7f28a4..9b56a8f81e1a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
+static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ /*
+ * Wa_14010685332:cnp/cmp,tgp,adp
+ * TODO: Clarify which platforms this applies to
+ * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
+ * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
+ */
+ if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
+ SBCLK_RUN_REFCLK_DIS);
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
+ }
+}
+
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3063,6 +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
+
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3104,15 +3124,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
- /* Wa_14010685332:cnp/cmp,tgp,adp */
- if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
- INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, 0);
- }
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
@@ -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
}
}
+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 mask = SDE_GMBUS_ICP;
+
+ GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+}
+
static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_postinstall(dev_priv);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);
gen8_gt_irq_postinstall(&dev_priv->gt);
@@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
gen8_master_intr_enable(dev_priv->uncore.regs);
}
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- u32 mask = SDE_GMBUS_ICP;
-
- GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
-}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
--
2.29.2
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 18:00 ` Lyude Paul
0 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 18:00 UTC (permalink / raw)
To: intel-gfx, Imre Deak
Cc: David Airlie, open list, open list:DRM DRIVERS, Rodrigo Vivi,
Tejas Upadhyay
From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.
v2:
* Move Wa_14010685332 into it's own function - vsyrjala
* Add TODO comment about figuring out if we can move this workaround - imre
v3:
* Rename cnp_irq_post_reset() to cnp_display_clock_wa()
* Add TODO item mentioning we need to clarify which platforms this
workaround applies to
* Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
functionally equivalent on gen9 bc to the code v2 added
* Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
more or less identical to spt_hpd_irq_setup() minus additionally enabling
one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
separate patch.
v4:
* Revert Wa_14010685332 system list in comments to how it was before
* Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
1 file changed, 32 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98145a7f28a4..9b56a8f81e1a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
+static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ /*
+ * Wa_14010685332:cnp/cmp,tgp,adp
+ * TODO: Clarify which platforms this applies to
+ * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
+ * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
+ */
+ if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
+ SBCLK_RUN_REFCLK_DIS);
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
+ }
+}
+
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3063,6 +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
+
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3104,15 +3124,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
- /* Wa_14010685332:cnp/cmp,tgp,adp */
- if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
- INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, 0);
- }
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
@@ -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
}
}
+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 mask = SDE_GMBUS_ICP;
+
+ GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+}
+
static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_postinstall(dev_priv);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);
gen8_gt_irq_postinstall(&dev_priv->gt);
@@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
gen8_master_intr_enable(dev_priv->uncore.regs);
}
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- u32 mask = SDE_GMBUS_ICP;
-
- GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
-}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
--
2.29.2
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Intel-gfx] [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 18:00 ` Lyude Paul
0 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 18:00 UTC (permalink / raw)
To: intel-gfx, Imre Deak; +Cc: David Airlie, open list, open list:DRM DRIVERS
From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
For Legacy S3 suspend/resume GEN9 BC needs to enable and
setup TGP PCH.
v2:
* Move Wa_14010685332 into it's own function - vsyrjala
* Add TODO comment about figuring out if we can move this workaround - imre
v3:
* Rename cnp_irq_post_reset() to cnp_display_clock_wa()
* Add TODO item mentioning we need to clarify which platforms this
workaround applies to
* Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
functionally equivalent on gen9 bc to the code v2 added
* Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
more or less identical to spt_hpd_irq_setup() minus additionally enabling
one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
separate patch.
v4:
* Revert Wa_14010685332 system list in comments to how it was before
* Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
---
drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
1 file changed, 32 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 98145a7f28a4..9b56a8f81e1a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
spin_unlock_irq(&dev_priv->irq_lock);
}
+static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+
+ /*
+ * Wa_14010685332:cnp/cmp,tgp,adp
+ * TODO: Clarify which platforms this applies to
+ * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
+ * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
+ */
+ if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
+ (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
+ SBCLK_RUN_REFCLK_DIS);
+ intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
+ }
+}
+
static void gen8_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3063,6 +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_reset(dev_priv);
+
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3104,15 +3124,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
GEN3_IRQ_RESET(uncore, SDE);
- /* Wa_14010685332:cnp/cmp,tgp,adp */
- if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
- (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
- INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
- intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
- SBCLK_RUN_REFCLK_DIS, 0);
- }
+ cnp_display_clock_wa(dev_priv);
}
static void gen11_irq_reset(struct drm_i915_private *dev_priv)
@@ -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
}
}
+static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
+{
+ struct intel_uncore *uncore = &dev_priv->uncore;
+ u32 mask = SDE_GMBUS_ICP;
+
+ GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
+}
+
static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
{
- if (HAS_PCH_SPLIT(dev_priv))
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_postinstall(dev_priv);
+ else if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev_priv);
gen8_gt_irq_postinstall(&dev_priv->gt);
@@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
gen8_master_intr_enable(dev_priv->uncore.regs);
}
-static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
-{
- struct intel_uncore *uncore = &dev_priv->uncore;
- u32 mask = SDE_GMBUS_ICP;
-
- GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
-}
static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
{
--
2.29.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/icp+: Use icp_hpd_irq_setup() instead of spt_hpd_irq_setup()
2021-02-17 2:53 ` Lyude Paul
(?)
@ 2021-02-17 18:18 ` Rodrigo Vivi
-1 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Vivi @ 2021-02-17 18:18 UTC (permalink / raw)
To: Lyude Paul
Cc: intel-gfx, David Airlie, open list, open list:DRM DRIVERS,
Tejas Upadhyay
On Tue, Feb 16, 2021 at 09:53:37PM -0500, Lyude Paul wrote:
> While reviewing patches for handling workarounds related to gen9 bc, Imre
> from Intel discovered that we're using spt_hpd_irq_setup() on ICP+ PCHs
> despite it being almost the same as icp_hpd_irq_setup(). Since we need to
> be calling icp_hpd_irq_setup() to ensure that CML-S/TGP platforms function
> correctly anyway, let's move platforms using PCH_ICP which aren't handled
> by gen11_hpd_irq_setup() over to icp_hpd_irq_setup().
>
> Cc: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
makes sense to me...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f86b147f588f..7ec61187a315 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4320,6 +4320,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
> else if (IS_GEN9_LP(dev_priv))
> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> else
> --
> 2.29.2
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/icp+: Use icp_hpd_irq_setup() instead of spt_hpd_irq_setup()
@ 2021-02-17 18:18 ` Rodrigo Vivi
0 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Vivi @ 2021-02-17 18:18 UTC (permalink / raw)
To: Lyude Paul
Cc: David Airlie, intel-gfx, Tejas Upadhyay, open list,
open list:DRM DRIVERS
On Tue, Feb 16, 2021 at 09:53:37PM -0500, Lyude Paul wrote:
> While reviewing patches for handling workarounds related to gen9 bc, Imre
> from Intel discovered that we're using spt_hpd_irq_setup() on ICP+ PCHs
> despite it being almost the same as icp_hpd_irq_setup(). Since we need to
> be calling icp_hpd_irq_setup() to ensure that CML-S/TGP platforms function
> correctly anyway, let's move platforms using PCH_ICP which aren't handled
> by gen11_hpd_irq_setup() over to icp_hpd_irq_setup().
>
> Cc: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
makes sense to me...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f86b147f588f..7ec61187a315 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4320,6 +4320,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
> else if (IS_GEN9_LP(dev_priv))
> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> else
> --
> 2.29.2
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/icp+: Use icp_hpd_irq_setup() instead of spt_hpd_irq_setup()
@ 2021-02-17 18:18 ` Rodrigo Vivi
0 siblings, 0 replies; 28+ messages in thread
From: Rodrigo Vivi @ 2021-02-17 18:18 UTC (permalink / raw)
To: Lyude Paul; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
On Tue, Feb 16, 2021 at 09:53:37PM -0500, Lyude Paul wrote:
> While reviewing patches for handling workarounds related to gen9 bc, Imre
> from Intel discovered that we're using spt_hpd_irq_setup() on ICP+ PCHs
> despite it being almost the same as icp_hpd_irq_setup(). Since we need to
> be calling icp_hpd_irq_setup() to ensure that CML-S/TGP platforms function
> correctly anyway, let's move platforms using PCH_ICP which aren't handled
> by gen11_hpd_irq_setup() over to icp_hpd_irq_setup().
>
> Cc: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
makes sense to me...
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f86b147f588f..7ec61187a315 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4320,6 +4320,8 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
> else if (IS_GEN9_LP(dev_priv))
> dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
> + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
> dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
> else
> --
> 2.29.2
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev2)
2021-02-17 2:53 ` Lyude Paul
` (6 preceding siblings ...)
(?)
@ 2021-02-17 19:31 ` Patchwork
-1 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-02-17 19:31 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 3255 bytes --]
== Series Details ==
Series: series starting with [v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/87148/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9783 -> Patchwork_19697
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/index.html
Known issues
------------
Here are the changes found in Patchwork_19697 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_render_tiled_blits@basic:
- fi-tgl-y: NOTRUN -> [DMESG-WARN][1] ([i915#402]) +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/fi-tgl-y/igt@gem_render_tiled_blits@basic.html
* igt@i915_selftest@live@gt_lrc:
- fi-tgl-y: NOTRUN -> [DMESG-FAIL][2] ([i915#2373])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/fi-tgl-y/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- fi-tgl-y: NOTRUN -> [DMESG-FAIL][3] ([i915#1759])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/fi-tgl-y/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@vga-edid-read:
- fi-tgl-y: NOTRUN -> [SKIP][4] ([fdo#111827]) +8 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/fi-tgl-y/igt@kms_chamelium@vga-edid-read.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-y: NOTRUN -> [SKIP][5] ([fdo#109285])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/fi-tgl-y/igt@kms_force_connector_basic@force-load-detect.html
#### Possible fixes ####
* igt@i915_selftest@live@blt:
- fi-snb-2520m: [DMESG-FAIL][6] -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/fi-snb-2520m/igt@i915_selftest@live@blt.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/fi-snb-2520m/igt@i915_selftest@live@blt.html
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (42 -> 39)
------------------------------
Additional (1): fi-tgl-y
Missing (4): fi-ilk-m540 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_9783 -> Patchwork_19697
CI-20190529: 20190529
CI_DRM_9783: 498a1b2bfd0ecf4401c2f653a82e9ae2c80c9145 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6005: b69a3c463f0aec46b19c14ac24351d292cb11c08 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_19697: 22a54b838f719c2be7f771d0f95c496b495a585c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
22a54b838f71 drm/i915/icp+: Use icp_hpd_irq_setup() instead of spt_hpd_irq_setup()
85c3286dab00 drm/i915/gen9bc: Handle TGP PCH during suspend/resume
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/index.html
[-- Attachment #1.2: Type: text/html, Size: 4007 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
2021-02-17 18:00 ` Lyude Paul
(?)
@ 2021-02-17 21:18 ` Imre Deak
-1 siblings, 0 replies; 28+ messages in thread
From: Imre Deak @ 2021-02-17 21:18 UTC (permalink / raw)
To: Lyude Paul
Cc: intel-gfx, Tejas Upadhyay, Matt Roper, Jani Nikula,
Joonas Lahtinen, Rodrigo Vivi, David Airlie, Daniel Vetter,
open list:DRM DRIVERS, open list
On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaround - imre
> v3:
> * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> * Add TODO item mentioning we need to clarify which platforms this
> workaround applies to
> * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> functionally equivalent on gen9 bc to the code v2 added
> * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
> more or less identical to spt_hpd_irq_setup() minus additionally enabling
> one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> separate patch.
> v4:
> * Revert Wa_14010685332 system list in comments to how it was before
> * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
Thanks, looks ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>
nit: cnp_display_clock_gating_wa() would be an even better name, could
be renamed while applying.
> ---
> drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
> 1 file changed, 32 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 98145a7f28a4..9b56a8f81e1a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> +
> + /*
> + * Wa_14010685332:cnp/cmp,tgp,adp
> + * TODO: Clarify which platforms this applies to
> + * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
> + * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
> + */
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> + SBCLK_RUN_REFCLK_DIS);
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> + }
> +}
> +
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3063,6 +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
>
> if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_reset(dev_priv);
> +
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3104,15 +3124,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:cnp/cmp,tgp,adp */
> - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, 0);
> - }
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> + u32 mask = SDE_GMBUS_ICP;
> +
> + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> +}
> +
> static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_irq_postinstall(dev_priv);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_postinstall(dev_priv);
>
> gen8_gt_irq_postinstall(&dev_priv->gt);
> @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> gen8_master_intr_enable(dev_priv->uncore.regs);
> }
>
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u32 mask = SDE_GMBUS_ICP;
> -
> - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> -}
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> --
> 2.29.2
>
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 21:18 ` Imre Deak
0 siblings, 0 replies; 28+ messages in thread
From: Imre Deak @ 2021-02-17 21:18 UTC (permalink / raw)
To: Lyude Paul
Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS,
Rodrigo Vivi, Tejas Upadhyay
On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaround - imre
> v3:
> * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> * Add TODO item mentioning we need to clarify which platforms this
> workaround applies to
> * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> functionally equivalent on gen9 bc to the code v2 added
> * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
> more or less identical to spt_hpd_irq_setup() minus additionally enabling
> one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> separate patch.
> v4:
> * Revert Wa_14010685332 system list in comments to how it was before
> * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
Thanks, looks ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>
nit: cnp_display_clock_gating_wa() would be an even better name, could
be renamed while applying.
> ---
> drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
> 1 file changed, 32 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 98145a7f28a4..9b56a8f81e1a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> +
> + /*
> + * Wa_14010685332:cnp/cmp,tgp,adp
> + * TODO: Clarify which platforms this applies to
> + * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
> + * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
> + */
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> + SBCLK_RUN_REFCLK_DIS);
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> + }
> +}
> +
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3063,6 +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
>
> if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_reset(dev_priv);
> +
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3104,15 +3124,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:cnp/cmp,tgp,adp */
> - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, 0);
> - }
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> + u32 mask = SDE_GMBUS_ICP;
> +
> + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> +}
> +
> static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_irq_postinstall(dev_priv);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_postinstall(dev_priv);
>
> gen8_gt_irq_postinstall(&dev_priv->gt);
> @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> gen8_master_intr_enable(dev_priv->uncore.regs);
> }
>
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u32 mask = SDE_GMBUS_ICP;
> -
> - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> -}
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> --
> 2.29.2
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 21:18 ` Imre Deak
0 siblings, 0 replies; 28+ messages in thread
From: Imre Deak @ 2021-02-17 21:18 UTC (permalink / raw)
To: Lyude Paul; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
>
> For Legacy S3 suspend/resume GEN9 BC needs to enable and
> setup TGP PCH.
>
> v2:
> * Move Wa_14010685332 into it's own function - vsyrjala
> * Add TODO comment about figuring out if we can move this workaround - imre
> v3:
> * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> * Add TODO item mentioning we need to clarify which platforms this
> workaround applies to
> * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> functionally equivalent on gen9 bc to the code v2 added
> * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
> more or less identical to spt_hpd_irq_setup() minus additionally enabling
> one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> separate patch.
> v4:
> * Revert Wa_14010685332 system list in comments to how it was before
> * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
Thanks, looks ok to me:
Reviewed-by: Imre Deak <imre.deak@intel.com>
nit: cnp_display_clock_gating_wa() would be an even better name, could
be renamed while applying.
> ---
> drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
> 1 file changed, 32 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 98145a7f28a4..9b56a8f81e1a 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> +
> + /*
> + * Wa_14010685332:cnp/cmp,tgp,adp
> + * TODO: Clarify which platforms this applies to
> + * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as
> + * on earlier platforms and whether the workaround is also needed for runtime suspend/resume
> + */
> + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,
> + SBCLK_RUN_REFCLK_DIS);
> + intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);
> + }
> +}
> +
> static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -3063,6 +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv)
>
> if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_reset(dev_priv);
> +
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3104,15 +3124,7 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> GEN3_IRQ_RESET(uncore, SDE);
>
> - /* Wa_14010685332:cnp/cmp,tgp,adp */
> - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
> - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> - SBCLK_RUN_REFCLK_DIS, 0);
> - }
> + cnp_display_clock_wa(dev_priv);
> }
>
> static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> @@ -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> }
> }
>
> +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> +{
> + struct intel_uncore *uncore = &dev_priv->uncore;
> + u32 mask = SDE_GMBUS_ICP;
> +
> + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> +}
> +
> static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> - if (HAS_PCH_SPLIT(dev_priv))
> + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> + icp_irq_postinstall(dev_priv);
> + else if (HAS_PCH_SPLIT(dev_priv))
> ibx_irq_postinstall(dev_priv);
>
> gen8_gt_irq_postinstall(&dev_priv->gt);
> @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> gen8_master_intr_enable(dev_priv->uncore.regs);
> }
>
> -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> -{
> - struct intel_uncore *uncore = &dev_priv->uncore;
> - u32 mask = SDE_GMBUS_ICP;
> -
> - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> -}
>
> static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> {
> --
> 2.29.2
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
2021-02-17 21:18 ` Imre Deak
(?)
@ 2021-02-17 21:19 ` Lyude Paul
-1 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 21:19 UTC (permalink / raw)
To: imre.deak
Cc: intel-gfx, Tejas Upadhyay, Matt Roper, Jani Nikula,
Joonas Lahtinen, Rodrigo Vivi, David Airlie, Daniel Vetter,
open list:DRM DRIVERS, open list
On Wed, 2021-02-17 at 23:18 +0200, Imre Deak wrote:
> On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> >
> > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > setup TGP PCH.
> >
> > v2:
> > * Move Wa_14010685332 into it's own function - vsyrjala
> > * Add TODO comment about figuring out if we can move this workaround - imre
> > v3:
> > * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> > * Add TODO item mentioning we need to clarify which platforms this
> > workaround applies to
> > * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> > functionally equivalent on gen9 bc to the code v2 added
> > * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
> > more or less identical to spt_hpd_irq_setup() minus additionally enabling
> > one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> > separate patch.
> > v4:
> > * Revert Wa_14010685332 system list in comments to how it was before
> > * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > Signed-off-by: Lyude Paul <lyude@redhat.com>
>
> Thanks, looks ok to me:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> nit: cnp_display_clock_gating_wa() would be an even better name, could
> be renamed while applying.
Sure thing. JFYI - I'm going to hold off on pushing this patch until I've got
confirmation from the OEMs this is for that these patches still fix their issues
(since I unfortunately don't have any access to this hardware).
>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
> > 1 file changed, 32 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 98145a7f28a4..9b56a8f81e1a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct
> > drm_i915_private *dev_priv)
> > spin_unlock_irq(&dev_priv->irq_lock);
> > }
> >
> > +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > +
> > + /*
> > + * Wa_14010685332:cnp/cmp,tgp,adp
> > + * TODO: Clarify which platforms this applies to
> > + * TODO: Figure out if this workaround can be applied in the s0ix
> > suspend/resume handlers as
> > + * on earlier platforms and whether the workaround is also needed
> > for runtime suspend/resume
> > + */
> > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1)) {
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > SBCLK_RUN_REFCLK_DIS,
> > + SBCLK_RUN_REFCLK_DIS);
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > SBCLK_RUN_REFCLK_DIS, 0);
> > + }
> > +}
> > +
> > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > {
> > struct intel_uncore *uncore = &dev_priv->uncore;
> > @@ -3063,6 +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private
> > *dev_priv)
> >
> > if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_reset(dev_priv);
> > +
> > + cnp_display_clock_wa(dev_priv);
> > }
> >
> > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3104,15 +3124,7 @@ static void gen11_display_irq_reset(struct
> > drm_i915_private *dev_priv)
> > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > GEN3_IRQ_RESET(uncore, SDE);
> >
> > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS, 0);
> > - }
> > + cnp_display_clock_wa(dev_priv);
> > }
> >
> > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > }
> > }
> >
> > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > + u32 mask = SDE_GMBUS_ICP;
> > +
> > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > +}
> > +
> > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_irq_postinstall(dev_priv);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_postinstall(dev_priv);
> >
> > gen8_gt_irq_postinstall(&dev_priv->gt);
> > @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > gen8_master_intr_enable(dev_priv->uncore.regs);
> > }
> >
> > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > -{
> > - struct intel_uncore *uncore = &dev_priv->uncore;
> > - u32 mask = SDE_GMBUS_ICP;
> > -
> > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > -}
> >
> > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > --
> > 2.29.2
> >
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 21:19 ` Lyude Paul
0 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 21:19 UTC (permalink / raw)
To: imre.deak
Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS,
Rodrigo Vivi, Tejas Upadhyay
On Wed, 2021-02-17 at 23:18 +0200, Imre Deak wrote:
> On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> >
> > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > setup TGP PCH.
> >
> > v2:
> > * Move Wa_14010685332 into it's own function - vsyrjala
> > * Add TODO comment about figuring out if we can move this workaround - imre
> > v3:
> > * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> > * Add TODO item mentioning we need to clarify which platforms this
> > workaround applies to
> > * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> > functionally equivalent on gen9 bc to the code v2 added
> > * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
> > more or less identical to spt_hpd_irq_setup() minus additionally enabling
> > one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> > separate patch.
> > v4:
> > * Revert Wa_14010685332 system list in comments to how it was before
> > * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > Signed-off-by: Lyude Paul <lyude@redhat.com>
>
> Thanks, looks ok to me:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> nit: cnp_display_clock_gating_wa() would be an even better name, could
> be renamed while applying.
Sure thing. JFYI - I'm going to hold off on pushing this patch until I've got
confirmation from the OEMs this is for that these patches still fix their issues
(since I unfortunately don't have any access to this hardware).
>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
> > 1 file changed, 32 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 98145a7f28a4..9b56a8f81e1a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct
> > drm_i915_private *dev_priv)
> > spin_unlock_irq(&dev_priv->irq_lock);
> > }
> >
> > +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > +
> > + /*
> > + * Wa_14010685332:cnp/cmp,tgp,adp
> > + * TODO: Clarify which platforms this applies to
> > + * TODO: Figure out if this workaround can be applied in the s0ix
> > suspend/resume handlers as
> > + * on earlier platforms and whether the workaround is also needed
> > for runtime suspend/resume
> > + */
> > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1)) {
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > SBCLK_RUN_REFCLK_DIS,
> > + SBCLK_RUN_REFCLK_DIS);
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > SBCLK_RUN_REFCLK_DIS, 0);
> > + }
> > +}
> > +
> > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > {
> > struct intel_uncore *uncore = &dev_priv->uncore;
> > @@ -3063,6 +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private
> > *dev_priv)
> >
> > if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_reset(dev_priv);
> > +
> > + cnp_display_clock_wa(dev_priv);
> > }
> >
> > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3104,15 +3124,7 @@ static void gen11_display_irq_reset(struct
> > drm_i915_private *dev_priv)
> > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > GEN3_IRQ_RESET(uncore, SDE);
> >
> > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS, 0);
> > - }
> > + cnp_display_clock_wa(dev_priv);
> > }
> >
> > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > }
> > }
> >
> > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > + u32 mask = SDE_GMBUS_ICP;
> > +
> > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > +}
> > +
> > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_irq_postinstall(dev_priv);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_postinstall(dev_priv);
> >
> > gen8_gt_irq_postinstall(&dev_priv->gt);
> > @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > gen8_master_intr_enable(dev_priv->uncore.regs);
> > }
> >
> > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > -{
> > - struct intel_uncore *uncore = &dev_priv->uncore;
> > - u32 mask = SDE_GMBUS_ICP;
> > -
> > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > -}
> >
> > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > --
> > 2.29.2
> >
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-17 21:19 ` Lyude Paul
0 siblings, 0 replies; 28+ messages in thread
From: Lyude Paul @ 2021-02-17 21:19 UTC (permalink / raw)
To: imre.deak; +Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
On Wed, 2021-02-17 at 23:18 +0200, Imre Deak wrote:
> On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> > From: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> >
> > For Legacy S3 suspend/resume GEN9 BC needs to enable and
> > setup TGP PCH.
> >
> > v2:
> > * Move Wa_14010685332 into it's own function - vsyrjala
> > * Add TODO comment about figuring out if we can move this workaround - imre
> > v3:
> > * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> > * Add TODO item mentioning we need to clarify which platforms this
> > workaround applies to
> > * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> > functionally equivalent on gen9 bc to the code v2 added
> > * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks to be
> > more or less identical to spt_hpd_irq_setup() minus additionally enabling
> > one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> > separate patch.
> > v4:
> > * Revert Wa_14010685332 system list in comments to how it was before
> > * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
> >
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > Signed-off-by: Lyude Paul <lyude@redhat.com>
>
> Thanks, looks ok to me:
> Reviewed-by: Imre Deak <imre.deak@intel.com>
>
> nit: cnp_display_clock_gating_wa() would be an even better name, could
> be renamed while applying.
Sure thing. JFYI - I'm going to hold off on pushing this patch until I've got
confirmation from the OEMs this is for that these patches still fix their issues
(since I unfortunately don't have any access to this hardware).
>
> > ---
> > drivers/gpu/drm/i915/i915_irq.c | 49 +++++++++++++++++++++------------
> > 1 file changed, 32 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 98145a7f28a4..9b56a8f81e1a 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct
> > drm_i915_private *dev_priv)
> > spin_unlock_irq(&dev_priv->irq_lock);
> > }
> >
> > +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > +
> > + /*
> > + * Wa_14010685332:cnp/cmp,tgp,adp
> > + * TODO: Clarify which platforms this applies to
> > + * TODO: Figure out if this workaround can be applied in the s0ix
> > suspend/resume handlers as
> > + * on earlier platforms and whether the workaround is also needed
> > for runtime suspend/resume
> > + */
> > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv)
> > < PCH_DG1)) {
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > SBCLK_RUN_REFCLK_DIS,
> > + SBCLK_RUN_REFCLK_DIS);
> > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > SBCLK_RUN_REFCLK_DIS, 0);
> > + }
> > +}
> > +
> > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > {
> > struct intel_uncore *uncore = &dev_priv->uncore;
> > @@ -3063,6 +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private
> > *dev_priv)
> >
> > if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_reset(dev_priv);
> > +
> > + cnp_display_clock_wa(dev_priv);
> > }
> >
> > static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3104,15 +3124,7 @@ static void gen11_display_irq_reset(struct
> > drm_i915_private *dev_priv)
> > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > GEN3_IRQ_RESET(uncore, SDE);
> >
> > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS,
> > SBCLK_RUN_REFCLK_DIS);
> > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > - SBCLK_RUN_REFCLK_DIS, 0);
> > - }
> > + cnp_display_clock_wa(dev_priv);
> > }
> >
> > static void gen11_irq_reset(struct drm_i915_private *dev_priv)
> > @@ -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > }
> > }
> >
> > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > +{
> > + struct intel_uncore *uncore = &dev_priv->uncore;
> > + u32 mask = SDE_GMBUS_ICP;
> > +
> > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > +}
> > +
> > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > - if (HAS_PCH_SPLIT(dev_priv))
> > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > + icp_irq_postinstall(dev_priv);
> > + else if (HAS_PCH_SPLIT(dev_priv))
> > ibx_irq_postinstall(dev_priv);
> >
> > gen8_gt_irq_postinstall(&dev_priv->gt);
> > @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > gen8_master_intr_enable(dev_priv->uncore.regs);
> > }
> >
> > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > -{
> > - struct intel_uncore *uncore = &dev_priv->uncore;
> > - u32 mask = SDE_GMBUS_ICP;
> > -
> > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff);
> > -}
> >
> > static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
> > {
> > --
> > 2.29.2
> >
>
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
asked me a question, are waiting for a review/merge on a patch, etc. and I
haven't responded in a while, please feel free to send me another email to check
on my status. I don't bite!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev2)
2021-02-17 2:53 ` Lyude Paul
` (7 preceding siblings ...)
(?)
@ 2021-02-17 23:05 ` Patchwork
-1 siblings, 0 replies; 28+ messages in thread
From: Patchwork @ 2021-02-17 23:05 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30308 bytes --]
== Series Details ==
Series: series starting with [v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/87148/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9783_full -> Patchwork_19697_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_19697_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#3002])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl4/igt@gem_create@create-massive.html
* igt@gem_ctx_persistence@process:
- shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +1 similar issue
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-snb6/igt@gem_ctx_persistence@process.html
* igt@gem_eio@in-flight-suspend:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#1037] / [i915#198])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl9/igt@gem_eio@in-flight-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl3/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: NOTRUN -> [FAIL][5] ([i915#2846])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][8] ([i915#2842])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-kbl1/igt@gem_exec_fair@basic-none@vecs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl7/igt@gem_exec_fair@basic-none@vecs0.html
- shard-apl: [PASS][11] -> [FAIL][12] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-apl6/igt@gem_exec_fair@basic-none@vecs0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl2/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_reloc@basic-many-active@vcs0:
- shard-kbl: NOTRUN -> [FAIL][14] ([i915#2389]) +4 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl6/igt@gem_exec_reloc@basic-many-active@vcs0.html
* igt@gem_exec_reloc@basic-parallel:
- shard-apl: NOTRUN -> [TIMEOUT][15] ([i915#1729])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl3/igt@gem_exec_reloc@basic-parallel.html
* igt@gem_exec_reloc@basic-wide-active@bcs0:
- shard-apl: NOTRUN -> [FAIL][16] ([i915#2389]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl2/igt@gem_exec_reloc@basic-wide-active@bcs0.html
* igt@gem_exec_schedule@u-fairslice@rcs0:
- shard-skl: [PASS][17] -> [DMESG-WARN][18] ([i915#1610] / [i915#2803])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl4/igt@gem_exec_schedule@u-fairslice@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl10/igt@gem_exec_schedule@u-fairslice@rcs0.html
* igt@gem_exec_schedule@u-fairslice@vecs0:
- shard-apl: NOTRUN -> [DMESG-WARN][19] ([i915#1610])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl3/igt@gem_exec_schedule@u-fairslice@vecs0.html
* igt@gem_pwrite@basic-exhaustion:
- shard-kbl: NOTRUN -> [WARN][20] ([i915#2658]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl2/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-glk: NOTRUN -> [SKIP][21] ([fdo#109271]) +29 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-glk2/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_userptr_blits@input-checking:
- shard-snb: NOTRUN -> [DMESG-WARN][22] ([i915#3002])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-snb6/igt@gem_userptr_blits@input-checking.html
* igt@gem_userptr_blits@vma-merge:
- shard-snb: NOTRUN -> [FAIL][23] ([i915#2724])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-snb6/igt@gem_userptr_blits@vma-merge.html
- shard-apl: NOTRUN -> [INCOMPLETE][24] ([i915#2502] / [i915#2667])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl6/igt@gem_userptr_blits@vma-merge.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-iclb: NOTRUN -> [SKIP][25] ([fdo#112306])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb8/igt@gen9_exec_parse@batch-invalid-length.html
* igt@i915_pm_dc@dc6-dpms:
- shard-kbl: NOTRUN -> [FAIL][26] ([i915#454])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl6/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][27] ([fdo#109271] / [i915#1937])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
- shard-apl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#1937])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_selftest@live@hangcheck:
- shard-skl: NOTRUN -> [INCOMPLETE][29] ([i915#2782])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl6/igt@i915_selftest@live@hangcheck.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][30] ([fdo#110725] / [fdo#111614]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb8/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][31] ([fdo#110723])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb8/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_big_joiner@basic:
- shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#2705])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl2/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-c-bad-rotation-90:
- shard-skl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111304])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl9/igt@kms_ccs@pipe-c-bad-rotation-90.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-glk: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +5 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-glk2/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-snb: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +16 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-snb7/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_color@pipe-c-ctm-0-5:
- shard-skl: [PASS][36] -> [DMESG-WARN][37] ([i915#1982])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl9/igt@kms_color@pipe-c-ctm-0-5.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl3/igt@kms_color@pipe-c-ctm-0-5.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-kbl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +24 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl4/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_color_chamelium@pipe-b-ctm-0-5:
- shard-skl: NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl9/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
* igt@kms_color_chamelium@pipe-b-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb8/igt@kms_color_chamelium@pipe-b-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-c-ctm-max:
- shard-apl: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +18 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl2/igt@kms_color_chamelium@pipe-c-ctm-max.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][42] ([i915#1319])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl3/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@uevent:
- shard-kbl: NOTRUN -> [FAIL][43] ([i915#2105])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl1/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding:
- shard-skl: NOTRUN -> [FAIL][44] ([i915#54])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-128x128-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-random:
- shard-apl: NOTRUN -> [FAIL][45] ([i915#54])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
- shard-skl: [PASS][46] -> [FAIL][47] ([i915#54]) +7 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl9/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109274] / [fdo#109278])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@pipe-d-single-bo:
- shard-glk: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#533]) +1 similar issue
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-glk2/igt@kms_cursor_legacy@pipe-d-single-bo.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109278]) +2 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb8/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109274])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb8/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][52] -> [FAIL][53] ([i915#2122])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@blocking-wf_vblank@a-edp1:
- shard-skl: [PASS][54] -> [FAIL][55] ([i915#2122]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl8/igt@kms_flip@blocking-wf_vblank@a-edp1.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl3/igt@kms_flip@blocking-wf_vblank@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: NOTRUN -> [FAIL][56] ([i915#2122]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl9/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs:
- shard-kbl: NOTRUN -> [FAIL][57] ([i915#2641])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#2642])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
- shard-kbl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2642])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
- shard-apl: NOTRUN -> [FAIL][60] ([i915#2641])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2672])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack:
- shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271]) +14 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl9/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109280]) +7 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite:
- shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271]) +206 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271]) +193 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#533])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][67] ([i915#265])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][68] ([fdo#108145] / [i915#265]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][69] ([i915#265]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl4/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][70] ([fdo#108145] / [i915#265]) +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
- shard-kbl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#658]) +4 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl6/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-2:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#658]) +6 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-3:
- shard-glk: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#658])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-glk2/igt@kms_psr2_sf@plane-move-sf-dmg-area-3.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][74] -> [SKIP][75] ([fdo#109642] / [fdo#111068] / [i915#658])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb3/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][76] -> [SKIP][77] ([fdo#109441]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-iclb2/igt@kms_psr@psr2_basic.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb3/igt@kms_psr@psr2_basic.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109441])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb8/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_sysfs_edid_timing:
- shard-apl: NOTRUN -> [FAIL][79] ([IGT#2])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl6/igt@kms_sysfs_edid_timing.html
* igt@kms_vblank@pipe-d-query-forked-hang:
- shard-snb: NOTRUN -> [SKIP][80] ([fdo#109271]) +296 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-snb6/igt@kms_vblank@pipe-d-query-forked-hang.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2437])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl1/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][82] ([i915#2530])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb8/igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame.html
* igt@perf@polling-parameterized:
- shard-tglb: [PASS][83] -> [FAIL][84] ([i915#1542])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-tglb1/igt@perf@polling-parameterized.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-tglb5/igt@perf@polling-parameterized.html
* igt@prime_nv_pcopy@test3_4:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109291])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb8/igt@prime_nv_pcopy@test3_4.html
* igt@prime_vgem@sync@rcs0:
- shard-iclb: [PASS][86] -> [INCOMPLETE][87] ([i915#409])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-iclb1/igt@prime_vgem@sync@rcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb3/igt@prime_vgem@sync@rcs0.html
* igt@sysfs_clients@recycle:
- shard-apl: [PASS][88] -> [FAIL][89] ([i915#3028])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-apl6/igt@sysfs_clients@recycle.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl3/igt@sysfs_clients@recycle.html
- shard-tglb: [PASS][90] -> [FAIL][91] ([i915#3028])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-tglb8/igt@sysfs_clients@recycle.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-tglb3/igt@sysfs_clients@recycle.html
* igt@sysfs_clients@recycle-many:
- shard-snb: NOTRUN -> [FAIL][92] ([i915#3028])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-snb5/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@split-10@bcs0:
- shard-kbl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#3026])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl6/igt@sysfs_clients@split-10@bcs0.html
* igt@sysfs_clients@split-10@vcs0:
- shard-skl: [PASS][94] -> [SKIP][95] ([fdo#109271] / [i915#3026]) +1 similar issue
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl3/igt@sysfs_clients@split-10@vcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl4/igt@sysfs_clients@split-10@vcs0.html
#### Possible fixes ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-glk: [TIMEOUT][96] ([i915#2918]) -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-glk8/igt@gem_ctx_persistence@close-replace-race.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-glk4/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][98] ([i915#1037] / [i915#3063]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-tglb2/igt@gem_eio@unwedge-stress.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-tglb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-apl: [FAIL][100] ([i915#2842]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-apl6/igt@gem_exec_fair@basic-none@vcs0.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl2/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [FAIL][102] ([i915#2842]) -> [PASS][103] +1 similar issue
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-glk5/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-iclb: [FAIL][104] ([i915#2842]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-iclb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_schedule@u-fairslice-all:
- shard-skl: [DMESG-WARN][106] ([i915#1610] / [i915#1982] / [i915#2803]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl2/igt@gem_exec_schedule@u-fairslice-all.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl9/igt@gem_exec_schedule@u-fairslice-all.html
* igt@gem_exec_schedule@u-fairslice@bcs0:
- shard-skl: [DMESG-WARN][108] ([i915#1610] / [i915#2803]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl4/igt@gem_exec_schedule@u-fairslice@bcs0.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl10/igt@gem_exec_schedule@u-fairslice@bcs0.html
* igt@i915_selftest@live@client:
- shard-glk: [DMESG-FAIL][110] ([i915#3047]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-glk8/igt@i915_selftest@live@client.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-glk4/igt@i915_selftest@live@client.html
* igt@i915_selftest@live@gem_contexts:
- shard-skl: [INCOMPLETE][112] ([i915#198] / [i915#2782]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl1/igt@i915_selftest@live@gem_contexts.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl6/igt@i915_selftest@live@gem_contexts.html
* igt@kms_async_flips@test-time-stamp:
- shard-tglb: [FAIL][114] ([i915#2597]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-tglb1/igt@kms_async_flips@test-time-stamp.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-tglb7/igt@kms_async_flips@test-time-stamp.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-random:
- shard-skl: [FAIL][116] ([i915#54]) -> [PASS][117] +4 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl10/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl2/igt@kms_cursor_crc@pipe-c-cursor-128x128-random.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic:
- shard-tglb: [FAIL][118] ([i915#2346]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-tglb8/igt@kms_cursor_legacy@flip-vs-cursor-atomic.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-tglb: [FAIL][120] ([i915#2598]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-tglb1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][122] ([i915#79]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-ts-check@c-edp1:
- shard-skl: [FAIL][124] ([i915#2122]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl10/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl5/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][126] ([i915#1188]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl5/igt@kms_hdr@bpc-switch.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl7/igt@kms_hdr@bpc-switch.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][128] ([fdo#108145] / [i915#265]) -> [PASS][129] +1 similar issue
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][130] ([fdo#109441]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_cpu.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@perf_pmu@rc6-suspend:
- shard-apl: [DMESG-WARN][132] ([i915#180]) -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-apl1/igt@perf_pmu@rc6-suspend.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-apl6/igt@perf_pmu@rc6-suspend.html
* igt@sysfs_clients@busy@bcs0:
- shard-glk: [FAIL][134] ([i915#3019]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-glk1/igt@sysfs_clients@busy@bcs0.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-glk5/igt@sysfs_clients@busy@bcs0.html
* igt@sysfs_clients@recycle-many:
- shard-iclb: [FAIL][136] ([i915#3028]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-iclb2/igt@sysfs_clients@recycle-many.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb3/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@sema-25@vecs0:
- shard-skl: [SKIP][138] ([fdo#109271]) -> [PASS][139]
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-skl8/igt@sysfs_clients@sema-25@vecs0.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-skl2/igt@sysfs_clients@sema-25@vecs0.html
* igt@sysfs_heartbeat_interval@precise@rcs0:
- shard-kbl: [INCOMPLETE][140] -> [PASS][141]
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-kbl2/igt@sysfs_heartbeat_interval@precise@rcs0.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-kbl2/igt@sysfs_heartbeat_interval@precise@rcs0.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][142] ([i915#2681] / [i915#2684]) -> [WARN][143] ([i915#1804] / [i915#2684])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9783/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][144] ([i915#1804]
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_19697/index.html
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_______________________________________________
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^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
2021-02-17 21:19 ` Lyude Paul
(?)
@ 2021-02-18 4:36 ` Surendrakumar Upadhyay, TejaskumarX
-1 siblings, 0 replies; 28+ messages in thread
From: Surendrakumar Upadhyay, TejaskumarX @ 2021-02-18 4:36 UTC (permalink / raw)
To: lyude, Deak, Imre
Cc: intel-gfx, Roper, Matthew D, Jani Nikula, Joonas Lahtinen, Vivi,
Rodrigo, David Airlie, Daniel Vetter, open list:DRM DRIVERS,
open list
> -----Original Message-----
> From: Lyude Paul <lyude@redhat.com>
> Sent: 18 February 2021 02:49
> To: Deak, Imre <imre.deak@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Surendrakumar Upadhyay, TejaskumarX
> <tejaskumarx.surendrakumar.upadhyay@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Jani Nikula <jani.nikula@linux.intel.com>;
> Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>; David Airlie <airlied@linux.ie>; Daniel Vetter
> <daniel@ffwll.ch>; open list:DRM DRIVERS <dri-
> devel@lists.freedesktop.org>; open list <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during
> suspend/resume
>
> On Wed, 2021-02-17 at 23:18 +0200, Imre Deak wrote:
> > On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> > > From: Tejas Upadhyay
> <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > >
> > > For Legacy S3 suspend/resume GEN9 BC needs to enable and setup TGP
> > > PCH.
> > >
> > > v2:
> > > * Move Wa_14010685332 into it's own function - vsyrjala
> > > * Add TODO comment about figuring out if we can move this workaround
> > > - imre
> > > v3:
> > > * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> > > * Add TODO item mentioning we need to clarify which platforms this
> > > workaround applies to
> > > * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> > > functionally equivalent on gen9 bc to the code v2 added
> > > * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks
> > > to be
> > > more or less identical to spt_hpd_irq_setup() minus additionally
> > > enabling
> > > one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> > > separate patch.
> > > v4:
> > > * Revert Wa_14010685332 system list in comments to how it was before
> > > * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Tejas Upadhyay
> > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > Signed-off-by: Lyude Paul <lyude@redhat.com>
> >
> > Thanks, looks ok to me:
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> >
> > nit: cnp_display_clock_gating_wa() would be an even better name, could
> > be renamed while applying.
>
> Sure thing. JFYI - I'm going to hold off on pushing this patch until I've got
> confirmation from the OEMs this is for that these patches still fix their issues
> (since I unfortunately don't have any access to this hardware).
I can follow up with OEM to test or I can get it tested in my LAB, as I have RKL RVP (CML CPU) + TGP PCH with me.
>
> >
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 49
> > > +++++++++++++++++++++------------
> > > 1 file changed, 32 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c index 98145a7f28a4..9b56a8f81e1a
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > +
> > > + /*
> > > + * Wa_14010685332:cnp/cmp,tgp,adp
> > > + * TODO: Clarify which platforms this applies to
> > > + * TODO: Figure out if this workaround can be applied in the
> > > +s0ix
> > > suspend/resume handlers as
> > > + * on earlier platforms and whether the workaround is also
> > > +needed
> > > for runtime suspend/resume
> > > + */
> > > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > +INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1)) {
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > SBCLK_RUN_REFCLK_DIS,
> > > + SBCLK_RUN_REFCLK_DIS);
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > SBCLK_RUN_REFCLK_DIS, 0);
> > > + }
> > > +}
> > > +
> > > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > > {
> > > struct intel_uncore *uncore = &dev_priv->uncore; @@ -3063,6
> > > +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private
> > > *dev_priv)
> > >
> > > if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_reset(dev_priv);
> > > +
> > > + cnp_display_clock_wa(dev_priv);
> > > }
> > >
> > > static void gen11_display_irq_reset(struct drm_i915_private
> > > *dev_priv) @@ -3104,15 +3124,7 @@ static void
> > > gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > GEN3_IRQ_RESET(uncore, SDE);
> > >
> > > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS, 0);
> > > - }
> > > + cnp_display_clock_wa(dev_priv);
> > > }
> > >
> > > static void gen11_irq_reset(struct drm_i915_private *dev_priv) @@
> > > -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > + u32 mask = SDE_GMBUS_ICP;
> > > +
> > > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); }
> > > +
> > > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_irq_postinstall(dev_priv);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_postinstall(dev_priv);
> > >
> > > gen8_gt_irq_postinstall(&dev_priv->gt);
> > > @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > gen8_master_intr_enable(dev_priv->uncore.regs);
> > > }
> > >
> > > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > -{
> > > - struct intel_uncore *uncore = &dev_priv->uncore;
> > > - u32 mask = SDE_GMBUS_ICP;
> > > -
> > > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); -}
> > >
> > > static void gen11_irq_postinstall(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > --
> > > 2.29.2
> > >
> >
>
> --
> Sincerely,
> Lyude Paul (she/her)
> Software Engineer at Red Hat
>
> Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
> asked me a question, are waiting for a review/merge on a patch, etc. and I
> haven't responded in a while, please feel free to send me another email to
> check on my status. I don't bite!
^ permalink raw reply [flat|nested] 28+ messages in thread
* RE: [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-18 4:36 ` Surendrakumar Upadhyay, TejaskumarX
0 siblings, 0 replies; 28+ messages in thread
From: Surendrakumar Upadhyay, TejaskumarX @ 2021-02-18 4:36 UTC (permalink / raw)
To: lyude, Deak, Imre
Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS, Vivi, Rodrigo
> -----Original Message-----
> From: Lyude Paul <lyude@redhat.com>
> Sent: 18 February 2021 02:49
> To: Deak, Imre <imre.deak@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Surendrakumar Upadhyay, TejaskumarX
> <tejaskumarx.surendrakumar.upadhyay@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Jani Nikula <jani.nikula@linux.intel.com>;
> Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>; David Airlie <airlied@linux.ie>; Daniel Vetter
> <daniel@ffwll.ch>; open list:DRM DRIVERS <dri-
> devel@lists.freedesktop.org>; open list <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during
> suspend/resume
>
> On Wed, 2021-02-17 at 23:18 +0200, Imre Deak wrote:
> > On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> > > From: Tejas Upadhyay
> <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > >
> > > For Legacy S3 suspend/resume GEN9 BC needs to enable and setup TGP
> > > PCH.
> > >
> > > v2:
> > > * Move Wa_14010685332 into it's own function - vsyrjala
> > > * Add TODO comment about figuring out if we can move this workaround
> > > - imre
> > > v3:
> > > * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> > > * Add TODO item mentioning we need to clarify which platforms this
> > > workaround applies to
> > > * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> > > functionally equivalent on gen9 bc to the code v2 added
> > > * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks
> > > to be
> > > more or less identical to spt_hpd_irq_setup() minus additionally
> > > enabling
> > > one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> > > separate patch.
> > > v4:
> > > * Revert Wa_14010685332 system list in comments to how it was before
> > > * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Tejas Upadhyay
> > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > Signed-off-by: Lyude Paul <lyude@redhat.com>
> >
> > Thanks, looks ok to me:
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> >
> > nit: cnp_display_clock_gating_wa() would be an even better name, could
> > be renamed while applying.
>
> Sure thing. JFYI - I'm going to hold off on pushing this patch until I've got
> confirmation from the OEMs this is for that these patches still fix their issues
> (since I unfortunately don't have any access to this hardware).
I can follow up with OEM to test or I can get it tested in my LAB, as I have RKL RVP (CML CPU) + TGP PCH with me.
>
> >
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 49
> > > +++++++++++++++++++++------------
> > > 1 file changed, 32 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c index 98145a7f28a4..9b56a8f81e1a
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > +
> > > + /*
> > > + * Wa_14010685332:cnp/cmp,tgp,adp
> > > + * TODO: Clarify which platforms this applies to
> > > + * TODO: Figure out if this workaround can be applied in the
> > > +s0ix
> > > suspend/resume handlers as
> > > + * on earlier platforms and whether the workaround is also
> > > +needed
> > > for runtime suspend/resume
> > > + */
> > > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > +INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1)) {
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > SBCLK_RUN_REFCLK_DIS,
> > > + SBCLK_RUN_REFCLK_DIS);
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > SBCLK_RUN_REFCLK_DIS, 0);
> > > + }
> > > +}
> > > +
> > > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > > {
> > > struct intel_uncore *uncore = &dev_priv->uncore; @@ -3063,6
> > > +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private
> > > *dev_priv)
> > >
> > > if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_reset(dev_priv);
> > > +
> > > + cnp_display_clock_wa(dev_priv);
> > > }
> > >
> > > static void gen11_display_irq_reset(struct drm_i915_private
> > > *dev_priv) @@ -3104,15 +3124,7 @@ static void
> > > gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > GEN3_IRQ_RESET(uncore, SDE);
> > >
> > > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS, 0);
> > > - }
> > > + cnp_display_clock_wa(dev_priv);
> > > }
> > >
> > > static void gen11_irq_reset(struct drm_i915_private *dev_priv) @@
> > > -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > + u32 mask = SDE_GMBUS_ICP;
> > > +
> > > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); }
> > > +
> > > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_irq_postinstall(dev_priv);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_postinstall(dev_priv);
> > >
> > > gen8_gt_irq_postinstall(&dev_priv->gt);
> > > @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > gen8_master_intr_enable(dev_priv->uncore.regs);
> > > }
> > >
> > > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > -{
> > > - struct intel_uncore *uncore = &dev_priv->uncore;
> > > - u32 mask = SDE_GMBUS_ICP;
> > > -
> > > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); -}
> > >
> > > static void gen11_irq_postinstall(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > --
> > > 2.29.2
> > >
> >
>
> --
> Sincerely,
> Lyude Paul (she/her)
> Software Engineer at Red Hat
>
> Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
> asked me a question, are waiting for a review/merge on a patch, etc. and I
> haven't responded in a while, please feel free to send me another email to
> check on my status. I don't bite!
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Intel-gfx] [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume
@ 2021-02-18 4:36 ` Surendrakumar Upadhyay, TejaskumarX
0 siblings, 0 replies; 28+ messages in thread
From: Surendrakumar Upadhyay, TejaskumarX @ 2021-02-18 4:36 UTC (permalink / raw)
To: lyude, Deak, Imre
Cc: David Airlie, intel-gfx, open list, open list:DRM DRIVERS
> -----Original Message-----
> From: Lyude Paul <lyude@redhat.com>
> Sent: 18 February 2021 02:49
> To: Deak, Imre <imre.deak@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Surendrakumar Upadhyay, TejaskumarX
> <tejaskumarx.surendrakumar.upadhyay@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Jani Nikula <jani.nikula@linux.intel.com>;
> Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Vivi, Rodrigo
> <rodrigo.vivi@intel.com>; David Airlie <airlied@linux.ie>; Daniel Vetter
> <daniel@ffwll.ch>; open list:DRM DRIVERS <dri-
> devel@lists.freedesktop.org>; open list <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH v4] drm/i915/gen9bc: Handle TGP PCH during
> suspend/resume
>
> On Wed, 2021-02-17 at 23:18 +0200, Imre Deak wrote:
> > On Wed, Feb 17, 2021 at 01:00:16PM -0500, Lyude Paul wrote:
> > > From: Tejas Upadhyay
> <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > >
> > > For Legacy S3 suspend/resume GEN9 BC needs to enable and setup TGP
> > > PCH.
> > >
> > > v2:
> > > * Move Wa_14010685332 into it's own function - vsyrjala
> > > * Add TODO comment about figuring out if we can move this workaround
> > > - imre
> > > v3:
> > > * Rename cnp_irq_post_reset() to cnp_display_clock_wa()
> > > * Add TODO item mentioning we need to clarify which platforms this
> > > workaround applies to
> > > * Just use ibx_irq_reset() in gen8_irq_reset(). This code should be
> > > functionally equivalent on gen9 bc to the code v2 added
> > > * Drop icp_hpd_irq_setup() call in spt_hpd_irq_setup(), this looks
> > > to be
> > > more or less identical to spt_hpd_irq_setup() minus additionally
> > > enabling
> > > one port. Will update i915 to use icp_hpd_irq_setup() for ICP in a
> > > separate patch.
> > > v4:
> > > * Revert Wa_14010685332 system list in comments to how it was before
> > > * Add back HAS_PCH_SPLIT() check before calling ibx_irq_reset()
> > >
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Signed-off-by: Tejas Upadhyay
> > > <tejaskumarx.surendrakumar.upadhyay@intel.com>
> > > Signed-off-by: Lyude Paul <lyude@redhat.com>
> >
> > Thanks, looks ok to me:
> > Reviewed-by: Imre Deak <imre.deak@intel.com>
> >
> > nit: cnp_display_clock_gating_wa() would be an even better name, could
> > be renamed while applying.
>
> Sure thing. JFYI - I'm going to hold off on pushing this patch until I've got
> confirmation from the OEMs this is for that these patches still fix their issues
> (since I unfortunately don't have any access to this hardware).
I can follow up with OEM to test or I can get it tested in my LAB, as I have RKL RVP (CML CPU) + TGP PCH with me.
>
> >
> > > ---
> > > drivers/gpu/drm/i915/i915_irq.c | 49
> > > +++++++++++++++++++++------------
> > > 1 file changed, 32 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c index 98145a7f28a4..9b56a8f81e1a
> > > 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -3040,6 +3040,24 @@ static void valleyview_irq_reset(struct
> > > drm_i915_private *dev_priv)
> > > spin_unlock_irq(&dev_priv->irq_lock);
> > > }
> > >
> > > +static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > +
> > > + /*
> > > + * Wa_14010685332:cnp/cmp,tgp,adp
> > > + * TODO: Clarify which platforms this applies to
> > > + * TODO: Figure out if this workaround can be applied in the
> > > +s0ix
> > > suspend/resume handlers as
> > > + * on earlier platforms and whether the workaround is also
> > > +needed
> > > for runtime suspend/resume
> > > + */
> > > + if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > + (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > +INTEL_PCH_TYPE(dev_priv)
> > > < PCH_DG1)) {
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > SBCLK_RUN_REFCLK_DIS,
> > > + SBCLK_RUN_REFCLK_DIS);
> > > + intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > SBCLK_RUN_REFCLK_DIS, 0);
> > > + }
> > > +}
> > > +
> > > static void gen8_irq_reset(struct drm_i915_private *dev_priv)
> > > {
> > > struct intel_uncore *uncore = &dev_priv->uncore; @@ -3063,6
> > > +3081,8 @@ static void gen8_irq_reset(struct drm_i915_private
> > > *dev_priv)
> > >
> > > if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_reset(dev_priv);
> > > +
> > > + cnp_display_clock_wa(dev_priv);
> > > }
> > >
> > > static void gen11_display_irq_reset(struct drm_i915_private
> > > *dev_priv) @@ -3104,15 +3124,7 @@ static void
> > > gen11_display_irq_reset(struct drm_i915_private *dev_priv)
> > > if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > GEN3_IRQ_RESET(uncore, SDE);
> > >
> > > - /* Wa_14010685332:cnp/cmp,tgp,adp */
> > > - if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||
> > > - (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
> > > - INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS,
> > > SBCLK_RUN_REFCLK_DIS);
> > > - intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
> > > - SBCLK_RUN_REFCLK_DIS, 0);
> > > - }
> > > + cnp_display_clock_wa(dev_priv);
> > > }
> > >
> > > static void gen11_irq_reset(struct drm_i915_private *dev_priv) @@
> > > -3764,9 +3776,19 @@ static void gen8_de_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > }
> > > }
> > >
> > > +static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > +{
> > > + struct intel_uncore *uncore = &dev_priv->uncore;
> > > + u32 mask = SDE_GMBUS_ICP;
> > > +
> > > + GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); }
> > > +
> > > static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
> > > {
> > > - if (HAS_PCH_SPLIT(dev_priv))
> > > + if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
> > > + icp_irq_postinstall(dev_priv);
> > > + else if (HAS_PCH_SPLIT(dev_priv))
> > > ibx_irq_postinstall(dev_priv);
> > >
> > > gen8_gt_irq_postinstall(&dev_priv->gt);
> > > @@ -3775,13 +3797,6 @@ static void gen8_irq_postinstall(struct
> > > drm_i915_private *dev_priv)
> > > gen8_master_intr_enable(dev_priv->uncore.regs);
> > > }
> > >
> > > -static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
> > > -{
> > > - struct intel_uncore *uncore = &dev_priv->uncore;
> > > - u32 mask = SDE_GMBUS_ICP;
> > > -
> > > - GEN3_IRQ_INIT(uncore, SDE, ~mask, 0xffffffff); -}
> > >
> > > static void gen11_irq_postinstall(struct drm_i915_private
> > > *dev_priv)
> > > {
> > > --
> > > 2.29.2
> > >
> >
>
> --
> Sincerely,
> Lyude Paul (she/her)
> Software Engineer at Red Hat
>
> Note: I deal with a lot of emails and have a lot of bugs on my plate. If you've
> asked me a question, are waiting for a review/merge on a patch, etc. and I
> haven't responded in a while, please feel free to send me another email to
> check on my status. I don't bite!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2021-02-18 4:37 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-17 2:53 [PATCH v3 1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume Lyude Paul
2021-02-17 2:53 ` [Intel-gfx] " Lyude Paul
2021-02-17 2:53 ` Lyude Paul
2021-02-17 2:53 ` [PATCH v3 2/2] drm/i915/icp+: Use icp_hpd_irq_setup() instead of spt_hpd_irq_setup() Lyude Paul
2021-02-17 2:53 ` [Intel-gfx] " Lyude Paul
2021-02-17 2:53 ` Lyude Paul
2021-02-17 18:18 ` Rodrigo Vivi
2021-02-17 18:18 ` [Intel-gfx] " Rodrigo Vivi
2021-02-17 18:18 ` Rodrigo Vivi
2021-02-17 3:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915/gen9bc: Handle TGP PCH during suspend/resume Patchwork
2021-02-17 4:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-02-17 8:02 ` [PATCH v3 1/2] " Imre Deak
2021-02-17 8:02 ` [Intel-gfx] " Imre Deak
2021-02-17 8:02 ` Imre Deak
2021-02-17 18:00 ` [PATCH v4] " Lyude Paul
2021-02-17 18:00 ` [Intel-gfx] " Lyude Paul
2021-02-17 18:00 ` Lyude Paul
2021-02-17 21:18 ` Imre Deak
2021-02-17 21:18 ` [Intel-gfx] " Imre Deak
2021-02-17 21:18 ` Imre Deak
2021-02-17 21:19 ` Lyude Paul
2021-02-17 21:19 ` [Intel-gfx] " Lyude Paul
2021-02-17 21:19 ` Lyude Paul
2021-02-18 4:36 ` Surendrakumar Upadhyay, TejaskumarX
2021-02-18 4:36 ` [Intel-gfx] " Surendrakumar Upadhyay, TejaskumarX
2021-02-18 4:36 ` Surendrakumar Upadhyay, TejaskumarX
2021-02-17 19:31 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v4] drm/i915/gen9bc: Handle TGP PCH during suspend/resume (rev2) Patchwork
2021-02-17 23:05 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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