From: Dmitry Osipenko <digetx@gmail.com> To: Nicolin Chen <nicoleotsuka@gmail.com> Cc: thierry.reding@gmail.com, joro@8bytes.org, will@kernel.org, vdumpa@nvidia.com, jonathanh@nvidia.com, linux-tegra@vger.kernel.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 6/6] iommu/tegra-smmu: Add pagetable mappings to debugfs Date: Wed, 15 Sep 2021 15:09:48 +0300 [thread overview] Message-ID: <a5a77169-8711-2983-d2cb-4b94061741b9@gmail.com> (raw) In-Reply-To: <20210915043806.GA19185@Asurada-Nvidia> 15.09.2021 07:38, Nicolin Chen пишет: > On Tue, Sep 14, 2021 at 10:20:30PM +0300, Dmitry Osipenko wrote: >> 14.09.2021 21:49, Nicolin Chen пишет: >>> On Tue, Sep 14, 2021 at 04:29:15PM +0300, Dmitry Osipenko wrote: >>>> 14.09.2021 04:38, Nicolin Chen пишет: >>>>> +static unsigned long pd_pt_index_iova(unsigned int pd_index, unsigned int pt_index) >>>>> +{ >>>>> + return ((dma_addr_t)pd_index & (SMMU_NUM_PDE - 1)) << SMMU_PDE_SHIFT | >>>>> + ((dma_addr_t)pt_index & (SMMU_NUM_PTE - 1)) << SMMU_PTE_SHIFT; >>>>> +} >>>> >>>> We know that IOVA is fixed to u32 for this controller. Can we avoid all >>>> these dma_addr_t castings? It should make code cleaner a tad, IMO. >>> >>> Tegra210 actually supports 34-bit IOVA... >>> >> >> It doesn't. 34-bit is PA, 32-bit is VA. >> >> Quote from T210 TRM: >> >> "The SMMU is a centralized virtual-to-physical translation for MSS. It >> maps a 32-bit virtual address to a 34-bit physical address. If the >> client address is 40 bits then bits 39:32 are ignored." > > If you scroll down by a couple of sections, you can see 34-bit > virtual addresses in section 18.6.1.2; and if checking one ASID > register, you can see it mention the extra two bits va[33:32]. Thanks for the pointer. It says that only certain memory clients allow to combine 4 ASIDs to form 34bit VA space. In this case the PA space is split into 4GB areas and there are additional bitfields which configure the ASID mapping of each 4GB area. Still each ASID is 32bit. This is what TRM says: "For the GPU and other clients with 34-bit address interfaces, the ASID registers are extended to point to four ASIDs. The SMMU supports 4GB of virtual address space per ASID, so mapping addr[33:32] into ASID[1:0] extends the virtual address space of a client to 16GB." > However, the driver currently sets its geometry.aperture_end to > 32-bit, and we can only get 32-bit IOVAs using PDE and PTE only, > so I think it should be safe to remove the castings here. I'll > wait for a couple of days and see if there'd be other comments > for me to address in next version. You will need to read the special "ASID Assignment Register" which supports 4 sub-ASIDs to translate the PA address into the actual VA. By default all clients are limited to a single ASID and upstream kernel doesn't support programming of 34bit VAs. So doesn't worth the effort to fully translate the VA, IMO. >> Even if it supported more than 32bit, then the returned ulong is 32bit, >> which doesn't make sense. > > On ARM64 (Tegra210), isn't ulong 64-bit? Yes, indeed.
WARNING: multiple messages have this Message-ID (diff)
From: Dmitry Osipenko <digetx@gmail.com> To: Nicolin Chen <nicoleotsuka@gmail.com> Cc: linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org, jonathanh@nvidia.com, thierry.reding@gmail.com, linux-tegra@vger.kernel.org, will@kernel.org Subject: Re: [PATCH v6 6/6] iommu/tegra-smmu: Add pagetable mappings to debugfs Date: Wed, 15 Sep 2021 15:09:48 +0300 [thread overview] Message-ID: <a5a77169-8711-2983-d2cb-4b94061741b9@gmail.com> (raw) In-Reply-To: <20210915043806.GA19185@Asurada-Nvidia> 15.09.2021 07:38, Nicolin Chen пишет: > On Tue, Sep 14, 2021 at 10:20:30PM +0300, Dmitry Osipenko wrote: >> 14.09.2021 21:49, Nicolin Chen пишет: >>> On Tue, Sep 14, 2021 at 04:29:15PM +0300, Dmitry Osipenko wrote: >>>> 14.09.2021 04:38, Nicolin Chen пишет: >>>>> +static unsigned long pd_pt_index_iova(unsigned int pd_index, unsigned int pt_index) >>>>> +{ >>>>> + return ((dma_addr_t)pd_index & (SMMU_NUM_PDE - 1)) << SMMU_PDE_SHIFT | >>>>> + ((dma_addr_t)pt_index & (SMMU_NUM_PTE - 1)) << SMMU_PTE_SHIFT; >>>>> +} >>>> >>>> We know that IOVA is fixed to u32 for this controller. Can we avoid all >>>> these dma_addr_t castings? It should make code cleaner a tad, IMO. >>> >>> Tegra210 actually supports 34-bit IOVA... >>> >> >> It doesn't. 34-bit is PA, 32-bit is VA. >> >> Quote from T210 TRM: >> >> "The SMMU is a centralized virtual-to-physical translation for MSS. It >> maps a 32-bit virtual address to a 34-bit physical address. If the >> client address is 40 bits then bits 39:32 are ignored." > > If you scroll down by a couple of sections, you can see 34-bit > virtual addresses in section 18.6.1.2; and if checking one ASID > register, you can see it mention the extra two bits va[33:32]. Thanks for the pointer. It says that only certain memory clients allow to combine 4 ASIDs to form 34bit VA space. In this case the PA space is split into 4GB areas and there are additional bitfields which configure the ASID mapping of each 4GB area. Still each ASID is 32bit. This is what TRM says: "For the GPU and other clients with 34-bit address interfaces, the ASID registers are extended to point to four ASIDs. The SMMU supports 4GB of virtual address space per ASID, so mapping addr[33:32] into ASID[1:0] extends the virtual address space of a client to 16GB." > However, the driver currently sets its geometry.aperture_end to > 32-bit, and we can only get 32-bit IOVAs using PDE and PTE only, > so I think it should be safe to remove the castings here. I'll > wait for a couple of days and see if there'd be other comments > for me to address in next version. You will need to read the special "ASID Assignment Register" which supports 4 sub-ASIDs to translate the PA address into the actual VA. By default all clients are limited to a single ASID and upstream kernel doesn't support programming of 34bit VAs. So doesn't worth the effort to fully translate the VA, IMO. >> Even if it supported more than 32bit, then the returned ulong is 32bit, >> which doesn't make sense. > > On ARM64 (Tegra210), isn't ulong 64-bit? Yes, indeed. _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2021-09-15 12:09 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-14 1:38 [PATCH v6 0/6] iommu/tegra-smmu: Add pagetable mappings to debugfs Nicolin Chen 2021-09-14 1:38 ` Nicolin Chen 2021-09-14 1:38 ` [PATCH v6 1/6] iommu/tegra-smmu: Rename struct iommu_group *group to *grp Nicolin Chen 2021-09-14 1:38 ` Nicolin Chen 2021-10-07 16:43 ` Thierry Reding 2021-10-07 16:43 ` Thierry Reding 2021-09-14 1:38 ` [PATCH v6 2/6] iommu/tegra-smmu: Rename struct tegra_smmu_group_soc *soc to *group_soc Nicolin Chen 2021-09-14 1:38 ` Nicolin Chen 2021-10-07 16:50 ` Thierry Reding 2021-10-07 16:50 ` Thierry Reding 2021-10-07 20:14 ` Nicolin Chen 2021-10-07 20:14 ` Nicolin Chen 2021-09-14 1:38 ` [PATCH v6 3/6] iommu/tegra-smmu: Rename struct tegra_smmu_swgroup *group to *swgrp Nicolin Chen 2021-09-14 1:38 ` Nicolin Chen 2021-10-07 16:57 ` Thierry Reding 2021-10-07 16:57 ` Thierry Reding 2021-10-07 20:29 ` Nicolin Chen 2021-10-07 20:29 ` Nicolin Chen 2021-09-14 1:38 ` [PATCH v6 4/6] iommu/tegra-smmu: Use swgrp pointer instead of swgroup id Nicolin Chen 2021-09-14 1:38 ` Nicolin Chen 2021-10-07 16:59 ` Thierry Reding 2021-10-07 16:59 ` Thierry Reding 2021-09-14 1:38 ` [PATCH v6 5/6] iommu/tegra-smmu: Attach as pointer to tegra_smmu_group Nicolin Chen 2021-09-14 1:38 ` Nicolin Chen 2021-10-07 17:02 ` Thierry Reding 2021-10-07 17:02 ` Thierry Reding 2021-09-14 1:38 ` [PATCH v6 6/6] iommu/tegra-smmu: Add pagetable mappings to debugfs Nicolin Chen 2021-09-14 1:38 ` Nicolin Chen 2021-09-14 13:29 ` Dmitry Osipenko 2021-09-14 13:29 ` Dmitry Osipenko 2021-09-14 18:49 ` Nicolin Chen 2021-09-14 18:49 ` Nicolin Chen 2021-09-14 19:20 ` Dmitry Osipenko 2021-09-14 19:20 ` Dmitry Osipenko 2021-09-15 4:38 ` Nicolin Chen 2021-09-15 4:38 ` Nicolin Chen 2021-09-15 12:09 ` Dmitry Osipenko [this message] 2021-09-15 12:09 ` Dmitry Osipenko 2021-09-15 12:18 ` Dmitry Osipenko 2021-09-15 12:18 ` Dmitry Osipenko 2021-09-15 22:19 ` Nicolin Chen 2021-09-15 22:19 ` Nicolin Chen 2021-10-07 17:13 ` Thierry Reding 2021-10-07 17:13 ` Thierry Reding 2021-10-07 20:41 ` Nicolin Chen 2021-10-07 20:41 ` Nicolin Chen
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