* [PATCH 0/7] arm64: zynqmp: Add support for existing Xilinx ZynqMP based boards
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree
Cc: monstr, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel
Hi,
This patchset is adding all current existing Xilinx ZynqMP boards.
zcu* boards are customer boards. zc1* are mainly Xilinx internal boards
but some of them have been shared with customers. zc1751 is unique in
this set because it is based board with FMC card for silicon/hard IP
validation.
All boards are using the same default clock configuration till clock
driver is merged to mainline. Some boards also contain other components
which are not described because mainline driver haven't been merged yet.
For example nand, qspi, pinctrl and phy.
Please let me know if you see any issue with these boards.
Thanks,
Michal
Michal Simek (7):
arm64: zynqmp: Add support for Xilinx zcu100-revC
arm64: zynqmp: Add support for Xilinx zcu102
arm64: zynqmp: Add support for Xilinx zcu104-revA
arm64: zynqmp: Add support for Xilinx zcu106-revA
arm64: zynqmp: Add support for Xilinx zcu111-revA
arm64: zynqmp: Add support for Xilinx zc12XX boards
arm64: zynqmp: Add support for Xilinx zc1751
arch/arm64/boot/dts/xilinx/Makefile | 15 +
arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 54 ++
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 42 ++
arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 42 ++
.../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 133 +++++
.../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 170 +++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 153 ++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 181 +++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 126 +++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 298 +++++++++++
.../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 197 ++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 530 ++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 446 +++++++++++++++++
17 files changed, 3234 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 0/7] arm64: zynqmp: Add support for existing Xilinx ZynqMP based boards
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: monstr-pSz03upnqPeHXe+LvDLADg, Masahiro Yamada,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, Will Deacon,
Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi,
This patchset is adding all current existing Xilinx ZynqMP boards.
zcu* boards are customer boards. zc1* are mainly Xilinx internal boards
but some of them have been shared with customers. zc1751 is unique in
this set because it is based board with FMC card for silicon/hard IP
validation.
All boards are using the same default clock configuration till clock
driver is merged to mainline. Some boards also contain other components
which are not described because mainline driver haven't been merged yet.
For example nand, qspi, pinctrl and phy.
Please let me know if you see any issue with these boards.
Thanks,
Michal
Michal Simek (7):
arm64: zynqmp: Add support for Xilinx zcu100-revC
arm64: zynqmp: Add support for Xilinx zcu102
arm64: zynqmp: Add support for Xilinx zcu104-revA
arm64: zynqmp: Add support for Xilinx zcu106-revA
arm64: zynqmp: Add support for Xilinx zcu111-revA
arm64: zynqmp: Add support for Xilinx zc12XX boards
arm64: zynqmp: Add support for Xilinx zc1751
arch/arm64/boot/dts/xilinx/Makefile | 15 +
arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 54 ++
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 42 ++
arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 42 ++
.../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 133 +++++
.../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 170 +++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 153 ++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 181 +++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 126 +++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 298 +++++++++++
.../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 197 ++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 530 ++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 446 +++++++++++++++++
17 files changed, 3234 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
--
1.9.1
--
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^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 0/7] arm64: zynqmp: Add support for existing Xilinx ZynqMP based boards
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This patchset is adding all current existing Xilinx ZynqMP boards.
zcu* boards are customer boards. zc1* are mainly Xilinx internal boards
but some of them have been shared with customers. zc1751 is unique in
this set because it is based board with FMC card for silicon/hard IP
validation.
All boards are using the same default clock configuration till clock
driver is merged to mainline. Some boards also contain other components
which are not described because mainline driver haven't been merged yet.
For example nand, qspi, pinctrl and phy.
Please let me know if you see any issue with these boards.
Thanks,
Michal
Michal Simek (7):
arm64: zynqmp: Add support for Xilinx zcu100-revC
arm64: zynqmp: Add support for Xilinx zcu102
arm64: zynqmp: Add support for Xilinx zcu104-revA
arm64: zynqmp: Add support for Xilinx zcu106-revA
arm64: zynqmp: Add support for Xilinx zcu111-revA
arm64: zynqmp: Add support for Xilinx zc12XX boards
arm64: zynqmp: Add support for Xilinx zc1751
arch/arm64/boot/dts/xilinx/Makefile | 15 +
arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 54 ++
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 42 ++
arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 42 ++
.../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 133 +++++
.../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 170 +++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 153 ++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 181 +++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 126 +++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 298 +++++++++++
.../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 197 ++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 530 ++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 446 +++++++++++++++++
17 files changed, 3234 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
--
1.9.1
^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 1/7] arm64: zynqmp: Add support for Xilinx zcu100-revC
2018-01-19 12:55 ` Michal Simek
@ 2018-01-19 12:55 ` Michal Simek
-1 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree
Cc: monstr, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel
This board has 2GB of memory, i2c, sd, wifi sdio, spis, uarts, display
port and usbs.
Board is using fixed clocks because clock driver hasn't been merged yet.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 298 ++++++++++++++++++++++
3 files changed, 512 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index eba179b23b17..7266a6a9c0cd 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
new file mode 100644
index 000000000000..9c09baca7dd7
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/ {
+ clk100: clk100 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk125: clk125 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk200: clk200 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ clk250: clk250 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ clk300: clk300 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <300000000>;
+ };
+
+ clk600: clk600 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ };
+
+ dp_aclk: clock0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-accuracy = <100>;
+ };
+
+ dp_aud_clk: clock1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ clock-accuracy = <100>;
+ };
+
+ dpdma_clk: dpdma_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <533000000>;
+ };
+
+ drm_clock: drm_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <262750000>;
+ clock-accuracy = <0x64>;
+ };
+};
+
+&can0 {
+ clocks = <&clk100 &clk100>;
+};
+
+&can1 {
+ clocks = <&clk100 &clk100>;
+};
+
+&fpd_dma_chan1 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan2 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan3 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan4 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan5 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan6 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan7 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan8 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan1 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan2 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan3 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan4 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan5 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan6 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan7 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan8 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&gem0 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem1 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem2 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem3 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gpio {
+ clocks = <&clk100>;
+};
+
+&i2c0 {
+ clocks = <&clk100>;
+};
+
+&i2c1 {
+ clocks = <&clk100>;
+};
+
+&sata {
+ clocks = <&clk250>;
+};
+
+&sdhci0 {
+ clocks = <&clk200 &clk200>;
+};
+
+&sdhci1 {
+ clocks = <&clk200 &clk200>;
+};
+
+&spi0 {
+ clocks = <&clk200 &clk200>;
+};
+
+&spi1 {
+ clocks = <&clk200 &clk200>;
+};
+
+&uart0 {
+ clocks = <&clk100 &clk100>;
+};
+
+&uart1 {
+ clocks = <&clk100 &clk100>;
+};
+
+&usb0 {
+ clocks = <&clk250>, <&clk250>;
+};
+
+&usb1 {
+ clocks = <&clk250>, <&clk250>;
+};
+
+&watchdog0 {
+ clocks = <&clk250>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
new file mode 100644
index 000000000000..01f5f95806d3
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU100 revC
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Nathalie Chan King Choy <nathalie@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU100 RevC";
+ compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
+
+ aliases {
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ rtc0 = &rtc;
+ serial0 = &uart1;
+ serial1 = &uart0;
+ serial2 = &dcc;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw4 {
+ label = "sw4";
+ gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ ds2 {
+ label = "ds2";
+ gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ ds3 {
+ label = "ds3";
+ gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx"; /* WLAN tx */
+ default-state = "off";
+ };
+
+ ds4 {
+ label = "ds4";
+ gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0rx"; /* WLAN rx */
+ default-state = "off";
+ };
+
+ ds5 {
+ label = "ds5";
+ gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ };
+
+ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
+ label = "vbus_det";
+ gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ bt_power {
+ label = "bt_power";
+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ wmmcsdio_fixed: fixedregulator-mmcsdio {
+ compatible = "regulator-fixed";
+ regulator-name = "wmmcsdio_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sdio_pwrseq: sdio_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
+ "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
+ "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
+ "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
+ "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
+ "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
+ "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
+ "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
+ "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
+ "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
+ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
+ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
+ "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
+ "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+ i2cswitch@75 { /* u11 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2csw_0: i2c@0 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * LSEXP_I2C0
+ */
+ };
+ i2csw_1: i2c@1 { /* i2c mw 75 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /*
+ * LSEXP_I2C1
+ */
+ };
+ i2csw_2: i2c@2 { /* i2c mw 75 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /*
+ * HSEXP_I2C2
+ */
+ };
+ i2csw_3: i2c@3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /*
+ * HSEXP_I2C3
+ */
+ };
+ i2csw_4: i2c@4 { /* i2c mw 75 0 10 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ pmic: tps65086x@5e { /* Custom TI PMIC u33 */
+ compatible = "ti,tps65086";
+ reg = <0x5e>;
+ interrupt-parent = <&gpio>;
+ interrupts = <77 GPIO_ACTIVE_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+ i2csw_5: i2c@5 { /* i2c mw 75 0 20 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* PS_PMBUS */
+ ina226@40 { /* u35 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <10000>;
+ /* MIO31 is alert which should be routed to PMUFW */
+ };
+ };
+ i2csw_6: i2c@6 { /* i2c mw 75 0 40 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /*
+ * Not Connected
+ */
+ };
+ i2csw_7: i2c@7 { /* i2c mw 75 0 80 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /*
+ * usb5744 (DNP) - U5
+ * 100kHz - this is default freq for us
+ */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+/* SD0 only supports 3.3V, no level shifter */
+&sdhci0 {
+ status = "okay";
+ no-1-8-v;
+ broken-cd; /* CD has to be enabled by default */
+ disable-wp;
+};
+
+&sdhci1 {
+ status = "okay";
+ bus-width = <0x4>;
+ non-removable;
+ disable-wp;
+ cap-power-off-card;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vqmmc-supply = <&wmmcsdio_fixed>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1831";
+ reg = <2>;
+ interrupt-parent = <&gpio>;
+ interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
+ };
+};
+
+&spi0 { /* Low Speed connector */
+ status = "okay";
+};
+
+&spi1 { /* High Speed connector */
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 1/7] arm64: zynqmp: Add support for Xilinx zcu100-revC
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: linux-arm-kernel
This board has 2GB of memory, i2c, sd, wifi sdio, spis, uarts, display
port and usbs.
Board is using fixed clocks because clock driver hasn't been merged yet.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 298 ++++++++++++++++++++++
3 files changed, 512 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index eba179b23b17..7266a6a9c0cd 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
new file mode 100644
index 000000000000..9c09baca7dd7
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Clock specification for Xilinx ZynqMP
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/ {
+ clk100: clk100 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ clk125: clk125 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ clk200: clk200 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ clk250: clk250 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <250000000>;
+ };
+
+ clk300: clk300 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <300000000>;
+ };
+
+ clk600: clk600 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ };
+
+ dp_aclk: clock0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-accuracy = <100>;
+ };
+
+ dp_aud_clk: clock1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ clock-accuracy = <100>;
+ };
+
+ dpdma_clk: dpdma_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <533000000>;
+ };
+
+ drm_clock: drm_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0x0>;
+ clock-frequency = <262750000>;
+ clock-accuracy = <0x64>;
+ };
+};
+
+&can0 {
+ clocks = <&clk100 &clk100>;
+};
+
+&can1 {
+ clocks = <&clk100 &clk100>;
+};
+
+&fpd_dma_chan1 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan2 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan3 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan4 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan5 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan6 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan7 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&fpd_dma_chan8 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan1 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan2 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan3 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan4 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan5 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan6 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan7 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan8 {
+ clocks = <&clk600>, <&clk100>;
+};
+
+&gem0 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem1 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem2 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gem3 {
+ clocks = <&clk125>, <&clk125>, <&clk125>;
+};
+
+&gpio {
+ clocks = <&clk100>;
+};
+
+&i2c0 {
+ clocks = <&clk100>;
+};
+
+&i2c1 {
+ clocks = <&clk100>;
+};
+
+&sata {
+ clocks = <&clk250>;
+};
+
+&sdhci0 {
+ clocks = <&clk200 &clk200>;
+};
+
+&sdhci1 {
+ clocks = <&clk200 &clk200>;
+};
+
+&spi0 {
+ clocks = <&clk200 &clk200>;
+};
+
+&spi1 {
+ clocks = <&clk200 &clk200>;
+};
+
+&uart0 {
+ clocks = <&clk100 &clk100>;
+};
+
+&uart1 {
+ clocks = <&clk100 &clk100>;
+};
+
+&usb0 {
+ clocks = <&clk250>, <&clk250>;
+};
+
+&usb1 {
+ clocks = <&clk250>, <&clk250>;
+};
+
+&watchdog0 {
+ clocks = <&clk250>;
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
new file mode 100644
index 000000000000..01f5f95806d3
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU100 revC
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Nathalie Chan King Choy <nathalie@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU100 RevC";
+ compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
+
+ aliases {
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ rtc0 = &rtc;
+ serial0 = &uart1;
+ serial1 = &uart0;
+ serial2 = &dcc;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw4 {
+ label = "sw4";
+ gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ ds2 {
+ label = "ds2";
+ gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ ds3 {
+ label = "ds3";
+ gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0tx"; /* WLAN tx */
+ default-state = "off";
+ };
+
+ ds4 {
+ label = "ds4";
+ gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "phy0rx"; /* WLAN rx */
+ default-state = "off";
+ };
+
+ ds5 {
+ label = "ds5";
+ gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "bluetooth-power";
+ };
+
+ vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
+ label = "vbus_det";
+ gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ bt_power {
+ label = "bt_power";
+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ wmmcsdio_fixed: fixedregulator-mmcsdio {
+ compatible = "regulator-fixed";
+ regulator-name = "wmmcsdio_fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ sdio_pwrseq: sdio_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
+ "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
+ "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
+ "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
+ "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
+ "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
+ "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
+ "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
+ "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
+ "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
+ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
+ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
+ "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
+ "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "", "", "",
+ "", "", "", "";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+ i2cswitch at 75 { /* u11 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2csw_0: i2c at 0 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * LSEXP_I2C0
+ */
+ };
+ i2csw_1: i2c at 1 { /* i2c mw 75 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /*
+ * LSEXP_I2C1
+ */
+ };
+ i2csw_2: i2c at 2 { /* i2c mw 75 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /*
+ * HSEXP_I2C2
+ */
+ };
+ i2csw_3: i2c at 3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /*
+ * HSEXP_I2C3
+ */
+ };
+ i2csw_4: i2c at 4 { /* i2c mw 75 0 10 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4>;
+
+ pmic: tps65086x at 5e { /* Custom TI PMIC u33 */
+ compatible = "ti,tps65086";
+ reg = <0x5e>;
+ interrupt-parent = <&gpio>;
+ interrupts = <77 GPIO_ACTIVE_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+ };
+ i2csw_5: i2c at 5 { /* i2c mw 75 0 20 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* PS_PMBUS */
+ ina226 at 40 { /* u35 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <10000>;
+ /* MIO31 is alert which should be routed to PMUFW */
+ };
+ };
+ i2csw_6: i2c at 6 { /* i2c mw 75 0 40 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /*
+ * Not Connected
+ */
+ };
+ i2csw_7: i2c at 7 { /* i2c mw 75 0 80 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /*
+ * usb5744 (DNP) - U5
+ * 100kHz - this is default freq for us
+ */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+/* SD0 only supports 3.3V, no level shifter */
+&sdhci0 {
+ status = "okay";
+ no-1-8-v;
+ broken-cd; /* CD has to be enabled by default */
+ disable-wp;
+};
+
+&sdhci1 {
+ status = "okay";
+ bus-width = <0x4>;
+ non-removable;
+ disable-wp;
+ cap-power-off-card;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vqmmc-supply = <&wmmcsdio_fixed>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wlcore: wlcore at 2 {
+ compatible = "ti,wl1831";
+ reg = <2>;
+ interrupt-parent = <&gpio>;
+ interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
+ };
+};
+
+&spi0 { /* Low Speed connector */
+ status = "okay";
+};
+
+&spi1 { /* High Speed connector */
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102
2018-01-19 12:55 ` Michal Simek
@ 2018-01-19 12:55 ` Michal Simek
-1 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree
Cc: monstr, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel
This patch is adding revA, revB and rev1.0. There are also other
revisions between which should be backward compatible with previous
versions. Unfortunately all revs are still in use.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 3 +
.../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
4 files changed, 637 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 7266a6a9c0cd..24e3ce801304 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1,3 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
new file mode 100644
index 000000000000..4b7477795fbd
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 Rev1.0
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-zcu102-revB.dts"
+
+/ {
+ model = "ZynqMP ZCU102 Rev1.0";
+ compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+};
+
+&eeprom {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ board_sn: board_sn@0 {
+ reg = <0x0 0x14>;
+ };
+
+ eth_mac: eth_mac@20 {
+ reg = <0x20 0x6>;
+ };
+
+ board_name: board_name@d0 {
+ reg = <0xd0 0x6>;
+ };
+
+ board_revision: board_revision@e0 {
+ reg = <0xe0 0x3>;
+ };
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
new file mode 100644
index 000000000000..6a15aacf65ef
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -0,0 +1,556 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 RevA
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU102 RevA";
+ compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@21 {
+ reg = <21>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u97: gpio@20 {
+ /*
+ * Enable all GTs to out from U-Boot
+ * i2c mw 20 6 0 - setup IO to output
+ * i2c mw 20 2 ef - setup output values on pins 0-7
+ * i2c mw 20 3 ff - setup output values on pins 10-17
+ */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - PS_GTR_LAN_SEL0
+ * 1 - PS_GTR_LAN_SEL1
+ * 2 - PS_GTR_LAN_SEL2
+ * 3 - PS_GTR_LAN_SEL3
+ * 4 - PCI_CLK_DIR_SEL
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 7, 10 - 17 - not connected
+ */
+
+ gtr_sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ output-low; /* PCIE = 0, DP = 1 */
+ line-name = "sel0";
+ };
+ gtr_sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ output-high; /* PCIE = 0, DP = 1 */
+ line-name = "sel1";
+ };
+ gtr_sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ output-high; /* PCIE = 0, USB0 = 1 */
+ line-name = "sel2";
+ };
+ gtr_sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ output-high; /* PCIE = 0, SATA = 1 */
+ line-name = "sel3";
+ };
+ };
+
+ tca6416_u61: gpio@21 { /* enable it by i2c mw 21 6 0 */
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - VCCPSPLL_EN
+ * 1 - MGTRAVCC_EN
+ * 2 - MGTRAVTT_EN
+ * 3 - VCCPSDDRPLL_EN
+ * 4 - MIO26_PMU_INPUT_LS
+ * 5 - PL_PMBUS_ALERT
+ * 6 - PS_PMBUS_ALERT
+ * 7 - MAXIM_PMBUS_ALERT
+ * 10 - PL_DDR4_VTERM_EN
+ * 11 - PL_DDR4_VPP_2V5_EN
+ * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+ * 13 - PS_DIMM_SUSPEND_EN
+ * 14 - PS_DDR4_VTERM_EN
+ * 15 - PS_DDR4_VPP_2V5_EN
+ * 16 - 17 - not connected
+ */
+ };
+
+ i2cswitch@75 { /* u60 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ ina226@40 { /* u76 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ ina226@41 { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u78 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u87 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u85 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u86 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u93 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u88 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4a { /* u15 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4b { /* u92 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* PL_PMBUS */
+ ina226@40 { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226@41 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u80 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u16 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u74 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u75 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* MAXIM_PMBUS - 00 */
+ max15301@a { /* u46 */
+ compatible = "maxim,max15301";
+ reg = <0xa>;
+ };
+ max15303@b { /* u4 */
+ compatible = "maxim,max15303";
+ reg = <0xb>;
+ };
+ max15303@10 { /* u13 */
+ compatible = "maxim,max15303";
+ reg = <0x10>;
+ };
+ max15301@13 { /* u47 */
+ compatible = "maxim,max15301";
+ reg = <0x13>;
+ };
+ max15303@14 { /* u7 */
+ compatible = "maxim,max15303";
+ reg = <0x14>;
+ };
+ max15303@15 { /* u6 */
+ compatible = "maxim,max15303";
+ reg = <0x15>;
+ };
+ max15303@16 { /* u10 */
+ compatible = "maxim,max15303";
+ reg = <0x16>;
+ };
+ max15303@17 { /* u9 */
+ compatible = "maxim,max15303";
+ reg = <0x17>;
+ };
+ max15301@18 { /* u63 */
+ compatible = "maxim,max15301";
+ reg = <0x18>;
+ };
+ max15303@1a { /* u49 */
+ compatible = "maxim,max15303";
+ reg = <0x1a>;
+ };
+ max15303@1d { /* u18 */
+ compatible = "maxim,max15303";
+ reg = <0x1d>;
+ };
+ max15303@20 { /* u8 */
+ compatible = "maxim,max15303";
+ status = "disabled"; /* unreachable */
+ reg = <0x20>;
+ };
+
+ max20751@72 { /* u95 */
+ compatible = "maxim,max20751";
+ reg = <0x72>;
+ };
+ max20751@73 { /* u96 */
+ compatible = "maxim,max20751";
+ reg = <0x73>;
+ };
+ };
+ /* Bus 3 is not connected */
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* PL i2c via PCA9306 - u45 */
+ i2cswitch@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 { /* i2c mw 74 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c@1 { /* i2c mw 74 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator1@36 { /* SI5341 - u69 */
+ reg = <0x36>;
+ };
+
+ };
+ i2c@2 { /* i2c mw 74 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator2@5d { /* USER SI570 - u42 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c@3 { /* i2c mw 74 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>; /* copy from zc702 */
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c@4 { /* i2c mw 74 0 10 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator4@69 {/* SI5328 - u20 */
+ reg = <0x69>;
+ /*
+ * Chip has interrupt present connected to PL
+ * interrupt-parent = <&>;
+ * interrupts = <>;
+ */
+ };
+ };
+ /* 5 - 7 unconnected */
+ };
+
+ i2cswitch@75 {
+ compatible = "nxp,pca9548"; /* u135 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* HPC0_IIC */
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* HPC1_IIC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SEP 3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SEP 2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SEP 1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SEP 0 */
+ };
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
new file mode 100644
index 000000000000..ed3cc684931f
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 RevB
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-zcu102-revA.dts"
+
+/ {
+ model = "ZynqMP ZCU102 RevB";
+ compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+};
+
+&gem3 {
+ phy-handle = <&phyc>;
+ phyc: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+ /* Cleanup from RevA */
+ /delete-node/ phy@21;
+};
+
+/* Different qspi 512Mbit version */
+
+/* Fix collision with u61 */
+&i2c0 {
+ i2cswitch@75 {
+ i2c@2 {
+ max15303@1b { /* u8 */
+ compatible = "maxim,max15303";
+ reg = <0x1b>;
+ };
+ /delete-node/ max15303@20;
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: linux-arm-kernel
This patch is adding revA, revB and rev1.0. There are also other
revisions between which should be backward compatible with previous
versions. Unfortunately all revs are still in use.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 3 +
.../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
4 files changed, 637 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 7266a6a9c0cd..24e3ce801304 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1,3 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
new file mode 100644
index 000000000000..4b7477795fbd
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 Rev1.0
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-zcu102-revB.dts"
+
+/ {
+ model = "ZynqMP ZCU102 Rev1.0";
+ compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+};
+
+&eeprom {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ board_sn: board_sn at 0 {
+ reg = <0x0 0x14>;
+ };
+
+ eth_mac: eth_mac at 20 {
+ reg = <0x20 0x6>;
+ };
+
+ board_name: board_name at d0 {
+ reg = <0xd0 0x6>;
+ };
+
+ board_revision: board_revision at e0 {
+ reg = <0xe0 0x3>;
+ };
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
new file mode 100644
index 000000000000..6a15aacf65ef
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
@@ -0,0 +1,556 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 RevA
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU102 RevA";
+ compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy at 21 {
+ reg = <21>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u97: gpio at 20 {
+ /*
+ * Enable all GTs to out from U-Boot
+ * i2c mw 20 6 0 - setup IO to output
+ * i2c mw 20 2 ef - setup output values on pins 0-7
+ * i2c mw 20 3 ff - setup output values on pins 10-17
+ */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - PS_GTR_LAN_SEL0
+ * 1 - PS_GTR_LAN_SEL1
+ * 2 - PS_GTR_LAN_SEL2
+ * 3 - PS_GTR_LAN_SEL3
+ * 4 - PCI_CLK_DIR_SEL
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 7, 10 - 17 - not connected
+ */
+
+ gtr_sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ output-low; /* PCIE = 0, DP = 1 */
+ line-name = "sel0";
+ };
+ gtr_sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ output-high; /* PCIE = 0, DP = 1 */
+ line-name = "sel1";
+ };
+ gtr_sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ output-high; /* PCIE = 0, USB0 = 1 */
+ line-name = "sel2";
+ };
+ gtr_sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ output-high; /* PCIE = 0, SATA = 1 */
+ line-name = "sel3";
+ };
+ };
+
+ tca6416_u61: gpio at 21 { /* enable it by i2c mw 21 6 0 */
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - VCCPSPLL_EN
+ * 1 - MGTRAVCC_EN
+ * 2 - MGTRAVTT_EN
+ * 3 - VCCPSDDRPLL_EN
+ * 4 - MIO26_PMU_INPUT_LS
+ * 5 - PL_PMBUS_ALERT
+ * 6 - PS_PMBUS_ALERT
+ * 7 - MAXIM_PMBUS_ALERT
+ * 10 - PL_DDR4_VTERM_EN
+ * 11 - PL_DDR4_VPP_2V5_EN
+ * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+ * 13 - PS_DIMM_SUSPEND_EN
+ * 14 - PS_DDR4_VTERM_EN
+ * 15 - PS_DDR4_VPP_2V5_EN
+ * 16 - 17 - not connected
+ */
+ };
+
+ i2cswitch at 75 { /* u60 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c at 0 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ ina226 at 40 { /* u76 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 41 { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 42 { /* u78 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 43 { /* u87 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 44 { /* u85 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 45 { /* u86 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 46 { /* u93 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 47 { /* u88 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 4a { /* u15 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 4b { /* u92 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c at 1 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* PL_PMBUS */
+ ina226 at 40 { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226 at 41 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 42 { /* u80 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 43 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 44 { /* u16 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 45 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 46 { /* u74 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 47 { /* u75 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c at 2 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* MAXIM_PMBUS - 00 */
+ max15301 at a { /* u46 */
+ compatible = "maxim,max15301";
+ reg = <0xa>;
+ };
+ max15303 at b { /* u4 */
+ compatible = "maxim,max15303";
+ reg = <0xb>;
+ };
+ max15303 at 10 { /* u13 */
+ compatible = "maxim,max15303";
+ reg = <0x10>;
+ };
+ max15301 at 13 { /* u47 */
+ compatible = "maxim,max15301";
+ reg = <0x13>;
+ };
+ max15303 at 14 { /* u7 */
+ compatible = "maxim,max15303";
+ reg = <0x14>;
+ };
+ max15303 at 15 { /* u6 */
+ compatible = "maxim,max15303";
+ reg = <0x15>;
+ };
+ max15303 at 16 { /* u10 */
+ compatible = "maxim,max15303";
+ reg = <0x16>;
+ };
+ max15303 at 17 { /* u9 */
+ compatible = "maxim,max15303";
+ reg = <0x17>;
+ };
+ max15301 at 18 { /* u63 */
+ compatible = "maxim,max15301";
+ reg = <0x18>;
+ };
+ max15303 at 1a { /* u49 */
+ compatible = "maxim,max15303";
+ reg = <0x1a>;
+ };
+ max15303 at 1d { /* u18 */
+ compatible = "maxim,max15303";
+ reg = <0x1d>;
+ };
+ max15303 at 20 { /* u8 */
+ compatible = "maxim,max15303";
+ status = "disabled"; /* unreachable */
+ reg = <0x20>;
+ };
+
+ max20751 at 72 { /* u95 */
+ compatible = "maxim,max20751";
+ reg = <0x72>;
+ };
+ max20751 at 73 { /* u96 */
+ compatible = "maxim,max20751";
+ reg = <0x73>;
+ };
+ };
+ /* Bus 3 is not connected */
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* PL i2c via PCA9306 - u45 */
+ i2cswitch at 74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c at 0 { /* i2c mw 74 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom at 54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c at 1 { /* i2c mw 74 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator1 at 36 { /* SI5341 - u69 */
+ reg = <0x36>;
+ };
+
+ };
+ i2c at 2 { /* i2c mw 74 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator2 at 5d { /* USER SI570 - u42 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c at 3 { /* i2c mw 74 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator3 at 5d { /* USER MGT SI570 - u56 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>; /* copy from zc702 */
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c at 4 { /* i2c mw 74 0 10 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator4 at 69 {/* SI5328 - u20 */
+ reg = <0x69>;
+ /*
+ * Chip has interrupt present connected to PL
+ * interrupt-parent = <&>;
+ * interrupts = <>;
+ */
+ };
+ };
+ /* 5 - 7 unconnected */
+ };
+
+ i2cswitch at 75 {
+ compatible = "nxp,pca9548"; /* u135 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* HPC0_IIC */
+ };
+ i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* HPC1_IIC */
+ };
+ i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c at 3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SEP 3 */
+ };
+ i2c at 5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SEP 2 */
+ };
+ i2c at 6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SEP 1 */
+ };
+ i2c at 7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SEP 0 */
+ };
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
new file mode 100644
index 000000000000..ed3cc684931f
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 RevB
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-zcu102-revA.dts"
+
+/ {
+ model = "ZynqMP ZCU102 RevB";
+ compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+};
+
+&gem3 {
+ phy-handle = <&phyc>;
+ phyc: phy at c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+ /* Cleanup from RevA */
+ /delete-node/ phy at 21;
+};
+
+/* Different qspi 512Mbit version */
+
+/* Fix collision with u61 */
+&i2c0 {
+ i2cswitch at 75 {
+ i2c at 2 {
+ max15303 at 1b { /* u8 */
+ compatible = "maxim,max15303";
+ reg = <0x1b>;
+ };
+ /delete-node/ max15303 at 20;
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 3/7] arm64: zynqmp: Add support for Xilinx zcu104-revA
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree
Cc: monstr, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel
Xilinx zcu104 is another customer board. It is sort of zcu102 clone
with some differences.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 197 ++++++++++++++++++++++
2 files changed, 198 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 24e3ce801304..1c039e59c7c3 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
new file mode 100644
index 000000000000..705df191b2f0
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU104
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU104 RevA";
+ compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Another connection to this bus via PL i2c via PCA9306 - u45 */
+ i2cswitch@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 { /* i2c mw 74 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ i2c@1 { /* i2c mw 74 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
+ reg = <0x6c>;
+ };
+ };
+
+ i2c@2 { /* i2c mw 74 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
+ reg = <0x43>;
+ };
+ irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
+ reg = <0x4d>;
+ };
+ };
+
+ i2c@4 { /* i2c mw 74 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ tca6416_u97: gpio@21 { /* enable it by i2c mw 21 6 0 */
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - IRPS5401_ALERT_B
+ * 1 - HDMI_8T49N241_INT_ALM
+ * 2 - MAX6643_OT_B
+ * 3 - MAX6643_FANFAIL_B
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 7 - FMC_LPC_PRSNT_M2C_B
+ * 4, 10 - 17 - not connected
+ */
+ };
+ };
+
+ i2c@5 { /* i2c mw 74 0 10 */ /* FMC_LPC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ i2c@7 { /* i2c mw 74 0 14 */ /* DDR4_SODIMM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+
+ /* 3, 6 not connected */
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 3/7] arm64: zynqmp: Add support for Xilinx zcu104-revA
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: monstr-pSz03upnqPeHXe+LvDLADg, Masahiro Yamada,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, Will Deacon,
Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Xilinx zcu104 is another customer board. It is sort of zcu102 clone
with some differences.
Signed-off-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 197 ++++++++++++++++++++++
2 files changed, 198 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 24e3ce801304..1c039e59c7c3 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
new file mode 100644
index 000000000000..705df191b2f0
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU104
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU104 RevA";
+ compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Another connection to this bus via PL i2c via PCA9306 - u45 */
+ i2cswitch@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 { /* i2c mw 74 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ i2c@1 { /* i2c mw 74 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
+ reg = <0x6c>;
+ };
+ };
+
+ i2c@2 { /* i2c mw 74 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
+ reg = <0x43>;
+ };
+ irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
+ reg = <0x4d>;
+ };
+ };
+
+ i2c@4 { /* i2c mw 74 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ tca6416_u97: gpio@21 { /* enable it by i2c mw 21 6 0 */
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - IRPS5401_ALERT_B
+ * 1 - HDMI_8T49N241_INT_ALM
+ * 2 - MAX6643_OT_B
+ * 3 - MAX6643_FANFAIL_B
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 7 - FMC_LPC_PRSNT_M2C_B
+ * 4, 10 - 17 - not connected
+ */
+ };
+ };
+
+ i2c@5 { /* i2c mw 74 0 10 */ /* FMC_LPC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ i2c@7 { /* i2c mw 74 0 14 */ /* DDR4_SODIMM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+
+ /* 3, 6 not connected */
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 3/7] arm64: zynqmp: Add support for Xilinx zcu104-revA
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: linux-arm-kernel
Xilinx zcu104 is another customer board. It is sort of zcu102 clone
with some differences.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 197 ++++++++++++++++++++++
2 files changed, 198 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 24e3ce801304..1c039e59c7c3 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
new file mode 100644
index 000000000000..705df191b2f0
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU104
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU104 RevA";
+ compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy at c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Another connection to this bus via PL i2c via PCA9306 - u45 */
+ i2cswitch at 74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c at 0 { /* i2c mw 74 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom at 54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+ i2c at 1 { /* i2c mw 74 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ clock_8t49n287: clock-generator at 6c { /* 8T49N287 - u182 */
+ reg = <0x6c>;
+ };
+ };
+
+ i2c at 2 { /* i2c mw 74 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ irps5401_43: irps54012 at 43 { /* IRPS5401 - u175 */
+ reg = <0x43>;
+ };
+ irps5401_4d: irps54012 at 4d { /* IRPS5401 - u180 */
+ reg = <0x4d>;
+ };
+ };
+
+ i2c at 4 { /* i2c mw 74 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ tca6416_u97: gpio at 21 { /* enable it by i2c mw 21 6 0 */
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - IRPS5401_ALERT_B
+ * 1 - HDMI_8T49N241_INT_ALM
+ * 2 - MAX6643_OT_B
+ * 3 - MAX6643_FANFAIL_B
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 7 - FMC_LPC_PRSNT_M2C_B
+ * 4, 10 - 17 - not connected
+ */
+ };
+ };
+
+ i2c at 5 { /* i2c mw 74 0 10 */ /* FMC_LPC */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ };
+
+ i2c at 7 { /* i2c mw 74 0 14 */ /* DDR4_SODIMM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ };
+
+ /* 3, 6 not connected */
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 4/7] arm64: zynqmp: Add support for Xilinx zcu106-revA
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree
Cc: monstr, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel
Xilinx zcu106 is a customer board. It is reusing some parts from zcu102.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 530 ++++++++++++++++++++++
2 files changed, 531 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 1c039e59c7c3..922c5da39600 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
new file mode 100644
index 000000000000..2676931c3c07
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -0,0 +1,530 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU106
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU106 RevA";
+ compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u97: gpio@20 {
+ /*
+ * Enable all GTs to out from U-Boot
+ * i2c mw 20 6 0 - setup IO to output
+ * i2c mw 20 2 ef - setup output values on pins 0-7
+ * i2c mw 20 3 ff - setup output values on pins 10-17
+ */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - SFP_SI5328_INT_ALM
+ * 1 - HDMI_SI5328_INT_ALM
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 10 - FMC_HPC0_PRSNT_M2C_B
+ * 11 - FMC_HPC1_PRSNT_M2C_B
+ * 2-4, 7, 12-17 - not connected
+ */
+ };
+
+ tca6416_u61: gpio@21 { /* enable it by i2c mw 21 6 0 */
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - VCCPSPLL_EN
+ * 1 - MGTRAVCC_EN
+ * 2 - MGTRAVTT_EN
+ * 3 - VCCPSDDRPLL_EN
+ * 4 - MIO26_PMU_INPUT_LS
+ * 5 - PL_PMBUS_ALERT
+ * 6 - PS_PMBUS_ALERT
+ * 7 - MAXIM_PMBUS_ALERT
+ * 10 - PL_DDR4_VTERM_EN
+ * 11 - PL_DDR4_VPP_2V5_EN
+ * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+ * 13 - PS_DIMM_SUSPEND_EN
+ * 14 - PS_DDR4_VTERM_EN
+ * 15 - PS_DDR4_VPP_2V5_EN
+ * 16 - 17 - not connected
+ */
+ };
+
+ i2cswitch@75 { /* u60 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ ina226@40 { /* u76 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ ina226@41 { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u78 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u87 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u85 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u86 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u93 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u88 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4a { /* u15 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4b { /* u92 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* PL_PMBUS */
+ ina226@40 { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226@41 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u80 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u16 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u74 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u75 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* MAXIM_PMBUS - 00 */
+ max15301@a { /* u46 */
+ compatible = "maxim,max15301";
+ reg = <0xa>;
+ };
+ max15303@b { /* u4 */
+ compatible = "maxim,max15303";
+ reg = <0xb>;
+ };
+ max15303@10 { /* u13 */
+ compatible = "maxim,max15303";
+ reg = <0x10>;
+ };
+ max15301@13 { /* u47 */
+ compatible = "maxim,max15301";
+ reg = <0x13>;
+ };
+ max15303@14 { /* u7 */
+ compatible = "maxim,max15303";
+ reg = <0x14>;
+ };
+ max15303@15 { /* u6 */
+ compatible = "maxim,max15303";
+ reg = <0x15>;
+ };
+ max15303@16 { /* u10 */
+ compatible = "maxim,max15303";
+ reg = <0x16>;
+ };
+ max15303@17 { /* u9 */
+ compatible = "maxim,max15303";
+ reg = <0x17>;
+ };
+ max15301@18 { /* u63 */
+ compatible = "maxim,max15301";
+ reg = <0x18>;
+ };
+ max15303@1a { /* u49 */
+ compatible = "maxim,max15303";
+ reg = <0x1a>;
+ };
+ max15303@1b { /* u8 */
+ compatible = "maxim,max15303";
+ reg = <0x1b>;
+ };
+ max15303@1d { /* u18 */
+ compatible = "maxim,max15303";
+ reg = <0x1d>;
+ };
+
+ max20751@72 { /* u95 */
+ compatible = "maxim,max20751";
+ reg = <0x72>;
+ };
+ max20751@73 { /* u96 */
+ compatible = "maxim,max20751";
+ reg = <0x73>;
+ };
+ };
+ /* Bus 3 is not connected */
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* PL i2c via PCA9306 - u45 */
+ i2cswitch@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 { /* i2c mw 74 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c@1 { /* i2c mw 74 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator1@36 { /* SI5341 - u69 */
+ reg = <0x36>;
+ };
+
+ };
+ i2c@2 { /* i2c mw 74 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator2@5d { /* USER SI570 - u42 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c@3 { /* i2c mw 74 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>; /* copy from zc702 */
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c@4 { /* i2c mw 74 0 10 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator4@69 {/* SI5328 - u20 */
+ reg = <0x69>;
+ };
+ };
+ i2c@5 { /* i2c mw 74 0 11 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>; /* FAN controller */
+ temp@4c {/* lm96163 - u128 */
+ compatible = "national,lm96163";
+ reg = <0x4c>;
+ };
+ };
+ /* 6 - 7 unconnected */
+ };
+
+ i2cswitch@75 {
+ compatible = "nxp,pca9548"; /* u135 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* HPC0_IIC */
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* HPC1_IIC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SEP 3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SEP 2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SEP 1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SEP 0 */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 4/7] arm64: zynqmp: Add support for Xilinx zcu106-revA
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: monstr-pSz03upnqPeHXe+LvDLADg, Masahiro Yamada,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, Will Deacon,
Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Xilinx zcu106 is a customer board. It is reusing some parts from zcu102.
Signed-off-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 530 ++++++++++++++++++++++
2 files changed, 531 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 1c039e59c7c3..922c5da39600 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
new file mode 100644
index 000000000000..2676931c3c07
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -0,0 +1,530 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU106
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU106 RevA";
+ compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u97: gpio@20 {
+ /*
+ * Enable all GTs to out from U-Boot
+ * i2c mw 20 6 0 - setup IO to output
+ * i2c mw 20 2 ef - setup output values on pins 0-7
+ * i2c mw 20 3 ff - setup output values on pins 10-17
+ */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - SFP_SI5328_INT_ALM
+ * 1 - HDMI_SI5328_INT_ALM
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 10 - FMC_HPC0_PRSNT_M2C_B
+ * 11 - FMC_HPC1_PRSNT_M2C_B
+ * 2-4, 7, 12-17 - not connected
+ */
+ };
+
+ tca6416_u61: gpio@21 { /* enable it by i2c mw 21 6 0 */
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - VCCPSPLL_EN
+ * 1 - MGTRAVCC_EN
+ * 2 - MGTRAVTT_EN
+ * 3 - VCCPSDDRPLL_EN
+ * 4 - MIO26_PMU_INPUT_LS
+ * 5 - PL_PMBUS_ALERT
+ * 6 - PS_PMBUS_ALERT
+ * 7 - MAXIM_PMBUS_ALERT
+ * 10 - PL_DDR4_VTERM_EN
+ * 11 - PL_DDR4_VPP_2V5_EN
+ * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+ * 13 - PS_DIMM_SUSPEND_EN
+ * 14 - PS_DDR4_VTERM_EN
+ * 15 - PS_DDR4_VPP_2V5_EN
+ * 16 - 17 - not connected
+ */
+ };
+
+ i2cswitch@75 { /* u60 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ ina226@40 { /* u76 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ ina226@41 { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u78 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u87 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u85 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u86 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u93 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u88 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4a { /* u15 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4b { /* u92 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* PL_PMBUS */
+ ina226@40 { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226@41 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u80 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@44 { /* u16 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u74 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226@47 { /* u75 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* MAXIM_PMBUS - 00 */
+ max15301@a { /* u46 */
+ compatible = "maxim,max15301";
+ reg = <0xa>;
+ };
+ max15303@b { /* u4 */
+ compatible = "maxim,max15303";
+ reg = <0xb>;
+ };
+ max15303@10 { /* u13 */
+ compatible = "maxim,max15303";
+ reg = <0x10>;
+ };
+ max15301@13 { /* u47 */
+ compatible = "maxim,max15301";
+ reg = <0x13>;
+ };
+ max15303@14 { /* u7 */
+ compatible = "maxim,max15303";
+ reg = <0x14>;
+ };
+ max15303@15 { /* u6 */
+ compatible = "maxim,max15303";
+ reg = <0x15>;
+ };
+ max15303@16 { /* u10 */
+ compatible = "maxim,max15303";
+ reg = <0x16>;
+ };
+ max15303@17 { /* u9 */
+ compatible = "maxim,max15303";
+ reg = <0x17>;
+ };
+ max15301@18 { /* u63 */
+ compatible = "maxim,max15301";
+ reg = <0x18>;
+ };
+ max15303@1a { /* u49 */
+ compatible = "maxim,max15303";
+ reg = <0x1a>;
+ };
+ max15303@1b { /* u8 */
+ compatible = "maxim,max15303";
+ reg = <0x1b>;
+ };
+ max15303@1d { /* u18 */
+ compatible = "maxim,max15303";
+ reg = <0x1d>;
+ };
+
+ max20751@72 { /* u95 */
+ compatible = "maxim,max20751";
+ reg = <0x72>;
+ };
+ max20751@73 { /* u96 */
+ compatible = "maxim,max20751";
+ reg = <0x73>;
+ };
+ };
+ /* Bus 3 is not connected */
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* PL i2c via PCA9306 - u45 */
+ i2cswitch@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 { /* i2c mw 74 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c@1 { /* i2c mw 74 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator1@36 { /* SI5341 - u69 */
+ reg = <0x36>;
+ };
+
+ };
+ i2c@2 { /* i2c mw 74 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator2@5d { /* USER SI570 - u42 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c@3 { /* i2c mw 74 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>; /* copy from zc702 */
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c@4 { /* i2c mw 74 0 10 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator4@69 {/* SI5328 - u20 */
+ reg = <0x69>;
+ };
+ };
+ i2c@5 { /* i2c mw 74 0 11 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>; /* FAN controller */
+ temp@4c {/* lm96163 - u128 */
+ compatible = "national,lm96163";
+ reg = <0x4c>;
+ };
+ };
+ /* 6 - 7 unconnected */
+ };
+
+ i2cswitch@75 {
+ compatible = "nxp,pca9548"; /* u135 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* HPC0_IIC */
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* HPC1_IIC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SEP 3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SEP 2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SEP 1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SEP 0 */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 4/7] arm64: zynqmp: Add support for Xilinx zcu106-revA
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: linux-arm-kernel
Xilinx zcu106 is a customer board. It is reusing some parts from zcu102.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 530 ++++++++++++++++++++++
2 files changed, 531 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 1c039e59c7c3..922c5da39600 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
new file mode 100644
index 000000000000..2676931c3c07
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
@@ -0,0 +1,530 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU106
+ *
+ * (C) Copyright 2016, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU106 RevA";
+ compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&dcc {
+ status = "okay";
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy at c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u97: gpio at 20 {
+ /*
+ * Enable all GTs to out from U-Boot
+ * i2c mw 20 6 0 - setup IO to output
+ * i2c mw 20 2 ef - setup output values on pins 0-7
+ * i2c mw 20 3 ff - setup output values on pins 10-17
+ */
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - SFP_SI5328_INT_ALM
+ * 1 - HDMI_SI5328_INT_ALM
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 10 - FMC_HPC0_PRSNT_M2C_B
+ * 11 - FMC_HPC1_PRSNT_M2C_B
+ * 2-4, 7, 12-17 - not connected
+ */
+ };
+
+ tca6416_u61: gpio at 21 { /* enable it by i2c mw 21 6 0 */
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - VCCPSPLL_EN
+ * 1 - MGTRAVCC_EN
+ * 2 - MGTRAVTT_EN
+ * 3 - VCCPSDDRPLL_EN
+ * 4 - MIO26_PMU_INPUT_LS
+ * 5 - PL_PMBUS_ALERT
+ * 6 - PS_PMBUS_ALERT
+ * 7 - MAXIM_PMBUS_ALERT
+ * 10 - PL_DDR4_VTERM_EN
+ * 11 - PL_DDR4_VPP_2V5_EN
+ * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
+ * 13 - PS_DIMM_SUSPEND_EN
+ * 14 - PS_DDR4_VTERM_EN
+ * 15 - PS_DDR4_VPP_2V5_EN
+ * 16 - 17 - not connected
+ */
+ };
+
+ i2cswitch at 75 { /* u60 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c at 0 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ ina226 at 40 { /* u76 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 41 { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 42 { /* u78 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 43 { /* u87 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 44 { /* u85 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 45 { /* u86 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 46 { /* u93 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 47 { /* u88 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 4a { /* u15 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 4b { /* u92 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c at 1 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* PL_PMBUS */
+ ina226 at 40 { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226 at 41 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 42 { /* u80 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 43 { /* u84 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 44 { /* u16 */
+ compatible = "ti,ina226";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 45 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 46 { /* u74 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 47 { /* u75 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c at 2 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* MAXIM_PMBUS - 00 */
+ max15301 at a { /* u46 */
+ compatible = "maxim,max15301";
+ reg = <0xa>;
+ };
+ max15303 at b { /* u4 */
+ compatible = "maxim,max15303";
+ reg = <0xb>;
+ };
+ max15303 at 10 { /* u13 */
+ compatible = "maxim,max15303";
+ reg = <0x10>;
+ };
+ max15301 at 13 { /* u47 */
+ compatible = "maxim,max15301";
+ reg = <0x13>;
+ };
+ max15303 at 14 { /* u7 */
+ compatible = "maxim,max15303";
+ reg = <0x14>;
+ };
+ max15303 at 15 { /* u6 */
+ compatible = "maxim,max15303";
+ reg = <0x15>;
+ };
+ max15303 at 16 { /* u10 */
+ compatible = "maxim,max15303";
+ reg = <0x16>;
+ };
+ max15303 at 17 { /* u9 */
+ compatible = "maxim,max15303";
+ reg = <0x17>;
+ };
+ max15301 at 18 { /* u63 */
+ compatible = "maxim,max15301";
+ reg = <0x18>;
+ };
+ max15303 at 1a { /* u49 */
+ compatible = "maxim,max15303";
+ reg = <0x1a>;
+ };
+ max15303 at 1b { /* u8 */
+ compatible = "maxim,max15303";
+ reg = <0x1b>;
+ };
+ max15303 at 1d { /* u18 */
+ compatible = "maxim,max15303";
+ reg = <0x1d>;
+ };
+
+ max20751 at 72 { /* u95 */
+ compatible = "maxim,max20751";
+ reg = <0x72>;
+ };
+ max20751 at 73 { /* u96 */
+ compatible = "maxim,max20751";
+ reg = <0x73>;
+ };
+ };
+ /* Bus 3 is not connected */
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* PL i2c via PCA9306 - u45 */
+ i2cswitch at 74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c at 0 { /* i2c mw 74 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom at 54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c at 1 { /* i2c mw 74 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator1 at 36 { /* SI5341 - u69 */
+ reg = <0x36>;
+ };
+
+ };
+ i2c at 2 { /* i2c mw 74 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator2 at 5d { /* USER SI570 - u42 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c at 3 { /* i2c mw 74 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator3 at 5d { /* USER MGT SI570 - u56 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>; /* copy from zc702 */
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c at 4 { /* i2c mw 74 0 10 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator4 at 69 {/* SI5328 - u20 */
+ reg = <0x69>;
+ };
+ };
+ i2c at 5 { /* i2c mw 74 0 11 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>; /* FAN controller */
+ temp at 4c {/* lm96163 - u128 */
+ compatible = "national,lm96163";
+ reg = <0x4c>;
+ };
+ };
+ /* 6 - 7 unconnected */
+ };
+
+ i2cswitch at 75 {
+ compatible = "nxp,pca9548"; /* u135 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* HPC0_IIC */
+ };
+ i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* HPC1_IIC */
+ };
+ i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c at 3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SEP 3 */
+ };
+ i2c at 5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SEP 2 */
+ };
+ i2c at 6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SEP 1 */
+ };
+ i2c at 7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SEP 0 */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 5/7] arm64: zynqmp: Add support for Xilinx zcu111-revA
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree
Cc: monstr, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel
Xilinx zcu111 is a customer board. It is reusing some parts from zcu102.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 446 ++++++++++++++++++++++
2 files changed, 447 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 922c5da39600..d15c9dc1d8f2 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
new file mode 100644
index 000000000000..b052ed837254
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -0,0 +1,446 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU111
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU111 RevA";
+ compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ /* Another 4GB connected to PL */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u22: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - MAX6643_OT_B
+ * 1 - MAX6643_FANFAIL_B
+ * 2 - MIO26_PMU_INPUT_LS
+ * 4 - SFP_SI5382_INT_ALM
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 10 - FMCP_HSPC_PRSNT_M2C_B
+ * 11 - CLK_SPI_MUX_SEL0
+ * 12 - CLK_SPI_MUX_SEL1
+ * 16 - IRPS5401_ALERT_B
+ * 17 - INA226_PMBUS_ALERT
+ * 3, 7, 13-15 - not connected
+ */
+ };
+
+ i2cswitch@75 { /* u23 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ /* PMBUS_ALERT done via pca9544 */
+ ina226@40 { /* u67 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226@41 { /* u59 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u61 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u60 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u64 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u69 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ ina226@47 { /* u66 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226@48 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ ina226@49 { /* u63 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4a { /* u3 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4b { /* u71 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4c { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4d { /* u73 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4e { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x4e>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 { /* i2c mw 75 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
+ reg = <0x43>;
+ };
+ irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
+ reg = <0x44>;
+ };
+ irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
+ reg = <0x45>;
+ };
+ /* u68 IR38064 +0 */
+ /* u70 IR38060 +1 */
+ /* u74 IR38060 +2 */
+ /* u75 IR38060 +6 */
+ /* J19 header too */
+
+ };
+ i2c@3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* SYSMON */
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ i2cswitch@74 { /* u26 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 { /* i2c mw 74 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u88 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c@1 { /* i2c mw 74 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator1@36 { /* SI5341 - u46 */
+ reg = <0x36>;
+ };
+
+ };
+ i2c@2 { /* i2c mw 74 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator2@5d { /* USER SI570 - u47 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c@3 { /* i2c mw 74 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator3@5d { /* USER MGT SI570 - u49 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c@4 { /* i2c mw 74 0 10 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator4@69 { /* SI5328 - u48 */
+ reg = <0x69>;
+ };
+ };
+ i2c@5 { /* i2c mw 74 0 11 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ sc18is603@2f { /* sc18is602 - u93 */
+ compatible = "nxp,sc18is603";
+ reg = <0x2f>;
+ /* 4 gpios for CS not handled by driver */
+ /*
+ * USB2ANY cable or
+ * LMK04208 - u90 or
+ * LMX2594 - u102 or
+ * LMX2594 - u103 or
+ * LMX2594 - u104
+ */
+ };
+ };
+ i2c@6 { /* i2c mw 74 0 11 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* FMC connector */
+ };
+ /* 7 NC */
+ };
+
+ i2cswitch@75 {
+ compatible = "nxp,pca9548"; /* u27 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* FMCP_HSPC_IIC */
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SFP3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SFP2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SFP1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SFP0 */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 5/7] arm64: zynqmp: Add support for Xilinx zcu111-revA
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: monstr-pSz03upnqPeHXe+LvDLADg, Masahiro Yamada,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, Will Deacon,
Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Xilinx zcu111 is a customer board. It is reusing some parts from zcu102.
Signed-off-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 446 ++++++++++++++++++++++
2 files changed, 447 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 922c5da39600..d15c9dc1d8f2 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
new file mode 100644
index 000000000000..b052ed837254
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -0,0 +1,446 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU111
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU111 RevA";
+ compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ /* Another 4GB connected to PL */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u22: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - MAX6643_OT_B
+ * 1 - MAX6643_FANFAIL_B
+ * 2 - MIO26_PMU_INPUT_LS
+ * 4 - SFP_SI5382_INT_ALM
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 10 - FMCP_HSPC_PRSNT_M2C_B
+ * 11 - CLK_SPI_MUX_SEL0
+ * 12 - CLK_SPI_MUX_SEL1
+ * 16 - IRPS5401_ALERT_B
+ * 17 - INA226_PMBUS_ALERT
+ * 3, 7, 13-15 - not connected
+ */
+ };
+
+ i2cswitch@75 { /* u23 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ /* PMBUS_ALERT done via pca9544 */
+ ina226@40 { /* u67 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226@41 { /* u59 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226@42 { /* u61 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226@43 { /* u60 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226@45 { /* u64 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226@46 { /* u69 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ ina226@47 { /* u66 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226@48 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ ina226@49 { /* u63 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4a { /* u3 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4b { /* u71 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4c { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4d { /* u73 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ ina226@4e { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x4e>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 { /* i2c mw 75 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
+ reg = <0x43>;
+ };
+ irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
+ reg = <0x44>;
+ };
+ irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
+ reg = <0x45>;
+ };
+ /* u68 IR38064 +0 */
+ /* u70 IR38060 +1 */
+ /* u74 IR38060 +2 */
+ /* u75 IR38060 +6 */
+ /* J19 header too */
+
+ };
+ i2c@3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* SYSMON */
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ i2cswitch@74 { /* u26 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 { /* i2c mw 74 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u88 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c@1 { /* i2c mw 74 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator1@36 { /* SI5341 - u46 */
+ reg = <0x36>;
+ };
+
+ };
+ i2c@2 { /* i2c mw 74 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator2@5d { /* USER SI570 - u47 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c@3 { /* i2c mw 74 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator3@5d { /* USER MGT SI570 - u49 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c@4 { /* i2c mw 74 0 10 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator4@69 { /* SI5328 - u48 */
+ reg = <0x69>;
+ };
+ };
+ i2c@5 { /* i2c mw 74 0 11 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ sc18is603@2f { /* sc18is602 - u93 */
+ compatible = "nxp,sc18is603";
+ reg = <0x2f>;
+ /* 4 gpios for CS not handled by driver */
+ /*
+ * USB2ANY cable or
+ * LMK04208 - u90 or
+ * LMX2594 - u102 or
+ * LMX2594 - u103 or
+ * LMX2594 - u104
+ */
+ };
+ };
+ i2c@6 { /* i2c mw 74 0 11 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* FMC connector */
+ };
+ /* 7 NC */
+ };
+
+ i2cswitch@75 {
+ compatible = "nxp,pca9548"; /* u27 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* FMCP_HSPC_IIC */
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SFP3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SFP2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SFP1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SFP0 */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 5/7] arm64: zynqmp: Add support for Xilinx zcu111-revA
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: linux-arm-kernel
Xilinx zcu111 is a customer board. It is reusing some parts from zcu102.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 1 +
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 446 ++++++++++++++++++++++
2 files changed, 447 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 922c5da39600..d15c9dc1d8f2 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu111-revA.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
new file mode 100644
index 000000000000..b052ed837254
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
@@ -0,0 +1,446 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU111
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP ZCU111 RevA";
+ compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &dcc;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ /* Another 4GB connected to PL */
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+ sw19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ gpio-key,wakeup;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat_led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy at c {
+ reg = <0xc>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u22: gpio at 20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* interrupt not connected */
+ #gpio-cells = <2>;
+ /*
+ * IRQ not connected
+ * Lines:
+ * 0 - MAX6643_OT_B
+ * 1 - MAX6643_FANFAIL_B
+ * 2 - MIO26_PMU_INPUT_LS
+ * 4 - SFP_SI5382_INT_ALM
+ * 5 - IIC_MUX_RESET_B
+ * 6 - GEM3_EXP_RESET_B
+ * 10 - FMCP_HSPC_PRSNT_M2C_B
+ * 11 - CLK_SPI_MUX_SEL0
+ * 12 - CLK_SPI_MUX_SEL1
+ * 16 - IRPS5401_ALERT_B
+ * 17 - INA226_PMBUS_ALERT
+ * 3, 7, 13-15 - not connected
+ */
+ };
+
+ i2cswitch at 75 { /* u23 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c at 0 { /* i2c mw 75 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ /* PMBUS_ALERT done via pca9544 */
+ ina226 at 40 { /* u67 */
+ compatible = "ti,ina226";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ ina226 at 41 { /* u59 */
+ compatible = "ti,ina226";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 42 { /* u61 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 43 { /* u60 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 45 { /* u64 */
+ compatible = "ti,ina226";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 46 { /* u69 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <2000>;
+ };
+ ina226 at 47 { /* u66 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 48 { /* u65 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 49 { /* u63 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 4a { /* u3 */
+ compatible = "ti,ina226";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 4b { /* u71 */
+ compatible = "ti,ina226";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 4c { /* u77 */
+ compatible = "ti,ina226";
+ reg = <0x4c>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 4d { /* u73 */
+ compatible = "ti,ina226";
+ reg = <0x4d>;
+ shunt-resistor = <5000>;
+ };
+ ina226 at 4e { /* u79 */
+ compatible = "ti,ina226";
+ reg = <0x4e>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c at 2 { /* i2c mw 75 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ irps5401_43: irps54012 at 43 { /* IRPS5401 - u53 check these */
+ reg = <0x43>;
+ };
+ irps5401_44: irps54012 at 44 { /* IRPS5401 - u55 */
+ reg = <0x44>;
+ };
+ irps5401_45: irps54012 at 45 { /* IRPS5401 - u57 */
+ reg = <0x45>;
+ };
+ /* u68 IR38064 +0 */
+ /* u70 IR38060 +1 */
+ /* u74 IR38060 +2 */
+ /* u75 IR38060 +6 */
+ /* J19 header too */
+
+ };
+ i2c at 3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* SYSMON */
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ i2cswitch at 74 { /* u26 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c at 0 { /* i2c mw 74 0 1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom at 54 { /* u88 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c at 1 { /* i2c mw 74 0 2 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator1 at 36 { /* SI5341 - u46 */
+ reg = <0x36>;
+ };
+
+ };
+ i2c at 2 { /* i2c mw 74 0 4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator2 at 5d { /* USER SI570 - u47 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ };
+ };
+ i2c at 3 { /* i2c mw 74 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator3 at 5d { /* USER MGT SI570 - u49 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ };
+ };
+ i2c at 4 { /* i2c mw 74 0 10 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si5328: clock-generator4 at 69 { /* SI5328 - u48 */
+ reg = <0x69>;
+ };
+ };
+ i2c at 5 { /* i2c mw 74 0 11 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ sc18is603 at 2f { /* sc18is602 - u93 */
+ compatible = "nxp,sc18is603";
+ reg = <0x2f>;
+ /* 4 gpios for CS not handled by driver */
+ /*
+ * USB2ANY cable or
+ * LMK04208 - u90 or
+ * LMX2594 - u102 or
+ * LMX2594 - u103 or
+ * LMX2594 - u104
+ */
+ };
+ };
+ i2c at 6 { /* i2c mw 74 0 11 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* FMC connector */
+ };
+ /* 7 NC */
+ };
+
+ i2cswitch at 75 {
+ compatible = "nxp,pca9548"; /* u27 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* FMCP_HSPC_IIC */
+ };
+ i2c at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* NC */
+ };
+ i2c at 2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c at 3 { /* i2c mw 75 0 8 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c at 4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SFP3 */
+ };
+ i2c at 5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SFP2 */
+ };
+ i2c at 6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SFP1 */
+ };
+ i2c at 7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SFP0 */
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 6/7] arm64: zynqmp: Add support for Xilinx zc12XX boards
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree
Cc: monstr, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel
These 3 boards requires minimal support to get Linux up and running.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 3 ++
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 54 +++++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 42 ++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 42 ++++++++++++++++++
4 files changed, 141 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index d15c9dc1d8f2..bdda451afaad 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
new file mode 100644
index 000000000000..0f7b4cf6078e
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1232
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1232 RevA";
+ compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
new file mode 100644
index 000000000000..9092828f92ec
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1254
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1254 RevA";
+ compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
new file mode 100644
index 000000000000..4f404c580eec
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1275
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1275 RevA";
+ compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 6/7] arm64: zynqmp: Add support for Xilinx zc12XX boards
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: monstr-pSz03upnqPeHXe+LvDLADg, Masahiro Yamada,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, Will Deacon,
Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
These 3 boards requires minimal support to get Linux up and running.
Signed-off-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/xilinx/Makefile | 3 ++
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 54 +++++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 42 ++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 42 ++++++++++++++++++
4 files changed, 141 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index d15c9dc1d8f2..bdda451afaad 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
new file mode 100644
index 000000000000..0f7b4cf6078e
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1232
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1232 RevA";
+ compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
new file mode 100644
index 000000000000..9092828f92ec
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1254
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ * Siva Durga Prasad Paladugu <sivadur-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1254 RevA";
+ compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
new file mode 100644
index 000000000000..4f404c580eec
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1275
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ * Siva Durga Prasad Paladugu <sivadur-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1275 RevA";
+ compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 6/7] arm64: zynqmp: Add support for Xilinx zc12XX boards
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: linux-arm-kernel
These 3 boards requires minimal support to get Linux up and running.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 3 ++
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 54 +++++++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 42 ++++++++++++++++++
arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts | 42 ++++++++++++++++++
4 files changed, 141 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index d15c9dc1d8f2..bdda451afaad 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
new file mode 100644
index 000000000000..0f7b4cf6078e
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1232
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1232 RevA";
+ compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
new file mode 100644
index 000000000000..9092828f92ec
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1254
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1254 RevA";
+ compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
new file mode 100644
index 000000000000..4f404c580eec
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZC1275
+ *
+ * (C) Copyright 2017 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP ZC1275 RevA";
+ compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &dcc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&dcc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 7/7] arm64: zynqmp: Add support for Xilinx zc1751
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree
Cc: monstr, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel
Xilinx zc1751 boards is used for silicon validation. Board can be
extended with 5 FMCs/DCs cards to connect various IPs. Describe all
these combinations.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 5 +
.../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 133 +++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 170 +++++++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 153 +++++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 181 +++++++++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 126 ++++++++++++++
6 files changed, 768 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index bdda451afaad..c2a0c00272e2 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -3,6 +3,11 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
new file mode 100644
index 000000000000..41f9e987c559
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm015-dc1
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm015-dc1 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ eeprom: eeprom@55 {
+ compatible = "atmel,24c64"; /* 24AA64 */
+ reg = <0x55>;
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA phy OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* eMMC */
+&sdhci0 {
+ status = "okay";
+ bus-width = <8>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
new file mode 100644
index 000000000000..c4d253cec526
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm016-dc2
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm016-dc2 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ can0 = &can0;
+ can1 = &can1;
+ ethernet0 = &gem2;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ usb0 = &usb1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem2 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@5 {
+ reg = <5>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u26: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* IRQ not connected */
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <1>;
+
+ spi0_flash0: spi0_flash0@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25wf080", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+
+ spi0_flash0@0 {
+ label = "spi0_flash0";
+ reg = <0x0 0x100000>;
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ num-cs = <1>;
+
+ spi1_flash0: spi1_flash0@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ spi1_flash0@0 {
+ label = "spi1_flash0";
+ reg = <0x0 0x84000>;
+ };
+ };
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
new file mode 100644
index 000000000000..9f312ef0e061
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm017-dc3
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP zc1751-xm017-dc3 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0 { /* VSC8211 */
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+/* just eeprom here */
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u26: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* IRQ not connected */
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+/* eeprom24c02 and SE98A temp chip pca9306 */
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA phy OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&sdhci1 { /* emmc with some settings */
+ status = "okay";
+};
+
+/* main */
+&uart0 {
+ status = "okay";
+};
+
+/* DB9 */
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
new file mode 100644
index 000000000000..c6eb888d7812
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm018-dc4
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP zc1751-xm018-dc4";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ can0 = &can0;
+ can1 = &can1;
+ ethernet0 = &gem0;
+ ethernet1 = &gem1;
+ ethernet2 = &gem2;
+ ethernet3 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&lpd_dma_chan1 {
+ status = "okay";
+};
+
+&lpd_dma_chan2 {
+ status = "okay";
+};
+
+&lpd_dma_chan3 {
+ status = "okay";
+};
+
+&lpd_dma_chan4 {
+ status = "okay";
+};
+
+&lpd_dma_chan5 {
+ status = "okay";
+};
+
+&lpd_dma_chan6 {
+ status = "okay";
+};
+
+&lpd_dma_chan7 {
+ status = "okay";
+};
+
+&lpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy0>;
+ ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
+ reg = <0>;
+ };
+ ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
+ reg = <7>;
+ };
+ ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
+ reg = <3>;
+ };
+ ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
+ reg = <8>;
+ };
+};
+
+&gem1 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy7>;
+};
+
+&gem2 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy3>;
+};
+
+&gem3 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy8>;
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
new file mode 100644
index 000000000000..2422f939ab53
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm019-dc5
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm019-dc5 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem1;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem1 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&sdhci0 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&ttc0 {
+ status = "okay";
+};
+
+&ttc1 {
+ status = "okay";
+};
+
+&ttc2 {
+ status = "okay";
+};
+
+&ttc3 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 7/7] arm64: zynqmp: Add support for Xilinx zc1751
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: monstr-pSz03upnqPeHXe+LvDLADg, Masahiro Yamada,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, Will Deacon,
Catalin Marinas, Rob Herring, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Xilinx zc1751 boards is used for silicon validation. Board can be
extended with 5 FMCs/DCs cards to connect various IPs. Describe all
these combinations.
Signed-off-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
---
arch/arm64/boot/dts/xilinx/Makefile | 5 +
.../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 133 +++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 170 +++++++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 153 +++++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 181 +++++++++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 126 ++++++++++++++
6 files changed, 768 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index bdda451afaad..c2a0c00272e2 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -3,6 +3,11 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
new file mode 100644
index 000000000000..41f9e987c559
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm015-dc1
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm015-dc1 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ eeprom: eeprom@55 {
+ compatible = "atmel,24c64"; /* 24AA64 */
+ reg = <0x55>;
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA phy OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* eMMC */
+&sdhci0 {
+ status = "okay";
+ bus-width = <8>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
new file mode 100644
index 000000000000..c4d253cec526
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm016-dc2
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm016-dc2 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ can0 = &can0;
+ can1 = &can1;
+ ethernet0 = &gem2;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ usb0 = &usb1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem2 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@5 {
+ reg = <5>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u26: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* IRQ not connected */
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <1>;
+
+ spi0_flash0: spi0_flash0@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25wf080", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+
+ spi0_flash0@0 {
+ label = "spi0_flash0";
+ reg = <0x0 0x100000>;
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ num-cs = <1>;
+
+ spi1_flash0: spi1_flash0@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ spi1_flash0@0 {
+ label = "spi1_flash0";
+ reg = <0x0 0x84000>;
+ };
+ };
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
new file mode 100644
index 000000000000..9f312ef0e061
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm017-dc3
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP zc1751-xm017-dc3 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0 { /* VSC8211 */
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+/* just eeprom here */
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u26: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* IRQ not connected */
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+/* eeprom24c02 and SE98A temp chip pca9306 */
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA phy OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&sdhci1 { /* emmc with some settings */
+ status = "okay";
+};
+
+/* main */
+&uart0 {
+ status = "okay";
+};
+
+/* DB9 */
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
new file mode 100644
index 000000000000..c6eb888d7812
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm018-dc4
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP zc1751-xm018-dc4";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ can0 = &can0;
+ can1 = &can1;
+ ethernet0 = &gem0;
+ ethernet1 = &gem1;
+ ethernet2 = &gem2;
+ ethernet3 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&lpd_dma_chan1 {
+ status = "okay";
+};
+
+&lpd_dma_chan2 {
+ status = "okay";
+};
+
+&lpd_dma_chan3 {
+ status = "okay";
+};
+
+&lpd_dma_chan4 {
+ status = "okay";
+};
+
+&lpd_dma_chan5 {
+ status = "okay";
+};
+
+&lpd_dma_chan6 {
+ status = "okay";
+};
+
+&lpd_dma_chan7 {
+ status = "okay";
+};
+
+&lpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy0>;
+ ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
+ reg = <0>;
+ };
+ ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
+ reg = <7>;
+ };
+ ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
+ reg = <3>;
+ };
+ ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
+ reg = <8>;
+ };
+};
+
+&gem1 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy7>;
+};
+
+&gem2 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy3>;
+};
+
+&gem3 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy8>;
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
new file mode 100644
index 000000000000..2422f939ab53
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm019-dc5
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm019-dc5 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem1;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem1 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&sdhci0 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&ttc0 {
+ status = "okay";
+};
+
+&ttc1 {
+ status = "okay";
+};
+
+&ttc2 {
+ status = "okay";
+};
+
+&ttc3 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
1.9.1
--
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^ permalink raw reply related [flat|nested] 37+ messages in thread
* [PATCH 7/7] arm64: zynqmp: Add support for Xilinx zc1751
@ 2018-01-19 12:55 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-01-19 12:55 UTC (permalink / raw)
To: linux-arm-kernel
Xilinx zc1751 boards is used for silicon validation. Board can be
extended with 5 FMCs/DCs cards to connect various IPs. Describe all
these combinations.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
arch/arm64/boot/dts/xilinx/Makefile | 5 +
.../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 133 +++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 170 +++++++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 153 +++++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 181 +++++++++++++++++++++
.../boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 126 ++++++++++++++
6 files changed, 768 insertions(+)
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index bdda451afaad..c2a0c00272e2 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -3,6 +3,11 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1275-revA.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm016-dc2.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm017-dc3.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm018-dc4.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
new file mode 100644
index 000000000000..41f9e987c559
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm015-dc1
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm015-dc1 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy at 0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ eeprom: eeprom at 55 {
+ compatible = "atmel,24c64"; /* 24AA64 */
+ reg = <0x55>;
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA phy OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* eMMC */
+&sdhci0 {
+ status = "okay";
+ bus-width = <8>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
new file mode 100644
index 000000000000..c4d253cec526
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm016-dc2
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm016-dc2 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ can0 = &can0;
+ can1 = &can1;
+ ethernet0 = &gem2;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ usb0 = &usb1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem2 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy at 5 {
+ reg = <5>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u26: gpio at 20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* IRQ not connected */
+ };
+
+ rtc at 68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+ num-cs = <1>;
+
+ spi0_flash0: spi0_flash0 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25wf080", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+
+ spi0_flash0 at 0 {
+ label = "spi0_flash0";
+ reg = <0x0 0x100000>;
+ };
+ };
+};
+
+&spi1 {
+ status = "okay";
+ num-cs = <1>;
+
+ spi1_flash0: spi1_flash0 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ spi1_flash0 at 0 {
+ label = "spi1_flash0";
+ reg = <0x0 0x84000>;
+ };
+ };
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
new file mode 100644
index 000000000000..9f312ef0e061
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm017-dc3
+ *
+ * (C) Copyright 2016 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP zc1751-xm017-dc3 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy at 0 { /* VSC8211 */
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+/* just eeprom here */
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tca6416_u26: gpio at 20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* IRQ not connected */
+ };
+
+ rtc at 68 {
+ compatible = "dallas,ds1339";
+ reg = <0x68>;
+ };
+};
+
+/* eeprom24c02 and SE98A temp chip pca9306 */
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA phy OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+&sdhci1 { /* emmc with some settings */
+ status = "okay";
+};
+
+/* main */
+&uart0 {
+ status = "okay";
+};
+
+/* DB9 */
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+/* ULPI SMSC USB3320 */
+&usb1 {
+ status = "okay";
+ dr_mode = "host";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
new file mode 100644
index 000000000000..c6eb888d7812
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm018-dc4
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP zc1751-xm018-dc4";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ can0 = &can0;
+ can1 = &can1;
+ ethernet0 = &gem0;
+ ethernet1 = &gem1;
+ ethernet2 = &gem2;
+ ethernet3 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&lpd_dma_chan1 {
+ status = "okay";
+};
+
+&lpd_dma_chan2 {
+ status = "okay";
+};
+
+&lpd_dma_chan3 {
+ status = "okay";
+};
+
+&lpd_dma_chan4 {
+ status = "okay";
+};
+
+&lpd_dma_chan5 {
+ status = "okay";
+};
+
+&lpd_dma_chan6 {
+ status = "okay";
+};
+
+&lpd_dma_chan7 {
+ status = "okay";
+};
+
+&lpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy0>;
+ ethernet_phy0: ethernet-phy at 0 { /* Marvell 88e1512 */
+ reg = <0>;
+ };
+ ethernet_phy7: ethernet-phy at 7 { /* Vitesse VSC8211 */
+ reg = <7>;
+ };
+ ethernet_phy3: ethernet-phy at 3 { /* Realtek RTL8211DN */
+ reg = <3>;
+ };
+ ethernet_phy8: ethernet-phy at 8 { /* Vitesse VSC8211 */
+ reg = <8>;
+ };
+};
+
+&gem1 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy7>;
+};
+
+&gem2 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy3>;
+};
+
+&gem3 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <ðernet_phy8>;
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
new file mode 100644
index 000000000000..2422f939ab53
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm019-dc5
+ *
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "ZynqMP zc1751-xm019-dc5 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem1;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem1 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy at 0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&sdhci0 {
+ status = "okay";
+ no-1-8-v;
+};
+
+&ttc0 {
+ status = "okay";
+};
+
+&ttc1 {
+ status = "okay";
+};
+
+&ttc2 {
+ status = "okay";
+};
+
+&ttc3 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [PATCH 1/7] arm64: zynqmp: Add support for Xilinx zcu100-revC
@ 2018-02-01 16:41 ` Rob Herring
0 siblings, 0 replies; 37+ messages in thread
From: Rob Herring @ 2018-02-01 16:41 UTC (permalink / raw)
To: Michal Simek
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Michal Simek, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Mark Rutland,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> This board has 2GB of memory, i2c, sd, wifi sdio, spis, uarts, display
> port and usbs.
> Board is using fixed clocks because clock driver hasn't been merged yet.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> arch/arm64/boot/dts/xilinx/Makefile | 1 +
> arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++++++++++
> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 298 ++++++++++++++++++++++
> 3 files changed, 512 insertions(+)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>
> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
> index eba179b23b17..7266a6a9c0cd 100644
> --- a/arch/arm64/boot/dts/xilinx/Makefile
> +++ b/arch/arm64/boot/dts/xilinx/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
> new file mode 100644
> index 000000000000..9c09baca7dd7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
> @@ -0,0 +1,213 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Clock specification for Xilinx ZynqMP
> + *
> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek@xilinx.com>
> + */
> +
> +/ {
> + clk100: clk100 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk125: clk125 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + clk200: clk200 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + };
> +
> + clk250: clk250 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <250000000>;
> + };
> +
> + clk300: clk300 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <300000000>;
> + };
> +
> + clk600: clk600 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <600000000>;
> + };
> +
> + dp_aclk: clock0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-accuracy = <100>;
> + };
> +
> + dp_aud_clk: clock1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24576000>;
> + clock-accuracy = <100>;
> + };
> +
> + dpdma_clk: dpdma_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0x0>;
> + clock-frequency = <533000000>;
> + };
> +
> + drm_clock: drm_clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0x0>;
> + clock-frequency = <262750000>;
> + clock-accuracy = <0x64>;
> + };
> +};
> +
> +&can0 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&can1 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&fpd_dma_chan1 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan2 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan3 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan4 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan5 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan6 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan7 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan8 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan1 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan2 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan3 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan4 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan5 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan6 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan7 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan8 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&gem0 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gem1 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gem2 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gem3 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gpio {
> + clocks = <&clk100>;
> +};
> +
> +&i2c0 {
> + clocks = <&clk100>;
> +};
> +
> +&i2c1 {
> + clocks = <&clk100>;
> +};
> +
> +&sata {
> + clocks = <&clk250>;
> +};
> +
> +&sdhci0 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&sdhci1 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&spi0 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&spi1 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&uart0 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&uart1 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&usb0 {
> + clocks = <&clk250>, <&clk250>;
> +};
> +
> +&usb1 {
> + clocks = <&clk250>, <&clk250>;
> +};
> +
> +&watchdog0 {
> + clocks = <&clk250>;
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> new file mode 100644
> index 000000000000..01f5f95806d3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> @@ -0,0 +1,298 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU100 revC
> + *
> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek@xilinx.com>
> + * Nathalie Chan King Choy <nathalie@xilinx.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "zynqmp.dtsi"
> +#include "zynqmp-clk.dtsi"
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "ZynqMP ZCU100 RevC";
> + compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
Documented?
> +
> + aliases {
> + gpio0 = &gpio;
Drop this.
> + i2c0 = &i2c1;
> + rtc0 = &rtc;
Is there more than one?
> + serial0 = &uart1;
> + serial1 = &uart0;
> + serial2 = &dcc;
> + spi0 = &spi0;
> + spi1 = &spi1;
> + usb0 = &usb0;
> + usb1 = &usb1;
Drop these.
> + mmc0 = &sdhci0;
> + mmc1 = &sdhci1;
> + };
> +
> + chosen {
> + bootargs = "earlycon";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x80000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + autorepeat;
> + sw4 {
> + label = "sw4";
> + gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + gpio-key,wakeup;
> + autorepeat;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + ds2 {
> + label = "ds2";
> + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> +
> + ds3 {
> + label = "ds3";
> + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "phy0tx"; /* WLAN tx */
> + default-state = "off";
> + };
> +
> + ds4 {
> + label = "ds4";
> + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "phy0rx"; /* WLAN rx */
> + default-state = "off";
> + };
> +
> + ds5 {
> + label = "ds5";
> + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "bluetooth-power";
> + };
> +
> + vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
> + label = "vbus_det";
> + gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> +
> + bt_power {
> + label = "bt_power";
> + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> + };
> +
> + wmmcsdio_fixed: fixedregulator-mmcsdio {
> + compatible = "regulator-fixed";
> + regulator-name = "wmmcsdio_fixed";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + sdio_pwrseq: sdio_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
> + };
> +};
> +
> +&dcc {
> + status = "okay";
> +};
> +
> +&gpio {
> + status = "okay";
> + gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
> + "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
> + "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
> + "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
> + "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
> + "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
> + "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
> + "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
> + "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
> + "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
> + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
> + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
> + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
> + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
> + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
> + "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
> + "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "";
> +};
> +
> +&i2c1 {
> + status = "okay";
> + clock-frequency = <100000>;
> + i2cswitch@75 { /* u11 */
i2c-mux@75
> + compatible = "nxp,pca9548";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x75>;
> + i2csw_0: i2c@0 { /* i2c mw 75 0 1 */
Linux commands for comments aren't relevant to dts files.
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /*
> + * LSEXP_I2C0
Is this a 96boards design? If so, using "label" and with defined names
is somewhat standard for defining low speed connector ports (and for
LEDs). That should also remove any need for using aliases for I2C and
SPI. Look at hikey or db410c.
> + */
> + };
> + i2csw_1: i2c@1 { /* i2c mw 75 0 2 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + /*
> + * LSEXP_I2C1
> + */
> + };
> + i2csw_2: i2c@2 { /* i2c mw 75 0 4 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + /*
> + * HSEXP_I2C2
> + */
> + };
> + i2csw_3: i2c@3 { /* i2c mw 75 0 8 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + /*
> + * HSEXP_I2C3
> + */
> + };
> + i2csw_4: i2c@4 { /* i2c mw 75 0 10 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x4>;
> +
> + pmic: tps65086x@5e { /* Custom TI PMIC u33 */
pmic@5e
> + compatible = "ti,tps65086";
> + reg = <0x5e>;
> + interrupt-parent = <&gpio>;
> + interrupts = <77 GPIO_ACTIVE_LOW>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + };
> + };
> + i2csw_5: i2c@5 { /* i2c mw 75 0 20 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <5>;
> + /* PS_PMBUS */
> + ina226@40 { /* u35 */
> + compatible = "ti,ina226";
> + reg = <0x40>;
> + shunt-resistor = <10000>;
> + /* MIO31 is alert which should be routed to PMUFW */
> + };
> + };
> + i2csw_6: i2c@6 { /* i2c mw 75 0 40 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <6>;
> + /*
> + * Not Connected
> + */
> + };
> + i2csw_7: i2c@7 { /* i2c mw 75 0 80 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <7>;
> + /*
> + * usb5744 (DNP) - U5
> + * 100kHz - this is default freq for us
> + */
> + };
> + };
> +};
> +
> +&rtc {
> + status = "okay";
> +};
> +
> +/* SD0 only supports 3.3V, no level shifter */
> +&sdhci0 {
> + status = "okay";
> + no-1-8-v;
> + broken-cd; /* CD has to be enabled by default */
> + disable-wp;
> +};
> +
> +&sdhci1 {
> + status = "okay";
> + bus-width = <0x4>;
> + non-removable;
> + disable-wp;
> + cap-power-off-card;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + vqmmc-supply = <&wmmcsdio_fixed>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + wlcore: wlcore@2 {
wifi@2
> + compatible = "ti,wl1831";
> + reg = <2>;
> + interrupt-parent = <&gpio>;
> + interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
> + };
> +};
> +
> +&spi0 { /* Low Speed connector */
> + status = "okay";
> +};
> +
> +&spi1 { /* High Speed connector */
> + status = "okay";
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +
> +};
> +
> +/* ULPI SMSC USB3320 */
> +&usb0 {
> + status = "okay";
> +};
> +
> +/* ULPI SMSC USB3320 */
> +&usb1 {
> + status = "okay";
> +};
> +
> +&watchdog0 {
> + status = "okay";
> +};
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 1/7] arm64: zynqmp: Add support for Xilinx zcu100-revC
@ 2018-02-01 16:41 ` Rob Herring
0 siblings, 0 replies; 37+ messages in thread
From: Rob Herring @ 2018-02-01 16:41 UTC (permalink / raw)
To: Michal Simek
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Michal Simek, Masahiro Yamada,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, Will Deacon,
Catalin Marinas, Mark Rutland,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> wrote:
> This board has 2GB of memory, i2c, sd, wifi sdio, spis, uarts, display
> port and usbs.
> Board is using fixed clocks because clock driver hasn't been merged yet.
>
> Signed-off-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> ---
>
> arch/arm64/boot/dts/xilinx/Makefile | 1 +
> arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++++++++++
> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 298 ++++++++++++++++++++++
> 3 files changed, 512 insertions(+)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>
> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
> index eba179b23b17..7266a6a9c0cd 100644
> --- a/arch/arm64/boot/dts/xilinx/Makefile
> +++ b/arch/arm64/boot/dts/xilinx/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
> new file mode 100644
> index 000000000000..9c09baca7dd7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
> @@ -0,0 +1,213 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Clock specification for Xilinx ZynqMP
> + *
> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> + */
> +
> +/ {
> + clk100: clk100 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk125: clk125 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + clk200: clk200 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + };
> +
> + clk250: clk250 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <250000000>;
> + };
> +
> + clk300: clk300 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <300000000>;
> + };
> +
> + clk600: clk600 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <600000000>;
> + };
> +
> + dp_aclk: clock0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-accuracy = <100>;
> + };
> +
> + dp_aud_clk: clock1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24576000>;
> + clock-accuracy = <100>;
> + };
> +
> + dpdma_clk: dpdma_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0x0>;
> + clock-frequency = <533000000>;
> + };
> +
> + drm_clock: drm_clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0x0>;
> + clock-frequency = <262750000>;
> + clock-accuracy = <0x64>;
> + };
> +};
> +
> +&can0 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&can1 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&fpd_dma_chan1 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan2 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan3 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan4 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan5 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan6 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan7 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan8 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan1 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan2 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan3 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan4 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan5 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan6 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan7 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan8 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&gem0 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gem1 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gem2 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gem3 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gpio {
> + clocks = <&clk100>;
> +};
> +
> +&i2c0 {
> + clocks = <&clk100>;
> +};
> +
> +&i2c1 {
> + clocks = <&clk100>;
> +};
> +
> +&sata {
> + clocks = <&clk250>;
> +};
> +
> +&sdhci0 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&sdhci1 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&spi0 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&spi1 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&uart0 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&uart1 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&usb0 {
> + clocks = <&clk250>, <&clk250>;
> +};
> +
> +&usb1 {
> + clocks = <&clk250>, <&clk250>;
> +};
> +
> +&watchdog0 {
> + clocks = <&clk250>;
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> new file mode 100644
> index 000000000000..01f5f95806d3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> @@ -0,0 +1,298 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU100 revC
> + *
> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> + * Nathalie Chan King Choy <nathalie-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> + */
> +
> +/dts-v1/;
> +
> +#include "zynqmp.dtsi"
> +#include "zynqmp-clk.dtsi"
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "ZynqMP ZCU100 RevC";
> + compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
Documented?
> +
> + aliases {
> + gpio0 = &gpio;
Drop this.
> + i2c0 = &i2c1;
> + rtc0 = &rtc;
Is there more than one?
> + serial0 = &uart1;
> + serial1 = &uart0;
> + serial2 = &dcc;
> + spi0 = &spi0;
> + spi1 = &spi1;
> + usb0 = &usb0;
> + usb1 = &usb1;
Drop these.
> + mmc0 = &sdhci0;
> + mmc1 = &sdhci1;
> + };
> +
> + chosen {
> + bootargs = "earlycon";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x80000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + autorepeat;
> + sw4 {
> + label = "sw4";
> + gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + gpio-key,wakeup;
> + autorepeat;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + ds2 {
> + label = "ds2";
> + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> +
> + ds3 {
> + label = "ds3";
> + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "phy0tx"; /* WLAN tx */
> + default-state = "off";
> + };
> +
> + ds4 {
> + label = "ds4";
> + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "phy0rx"; /* WLAN rx */
> + default-state = "off";
> + };
> +
> + ds5 {
> + label = "ds5";
> + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "bluetooth-power";
> + };
> +
> + vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
> + label = "vbus_det";
> + gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> +
> + bt_power {
> + label = "bt_power";
> + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> + };
> +
> + wmmcsdio_fixed: fixedregulator-mmcsdio {
> + compatible = "regulator-fixed";
> + regulator-name = "wmmcsdio_fixed";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + sdio_pwrseq: sdio_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
> + };
> +};
> +
> +&dcc {
> + status = "okay";
> +};
> +
> +&gpio {
> + status = "okay";
> + gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
> + "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
> + "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
> + "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
> + "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
> + "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
> + "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
> + "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
> + "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
> + "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
> + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
> + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
> + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
> + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
> + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
> + "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
> + "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "";
> +};
> +
> +&i2c1 {
> + status = "okay";
> + clock-frequency = <100000>;
> + i2cswitch@75 { /* u11 */
i2c-mux@75
> + compatible = "nxp,pca9548";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x75>;
> + i2csw_0: i2c@0 { /* i2c mw 75 0 1 */
Linux commands for comments aren't relevant to dts files.
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /*
> + * LSEXP_I2C0
Is this a 96boards design? If so, using "label" and with defined names
is somewhat standard for defining low speed connector ports (and for
LEDs). That should also remove any need for using aliases for I2C and
SPI. Look at hikey or db410c.
> + */
> + };
> + i2csw_1: i2c@1 { /* i2c mw 75 0 2 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + /*
> + * LSEXP_I2C1
> + */
> + };
> + i2csw_2: i2c@2 { /* i2c mw 75 0 4 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + /*
> + * HSEXP_I2C2
> + */
> + };
> + i2csw_3: i2c@3 { /* i2c mw 75 0 8 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + /*
> + * HSEXP_I2C3
> + */
> + };
> + i2csw_4: i2c@4 { /* i2c mw 75 0 10 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x4>;
> +
> + pmic: tps65086x@5e { /* Custom TI PMIC u33 */
pmic@5e
> + compatible = "ti,tps65086";
> + reg = <0x5e>;
> + interrupt-parent = <&gpio>;
> + interrupts = <77 GPIO_ACTIVE_LOW>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + };
> + };
> + i2csw_5: i2c@5 { /* i2c mw 75 0 20 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <5>;
> + /* PS_PMBUS */
> + ina226@40 { /* u35 */
> + compatible = "ti,ina226";
> + reg = <0x40>;
> + shunt-resistor = <10000>;
> + /* MIO31 is alert which should be routed to PMUFW */
> + };
> + };
> + i2csw_6: i2c@6 { /* i2c mw 75 0 40 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <6>;
> + /*
> + * Not Connected
> + */
> + };
> + i2csw_7: i2c@7 { /* i2c mw 75 0 80 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <7>;
> + /*
> + * usb5744 (DNP) - U5
> + * 100kHz - this is default freq for us
> + */
> + };
> + };
> +};
> +
> +&rtc {
> + status = "okay";
> +};
> +
> +/* SD0 only supports 3.3V, no level shifter */
> +&sdhci0 {
> + status = "okay";
> + no-1-8-v;
> + broken-cd; /* CD has to be enabled by default */
> + disable-wp;
> +};
> +
> +&sdhci1 {
> + status = "okay";
> + bus-width = <0x4>;
> + non-removable;
> + disable-wp;
> + cap-power-off-card;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + vqmmc-supply = <&wmmcsdio_fixed>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + wlcore: wlcore@2 {
wifi@2
> + compatible = "ti,wl1831";
> + reg = <2>;
> + interrupt-parent = <&gpio>;
> + interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
> + };
> +};
> +
> +&spi0 { /* Low Speed connector */
> + status = "okay";
> +};
> +
> +&spi1 { /* High Speed connector */
> + status = "okay";
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +
> +};
> +
> +/* ULPI SMSC USB3320 */
> +&usb0 {
> + status = "okay";
> +};
> +
> +/* ULPI SMSC USB3320 */
> +&usb1 {
> + status = "okay";
> +};
> +
> +&watchdog0 {
> + status = "okay";
> +};
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 1/7] arm64: zynqmp: Add support for Xilinx zcu100-revC
@ 2018-02-01 16:41 ` Rob Herring
0 siblings, 0 replies; 37+ messages in thread
From: Rob Herring @ 2018-02-01 16:41 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> This board has 2GB of memory, i2c, sd, wifi sdio, spis, uarts, display
> port and usbs.
> Board is using fixed clocks because clock driver hasn't been merged yet.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> arch/arm64/boot/dts/xilinx/Makefile | 1 +
> arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++++++++++
> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 298 ++++++++++++++++++++++
> 3 files changed, 512 insertions(+)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>
> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
> index eba179b23b17..7266a6a9c0cd 100644
> --- a/arch/arm64/boot/dts/xilinx/Makefile
> +++ b/arch/arm64/boot/dts/xilinx/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
> new file mode 100644
> index 000000000000..9c09baca7dd7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
> @@ -0,0 +1,213 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Clock specification for Xilinx ZynqMP
> + *
> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek@xilinx.com>
> + */
> +
> +/ {
> + clk100: clk100 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + clk125: clk125 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <125000000>;
> + };
> +
> + clk200: clk200 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + };
> +
> + clk250: clk250 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <250000000>;
> + };
> +
> + clk300: clk300 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <300000000>;
> + };
> +
> + clk600: clk600 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <600000000>;
> + };
> +
> + dp_aclk: clock0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-accuracy = <100>;
> + };
> +
> + dp_aud_clk: clock1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24576000>;
> + clock-accuracy = <100>;
> + };
> +
> + dpdma_clk: dpdma_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0x0>;
> + clock-frequency = <533000000>;
> + };
> +
> + drm_clock: drm_clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0x0>;
> + clock-frequency = <262750000>;
> + clock-accuracy = <0x64>;
> + };
> +};
> +
> +&can0 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&can1 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&fpd_dma_chan1 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan2 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan3 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan4 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan5 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan6 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan7 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&fpd_dma_chan8 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan1 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan2 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan3 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan4 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan5 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan6 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan7 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&lpd_dma_chan8 {
> + clocks = <&clk600>, <&clk100>;
> +};
> +
> +&gem0 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gem1 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gem2 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gem3 {
> + clocks = <&clk125>, <&clk125>, <&clk125>;
> +};
> +
> +&gpio {
> + clocks = <&clk100>;
> +};
> +
> +&i2c0 {
> + clocks = <&clk100>;
> +};
> +
> +&i2c1 {
> + clocks = <&clk100>;
> +};
> +
> +&sata {
> + clocks = <&clk250>;
> +};
> +
> +&sdhci0 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&sdhci1 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&spi0 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&spi1 {
> + clocks = <&clk200 &clk200>;
> +};
> +
> +&uart0 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&uart1 {
> + clocks = <&clk100 &clk100>;
> +};
> +
> +&usb0 {
> + clocks = <&clk250>, <&clk250>;
> +};
> +
> +&usb1 {
> + clocks = <&clk250>, <&clk250>;
> +};
> +
> +&watchdog0 {
> + clocks = <&clk250>;
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> new file mode 100644
> index 000000000000..01f5f95806d3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
> @@ -0,0 +1,298 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU100 revC
> + *
> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek@xilinx.com>
> + * Nathalie Chan King Choy <nathalie@xilinx.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "zynqmp.dtsi"
> +#include "zynqmp-clk.dtsi"
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "ZynqMP ZCU100 RevC";
> + compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
Documented?
> +
> + aliases {
> + gpio0 = &gpio;
Drop this.
> + i2c0 = &i2c1;
> + rtc0 = &rtc;
Is there more than one?
> + serial0 = &uart1;
> + serial1 = &uart0;
> + serial2 = &dcc;
> + spi0 = &spi0;
> + spi1 = &spi1;
> + usb0 = &usb0;
> + usb1 = &usb1;
Drop these.
> + mmc0 = &sdhci0;
> + mmc1 = &sdhci1;
> + };
> +
> + chosen {
> + bootargs = "earlycon";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory at 0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x80000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + autorepeat;
> + sw4 {
> + label = "sw4";
> + gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + gpio-key,wakeup;
> + autorepeat;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + ds2 {
> + label = "ds2";
> + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> +
> + ds3 {
> + label = "ds3";
> + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "phy0tx"; /* WLAN tx */
> + default-state = "off";
> + };
> +
> + ds4 {
> + label = "ds4";
> + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "phy0rx"; /* WLAN rx */
> + default-state = "off";
> + };
> +
> + ds5 {
> + label = "ds5";
> + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "bluetooth-power";
> + };
> +
> + vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
> + label = "vbus_det";
> + gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> +
> + bt_power {
> + label = "bt_power";
> + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> + };
> +
> + wmmcsdio_fixed: fixedregulator-mmcsdio {
> + compatible = "regulator-fixed";
> + regulator-name = "wmmcsdio_fixed";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + sdio_pwrseq: sdio_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
> + };
> +};
> +
> +&dcc {
> + status = "okay";
> +};
> +
> +&gpio {
> + status = "okay";
> + gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
> + "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
> + "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
> + "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
> + "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
> + "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
> + "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
> + "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
> + "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
> + "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
> + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
> + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
> + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
> + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
> + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
> + "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
> + "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "", "", "", "", "", "", "",
> + "", "", "", "";
> +};
> +
> +&i2c1 {
> + status = "okay";
> + clock-frequency = <100000>;
> + i2cswitch at 75 { /* u11 */
i2c-mux at 75
> + compatible = "nxp,pca9548";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x75>;
> + i2csw_0: i2c at 0 { /* i2c mw 75 0 1 */
Linux commands for comments aren't relevant to dts files.
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /*
> + * LSEXP_I2C0
Is this a 96boards design? If so, using "label" and with defined names
is somewhat standard for defining low speed connector ports (and for
LEDs). That should also remove any need for using aliases for I2C and
SPI. Look at hikey or db410c.
> + */
> + };
> + i2csw_1: i2c at 1 { /* i2c mw 75 0 2 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + /*
> + * LSEXP_I2C1
> + */
> + };
> + i2csw_2: i2c at 2 { /* i2c mw 75 0 4 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + /*
> + * HSEXP_I2C2
> + */
> + };
> + i2csw_3: i2c at 3 { /* i2c mw 75 0 8 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + /*
> + * HSEXP_I2C3
> + */
> + };
> + i2csw_4: i2c at 4 { /* i2c mw 75 0 10 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x4>;
> +
> + pmic: tps65086x at 5e { /* Custom TI PMIC u33 */
pmic at 5e
> + compatible = "ti,tps65086";
> + reg = <0x5e>;
> + interrupt-parent = <&gpio>;
> + interrupts = <77 GPIO_ACTIVE_LOW>;
> + #gpio-cells = <2>;
> + gpio-controller;
> + };
> + };
> + i2csw_5: i2c at 5 { /* i2c mw 75 0 20 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <5>;
> + /* PS_PMBUS */
> + ina226 at 40 { /* u35 */
> + compatible = "ti,ina226";
> + reg = <0x40>;
> + shunt-resistor = <10000>;
> + /* MIO31 is alert which should be routed to PMUFW */
> + };
> + };
> + i2csw_6: i2c at 6 { /* i2c mw 75 0 40 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <6>;
> + /*
> + * Not Connected
> + */
> + };
> + i2csw_7: i2c at 7 { /* i2c mw 75 0 80 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <7>;
> + /*
> + * usb5744 (DNP) - U5
> + * 100kHz - this is default freq for us
> + */
> + };
> + };
> +};
> +
> +&rtc {
> + status = "okay";
> +};
> +
> +/* SD0 only supports 3.3V, no level shifter */
> +&sdhci0 {
> + status = "okay";
> + no-1-8-v;
> + broken-cd; /* CD has to be enabled by default */
> + disable-wp;
> +};
> +
> +&sdhci1 {
> + status = "okay";
> + bus-width = <0x4>;
> + non-removable;
> + disable-wp;
> + cap-power-off-card;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + vqmmc-supply = <&wmmcsdio_fixed>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + wlcore: wlcore at 2 {
wifi at 2
> + compatible = "ti,wl1831";
> + reg = <2>;
> + interrupt-parent = <&gpio>;
> + interrupts = <76 IRQ_TYPE_EDGE_RISING>; /* MIO76 WLAN_IRQ 1V8 */
> + };
> +};
> +
> +&spi0 { /* Low Speed connector */
> + status = "okay";
> +};
> +
> +&spi1 { /* High Speed connector */
> + status = "okay";
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +
> +};
> +
> +/* ULPI SMSC USB3320 */
> +&usb0 {
> + status = "okay";
> +};
> +
> +/* ULPI SMSC USB3320 */
> +&usb1 {
> + status = "okay";
> +};
> +
> +&watchdog0 {
> + status = "okay";
> +};
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102
@ 2018-02-01 16:46 ` Rob Herring
0 siblings, 0 replies; 37+ messages in thread
From: Rob Herring @ 2018-02-01 16:46 UTC (permalink / raw)
To: Michal Simek
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Michal Simek, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Mark Rutland,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> This patch is adding revA, revB and rev1.0. There are also other
> revisions between which should be backward compatible with previous
> versions. Unfortunately all revs are still in use.
Similar comments to the 1st patch. I won't repeat them here.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> arch/arm64/boot/dts/xilinx/Makefile | 3 +
> .../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
> 4 files changed, 637 insertions(+)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
>
> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
> index 7266a6a9c0cd..24e3ce801304 100644
> --- a/arch/arm64/boot/dts/xilinx/Makefile
> +++ b/arch/arm64/boot/dts/xilinx/Makefile
> @@ -1,3 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
> new file mode 100644
> index 000000000000..4b7477795fbd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU102 Rev1.0
> + *
> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek@xilinx.com>
> + */
> +
> +#include "zynqmp-zcu102-revB.dts"
> +
> +/ {
> + model = "ZynqMP ZCU102 Rev1.0";
> + compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
Documented?
> +};
> +
> +&eeprom {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + board_sn: board_sn@0 {
Use '-' rather than '_' in node and property names.
> + reg = <0x0 0x14>;
> + };
> +
> + eth_mac: eth_mac@20 {
> + reg = <0x20 0x6>;
> + };
> +
> + board_name: board_name@d0 {
> + reg = <0xd0 0x6>;
> + };
> +
> + board_revision: board_revision@e0 {
> + reg = <0xe0 0x3>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> new file mode 100644
> index 000000000000..6a15aacf65ef
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> @@ -0,0 +1,556 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU102 RevA
> + *
> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek@xilinx.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "zynqmp.dtsi"
> +#include "zynqmp-clk.dtsi"
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "ZynqMP ZCU102 RevA";
> + compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
> +
> + aliases {
> + ethernet0 = &gem3;
> + gpio0 = &gpio;
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + mmc0 = &sdhci1;
> + rtc0 = &rtc;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &dcc;
> + usb0 = &usb0;
> + };
> +
> + chosen {
> + bootargs = "earlycon";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + autorepeat;
> + sw19 {
> + label = "sw19";
> + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
> + linux,code = <KEY_DOWN>;
> + gpio-key,wakeup;
> + autorepeat;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + heartbeat_led {
> + label = "heartbeat";
> + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +};
> +
> +&can1 {
> + status = "okay";
> +};
> +
> +&dcc {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan1 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan2 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan3 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan4 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan5 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan6 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan7 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan8 {
> + status = "okay";
> +};
> +
> +&gem3 {
> + status = "okay";
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> + phy0: phy@21 {
> + reg = <21>;
> + ti,rx-internal-delay = <0x8>;
> + ti,tx-internal-delay = <0xa>;
> + ti,fifo-depth = <0x1>;
> + };
> +};
> +
> +&gpio {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + tca6416_u97: gpio@20 {
> + /*
> + * Enable all GTs to out from U-Boot
> + * i2c mw 20 6 0 - setup IO to output
> + * i2c mw 20 2 ef - setup output values on pins 0-7
> + * i2c mw 20 3 ff - setup output values on pins 10-17
> + */
> + compatible = "ti,tca6416";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + /*
> + * IRQ not connected
> + * Lines:
> + * 0 - PS_GTR_LAN_SEL0
> + * 1 - PS_GTR_LAN_SEL1
> + * 2 - PS_GTR_LAN_SEL2
> + * 3 - PS_GTR_LAN_SEL3
> + * 4 - PCI_CLK_DIR_SEL
> + * 5 - IIC_MUX_RESET_B
> + * 6 - GEM3_EXP_RESET_B
> + * 7, 10 - 17 - not connected
> + */
> +
> + gtr_sel0 {
> + gpio-hog;
> + gpios = <0 0>;
> + output-low; /* PCIE = 0, DP = 1 */
> + line-name = "sel0";
> + };
> + gtr_sel1 {
> + gpio-hog;
> + gpios = <1 0>;
> + output-high; /* PCIE = 0, DP = 1 */
> + line-name = "sel1";
> + };
> + gtr_sel2 {
> + gpio-hog;
> + gpios = <2 0>;
> + output-high; /* PCIE = 0, USB0 = 1 */
> + line-name = "sel2";
> + };
> + gtr_sel3 {
> + gpio-hog;
> + gpios = <3 0>;
> + output-high; /* PCIE = 0, SATA = 1 */
> + line-name = "sel3";
> + };
> + };
> +
> + tca6416_u61: gpio@21 { /* enable it by i2c mw 21 6 0 */
> + compatible = "ti,tca6416";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + /*
> + * IRQ not connected
> + * Lines:
> + * 0 - VCCPSPLL_EN
> + * 1 - MGTRAVCC_EN
> + * 2 - MGTRAVTT_EN
> + * 3 - VCCPSDDRPLL_EN
> + * 4 - MIO26_PMU_INPUT_LS
> + * 5 - PL_PMBUS_ALERT
> + * 6 - PS_PMBUS_ALERT
> + * 7 - MAXIM_PMBUS_ALERT
> + * 10 - PL_DDR4_VTERM_EN
> + * 11 - PL_DDR4_VPP_2V5_EN
> + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
> + * 13 - PS_DIMM_SUSPEND_EN
> + * 14 - PS_DDR4_VTERM_EN
> + * 15 - PS_DDR4_VPP_2V5_EN
> + * 16 - 17 - not connected
> + */
> + };
> +
> + i2cswitch@75 { /* u60 */
> + compatible = "nxp,pca9544";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x75>;
> + i2c@0 { /* i2c mw 75 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /* PS_PMBUS */
> + ina226@40 { /* u76 */
Should be what the device does, not part numbers if possible. Standard
names are defined in the DT spec (additions welcome).
> + compatible = "ti,ina226";
> + reg = <0x40>;
> + shunt-resistor = <5000>;
> + };
> + ina226@41 { /* u77 */
> + compatible = "ti,ina226";
> + reg = <0x41>;
> + shunt-resistor = <5000>;
> + };
> + ina226@42 { /* u78 */
> + compatible = "ti,ina226";
> + reg = <0x42>;
> + shunt-resistor = <5000>;
> + };
> + ina226@43 { /* u87 */
> + compatible = "ti,ina226";
> + reg = <0x43>;
> + shunt-resistor = <5000>;
> + };
> + ina226@44 { /* u85 */
> + compatible = "ti,ina226";
> + reg = <0x44>;
> + shunt-resistor = <5000>;
> + };
> + ina226@45 { /* u86 */
> + compatible = "ti,ina226";
> + reg = <0x45>;
> + shunt-resistor = <5000>;
> + };
> + ina226@46 { /* u93 */
> + compatible = "ti,ina226";
> + reg = <0x46>;
> + shunt-resistor = <5000>;
> + };
> + ina226@47 { /* u88 */
> + compatible = "ti,ina226";
> + reg = <0x47>;
> + shunt-resistor = <5000>;
> + };
> + ina226@4a { /* u15 */
> + compatible = "ti,ina226";
> + reg = <0x4a>;
> + shunt-resistor = <5000>;
> + };
> + ina226@4b { /* u92 */
> + compatible = "ti,ina226";
> + reg = <0x4b>;
> + shunt-resistor = <5000>;
> + };
> + };
> + i2c@1 { /* i2c mw 75 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + /* PL_PMBUS */
> + ina226@40 { /* u79 */
> + compatible = "ti,ina226";
> + reg = <0x40>;
> + shunt-resistor = <2000>;
> + };
> + ina226@41 { /* u81 */
> + compatible = "ti,ina226";
> + reg = <0x41>;
> + shunt-resistor = <5000>;
> + };
> + ina226@42 { /* u80 */
> + compatible = "ti,ina226";
> + reg = <0x42>;
> + shunt-resistor = <5000>;
> + };
> + ina226@43 { /* u84 */
> + compatible = "ti,ina226";
> + reg = <0x43>;
> + shunt-resistor = <5000>;
> + };
> + ina226@44 { /* u16 */
> + compatible = "ti,ina226";
> + reg = <0x44>;
> + shunt-resistor = <5000>;
> + };
> + ina226@45 { /* u65 */
> + compatible = "ti,ina226";
> + reg = <0x45>;
> + shunt-resistor = <5000>;
> + };
> + ina226@46 { /* u74 */
> + compatible = "ti,ina226";
> + reg = <0x46>;
> + shunt-resistor = <5000>;
> + };
> + ina226@47 { /* u75 */
> + compatible = "ti,ina226";
> + reg = <0x47>;
> + shunt-resistor = <5000>;
> + };
> + };
> + i2c@2 { /* i2c mw 75 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + /* MAXIM_PMBUS - 00 */
> + max15301@a { /* u46 */
> + compatible = "maxim,max15301";
> + reg = <0xa>;
> + };
> + max15303@b { /* u4 */
> + compatible = "maxim,max15303";
> + reg = <0xb>;
> + };
> + max15303@10 { /* u13 */
> + compatible = "maxim,max15303";
> + reg = <0x10>;
> + };
> + max15301@13 { /* u47 */
> + compatible = "maxim,max15301";
> + reg = <0x13>;
> + };
> + max15303@14 { /* u7 */
> + compatible = "maxim,max15303";
> + reg = <0x14>;
> + };
> + max15303@15 { /* u6 */
> + compatible = "maxim,max15303";
> + reg = <0x15>;
> + };
> + max15303@16 { /* u10 */
> + compatible = "maxim,max15303";
> + reg = <0x16>;
> + };
> + max15303@17 { /* u9 */
> + compatible = "maxim,max15303";
> + reg = <0x17>;
> + };
> + max15301@18 { /* u63 */
> + compatible = "maxim,max15301";
> + reg = <0x18>;
> + };
> + max15303@1a { /* u49 */
> + compatible = "maxim,max15303";
> + reg = <0x1a>;
> + };
> + max15303@1d { /* u18 */
> + compatible = "maxim,max15303";
> + reg = <0x1d>;
> + };
> + max15303@20 { /* u8 */
> + compatible = "maxim,max15303";
> + status = "disabled"; /* unreachable */
> + reg = <0x20>;
> + };
> +
> + max20751@72 { /* u95 */
> + compatible = "maxim,max20751";
> + reg = <0x72>;
> + };
> + max20751@73 { /* u96 */
> + compatible = "maxim,max20751";
> + reg = <0x73>;
> + };
> + };
> + /* Bus 3 is not connected */
> + };
> +};
> +
> +&i2c1 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + /* PL i2c via PCA9306 - u45 */
> + i2cswitch@74 { /* u34 */
> + compatible = "nxp,pca9548";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x74>;
> + i2c@0 { /* i2c mw 74 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /*
> + * IIC_EEPROM 1kB memory which uses 256B blocks
> + * where every block has different address.
> + * 0 - 256B address 0x54
> + * 256B - 512B address 0x55
> + * 512B - 768B address 0x56
> + * 768B - 1024B address 0x57
> + */
> + eeprom: eeprom@54 { /* u23 */
> + compatible = "atmel,24c08";
> + reg = <0x54>;
> + };
> + };
> + i2c@1 { /* i2c mw 74 0 2 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + si5341: clock-generator1@36 { /* SI5341 - u69 */
Drop the 1 on clock-generator1.
> + reg = <0x36>;
> + };
> +
> + };
> + i2c@2 { /* i2c mw 74 0 4 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + si570_1: clock-generator2@5d { /* USER SI570 - u42 */
> + #clock-cells = <0>;
> + compatible = "silabs,si570";
> + reg = <0x5d>;
> + temperature-stability = <50>;
> + factory-fout = <300000000>;
> + clock-frequency = <300000000>;
> + };
> + };
> + i2c@3 { /* i2c mw 74 0 8 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
> + #clock-cells = <0>;
> + compatible = "silabs,si570";
> + reg = <0x5d>;
> + temperature-stability = <50>; /* copy from zc702 */
> + factory-fout = <156250000>;
> + clock-frequency = <148500000>;
> + };
> + };
> + i2c@4 { /* i2c mw 74 0 10 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <4>;
> + si5328: clock-generator4@69 {/* SI5328 - u20 */
> + reg = <0x69>;
> + /*
> + * Chip has interrupt present connected to PL
> + * interrupt-parent = <&>;
> + * interrupts = <>;
> + */
> + };
> + };
> + /* 5 - 7 unconnected */
> + };
> +
> + i2cswitch@75 {
> + compatible = "nxp,pca9548"; /* u135 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x75>;
> +
> + i2c@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /* HPC0_IIC */
> + };
> + i2c@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + /* HPC1_IIC */
> + };
> + i2c@2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + /* SYSMON */
> + };
> + i2c@3 { /* i2c mw 75 0 8 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + /* DDR4 SODIMM */
> + };
> + i2c@4 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <4>;
> + /* SEP 3 */
> + };
> + i2c@5 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <5>;
> + /* SEP 2 */
> + };
> + i2c@6 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <6>;
> + /* SEP 1 */
> + };
> + i2c@7 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <7>;
> + /* SEP 0 */
> + };
> + };
> +};
> +
> +&pcie {
> + status = "okay";
> +};
> +
> +&rtc {
> + status = "okay";
> +};
> +
> +&sata {
> + status = "okay";
> + /* SATA OOB timing settings */
> + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
> + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
> + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
> + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
> + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
> + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
> + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
> + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
> +};
> +
> +/* SD1 with level shifter */
> +&sdhci1 {
> + status = "okay";
> + no-1-8-v;
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +/* ULPI SMSC USB3320 */
> +&usb0 {
> + status = "okay";
> +};
> +
> +&watchdog0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
> new file mode 100644
> index 000000000000..ed3cc684931f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU102 RevB
> + *
> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek@xilinx.com>
> + */
> +
> +#include "zynqmp-zcu102-revA.dts"
> +
> +/ {
> + model = "ZynqMP ZCU102 RevB";
> + compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
> +};
> +
> +&gem3 {
> + phy-handle = <&phyc>;
> + phyc: phy@c {
> + reg = <0xc>;
> + ti,rx-internal-delay = <0x8>;
> + ti,tx-internal-delay = <0xa>;
> + ti,fifo-depth = <0x1>;
> + };
> + /* Cleanup from RevA */
> + /delete-node/ phy@21;
> +};
> +
> +/* Different qspi 512Mbit version */
> +
> +/* Fix collision with u61 */
> +&i2c0 {
> + i2cswitch@75 {
> + i2c@2 {
> + max15303@1b { /* u8 */
> + compatible = "maxim,max15303";
> + reg = <0x1b>;
> + };
> + /delete-node/ max15303@20;
> + };
> + };
> +};
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102
@ 2018-02-01 16:46 ` Rob Herring
0 siblings, 0 replies; 37+ messages in thread
From: Rob Herring @ 2018-02-01 16:46 UTC (permalink / raw)
To: Michal Simek
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Michal Simek, Masahiro Yamada,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, Will Deacon,
Catalin Marinas, Mark Rutland,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> wrote:
> This patch is adding revA, revB and rev1.0. There are also other
> revisions between which should be backward compatible with previous
> versions. Unfortunately all revs are still in use.
Similar comments to the 1st patch. I won't repeat them here.
>
> Signed-off-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> ---
>
> arch/arm64/boot/dts/xilinx/Makefile | 3 +
> .../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
> 4 files changed, 637 insertions(+)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
>
> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
> index 7266a6a9c0cd..24e3ce801304 100644
> --- a/arch/arm64/boot/dts/xilinx/Makefile
> +++ b/arch/arm64/boot/dts/xilinx/Makefile
> @@ -1,3 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
> new file mode 100644
> index 000000000000..4b7477795fbd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU102 Rev1.0
> + *
> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> + */
> +
> +#include "zynqmp-zcu102-revB.dts"
> +
> +/ {
> + model = "ZynqMP ZCU102 Rev1.0";
> + compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
Documented?
> +};
> +
> +&eeprom {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + board_sn: board_sn@0 {
Use '-' rather than '_' in node and property names.
> + reg = <0x0 0x14>;
> + };
> +
> + eth_mac: eth_mac@20 {
> + reg = <0x20 0x6>;
> + };
> +
> + board_name: board_name@d0 {
> + reg = <0xd0 0x6>;
> + };
> +
> + board_revision: board_revision@e0 {
> + reg = <0xe0 0x3>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> new file mode 100644
> index 000000000000..6a15aacf65ef
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> @@ -0,0 +1,556 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU102 RevA
> + *
> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> + */
> +
> +/dts-v1/;
> +
> +#include "zynqmp.dtsi"
> +#include "zynqmp-clk.dtsi"
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "ZynqMP ZCU102 RevA";
> + compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
> +
> + aliases {
> + ethernet0 = &gem3;
> + gpio0 = &gpio;
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + mmc0 = &sdhci1;
> + rtc0 = &rtc;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &dcc;
> + usb0 = &usb0;
> + };
> +
> + chosen {
> + bootargs = "earlycon";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + autorepeat;
> + sw19 {
> + label = "sw19";
> + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
> + linux,code = <KEY_DOWN>;
> + gpio-key,wakeup;
> + autorepeat;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + heartbeat_led {
> + label = "heartbeat";
> + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +};
> +
> +&can1 {
> + status = "okay";
> +};
> +
> +&dcc {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan1 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan2 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan3 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan4 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan5 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan6 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan7 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan8 {
> + status = "okay";
> +};
> +
> +&gem3 {
> + status = "okay";
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> + phy0: phy@21 {
> + reg = <21>;
> + ti,rx-internal-delay = <0x8>;
> + ti,tx-internal-delay = <0xa>;
> + ti,fifo-depth = <0x1>;
> + };
> +};
> +
> +&gpio {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + tca6416_u97: gpio@20 {
> + /*
> + * Enable all GTs to out from U-Boot
> + * i2c mw 20 6 0 - setup IO to output
> + * i2c mw 20 2 ef - setup output values on pins 0-7
> + * i2c mw 20 3 ff - setup output values on pins 10-17
> + */
> + compatible = "ti,tca6416";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + /*
> + * IRQ not connected
> + * Lines:
> + * 0 - PS_GTR_LAN_SEL0
> + * 1 - PS_GTR_LAN_SEL1
> + * 2 - PS_GTR_LAN_SEL2
> + * 3 - PS_GTR_LAN_SEL3
> + * 4 - PCI_CLK_DIR_SEL
> + * 5 - IIC_MUX_RESET_B
> + * 6 - GEM3_EXP_RESET_B
> + * 7, 10 - 17 - not connected
> + */
> +
> + gtr_sel0 {
> + gpio-hog;
> + gpios = <0 0>;
> + output-low; /* PCIE = 0, DP = 1 */
> + line-name = "sel0";
> + };
> + gtr_sel1 {
> + gpio-hog;
> + gpios = <1 0>;
> + output-high; /* PCIE = 0, DP = 1 */
> + line-name = "sel1";
> + };
> + gtr_sel2 {
> + gpio-hog;
> + gpios = <2 0>;
> + output-high; /* PCIE = 0, USB0 = 1 */
> + line-name = "sel2";
> + };
> + gtr_sel3 {
> + gpio-hog;
> + gpios = <3 0>;
> + output-high; /* PCIE = 0, SATA = 1 */
> + line-name = "sel3";
> + };
> + };
> +
> + tca6416_u61: gpio@21 { /* enable it by i2c mw 21 6 0 */
> + compatible = "ti,tca6416";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + /*
> + * IRQ not connected
> + * Lines:
> + * 0 - VCCPSPLL_EN
> + * 1 - MGTRAVCC_EN
> + * 2 - MGTRAVTT_EN
> + * 3 - VCCPSDDRPLL_EN
> + * 4 - MIO26_PMU_INPUT_LS
> + * 5 - PL_PMBUS_ALERT
> + * 6 - PS_PMBUS_ALERT
> + * 7 - MAXIM_PMBUS_ALERT
> + * 10 - PL_DDR4_VTERM_EN
> + * 11 - PL_DDR4_VPP_2V5_EN
> + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
> + * 13 - PS_DIMM_SUSPEND_EN
> + * 14 - PS_DDR4_VTERM_EN
> + * 15 - PS_DDR4_VPP_2V5_EN
> + * 16 - 17 - not connected
> + */
> + };
> +
> + i2cswitch@75 { /* u60 */
> + compatible = "nxp,pca9544";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x75>;
> + i2c@0 { /* i2c mw 75 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /* PS_PMBUS */
> + ina226@40 { /* u76 */
Should be what the device does, not part numbers if possible. Standard
names are defined in the DT spec (additions welcome).
> + compatible = "ti,ina226";
> + reg = <0x40>;
> + shunt-resistor = <5000>;
> + };
> + ina226@41 { /* u77 */
> + compatible = "ti,ina226";
> + reg = <0x41>;
> + shunt-resistor = <5000>;
> + };
> + ina226@42 { /* u78 */
> + compatible = "ti,ina226";
> + reg = <0x42>;
> + shunt-resistor = <5000>;
> + };
> + ina226@43 { /* u87 */
> + compatible = "ti,ina226";
> + reg = <0x43>;
> + shunt-resistor = <5000>;
> + };
> + ina226@44 { /* u85 */
> + compatible = "ti,ina226";
> + reg = <0x44>;
> + shunt-resistor = <5000>;
> + };
> + ina226@45 { /* u86 */
> + compatible = "ti,ina226";
> + reg = <0x45>;
> + shunt-resistor = <5000>;
> + };
> + ina226@46 { /* u93 */
> + compatible = "ti,ina226";
> + reg = <0x46>;
> + shunt-resistor = <5000>;
> + };
> + ina226@47 { /* u88 */
> + compatible = "ti,ina226";
> + reg = <0x47>;
> + shunt-resistor = <5000>;
> + };
> + ina226@4a { /* u15 */
> + compatible = "ti,ina226";
> + reg = <0x4a>;
> + shunt-resistor = <5000>;
> + };
> + ina226@4b { /* u92 */
> + compatible = "ti,ina226";
> + reg = <0x4b>;
> + shunt-resistor = <5000>;
> + };
> + };
> + i2c@1 { /* i2c mw 75 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + /* PL_PMBUS */
> + ina226@40 { /* u79 */
> + compatible = "ti,ina226";
> + reg = <0x40>;
> + shunt-resistor = <2000>;
> + };
> + ina226@41 { /* u81 */
> + compatible = "ti,ina226";
> + reg = <0x41>;
> + shunt-resistor = <5000>;
> + };
> + ina226@42 { /* u80 */
> + compatible = "ti,ina226";
> + reg = <0x42>;
> + shunt-resistor = <5000>;
> + };
> + ina226@43 { /* u84 */
> + compatible = "ti,ina226";
> + reg = <0x43>;
> + shunt-resistor = <5000>;
> + };
> + ina226@44 { /* u16 */
> + compatible = "ti,ina226";
> + reg = <0x44>;
> + shunt-resistor = <5000>;
> + };
> + ina226@45 { /* u65 */
> + compatible = "ti,ina226";
> + reg = <0x45>;
> + shunt-resistor = <5000>;
> + };
> + ina226@46 { /* u74 */
> + compatible = "ti,ina226";
> + reg = <0x46>;
> + shunt-resistor = <5000>;
> + };
> + ina226@47 { /* u75 */
> + compatible = "ti,ina226";
> + reg = <0x47>;
> + shunt-resistor = <5000>;
> + };
> + };
> + i2c@2 { /* i2c mw 75 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + /* MAXIM_PMBUS - 00 */
> + max15301@a { /* u46 */
> + compatible = "maxim,max15301";
> + reg = <0xa>;
> + };
> + max15303@b { /* u4 */
> + compatible = "maxim,max15303";
> + reg = <0xb>;
> + };
> + max15303@10 { /* u13 */
> + compatible = "maxim,max15303";
> + reg = <0x10>;
> + };
> + max15301@13 { /* u47 */
> + compatible = "maxim,max15301";
> + reg = <0x13>;
> + };
> + max15303@14 { /* u7 */
> + compatible = "maxim,max15303";
> + reg = <0x14>;
> + };
> + max15303@15 { /* u6 */
> + compatible = "maxim,max15303";
> + reg = <0x15>;
> + };
> + max15303@16 { /* u10 */
> + compatible = "maxim,max15303";
> + reg = <0x16>;
> + };
> + max15303@17 { /* u9 */
> + compatible = "maxim,max15303";
> + reg = <0x17>;
> + };
> + max15301@18 { /* u63 */
> + compatible = "maxim,max15301";
> + reg = <0x18>;
> + };
> + max15303@1a { /* u49 */
> + compatible = "maxim,max15303";
> + reg = <0x1a>;
> + };
> + max15303@1d { /* u18 */
> + compatible = "maxim,max15303";
> + reg = <0x1d>;
> + };
> + max15303@20 { /* u8 */
> + compatible = "maxim,max15303";
> + status = "disabled"; /* unreachable */
> + reg = <0x20>;
> + };
> +
> + max20751@72 { /* u95 */
> + compatible = "maxim,max20751";
> + reg = <0x72>;
> + };
> + max20751@73 { /* u96 */
> + compatible = "maxim,max20751";
> + reg = <0x73>;
> + };
> + };
> + /* Bus 3 is not connected */
> + };
> +};
> +
> +&i2c1 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + /* PL i2c via PCA9306 - u45 */
> + i2cswitch@74 { /* u34 */
> + compatible = "nxp,pca9548";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x74>;
> + i2c@0 { /* i2c mw 74 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /*
> + * IIC_EEPROM 1kB memory which uses 256B blocks
> + * where every block has different address.
> + * 0 - 256B address 0x54
> + * 256B - 512B address 0x55
> + * 512B - 768B address 0x56
> + * 768B - 1024B address 0x57
> + */
> + eeprom: eeprom@54 { /* u23 */
> + compatible = "atmel,24c08";
> + reg = <0x54>;
> + };
> + };
> + i2c@1 { /* i2c mw 74 0 2 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + si5341: clock-generator1@36 { /* SI5341 - u69 */
Drop the 1 on clock-generator1.
> + reg = <0x36>;
> + };
> +
> + };
> + i2c@2 { /* i2c mw 74 0 4 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + si570_1: clock-generator2@5d { /* USER SI570 - u42 */
> + #clock-cells = <0>;
> + compatible = "silabs,si570";
> + reg = <0x5d>;
> + temperature-stability = <50>;
> + factory-fout = <300000000>;
> + clock-frequency = <300000000>;
> + };
> + };
> + i2c@3 { /* i2c mw 74 0 8 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
> + #clock-cells = <0>;
> + compatible = "silabs,si570";
> + reg = <0x5d>;
> + temperature-stability = <50>; /* copy from zc702 */
> + factory-fout = <156250000>;
> + clock-frequency = <148500000>;
> + };
> + };
> + i2c@4 { /* i2c mw 74 0 10 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <4>;
> + si5328: clock-generator4@69 {/* SI5328 - u20 */
> + reg = <0x69>;
> + /*
> + * Chip has interrupt present connected to PL
> + * interrupt-parent = <&>;
> + * interrupts = <>;
> + */
> + };
> + };
> + /* 5 - 7 unconnected */
> + };
> +
> + i2cswitch@75 {
> + compatible = "nxp,pca9548"; /* u135 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x75>;
> +
> + i2c@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /* HPC0_IIC */
> + };
> + i2c@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + /* HPC1_IIC */
> + };
> + i2c@2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + /* SYSMON */
> + };
> + i2c@3 { /* i2c mw 75 0 8 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + /* DDR4 SODIMM */
> + };
> + i2c@4 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <4>;
> + /* SEP 3 */
> + };
> + i2c@5 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <5>;
> + /* SEP 2 */
> + };
> + i2c@6 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <6>;
> + /* SEP 1 */
> + };
> + i2c@7 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <7>;
> + /* SEP 0 */
> + };
> + };
> +};
> +
> +&pcie {
> + status = "okay";
> +};
> +
> +&rtc {
> + status = "okay";
> +};
> +
> +&sata {
> + status = "okay";
> + /* SATA OOB timing settings */
> + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
> + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
> + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
> + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
> + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
> + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
> + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
> + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
> +};
> +
> +/* SD1 with level shifter */
> +&sdhci1 {
> + status = "okay";
> + no-1-8-v;
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +/* ULPI SMSC USB3320 */
> +&usb0 {
> + status = "okay";
> +};
> +
> +&watchdog0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
> new file mode 100644
> index 000000000000..ed3cc684931f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU102 RevB
> + *
> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
> + */
> +
> +#include "zynqmp-zcu102-revA.dts"
> +
> +/ {
> + model = "ZynqMP ZCU102 RevB";
> + compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
> +};
> +
> +&gem3 {
> + phy-handle = <&phyc>;
> + phyc: phy@c {
> + reg = <0xc>;
> + ti,rx-internal-delay = <0x8>;
> + ti,tx-internal-delay = <0xa>;
> + ti,fifo-depth = <0x1>;
> + };
> + /* Cleanup from RevA */
> + /delete-node/ phy@21;
> +};
> +
> +/* Different qspi 512Mbit version */
> +
> +/* Fix collision with u61 */
> +&i2c0 {
> + i2cswitch@75 {
> + i2c@2 {
> + max15303@1b { /* u8 */
> + compatible = "maxim,max15303";
> + reg = <0x1b>;
> + };
> + /delete-node/ max15303@20;
> + };
> + };
> +};
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102
@ 2018-02-01 16:46 ` Rob Herring
0 siblings, 0 replies; 37+ messages in thread
From: Rob Herring @ 2018-02-01 16:46 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek@xilinx.com> wrote:
> This patch is adding revA, revB and rev1.0. There are also other
> revisions between which should be backward compatible with previous
> versions. Unfortunately all revs are still in use.
Similar comments to the 1st patch. I won't repeat them here.
>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
> arch/arm64/boot/dts/xilinx/Makefile | 3 +
> .../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
> 4 files changed, 637 insertions(+)
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
>
> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
> index 7266a6a9c0cd..24e3ce801304 100644
> --- a/arch/arm64/boot/dts/xilinx/Makefile
> +++ b/arch/arm64/boot/dts/xilinx/Makefile
> @@ -1,3 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
> new file mode 100644
> index 000000000000..4b7477795fbd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
> @@ -0,0 +1,36 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU102 Rev1.0
> + *
> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek@xilinx.com>
> + */
> +
> +#include "zynqmp-zcu102-revB.dts"
> +
> +/ {
> + model = "ZynqMP ZCU102 Rev1.0";
> + compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
Documented?
> +};
> +
> +&eeprom {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + board_sn: board_sn at 0 {
Use '-' rather than '_' in node and property names.
> + reg = <0x0 0x14>;
> + };
> +
> + eth_mac: eth_mac at 20 {
> + reg = <0x20 0x6>;
> + };
> +
> + board_name: board_name at d0 {
> + reg = <0xd0 0x6>;
> + };
> +
> + board_revision: board_revision at e0 {
> + reg = <0xe0 0x3>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> new file mode 100644
> index 000000000000..6a15aacf65ef
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
> @@ -0,0 +1,556 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU102 RevA
> + *
> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek@xilinx.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "zynqmp.dtsi"
> +#include "zynqmp-clk.dtsi"
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "ZynqMP ZCU102 RevA";
> + compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
> +
> + aliases {
> + ethernet0 = &gem3;
> + gpio0 = &gpio;
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + mmc0 = &sdhci1;
> + rtc0 = &rtc;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &dcc;
> + usb0 = &usb0;
> + };
> +
> + chosen {
> + bootargs = "earlycon";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory at 0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + autorepeat;
> + sw19 {
> + label = "sw19";
> + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
> + linux,code = <KEY_DOWN>;
> + gpio-key,wakeup;
> + autorepeat;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + heartbeat_led {
> + label = "heartbeat";
> + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +};
> +
> +&can1 {
> + status = "okay";
> +};
> +
> +&dcc {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan1 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan2 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan3 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan4 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan5 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan6 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan7 {
> + status = "okay";
> +};
> +
> +&fpd_dma_chan8 {
> + status = "okay";
> +};
> +
> +&gem3 {
> + status = "okay";
> + phy-handle = <&phy0>;
> + phy-mode = "rgmii-id";
> + phy0: phy at 21 {
> + reg = <21>;
> + ti,rx-internal-delay = <0x8>;
> + ti,tx-internal-delay = <0xa>;
> + ti,fifo-depth = <0x1>;
> + };
> +};
> +
> +&gpio {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + tca6416_u97: gpio at 20 {
> + /*
> + * Enable all GTs to out from U-Boot
> + * i2c mw 20 6 0 - setup IO to output
> + * i2c mw 20 2 ef - setup output values on pins 0-7
> + * i2c mw 20 3 ff - setup output values on pins 10-17
> + */
> + compatible = "ti,tca6416";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + /*
> + * IRQ not connected
> + * Lines:
> + * 0 - PS_GTR_LAN_SEL0
> + * 1 - PS_GTR_LAN_SEL1
> + * 2 - PS_GTR_LAN_SEL2
> + * 3 - PS_GTR_LAN_SEL3
> + * 4 - PCI_CLK_DIR_SEL
> + * 5 - IIC_MUX_RESET_B
> + * 6 - GEM3_EXP_RESET_B
> + * 7, 10 - 17 - not connected
> + */
> +
> + gtr_sel0 {
> + gpio-hog;
> + gpios = <0 0>;
> + output-low; /* PCIE = 0, DP = 1 */
> + line-name = "sel0";
> + };
> + gtr_sel1 {
> + gpio-hog;
> + gpios = <1 0>;
> + output-high; /* PCIE = 0, DP = 1 */
> + line-name = "sel1";
> + };
> + gtr_sel2 {
> + gpio-hog;
> + gpios = <2 0>;
> + output-high; /* PCIE = 0, USB0 = 1 */
> + line-name = "sel2";
> + };
> + gtr_sel3 {
> + gpio-hog;
> + gpios = <3 0>;
> + output-high; /* PCIE = 0, SATA = 1 */
> + line-name = "sel3";
> + };
> + };
> +
> + tca6416_u61: gpio at 21 { /* enable it by i2c mw 21 6 0 */
> + compatible = "ti,tca6416";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + /*
> + * IRQ not connected
> + * Lines:
> + * 0 - VCCPSPLL_EN
> + * 1 - MGTRAVCC_EN
> + * 2 - MGTRAVTT_EN
> + * 3 - VCCPSDDRPLL_EN
> + * 4 - MIO26_PMU_INPUT_LS
> + * 5 - PL_PMBUS_ALERT
> + * 6 - PS_PMBUS_ALERT
> + * 7 - MAXIM_PMBUS_ALERT
> + * 10 - PL_DDR4_VTERM_EN
> + * 11 - PL_DDR4_VPP_2V5_EN
> + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
> + * 13 - PS_DIMM_SUSPEND_EN
> + * 14 - PS_DDR4_VTERM_EN
> + * 15 - PS_DDR4_VPP_2V5_EN
> + * 16 - 17 - not connected
> + */
> + };
> +
> + i2cswitch at 75 { /* u60 */
> + compatible = "nxp,pca9544";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x75>;
> + i2c at 0 { /* i2c mw 75 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /* PS_PMBUS */
> + ina226 at 40 { /* u76 */
Should be what the device does, not part numbers if possible. Standard
names are defined in the DT spec (additions welcome).
> + compatible = "ti,ina226";
> + reg = <0x40>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 41 { /* u77 */
> + compatible = "ti,ina226";
> + reg = <0x41>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 42 { /* u78 */
> + compatible = "ti,ina226";
> + reg = <0x42>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 43 { /* u87 */
> + compatible = "ti,ina226";
> + reg = <0x43>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 44 { /* u85 */
> + compatible = "ti,ina226";
> + reg = <0x44>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 45 { /* u86 */
> + compatible = "ti,ina226";
> + reg = <0x45>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 46 { /* u93 */
> + compatible = "ti,ina226";
> + reg = <0x46>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 47 { /* u88 */
> + compatible = "ti,ina226";
> + reg = <0x47>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 4a { /* u15 */
> + compatible = "ti,ina226";
> + reg = <0x4a>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 4b { /* u92 */
> + compatible = "ti,ina226";
> + reg = <0x4b>;
> + shunt-resistor = <5000>;
> + };
> + };
> + i2c at 1 { /* i2c mw 75 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + /* PL_PMBUS */
> + ina226 at 40 { /* u79 */
> + compatible = "ti,ina226";
> + reg = <0x40>;
> + shunt-resistor = <2000>;
> + };
> + ina226 at 41 { /* u81 */
> + compatible = "ti,ina226";
> + reg = <0x41>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 42 { /* u80 */
> + compatible = "ti,ina226";
> + reg = <0x42>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 43 { /* u84 */
> + compatible = "ti,ina226";
> + reg = <0x43>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 44 { /* u16 */
> + compatible = "ti,ina226";
> + reg = <0x44>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 45 { /* u65 */
> + compatible = "ti,ina226";
> + reg = <0x45>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 46 { /* u74 */
> + compatible = "ti,ina226";
> + reg = <0x46>;
> + shunt-resistor = <5000>;
> + };
> + ina226 at 47 { /* u75 */
> + compatible = "ti,ina226";
> + reg = <0x47>;
> + shunt-resistor = <5000>;
> + };
> + };
> + i2c at 2 { /* i2c mw 75 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + /* MAXIM_PMBUS - 00 */
> + max15301 at a { /* u46 */
> + compatible = "maxim,max15301";
> + reg = <0xa>;
> + };
> + max15303 at b { /* u4 */
> + compatible = "maxim,max15303";
> + reg = <0xb>;
> + };
> + max15303 at 10 { /* u13 */
> + compatible = "maxim,max15303";
> + reg = <0x10>;
> + };
> + max15301 at 13 { /* u47 */
> + compatible = "maxim,max15301";
> + reg = <0x13>;
> + };
> + max15303 at 14 { /* u7 */
> + compatible = "maxim,max15303";
> + reg = <0x14>;
> + };
> + max15303 at 15 { /* u6 */
> + compatible = "maxim,max15303";
> + reg = <0x15>;
> + };
> + max15303 at 16 { /* u10 */
> + compatible = "maxim,max15303";
> + reg = <0x16>;
> + };
> + max15303 at 17 { /* u9 */
> + compatible = "maxim,max15303";
> + reg = <0x17>;
> + };
> + max15301 at 18 { /* u63 */
> + compatible = "maxim,max15301";
> + reg = <0x18>;
> + };
> + max15303 at 1a { /* u49 */
> + compatible = "maxim,max15303";
> + reg = <0x1a>;
> + };
> + max15303 at 1d { /* u18 */
> + compatible = "maxim,max15303";
> + reg = <0x1d>;
> + };
> + max15303 at 20 { /* u8 */
> + compatible = "maxim,max15303";
> + status = "disabled"; /* unreachable */
> + reg = <0x20>;
> + };
> +
> + max20751 at 72 { /* u95 */
> + compatible = "maxim,max20751";
> + reg = <0x72>;
> + };
> + max20751 at 73 { /* u96 */
> + compatible = "maxim,max20751";
> + reg = <0x73>;
> + };
> + };
> + /* Bus 3 is not connected */
> + };
> +};
> +
> +&i2c1 {
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + /* PL i2c via PCA9306 - u45 */
> + i2cswitch at 74 { /* u34 */
> + compatible = "nxp,pca9548";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x74>;
> + i2c at 0 { /* i2c mw 74 0 1 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /*
> + * IIC_EEPROM 1kB memory which uses 256B blocks
> + * where every block has different address.
> + * 0 - 256B address 0x54
> + * 256B - 512B address 0x55
> + * 512B - 768B address 0x56
> + * 768B - 1024B address 0x57
> + */
> + eeprom: eeprom at 54 { /* u23 */
> + compatible = "atmel,24c08";
> + reg = <0x54>;
> + };
> + };
> + i2c at 1 { /* i2c mw 74 0 2 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + si5341: clock-generator1 at 36 { /* SI5341 - u69 */
Drop the 1 on clock-generator1.
> + reg = <0x36>;
> + };
> +
> + };
> + i2c at 2 { /* i2c mw 74 0 4 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + si570_1: clock-generator2 at 5d { /* USER SI570 - u42 */
> + #clock-cells = <0>;
> + compatible = "silabs,si570";
> + reg = <0x5d>;
> + temperature-stability = <50>;
> + factory-fout = <300000000>;
> + clock-frequency = <300000000>;
> + };
> + };
> + i2c at 3 { /* i2c mw 74 0 8 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + si570_2: clock-generator3 at 5d { /* USER MGT SI570 - u56 */
> + #clock-cells = <0>;
> + compatible = "silabs,si570";
> + reg = <0x5d>;
> + temperature-stability = <50>; /* copy from zc702 */
> + factory-fout = <156250000>;
> + clock-frequency = <148500000>;
> + };
> + };
> + i2c at 4 { /* i2c mw 74 0 10 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <4>;
> + si5328: clock-generator4 at 69 {/* SI5328 - u20 */
> + reg = <0x69>;
> + /*
> + * Chip has interrupt present connected to PL
> + * interrupt-parent = <&>;
> + * interrupts = <>;
> + */
> + };
> + };
> + /* 5 - 7 unconnected */
> + };
> +
> + i2cswitch at 75 {
> + compatible = "nxp,pca9548"; /* u135 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x75>;
> +
> + i2c at 0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + /* HPC0_IIC */
> + };
> + i2c at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + /* HPC1_IIC */
> + };
> + i2c at 2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <2>;
> + /* SYSMON */
> + };
> + i2c at 3 { /* i2c mw 75 0 8 */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <3>;
> + /* DDR4 SODIMM */
> + };
> + i2c at 4 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <4>;
> + /* SEP 3 */
> + };
> + i2c at 5 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <5>;
> + /* SEP 2 */
> + };
> + i2c at 6 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <6>;
> + /* SEP 1 */
> + };
> + i2c at 7 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <7>;
> + /* SEP 0 */
> + };
> + };
> +};
> +
> +&pcie {
> + status = "okay";
> +};
> +
> +&rtc {
> + status = "okay";
> +};
> +
> +&sata {
> + status = "okay";
> + /* SATA OOB timing settings */
> + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
> + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
> + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
> + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
> + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
> + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
> + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
> + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
> +};
> +
> +/* SD1 with level shifter */
> +&sdhci1 {
> + status = "okay";
> + no-1-8-v;
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +/* ULPI SMSC USB3320 */
> +&usb0 {
> + status = "okay";
> +};
> +
> +&watchdog0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
> new file mode 100644
> index 000000000000..ed3cc684931f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * dts file for Xilinx ZynqMP ZCU102 RevB
> + *
> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
> + *
> + * Michal Simek <michal.simek@xilinx.com>
> + */
> +
> +#include "zynqmp-zcu102-revA.dts"
> +
> +/ {
> + model = "ZynqMP ZCU102 RevB";
> + compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
> +};
> +
> +&gem3 {
> + phy-handle = <&phyc>;
> + phyc: phy at c {
> + reg = <0xc>;
> + ti,rx-internal-delay = <0x8>;
> + ti,tx-internal-delay = <0xa>;
> + ti,fifo-depth = <0x1>;
> + };
> + /* Cleanup from RevA */
> + /delete-node/ phy at 21;
> +};
> +
> +/* Different qspi 512Mbit version */
> +
> +/* Fix collision with u61 */
> +&i2c0 {
> + i2cswitch at 75 {
> + i2c at 2 {
> + max15303 at 1b { /* u8 */
> + compatible = "maxim,max15303";
> + reg = <0x1b>;
> + };
> + /delete-node/ max15303 at 20;
> + };
> + };
> +};
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102
@ 2018-02-01 17:26 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-02-01 17:26 UTC (permalink / raw)
To: Rob Herring, Michal Simek
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Michal Simek, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Mark Rutland,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On 1.2.2018 17:46, Rob Herring wrote:
> On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>> This patch is adding revA, revB and rev1.0. There are also other
>> revisions between which should be backward compatible with previous
>> versions. Unfortunately all revs are still in use.
>
> Similar comments to the 1st patch. I won't repeat them here.
>
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>> arch/arm64/boot/dts/xilinx/Makefile | 3 +
>> .../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
>> 4 files changed, 637 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
>> index 7266a6a9c0cd..24e3ce801304 100644
>> --- a/arch/arm64/boot/dts/xilinx/Makefile
>> +++ b/arch/arm64/boot/dts/xilinx/Makefile
>> @@ -1,3 +1,6 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> new file mode 100644
>> index 000000000000..4b7477795fbd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> @@ -0,0 +1,36 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU102 Rev1.0
>> + *
>> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek@xilinx.com>
>> + */
>> +
>> +#include "zynqmp-zcu102-revB.dts"
>> +
>> +/ {
>> + model = "ZynqMP ZCU102 Rev1.0";
>> + compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
>
> Documented?
What exactly should be documented? All compatible strings? Or just
xlnx,zynqmp one?
Some user space libraries are checking this compatible strings and
changing behavior based on that. That's why I am putting there all of them.
>
>> +};
>> +
>> +&eeprom {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + board_sn: board_sn@0 {
>
> Use '-' rather than '_' in node and property names.
ok.
>
>> + reg = <0x0 0x14>;
>> + };
>> +
>> + eth_mac: eth_mac@20 {
>> + reg = <0x20 0x6>;
>> + };
>> +
>> + board_name: board_name@d0 {
>> + reg = <0xd0 0x6>;
>> + };
>> +
>> + board_revision: board_revision@e0 {
>> + reg = <0xe0 0x3>;
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> new file mode 100644
>> index 000000000000..6a15aacf65ef
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> @@ -0,0 +1,556 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU102 RevA
>> + *
>> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek@xilinx.com>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "zynqmp.dtsi"
>> +#include "zynqmp-clk.dtsi"
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + model = "ZynqMP ZCU102 RevA";
>> + compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
>> +
>> + aliases {
>> + ethernet0 = &gem3;
>> + gpio0 = &gpio;
>> + i2c0 = &i2c0;
>> + i2c1 = &i2c1;
>> + mmc0 = &sdhci1;
>> + rtc0 = &rtc;
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + serial2 = &dcc;
>> + usb0 = &usb0;
>> + };
>> +
>> + chosen {
>> + bootargs = "earlycon";
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + autorepeat;
>> + sw19 {
>> + label = "sw19";
>> + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
>> + linux,code = <KEY_DOWN>;
>> + gpio-key,wakeup;
>> + autorepeat;
>> + };
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> + heartbeat_led {
>> + label = "heartbeat";
>> + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "heartbeat";
>> + };
>> + };
>> +};
>> +
>> +&can1 {
>> + status = "okay";
>> +};
>> +
>> +&dcc {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan1 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan2 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan3 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan4 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan5 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan6 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan7 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan8 {
>> + status = "okay";
>> +};
>> +
>> +&gem3 {
>> + status = "okay";
>> + phy-handle = <&phy0>;
>> + phy-mode = "rgmii-id";
>> + phy0: phy@21 {
>> + reg = <21>;
>> + ti,rx-internal-delay = <0x8>;
>> + ti,tx-internal-delay = <0xa>;
>> + ti,fifo-depth = <0x1>;
>> + };
>> +};
>> +
>> +&gpio {
>> + status = "okay";
>> +};
>> +
>> +&i2c0 {
>> + status = "okay";
>> + clock-frequency = <400000>;
>> +
>> + tca6416_u97: gpio@20 {
>> + /*
>> + * Enable all GTs to out from U-Boot
>> + * i2c mw 20 6 0 - setup IO to output
>> + * i2c mw 20 2 ef - setup output values on pins 0-7
>> + * i2c mw 20 3 ff - setup output values on pins 10-17
>> + */
>> + compatible = "ti,tca6416";
>> + reg = <0x20>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + /*
>> + * IRQ not connected
>> + * Lines:
>> + * 0 - PS_GTR_LAN_SEL0
>> + * 1 - PS_GTR_LAN_SEL1
>> + * 2 - PS_GTR_LAN_SEL2
>> + * 3 - PS_GTR_LAN_SEL3
>> + * 4 - PCI_CLK_DIR_SEL
>> + * 5 - IIC_MUX_RESET_B
>> + * 6 - GEM3_EXP_RESET_B
>> + * 7, 10 - 17 - not connected
>> + */
>> +
>> + gtr_sel0 {
>> + gpio-hog;
>> + gpios = <0 0>;
>> + output-low; /* PCIE = 0, DP = 1 */
>> + line-name = "sel0";
>> + };
>> + gtr_sel1 {
>> + gpio-hog;
>> + gpios = <1 0>;
>> + output-high; /* PCIE = 0, DP = 1 */
>> + line-name = "sel1";
>> + };
>> + gtr_sel2 {
>> + gpio-hog;
>> + gpios = <2 0>;
>> + output-high; /* PCIE = 0, USB0 = 1 */
>> + line-name = "sel2";
>> + };
>> + gtr_sel3 {
>> + gpio-hog;
>> + gpios = <3 0>;
>> + output-high; /* PCIE = 0, SATA = 1 */
>> + line-name = "sel3";
>> + };
>> + };
>> +
>> + tca6416_u61: gpio@21 { /* enable it by i2c mw 21 6 0 */
>> + compatible = "ti,tca6416";
>> + reg = <0x21>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + /*
>> + * IRQ not connected
>> + * Lines:
>> + * 0 - VCCPSPLL_EN
>> + * 1 - MGTRAVCC_EN
>> + * 2 - MGTRAVTT_EN
>> + * 3 - VCCPSDDRPLL_EN
>> + * 4 - MIO26_PMU_INPUT_LS
>> + * 5 - PL_PMBUS_ALERT
>> + * 6 - PS_PMBUS_ALERT
>> + * 7 - MAXIM_PMBUS_ALERT
>> + * 10 - PL_DDR4_VTERM_EN
>> + * 11 - PL_DDR4_VPP_2V5_EN
>> + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
>> + * 13 - PS_DIMM_SUSPEND_EN
>> + * 14 - PS_DDR4_VTERM_EN
>> + * 15 - PS_DDR4_VPP_2V5_EN
>> + * 16 - 17 - not connected
>> + */
>> + };
>> +
>> + i2cswitch@75 { /* u60 */
>> + compatible = "nxp,pca9544";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x75>;
>> + i2c@0 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /* PS_PMBUS */
>> + ina226@40 { /* u76 */
>
> Should be what the device does, not part numbers if possible. Standard
> names are defined in the DT spec (additions welcome).
I need to document also identification from schematics because without
it it won't be clear which one is which part on schematics and at the
end it will be just a mess.
>
>> + compatible = "ti,ina226";
>> + reg = <0x40>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@41 { /* u77 */
>> + compatible = "ti,ina226";
>> + reg = <0x41>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@42 { /* u78 */
>> + compatible = "ti,ina226";
>> + reg = <0x42>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@43 { /* u87 */
>> + compatible = "ti,ina226";
>> + reg = <0x43>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@44 { /* u85 */
>> + compatible = "ti,ina226";
>> + reg = <0x44>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@45 { /* u86 */
>> + compatible = "ti,ina226";
>> + reg = <0x45>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@46 { /* u93 */
>> + compatible = "ti,ina226";
>> + reg = <0x46>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@47 { /* u88 */
>> + compatible = "ti,ina226";
>> + reg = <0x47>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@4a { /* u15 */
>> + compatible = "ti,ina226";
>> + reg = <0x4a>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@4b { /* u92 */
>> + compatible = "ti,ina226";
>> + reg = <0x4b>;
>> + shunt-resistor = <5000>;
>> + };
>> + };
>> + i2c@1 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <1>;
>> + /* PL_PMBUS */
>> + ina226@40 { /* u79 */
>> + compatible = "ti,ina226";
>> + reg = <0x40>;
>> + shunt-resistor = <2000>;
>> + };
>> + ina226@41 { /* u81 */
>> + compatible = "ti,ina226";
>> + reg = <0x41>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@42 { /* u80 */
>> + compatible = "ti,ina226";
>> + reg = <0x42>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@43 { /* u84 */
>> + compatible = "ti,ina226";
>> + reg = <0x43>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@44 { /* u16 */
>> + compatible = "ti,ina226";
>> + reg = <0x44>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@45 { /* u65 */
>> + compatible = "ti,ina226";
>> + reg = <0x45>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@46 { /* u74 */
>> + compatible = "ti,ina226";
>> + reg = <0x46>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@47 { /* u75 */
>> + compatible = "ti,ina226";
>> + reg = <0x47>;
>> + shunt-resistor = <5000>;
>> + };
>> + };
>> + i2c@2 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <2>;
>> + /* MAXIM_PMBUS - 00 */
>> + max15301@a { /* u46 */
>> + compatible = "maxim,max15301";
>> + reg = <0xa>;
>> + };
>> + max15303@b { /* u4 */
>> + compatible = "maxim,max15303";
>> + reg = <0xb>;
>> + };
>> + max15303@10 { /* u13 */
>> + compatible = "maxim,max15303";
>> + reg = <0x10>;
>> + };
>> + max15301@13 { /* u47 */
>> + compatible = "maxim,max15301";
>> + reg = <0x13>;
>> + };
>> + max15303@14 { /* u7 */
>> + compatible = "maxim,max15303";
>> + reg = <0x14>;
>> + };
>> + max15303@15 { /* u6 */
>> + compatible = "maxim,max15303";
>> + reg = <0x15>;
>> + };
>> + max15303@16 { /* u10 */
>> + compatible = "maxim,max15303";
>> + reg = <0x16>;
>> + };
>> + max15303@17 { /* u9 */
>> + compatible = "maxim,max15303";
>> + reg = <0x17>;
>> + };
>> + max15301@18 { /* u63 */
>> + compatible = "maxim,max15301";
>> + reg = <0x18>;
>> + };
>> + max15303@1a { /* u49 */
>> + compatible = "maxim,max15303";
>> + reg = <0x1a>;
>> + };
>> + max15303@1d { /* u18 */
>> + compatible = "maxim,max15303";
>> + reg = <0x1d>;
>> + };
>> + max15303@20 { /* u8 */
>> + compatible = "maxim,max15303";
>> + status = "disabled"; /* unreachable */
>> + reg = <0x20>;
>> + };
>> +
>> + max20751@72 { /* u95 */
>> + compatible = "maxim,max20751";
>> + reg = <0x72>;
>> + };
>> + max20751@73 { /* u96 */
>> + compatible = "maxim,max20751";
>> + reg = <0x73>;
>> + };
>> + };
>> + /* Bus 3 is not connected */
>> + };
>> +};
>> +
>> +&i2c1 {
>> + status = "okay";
>> + clock-frequency = <400000>;
>> +
>> + /* PL i2c via PCA9306 - u45 */
>> + i2cswitch@74 { /* u34 */
>> + compatible = "nxp,pca9548";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x74>;
>> + i2c@0 { /* i2c mw 74 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /*
>> + * IIC_EEPROM 1kB memory which uses 256B blocks
>> + * where every block has different address.
>> + * 0 - 256B address 0x54
>> + * 256B - 512B address 0x55
>> + * 512B - 768B address 0x56
>> + * 768B - 1024B address 0x57
>> + */
>> + eeprom: eeprom@54 { /* u23 */
>> + compatible = "atmel,24c08";
>> + reg = <0x54>;
>> + };
>> + };
>> + i2c@1 { /* i2c mw 74 0 2 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <1>;
>> + si5341: clock-generator1@36 { /* SI5341 - u69 */
>
> Drop the 1 on clock-generator1.
ok.
Thanks,
Michal
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102
@ 2018-02-01 17:26 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-02-01 17:26 UTC (permalink / raw)
To: Rob Herring, Michal Simek
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Michal Simek, Masahiro Yamada,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, Will Deacon,
Catalin Marinas, Mark Rutland,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On 1.2.2018 17:46, Rob Herring wrote:
> On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> wrote:
>> This patch is adding revA, revB and rev1.0. There are also other
>> revisions between which should be backward compatible with previous
>> versions. Unfortunately all revs are still in use.
>
> Similar comments to the 1st patch. I won't repeat them here.
>
>>
>> Signed-off-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>> ---
>>
>> arch/arm64/boot/dts/xilinx/Makefile | 3 +
>> .../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
>> 4 files changed, 637 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
>> index 7266a6a9c0cd..24e3ce801304 100644
>> --- a/arch/arm64/boot/dts/xilinx/Makefile
>> +++ b/arch/arm64/boot/dts/xilinx/Makefile
>> @@ -1,3 +1,6 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> new file mode 100644
>> index 000000000000..4b7477795fbd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> @@ -0,0 +1,36 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU102 Rev1.0
>> + *
>> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>> + */
>> +
>> +#include "zynqmp-zcu102-revB.dts"
>> +
>> +/ {
>> + model = "ZynqMP ZCU102 Rev1.0";
>> + compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
>
> Documented?
What exactly should be documented? All compatible strings? Or just
xlnx,zynqmp one?
Some user space libraries are checking this compatible strings and
changing behavior based on that. That's why I am putting there all of them.
>
>> +};
>> +
>> +&eeprom {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + board_sn: board_sn@0 {
>
> Use '-' rather than '_' in node and property names.
ok.
>
>> + reg = <0x0 0x14>;
>> + };
>> +
>> + eth_mac: eth_mac@20 {
>> + reg = <0x20 0x6>;
>> + };
>> +
>> + board_name: board_name@d0 {
>> + reg = <0xd0 0x6>;
>> + };
>> +
>> + board_revision: board_revision@e0 {
>> + reg = <0xe0 0x3>;
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> new file mode 100644
>> index 000000000000..6a15aacf65ef
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> @@ -0,0 +1,556 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU102 RevA
>> + *
>> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "zynqmp.dtsi"
>> +#include "zynqmp-clk.dtsi"
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + model = "ZynqMP ZCU102 RevA";
>> + compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
>> +
>> + aliases {
>> + ethernet0 = &gem3;
>> + gpio0 = &gpio;
>> + i2c0 = &i2c0;
>> + i2c1 = &i2c1;
>> + mmc0 = &sdhci1;
>> + rtc0 = &rtc;
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + serial2 = &dcc;
>> + usb0 = &usb0;
>> + };
>> +
>> + chosen {
>> + bootargs = "earlycon";
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + autorepeat;
>> + sw19 {
>> + label = "sw19";
>> + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
>> + linux,code = <KEY_DOWN>;
>> + gpio-key,wakeup;
>> + autorepeat;
>> + };
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> + heartbeat_led {
>> + label = "heartbeat";
>> + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "heartbeat";
>> + };
>> + };
>> +};
>> +
>> +&can1 {
>> + status = "okay";
>> +};
>> +
>> +&dcc {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan1 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan2 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan3 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan4 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan5 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan6 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan7 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan8 {
>> + status = "okay";
>> +};
>> +
>> +&gem3 {
>> + status = "okay";
>> + phy-handle = <&phy0>;
>> + phy-mode = "rgmii-id";
>> + phy0: phy@21 {
>> + reg = <21>;
>> + ti,rx-internal-delay = <0x8>;
>> + ti,tx-internal-delay = <0xa>;
>> + ti,fifo-depth = <0x1>;
>> + };
>> +};
>> +
>> +&gpio {
>> + status = "okay";
>> +};
>> +
>> +&i2c0 {
>> + status = "okay";
>> + clock-frequency = <400000>;
>> +
>> + tca6416_u97: gpio@20 {
>> + /*
>> + * Enable all GTs to out from U-Boot
>> + * i2c mw 20 6 0 - setup IO to output
>> + * i2c mw 20 2 ef - setup output values on pins 0-7
>> + * i2c mw 20 3 ff - setup output values on pins 10-17
>> + */
>> + compatible = "ti,tca6416";
>> + reg = <0x20>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + /*
>> + * IRQ not connected
>> + * Lines:
>> + * 0 - PS_GTR_LAN_SEL0
>> + * 1 - PS_GTR_LAN_SEL1
>> + * 2 - PS_GTR_LAN_SEL2
>> + * 3 - PS_GTR_LAN_SEL3
>> + * 4 - PCI_CLK_DIR_SEL
>> + * 5 - IIC_MUX_RESET_B
>> + * 6 - GEM3_EXP_RESET_B
>> + * 7, 10 - 17 - not connected
>> + */
>> +
>> + gtr_sel0 {
>> + gpio-hog;
>> + gpios = <0 0>;
>> + output-low; /* PCIE = 0, DP = 1 */
>> + line-name = "sel0";
>> + };
>> + gtr_sel1 {
>> + gpio-hog;
>> + gpios = <1 0>;
>> + output-high; /* PCIE = 0, DP = 1 */
>> + line-name = "sel1";
>> + };
>> + gtr_sel2 {
>> + gpio-hog;
>> + gpios = <2 0>;
>> + output-high; /* PCIE = 0, USB0 = 1 */
>> + line-name = "sel2";
>> + };
>> + gtr_sel3 {
>> + gpio-hog;
>> + gpios = <3 0>;
>> + output-high; /* PCIE = 0, SATA = 1 */
>> + line-name = "sel3";
>> + };
>> + };
>> +
>> + tca6416_u61: gpio@21 { /* enable it by i2c mw 21 6 0 */
>> + compatible = "ti,tca6416";
>> + reg = <0x21>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + /*
>> + * IRQ not connected
>> + * Lines:
>> + * 0 - VCCPSPLL_EN
>> + * 1 - MGTRAVCC_EN
>> + * 2 - MGTRAVTT_EN
>> + * 3 - VCCPSDDRPLL_EN
>> + * 4 - MIO26_PMU_INPUT_LS
>> + * 5 - PL_PMBUS_ALERT
>> + * 6 - PS_PMBUS_ALERT
>> + * 7 - MAXIM_PMBUS_ALERT
>> + * 10 - PL_DDR4_VTERM_EN
>> + * 11 - PL_DDR4_VPP_2V5_EN
>> + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
>> + * 13 - PS_DIMM_SUSPEND_EN
>> + * 14 - PS_DDR4_VTERM_EN
>> + * 15 - PS_DDR4_VPP_2V5_EN
>> + * 16 - 17 - not connected
>> + */
>> + };
>> +
>> + i2cswitch@75 { /* u60 */
>> + compatible = "nxp,pca9544";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x75>;
>> + i2c@0 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /* PS_PMBUS */
>> + ina226@40 { /* u76 */
>
> Should be what the device does, not part numbers if possible. Standard
> names are defined in the DT spec (additions welcome).
I need to document also identification from schematics because without
it it won't be clear which one is which part on schematics and at the
end it will be just a mess.
>
>> + compatible = "ti,ina226";
>> + reg = <0x40>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@41 { /* u77 */
>> + compatible = "ti,ina226";
>> + reg = <0x41>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@42 { /* u78 */
>> + compatible = "ti,ina226";
>> + reg = <0x42>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@43 { /* u87 */
>> + compatible = "ti,ina226";
>> + reg = <0x43>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@44 { /* u85 */
>> + compatible = "ti,ina226";
>> + reg = <0x44>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@45 { /* u86 */
>> + compatible = "ti,ina226";
>> + reg = <0x45>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@46 { /* u93 */
>> + compatible = "ti,ina226";
>> + reg = <0x46>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@47 { /* u88 */
>> + compatible = "ti,ina226";
>> + reg = <0x47>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@4a { /* u15 */
>> + compatible = "ti,ina226";
>> + reg = <0x4a>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@4b { /* u92 */
>> + compatible = "ti,ina226";
>> + reg = <0x4b>;
>> + shunt-resistor = <5000>;
>> + };
>> + };
>> + i2c@1 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <1>;
>> + /* PL_PMBUS */
>> + ina226@40 { /* u79 */
>> + compatible = "ti,ina226";
>> + reg = <0x40>;
>> + shunt-resistor = <2000>;
>> + };
>> + ina226@41 { /* u81 */
>> + compatible = "ti,ina226";
>> + reg = <0x41>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@42 { /* u80 */
>> + compatible = "ti,ina226";
>> + reg = <0x42>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@43 { /* u84 */
>> + compatible = "ti,ina226";
>> + reg = <0x43>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@44 { /* u16 */
>> + compatible = "ti,ina226";
>> + reg = <0x44>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@45 { /* u65 */
>> + compatible = "ti,ina226";
>> + reg = <0x45>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@46 { /* u74 */
>> + compatible = "ti,ina226";
>> + reg = <0x46>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226@47 { /* u75 */
>> + compatible = "ti,ina226";
>> + reg = <0x47>;
>> + shunt-resistor = <5000>;
>> + };
>> + };
>> + i2c@2 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <2>;
>> + /* MAXIM_PMBUS - 00 */
>> + max15301@a { /* u46 */
>> + compatible = "maxim,max15301";
>> + reg = <0xa>;
>> + };
>> + max15303@b { /* u4 */
>> + compatible = "maxim,max15303";
>> + reg = <0xb>;
>> + };
>> + max15303@10 { /* u13 */
>> + compatible = "maxim,max15303";
>> + reg = <0x10>;
>> + };
>> + max15301@13 { /* u47 */
>> + compatible = "maxim,max15301";
>> + reg = <0x13>;
>> + };
>> + max15303@14 { /* u7 */
>> + compatible = "maxim,max15303";
>> + reg = <0x14>;
>> + };
>> + max15303@15 { /* u6 */
>> + compatible = "maxim,max15303";
>> + reg = <0x15>;
>> + };
>> + max15303@16 { /* u10 */
>> + compatible = "maxim,max15303";
>> + reg = <0x16>;
>> + };
>> + max15303@17 { /* u9 */
>> + compatible = "maxim,max15303";
>> + reg = <0x17>;
>> + };
>> + max15301@18 { /* u63 */
>> + compatible = "maxim,max15301";
>> + reg = <0x18>;
>> + };
>> + max15303@1a { /* u49 */
>> + compatible = "maxim,max15303";
>> + reg = <0x1a>;
>> + };
>> + max15303@1d { /* u18 */
>> + compatible = "maxim,max15303";
>> + reg = <0x1d>;
>> + };
>> + max15303@20 { /* u8 */
>> + compatible = "maxim,max15303";
>> + status = "disabled"; /* unreachable */
>> + reg = <0x20>;
>> + };
>> +
>> + max20751@72 { /* u95 */
>> + compatible = "maxim,max20751";
>> + reg = <0x72>;
>> + };
>> + max20751@73 { /* u96 */
>> + compatible = "maxim,max20751";
>> + reg = <0x73>;
>> + };
>> + };
>> + /* Bus 3 is not connected */
>> + };
>> +};
>> +
>> +&i2c1 {
>> + status = "okay";
>> + clock-frequency = <400000>;
>> +
>> + /* PL i2c via PCA9306 - u45 */
>> + i2cswitch@74 { /* u34 */
>> + compatible = "nxp,pca9548";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x74>;
>> + i2c@0 { /* i2c mw 74 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /*
>> + * IIC_EEPROM 1kB memory which uses 256B blocks
>> + * where every block has different address.
>> + * 0 - 256B address 0x54
>> + * 256B - 512B address 0x55
>> + * 512B - 768B address 0x56
>> + * 768B - 1024B address 0x57
>> + */
>> + eeprom: eeprom@54 { /* u23 */
>> + compatible = "atmel,24c08";
>> + reg = <0x54>;
>> + };
>> + };
>> + i2c@1 { /* i2c mw 74 0 2 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <1>;
>> + si5341: clock-generator1@36 { /* SI5341 - u69 */
>
> Drop the 1 on clock-generator1.
ok.
Thanks,
Michal
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^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102
@ 2018-02-01 17:26 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-02-01 17:26 UTC (permalink / raw)
To: linux-arm-kernel
On 1.2.2018 17:46, Rob Herring wrote:
> On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>> This patch is adding revA, revB and rev1.0. There are also other
>> revisions between which should be backward compatible with previous
>> versions. Unfortunately all revs are still in use.
>
> Similar comments to the 1st patch. I won't repeat them here.
>
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>> arch/arm64/boot/dts/xilinx/Makefile | 3 +
>> .../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
>> 4 files changed, 637 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
>> index 7266a6a9c0cd..24e3ce801304 100644
>> --- a/arch/arm64/boot/dts/xilinx/Makefile
>> +++ b/arch/arm64/boot/dts/xilinx/Makefile
>> @@ -1,3 +1,6 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> new file mode 100644
>> index 000000000000..4b7477795fbd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> @@ -0,0 +1,36 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU102 Rev1.0
>> + *
>> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek@xilinx.com>
>> + */
>> +
>> +#include "zynqmp-zcu102-revB.dts"
>> +
>> +/ {
>> + model = "ZynqMP ZCU102 Rev1.0";
>> + compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
>
> Documented?
What exactly should be documented? All compatible strings? Or just
xlnx,zynqmp one?
Some user space libraries are checking this compatible strings and
changing behavior based on that. That's why I am putting there all of them.
>
>> +};
>> +
>> +&eeprom {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + board_sn: board_sn at 0 {
>
> Use '-' rather than '_' in node and property names.
ok.
>
>> + reg = <0x0 0x14>;
>> + };
>> +
>> + eth_mac: eth_mac at 20 {
>> + reg = <0x20 0x6>;
>> + };
>> +
>> + board_name: board_name at d0 {
>> + reg = <0xd0 0x6>;
>> + };
>> +
>> + board_revision: board_revision at e0 {
>> + reg = <0xe0 0x3>;
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> new file mode 100644
>> index 000000000000..6a15aacf65ef
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> @@ -0,0 +1,556 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU102 RevA
>> + *
>> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek@xilinx.com>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "zynqmp.dtsi"
>> +#include "zynqmp-clk.dtsi"
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + model = "ZynqMP ZCU102 RevA";
>> + compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
>> +
>> + aliases {
>> + ethernet0 = &gem3;
>> + gpio0 = &gpio;
>> + i2c0 = &i2c0;
>> + i2c1 = &i2c1;
>> + mmc0 = &sdhci1;
>> + rtc0 = &rtc;
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + serial2 = &dcc;
>> + usb0 = &usb0;
>> + };
>> +
>> + chosen {
>> + bootargs = "earlycon";
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + memory at 0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + autorepeat;
>> + sw19 {
>> + label = "sw19";
>> + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
>> + linux,code = <KEY_DOWN>;
>> + gpio-key,wakeup;
>> + autorepeat;
>> + };
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> + heartbeat_led {
>> + label = "heartbeat";
>> + gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "heartbeat";
>> + };
>> + };
>> +};
>> +
>> +&can1 {
>> + status = "okay";
>> +};
>> +
>> +&dcc {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan1 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan2 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan3 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan4 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan5 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan6 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan7 {
>> + status = "okay";
>> +};
>> +
>> +&fpd_dma_chan8 {
>> + status = "okay";
>> +};
>> +
>> +&gem3 {
>> + status = "okay";
>> + phy-handle = <&phy0>;
>> + phy-mode = "rgmii-id";
>> + phy0: phy at 21 {
>> + reg = <21>;
>> + ti,rx-internal-delay = <0x8>;
>> + ti,tx-internal-delay = <0xa>;
>> + ti,fifo-depth = <0x1>;
>> + };
>> +};
>> +
>> +&gpio {
>> + status = "okay";
>> +};
>> +
>> +&i2c0 {
>> + status = "okay";
>> + clock-frequency = <400000>;
>> +
>> + tca6416_u97: gpio at 20 {
>> + /*
>> + * Enable all GTs to out from U-Boot
>> + * i2c mw 20 6 0 - setup IO to output
>> + * i2c mw 20 2 ef - setup output values on pins 0-7
>> + * i2c mw 20 3 ff - setup output values on pins 10-17
>> + */
>> + compatible = "ti,tca6416";
>> + reg = <0x20>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + /*
>> + * IRQ not connected
>> + * Lines:
>> + * 0 - PS_GTR_LAN_SEL0
>> + * 1 - PS_GTR_LAN_SEL1
>> + * 2 - PS_GTR_LAN_SEL2
>> + * 3 - PS_GTR_LAN_SEL3
>> + * 4 - PCI_CLK_DIR_SEL
>> + * 5 - IIC_MUX_RESET_B
>> + * 6 - GEM3_EXP_RESET_B
>> + * 7, 10 - 17 - not connected
>> + */
>> +
>> + gtr_sel0 {
>> + gpio-hog;
>> + gpios = <0 0>;
>> + output-low; /* PCIE = 0, DP = 1 */
>> + line-name = "sel0";
>> + };
>> + gtr_sel1 {
>> + gpio-hog;
>> + gpios = <1 0>;
>> + output-high; /* PCIE = 0, DP = 1 */
>> + line-name = "sel1";
>> + };
>> + gtr_sel2 {
>> + gpio-hog;
>> + gpios = <2 0>;
>> + output-high; /* PCIE = 0, USB0 = 1 */
>> + line-name = "sel2";
>> + };
>> + gtr_sel3 {
>> + gpio-hog;
>> + gpios = <3 0>;
>> + output-high; /* PCIE = 0, SATA = 1 */
>> + line-name = "sel3";
>> + };
>> + };
>> +
>> + tca6416_u61: gpio at 21 { /* enable it by i2c mw 21 6 0 */
>> + compatible = "ti,tca6416";
>> + reg = <0x21>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + /*
>> + * IRQ not connected
>> + * Lines:
>> + * 0 - VCCPSPLL_EN
>> + * 1 - MGTRAVCC_EN
>> + * 2 - MGTRAVTT_EN
>> + * 3 - VCCPSDDRPLL_EN
>> + * 4 - MIO26_PMU_INPUT_LS
>> + * 5 - PL_PMBUS_ALERT
>> + * 6 - PS_PMBUS_ALERT
>> + * 7 - MAXIM_PMBUS_ALERT
>> + * 10 - PL_DDR4_VTERM_EN
>> + * 11 - PL_DDR4_VPP_2V5_EN
>> + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
>> + * 13 - PS_DIMM_SUSPEND_EN
>> + * 14 - PS_DDR4_VTERM_EN
>> + * 15 - PS_DDR4_VPP_2V5_EN
>> + * 16 - 17 - not connected
>> + */
>> + };
>> +
>> + i2cswitch at 75 { /* u60 */
>> + compatible = "nxp,pca9544";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x75>;
>> + i2c at 0 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /* PS_PMBUS */
>> + ina226 at 40 { /* u76 */
>
> Should be what the device does, not part numbers if possible. Standard
> names are defined in the DT spec (additions welcome).
I need to document also identification from schematics because without
it it won't be clear which one is which part on schematics and at the
end it will be just a mess.
>
>> + compatible = "ti,ina226";
>> + reg = <0x40>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 41 { /* u77 */
>> + compatible = "ti,ina226";
>> + reg = <0x41>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 42 { /* u78 */
>> + compatible = "ti,ina226";
>> + reg = <0x42>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 43 { /* u87 */
>> + compatible = "ti,ina226";
>> + reg = <0x43>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 44 { /* u85 */
>> + compatible = "ti,ina226";
>> + reg = <0x44>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 45 { /* u86 */
>> + compatible = "ti,ina226";
>> + reg = <0x45>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 46 { /* u93 */
>> + compatible = "ti,ina226";
>> + reg = <0x46>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 47 { /* u88 */
>> + compatible = "ti,ina226";
>> + reg = <0x47>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 4a { /* u15 */
>> + compatible = "ti,ina226";
>> + reg = <0x4a>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 4b { /* u92 */
>> + compatible = "ti,ina226";
>> + reg = <0x4b>;
>> + shunt-resistor = <5000>;
>> + };
>> + };
>> + i2c at 1 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <1>;
>> + /* PL_PMBUS */
>> + ina226 at 40 { /* u79 */
>> + compatible = "ti,ina226";
>> + reg = <0x40>;
>> + shunt-resistor = <2000>;
>> + };
>> + ina226 at 41 { /* u81 */
>> + compatible = "ti,ina226";
>> + reg = <0x41>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 42 { /* u80 */
>> + compatible = "ti,ina226";
>> + reg = <0x42>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 43 { /* u84 */
>> + compatible = "ti,ina226";
>> + reg = <0x43>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 44 { /* u16 */
>> + compatible = "ti,ina226";
>> + reg = <0x44>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 45 { /* u65 */
>> + compatible = "ti,ina226";
>> + reg = <0x45>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 46 { /* u74 */
>> + compatible = "ti,ina226";
>> + reg = <0x46>;
>> + shunt-resistor = <5000>;
>> + };
>> + ina226 at 47 { /* u75 */
>> + compatible = "ti,ina226";
>> + reg = <0x47>;
>> + shunt-resistor = <5000>;
>> + };
>> + };
>> + i2c at 2 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <2>;
>> + /* MAXIM_PMBUS - 00 */
>> + max15301 at a { /* u46 */
>> + compatible = "maxim,max15301";
>> + reg = <0xa>;
>> + };
>> + max15303 at b { /* u4 */
>> + compatible = "maxim,max15303";
>> + reg = <0xb>;
>> + };
>> + max15303 at 10 { /* u13 */
>> + compatible = "maxim,max15303";
>> + reg = <0x10>;
>> + };
>> + max15301 at 13 { /* u47 */
>> + compatible = "maxim,max15301";
>> + reg = <0x13>;
>> + };
>> + max15303 at 14 { /* u7 */
>> + compatible = "maxim,max15303";
>> + reg = <0x14>;
>> + };
>> + max15303 at 15 { /* u6 */
>> + compatible = "maxim,max15303";
>> + reg = <0x15>;
>> + };
>> + max15303 at 16 { /* u10 */
>> + compatible = "maxim,max15303";
>> + reg = <0x16>;
>> + };
>> + max15303 at 17 { /* u9 */
>> + compatible = "maxim,max15303";
>> + reg = <0x17>;
>> + };
>> + max15301 at 18 { /* u63 */
>> + compatible = "maxim,max15301";
>> + reg = <0x18>;
>> + };
>> + max15303 at 1a { /* u49 */
>> + compatible = "maxim,max15303";
>> + reg = <0x1a>;
>> + };
>> + max15303 at 1d { /* u18 */
>> + compatible = "maxim,max15303";
>> + reg = <0x1d>;
>> + };
>> + max15303 at 20 { /* u8 */
>> + compatible = "maxim,max15303";
>> + status = "disabled"; /* unreachable */
>> + reg = <0x20>;
>> + };
>> +
>> + max20751 at 72 { /* u95 */
>> + compatible = "maxim,max20751";
>> + reg = <0x72>;
>> + };
>> + max20751 at 73 { /* u96 */
>> + compatible = "maxim,max20751";
>> + reg = <0x73>;
>> + };
>> + };
>> + /* Bus 3 is not connected */
>> + };
>> +};
>> +
>> +&i2c1 {
>> + status = "okay";
>> + clock-frequency = <400000>;
>> +
>> + /* PL i2c via PCA9306 - u45 */
>> + i2cswitch at 74 { /* u34 */
>> + compatible = "nxp,pca9548";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x74>;
>> + i2c at 0 { /* i2c mw 74 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /*
>> + * IIC_EEPROM 1kB memory which uses 256B blocks
>> + * where every block has different address.
>> + * 0 - 256B address 0x54
>> + * 256B - 512B address 0x55
>> + * 512B - 768B address 0x56
>> + * 768B - 1024B address 0x57
>> + */
>> + eeprom: eeprom at 54 { /* u23 */
>> + compatible = "atmel,24c08";
>> + reg = <0x54>;
>> + };
>> + };
>> + i2c at 1 { /* i2c mw 74 0 2 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <1>;
>> + si5341: clock-generator1 at 36 { /* SI5341 - u69 */
>
> Drop the 1 on clock-generator1.
ok.
Thanks,
Michal
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 1/7] arm64: zynqmp: Add support for Xilinx zcu100-revC
@ 2018-02-01 17:33 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-02-01 17:33 UTC (permalink / raw)
To: Rob Herring, Michal Simek
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Michal Simek, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Mark Rutland,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On 1.2.2018 17:41, Rob Herring wrote:
> On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>> This board has 2GB of memory, i2c, sd, wifi sdio, spis, uarts, display
>> port and usbs.
>> Board is using fixed clocks because clock driver hasn't been merged yet.
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>> arch/arm64/boot/dts/xilinx/Makefile | 1 +
>> arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++++++++++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 298 ++++++++++++++++++++++
>> 3 files changed, 512 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
>> index eba179b23b17..7266a6a9c0cd 100644
>> --- a/arch/arm64/boot/dts/xilinx/Makefile
>> +++ b/arch/arm64/boot/dts/xilinx/Makefile
>> @@ -1,2 +1,3 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
>> new file mode 100644
>> index 000000000000..9c09baca7dd7
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
>> @@ -0,0 +1,213 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Clock specification for Xilinx ZynqMP
>> + *
>> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek@xilinx.com>
>> + */
>> +
>> +/ {
>> + clk100: clk100 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <100000000>;
>> + };
>> +
>> + clk125: clk125 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + };
>> +
>> + clk200: clk200 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <200000000>;
>> + };
>> +
>> + clk250: clk250 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <250000000>;
>> + };
>> +
>> + clk300: clk300 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <300000000>;
>> + };
>> +
>> + clk600: clk600 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <600000000>;
>> + };
>> +
>> + dp_aclk: clock0 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <100000000>;
>> + clock-accuracy = <100>;
>> + };
>> +
>> + dp_aud_clk: clock1 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <24576000>;
>> + clock-accuracy = <100>;
>> + };
>> +
>> + dpdma_clk: dpdma_clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0x0>;
>> + clock-frequency = <533000000>;
>> + };
>> +
>> + drm_clock: drm_clock {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0x0>;
>> + clock-frequency = <262750000>;
>> + clock-accuracy = <0x64>;
>> + };
>> +};
>> +
>> +&can0 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&can1 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&fpd_dma_chan1 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan2 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan3 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan4 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan5 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan6 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan7 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan8 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan1 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan2 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan3 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan4 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan5 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan6 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan7 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan8 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&gem0 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gem1 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gem2 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gem3 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gpio {
>> + clocks = <&clk100>;
>> +};
>> +
>> +&i2c0 {
>> + clocks = <&clk100>;
>> +};
>> +
>> +&i2c1 {
>> + clocks = <&clk100>;
>> +};
>> +
>> +&sata {
>> + clocks = <&clk250>;
>> +};
>> +
>> +&sdhci0 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&sdhci1 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&spi0 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&spi1 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&uart0 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&uart1 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&usb0 {
>> + clocks = <&clk250>, <&clk250>;
>> +};
>> +
>> +&usb1 {
>> + clocks = <&clk250>, <&clk250>;
>> +};
>> +
>> +&watchdog0 {
>> + clocks = <&clk250>;
>> +};
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> new file mode 100644
>> index 000000000000..01f5f95806d3
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> @@ -0,0 +1,298 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU100 revC
>> + *
>> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek@xilinx.com>
>> + * Nathalie Chan King Choy <nathalie@xilinx.com>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "zynqmp.dtsi"
>> +#include "zynqmp-clk.dtsi"
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + model = "ZynqMP ZCU100 RevC";
>> + compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
>
> Documented?
>
>> +
>> + aliases {
>> + gpio0 = &gpio;
>
> Drop this.
>
>> + i2c0 = &i2c1;
>> + rtc0 = &rtc;
>
> Is there more than one?
In programmable logic logic there can be plenty of them.
>
>> + serial0 = &uart1;
>> + serial1 = &uart0;
>> + serial2 = &dcc;
>> + spi0 = &spi0;
>> + spi1 = &spi1;
>
>> + usb0 = &usb0;
>> + usb1 = &usb1;
>
> Drop these.
>
>> + mmc0 = &sdhci0;
>> + mmc1 = &sdhci1;
>> + };
>> +
>> + chosen {
>> + bootargs = "earlycon";
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x80000000>;
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + autorepeat;
>> + sw4 {
>> + label = "sw4";
>> + gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
>> + linux,code = <KEY_POWER>;
>> + gpio-key,wakeup;
>> + autorepeat;
>> + };
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> + ds2 {
>> + label = "ds2";
>> + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "heartbeat";
>> + };
>> +
>> + ds3 {
>> + label = "ds3";
>> + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "phy0tx"; /* WLAN tx */
>> + default-state = "off";
>> + };
>> +
>> + ds4 {
>> + label = "ds4";
>> + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "phy0rx"; /* WLAN rx */
>> + default-state = "off";
>> + };
>> +
>> + ds5 {
>> + label = "ds5";
>> + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "bluetooth-power";
>> + };
>> +
>> + vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
>> + label = "vbus_det";
>> + gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
>> + default-state = "on";
>> + };
>> +
>> + bt_power {
>> + label = "bt_power";
>> + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
>> + default-state = "on";
>> + };
>> + };
>> +
>> + wmmcsdio_fixed: fixedregulator-mmcsdio {
>> + compatible = "regulator-fixed";
>> + regulator-name = "wmmcsdio_fixed";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + sdio_pwrseq: sdio_pwrseq {
>> + compatible = "mmc-pwrseq-simple";
>> + reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
>> + };
>> +};
>> +
>> +&dcc {
>> + status = "okay";
>> +};
>> +
>> +&gpio {
>> + status = "okay";
>> + gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
>> + "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
>> + "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
>> + "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
>> + "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
>> + "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
>> + "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
>> + "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
>> + "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
>> + "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
>> + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
>> + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
>> + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
>> + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
>> + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
>> + "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
>> + "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "";
>> +};
>> +
>> +&i2c1 {
>> + status = "okay";
>> + clock-frequency = <100000>;
>> + i2cswitch@75 { /* u11 */
>
> i2c-mux@75
>
>> + compatible = "nxp,pca9548";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x75>;
>> + i2csw_0: i2c@0 { /* i2c mw 75 0 1 */
>
> Linux commands for comments aren't relevant to dts files.
I was removing this from others and forget this one.
Just a note: It is u-boot command.
>
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /*
>> + * LSEXP_I2C0
>
> Is this a 96boards design? If so, using "label" and with defined names
> is somewhat standard for defining low speed connector ports (and for
> LEDs). That should also remove any need for using aliases for I2C and
> SPI. Look at hikey or db410c.
i2c, spi is easy
label = "HS-I2C2";
leds are also fine and fixed.
serial labeling depends on configuration. It means serial0 can be
LS-UART0 or 1 or PL based uart can be connected there.
Thanks,
Michal
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 1/7] arm64: zynqmp: Add support for Xilinx zcu100-revC
@ 2018-02-01 17:33 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-02-01 17:33 UTC (permalink / raw)
To: Rob Herring, Michal Simek
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Michal Simek, Masahiro Yamada,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, Will Deacon,
Catalin Marinas, Mark Rutland,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
On 1.2.2018 17:41, Rob Herring wrote:
> On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> wrote:
>> This board has 2GB of memory, i2c, sd, wifi sdio, spis, uarts, display
>> port and usbs.
>> Board is using fixed clocks because clock driver hasn't been merged yet.
>>
>> Signed-off-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>> ---
>>
>> arch/arm64/boot/dts/xilinx/Makefile | 1 +
>> arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++++++++++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 298 ++++++++++++++++++++++
>> 3 files changed, 512 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
>> index eba179b23b17..7266a6a9c0cd 100644
>> --- a/arch/arm64/boot/dts/xilinx/Makefile
>> +++ b/arch/arm64/boot/dts/xilinx/Makefile
>> @@ -1,2 +1,3 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
>> new file mode 100644
>> index 000000000000..9c09baca7dd7
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
>> @@ -0,0 +1,213 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Clock specification for Xilinx ZynqMP
>> + *
>> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>> + */
>> +
>> +/ {
>> + clk100: clk100 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <100000000>;
>> + };
>> +
>> + clk125: clk125 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + };
>> +
>> + clk200: clk200 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <200000000>;
>> + };
>> +
>> + clk250: clk250 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <250000000>;
>> + };
>> +
>> + clk300: clk300 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <300000000>;
>> + };
>> +
>> + clk600: clk600 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <600000000>;
>> + };
>> +
>> + dp_aclk: clock0 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <100000000>;
>> + clock-accuracy = <100>;
>> + };
>> +
>> + dp_aud_clk: clock1 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <24576000>;
>> + clock-accuracy = <100>;
>> + };
>> +
>> + dpdma_clk: dpdma_clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0x0>;
>> + clock-frequency = <533000000>;
>> + };
>> +
>> + drm_clock: drm_clock {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0x0>;
>> + clock-frequency = <262750000>;
>> + clock-accuracy = <0x64>;
>> + };
>> +};
>> +
>> +&can0 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&can1 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&fpd_dma_chan1 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan2 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan3 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan4 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan5 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan6 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan7 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan8 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan1 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan2 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan3 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan4 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan5 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan6 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan7 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan8 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&gem0 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gem1 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gem2 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gem3 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gpio {
>> + clocks = <&clk100>;
>> +};
>> +
>> +&i2c0 {
>> + clocks = <&clk100>;
>> +};
>> +
>> +&i2c1 {
>> + clocks = <&clk100>;
>> +};
>> +
>> +&sata {
>> + clocks = <&clk250>;
>> +};
>> +
>> +&sdhci0 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&sdhci1 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&spi0 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&spi1 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&uart0 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&uart1 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&usb0 {
>> + clocks = <&clk250>, <&clk250>;
>> +};
>> +
>> +&usb1 {
>> + clocks = <&clk250>, <&clk250>;
>> +};
>> +
>> +&watchdog0 {
>> + clocks = <&clk250>;
>> +};
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> new file mode 100644
>> index 000000000000..01f5f95806d3
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> @@ -0,0 +1,298 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU100 revC
>> + *
>> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>> + * Nathalie Chan King Choy <nathalie-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "zynqmp.dtsi"
>> +#include "zynqmp-clk.dtsi"
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + model = "ZynqMP ZCU100 RevC";
>> + compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
>
> Documented?
>
>> +
>> + aliases {
>> + gpio0 = &gpio;
>
> Drop this.
>
>> + i2c0 = &i2c1;
>> + rtc0 = &rtc;
>
> Is there more than one?
In programmable logic logic there can be plenty of them.
>
>> + serial0 = &uart1;
>> + serial1 = &uart0;
>> + serial2 = &dcc;
>> + spi0 = &spi0;
>> + spi1 = &spi1;
>
>> + usb0 = &usb0;
>> + usb1 = &usb1;
>
> Drop these.
>
>> + mmc0 = &sdhci0;
>> + mmc1 = &sdhci1;
>> + };
>> +
>> + chosen {
>> + bootargs = "earlycon";
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x80000000>;
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + autorepeat;
>> + sw4 {
>> + label = "sw4";
>> + gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
>> + linux,code = <KEY_POWER>;
>> + gpio-key,wakeup;
>> + autorepeat;
>> + };
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> + ds2 {
>> + label = "ds2";
>> + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "heartbeat";
>> + };
>> +
>> + ds3 {
>> + label = "ds3";
>> + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "phy0tx"; /* WLAN tx */
>> + default-state = "off";
>> + };
>> +
>> + ds4 {
>> + label = "ds4";
>> + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "phy0rx"; /* WLAN rx */
>> + default-state = "off";
>> + };
>> +
>> + ds5 {
>> + label = "ds5";
>> + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "bluetooth-power";
>> + };
>> +
>> + vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
>> + label = "vbus_det";
>> + gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
>> + default-state = "on";
>> + };
>> +
>> + bt_power {
>> + label = "bt_power";
>> + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
>> + default-state = "on";
>> + };
>> + };
>> +
>> + wmmcsdio_fixed: fixedregulator-mmcsdio {
>> + compatible = "regulator-fixed";
>> + regulator-name = "wmmcsdio_fixed";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + sdio_pwrseq: sdio_pwrseq {
>> + compatible = "mmc-pwrseq-simple";
>> + reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
>> + };
>> +};
>> +
>> +&dcc {
>> + status = "okay";
>> +};
>> +
>> +&gpio {
>> + status = "okay";
>> + gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
>> + "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
>> + "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
>> + "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
>> + "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
>> + "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
>> + "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
>> + "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
>> + "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
>> + "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
>> + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
>> + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
>> + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
>> + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
>> + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
>> + "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
>> + "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "";
>> +};
>> +
>> +&i2c1 {
>> + status = "okay";
>> + clock-frequency = <100000>;
>> + i2cswitch@75 { /* u11 */
>
> i2c-mux@75
>
>> + compatible = "nxp,pca9548";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x75>;
>> + i2csw_0: i2c@0 { /* i2c mw 75 0 1 */
>
> Linux commands for comments aren't relevant to dts files.
I was removing this from others and forget this one.
Just a note: It is u-boot command.
>
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /*
>> + * LSEXP_I2C0
>
> Is this a 96boards design? If so, using "label" and with defined names
> is somewhat standard for defining low speed connector ports (and for
> LEDs). That should also remove any need for using aliases for I2C and
> SPI. Look at hikey or db410c.
i2c, spi is easy
label = "HS-I2C2";
leds are also fine and fixed.
serial labeling depends on configuration. It means serial0 can be
LS-UART0 or 1 or PL based uart can be connected there.
Thanks,
Michal
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^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 1/7] arm64: zynqmp: Add support for Xilinx zcu100-revC
@ 2018-02-01 17:33 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-02-01 17:33 UTC (permalink / raw)
To: linux-arm-kernel
On 1.2.2018 17:41, Rob Herring wrote:
> On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>> This board has 2GB of memory, i2c, sd, wifi sdio, spis, uarts, display
>> port and usbs.
>> Board is using fixed clocks because clock driver hasn't been merged yet.
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>> arch/arm64/boot/dts/xilinx/Makefile | 1 +
>> arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi | 213 ++++++++++++++++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 298 ++++++++++++++++++++++
>> 3 files changed, 512 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
>> index eba179b23b17..7266a6a9c0cd 100644
>> --- a/arch/arm64/boot/dts/xilinx/Makefile
>> +++ b/arch/arm64/boot/dts/xilinx/Makefile
>> @@ -1,2 +1,3 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
>> new file mode 100644
>> index 000000000000..9c09baca7dd7
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi
>> @@ -0,0 +1,213 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Clock specification for Xilinx ZynqMP
>> + *
>> + * (C) Copyright 2015 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek@xilinx.com>
>> + */
>> +
>> +/ {
>> + clk100: clk100 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <100000000>;
>> + };
>> +
>> + clk125: clk125 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <125000000>;
>> + };
>> +
>> + clk200: clk200 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <200000000>;
>> + };
>> +
>> + clk250: clk250 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <250000000>;
>> + };
>> +
>> + clk300: clk300 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <300000000>;
>> + };
>> +
>> + clk600: clk600 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <600000000>;
>> + };
>> +
>> + dp_aclk: clock0 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <100000000>;
>> + clock-accuracy = <100>;
>> + };
>> +
>> + dp_aud_clk: clock1 {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <24576000>;
>> + clock-accuracy = <100>;
>> + };
>> +
>> + dpdma_clk: dpdma_clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0x0>;
>> + clock-frequency = <533000000>;
>> + };
>> +
>> + drm_clock: drm_clock {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0x0>;
>> + clock-frequency = <262750000>;
>> + clock-accuracy = <0x64>;
>> + };
>> +};
>> +
>> +&can0 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&can1 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&fpd_dma_chan1 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan2 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan3 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan4 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan5 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan6 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan7 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&fpd_dma_chan8 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan1 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan2 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan3 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan4 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan5 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan6 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan7 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&lpd_dma_chan8 {
>> + clocks = <&clk600>, <&clk100>;
>> +};
>> +
>> +&gem0 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gem1 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gem2 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gem3 {
>> + clocks = <&clk125>, <&clk125>, <&clk125>;
>> +};
>> +
>> +&gpio {
>> + clocks = <&clk100>;
>> +};
>> +
>> +&i2c0 {
>> + clocks = <&clk100>;
>> +};
>> +
>> +&i2c1 {
>> + clocks = <&clk100>;
>> +};
>> +
>> +&sata {
>> + clocks = <&clk250>;
>> +};
>> +
>> +&sdhci0 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&sdhci1 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&spi0 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&spi1 {
>> + clocks = <&clk200 &clk200>;
>> +};
>> +
>> +&uart0 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&uart1 {
>> + clocks = <&clk100 &clk100>;
>> +};
>> +
>> +&usb0 {
>> + clocks = <&clk250>, <&clk250>;
>> +};
>> +
>> +&usb1 {
>> + clocks = <&clk250>, <&clk250>;
>> +};
>> +
>> +&watchdog0 {
>> + clocks = <&clk250>;
>> +};
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> new file mode 100644
>> index 000000000000..01f5f95806d3
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
>> @@ -0,0 +1,298 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU100 revC
>> + *
>> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek@xilinx.com>
>> + * Nathalie Chan King Choy <nathalie@xilinx.com>
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "zynqmp.dtsi"
>> +#include "zynqmp-clk.dtsi"
>> +#include <dt-bindings/input/input.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + model = "ZynqMP ZCU100 RevC";
>> + compatible = "xlnx,zynqmp-zcu100-revC", "xlnx,zynqmp-zcu100", "xlnx,zynqmp";
>
> Documented?
>
>> +
>> + aliases {
>> + gpio0 = &gpio;
>
> Drop this.
>
>> + i2c0 = &i2c1;
>> + rtc0 = &rtc;
>
> Is there more than one?
In programmable logic logic there can be plenty of them.
>
>> + serial0 = &uart1;
>> + serial1 = &uart0;
>> + serial2 = &dcc;
>> + spi0 = &spi0;
>> + spi1 = &spi1;
>
>> + usb0 = &usb0;
>> + usb1 = &usb1;
>
> Drop these.
>
>> + mmc0 = &sdhci0;
>> + mmc1 = &sdhci1;
>> + };
>> +
>> + chosen {
>> + bootargs = "earlycon";
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + memory at 0 {
>> + device_type = "memory";
>> + reg = <0x0 0x0 0x0 0x80000000>;
>> + };
>> +
>> + gpio-keys {
>> + compatible = "gpio-keys";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + autorepeat;
>> + sw4 {
>> + label = "sw4";
>> + gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
>> + linux,code = <KEY_POWER>;
>> + gpio-key,wakeup;
>> + autorepeat;
>> + };
>> + };
>> +
>> + leds {
>> + compatible = "gpio-leds";
>> + ds2 {
>> + label = "ds2";
>> + gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "heartbeat";
>> + };
>> +
>> + ds3 {
>> + label = "ds3";
>> + gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "phy0tx"; /* WLAN tx */
>> + default-state = "off";
>> + };
>> +
>> + ds4 {
>> + label = "ds4";
>> + gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "phy0rx"; /* WLAN rx */
>> + default-state = "off";
>> + };
>> +
>> + ds5 {
>> + label = "ds5";
>> + gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
>> + linux,default-trigger = "bluetooth-power";
>> + };
>> +
>> + vbus_det { /* U5 USB5744 VBUS detection via MIO25 */
>> + label = "vbus_det";
>> + gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
>> + default-state = "on";
>> + };
>> +
>> + bt_power {
>> + label = "bt_power";
>> + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
>> + default-state = "on";
>> + };
>> + };
>> +
>> + wmmcsdio_fixed: fixedregulator-mmcsdio {
>> + compatible = "regulator-fixed";
>> + regulator-name = "wmmcsdio_fixed";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + sdio_pwrseq: sdio_pwrseq {
>> + compatible = "mmc-pwrseq-simple";
>> + reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
>> + };
>> +};
>> +
>> +&dcc {
>> + status = "okay";
>> +};
>> +
>> +&gpio {
>> + status = "okay";
>> + gpio-line-names = "UART1_TX", "UART1_RX", "UART0_RX", "UART0_TX", "I2C1_SCL",
>> + "I2C1_SDA", "SPI1_SCLK", "WLAN_EN", "BT_EN", "SPI1_CS",
>> + "SPI1_MISO", "SPI1_MOSI", "I2C_MUX_RESET", "SD0_DAT0", "SD0_DAT1",
>> + "SD0_DAT2", "SD0_DAT3", "PS_LED3", "PS_LED2", "PS_LED1",
>> + "PS_LED0", "SD0_CMD", "SD0_CLK", "GPIO_PB", "SD0_DETECT",
>> + "VBUS_DET", "POWER_INT", "DP_AUX", "DP_HPD", "DP_OE",
>> + "DP_AUX_IN", "INA226_ALERT", "PS_FP_PWR_EN", "PL_PWR_EN", "POWER_KILL",
>> + "", "GPIO-A", "GPIO-B", "SPI0_SCLK", "GPIO-C",
>> + "GPIO-D", "SPI0_CS", "SPI0_MISO", "SPI_MOSI", "GPIO-E",
>> + "GPIO-F", "SD1_D0", "SD1_D1", "SD1_D2", "SD1_D3",
>> + "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2",
>> + "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3",
>> + "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK",
>> + "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1",
>> + "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6",
>> + "USB_DATA7", "WLAN_IRQ", "PMIC_IRQ", /* MIO end and EMIO start */
>> + "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "", "", "", "", "", "", "",
>> + "", "", "", "";
>> +};
>> +
>> +&i2c1 {
>> + status = "okay";
>> + clock-frequency = <100000>;
>> + i2cswitch at 75 { /* u11 */
>
> i2c-mux at 75
>
>> + compatible = "nxp,pca9548";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x75>;
>> + i2csw_0: i2c at 0 { /* i2c mw 75 0 1 */
>
> Linux commands for comments aren't relevant to dts files.
I was removing this from others and forget this one.
Just a note: It is u-boot command.
>
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /*
>> + * LSEXP_I2C0
>
> Is this a 96boards design? If so, using "label" and with defined names
> is somewhat standard for defining low speed connector ports (and for
> LEDs). That should also remove any need for using aliases for I2C and
> SPI. Look at hikey or db410c.
i2c, spi is easy
label = "HS-I2C2";
leds are also fine and fixed.
serial labeling depends on configuration. It means serial0 can be
LS-UART0 or 1 or PL based uart can be connected there.
Thanks,
Michal
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102
@ 2018-02-06 14:01 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-02-06 14:01 UTC (permalink / raw)
To: Rob Herring, Michal Simek
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Michal Simek, Masahiro Yamada, linux-kernel, Arnd Bergmann,
Will Deacon, Catalin Marinas, Mark Rutland,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Rob,
On 1.2.2018 17:46, Rob Herring wrote:
> On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>> This patch is adding revA, revB and rev1.0. There are also other
>> revisions between which should be backward compatible with previous
>> versions. Unfortunately all revs are still in use.
>
> Similar comments to the 1st patch. I won't repeat them here.
>
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>> arch/arm64/boot/dts/xilinx/Makefile | 3 +
>> .../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
>> 4 files changed, 637 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
>> index 7266a6a9c0cd..24e3ce801304 100644
>> --- a/arch/arm64/boot/dts/xilinx/Makefile
>> +++ b/arch/arm64/boot/dts/xilinx/Makefile
>> @@ -1,3 +1,6 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> new file mode 100644
>> index 000000000000..4b7477795fbd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> @@ -0,0 +1,36 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU102 Rev1.0
>> + *
>> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek@xilinx.com>
>> + */
>> +
>> +#include "zynqmp-zcu102-revB.dts"
>> +
>> +/ {
>> + model = "ZynqMP ZCU102 Rev1.0";
>> + compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
>
> Documented?
Still waiting what exactly should be documented and where this should be
added.
I have seen that broadcom was doing this properly for arm32
(bindings/arm/bcm) but for example brcm,stingray is not documented.
I am happy to document our strings but I would like to do it just once
when I know proper location and style.
>
>> +};
>> +
>> +&eeprom {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + board_sn: board_sn@0 {
>
> Use '-' rather than '_' in node and property names.
I will change this in node name even based on spec and Table 2.1
underscore is also permitted. Maybe priorities should be reflected in
that table too.
>> + i2cswitch@75 { /* u60 */
>> + compatible = "nxp,pca9544";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x75>;
>> + i2c@0 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /* PS_PMBUS */
>> + ina226@40 { /* u76 */
>
> Should be what the device does, not part numbers if possible. Standard
> names are defined in the DT spec (additions welcome).
I have suggested power-monitor name for this case. Pull request #15 for
that.
Thanks,
Michal
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102
@ 2018-02-06 14:01 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-02-06 14:01 UTC (permalink / raw)
To: Rob Herring, Michal Simek
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Michal Simek, Masahiro Yamada,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann, Will Deacon,
Catalin Marinas, Mark Rutland,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
Hi Rob,
On 1.2.2018 17:46, Rob Herring wrote:
> On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> wrote:
>> This patch is adding revA, revB and rev1.0. There are also other
>> revisions between which should be backward compatible with previous
>> versions. Unfortunately all revs are still in use.
>
> Similar comments to the 1st patch. I won't repeat them here.
>
>>
>> Signed-off-by: Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>> ---
>>
>> arch/arm64/boot/dts/xilinx/Makefile | 3 +
>> .../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
>> 4 files changed, 637 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
>> index 7266a6a9c0cd..24e3ce801304 100644
>> --- a/arch/arm64/boot/dts/xilinx/Makefile
>> +++ b/arch/arm64/boot/dts/xilinx/Makefile
>> @@ -1,3 +1,6 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> new file mode 100644
>> index 000000000000..4b7477795fbd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> @@ -0,0 +1,36 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU102 Rev1.0
>> + *
>> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org>
>> + */
>> +
>> +#include "zynqmp-zcu102-revB.dts"
>> +
>> +/ {
>> + model = "ZynqMP ZCU102 Rev1.0";
>> + compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
>
> Documented?
Still waiting what exactly should be documented and where this should be
added.
I have seen that broadcom was doing this properly for arm32
(bindings/arm/bcm) but for example brcm,stingray is not documented.
I am happy to document our strings but I would like to do it just once
when I know proper location and style.
>
>> +};
>> +
>> +&eeprom {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + board_sn: board_sn@0 {
>
> Use '-' rather than '_' in node and property names.
I will change this in node name even based on spec and Table 2.1
underscore is also permitted. Maybe priorities should be reflected in
that table too.
>> + i2cswitch@75 { /* u60 */
>> + compatible = "nxp,pca9544";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x75>;
>> + i2c@0 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /* PS_PMBUS */
>> + ina226@40 { /* u76 */
>
> Should be what the device does, not part numbers if possible. Standard
> names are defined in the DT spec (additions welcome).
I have suggested power-monitor name for this case. Pull request #15 for
that.
Thanks,
Michal
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^ permalink raw reply [flat|nested] 37+ messages in thread
* [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102
@ 2018-02-06 14:01 ` Michal Simek
0 siblings, 0 replies; 37+ messages in thread
From: Michal Simek @ 2018-02-06 14:01 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rob,
On 1.2.2018 17:46, Rob Herring wrote:
> On Fri, Jan 19, 2018 at 6:55 AM, Michal Simek <michal.simek@xilinx.com> wrote:
>> This patch is adding revA, revB and rev1.0. There are also other
>> revisions between which should be backward compatible with previous
>> versions. Unfortunately all revs are still in use.
>
> Similar comments to the 1st patch. I won't repeat them here.
>
>>
>> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
>> ---
>>
>> arch/arm64/boot/dts/xilinx/Makefile | 3 +
>> .../arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts | 36 ++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 556 +++++++++++++++++++++
>> arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts | 42 ++
>> 4 files changed, 637 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
>>
>> diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
>> index 7266a6a9c0cd..24e3ce801304 100644
>> --- a/arch/arm64/boot/dts/xilinx/Makefile
>> +++ b/arch/arm64/boot/dts/xilinx/Makefile
>> @@ -1,3 +1,6 @@
>> # SPDX-License-Identifier: GPL-2.0
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ep108.dtb
>> dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
>> +dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> new file mode 100644
>> index 000000000000..4b7477795fbd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts
>> @@ -0,0 +1,36 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * dts file for Xilinx ZynqMP ZCU102 Rev1.0
>> + *
>> + * (C) Copyright 2016 - 2018, Xilinx, Inc.
>> + *
>> + * Michal Simek <michal.simek@xilinx.com>
>> + */
>> +
>> +#include "zynqmp-zcu102-revB.dts"
>> +
>> +/ {
>> + model = "ZynqMP ZCU102 Rev1.0";
>> + compatible = "xlnx,zynqmp-zcu102-rev1.0", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
>
> Documented?
Still waiting what exactly should be documented and where this should be
added.
I have seen that broadcom was doing this properly for arm32
(bindings/arm/bcm) but for example brcm,stingray is not documented.
I am happy to document our strings but I would like to do it just once
when I know proper location and style.
>
>> +};
>> +
>> +&eeprom {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + board_sn: board_sn at 0 {
>
> Use '-' rather than '_' in node and property names.
I will change this in node name even based on spec and Table 2.1
underscore is also permitted. Maybe priorities should be reflected in
that table too.
>> + i2cswitch at 75 { /* u60 */
>> + compatible = "nxp,pca9544";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x75>;
>> + i2c at 0 { /* i2c mw 75 0 1 */
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0>;
>> + /* PS_PMBUS */
>> + ina226 at 40 { /* u76 */
>
> Should be what the device does, not part numbers if possible. Standard
> names are defined in the DT spec (additions welcome).
I have suggested power-monitor name for this case. Pull request #15 for
that.
Thanks,
Michal
^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2018-02-06 14:02 UTC | newest]
Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-19 12:55 [PATCH 0/7] arm64: zynqmp: Add support for existing Xilinx ZynqMP based boards Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-01-19 12:55 ` [PATCH 1/7] arm64: zynqmp: Add support for Xilinx zcu100-revC Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-02-01 16:41 ` Rob Herring
2018-02-01 16:41 ` Rob Herring
2018-02-01 16:41 ` Rob Herring
2018-02-01 17:33 ` Michal Simek
2018-02-01 17:33 ` Michal Simek
2018-02-01 17:33 ` Michal Simek
2018-01-19 12:55 ` [PATCH 2/7] arm64: zynqmp: Add support for Xilinx zcu102 Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-02-01 16:46 ` Rob Herring
2018-02-01 16:46 ` Rob Herring
2018-02-01 16:46 ` Rob Herring
2018-02-01 17:26 ` Michal Simek
2018-02-01 17:26 ` Michal Simek
2018-02-01 17:26 ` Michal Simek
2018-02-06 14:01 ` Michal Simek
2018-02-06 14:01 ` Michal Simek
2018-02-06 14:01 ` Michal Simek
2018-01-19 12:55 ` [PATCH 3/7] arm64: zynqmp: Add support for Xilinx zcu104-revA Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-01-19 12:55 ` [PATCH 4/7] arm64: zynqmp: Add support for Xilinx zcu106-revA Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-01-19 12:55 ` [PATCH 5/7] arm64: zynqmp: Add support for Xilinx zcu111-revA Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-01-19 12:55 ` [PATCH 6/7] arm64: zynqmp: Add support for Xilinx zc12XX boards Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-01-19 12:55 ` [PATCH 7/7] arm64: zynqmp: Add support for Xilinx zc1751 Michal Simek
2018-01-19 12:55 ` Michal Simek
2018-01-19 12:55 ` Michal Simek
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