* [PATCH] drm/i915: Protect DDI port to DPLL map from theoretical race.
@ 2017-12-15 22:35 Rodrigo Vivi
2017-12-15 22:36 ` ✗ Fi.CI.BAT: failure for " Patchwork
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Rodrigo Vivi @ 2017-12-15 22:35 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Maarten, Lankhorst, Rodrigo Vivi
In case we have multiple modesets for different connectors
happening in parallel we could have a race on the RMW on these
shared registers.
This possibility was initially raised by Paulo when reviewing
commit '555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")'
but the original possibility comes from commit '5416d871136d
("drm/i915/skl: Set the eDP link rate on DPLL0")'. Or maybe
later when atomic commits entered into picture.
Apparently the discussion around this topic showed that the
right solution would be on serializing the atomic commits in
a way that we don't have the possibility of races here since
if that parallel modeset happenings apparently many other
things will be on fire.
Code is there since SKL and there was no report of issue,
but since we never looked back to that serialization possibility,
and also we don't have an igt case for that it is better to at
least protect this corner.
Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Fixes: 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")
Fixes: 5416d871136d ("drm/i915/skl: Set the eDP link rate on DPLL0")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst maarten.lankhorst@linux.intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8467a797a70b..eb816ff2fa77 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2095,6 +2095,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
if (WARN_ON(!pll))
return;
+ mutex_lock(&dev_priv->dpll_lock);
+
if (IS_CANNONLAKE(dev_priv)) {
/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
val = I915_READ(DPCLKA_CFGCR0);
@@ -2124,6 +2126,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
} else if (INTEL_INFO(dev_priv)->gen < 9) {
I915_WRITE_LOG(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
}
+
+ mutex_unlock(&dev_priv->dpll_lock);
}
static void intel_ddi_clk_disable(struct intel_encoder *encoder)
--
2.13.6
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Protect DDI port to DPLL map from theoretical race.
2017-12-15 22:35 [PATCH] drm/i915: Protect DDI port to DPLL map from theoretical race Rodrigo Vivi
@ 2017-12-15 22:36 ` Patchwork
2017-12-15 22:43 ` [PATCH v2] " Rodrigo Vivi
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2017-12-15 22:36 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Protect DDI port to DPLL map from theoretical race.
URL : https://patchwork.freedesktop.org/series/35446/
State : failure
== Summary ==
Applying: drm/i915: Protect DDI port to DPLL map from theoretical race.
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/intel_ddi.c).
error: could not build fake ancestor
Patch failed at 0001 drm/i915: Protect DDI port to DPLL map from theoretical race.
The copy of the patch that failed is found in: .git/rebase-apply/patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2] drm/i915: Protect DDI port to DPLL map from theoretical race.
2017-12-15 22:35 [PATCH] drm/i915: Protect DDI port to DPLL map from theoretical race Rodrigo Vivi
2017-12-15 22:36 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2017-12-15 22:43 ` Rodrigo Vivi
2017-12-18 10:40 ` Maarten Lankhorst
2017-12-15 23:04 ` ✓ Fi.CI.BAT: success for drm/i915: Protect DDI port to DPLL map from theoretical race. (rev2) Patchwork
` (2 subsequent siblings)
4 siblings, 1 reply; 8+ messages in thread
From: Rodrigo Vivi @ 2017-12-15 22:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni, Maarten, Lankhorst, Rodrigo Vivi
In case we have multiple modesets for different connectors
happening in parallel we could have a race on the RMW on these
shared registers.
This possibility was initially raised by Paulo when reviewing
commit '555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")'
but the original possibility comes from commit '5416d871136d
("drm/i915/skl: Set the eDP link rate on DPLL0")'. Or maybe
later when atomic commits entered into picture.
Apparently the discussion around this topic showed that the
right solution would be on serializing the atomic commits in
a way that we don't have the possibility of races here since
if that parallel modeset happenings apparently many other
things will be on fire.
Code is there since SKL and there was no report of issue,
but since we never looked back to that serialization possibility,
and also we don't have an igt case for that it is better to at
least protect this corner.
Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Fixes: 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")
Fixes: 5416d871136d ("drm/i915/skl: Set the eDP link rate on DPLL0")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst maarten.lankhorst@linux.intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 369f780588fb..f624ba8e23be 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2095,6 +2095,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
if (WARN_ON(!pll))
return;
+ mutex_lock(&dev_priv->dpll_lock);
+
if (IS_CANNONLAKE(dev_priv)) {
/* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
val = I915_READ(DPCLKA_CFGCR0);
@@ -2124,6 +2126,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
} else if (INTEL_INFO(dev_priv)->gen < 9) {
I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
}
+
+ mutex_unlock(&dev_priv->dpll_lock);
}
static void intel_ddi_clk_disable(struct intel_encoder *encoder)
--
2.13.6
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Protect DDI port to DPLL map from theoretical race. (rev2)
2017-12-15 22:35 [PATCH] drm/i915: Protect DDI port to DPLL map from theoretical race Rodrigo Vivi
2017-12-15 22:36 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-12-15 22:43 ` [PATCH v2] " Rodrigo Vivi
@ 2017-12-15 23:04 ` Patchwork
2017-12-16 0:08 ` ✗ Fi.CI.IGT: failure " Patchwork
2017-12-20 17:32 ` [PATCH] drm/i915: Protect DDI port to DPLL map from theoretical race Ausmus, James
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2017-12-15 23:04 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Protect DDI port to DPLL map from theoretical race. (rev2)
URL : https://patchwork.freedesktop.org/series/35446/
State : success
== Summary ==
Series 35446v2 drm/i915: Protect DDI port to DPLL map from theoretical race.
https://patchwork.freedesktop.org/api/1.0/series/35446/revisions/2/mbox/
Test debugfs_test:
Subgroup read_all_entries:
dmesg-fail -> PASS (fi-elk-e7500) fdo#103989 +1
Test gem_sync:
Subgroup basic-all:
dmesg-fail -> FAIL (fi-blb-e6850) fdo#104259
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
dmesg-warn -> PASS (fi-kbl-r) fdo#104172 +1
Subgroup suspend-read-crc-pipe-b:
incomplete -> PASS (fi-snb-2520m) fdo#103713
fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
fdo#104259 https://bugs.freedesktop.org/show_bug.cgi?id=104259
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:431s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:436s
fi-blb-e6850 total:288 pass:222 dwarn:1 dfail:0 fail:1 skip:64 time:388s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:504s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:280s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:498s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:502s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:482s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:480s
fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:533s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:407s
fi-hsw-4770r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:414s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:394s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:479s
fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:431s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:478s
fi-kbl-7560u total:288 pass:268 dwarn:1 dfail:0 fail:0 skip:19 time:528s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:470s
fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:523s
fi-pnv-d510 total:288 pass:221 dwarn:1 dfail:0 fail:1 skip:65 time:592s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:440s
fi-skl-6600u total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:530s
fi-skl-6700hq total:288 pass:261 dwarn:1 dfail:0 fail:0 skip:26 time:557s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:489s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:447s
fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:541s
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:407s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:587s
fi-cnl-y total:224 pass:199 dwarn:0 dfail:0 fail:0 skip:24
fi-glk-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:480s
fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:509s
e62100b705b3eb079c6acd60c25a8d54d92b7dac drm-tip: 2017y-12m-15d-21h-18m-47s UTC integration manifest
32b773f75cb9 drm/i915: Protect DDI port to DPLL map from theoretical race.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7513/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: Protect DDI port to DPLL map from theoretical race. (rev2)
2017-12-15 22:35 [PATCH] drm/i915: Protect DDI port to DPLL map from theoretical race Rodrigo Vivi
` (2 preceding siblings ...)
2017-12-15 23:04 ` ✓ Fi.CI.BAT: success for drm/i915: Protect DDI port to DPLL map from theoretical race. (rev2) Patchwork
@ 2017-12-16 0:08 ` Patchwork
2017-12-20 17:32 ` [PATCH] drm/i915: Protect DDI port to DPLL map from theoretical race Ausmus, James
4 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2017-12-16 0:08 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Protect DDI port to DPLL map from theoretical race. (rev2)
URL : https://patchwork.freedesktop.org/series/35446/
State : failure
== Summary ==
Warning: bzip CI_DRM_3525/shard-glkb6/results10.json.bz2 wasn't in correct JSON format
Test gem_softpin:
Subgroup noreloc-s3:
pass -> SKIP (shard-snb) fdo#102365
Test gem_eio:
Subgroup in-flight:
dmesg-warn -> PASS (shard-snb) fdo#104058
Test gem_mmap_gtt:
Subgroup basic-wc:
pass -> FAIL (shard-hsw)
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
pass -> FAIL (shard-snb) fdo#101623
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#104058 https://bugs.freedesktop.org/show_bug.cgi?id=104058
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
shard-hsw total:2712 pass:1536 dwarn:1 dfail:0 fail:11 skip:1164 time:9441s
shard-snb total:2712 pass:1307 dwarn:1 dfail:0 fail:12 skip:1392 time:7961s
Blacklisted hosts:
shard-apl total:2712 pass:1685 dwarn:1 dfail:0 fail:25 skip:1001 time:13832s
shard-kbl total:2712 pass:1804 dwarn:1 dfail:0 fail:28 skip:879 time:11169s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7513/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] drm/i915: Protect DDI port to DPLL map from theoretical race.
2017-12-15 22:43 ` [PATCH v2] " Rodrigo Vivi
@ 2017-12-18 10:40 ` Maarten Lankhorst
2017-12-18 22:36 ` Rodrigo Vivi
0 siblings, 1 reply; 8+ messages in thread
From: Maarten Lankhorst @ 2017-12-18 10:40 UTC (permalink / raw)
To: Rodrigo Vivi, intel-gfx; +Cc: Paulo Zanoni
Op 15-12-17 om 23:43 schreef Rodrigo Vivi:
> In case we have multiple modesets for different connectors
> happening in parallel we could have a race on the RMW on these
> shared registers.
>
> This possibility was initially raised by Paulo when reviewing
> commit '555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")'
> but the original possibility comes from commit '5416d871136d
> ("drm/i915/skl: Set the eDP link rate on DPLL0")'. Or maybe
> later when atomic commits entered into picture.
>
> Apparently the discussion around this topic showed that the
> right solution would be on serializing the atomic commits in
> a way that we don't have the possibility of races here since
> if that parallel modeset happenings apparently many other
> things will be on fire.
>
> Code is there since SKL and there was no report of issue,
> but since we never looked back to that serialization possibility,
> and also we don't have an igt case for that it is better to at
> least protect this corner.
>
> Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Fixes: 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")
> Fixes: 5416d871136d ("drm/i915/skl: Set the eDP link rate on DPLL0")
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Maarten Lankhorst maarten.lankhorst@linux.intel.com
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 369f780588fb..f624ba8e23be 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2095,6 +2095,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
> if (WARN_ON(!pll))
> return;
>
> + mutex_lock(&dev_priv->dpll_lock);
> +
> if (IS_CANNONLAKE(dev_priv)) {
> /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
> val = I915_READ(DPCLKA_CFGCR0);
> @@ -2124,6 +2126,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
> } else if (INTEL_INFO(dev_priv)->gen < 9) {
> I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
> }
> +
> + mutex_unlock(&dev_priv->dpll_lock);
> }
>
> static void intel_ddi_clk_disable(struct intel_encoder *encoder)
What is the difference between v1 and this? Changelog would be nice, or a comment that you resent it. :)
Patch looks sane, so Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2] drm/i915: Protect DDI port to DPLL map from theoretical race.
2017-12-18 10:40 ` Maarten Lankhorst
@ 2017-12-18 22:36 ` Rodrigo Vivi
0 siblings, 0 replies; 8+ messages in thread
From: Rodrigo Vivi @ 2017-12-18 22:36 UTC (permalink / raw)
To: Maarten Lankhorst; +Cc: intel-gfx, Paulo Zanoni
On Mon, Dec 18, 2017 at 10:40:02AM +0000, Maarten Lankhorst wrote:
> Op 15-12-17 om 23:43 schreef Rodrigo Vivi:
> > In case we have multiple modesets for different connectors
> > happening in parallel we could have a race on the RMW on these
> > shared registers.
> >
> > This possibility was initially raised by Paulo when reviewing
> > commit '555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")'
> > but the original possibility comes from commit '5416d871136d
> > ("drm/i915/skl: Set the eDP link rate on DPLL0")'. Or maybe
> > later when atomic commits entered into picture.
> >
> > Apparently the discussion around this topic showed that the
> > right solution would be on serializing the atomic commits in
> > a way that we don't have the possibility of races here since
> > if that parallel modeset happenings apparently many other
> > things will be on fire.
> >
> > Code is there since SKL and there was no report of issue,
> > but since we never looked back to that serialization possibility,
> > and also we don't have an igt case for that it is better to at
> > least protect this corner.
> >
> > Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Fixes: 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")
> > Fixes: 5416d871136d ("drm/i915/skl: Set the eDP link rate on DPLL0")
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Maarten Lankhorst maarten.lankhorst@linux.intel.com
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index 369f780588fb..f624ba8e23be 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2095,6 +2095,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
> > if (WARN_ON(!pll))
> > return;
> >
> > + mutex_lock(&dev_priv->dpll_lock);
> > +
> > if (IS_CANNONLAKE(dev_priv)) {
> > /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
> > val = I915_READ(DPCLKA_CFGCR0);
> > @@ -2124,6 +2126,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
> > } else if (INTEL_INFO(dev_priv)->gen < 9) {
> > I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
> > }
> > +
> > + mutex_unlock(&dev_priv->dpll_lock);
> > }
> >
> > static void intel_ddi_clk_disable(struct intel_encoder *encoder)
>
> What is the difference between v1 and this? Changelog would be nice, or a comment that you resent it. :)
no difference at all... but I forgot to add the mention of the rebase on the right branch.
>
> Patch looks sane, so Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Thanks... Merging this now...
>
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915: Protect DDI port to DPLL map from theoretical race.
2017-12-15 22:35 [PATCH] drm/i915: Protect DDI port to DPLL map from theoretical race Rodrigo Vivi
` (3 preceding siblings ...)
2017-12-16 0:08 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2017-12-20 17:32 ` Ausmus, James
4 siblings, 0 replies; 8+ messages in thread
From: Ausmus, James @ 2017-12-20 17:32 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: Intel GFX, Paulo Zanoni
On Fri, Dec 15, 2017 at 2:35 PM, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> In case we have multiple modesets for different connectors
> happening in parallel we could have a race on the RMW on these
> shared registers.
>
> This possibility was initially raised by Paulo when reviewing
> commit '555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")'
> but the original possibility comes from commit '5416d871136d
> ("drm/i915/skl: Set the eDP link rate on DPLL0")'. Or maybe
> later when atomic commits entered into picture.
>
> Apparently the discussion around this topic showed that the
> right solution would be on serializing the atomic commits in
> a way that we don't have the possibility of races here since
> if that parallel modeset happenings apparently many other
> things will be on fire.
>
> Code is there since SKL and there was no report of issue,
> but since we never looked back to that serialization possibility,
> and also we don't have an igt case for that it is better to at
> least protect this corner.
>
> Suggested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Fixes: 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")
> Fixes: 5416d871136d ("drm/i915/skl: Set the eDP link rate on DPLL0")
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Maarten Lankhorst maarten.lankhorst@linux.intel.com
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 8467a797a70b..eb816ff2fa77 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2095,6 +2095,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
Shouldn't we also do the same in intel_ddi_clk_disable?
> if (WARN_ON(!pll))
> return;
>
> + mutex_lock(&dev_priv->dpll_lock);
> +
> if (IS_CANNONLAKE(dev_priv)) {
> /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
> val = I915_READ(DPCLKA_CFGCR0);
> @@ -2124,6 +2126,8 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
> } else if (INTEL_INFO(dev_priv)->gen < 9) {
> I915_WRITE_LOG(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
> }
> +
> + mutex_unlock(&dev_priv->dpll_lock);
> }
>
> static void intel_ddi_clk_disable(struct intel_encoder *encoder)
> --
> 2.13.6
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
James Ausmus
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2017-12-20 17:33 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-12-15 22:35 [PATCH] drm/i915: Protect DDI port to DPLL map from theoretical race Rodrigo Vivi
2017-12-15 22:36 ` ✗ Fi.CI.BAT: failure for " Patchwork
2017-12-15 22:43 ` [PATCH v2] " Rodrigo Vivi
2017-12-18 10:40 ` Maarten Lankhorst
2017-12-18 22:36 ` Rodrigo Vivi
2017-12-15 23:04 ` ✓ Fi.CI.BAT: success for drm/i915: Protect DDI port to DPLL map from theoretical race. (rev2) Patchwork
2017-12-16 0:08 ` ✗ Fi.CI.IGT: failure " Patchwork
2017-12-20 17:32 ` [PATCH] drm/i915: Protect DDI port to DPLL map from theoretical race Ausmus, James
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