* [PATCH v2 00/27] Adding partial support for 128-bit riscv target
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
This series of patches provides partial 128-bit support for the riscv
target architecture.
Feedback on v1 was most useful and led to many improvements.
+ the load and store make use of a not yet upstreamed patch from Richard,
+ use of the existing Int128 computations in helpers, and addition of
a few more operations there, in particular division and remainder
+ refactoring of the calls to the code generation helpers, as suggested
by Richard, lead to a much cleaner solution. I did that for gen_arith
and gen_shift, not for gen_unary as it used only for the bitmanip
extension that I did not take into consideration yet
+ split of the patch in smaller pieces, as advised by Alistair
Two things suggested I could not achieve:
- the total eviction of the #ifdefs taking the target size into account:
I cheated by using #else when I needed, IMHO a shame
- the qemu_build_not_reached() use when accessing the upper part of the
registers: the misa/misah field is used for this check, and in 128-bit
the compiler cannot infer that the field is read only.
The checks I made in between each patch:
* smooth boot of busybear linux on rv64
* correct execution of all riscv-probe programs on rv32
For the 128-bit, the tests are there: https://github.com/fpetrot/128-test
* from hash 925e1af2c7, run the tests in unit_test_i
* from hash 6d4a39f2c4, run in addition the tests in unit_test_m
* from hash 864e563916, run in addition the tests unit_test_csr
Frédéric Pétrot (27):
memory: add a few defines for octo (128-bit) values
Int128.h: addition of a few 128-bit operations
target/riscv: adding upper 64 bits for misa
target/riscv: array for the 64 upper bits of 128-bit registers
target/riscv: additional macros to check instruction support
target/riscv: separation of bitwise logic and aritmetic helpers
target/riscv: refactoring calls to gen_arith
target/riscv: refactoring calls to gen_shift
target/riscv: setup everything so that riscv128-softmmu compiles
target/riscv: adding accessors to the registers upper part
target/riscv: handling 128-bit part in logic/arith/shift gen helpers
target/riscv: moving some insns close to similar insns
target/riscv: rename a few gen function helpers
target/riscv: 128-bit support for instructions using
gen_arith/gen_logic
target/riscv: 128-bit support for instructions using gen_shift
target/riscv: support for 128-bit loads and store
target/riscv: 128-bit double word integer arithmetic instructions
target/riscv: 128-bit double word integer shift instructions
target/riscv: support for 128-bit base multiplications insns
target/riscv: addition of the 'd' insns for 128-bit mult/div/rem
target/riscv: div and rem insns on 128-bit
target/riscv: adding high part of some csrs
target/riscv: helper functions to wrap calls to 128-bit csr insns
target/riscv: modification of the trans_csrxx for 128-bit support
target/riscv: actual functions to realize crs 128-bit insns
target/riscv: adding 128-bit access functions for some csrs
target/riscv: support for 128-bit satp
configs/devices/riscv128-softmmu/default.mak | 17 +
configs/targets/riscv128-softmmu.mak | 6 +
include/exec/memop.h | 6 +
include/hw/riscv/sifive_cpu.h | 3 +
include/qemu/int128.h | 264 ++++++
target/riscv/cpu-param.h | 10 +
target/riscv/cpu.h | 40 +
target/riscv/cpu_bits.h | 11 +
target/riscv/helper.h | 9 +
target/riscv/insn16.decode | 32 +-
target/riscv/insn32.decode | 25 +
target/riscv/cpu.c | 49 +-
target/riscv/cpu_helper.c | 54 +-
target/riscv/csr.c | 329 ++++++-
target/riscv/gdbstub.c | 3 +
target/riscv/m128_helper.c | 109 +++
target/riscv/op_helper.c | 44 +
target/riscv/translate.c | 351 ++++++-
target/riscv/insn_trans/trans_rvb.c.inc | 80 +-
target/riscv/insn_trans/trans_rvd.c.inc | 12 +-
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
target/riscv/insn_trans/trans_rvi.c.inc | 936 ++++++++++++++++---
target/riscv/insn_trans/trans_rvm.c.inc | 352 ++++++-
gdb-xml/riscv-128bit-cpu.xml | 48 +
gdb-xml/riscv-128bit-virtual.xml | 12 +
target/riscv/Kconfig | 3 +
target/riscv/meson.build | 1 +
27 files changed, 2579 insertions(+), 233 deletions(-)
create mode 100644 configs/devices/riscv128-softmmu/default.mak
create mode 100644 configs/targets/riscv128-softmmu.mak
create mode 100644 target/riscv/m128_helper.c
create mode 100644 gdb-xml/riscv-128bit-cpu.xml
create mode 100644 gdb-xml/riscv-128bit-virtual.xml
--
2.33.0
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v2 00/27] Adding partial support for 128-bit riscv target
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
This series of patches provides partial 128-bit support for the riscv
target architecture.
Feedback on v1 was most useful and led to many improvements.
+ the load and store make use of a not yet upstreamed patch from Richard,
+ use of the existing Int128 computations in helpers, and addition of
a few more operations there, in particular division and remainder
+ refactoring of the calls to the code generation helpers, as suggested
by Richard, lead to a much cleaner solution. I did that for gen_arith
and gen_shift, not for gen_unary as it used only for the bitmanip
extension that I did not take into consideration yet
+ split of the patch in smaller pieces, as advised by Alistair
Two things suggested I could not achieve:
- the total eviction of the #ifdefs taking the target size into account:
I cheated by using #else when I needed, IMHO a shame
- the qemu_build_not_reached() use when accessing the upper part of the
registers: the misa/misah field is used for this check, and in 128-bit
the compiler cannot infer that the field is read only.
The checks I made in between each patch:
* smooth boot of busybear linux on rv64
* correct execution of all riscv-probe programs on rv32
For the 128-bit, the tests are there: https://github.com/fpetrot/128-test
* from hash 925e1af2c7, run the tests in unit_test_i
* from hash 6d4a39f2c4, run in addition the tests in unit_test_m
* from hash 864e563916, run in addition the tests unit_test_csr
Frédéric Pétrot (27):
memory: add a few defines for octo (128-bit) values
Int128.h: addition of a few 128-bit operations
target/riscv: adding upper 64 bits for misa
target/riscv: array for the 64 upper bits of 128-bit registers
target/riscv: additional macros to check instruction support
target/riscv: separation of bitwise logic and aritmetic helpers
target/riscv: refactoring calls to gen_arith
target/riscv: refactoring calls to gen_shift
target/riscv: setup everything so that riscv128-softmmu compiles
target/riscv: adding accessors to the registers upper part
target/riscv: handling 128-bit part in logic/arith/shift gen helpers
target/riscv: moving some insns close to similar insns
target/riscv: rename a few gen function helpers
target/riscv: 128-bit support for instructions using
gen_arith/gen_logic
target/riscv: 128-bit support for instructions using gen_shift
target/riscv: support for 128-bit loads and store
target/riscv: 128-bit double word integer arithmetic instructions
target/riscv: 128-bit double word integer shift instructions
target/riscv: support for 128-bit base multiplications insns
target/riscv: addition of the 'd' insns for 128-bit mult/div/rem
target/riscv: div and rem insns on 128-bit
target/riscv: adding high part of some csrs
target/riscv: helper functions to wrap calls to 128-bit csr insns
target/riscv: modification of the trans_csrxx for 128-bit support
target/riscv: actual functions to realize crs 128-bit insns
target/riscv: adding 128-bit access functions for some csrs
target/riscv: support for 128-bit satp
configs/devices/riscv128-softmmu/default.mak | 17 +
configs/targets/riscv128-softmmu.mak | 6 +
include/exec/memop.h | 6 +
include/hw/riscv/sifive_cpu.h | 3 +
include/qemu/int128.h | 264 ++++++
target/riscv/cpu-param.h | 10 +
target/riscv/cpu.h | 40 +
target/riscv/cpu_bits.h | 11 +
target/riscv/helper.h | 9 +
target/riscv/insn16.decode | 32 +-
target/riscv/insn32.decode | 25 +
target/riscv/cpu.c | 49 +-
target/riscv/cpu_helper.c | 54 +-
target/riscv/csr.c | 329 ++++++-
target/riscv/gdbstub.c | 3 +
target/riscv/m128_helper.c | 109 +++
target/riscv/op_helper.c | 44 +
target/riscv/translate.c | 351 ++++++-
target/riscv/insn_trans/trans_rvb.c.inc | 80 +-
target/riscv/insn_trans/trans_rvd.c.inc | 12 +-
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
target/riscv/insn_trans/trans_rvi.c.inc | 936 ++++++++++++++++---
target/riscv/insn_trans/trans_rvm.c.inc | 352 ++++++-
gdb-xml/riscv-128bit-cpu.xml | 48 +
gdb-xml/riscv-128bit-virtual.xml | 12 +
target/riscv/Kconfig | 3 +
target/riscv/meson.build | 1 +
27 files changed, 2579 insertions(+), 233 deletions(-)
create mode 100644 configs/devices/riscv128-softmmu/default.mak
create mode 100644 configs/targets/riscv128-softmmu.mak
create mode 100644 target/riscv/m128_helper.c
create mode 100644 gdb-xml/riscv-128bit-cpu.xml
create mode 100644 gdb-xml/riscv-128bit-virtual.xml
--
2.33.0
^ permalink raw reply [flat|nested] 60+ messages in thread
* [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Introducing unsigned quad, signed quad, and octo accesses types
to handle load and store by 128-bit processors.
This is just a small addition to Richard's patch not yet upstreamed
https://lore.kernel.org/qemu-devel/20210818191920.390759-24-richard.henderson@linaro.org/
Note that the patch must be applied first for the rest to compile
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
include/exec/memop.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 04264ffd6b..9297f58a39 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -85,10 +85,13 @@ typedef enum MemOp {
MO_UB = MO_8,
MO_UW = MO_16,
MO_UL = MO_32,
+ MO_UQ = MO_64,
MO_SB = MO_SIGN | MO_8,
MO_SW = MO_SIGN | MO_16,
MO_SL = MO_SIGN | MO_32,
+ MO_SQ = MO_SIGN | MO_64,
MO_Q = MO_64,
+ MO_O = MO_128,
MO_LEUW = MO_LE | MO_UW,
MO_LEUL = MO_LE | MO_UL,
@@ -105,9 +108,12 @@ typedef enum MemOp {
#ifdef NEED_CPU_H
MO_TEUW = MO_TE | MO_UW,
MO_TEUL = MO_TE | MO_UL,
+ MO_TEUQ = MO_TE | MO_UQ,
MO_TESW = MO_TE | MO_SW,
MO_TESL = MO_TE | MO_SL,
+ MO_TESQ = MO_TE | MO_SQ,
MO_TEQ = MO_TE | MO_Q,
+ MO_TEO = MO_TE | MO_O,
#endif
MO_SSIZE = MO_SIZE | MO_SIGN,
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Introducing unsigned quad, signed quad, and octo accesses types
to handle load and store by 128-bit processors.
This is just a small addition to Richard's patch not yet upstreamed
https://lore.kernel.org/qemu-devel/20210818191920.390759-24-richard.henderson@linaro.org/
Note that the patch must be applied first for the rest to compile
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
include/exec/memop.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 04264ffd6b..9297f58a39 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -85,10 +85,13 @@ typedef enum MemOp {
MO_UB = MO_8,
MO_UW = MO_16,
MO_UL = MO_32,
+ MO_UQ = MO_64,
MO_SB = MO_SIGN | MO_8,
MO_SW = MO_SIGN | MO_16,
MO_SL = MO_SIGN | MO_32,
+ MO_SQ = MO_SIGN | MO_64,
MO_Q = MO_64,
+ MO_O = MO_128,
MO_LEUW = MO_LE | MO_UW,
MO_LEUL = MO_LE | MO_UL,
@@ -105,9 +108,12 @@ typedef enum MemOp {
#ifdef NEED_CPU_H
MO_TEUW = MO_TE | MO_UW,
MO_TEUL = MO_TE | MO_UL,
+ MO_TEUQ = MO_TE | MO_UQ,
MO_TESW = MO_TE | MO_SW,
MO_TESL = MO_TE | MO_SL,
+ MO_TESQ = MO_TE | MO_SQ,
MO_TEQ = MO_TE | MO_Q,
+ MO_TEO = MO_TE | MO_O,
#endif
MO_SSIZE = MO_SIZE | MO_SIGN,
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 02/27] Int128.h: addition of a few 128-bit operations
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Addition of not, xor, div and rem on 128-bit integers, used in particular
within div/rem and csr helpers for computations on 128-bit registers.
These will be used by the 128-bit riscv version.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
include/qemu/int128.h | 264 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 264 insertions(+)
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index 2ac0746426..b3236d85ad 100644
--- a/include/qemu/int128.h
+++ b/include/qemu/int128.h
@@ -58,6 +58,11 @@ static inline Int128 int128_exts64(int64_t a)
return a;
}
+static inline Int128 int128_not(Int128 a)
+{
+ return ~a;
+}
+
static inline Int128 int128_and(Int128 a, Int128 b)
{
return a & b;
@@ -68,6 +73,11 @@ static inline Int128 int128_or(Int128 a, Int128 b)
return a | b;
}
+static inline Int128 int128_xor(Int128 a, Int128 b)
+{
+ return a ^ b;
+}
+
static inline Int128 int128_rshift(Int128 a, int n)
{
return a >> n;
@@ -162,6 +172,26 @@ static inline Int128 bswap128(Int128 a)
#endif
}
+static inline Int128 int128_divu(Int128 a, Int128 b)
+{
+ return (__uint128_t)a / (__uint128_t)b;
+}
+
+static inline Int128 int128_remu(Int128 a, Int128 b)
+{
+ return (__uint128_t)a % (__uint128_t)b;
+}
+
+static inline Int128 int128_divs(Int128 a, Int128 b)
+{
+ return a / b;
+}
+
+static inline Int128 int128_rems(Int128 a, Int128 b)
+{
+ return a % b;
+}
+
#else /* !CONFIG_INT128 */
typedef struct Int128 Int128;
@@ -235,6 +265,11 @@ static inline Int128 int128_exts64(int64_t a)
return int128_make128(a, (a < 0) ? -1 : 0);
}
+static inline Int128 int128_not(Int128 a)
+{
+ return int128_make128(~a.lo, ~a.hi);
+}
+
static inline Int128 int128_and(Int128 a, Int128 b)
{
return int128_make128(a.lo & b.lo, a.hi & b.hi);
@@ -245,6 +280,11 @@ static inline Int128 int128_or(Int128 a, Int128 b)
return int128_make128(a.lo | b.lo, a.hi | b.hi);
}
+static inline Int128 int128_xor(Int128 a, Int128 b)
+{
+ return int128_make128(a.lo ^ b.lo, a.hi ^ b.hi);
+}
+
static inline Int128 int128_rshift(Int128 a, int n)
{
int64_t h;
@@ -359,6 +399,228 @@ static inline Int128 bswap128(Int128 a)
return int128_make128(bswap64(a.hi), bswap64(a.lo));
}
+#include "qemu/host-utils.h"
+/*
+ * Division and remainder algorithms for 128-bit.
+ * Naïve implementation of Knuth Algorithm D, can be optimized quite a bit if
+ * it becomes a bootleneck.
+ * Precondition: function never called with v equals to 0, has to be dealt
+ * with beforehand.
+ */
+static inline void divrem128(uint64_t ul, uint64_t uh,
+ uint64_t vl, uint64_t vh,
+ uint64_t *ql, uint64_t *qh,
+ uint64_t *rl, uint64_t *rh)
+{
+ const uint64_t b = ((uint64_t) 1) << 32;
+ const int m = 4;
+ uint64_t qhat, rhat, p;
+ int n, s, i;
+ int64_t j, t, k;
+
+ /* Build arrays of 32-bit words for u and v */
+ uint32_t u[4] = {ul & 0xffffffff, (ul >> 32) & 0xffffffff,
+ uh & 0xffffffff, (uh >> 32) & 0xffffffff};
+ uint32_t v[4] = {vl & 0xffffffff, (vl >> 32) & 0xffffffff,
+ vh & 0xffffffff, (vh >> 32) & 0xffffffff};
+
+ uint32_t q[4] = {0}, r[4] = {0}, un[5] = {0}, vn[4] = {0};
+
+ if (v[3]) {
+ n = 4;
+ } else if (v[2]) {
+ n = 3;
+ } else if (v[1]) {
+ n = 2;
+ } else if (v[0]) {
+ n = 1;
+ } else {
+ /* never happens, but makes gcc shy */
+ n = 0;
+ }
+
+ if (n == 1) {
+ /* Take care of the case of a single-digit divisor here */
+ k = 0;
+ for (j = m - 1; j >= 0; j--) {
+ q[j] = (k * b + u[j]) / v[0];
+ k = (k * b + u[j]) - q[j] * v[0];
+ }
+ if (r != NULL) {
+ r[0] = k;
+ }
+ } else {
+ s = clz32(v[n - 1]); /* 0 <= s <= 32 */
+ if (s != 0) {
+ for (i = n - 1; i > 0; i--) {
+ vn[i] = ((v[i] << s) | (v[i - 1] >> (32 - s)));
+ }
+ vn[0] = v[0] << s;
+
+ un[m] = u[m - 1] >> (32 - s);
+ for (i = m - 1; i > 0; i--) {
+ un[i] = (u[i] << s) | (u[i - 1] >> (32 - s));
+ }
+ un[0] = u[0] << s;
+ } else {
+ for (i = 0; i < n; i++) {
+ vn[i] = v[i];
+ }
+
+ for (i = 0; i < m; i++) {
+ un[i] = u[i];
+ }
+ un[m] = 0;
+ }
+
+ /* Step D2 : loop on j */
+ for (j = m - n; j >= 0; j--) { /* Main loop */
+ /* Step D3 : Compute estimate qhat of q[j] */
+ qhat = (un[j + n] * b + un[j + n - 1]) / vn[n - 1];
+ /* Optimized mod vn[n -1 ] */
+ rhat = (un[j + n] * b + un[j + n - 1]) - qhat * vn[n - 1];
+
+ while (true) {
+ if (qhat == b
+ || qhat * vn[n - 2] > b * rhat + un[j + n - 2]) {
+ qhat = qhat - 1;
+ rhat = rhat + vn[n - 1];
+ if (rhat < b) {
+ continue;
+ }
+ }
+ break;
+ }
+
+ /* Step D4 : Multiply and subtract */
+ k = 0;
+ for (i = 0; i < n; i++) {
+ p = qhat * vn[i];
+ t = un[i + j] - k - (p & 0xffffffff);
+ un[i + j] = t;
+ k = (p >> 32) - (t >> 32);
+ }
+ t = un[j + n] - k;
+ un[j + n] = t;
+
+ /* Step D5 */
+ q[j] = qhat; /* Store quotient digit */
+ /* Step D6 */
+ if (t < 0) { /* If we subtracted too much, add back */
+ q[j] = q[j] - 1;
+ k = 0;
+ for (i = 0; i < n; i++) {
+ t = un[i + j] + vn[i] + k;
+ un[i + j] = t;
+ k = t >> 32;
+ }
+ un[j + n] = un[j + n] + k;
+ }
+ } /* D7 Loop */
+
+ /* Step D8 : Unnormalize */
+ if (rl && rh) {
+ if (s != 0) {
+ for (i = 0; i < n; i++) {
+ r[i] = (un[i] >> s) | (un[i + 1] << (32 - s));
+ }
+ } else {
+ for (i = 0; i < n; i++) {
+ r[i] = un[i];
+ }
+ }
+ }
+ }
+
+ if (ql && qh) {
+ *ql = q[0] | ((uint64_t)q[1] << 32);
+ *qh = q[2] | ((uint64_t)q[3] << 32);
+ }
+
+ if (rl && rh) {
+ *rl = r[0] | ((uint64_t)r[1] << 32);
+ *rh = r[2] | ((uint64_t)r[3] << 32);
+ }
+}
+
+static inline Int128 int128_divu(Int128 a, Int128 b)
+{
+ uint64_t qh, ql;
+
+ divrem128(int128_getlo(a), int128_gethi(a),
+ int128_getlo(b), int128_gethi(b),
+ &ql, &qh,
+ NULL, NULL);
+
+ return int128_make128(ql, qh);
+}
+
+static inline Int128 int128_remu(Int128 a, Int128 b)
+{
+ uint64_t rh, rl;
+
+ divrem128(int128_getlo(a), int128_gethi(a),
+ int128_getlo(b), int128_gethi(b),
+ NULL, NULL,
+ &rl, &rh);
+
+ return int128_make128(rl, rh);
+}
+
+static inline Int128 int128_divs(Int128 a, Int128 b)
+{
+ uint64_t qh, ql;
+ bool sgna = !int128_nonneg(a),
+ sgnb = !int128_nonneg(b);
+
+ if (sgna) {
+ a = int128_neg(a);
+ }
+
+ if (sgnb) {
+ b = int128_neg(b);
+ }
+
+ divrem128(int128_getlo(a), int128_gethi(a),
+ int128_getlo(b), int128_gethi(b),
+ &ql, &qh,
+ NULL, NULL);
+ Int128 q = int128_make128(ql, qh);
+
+ if (sgna != sgnb) {
+ q = int128_neg(q);
+ }
+
+ return q;
+}
+
+static inline Int128 int128_rems(Int128 a, Int128 b)
+{
+ uint64_t rh, rl;
+ bool sgna = !int128_nonneg(a),
+ sgnb = !int128_nonneg(b);
+
+ if (sgna) {
+ a = int128_neg(a);
+ }
+
+ if (sgnb) {
+ b = int128_neg(b);
+ }
+
+ divrem128(int128_getlo(a), int128_gethi(a),
+ int128_getlo(b), int128_gethi(b),
+ NULL, NULL,
+ &rl, &rh);
+ Int128 r = int128_make128(rl, rh);
+
+ if (sgna) {
+ r = int128_neg(r);
+ }
+
+ return r;
+}
+
#endif /* CONFIG_INT128 */
static inline void bswap128s(Int128 *s)
@@ -366,4 +628,6 @@ static inline void bswap128s(Int128 *s)
*s = bswap128(*s);
}
+#define UINT128_MAX int128_make128(~0LL, ~0LL)
+
#endif /* INT128_H */
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 02/27] Int128.h: addition of a few 128-bit operations
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Addition of not, xor, div and rem on 128-bit integers, used in particular
within div/rem and csr helpers for computations on 128-bit registers.
These will be used by the 128-bit riscv version.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
include/qemu/int128.h | 264 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 264 insertions(+)
diff --git a/include/qemu/int128.h b/include/qemu/int128.h
index 2ac0746426..b3236d85ad 100644
--- a/include/qemu/int128.h
+++ b/include/qemu/int128.h
@@ -58,6 +58,11 @@ static inline Int128 int128_exts64(int64_t a)
return a;
}
+static inline Int128 int128_not(Int128 a)
+{
+ return ~a;
+}
+
static inline Int128 int128_and(Int128 a, Int128 b)
{
return a & b;
@@ -68,6 +73,11 @@ static inline Int128 int128_or(Int128 a, Int128 b)
return a | b;
}
+static inline Int128 int128_xor(Int128 a, Int128 b)
+{
+ return a ^ b;
+}
+
static inline Int128 int128_rshift(Int128 a, int n)
{
return a >> n;
@@ -162,6 +172,26 @@ static inline Int128 bswap128(Int128 a)
#endif
}
+static inline Int128 int128_divu(Int128 a, Int128 b)
+{
+ return (__uint128_t)a / (__uint128_t)b;
+}
+
+static inline Int128 int128_remu(Int128 a, Int128 b)
+{
+ return (__uint128_t)a % (__uint128_t)b;
+}
+
+static inline Int128 int128_divs(Int128 a, Int128 b)
+{
+ return a / b;
+}
+
+static inline Int128 int128_rems(Int128 a, Int128 b)
+{
+ return a % b;
+}
+
#else /* !CONFIG_INT128 */
typedef struct Int128 Int128;
@@ -235,6 +265,11 @@ static inline Int128 int128_exts64(int64_t a)
return int128_make128(a, (a < 0) ? -1 : 0);
}
+static inline Int128 int128_not(Int128 a)
+{
+ return int128_make128(~a.lo, ~a.hi);
+}
+
static inline Int128 int128_and(Int128 a, Int128 b)
{
return int128_make128(a.lo & b.lo, a.hi & b.hi);
@@ -245,6 +280,11 @@ static inline Int128 int128_or(Int128 a, Int128 b)
return int128_make128(a.lo | b.lo, a.hi | b.hi);
}
+static inline Int128 int128_xor(Int128 a, Int128 b)
+{
+ return int128_make128(a.lo ^ b.lo, a.hi ^ b.hi);
+}
+
static inline Int128 int128_rshift(Int128 a, int n)
{
int64_t h;
@@ -359,6 +399,228 @@ static inline Int128 bswap128(Int128 a)
return int128_make128(bswap64(a.hi), bswap64(a.lo));
}
+#include "qemu/host-utils.h"
+/*
+ * Division and remainder algorithms for 128-bit.
+ * Naïve implementation of Knuth Algorithm D, can be optimized quite a bit if
+ * it becomes a bootleneck.
+ * Precondition: function never called with v equals to 0, has to be dealt
+ * with beforehand.
+ */
+static inline void divrem128(uint64_t ul, uint64_t uh,
+ uint64_t vl, uint64_t vh,
+ uint64_t *ql, uint64_t *qh,
+ uint64_t *rl, uint64_t *rh)
+{
+ const uint64_t b = ((uint64_t) 1) << 32;
+ const int m = 4;
+ uint64_t qhat, rhat, p;
+ int n, s, i;
+ int64_t j, t, k;
+
+ /* Build arrays of 32-bit words for u and v */
+ uint32_t u[4] = {ul & 0xffffffff, (ul >> 32) & 0xffffffff,
+ uh & 0xffffffff, (uh >> 32) & 0xffffffff};
+ uint32_t v[4] = {vl & 0xffffffff, (vl >> 32) & 0xffffffff,
+ vh & 0xffffffff, (vh >> 32) & 0xffffffff};
+
+ uint32_t q[4] = {0}, r[4] = {0}, un[5] = {0}, vn[4] = {0};
+
+ if (v[3]) {
+ n = 4;
+ } else if (v[2]) {
+ n = 3;
+ } else if (v[1]) {
+ n = 2;
+ } else if (v[0]) {
+ n = 1;
+ } else {
+ /* never happens, but makes gcc shy */
+ n = 0;
+ }
+
+ if (n == 1) {
+ /* Take care of the case of a single-digit divisor here */
+ k = 0;
+ for (j = m - 1; j >= 0; j--) {
+ q[j] = (k * b + u[j]) / v[0];
+ k = (k * b + u[j]) - q[j] * v[0];
+ }
+ if (r != NULL) {
+ r[0] = k;
+ }
+ } else {
+ s = clz32(v[n - 1]); /* 0 <= s <= 32 */
+ if (s != 0) {
+ for (i = n - 1; i > 0; i--) {
+ vn[i] = ((v[i] << s) | (v[i - 1] >> (32 - s)));
+ }
+ vn[0] = v[0] << s;
+
+ un[m] = u[m - 1] >> (32 - s);
+ for (i = m - 1; i > 0; i--) {
+ un[i] = (u[i] << s) | (u[i - 1] >> (32 - s));
+ }
+ un[0] = u[0] << s;
+ } else {
+ for (i = 0; i < n; i++) {
+ vn[i] = v[i];
+ }
+
+ for (i = 0; i < m; i++) {
+ un[i] = u[i];
+ }
+ un[m] = 0;
+ }
+
+ /* Step D2 : loop on j */
+ for (j = m - n; j >= 0; j--) { /* Main loop */
+ /* Step D3 : Compute estimate qhat of q[j] */
+ qhat = (un[j + n] * b + un[j + n - 1]) / vn[n - 1];
+ /* Optimized mod vn[n -1 ] */
+ rhat = (un[j + n] * b + un[j + n - 1]) - qhat * vn[n - 1];
+
+ while (true) {
+ if (qhat == b
+ || qhat * vn[n - 2] > b * rhat + un[j + n - 2]) {
+ qhat = qhat - 1;
+ rhat = rhat + vn[n - 1];
+ if (rhat < b) {
+ continue;
+ }
+ }
+ break;
+ }
+
+ /* Step D4 : Multiply and subtract */
+ k = 0;
+ for (i = 0; i < n; i++) {
+ p = qhat * vn[i];
+ t = un[i + j] - k - (p & 0xffffffff);
+ un[i + j] = t;
+ k = (p >> 32) - (t >> 32);
+ }
+ t = un[j + n] - k;
+ un[j + n] = t;
+
+ /* Step D5 */
+ q[j] = qhat; /* Store quotient digit */
+ /* Step D6 */
+ if (t < 0) { /* If we subtracted too much, add back */
+ q[j] = q[j] - 1;
+ k = 0;
+ for (i = 0; i < n; i++) {
+ t = un[i + j] + vn[i] + k;
+ un[i + j] = t;
+ k = t >> 32;
+ }
+ un[j + n] = un[j + n] + k;
+ }
+ } /* D7 Loop */
+
+ /* Step D8 : Unnormalize */
+ if (rl && rh) {
+ if (s != 0) {
+ for (i = 0; i < n; i++) {
+ r[i] = (un[i] >> s) | (un[i + 1] << (32 - s));
+ }
+ } else {
+ for (i = 0; i < n; i++) {
+ r[i] = un[i];
+ }
+ }
+ }
+ }
+
+ if (ql && qh) {
+ *ql = q[0] | ((uint64_t)q[1] << 32);
+ *qh = q[2] | ((uint64_t)q[3] << 32);
+ }
+
+ if (rl && rh) {
+ *rl = r[0] | ((uint64_t)r[1] << 32);
+ *rh = r[2] | ((uint64_t)r[3] << 32);
+ }
+}
+
+static inline Int128 int128_divu(Int128 a, Int128 b)
+{
+ uint64_t qh, ql;
+
+ divrem128(int128_getlo(a), int128_gethi(a),
+ int128_getlo(b), int128_gethi(b),
+ &ql, &qh,
+ NULL, NULL);
+
+ return int128_make128(ql, qh);
+}
+
+static inline Int128 int128_remu(Int128 a, Int128 b)
+{
+ uint64_t rh, rl;
+
+ divrem128(int128_getlo(a), int128_gethi(a),
+ int128_getlo(b), int128_gethi(b),
+ NULL, NULL,
+ &rl, &rh);
+
+ return int128_make128(rl, rh);
+}
+
+static inline Int128 int128_divs(Int128 a, Int128 b)
+{
+ uint64_t qh, ql;
+ bool sgna = !int128_nonneg(a),
+ sgnb = !int128_nonneg(b);
+
+ if (sgna) {
+ a = int128_neg(a);
+ }
+
+ if (sgnb) {
+ b = int128_neg(b);
+ }
+
+ divrem128(int128_getlo(a), int128_gethi(a),
+ int128_getlo(b), int128_gethi(b),
+ &ql, &qh,
+ NULL, NULL);
+ Int128 q = int128_make128(ql, qh);
+
+ if (sgna != sgnb) {
+ q = int128_neg(q);
+ }
+
+ return q;
+}
+
+static inline Int128 int128_rems(Int128 a, Int128 b)
+{
+ uint64_t rh, rl;
+ bool sgna = !int128_nonneg(a),
+ sgnb = !int128_nonneg(b);
+
+ if (sgna) {
+ a = int128_neg(a);
+ }
+
+ if (sgnb) {
+ b = int128_neg(b);
+ }
+
+ divrem128(int128_getlo(a), int128_gethi(a),
+ int128_getlo(b), int128_gethi(b),
+ NULL, NULL,
+ &rl, &rh);
+ Int128 r = int128_make128(rl, rh);
+
+ if (sgna) {
+ r = int128_neg(r);
+ }
+
+ return r;
+}
+
#endif /* CONFIG_INT128 */
static inline void bswap128s(Int128 *s)
@@ -366,4 +628,6 @@ static inline void bswap128s(Int128 *s)
*s = bswap128(*s);
}
+#define UINT128_MAX int128_make128(~0LL, ~0LL)
+
#endif /* INT128_H */
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 03/27] target/riscv: adding upper 64 bits for misa
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Addition of misah, upper part of misa in the 128-bit extension.
This is required for the is_64bit and is_128bit macros that we
introduce in addition to the existing is_32bit one to know which
register size the processor uses.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 11 +++++++++++
target/riscv/cpu.c | 2 ++
target/riscv/translate.c | 21 ++++++++++++++++++++-
3 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5896aca346..0c41b60b25 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -37,6 +37,7 @@
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
+#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("rv128")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
@@ -49,10 +50,16 @@
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
+#else
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE128
#endif
+/* Mask for the MXLEN flag in the misa CSR */
+#define MXLEN_MASK ((target_ulong)3 << (TARGET_LONG_BITS - 2))
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
+/* To be used on misah, the upper part of misa */
+#define RV128 ((target_ulong)3 << (TARGET_LONG_BITS - 2))
#define RV(x) ((target_ulong)1 << (x - 'A'))
@@ -187,6 +194,10 @@ struct CPURISCVState {
target_ulong hgatp;
uint64_t htimedelta;
+ /* Upper 64-bits of 128-bit misa CSR */
+ uint64_t misah;
+ uint64_t misah_mask;
+
/* Virtual CSRs */
/*
* For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7c626d89cd..02417be926 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -154,8 +154,10 @@ static void riscv_any_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
#if defined(TARGET_RISCV32)
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ set_misah(env, 0);
#elif defined(TARGET_RISCV64)
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ set_misah(env, 0);
#endif
set_priv_version(env, PRIV_VERSION_1_11_0);
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 74b33fa3c9..c04430805e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -56,6 +56,7 @@ typedef struct DisasContext {
target_ulong pc_succ_insn;
target_ulong priv_ver;
target_ulong misa;
+ uint64_t misah;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t mem_idx;
@@ -90,13 +91,30 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
#ifdef TARGET_RISCV32
# define is_32bit(ctx) true
+# define is_64bit(ctx) false
+# define is_128bit(ctx) false
#elif defined(CONFIG_USER_ONLY)
# define is_32bit(ctx) false
+# define is_64_bit(ctx) true
+# define is_128_bit(ctx) false
#else
static inline bool is_32bit(DisasContext *ctx)
{
- return (ctx->misa & RV32) == RV32;
+ return (ctx->misa & MXLEN_MASK) == RV32;
}
+
+static inline bool is_64bit(DisasContext *ctx)
+{
+ return (ctx->misa & MXLEN_MASK) == RV64;
+}
+#if !defined(TARGET_RISCV64)
+static inline bool is_128bit(DisasContext *ctx)
+{
+ return (ctx->misah & MXLEN_MASK) == RV128;
+}
+#else
+# define is_128bit(ctx) false
+#endif
#endif
/* The word size for this operation. */
@@ -530,6 +548,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->virt_enabled = false;
#endif
ctx->misa = env->misa;
+ ctx->misah = env->misah;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
ctx->vlen = cpu->cfg.vlen;
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 03/27] target/riscv: adding upper 64 bits for misa
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Addition of misah, upper part of misa in the 128-bit extension.
This is required for the is_64bit and is_128bit macros that we
introduce in addition to the existing is_32bit one to know which
register size the processor uses.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 11 +++++++++++
target/riscv/cpu.c | 2 ++
target/riscv/translate.c | 21 ++++++++++++++++++++-
3 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5896aca346..0c41b60b25 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -37,6 +37,7 @@
#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
+#define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("rv128")
#define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
@@ -49,10 +50,16 @@
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64
+#else
+# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE128
#endif
+/* Mask for the MXLEN flag in the misa CSR */
+#define MXLEN_MASK ((target_ulong)3 << (TARGET_LONG_BITS - 2))
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
+/* To be used on misah, the upper part of misa */
+#define RV128 ((target_ulong)3 << (TARGET_LONG_BITS - 2))
#define RV(x) ((target_ulong)1 << (x - 'A'))
@@ -187,6 +194,10 @@ struct CPURISCVState {
target_ulong hgatp;
uint64_t htimedelta;
+ /* Upper 64-bits of 128-bit misa CSR */
+ uint64_t misah;
+ uint64_t misah_mask;
+
/* Virtual CSRs */
/*
* For RV32 this is 32-bit vsstatus and 32-bit vsstatush.
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7c626d89cd..02417be926 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -154,8 +154,10 @@ static void riscv_any_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
#if defined(TARGET_RISCV32)
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ set_misah(env, 0);
#elif defined(TARGET_RISCV64)
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ set_misah(env, 0);
#endif
set_priv_version(env, PRIV_VERSION_1_11_0);
}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 74b33fa3c9..c04430805e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -56,6 +56,7 @@ typedef struct DisasContext {
target_ulong pc_succ_insn;
target_ulong priv_ver;
target_ulong misa;
+ uint64_t misah;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t mem_idx;
@@ -90,13 +91,30 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
#ifdef TARGET_RISCV32
# define is_32bit(ctx) true
+# define is_64bit(ctx) false
+# define is_128bit(ctx) false
#elif defined(CONFIG_USER_ONLY)
# define is_32bit(ctx) false
+# define is_64_bit(ctx) true
+# define is_128_bit(ctx) false
#else
static inline bool is_32bit(DisasContext *ctx)
{
- return (ctx->misa & RV32) == RV32;
+ return (ctx->misa & MXLEN_MASK) == RV32;
}
+
+static inline bool is_64bit(DisasContext *ctx)
+{
+ return (ctx->misa & MXLEN_MASK) == RV64;
+}
+#if !defined(TARGET_RISCV64)
+static inline bool is_128bit(DisasContext *ctx)
+{
+ return (ctx->misah & MXLEN_MASK) == RV128;
+}
+#else
+# define is_128bit(ctx) false
+#endif
#endif
/* The word size for this operation. */
@@ -530,6 +548,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->virt_enabled = false;
#endif
ctx->misa = env->misa;
+ ctx->misah = env->misah;
ctx->frm = -1; /* unknown rounding mode */
ctx->ext_ifencei = cpu->cfg.ext_ifencei;
ctx->vlen = cpu->cfg.vlen;
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 04/27] target/riscv: array for the 64 upper bits of 128-bit registers
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 3 +++
target/riscv/translate.c | 6 +++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0c41b60b25..1de9a1286b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -120,6 +120,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
+ target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
uint64_t fpr[32]; /* assume both F and D extensions */
/* vector coprocessor state. */
@@ -405,6 +406,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
FIELD(TB_FLAGS, HLSX, 9, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
+bool riscv_cpu_is_64bit(CPURISCVState *env);
+bool riscv_cpu_is_128bit(CPURISCVState *env);
/*
* A simplification for VLMAX
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c04430805e..3c929ce960 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -32,7 +32,7 @@
#include "instmap.h"
/* global register indices */
-static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
+static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
@@ -55,6 +55,7 @@ typedef struct DisasContext {
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
target_ulong priv_ver;
+ /* Type of csrs should be MXLEN, that might be dynamically settable */
target_ulong misa;
uint64_t misah;
uint32_t opcode;
@@ -658,10 +659,13 @@ void riscv_translate_init(void)
* unless you specifically block reads/writes to reg 0.
*/
cpu_gpr[0] = NULL;
+ cpu_gprh[0] = NULL;
for (i = 1; i < 32; i++) {
cpu_gpr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
+ cpu_gprh[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]);
}
for (i = 0; i < 32; i++) {
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 04/27] target/riscv: array for the 64 upper bits of 128-bit registers
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 3 +++
target/riscv/translate.c | 6 +++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0c41b60b25..1de9a1286b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -120,6 +120,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
+ target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
uint64_t fpr[32]; /* assume both F and D extensions */
/* vector coprocessor state. */
@@ -405,6 +406,8 @@ FIELD(TB_FLAGS, VILL, 8, 1)
FIELD(TB_FLAGS, HLSX, 9, 1)
bool riscv_cpu_is_32bit(CPURISCVState *env);
+bool riscv_cpu_is_64bit(CPURISCVState *env);
+bool riscv_cpu_is_128bit(CPURISCVState *env);
/*
* A simplification for VLMAX
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c04430805e..3c929ce960 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -32,7 +32,7 @@
#include "instmap.h"
/* global register indices */
-static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
+static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
@@ -55,6 +55,7 @@ typedef struct DisasContext {
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
target_ulong priv_ver;
+ /* Type of csrs should be MXLEN, that might be dynamically settable */
target_ulong misa;
uint64_t misah;
uint32_t opcode;
@@ -658,10 +659,13 @@ void riscv_translate_init(void)
* unless you specifically block reads/writes to reg 0.
*/
cpu_gpr[0] = NULL;
+ cpu_gprh[0] = NULL;
for (i = 1; i < 32; i++) {
cpu_gpr[i] = tcg_global_mem_new(cpu_env,
offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
+ cpu_gprh[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]);
}
for (i = 0; i < 32; i++) {
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 05/27] target/riscv: additional macros to check instruction support
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3c929ce960..96a1e40606 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -357,11 +357,29 @@ EX_SH(12)
} while (0)
#define REQUIRE_64BIT(ctx) do { \
- if (is_32bit(ctx)) { \
+ if (!is_64bit(ctx)) { \
return false; \
} \
} while (0)
+#define REQUIRE_128BIT(ctx) do { \
+ if (!is_128bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_32_OR_64BIT(ctx) do { \
+ if (is_128bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_64_OR_128BIT(ctx) do { \
+ if (is_32bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
static int ex_rvc_register(DisasContext *ctx, int reg)
{
return 8 + reg;
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 05/27] target/riscv: additional macros to check instruction support
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Given that the 128-bit version of the riscv spec adds new instructions, and
that some instructions that were previously only available in 64-bit mode
are now available for both 64-bit and 128-bit, we added new macros to check
for the processor mode during translation.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3c929ce960..96a1e40606 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -357,11 +357,29 @@ EX_SH(12)
} while (0)
#define REQUIRE_64BIT(ctx) do { \
- if (is_32bit(ctx)) { \
+ if (!is_64bit(ctx)) { \
return false; \
} \
} while (0)
+#define REQUIRE_128BIT(ctx) do { \
+ if (!is_128bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_32_OR_64BIT(ctx) do { \
+ if (is_128bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
+#define REQUIRE_64_OR_128BIT(ctx) do { \
+ if (is_32bit(ctx)) { \
+ return false; \
+ } \
+} while (0)
+
static int ex_rvc_register(DisasContext *ctx, int reg)
{
return 8 + reg;
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Introduction of a gen_logic function for bitwise logic to implement
instructions in which not propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 27 +++++++++++++++++++++++++
target/riscv/insn_trans/trans_rvb.c.inc | 16 +++++++--------
target/riscv/insn_trans/trans_rvi.c.inc | 12 +++++------
3 files changed, 41 insertions(+), 14 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 96a1e40606..86623f81e8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -394,6 +394,19 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
/* Include the auto-generated decoder for 32 bit insn */
#include "decode-insn32.c.inc"
+static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
+ void (*func)(TCGv, TCGv, target_long))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+
+ func(dest, src1, a->imm);
+
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
void (*func)(TCGv, TCGv, target_long))
{
@@ -419,6 +432,20 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
return true;
}
+static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext,
+ void (*func)(TCGv, TCGv, TCGv))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
+
+ func(dest, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
void (*func)(TCGv, TCGv, TCGv))
{
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index b72e76255c..326d9939a0 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -49,19 +49,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
}
static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
@@ -74,7 +74,7 @@ static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_pack(DisasContext *ctx, arg_pack *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_pack);
+ return gen_logic(ctx, a, EXT_NONE, gen_pack);
}
static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
@@ -88,7 +88,7 @@ static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_packu(DisasContext *ctx, arg_packu *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packu);
+ return gen_logic(ctx, a, EXT_NONE, gen_packu);
}
static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
@@ -102,7 +102,7 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_packh(DisasContext *ctx, arg_packh *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packh);
+ return gen_logic(ctx, a, EXT_NONE, gen_packh);
}
static bool trans_min(DisasContext *ctx, arg_min *a)
@@ -393,7 +393,7 @@ static bool trans_packw(DisasContext *ctx, arg_packw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packw);
+ return gen_logic(ctx, a, EXT_NONE, gen_packw);
}
static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
@@ -409,7 +409,7 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packuw);
+ return gen_logic(ctx, a, EXT_NONE, gen_packuw);
}
static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 920ae0edb3..844080ec2b 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -252,17 +252,17 @@ static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
static bool trans_xori(DisasContext *ctx, arg_xori *a)
{
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
+ return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
}
static bool trans_ori(DisasContext *ctx, arg_ori *a)
{
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
+ return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
}
static bool trans_andi(DisasContext *ctx, arg_andi *a)
{
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
+ return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
@@ -307,7 +307,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -322,12 +322,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_and_tl);
}
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Introduction of a gen_logic function for bitwise logic to implement
instructions in which not propagation of information occurs between bits and
use of this function on the bitwise instructions.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 27 +++++++++++++++++++++++++
target/riscv/insn_trans/trans_rvb.c.inc | 16 +++++++--------
target/riscv/insn_trans/trans_rvi.c.inc | 12 +++++------
3 files changed, 41 insertions(+), 14 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 96a1e40606..86623f81e8 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -394,6 +394,19 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
/* Include the auto-generated decoder for 32 bit insn */
#include "decode-insn32.c.inc"
+static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
+ void (*func)(TCGv, TCGv, target_long))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+
+ func(dest, src1, a->imm);
+
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
void (*func)(TCGv, TCGv, target_long))
{
@@ -419,6 +432,20 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
return true;
}
+static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext,
+ void (*func)(TCGv, TCGv, TCGv))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
+
+ func(dest, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
void (*func)(TCGv, TCGv, TCGv))
{
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index b72e76255c..326d9939a0 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -49,19 +49,19 @@ static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
static bool trans_andn(DisasContext *ctx, arg_andn *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_andc_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_andc_tl);
}
static bool trans_orn(DisasContext *ctx, arg_orn *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_orc_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_orc_tl);
}
static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
}
static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
@@ -74,7 +74,7 @@ static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_pack(DisasContext *ctx, arg_pack *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_pack);
+ return gen_logic(ctx, a, EXT_NONE, gen_pack);
}
static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
@@ -88,7 +88,7 @@ static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_packu(DisasContext *ctx, arg_packu *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packu);
+ return gen_logic(ctx, a, EXT_NONE, gen_packu);
}
static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
@@ -102,7 +102,7 @@ static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_packh(DisasContext *ctx, arg_packh *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packh);
+ return gen_logic(ctx, a, EXT_NONE, gen_packh);
}
static bool trans_min(DisasContext *ctx, arg_min *a)
@@ -393,7 +393,7 @@ static bool trans_packw(DisasContext *ctx, arg_packw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packw);
+ return gen_logic(ctx, a, EXT_NONE, gen_packw);
}
static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
@@ -409,7 +409,7 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_packuw);
+ return gen_logic(ctx, a, EXT_NONE, gen_packuw);
}
static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 920ae0edb3..844080ec2b 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -252,17 +252,17 @@ static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
static bool trans_xori(DisasContext *ctx, arg_xori *a)
{
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
+ return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_xori_tl);
}
static bool trans_ori(DisasContext *ctx, arg_ori *a)
{
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
+ return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_ori_tl);
}
static bool trans_andi(DisasContext *ctx, arg_andi *a)
{
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
+ return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
@@ -307,7 +307,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_xor_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -322,12 +322,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_or_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_and_tl);
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_and_tl);
}
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 07/27] target/riscv: refactoring calls to gen_arith
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
gen_arith now takes three functions instead of one as arguments, one for
each register size.
All call sites changed to use this refactored version, without yet
supporting sizes other than 32 and 64.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 100 +++++++++++++++++-------
target/riscv/insn_trans/trans_rvb.c.inc | 17 ++--
target/riscv/insn_trans/trans_rvi.c.inc | 26 +++---
target/riscv/insn_trans/trans_rvm.c.inc | 39 ++++++---
4 files changed, 123 insertions(+), 59 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 86623f81e8..c940698478 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -407,55 +407,97 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
return true;
}
+static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext,
+ void (*func)(TCGv, TCGv, TCGv))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
+
+ func(dest, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, target_long))
+ void (*fn32)(TCGv, TCGv, target_long),
+ void (*fn64)(TCGv, TCGv, target_long),
+ void (*fn128)(TCGv, TCGv, TCGv, TCGv, target_long))
{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ if (is_32bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
- func(dest, src1, a->imm);
+ fn32(dest, src1, a->imm);
- gen_set_gpr(ctx, a->rd, dest);
+ gen_set_gpr(ctx, a->rd, dest);
+ } else if (is_64bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+
+ fn64(dest, src1, a->imm);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ } else {
+ return false;
+ }
return true;
}
static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, TCGv))
+ void (*fn32)(TCGv, TCGv, TCGv),
+ void (*fn64)(TCGv, TCGv, TCGv),
+ void (*fn128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, ext);
- TCGv src2 = tcg_constant_tl(a->imm);
+ if (is_32bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = tcg_constant_tl(a->imm);
- func(dest, src1, src2);
+ fn32(dest, src1, src2);
- gen_set_gpr(ctx, a->rd, dest);
- return true;
-}
+ gen_set_gpr(ctx, a->rd, dest);
+ } else if (is_64bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = tcg_constant_tl(a->imm);
-static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, TCGv))
-{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, ext);
- TCGv src2 = get_gpr(ctx, a->rs2, ext);
-
- func(dest, src1, src2);
-
- gen_set_gpr(ctx, a->rd, dest);
+ fn64(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ } else {
+ return false;
+ }
return true;
}
static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, TCGv))
+ void (*fn32)(TCGv, TCGv, TCGv),
+ void (*fn64)(TCGv, TCGv, TCGv),
+ void (*fn128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, ext);
- TCGv src2 = get_gpr(ctx, a->rs2, ext);
- func(dest, src1, src2);
+ if (is_32bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
- gen_set_gpr(ctx, a->rd, dest);
+ fn32(dest, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ } else if (is_64bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
+
+ fn64(dest, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ } else {
+ return false;
+ }
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 326d9939a0..fef239eed9 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -108,25 +108,25 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
static bool trans_min(DisasContext *ctx, arg_min *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
+ return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl, tcg_gen_smin_tl, NULL);
}
static bool trans_max(DisasContext *ctx, arg_max *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
+ return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl, tcg_gen_smax_tl, NULL);
}
static bool trans_minu(DisasContext *ctx, arg_minu *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
+ return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl, tcg_gen_umin_tl, NULL);
}
static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
+ return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl, tcg_gen_umax_tl, NULL);
}
static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
@@ -340,7 +340,8 @@ GEN_SHADD(3)
static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
{ \
REQUIRE_EXT(ctx, RVB); \
- return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); \
+ return gen_arith(ctx, a, EXT_NONE, \
+ gen_sh##SHAMT##add, gen_sh##SHAMT##add, NULL); \
}
GEN_TRANS_SHADD(1)
@@ -615,7 +616,9 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
{ \
REQUIRE_64BIT(ctx); \
REQUIRE_EXT(ctx, RVB); \
- return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \
+ return gen_arith(ctx, a, EXT_NONE, \
+ gen_sh##SHAMT##add_uw, \
+ gen_sh##SHAMT##add_uw, NULL); \
}
GEN_TRANS_SHADD_UW(1)
@@ -632,7 +635,7 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
+ return gen_arith(ctx, a, EXT_NONE, gen_add_uw, gen_add_uw, NULL);
}
static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 844080ec2b..c284dd19b3 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -227,7 +227,8 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
+ return gen_arith_imm_fn(ctx, a, EXT_NONE,
+ tcg_gen_addi_tl, tcg_gen_addi_tl, NULL);
}
static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
@@ -242,12 +243,14 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
- return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt);
+ return gen_arith_imm_tl(ctx, a, EXT_SIGN,
+ gen_slt, gen_slt, NULL);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
- return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu);
+ return gen_arith_imm_tl(ctx, a, EXT_SIGN,
+ gen_sltu, gen_sltu, NULL);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
@@ -282,12 +285,14 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
+ return gen_arith(ctx, a, EXT_NONE,
+ tcg_gen_add_tl, tcg_gen_add_tl, NULL);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
+ return gen_arith(ctx, a, EXT_NONE,
+ tcg_gen_sub_tl, tcg_gen_sub_tl, NULL);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -297,12 +302,12 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_slt);
+ return gen_arith(ctx, a, EXT_SIGN, gen_slt, gen_slt, NULL);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
+ return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu, NULL);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
@@ -334,7 +339,8 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
+ return gen_arith_imm_fn(ctx, a, EXT_NONE,
+ NULL, tcg_gen_addi_tl, NULL);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
@@ -372,14 +378,14 @@ static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
+ return gen_arith(ctx, a, EXT_NONE, NULL, tcg_gen_add_tl, NULL);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
+ return gen_arith(ctx, a, EXT_NONE, NULL, tcg_gen_sub_tl, NULL);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index b89a85ad3a..0c5f1ba548 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -22,7 +22,8 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
+ return gen_arith(ctx, a, EXT_NONE,
+ tcg_gen_mul_tl, tcg_gen_mul_tl, NULL);
}
static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
@@ -36,7 +37,8 @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_NONE, gen_mulh);
+ return gen_arith(ctx, a, EXT_NONE,
+ gen_mulh, gen_mulh, NULL);
}
static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
@@ -57,7 +59,8 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
+ return gen_arith(ctx, a, EXT_NONE,
+ gen_mulhsu, gen_mulhsu, NULL);
}
static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
@@ -71,7 +74,8 @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
+ return gen_arith(ctx, a, EXT_NONE,
+ gen_mulhu, gen_mulhu, NULL);
}
static void gen_div(TCGv ret, TCGv source1, TCGv source2)
@@ -110,7 +114,8 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2)
static bool trans_div(DisasContext *ctx, arg_div *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_SIGN, gen_div);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_div, gen_div, NULL);
}
static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
@@ -138,7 +143,8 @@ static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_ZERO, gen_divu);
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_divu, gen_divu, NULL);
}
static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
@@ -179,7 +185,8 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_SIGN, gen_rem);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_rem, gen_rem, NULL);
}
static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
@@ -207,7 +214,8 @@ static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_ZERO, gen_remu);
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_remu, gen_remu, NULL);
}
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
@@ -215,7 +223,8 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
+ return gen_arith(ctx, a, EXT_NONE,
+ tcg_gen_mul_tl, tcg_gen_mul_tl, NULL);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
@@ -223,7 +232,8 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
- return gen_arith(ctx, a, EXT_SIGN, gen_div);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_div, gen_div, NULL);
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
@@ -231,7 +241,8 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
- return gen_arith(ctx, a, EXT_ZERO, gen_divu);
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_divu, gen_divu, NULL);
}
static bool trans_remw(DisasContext *ctx, arg_remw *a)
@@ -239,7 +250,8 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
- return gen_arith(ctx, a, EXT_SIGN, gen_rem);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_rem, gen_rem, NULL);
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
@@ -247,5 +259,6 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
- return gen_arith(ctx, a, EXT_ZERO, gen_remu);
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_remu, gen_remu, NULL);
}
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 07/27] target/riscv: refactoring calls to gen_arith
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
gen_arith now takes three functions instead of one as arguments, one for
each register size.
All call sites changed to use this refactored version, without yet
supporting sizes other than 32 and 64.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 100 +++++++++++++++++-------
target/riscv/insn_trans/trans_rvb.c.inc | 17 ++--
target/riscv/insn_trans/trans_rvi.c.inc | 26 +++---
target/riscv/insn_trans/trans_rvm.c.inc | 39 ++++++---
4 files changed, 123 insertions(+), 59 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 86623f81e8..c940698478 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -407,55 +407,97 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
return true;
}
+static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext,
+ void (*func)(TCGv, TCGv, TCGv))
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
+
+ func(dest, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, target_long))
+ void (*fn32)(TCGv, TCGv, target_long),
+ void (*fn64)(TCGv, TCGv, target_long),
+ void (*fn128)(TCGv, TCGv, TCGv, TCGv, target_long))
{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ if (is_32bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
- func(dest, src1, a->imm);
+ fn32(dest, src1, a->imm);
- gen_set_gpr(ctx, a->rd, dest);
+ gen_set_gpr(ctx, a->rd, dest);
+ } else if (is_64bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+
+ fn64(dest, src1, a->imm);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ } else {
+ return false;
+ }
return true;
}
static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, TCGv))
+ void (*fn32)(TCGv, TCGv, TCGv),
+ void (*fn64)(TCGv, TCGv, TCGv),
+ void (*fn128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, ext);
- TCGv src2 = tcg_constant_tl(a->imm);
+ if (is_32bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = tcg_constant_tl(a->imm);
- func(dest, src1, src2);
+ fn32(dest, src1, src2);
- gen_set_gpr(ctx, a->rd, dest);
- return true;
-}
+ gen_set_gpr(ctx, a->rd, dest);
+ } else if (is_64bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = tcg_constant_tl(a->imm);
-static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, TCGv))
-{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, ext);
- TCGv src2 = get_gpr(ctx, a->rs2, ext);
-
- func(dest, src1, src2);
-
- gen_set_gpr(ctx, a->rd, dest);
+ fn64(dest, src1, src2);
+ gen_set_gpr(ctx, a->rd, dest);
+ } else {
+ return false;
+ }
return true;
}
static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, TCGv))
+ void (*fn32)(TCGv, TCGv, TCGv),
+ void (*fn64)(TCGv, TCGv, TCGv),
+ void (*fn128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, ext);
- TCGv src2 = get_gpr(ctx, a->rs2, ext);
- func(dest, src1, src2);
+ if (is_32bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
- gen_set_gpr(ctx, a->rd, dest);
+ fn32(dest, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ } else if (is_64bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, ext);
+
+ fn64(dest, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ } else {
+ return false;
+ }
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 326d9939a0..fef239eed9 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -108,25 +108,25 @@ static bool trans_packh(DisasContext *ctx, arg_packh *a)
static bool trans_min(DisasContext *ctx, arg_min *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl);
+ return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl, tcg_gen_smin_tl, NULL);
}
static bool trans_max(DisasContext *ctx, arg_max *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl);
+ return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl, tcg_gen_smax_tl, NULL);
}
static bool trans_minu(DisasContext *ctx, arg_minu *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl);
+ return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl, tcg_gen_umin_tl, NULL);
}
static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl);
+ return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl, tcg_gen_umax_tl, NULL);
}
static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
@@ -340,7 +340,8 @@ GEN_SHADD(3)
static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
{ \
REQUIRE_EXT(ctx, RVB); \
- return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add); \
+ return gen_arith(ctx, a, EXT_NONE, \
+ gen_sh##SHAMT##add, gen_sh##SHAMT##add, NULL); \
}
GEN_TRANS_SHADD(1)
@@ -615,7 +616,9 @@ static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
{ \
REQUIRE_64BIT(ctx); \
REQUIRE_EXT(ctx, RVB); \
- return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw); \
+ return gen_arith(ctx, a, EXT_NONE, \
+ gen_sh##SHAMT##add_uw, \
+ gen_sh##SHAMT##add_uw, NULL); \
}
GEN_TRANS_SHADD_UW(1)
@@ -632,7 +635,7 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
+ return gen_arith(ctx, a, EXT_NONE, gen_add_uw, gen_add_uw, NULL);
}
static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 844080ec2b..c284dd19b3 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -227,7 +227,8 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
+ return gen_arith_imm_fn(ctx, a, EXT_NONE,
+ tcg_gen_addi_tl, tcg_gen_addi_tl, NULL);
}
static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
@@ -242,12 +243,14 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
- return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_slt);
+ return gen_arith_imm_tl(ctx, a, EXT_SIGN,
+ gen_slt, gen_slt, NULL);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
- return gen_arith_imm_tl(ctx, a, EXT_SIGN, gen_sltu);
+ return gen_arith_imm_tl(ctx, a, EXT_SIGN,
+ gen_sltu, gen_sltu, NULL);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
@@ -282,12 +285,14 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
+ return gen_arith(ctx, a, EXT_NONE,
+ tcg_gen_add_tl, tcg_gen_add_tl, NULL);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
+ return gen_arith(ctx, a, EXT_NONE,
+ tcg_gen_sub_tl, tcg_gen_sub_tl, NULL);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -297,12 +302,12 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_slt);
+ return gen_arith(ctx, a, EXT_SIGN, gen_slt, gen_slt, NULL);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
+ return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu, NULL);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
@@ -334,7 +339,8 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_arith_imm_fn(ctx, a, EXT_NONE, tcg_gen_addi_tl);
+ return gen_arith_imm_fn(ctx, a, EXT_NONE,
+ NULL, tcg_gen_addi_tl, NULL);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
@@ -372,14 +378,14 @@ static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_add_tl);
+ return gen_arith(ctx, a, EXT_NONE, NULL, tcg_gen_add_tl, NULL);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_sub_tl);
+ return gen_arith(ctx, a, EXT_NONE, NULL, tcg_gen_sub_tl, NULL);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index b89a85ad3a..0c5f1ba548 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -22,7 +22,8 @@
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
+ return gen_arith(ctx, a, EXT_NONE,
+ tcg_gen_mul_tl, tcg_gen_mul_tl, NULL);
}
static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
@@ -36,7 +37,8 @@ static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_NONE, gen_mulh);
+ return gen_arith(ctx, a, EXT_NONE,
+ gen_mulh, gen_mulh, NULL);
}
static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
@@ -57,7 +59,8 @@ static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_NONE, gen_mulhsu);
+ return gen_arith(ctx, a, EXT_NONE,
+ gen_mulhsu, gen_mulhsu, NULL);
}
static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
@@ -71,7 +74,8 @@ static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_NONE, gen_mulhu);
+ return gen_arith(ctx, a, EXT_NONE,
+ gen_mulhu, gen_mulhu, NULL);
}
static void gen_div(TCGv ret, TCGv source1, TCGv source2)
@@ -110,7 +114,8 @@ static void gen_div(TCGv ret, TCGv source1, TCGv source2)
static bool trans_div(DisasContext *ctx, arg_div *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_SIGN, gen_div);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_div, gen_div, NULL);
}
static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
@@ -138,7 +143,8 @@ static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_ZERO, gen_divu);
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_divu, gen_divu, NULL);
}
static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
@@ -179,7 +185,8 @@ static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_SIGN, gen_rem);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_rem, gen_rem, NULL);
}
static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
@@ -207,7 +214,8 @@ static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
REQUIRE_EXT(ctx, RVM);
- return gen_arith(ctx, a, EXT_ZERO, gen_remu);
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_remu, gen_remu, NULL);
}
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
@@ -215,7 +223,8 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
- return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl);
+ return gen_arith(ctx, a, EXT_NONE,
+ tcg_gen_mul_tl, tcg_gen_mul_tl, NULL);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
@@ -223,7 +232,8 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
- return gen_arith(ctx, a, EXT_SIGN, gen_div);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_div, gen_div, NULL);
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
@@ -231,7 +241,8 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
- return gen_arith(ctx, a, EXT_ZERO, gen_divu);
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_divu, gen_divu, NULL);
}
static bool trans_remw(DisasContext *ctx, arg_remw *a)
@@ -239,7 +250,8 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
- return gen_arith(ctx, a, EXT_SIGN, gen_rem);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_rem, gen_rem, NULL);
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
@@ -247,5 +259,6 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
- return gen_arith(ctx, a, EXT_ZERO, gen_remu);
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_remu, gen_remu, NULL);
}
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 08/27] target/riscv: refactoring calls to gen_shift
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
As for arithmetic operations, we now pass functions pointers to deal with
32, 64 and 128-bit shift operations, and to change all call sites accordingly.
For now, 128-bit operations are still not handled.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 77 ++++++++++++++++++-------
target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++--------
target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++-----
3 files changed, 101 insertions(+), 57 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c940698478..0700c82a36 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -502,21 +502,41 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
}
static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, target_long))
+ void (*fn32)(TCGv, TCGv, target_long),
+ void (*fn64)(TCGv, TCGv, target_long),
+ void (*fn128)(TCGv, TCGv, TCGv, TCGv, target_long))
{
- TCGv dest, src1;
- int max_len = oper_len(ctx);
+ if (is_32bit(ctx)) {
+ TCGv dest, src1;
+ int max_len = oper_len(ctx);
- if (a->shamt >= max_len) {
+ if (a->shamt >= max_len) {
+ return false;
+ }
+
+ dest = dest_gpr(ctx, a->rd);
+ src1 = get_gpr(ctx, a->rs1, ext);
+
+ fn32(dest, src1, a->shamt);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ } else if (is_64bit(ctx)) {
+ TCGv dest, src1;
+ int max_len = oper_len(ctx);
+
+ if (a->shamt >= max_len) {
+ return false;
+ }
+
+ dest = dest_gpr(ctx, a->rd);
+ src1 = get_gpr(ctx, a->rs1, ext);
+
+ fn64(dest, src1, a->shamt);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ } else {
return false;
}
-
- dest = dest_gpr(ctx, a->rd);
- src1 = get_gpr(ctx, a->rs1, ext);
-
- func(dest, src1, a->shamt);
-
- gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -541,18 +561,35 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
}
static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, TCGv))
+ void (*fn32)(TCGv, TCGv, TCGv),
+ void (*fn64)(TCGv, TCGv, TCGv),
+ void (*fn128)(TCGv, TCGv, TCGv, TCGv, TCGv))
{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, ext);
- TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
- TCGv ext2 = tcg_temp_new();
+ if (is_32bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv ext2 = tcg_temp_new();
- tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
- func(dest, src1, ext2);
+ tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
+ fn32(dest, src1, ext2);
- gen_set_gpr(ctx, a->rd, dest);
- tcg_temp_free(ext2);
+ gen_set_gpr(ctx, a->rd, dest);
+ tcg_temp_free(ext2);
+ } else if (is_64bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv ext2 = tcg_temp_new();
+
+ tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
+ fn64(dest, src1, ext2);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ tcg_temp_free(ext2);
+ } else {
+ return false;
+ }
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index fef239eed9..cdae9671ff 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -160,7 +160,7 @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bset(DisasContext *ctx, arg_bset *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_bset);
+ return gen_shift(ctx, a, EXT_NONE, gen_bset, gen_bset, NULL);
}
static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
@@ -182,7 +182,7 @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_bclr);
+ return gen_shift(ctx, a, EXT_NONE, gen_bclr, gen_bclr, NULL);
}
static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
@@ -204,7 +204,7 @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_binv(DisasContext *ctx, arg_binv *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_binv);
+ return gen_shift(ctx, a, EXT_NONE, gen_binv, gen_binv, NULL);
}
static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
@@ -222,7 +222,7 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bext(DisasContext *ctx, arg_bext *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_bext);
+ return gen_shift(ctx, a, EXT_NONE, gen_bext, gen_bext, NULL);
}
static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
@@ -241,7 +241,7 @@ static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_slo(DisasContext *ctx, arg_slo *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
+ return gen_shift(ctx, a, EXT_NONE, gen_slo, gen_slo, NULL);
}
static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
@@ -260,7 +260,7 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_sro(DisasContext *ctx, arg_sro *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
+ return gen_shift(ctx, a, EXT_ZERO, gen_sro, gen_sro, NULL);
}
static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
@@ -272,25 +272,26 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
+ return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl, tcg_gen_rotr_tl, NULL);
}
static bool trans_rori(DisasContext *ctx, arg_rori *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE,
+ tcg_gen_rotri_tl, tcg_gen_rotri_tl, NULL);
}
static bool trans_rol(DisasContext *ctx, arg_rol *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
+ return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl, tcg_gen_rotl_tl, NULL);
}
static bool trans_grev(DisasContext *ctx, arg_grev *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
+ return gen_shift(ctx, a, EXT_NONE, gen_helper_grev, gen_helper_grev, NULL);
}
static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
@@ -306,13 +307,13 @@ static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi, gen_grevi, NULL);
}
static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
+ return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc, gen_helper_gorc, NULL);
}
static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
@@ -418,7 +419,7 @@ static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bset);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_bset, NULL);
}
static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
@@ -434,7 +435,7 @@ static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bclr);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_bclr, NULL);
}
static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
@@ -450,7 +451,7 @@ static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_binv);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_binv, NULL);
}
static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
@@ -466,7 +467,7 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bext);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_bext, NULL);
}
static bool trans_slow(DisasContext *ctx, arg_slow *a)
@@ -474,7 +475,7 @@ static bool trans_slow(DisasContext *ctx, arg_slow *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_slo, NULL);
}
static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
@@ -490,7 +491,7 @@ static bool trans_srow(DisasContext *ctx, arg_srow *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
+ return gen_shift(ctx, a, EXT_ZERO, NULL, gen_sro, NULL);
}
static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
@@ -524,7 +525,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_rorw);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_rorw, NULL);
}
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
@@ -558,7 +559,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_rolw);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_rolw, NULL);
}
static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
@@ -566,7 +567,7 @@ static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
+ return gen_shift(ctx, a, EXT_ZERO, NULL, gen_helper_grev, NULL);
}
static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
@@ -582,7 +583,7 @@ static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
+ return gen_shift(ctx, a, EXT_ZERO, NULL, gen_helper_gorc, NULL);
}
static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
@@ -647,5 +648,5 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_slli_uw, NULL);
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index c284dd19b3..aa1e3f07e5 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -270,17 +270,20 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
- return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE,
+ tcg_gen_shli_tl, tcg_gen_shli_tl, NULL);
}
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
- return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_ZERO,
+ tcg_gen_shri_tl, tcg_gen_shri_tl, NULL);
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
- return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_SIGN,
+ tcg_gen_sari_tl, tcg_gen_sari_tl, NULL);
}
static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -297,7 +300,8 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
static bool trans_sll(DisasContext *ctx, arg_sll *a)
{
- return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
+ return gen_shift(ctx, a, EXT_NONE,
+ tcg_gen_shl_tl, tcg_gen_shl_tl, NULL);
}
static bool trans_slt(DisasContext *ctx, arg_slt *a)
@@ -317,12 +321,12 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a)
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
- return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
+ return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, tcg_gen_shr_tl, NULL);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
- return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
+ return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, tcg_gen_sar_tl, NULL);
}
static bool trans_or(DisasContext *ctx, arg_or *a)
@@ -339,15 +343,14 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_arith_imm_fn(ctx, a, EXT_NONE,
- NULL, tcg_gen_addi_tl, NULL);
+ return gen_arith_imm_fn(ctx, a, EXT_NONE, NULL, tcg_gen_addi_tl, NULL);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, tcg_gen_shli_tl, NULL);
}
static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
@@ -359,7 +362,7 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_srliw, NULL);
}
static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
@@ -371,7 +374,7 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_sraiw, NULL);
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)
@@ -392,21 +395,24 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
+ return gen_shift(ctx, a, EXT_NONE,
+ tcg_gen_shl_tl, tcg_gen_shl_tl, NULL);
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
+ return gen_shift(ctx, a, EXT_ZERO,
+ NULL, tcg_gen_shr_tl, NULL);
}
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
+ return gen_shift(ctx, a, EXT_SIGN,
+ NULL, tcg_gen_sar_tl, NULL);
}
static bool trans_fence(DisasContext *ctx, arg_fence *a)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 08/27] target/riscv: refactoring calls to gen_shift
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
As for arithmetic operations, we now pass functions pointers to deal with
32, 64 and 128-bit shift operations, and to change all call sites accordingly.
For now, 128-bit operations are still not handled.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 77 ++++++++++++++++++-------
target/riscv/insn_trans/trans_rvb.c.inc | 47 +++++++--------
target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++-----
3 files changed, 101 insertions(+), 57 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c940698478..0700c82a36 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -502,21 +502,41 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
}
static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, target_long))
+ void (*fn32)(TCGv, TCGv, target_long),
+ void (*fn64)(TCGv, TCGv, target_long),
+ void (*fn128)(TCGv, TCGv, TCGv, TCGv, target_long))
{
- TCGv dest, src1;
- int max_len = oper_len(ctx);
+ if (is_32bit(ctx)) {
+ TCGv dest, src1;
+ int max_len = oper_len(ctx);
- if (a->shamt >= max_len) {
+ if (a->shamt >= max_len) {
+ return false;
+ }
+
+ dest = dest_gpr(ctx, a->rd);
+ src1 = get_gpr(ctx, a->rs1, ext);
+
+ fn32(dest, src1, a->shamt);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ } else if (is_64bit(ctx)) {
+ TCGv dest, src1;
+ int max_len = oper_len(ctx);
+
+ if (a->shamt >= max_len) {
+ return false;
+ }
+
+ dest = dest_gpr(ctx, a->rd);
+ src1 = get_gpr(ctx, a->rs1, ext);
+
+ fn64(dest, src1, a->shamt);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ } else {
return false;
}
-
- dest = dest_gpr(ctx, a->rd);
- src1 = get_gpr(ctx, a->rs1, ext);
-
- func(dest, src1, a->shamt);
-
- gen_set_gpr(ctx, a->rd, dest);
return true;
}
@@ -541,18 +561,35 @@ static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
}
static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
- void (*func)(TCGv, TCGv, TCGv))
+ void (*fn32)(TCGv, TCGv, TCGv),
+ void (*fn64)(TCGv, TCGv, TCGv),
+ void (*fn128)(TCGv, TCGv, TCGv, TCGv, TCGv))
{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, ext);
- TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
- TCGv ext2 = tcg_temp_new();
+ if (is_32bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv ext2 = tcg_temp_new();
- tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
- func(dest, src1, ext2);
+ tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
+ fn32(dest, src1, ext2);
- gen_set_gpr(ctx, a->rd, dest);
- tcg_temp_free(ext2);
+ gen_set_gpr(ctx, a->rd, dest);
+ tcg_temp_free(ext2);
+ } else if (is_64bit(ctx)) {
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv ext2 = tcg_temp_new();
+
+ tcg_gen_andi_tl(ext2, src2, oper_len(ctx) - 1);
+ fn64(dest, src1, ext2);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ tcg_temp_free(ext2);
+ } else {
+ return false;
+ }
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index fef239eed9..cdae9671ff 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -160,7 +160,7 @@ static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bset(DisasContext *ctx, arg_bset *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_bset);
+ return gen_shift(ctx, a, EXT_NONE, gen_bset, gen_bset, NULL);
}
static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
@@ -182,7 +182,7 @@ static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_bclr);
+ return gen_shift(ctx, a, EXT_NONE, gen_bclr, gen_bclr, NULL);
}
static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
@@ -204,7 +204,7 @@ static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_binv(DisasContext *ctx, arg_binv *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_binv);
+ return gen_shift(ctx, a, EXT_NONE, gen_binv, gen_binv, NULL);
}
static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
@@ -222,7 +222,7 @@ static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
static bool trans_bext(DisasContext *ctx, arg_bext *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_bext);
+ return gen_shift(ctx, a, EXT_NONE, gen_bext, gen_bext, NULL);
}
static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
@@ -241,7 +241,7 @@ static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_slo(DisasContext *ctx, arg_slo *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
+ return gen_shift(ctx, a, EXT_NONE, gen_slo, gen_slo, NULL);
}
static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
@@ -260,7 +260,7 @@ static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
static bool trans_sro(DisasContext *ctx, arg_sro *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
+ return gen_shift(ctx, a, EXT_ZERO, gen_sro, gen_sro, NULL);
}
static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
@@ -272,25 +272,26 @@ static bool trans_sroi(DisasContext *ctx, arg_sroi *a)
static bool trans_ror(DisasContext *ctx, arg_ror *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl);
+ return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotr_tl, tcg_gen_rotr_tl, NULL);
}
static bool trans_rori(DisasContext *ctx, arg_rori *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_rotri_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE,
+ tcg_gen_rotri_tl, tcg_gen_rotri_tl, NULL);
}
static bool trans_rol(DisasContext *ctx, arg_rol *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
+ return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl, tcg_gen_rotl_tl, NULL);
}
static bool trans_grev(DisasContext *ctx, arg_grev *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_NONE, gen_helper_grev);
+ return gen_shift(ctx, a, EXT_NONE, gen_helper_grev, gen_helper_grev, NULL);
}
static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
@@ -306,13 +307,13 @@ static void gen_grevi(TCGv dest, TCGv src, target_long shamt)
static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_grevi, gen_grevi, NULL);
}
static bool trans_gorc(DisasContext *ctx, arg_gorc *a)
{
REQUIRE_EXT(ctx, RVB);
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
+ return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc, gen_helper_gorc, NULL);
}
static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
@@ -418,7 +419,7 @@ static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bset);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_bset, NULL);
}
static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
@@ -434,7 +435,7 @@ static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bclr);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_bclr, NULL);
}
static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
@@ -450,7 +451,7 @@ static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_binv);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_binv, NULL);
}
static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
@@ -466,7 +467,7 @@ static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_bext);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_bext, NULL);
}
static bool trans_slow(DisasContext *ctx, arg_slow *a)
@@ -474,7 +475,7 @@ static bool trans_slow(DisasContext *ctx, arg_slow *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_slo);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_slo, NULL);
}
static bool trans_sloiw(DisasContext *ctx, arg_sloiw *a)
@@ -490,7 +491,7 @@ static bool trans_srow(DisasContext *ctx, arg_srow *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_sro);
+ return gen_shift(ctx, a, EXT_ZERO, NULL, gen_sro, NULL);
}
static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
@@ -524,7 +525,7 @@ static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_rorw);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_rorw, NULL);
}
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
@@ -558,7 +559,7 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, gen_rolw);
+ return gen_shift(ctx, a, EXT_NONE, NULL, gen_rolw, NULL);
}
static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
@@ -566,7 +567,7 @@ static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_grev);
+ return gen_shift(ctx, a, EXT_ZERO, NULL, gen_helper_grev, NULL);
}
static bool trans_greviw(DisasContext *ctx, arg_greviw *a)
@@ -582,7 +583,7 @@ static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, gen_helper_gorc);
+ return gen_shift(ctx, a, EXT_ZERO, NULL, gen_helper_gorc, NULL);
}
static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
@@ -647,5 +648,5 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_EXT(ctx, RVB);
- return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_slli_uw, NULL);
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index c284dd19b3..aa1e3f07e5 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -270,17 +270,20 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
- return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE,
+ tcg_gen_shli_tl, tcg_gen_shli_tl, NULL);
}
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
- return gen_shift_imm_fn(ctx, a, EXT_ZERO, tcg_gen_shri_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_ZERO,
+ tcg_gen_shri_tl, tcg_gen_shri_tl, NULL);
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
- return gen_shift_imm_fn(ctx, a, EXT_SIGN, tcg_gen_sari_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_SIGN,
+ tcg_gen_sari_tl, tcg_gen_sari_tl, NULL);
}
static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -297,7 +300,8 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
static bool trans_sll(DisasContext *ctx, arg_sll *a)
{
- return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
+ return gen_shift(ctx, a, EXT_NONE,
+ tcg_gen_shl_tl, tcg_gen_shl_tl, NULL);
}
static bool trans_slt(DisasContext *ctx, arg_slt *a)
@@ -317,12 +321,12 @@ static bool trans_xor(DisasContext *ctx, arg_xor *a)
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
- return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
+ return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, tcg_gen_shr_tl, NULL);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
- return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
+ return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, tcg_gen_sar_tl, NULL);
}
static bool trans_or(DisasContext *ctx, arg_or *a)
@@ -339,15 +343,14 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_arith_imm_fn(ctx, a, EXT_NONE,
- NULL, tcg_gen_addi_tl, NULL);
+ return gen_arith_imm_fn(ctx, a, EXT_NONE, NULL, tcg_gen_addi_tl, NULL);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, tcg_gen_shli_tl);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, tcg_gen_shli_tl, NULL);
}
static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
@@ -359,7 +362,7 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_srliw);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_srliw, NULL);
}
static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
@@ -371,7 +374,7 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_sraiw);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_sraiw, NULL);
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)
@@ -392,21 +395,24 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift(ctx, a, EXT_NONE, tcg_gen_shl_tl);
+ return gen_shift(ctx, a, EXT_NONE,
+ tcg_gen_shl_tl, tcg_gen_shl_tl, NULL);
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
+ return gen_shift(ctx, a, EXT_ZERO,
+ NULL, tcg_gen_shr_tl, NULL);
}
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
+ return gen_shift(ctx, a, EXT_SIGN,
+ NULL, tcg_gen_sar_tl, NULL);
}
static bool trans_fence(DisasContext *ctx, arg_fence *a)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
This patch is kind of a mess because several files have to be slightly
modified to allow for a new target. Most of these modifications have to deal
with changing what was a binary choice into a ternary one. Although we did
our best to avoid testing for TARGET_RISCV128 (which we did), it is
implicitly there in '#else' statements.
Most added infrastructure files are no far from being copies of the 64-bit
version.
Once this patch applied, adding risc128-sofmmu to --target-list produces
a (no so useful yet) executable.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
configs/devices/riscv128-softmmu/default.mak | 17 +++++++
configs/targets/riscv128-softmmu.mak | 6 +++
include/hw/riscv/sifive_cpu.h | 3 ++
target/riscv/cpu-param.h | 5 ++
target/riscv/cpu.c | 47 ++++++++++++++++---
target/riscv/gdbstub.c | 3 ++
target/riscv/insn_trans/trans_rvd.c.inc | 12 ++---
target/riscv/insn_trans/trans_rvf.c.inc | 6 +--
gdb-xml/riscv-128bit-cpu.xml | 48 ++++++++++++++++++++
gdb-xml/riscv-128bit-virtual.xml | 12 +++++
target/riscv/Kconfig | 3 ++
11 files changed, 147 insertions(+), 15 deletions(-)
create mode 100644 configs/devices/riscv128-softmmu/default.mak
create mode 100644 configs/targets/riscv128-softmmu.mak
create mode 100644 gdb-xml/riscv-128bit-cpu.xml
create mode 100644 gdb-xml/riscv-128bit-virtual.xml
diff --git a/configs/devices/riscv128-softmmu/default.mak b/configs/devices/riscv128-softmmu/default.mak
new file mode 100644
index 0000000000..e838f35785
--- /dev/null
+++ b/configs/devices/riscv128-softmmu/default.mak
@@ -0,0 +1,17 @@
+# Default configuration for riscv128-softmmu
+
+# Uncomment the following lines to disable these optional devices:
+#
+#CONFIG_PCI_DEVICES=n
+# No does not seem to be an option for these two parameters
+CONFIG_SEMIHOSTING=y
+CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+
+# Boards:
+#
+CONFIG_SPIKE=n
+CONFIG_SIFIVE_E=n
+CONFIG_SIFIVE_U=n
+CONFIG_RISCV_VIRT=y
+CONFIG_MICROCHIP_PFSOC=n
+CONFIG_SHAKTI_C=n
diff --git a/configs/targets/riscv128-softmmu.mak b/configs/targets/riscv128-softmmu.mak
new file mode 100644
index 0000000000..7e5976bbf3
--- /dev/null
+++ b/configs/targets/riscv128-softmmu.mak
@@ -0,0 +1,6 @@
+#For now a raw copy of the riscv64 version as changing TARGET_ARCH to riscv64 might trigger to much stuff for now
+TARGET_ARCH=riscv128
+TARGET_BASE_ARCH=riscv
+TARGET_SUPPORTS_MTTCG=y
+TARGET_XML_FILES=gdb-xml/riscv-128bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-128bit-virtual.xml
+TARGET_NEED_FDT=y
diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
index 136799633a..64078feba8 100644
--- a/include/hw/riscv/sifive_cpu.h
+++ b/include/hw/riscv/sifive_cpu.h
@@ -26,6 +26,9 @@
#elif defined(TARGET_RISCV64)
#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
+#else
+#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
+#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
#endif
#endif /* HW_SIFIVE_CPU_H */
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index 80eb615f93..c10459b56f 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -16,6 +16,11 @@
# define TARGET_LONG_BITS 32
# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
+#else
+/* 64-bit target, since QEMU isn't built to have TARGET_LONG_BITS over 64 */
+# define TARGET_LONG_BITS 64
+# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
+# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
/*
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 02417be926..fc75f659fa 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -110,18 +110,36 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
bool riscv_cpu_is_32bit(CPURISCVState *env)
{
- if (env->misa & RV64) {
- return false;
- }
+ return (env->misa & MXLEN_MASK) == RV32;
+}
+
+bool riscv_cpu_is_64bit(CPURISCVState *env)
+{
+ return (env->misa & MXLEN_MASK) == RV64;
+}
- return true;
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV32)
+bool riscv_cpu_is_128bit(CPURISCVState *env)
+{
+ return false;
+}
+#else
+bool riscv_cpu_is_128bit(CPURISCVState *env)
+{
+ return (env->misah & MXLEN_MASK) == RV128;
}
+#endif
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa_mask = env->misa = misa;
}
+static void set_misah(CPURISCVState *env, target_ulong misah)
+{
+ env->misah_mask = env->misah = misah;
+}
+
static void set_priv_version(CPURISCVState *env, int priv_ver)
{
env->priv_ver = priv_ver;
@@ -158,6 +176,9 @@ static void riscv_any_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
set_misah(env, 0);
+#else
+ set_misa(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ set_misah(env, RV128);
#endif
set_priv_version(env, PRIV_VERSION_1_11_0);
}
@@ -184,7 +205,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
set_priv_version(env, PRIV_VERSION_1_10_0);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
-#else
+#elif defined(TARGET_RISCV32)
static void rv32_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -224,6 +245,14 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
+#else
+static void rv128_base_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ /* We set this in the realise function */
+ set_misa(env, 0);
+ set_misah(env, RV128);
+}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -442,7 +471,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
set_resetvec(env, cpu->cfg.resetvec);
/* If only XLEN is set for misa, then set misa from properties */
- if (env->misa == RV32 || env->misa == RV64) {
+ if (env->misa == RV32 || env->misa == RV64
+ || (env->misah == RV128 && env->misa == 0)
+ ) {
/* Do some ISA extension error checking */
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
error_setg(errp,
@@ -709,6 +740,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
#elif defined(TARGET_RISCV64)
cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+#else
+ cc->gdb_core_xml_file = "riscv-128bit-cpu.xml";
#endif
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
@@ -796,6 +829,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
+#else
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
#endif
};
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index a7a9c0b1fe..a7233948f8 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -204,6 +204,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
#elif defined(TARGET_RISCV64)
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-64bit-virtual.xml", 0);
+#else
+ gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
+ 1, "riscv-128bit-virtual.xml", 0);
#endif
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index db9ae15755..41da696ec4 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -393,11 +393,11 @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
-#ifdef TARGET_RISCV64
+#ifdef TARGET_RISCV32
+ qemu_build_not_reached();
+#else
gen_set_gpr(ctx, a->rd, cpu_fpr[a->rs1]);
return true;
-#else
- qemu_build_not_reached();
#endif
}
@@ -437,11 +437,11 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
-#ifdef TARGET_RISCV64
+#ifdef TARGET_RISCV32
+ qemu_build_not_reached();
+#else
tcg_gen_mov_tl(cpu_fpr[a->rd], get_gpr(ctx, a->rs1, EXT_NONE));
mark_fs_dirty(ctx);
return true;
-#else
- qemu_build_not_reached();
#endif
}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index bddbd418d9..90cc51e5d6 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -311,10 +311,10 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
TCGv dest = dest_gpr(ctx, a->rd);
-#if defined(TARGET_RISCV64)
- tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]);
-#else
+#if defined(TARGET_RISCV32)
tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
+#else
+ tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]);
#endif
gen_set_gpr(ctx, a->rd, dest);
diff --git a/gdb-xml/riscv-128bit-cpu.xml b/gdb-xml/riscv-128bit-cpu.xml
new file mode 100644
index 0000000000..c98168148f
--- /dev/null
+++ b/gdb-xml/riscv-128bit-cpu.xml
@@ -0,0 +1,48 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- Register numbers are hard-coded in order to maintain backward
+ compatibility with older versions of tools that didn't use xml
+ register descriptions. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<!-- FIXME : All GPRs are marked as 64-bits since gdb doesn't like 128-bit registers for now. -->
+<feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="64" type="int" regnum="0"/>
+ <reg name="ra" bitsize="64" type="code_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="tp" bitsize="64" type="data_ptr"/>
+ <reg name="t0" bitsize="64" type="int"/>
+ <reg name="t1" bitsize="64" type="int"/>
+ <reg name="t2" bitsize="64" type="int"/>
+ <reg name="fp" bitsize="64" type="data_ptr"/>
+ <reg name="s1" bitsize="64" type="int"/>
+ <reg name="a0" bitsize="64" type="int"/>
+ <reg name="a1" bitsize="64" type="int"/>
+ <reg name="a2" bitsize="64" type="int"/>
+ <reg name="a3" bitsize="64" type="int"/>
+ <reg name="a4" bitsize="64" type="int"/>
+ <reg name="a5" bitsize="64" type="int"/>
+ <reg name="a6" bitsize="64" type="int"/>
+ <reg name="a7" bitsize="64" type="int"/>
+ <reg name="s2" bitsize="64" type="int"/>
+ <reg name="s3" bitsize="64" type="int"/>
+ <reg name="s4" bitsize="64" type="int"/>
+ <reg name="s5" bitsize="64" type="int"/>
+ <reg name="s6" bitsize="64" type="int"/>
+ <reg name="s7" bitsize="64" type="int"/>
+ <reg name="s8" bitsize="64" type="int"/>
+ <reg name="s9" bitsize="64" type="int"/>
+ <reg name="s10" bitsize="64" type="int"/>
+ <reg name="s11" bitsize="64" type="int"/>
+ <reg name="t3" bitsize="64" type="int"/>
+ <reg name="t4" bitsize="64" type="int"/>
+ <reg name="t5" bitsize="64" type="int"/>
+ <reg name="t6" bitsize="64" type="int"/>
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+</feature>
diff --git a/gdb-xml/riscv-128bit-virtual.xml b/gdb-xml/riscv-128bit-virtual.xml
new file mode 100644
index 0000000000..db9a0ff677
--- /dev/null
+++ b/gdb-xml/riscv-128bit-virtual.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<!-- FIXME : priv marked as 64-bits since gdb doesn't like 128-bit registers for now. -->
+<feature name="org.gnu.gdb.riscv.virtual">
+ <reg name="priv" bitsize="64"/>
+</feature>
diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig
index b9e5932f13..f9ea52a59a 100644
--- a/target/riscv/Kconfig
+++ b/target/riscv/Kconfig
@@ -3,3 +3,6 @@ config RISCV32
config RISCV64
bool
+
+config RISCV128
+ bool
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
This patch is kind of a mess because several files have to be slightly
modified to allow for a new target. Most of these modifications have to deal
with changing what was a binary choice into a ternary one. Although we did
our best to avoid testing for TARGET_RISCV128 (which we did), it is
implicitly there in '#else' statements.
Most added infrastructure files are no far from being copies of the 64-bit
version.
Once this patch applied, adding risc128-sofmmu to --target-list produces
a (no so useful yet) executable.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
configs/devices/riscv128-softmmu/default.mak | 17 +++++++
configs/targets/riscv128-softmmu.mak | 6 +++
include/hw/riscv/sifive_cpu.h | 3 ++
target/riscv/cpu-param.h | 5 ++
target/riscv/cpu.c | 47 ++++++++++++++++---
target/riscv/gdbstub.c | 3 ++
target/riscv/insn_trans/trans_rvd.c.inc | 12 ++---
target/riscv/insn_trans/trans_rvf.c.inc | 6 +--
gdb-xml/riscv-128bit-cpu.xml | 48 ++++++++++++++++++++
gdb-xml/riscv-128bit-virtual.xml | 12 +++++
target/riscv/Kconfig | 3 ++
11 files changed, 147 insertions(+), 15 deletions(-)
create mode 100644 configs/devices/riscv128-softmmu/default.mak
create mode 100644 configs/targets/riscv128-softmmu.mak
create mode 100644 gdb-xml/riscv-128bit-cpu.xml
create mode 100644 gdb-xml/riscv-128bit-virtual.xml
diff --git a/configs/devices/riscv128-softmmu/default.mak b/configs/devices/riscv128-softmmu/default.mak
new file mode 100644
index 0000000000..e838f35785
--- /dev/null
+++ b/configs/devices/riscv128-softmmu/default.mak
@@ -0,0 +1,17 @@
+# Default configuration for riscv128-softmmu
+
+# Uncomment the following lines to disable these optional devices:
+#
+#CONFIG_PCI_DEVICES=n
+# No does not seem to be an option for these two parameters
+CONFIG_SEMIHOSTING=y
+CONFIG_ARM_COMPATIBLE_SEMIHOSTING=y
+
+# Boards:
+#
+CONFIG_SPIKE=n
+CONFIG_SIFIVE_E=n
+CONFIG_SIFIVE_U=n
+CONFIG_RISCV_VIRT=y
+CONFIG_MICROCHIP_PFSOC=n
+CONFIG_SHAKTI_C=n
diff --git a/configs/targets/riscv128-softmmu.mak b/configs/targets/riscv128-softmmu.mak
new file mode 100644
index 0000000000..7e5976bbf3
--- /dev/null
+++ b/configs/targets/riscv128-softmmu.mak
@@ -0,0 +1,6 @@
+#For now a raw copy of the riscv64 version as changing TARGET_ARCH to riscv64 might trigger to much stuff for now
+TARGET_ARCH=riscv128
+TARGET_BASE_ARCH=riscv
+TARGET_SUPPORTS_MTTCG=y
+TARGET_XML_FILES=gdb-xml/riscv-128bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-128bit-virtual.xml
+TARGET_NEED_FDT=y
diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
index 136799633a..64078feba8 100644
--- a/include/hw/riscv/sifive_cpu.h
+++ b/include/hw/riscv/sifive_cpu.h
@@ -26,6 +26,9 @@
#elif defined(TARGET_RISCV64)
#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
+#else
+#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
+#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
#endif
#endif /* HW_SIFIVE_CPU_H */
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index 80eb615f93..c10459b56f 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -16,6 +16,11 @@
# define TARGET_LONG_BITS 32
# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
+#else
+/* 64-bit target, since QEMU isn't built to have TARGET_LONG_BITS over 64 */
+# define TARGET_LONG_BITS 64
+# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
+# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
/*
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 02417be926..fc75f659fa 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -110,18 +110,36 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
bool riscv_cpu_is_32bit(CPURISCVState *env)
{
- if (env->misa & RV64) {
- return false;
- }
+ return (env->misa & MXLEN_MASK) == RV32;
+}
+
+bool riscv_cpu_is_64bit(CPURISCVState *env)
+{
+ return (env->misa & MXLEN_MASK) == RV64;
+}
- return true;
+#if defined(TARGET_RISCV64) || defined(TARGET_RISCV32)
+bool riscv_cpu_is_128bit(CPURISCVState *env)
+{
+ return false;
+}
+#else
+bool riscv_cpu_is_128bit(CPURISCVState *env)
+{
+ return (env->misah & MXLEN_MASK) == RV128;
}
+#endif
static void set_misa(CPURISCVState *env, target_ulong misa)
{
env->misa_mask = env->misa = misa;
}
+static void set_misah(CPURISCVState *env, target_ulong misah)
+{
+ env->misah_mask = env->misah = misah;
+}
+
static void set_priv_version(CPURISCVState *env, int priv_ver)
{
env->priv_ver = priv_ver;
@@ -158,6 +176,9 @@ static void riscv_any_cpu_init(Object *obj)
#elif defined(TARGET_RISCV64)
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
set_misah(env, 0);
+#else
+ set_misa(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+ set_misah(env, RV128);
#endif
set_priv_version(env, PRIV_VERSION_1_11_0);
}
@@ -184,7 +205,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
set_priv_version(env, PRIV_VERSION_1_10_0);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
-#else
+#elif defined(TARGET_RISCV32)
static void rv32_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
@@ -224,6 +245,14 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
+#else
+static void rv128_base_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ /* We set this in the realise function */
+ set_misa(env, 0);
+ set_misah(env, RV128);
+}
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -442,7 +471,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
set_resetvec(env, cpu->cfg.resetvec);
/* If only XLEN is set for misa, then set misa from properties */
- if (env->misa == RV32 || env->misa == RV64) {
+ if (env->misa == RV32 || env->misa == RV64
+ || (env->misah == RV128 && env->misa == 0)
+ ) {
/* Do some ISA extension error checking */
if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
error_setg(errp,
@@ -709,6 +740,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
#elif defined(TARGET_RISCV64)
cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+#else
+ cc->gdb_core_xml_file = "riscv-128bit-cpu.xml";
#endif
cc->gdb_stop_before_watchpoint = true;
cc->disas_set_info = riscv_cpu_disas_set_info;
@@ -796,6 +829,8 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
+#else
+ DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
#endif
};
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index a7a9c0b1fe..a7233948f8 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -204,6 +204,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
#elif defined(TARGET_RISCV64)
gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
1, "riscv-64bit-virtual.xml", 0);
+#else
+ gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual,
+ 1, "riscv-128bit-virtual.xml", 0);
#endif
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index db9ae15755..41da696ec4 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -393,11 +393,11 @@ static bool trans_fmv_x_d(DisasContext *ctx, arg_fmv_x_d *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
-#ifdef TARGET_RISCV64
+#ifdef TARGET_RISCV32
+ qemu_build_not_reached();
+#else
gen_set_gpr(ctx, a->rd, cpu_fpr[a->rs1]);
return true;
-#else
- qemu_build_not_reached();
#endif
}
@@ -437,11 +437,11 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
-#ifdef TARGET_RISCV64
+#ifdef TARGET_RISCV32
+ qemu_build_not_reached();
+#else
tcg_gen_mov_tl(cpu_fpr[a->rd], get_gpr(ctx, a->rs1, EXT_NONE));
mark_fs_dirty(ctx);
return true;
-#else
- qemu_build_not_reached();
#endif
}
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index bddbd418d9..90cc51e5d6 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -311,10 +311,10 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_x_w *a)
TCGv dest = dest_gpr(ctx, a->rd);
-#if defined(TARGET_RISCV64)
- tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]);
-#else
+#if defined(TARGET_RISCV32)
tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
+#else
+ tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]);
#endif
gen_set_gpr(ctx, a->rd, dest);
diff --git a/gdb-xml/riscv-128bit-cpu.xml b/gdb-xml/riscv-128bit-cpu.xml
new file mode 100644
index 0000000000..c98168148f
--- /dev/null
+++ b/gdb-xml/riscv-128bit-cpu.xml
@@ -0,0 +1,48 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!-- Register numbers are hard-coded in order to maintain backward
+ compatibility with older versions of tools that didn't use xml
+ register descriptions. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<!-- FIXME : All GPRs are marked as 64-bits since gdb doesn't like 128-bit registers for now. -->
+<feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="64" type="int" regnum="0"/>
+ <reg name="ra" bitsize="64" type="code_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="tp" bitsize="64" type="data_ptr"/>
+ <reg name="t0" bitsize="64" type="int"/>
+ <reg name="t1" bitsize="64" type="int"/>
+ <reg name="t2" bitsize="64" type="int"/>
+ <reg name="fp" bitsize="64" type="data_ptr"/>
+ <reg name="s1" bitsize="64" type="int"/>
+ <reg name="a0" bitsize="64" type="int"/>
+ <reg name="a1" bitsize="64" type="int"/>
+ <reg name="a2" bitsize="64" type="int"/>
+ <reg name="a3" bitsize="64" type="int"/>
+ <reg name="a4" bitsize="64" type="int"/>
+ <reg name="a5" bitsize="64" type="int"/>
+ <reg name="a6" bitsize="64" type="int"/>
+ <reg name="a7" bitsize="64" type="int"/>
+ <reg name="s2" bitsize="64" type="int"/>
+ <reg name="s3" bitsize="64" type="int"/>
+ <reg name="s4" bitsize="64" type="int"/>
+ <reg name="s5" bitsize="64" type="int"/>
+ <reg name="s6" bitsize="64" type="int"/>
+ <reg name="s7" bitsize="64" type="int"/>
+ <reg name="s8" bitsize="64" type="int"/>
+ <reg name="s9" bitsize="64" type="int"/>
+ <reg name="s10" bitsize="64" type="int"/>
+ <reg name="s11" bitsize="64" type="int"/>
+ <reg name="t3" bitsize="64" type="int"/>
+ <reg name="t4" bitsize="64" type="int"/>
+ <reg name="t5" bitsize="64" type="int"/>
+ <reg name="t6" bitsize="64" type="int"/>
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+</feature>
diff --git a/gdb-xml/riscv-128bit-virtual.xml b/gdb-xml/riscv-128bit-virtual.xml
new file mode 100644
index 0000000000..db9a0ff677
--- /dev/null
+++ b/gdb-xml/riscv-128bit-virtual.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<!-- FIXME : priv marked as 64-bits since gdb doesn't like 128-bit registers for now. -->
+<feature name="org.gnu.gdb.riscv.virtual">
+ <reg name="priv" bitsize="64"/>
+</feature>
diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig
index b9e5932f13..f9ea52a59a 100644
--- a/target/riscv/Kconfig
+++ b/target/riscv/Kconfig
@@ -3,3 +3,6 @@ config RISCV32
config RISCV64
bool
+
+config RISCV128
+ bool
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 10/27] target/riscv: adding accessors to the registers upper part
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Set and get functions to access the 64 top bits of the register, stored
in the gprh field of the cpu state.
It looks as if the access to the gprh field can not be protected to make
sure it is accessed only in the 128-bit version of the processor because
the misa/misah field is writable (as it should since the spec indicates
that the registers size might be dynamically changeable), although it is
for now only set at initialization time.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 45 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0700c82a36..9a74abecdd 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -251,6 +251,25 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
g_assert_not_reached();
}
+/* Make sure high part of registers not accessed when not 128-bit */
+static inline TCGv cpu_gprh_check(DisasContext *ctx, int reg_num)
+{
+ if (is_128bit(ctx)) {
+ return cpu_gprh[reg_num];
+ } else {
+ /* Cannot use qemu_build_not_reached as misa is rw */
+ return 0;
+ }
+}
+
+static TCGv get_gprh(DisasContext *ctx, int reg_num)
+{
+ if (reg_num == 0 || ctx->w) {
+ return ctx->zero;
+ }
+ return cpu_gprh_check(ctx, reg_num);
+}
+
static TCGv dest_gpr(DisasContext *ctx, int reg_num)
{
if (reg_num == 0 || ctx->w) {
@@ -259,6 +278,14 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
return cpu_gpr[reg_num];
}
+static TCGv dest_gprh(DisasContext *ctx, int reg_num)
+{
+ if (reg_num == 0 || ctx->w) {
+ return temp_new(ctx);
+ }
+ return cpu_gprh_check(ctx, reg_num);
+}
+
static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
{
if (reg_num != 0) {
@@ -270,6 +297,17 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
}
}
+static void gen_set_gprh(DisasContext *ctx, int reg_num, TCGv t)
+{
+ if (reg_num != 0) {
+ if (ctx->w) {
+ tcg_gen_sari_tl(cpu_gprh_check(ctx, reg_num), cpu_gpr[reg_num], 63);
+ } else {
+ tcg_gen_mov_tl(cpu_gprh_check(ctx, reg_num), t);
+ }
+ }
+}
+
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
@@ -404,6 +442,13 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
+ /* Temporary code so that the patch compiles */
+ if (is_128bit(ctx)) {
+ (void)get_gprh(ctx, 6);
+ (void)dest_gprh(ctx, 6);
+ gen_set_gprh(ctx, 6, NULL);
+ }
+
return true;
}
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 10/27] target/riscv: adding accessors to the registers upper part
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Set and get functions to access the 64 top bits of the register, stored
in the gprh field of the cpu state.
It looks as if the access to the gprh field can not be protected to make
sure it is accessed only in the 128-bit version of the processor because
the misa/misah field is writable (as it should since the spec indicates
that the registers size might be dynamically changeable), although it is
for now only set at initialization time.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 45 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0700c82a36..9a74abecdd 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -251,6 +251,25 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
g_assert_not_reached();
}
+/* Make sure high part of registers not accessed when not 128-bit */
+static inline TCGv cpu_gprh_check(DisasContext *ctx, int reg_num)
+{
+ if (is_128bit(ctx)) {
+ return cpu_gprh[reg_num];
+ } else {
+ /* Cannot use qemu_build_not_reached as misa is rw */
+ return 0;
+ }
+}
+
+static TCGv get_gprh(DisasContext *ctx, int reg_num)
+{
+ if (reg_num == 0 || ctx->w) {
+ return ctx->zero;
+ }
+ return cpu_gprh_check(ctx, reg_num);
+}
+
static TCGv dest_gpr(DisasContext *ctx, int reg_num)
{
if (reg_num == 0 || ctx->w) {
@@ -259,6 +278,14 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
return cpu_gpr[reg_num];
}
+static TCGv dest_gprh(DisasContext *ctx, int reg_num)
+{
+ if (reg_num == 0 || ctx->w) {
+ return temp_new(ctx);
+ }
+ return cpu_gprh_check(ctx, reg_num);
+}
+
static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
{
if (reg_num != 0) {
@@ -270,6 +297,17 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
}
}
+static void gen_set_gprh(DisasContext *ctx, int reg_num, TCGv t)
+{
+ if (reg_num != 0) {
+ if (ctx->w) {
+ tcg_gen_sari_tl(cpu_gprh_check(ctx, reg_num), cpu_gpr[reg_num], 63);
+ } else {
+ tcg_gen_mov_tl(cpu_gprh_check(ctx, reg_num), t);
+ }
+ }
+}
+
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
@@ -404,6 +442,13 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
+ /* Temporary code so that the patch compiles */
+ if (is_128bit(ctx)) {
+ (void)get_gprh(ctx, 6);
+ (void)dest_gprh(ctx, 6);
+ gen_set_gprh(ctx, 6, NULL);
+ }
+
return true;
}
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
The code generation helpers are now able to handle also the 128-bit
functions, although no such function exists yet.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 102 +++++++++++++++++++++++++++++++++------
1 file changed, 88 insertions(+), 14 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9a74abecdd..b3f70bcde0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -442,11 +442,14 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
- /* Temporary code so that the patch compiles */
if (is_128bit(ctx)) {
- (void)get_gprh(ctx, 6);
- (void)dest_gprh(ctx, 6);
- gen_set_gprh(ctx, 6, NULL);
+ uint64_t immh = -(a->imm < 0);
+ src1 = get_gprh(ctx, a->rs1);
+ dest = dest_gprh(ctx, a->rd);
+
+ func(dest, src1, immh);
+
+ gen_set_gprh(ctx, a->rd, dest);
}
return true;
@@ -463,6 +466,15 @@ static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
+ if (is_128bit(ctx)) {
+ dest = dest_gprh(ctx, a->rd);
+ src1 = get_gprh(ctx, a->rs1);
+ src2 = get_gprh(ctx, a->rs2);
+
+ func(dest, src1, src2);
+
+ gen_set_gprh(ctx, a->rd, dest);
+ }
return true;
}
@@ -485,8 +497,16 @@ static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
fn64(dest, src1, a->imm);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd);
+
+ fn128(destl, desth, src1l, src1h, a->imm);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
}
return true;
}
@@ -512,8 +532,18 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
fn64(dest, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd),
+ imml = tcg_constant_tl(a->imm),
+ immh = tcg_constant_tl(-(a->imm < 0));
+
+ fn128(destl, desth, src1l, src1h, imml, immh);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
}
return true;
}
@@ -540,8 +570,21 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
fn64(dest, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ src2l = get_gpr(ctx, a->rs2, ext),
+ src2h = get_gprh(ctx, a->rs2),
+ destl = tcg_temp_new(),
+ desth = tcg_temp_new();
+
+ fn128(destl, desth, src1l, src1h, src2l, src2h);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ tcg_temp_free(destl);
+ tcg_temp_free(desth);
}
return true;
}
@@ -579,8 +622,24 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
fn64(dest, src1, a->shamt);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ if ((ctx->w && a->shamt >= 32)
+ || (!ctx->w && a->shamt >= 128)) {
+ return false;
+ }
+
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ destl = tcg_temp_new(),
+ desth = tcg_temp_new();
+
+ fn128(destl, desth, src1l, src1h, a->shamt);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ tcg_temp_free(destl);
+ tcg_temp_free(desth);
}
return true;
}
@@ -632,8 +691,23 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
tcg_temp_free(ext2);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ src2l = get_gpr(ctx, a->rs2, EXT_NONE),
+ destl = tcg_temp_new(),
+ desth = tcg_temp_new(),
+ shamt = tcg_temp_new();
+
+ tcg_gen_andi_tl(shamt, src2l, !ctx->w << 5 | 0x1f);
+ fn128(destl, desth, src1l, src1h, shamt);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ tcg_temp_free(destl);
+ tcg_temp_free(desth);
+ tcg_temp_free(shamt);
}
return true;
}
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
The code generation helpers are now able to handle also the 128-bit
functions, although no such function exists yet.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 102 +++++++++++++++++++++++++++++++++------
1 file changed, 88 insertions(+), 14 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9a74abecdd..b3f70bcde0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -442,11 +442,14 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
- /* Temporary code so that the patch compiles */
if (is_128bit(ctx)) {
- (void)get_gprh(ctx, 6);
- (void)dest_gprh(ctx, 6);
- gen_set_gprh(ctx, 6, NULL);
+ uint64_t immh = -(a->imm < 0);
+ src1 = get_gprh(ctx, a->rs1);
+ dest = dest_gprh(ctx, a->rd);
+
+ func(dest, src1, immh);
+
+ gen_set_gprh(ctx, a->rd, dest);
}
return true;
@@ -463,6 +466,15 @@ static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
+ if (is_128bit(ctx)) {
+ dest = dest_gprh(ctx, a->rd);
+ src1 = get_gprh(ctx, a->rs1);
+ src2 = get_gprh(ctx, a->rs2);
+
+ func(dest, src1, src2);
+
+ gen_set_gprh(ctx, a->rd, dest);
+ }
return true;
}
@@ -485,8 +497,16 @@ static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
fn64(dest, src1, a->imm);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd);
+
+ fn128(destl, desth, src1l, src1h, a->imm);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
}
return true;
}
@@ -512,8 +532,18 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
fn64(dest, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd),
+ imml = tcg_constant_tl(a->imm),
+ immh = tcg_constant_tl(-(a->imm < 0));
+
+ fn128(destl, desth, src1l, src1h, imml, immh);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
}
return true;
}
@@ -540,8 +570,21 @@ static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
fn64(dest, src1, src2);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ src2l = get_gpr(ctx, a->rs2, ext),
+ src2h = get_gprh(ctx, a->rs2),
+ destl = tcg_temp_new(),
+ desth = tcg_temp_new();
+
+ fn128(destl, desth, src1l, src1h, src2l, src2h);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ tcg_temp_free(destl);
+ tcg_temp_free(desth);
}
return true;
}
@@ -579,8 +622,24 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
fn64(dest, src1, a->shamt);
gen_set_gpr(ctx, a->rd, dest);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ if ((ctx->w && a->shamt >= 32)
+ || (!ctx->w && a->shamt >= 128)) {
+ return false;
+ }
+
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ destl = tcg_temp_new(),
+ desth = tcg_temp_new();
+
+ fn128(destl, desth, src1l, src1h, a->shamt);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ tcg_temp_free(destl);
+ tcg_temp_free(desth);
}
return true;
}
@@ -632,8 +691,23 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
tcg_temp_free(ext2);
- } else {
- return false;
+ } else if (is_128bit(ctx)) {
+ TCGv src1l = get_gpr(ctx, a->rs1, ext),
+ src1h = get_gprh(ctx, a->rs1),
+ src2l = get_gpr(ctx, a->rs2, EXT_NONE),
+ destl = tcg_temp_new(),
+ desth = tcg_temp_new(),
+ shamt = tcg_temp_new();
+
+ tcg_gen_andi_tl(shamt, src2l, !ctx->w << 5 | 0x1f);
+ fn128(destl, desth, src1l, src1h, shamt);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ tcg_temp_free(destl);
+ tcg_temp_free(desth);
+ tcg_temp_free(shamt);
}
return true;
}
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 12/27] target/riscv: moving some insns close to similar insns
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
where they more logically belong.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++-------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index aa1e3f07e5..9e5782d1f5 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -177,6 +177,18 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
return gen_load(ctx, a, MO_TEUW);
}
+static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
+{
+ REQUIRE_64BIT(ctx);
+ return gen_load(ctx, a, MO_TEUL);
+}
+
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+ REQUIRE_64BIT(ctx);
+ return gen_load(ctx, a, MO_TEQ);
+}
+
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -207,18 +219,6 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
return gen_store(ctx, a, MO_TESL);
}
-static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
-{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEUL);
-}
-
-static bool trans_ld(DisasContext *ctx, arg_ld *a)
-{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEQ);
-}
-
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
REQUIRE_64BIT(ctx);
@@ -314,11 +314,6 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu, NULL);
}
-static bool trans_xor(DisasContext *ctx, arg_xor *a)
-{
- return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl);
-}
-
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, tcg_gen_shr_tl, NULL);
@@ -329,6 +324,11 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, tcg_gen_sar_tl, NULL);
}
+static bool trans_xor(DisasContext *ctx, arg_xor *a)
+{
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl);
+}
+
static bool trans_or(DisasContext *ctx, arg_or *a)
{
return gen_logic(ctx, a, EXT_NONE, tcg_gen_or_tl);
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 12/27] target/riscv: moving some insns close to similar insns
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
where they more logically belong.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++-------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index aa1e3f07e5..9e5782d1f5 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -177,6 +177,18 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
return gen_load(ctx, a, MO_TEUW);
}
+static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
+{
+ REQUIRE_64BIT(ctx);
+ return gen_load(ctx, a, MO_TEUL);
+}
+
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+ REQUIRE_64BIT(ctx);
+ return gen_load(ctx, a, MO_TEQ);
+}
+
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -207,18 +219,6 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
return gen_store(ctx, a, MO_TESL);
}
-static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
-{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEUL);
-}
-
-static bool trans_ld(DisasContext *ctx, arg_ld *a)
-{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEQ);
-}
-
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
REQUIRE_64BIT(ctx);
@@ -314,11 +314,6 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu, NULL);
}
-static bool trans_xor(DisasContext *ctx, arg_xor *a)
-{
- return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl);
-}
-
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, tcg_gen_shr_tl, NULL);
@@ -329,6 +324,11 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, tcg_gen_sar_tl, NULL);
}
+static bool trans_xor(DisasContext *ctx, arg_xor *a)
+{
+ return gen_logic(ctx, a, EXT_NONE, tcg_gen_xor_tl);
+}
+
static bool trans_or(DisasContext *ctx, arg_or *a)
{
return gen_logic(ctx, a, EXT_NONE, tcg_gen_or_tl);
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 13/27] target/riscv: rename a few gen function helpers
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Add the tl suffix to the existing integer gen_xxx functions that apply to
target_long types for which a 128-bit version will also exist, so
that it is immediately visible which function is for which type(s).
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++++++---------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 9e5782d1f5..ab85693364 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -136,7 +136,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
return gen_branch(ctx, a, TCG_COND_GEU);
}
-static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
+static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
{
TCGv dest = dest_gpr(ctx, a->rd);
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -152,6 +152,11 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
return true;
}
+static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
+{
+ return gen_load_tl(ctx, a, memop);
+}
+
static bool trans_lb(DisasContext *ctx, arg_lb *a)
{
return gen_load(ctx, a, MO_SB);
@@ -189,7 +194,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a)
return gen_load(ctx, a, MO_TEQ);
}
-static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
+static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
{
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
@@ -204,6 +209,11 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
return true;
}
+static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
+{
+ return gen_store_tl(ctx, a, memop);
+}
+
static bool trans_sb(DisasContext *ctx, arg_sb *a)
{
return gen_store(ctx, a, MO_SB);
@@ -231,12 +241,12 @@ static bool trans_addi(DisasContext *ctx, arg_addi *a)
tcg_gen_addi_tl, tcg_gen_addi_tl, NULL);
}
-static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
+static void gen_slt_tl(TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
}
-static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
+static void gen_sltu_tl(TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
}
@@ -244,13 +254,13 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
return gen_arith_imm_tl(ctx, a, EXT_SIGN,
- gen_slt, gen_slt, NULL);
+ gen_slt_lt, gen_slt_lt, NULL);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
return gen_arith_imm_tl(ctx, a, EXT_SIGN,
- gen_sltu, gen_sltu, NULL);
+ gen_sltu_lt, gen_sltu_lt, NULL);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
@@ -306,12 +316,12 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_slt, gen_slt, NULL);
+ return gen_arith(ctx, a, EXT_SIGN, gen_slt_lt, gen_slt_lt, NULL);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu, NULL);
+ return gen_arith(ctx, a, EXT_SIGN, gen_sltu_lt, gen_sltu_lt, NULL);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -353,7 +363,7 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, tcg_gen_shli_tl, NULL);
}
-static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
+static void gen_srliw_tl(TCGv dst, TCGv src, target_long shamt)
{
tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
}
@@ -362,10 +372,10 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_srliw, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_srliw_tl, NULL);
}
-static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
+static void gen_sraiw_tl(TCGv dst, TCGv src, target_long shamt)
{
tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
}
@@ -374,7 +384,7 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_sraiw, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_sraiw_tl, NULL);
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 13/27] target/riscv: rename a few gen function helpers
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Add the tl suffix to the existing integer gen_xxx functions that apply to
target_long types for which a 128-bit version will also exist, so
that it is immediately visible which function is for which type(s).
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++++++---------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 9e5782d1f5..ab85693364 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -136,7 +136,7 @@ static bool trans_bgeu(DisasContext *ctx, arg_bgeu *a)
return gen_branch(ctx, a, TCG_COND_GEU);
}
-static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
+static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
{
TCGv dest = dest_gpr(ctx, a->rd);
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -152,6 +152,11 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
return true;
}
+static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
+{
+ return gen_load_tl(ctx, a, memop);
+}
+
static bool trans_lb(DisasContext *ctx, arg_lb *a)
{
return gen_load(ctx, a, MO_SB);
@@ -189,7 +194,7 @@ static bool trans_ld(DisasContext *ctx, arg_ld *a)
return gen_load(ctx, a, MO_TEQ);
}
-static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
+static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
{
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
TCGv data = get_gpr(ctx, a->rs2, EXT_NONE);
@@ -204,6 +209,11 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
return true;
}
+static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
+{
+ return gen_store_tl(ctx, a, memop);
+}
+
static bool trans_sb(DisasContext *ctx, arg_sb *a)
{
return gen_store(ctx, a, MO_SB);
@@ -231,12 +241,12 @@ static bool trans_addi(DisasContext *ctx, arg_addi *a)
tcg_gen_addi_tl, tcg_gen_addi_tl, NULL);
}
-static void gen_slt(TCGv ret, TCGv s1, TCGv s2)
+static void gen_slt_tl(TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
}
-static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
+static void gen_sltu_tl(TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
}
@@ -244,13 +254,13 @@ static void gen_sltu(TCGv ret, TCGv s1, TCGv s2)
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
return gen_arith_imm_tl(ctx, a, EXT_SIGN,
- gen_slt, gen_slt, NULL);
+ gen_slt_lt, gen_slt_lt, NULL);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
return gen_arith_imm_tl(ctx, a, EXT_SIGN,
- gen_sltu, gen_sltu, NULL);
+ gen_sltu_lt, gen_sltu_lt, NULL);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
@@ -306,12 +316,12 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_slt, gen_slt, NULL);
+ return gen_arith(ctx, a, EXT_SIGN, gen_slt_lt, gen_slt_lt, NULL);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_sltu, gen_sltu, NULL);
+ return gen_arith(ctx, a, EXT_SIGN, gen_sltu_lt, gen_sltu_lt, NULL);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -353,7 +363,7 @@ static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, tcg_gen_shli_tl, NULL);
}
-static void gen_srliw(TCGv dst, TCGv src, target_long shamt)
+static void gen_srliw_tl(TCGv dst, TCGv src, target_long shamt)
{
tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
}
@@ -362,10 +372,10 @@ static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_srliw, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_srliw_tl, NULL);
}
-static void gen_sraiw(TCGv dst, TCGv src, target_long shamt)
+static void gen_sraiw_tl(TCGv dst, TCGv src, target_long shamt)
{
tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
}
@@ -374,7 +384,7 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_sraiw, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_sraiw_tl, NULL);
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 14/27] target/riscv: 128-bit support for instructions using gen_arith/gen_logic
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
The RISCV ISA is such that the arithmetic and logic instructions have the
same opcode, irrelevant of the base register size.
So, for all arithmetic and logic insns existing for the 3 register sizes,
excluding shifts, this patch adds the support for the 128-bit computations.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 223 +++++++++++++++++++++---
1 file changed, 198 insertions(+), 25 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index ab85693364..814aa5f1b7 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -26,14 +26,17 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
{
- REQUIRE_64BIT(ctx);
- return trans_illegal(ctx, a);
+ REQUIRE_64_OR_128BIT(ctx);
+ return trans_illegal(ctx, a);
}
static bool trans_lui(DisasContext *ctx, arg_lui *a)
{
if (a->rd != 0) {
tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
+ if (is_128bit(ctx)) {
+ tcg_gen_movi_tl(cpu_gprh_check(ctx, a->rd), -(a->imm < 0));
+ }
}
return true;
}
@@ -41,7 +44,19 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
if (a->rd != 0) {
+ if (is_128bit(ctx)) {
+ /* TODO : when pc is 128 bits, use all its bits */
+ TCGv pc = tcg_constant_tl(ctx->base.pc_next),
+ imm = tcg_constant_tl(a->imm),
+ immh = tcg_constant_tl(-(a->imm < 0)),
+ zero = tcg_constant_tl(0);
+ tcg_gen_add2_tl(cpu_gpr[a->rd], cpu_gprh_check(ctx, a->rd),
+ pc, zero,
+ imm, immh);
+ return true;
+ }
tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
+ return true;
}
return true;
}
@@ -84,13 +99,121 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
return true;
}
+/*
+ * Comparison predicates using bitwise logic taken from Hacker's Delight, 2.12
+ * We are just interested in the sign bit, so rl is not used but for subtracting
+ */
+static bool gen_setcond_i128(TCGv rl, TCGv rh,
+ TCGv al, TCGv ah,
+ TCGv bl, TCGv bh,
+ TCGCond cond)
+{
+ switch (cond) {
+ case TCG_COND_EQ:
+ tcg_gen_setcond_tl(TCG_COND_EQ, rl, al, bl);
+ tcg_gen_setcond_tl(TCG_COND_EQ, rh, ah, bh);
+ tcg_gen_and_tl(rl, rl, rh);
+ break;
+
+ case TCG_COND_NE:
+ tcg_gen_setcond_tl(TCG_COND_NE, rl, al, bl);
+ tcg_gen_setcond_tl(TCG_COND_NE, rh, ah, bh);
+ tcg_gen_or_tl(rl, rl, rh);
+ break;
+
+ case TCG_COND_LT:
+ {
+ TCGv tmp1 = tcg_temp_new(),
+ tmp2 = tcg_temp_new();
+
+ tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh);
+ tcg_gen_xor_tl(tmp1, rh, ah);
+ tcg_gen_xor_tl(tmp2, ah, bh);
+ tcg_gen_and_tl(tmp1, tmp1, tmp2);
+ tcg_gen_xor_tl(tmp1, rh, tmp1);
+ tcg_gen_shri_tl(rl, tmp1, 63);
+
+ tcg_temp_free(tmp1);
+ tcg_temp_free(tmp2);
+ break;
+ }
+
+ case TCG_COND_GE:
+ /* Invert result of TCG_COND_LT */
+ gen_setcond_i128(rl, rh, al, ah, bl, bh, TCG_COND_LT);
+ tcg_gen_xori_tl(rl, rl, 1);
+ break;
+
+ case TCG_COND_LTU:
+ {
+ TCGv tmp1 = tcg_temp_new(),
+ tmp2 = tcg_temp_new();
+
+ tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh);
+ tcg_gen_eqv_tl(tmp1, ah, bh);
+ tcg_gen_and_tl(tmp1, tmp1, rh);
+ tcg_gen_andc_tl(tmp2, bh, ah);
+ tcg_gen_or_tl(tmp1, tmp1, tmp2);
+ tcg_gen_shri_tl(rl, tmp1, 63);
+
+ tcg_temp_free(tmp1);
+ tcg_temp_free(tmp2);
+ break;
+ }
+
+ case TCG_COND_GEU:
+ /* Invert result of TCG_COND_LTU */
+ gen_setcond_i128(rl, rh, al, ah, bl, bh, TCG_COND_LTU);
+ tcg_gen_xori_tl(rl, rl, 1);
+ break;
+
+ default:
+ return false;
+ }
+ tcg_gen_movi_tl(rh, 0);
+ return true;
+}
+
static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
{
TCGLabel *l = gen_new_label();
TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
- tcg_gen_brcond_tl(cond, src1, src2, l);
+ if (is_128bit(ctx)) {
+ TCGv src1h = get_gprh(ctx, a->rs1),
+ src2h = get_gprh(ctx, a->rs2),
+ tmpl = tcg_temp_new(),
+ tmph = tcg_temp_new();
+
+ /*
+ * Do not use gen_setcond_i128 for EQ and NE as these conditions are
+ * often met and can be more efficiently implemented.
+ */
+ if (cond == TCG_COND_EQ || cond == TCG_COND_NE) {
+ /*
+ * bnez and beqz being used quite often too, lets optimize them,
+ * although QEMU's tcg optimizer handles these cases nicely
+ */
+ if (a->rs2 == 0) {
+ tcg_gen_or_tl(tmpl, src1, src1h);
+ tcg_gen_brcondi_tl(cond, tmpl, 0, l);
+ } else {
+ tcg_gen_xor_tl(tmpl, src1, src2);
+ tcg_gen_xor_tl(tmph, src1h, src2h);
+ tcg_gen_or_tl(tmpl, tmpl, tmph);
+ tcg_gen_brcondi_tl(cond, tmpl, 0, l);
+ }
+ } else {
+ gen_setcond_i128(tmpl, tmph, src1, src1h, src2, src2h, cond);
+ tcg_gen_brcondi_tl(TCG_COND_NE, tmpl, 0, l);
+ }
+
+ tcg_temp_free(tmph);
+ tcg_temp_free(tmpl);
+ } else {
+ tcg_gen_brcond_tl(cond, src1, src2, l);
+ }
gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
gen_set_label(l); /* branch taken */
@@ -235,10 +358,18 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
return gen_store(ctx, a, MO_TEQ);
}
+static void gen_addi2_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long imm)
+{
+ TCGv imml = tcg_constant_tl(imm),
+ immh = tcg_constant_tl(-(imm < 0));
+ tcg_gen_add2_tl(retl, reth, srcl, srch, imml, immh);
+}
+
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
return gen_arith_imm_fn(ctx, a, EXT_NONE,
- tcg_gen_addi_tl, tcg_gen_addi_tl, NULL);
+ tcg_gen_addi_tl, tcg_gen_addi_tl, gen_addi2_i128);
}
static void gen_slt_tl(TCGv ret, TCGv s1, TCGv s2)
@@ -246,21 +377,33 @@ static void gen_slt_tl(TCGv ret, TCGv s1, TCGv s2)
tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
}
+static void gen_slt_i128(TCGv retl, TCGv reth,
+ TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h)
+{
+ gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LT);
+}
+
static void gen_sltu_tl(TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
}
+static void gen_sltu_i128(TCGv retl, TCGv reth,
+ TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h)
+{
+ gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LTU);
+}
+
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
return gen_arith_imm_tl(ctx, a, EXT_SIGN,
- gen_slt_lt, gen_slt_lt, NULL);
+ gen_slt_tl, gen_slt_tl, gen_slt_i128);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
return gen_arith_imm_tl(ctx, a, EXT_SIGN,
- gen_sltu_lt, gen_sltu_lt, NULL);
+ gen_sltu_tl, gen_sltu_tl, gen_sltu_i128);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
@@ -299,13 +442,13 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
return gen_arith(ctx, a, EXT_NONE,
- tcg_gen_add_tl, tcg_gen_add_tl, NULL);
+ tcg_gen_add_tl, tcg_gen_add_tl, tcg_gen_add2_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
return gen_arith(ctx, a, EXT_NONE,
- tcg_gen_sub_tl, tcg_gen_sub_tl, NULL);
+ tcg_gen_sub_tl, tcg_gen_sub_tl, tcg_gen_sub2_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -316,22 +459,26 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_slt_lt, gen_slt_lt, NULL);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_slt_tl, gen_slt_tl, gen_slt_i128);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_sltu_lt, gen_sltu_lt, NULL);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_sltu_tl, gen_sltu_tl, gen_sltu_i128);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
- return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, tcg_gen_shr_tl, NULL);
+ return gen_shift(ctx, a, EXT_ZERO,
+ tcg_gen_shr_tl, tcg_gen_shr_tl, NULL);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
- return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, tcg_gen_sar_tl, NULL);
+ return gen_shift(ctx, a, EXT_SIGN,
+ tcg_gen_sar_tl, tcg_gen_sar_tl, NULL);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
@@ -349,18 +496,26 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
return gen_logic(ctx, a, EXT_NONE, tcg_gen_and_tl);
}
+static void gen_addiw_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long imm)
+{
+ tcg_gen_addi_tl(retl, srcl, imm);
+}
+
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_arith_imm_fn(ctx, a, EXT_NONE, NULL, tcg_gen_addi_tl, NULL);
+ return gen_arith_imm_fn(ctx, a, EXT_NONE,
+ NULL, tcg_gen_addi_tl, gen_addiw_i128);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, tcg_gen_shli_tl, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE,
+ NULL, tcg_gen_shli_tl, NULL);
}
static void gen_srliw_tl(TCGv dst, TCGv src, target_long shamt)
@@ -370,9 +525,10 @@ static void gen_srliw_tl(TCGv dst, TCGv src, target_long shamt)
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_srliw_tl, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE,
+ NULL, gen_srliw_tl, NULL);
}
static void gen_sraiw_tl(TCGv dst, TCGv src, target_long shamt)
@@ -382,23 +538,40 @@ static void gen_sraiw_tl(TCGv dst, TCGv src, target_long shamt)
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_sraiw_tl, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE,
+ NULL, gen_sraiw_tl, NULL);
+}
+
+static void gen_addw_i128(TCGv retl, TCGv reth,
+ TCGv src1l, TCGv src1h,
+ TCGv src2l, TCGv src2h)
+{
+ tcg_gen_add_tl(retl, src1l, src2l);
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_arith(ctx, a, EXT_NONE, NULL, tcg_gen_add_tl, NULL);
+ return gen_arith(ctx, a, EXT_NONE,
+ NULL, tcg_gen_add_tl, gen_addw_i128);
+}
+
+static void gen_subw_i128(TCGv retl, TCGv reth,
+ TCGv src1l, TCGv src1h,
+ TCGv src2l, TCGv src2h)
+{
+ tcg_gen_sub_tl(retl, src1l, src2l);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_arith(ctx, a, EXT_NONE, NULL, tcg_gen_sub_tl, NULL);
+ return gen_arith(ctx, a, EXT_NONE,
+ NULL, tcg_gen_sub_tl, gen_subw_i128);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
@@ -406,7 +579,7 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
REQUIRE_64BIT(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_NONE,
- tcg_gen_shl_tl, tcg_gen_shl_tl, NULL);
+ NULL, tcg_gen_shl_tl, NULL);
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 14/27] target/riscv: 128-bit support for instructions using gen_arith/gen_logic
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
The RISCV ISA is such that the arithmetic and logic instructions have the
same opcode, irrelevant of the base register size.
So, for all arithmetic and logic insns existing for the 3 register sizes,
excluding shifts, this patch adds the support for the 128-bit computations.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 223 +++++++++++++++++++++---
1 file changed, 198 insertions(+), 25 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index ab85693364..814aa5f1b7 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -26,14 +26,17 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
{
- REQUIRE_64BIT(ctx);
- return trans_illegal(ctx, a);
+ REQUIRE_64_OR_128BIT(ctx);
+ return trans_illegal(ctx, a);
}
static bool trans_lui(DisasContext *ctx, arg_lui *a)
{
if (a->rd != 0) {
tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
+ if (is_128bit(ctx)) {
+ tcg_gen_movi_tl(cpu_gprh_check(ctx, a->rd), -(a->imm < 0));
+ }
}
return true;
}
@@ -41,7 +44,19 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
if (a->rd != 0) {
+ if (is_128bit(ctx)) {
+ /* TODO : when pc is 128 bits, use all its bits */
+ TCGv pc = tcg_constant_tl(ctx->base.pc_next),
+ imm = tcg_constant_tl(a->imm),
+ immh = tcg_constant_tl(-(a->imm < 0)),
+ zero = tcg_constant_tl(0);
+ tcg_gen_add2_tl(cpu_gpr[a->rd], cpu_gprh_check(ctx, a->rd),
+ pc, zero,
+ imm, immh);
+ return true;
+ }
tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
+ return true;
}
return true;
}
@@ -84,13 +99,121 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
return true;
}
+/*
+ * Comparison predicates using bitwise logic taken from Hacker's Delight, 2.12
+ * We are just interested in the sign bit, so rl is not used but for subtracting
+ */
+static bool gen_setcond_i128(TCGv rl, TCGv rh,
+ TCGv al, TCGv ah,
+ TCGv bl, TCGv bh,
+ TCGCond cond)
+{
+ switch (cond) {
+ case TCG_COND_EQ:
+ tcg_gen_setcond_tl(TCG_COND_EQ, rl, al, bl);
+ tcg_gen_setcond_tl(TCG_COND_EQ, rh, ah, bh);
+ tcg_gen_and_tl(rl, rl, rh);
+ break;
+
+ case TCG_COND_NE:
+ tcg_gen_setcond_tl(TCG_COND_NE, rl, al, bl);
+ tcg_gen_setcond_tl(TCG_COND_NE, rh, ah, bh);
+ tcg_gen_or_tl(rl, rl, rh);
+ break;
+
+ case TCG_COND_LT:
+ {
+ TCGv tmp1 = tcg_temp_new(),
+ tmp2 = tcg_temp_new();
+
+ tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh);
+ tcg_gen_xor_tl(tmp1, rh, ah);
+ tcg_gen_xor_tl(tmp2, ah, bh);
+ tcg_gen_and_tl(tmp1, tmp1, tmp2);
+ tcg_gen_xor_tl(tmp1, rh, tmp1);
+ tcg_gen_shri_tl(rl, tmp1, 63);
+
+ tcg_temp_free(tmp1);
+ tcg_temp_free(tmp2);
+ break;
+ }
+
+ case TCG_COND_GE:
+ /* Invert result of TCG_COND_LT */
+ gen_setcond_i128(rl, rh, al, ah, bl, bh, TCG_COND_LT);
+ tcg_gen_xori_tl(rl, rl, 1);
+ break;
+
+ case TCG_COND_LTU:
+ {
+ TCGv tmp1 = tcg_temp_new(),
+ tmp2 = tcg_temp_new();
+
+ tcg_gen_sub2_tl(rl, rh, al, ah, bl, bh);
+ tcg_gen_eqv_tl(tmp1, ah, bh);
+ tcg_gen_and_tl(tmp1, tmp1, rh);
+ tcg_gen_andc_tl(tmp2, bh, ah);
+ tcg_gen_or_tl(tmp1, tmp1, tmp2);
+ tcg_gen_shri_tl(rl, tmp1, 63);
+
+ tcg_temp_free(tmp1);
+ tcg_temp_free(tmp2);
+ break;
+ }
+
+ case TCG_COND_GEU:
+ /* Invert result of TCG_COND_LTU */
+ gen_setcond_i128(rl, rh, al, ah, bl, bh, TCG_COND_LTU);
+ tcg_gen_xori_tl(rl, rl, 1);
+ break;
+
+ default:
+ return false;
+ }
+ tcg_gen_movi_tl(rh, 0);
+ return true;
+}
+
static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond)
{
TCGLabel *l = gen_new_label();
TCGv src1 = get_gpr(ctx, a->rs1, EXT_SIGN);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_SIGN);
- tcg_gen_brcond_tl(cond, src1, src2, l);
+ if (is_128bit(ctx)) {
+ TCGv src1h = get_gprh(ctx, a->rs1),
+ src2h = get_gprh(ctx, a->rs2),
+ tmpl = tcg_temp_new(),
+ tmph = tcg_temp_new();
+
+ /*
+ * Do not use gen_setcond_i128 for EQ and NE as these conditions are
+ * often met and can be more efficiently implemented.
+ */
+ if (cond == TCG_COND_EQ || cond == TCG_COND_NE) {
+ /*
+ * bnez and beqz being used quite often too, lets optimize them,
+ * although QEMU's tcg optimizer handles these cases nicely
+ */
+ if (a->rs2 == 0) {
+ tcg_gen_or_tl(tmpl, src1, src1h);
+ tcg_gen_brcondi_tl(cond, tmpl, 0, l);
+ } else {
+ tcg_gen_xor_tl(tmpl, src1, src2);
+ tcg_gen_xor_tl(tmph, src1h, src2h);
+ tcg_gen_or_tl(tmpl, tmpl, tmph);
+ tcg_gen_brcondi_tl(cond, tmpl, 0, l);
+ }
+ } else {
+ gen_setcond_i128(tmpl, tmph, src1, src1h, src2, src2h, cond);
+ tcg_gen_brcondi_tl(TCG_COND_NE, tmpl, 0, l);
+ }
+
+ tcg_temp_free(tmph);
+ tcg_temp_free(tmpl);
+ } else {
+ tcg_gen_brcond_tl(cond, src1, src2, l);
+ }
gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
gen_set_label(l); /* branch taken */
@@ -235,10 +358,18 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
return gen_store(ctx, a, MO_TEQ);
}
+static void gen_addi2_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long imm)
+{
+ TCGv imml = tcg_constant_tl(imm),
+ immh = tcg_constant_tl(-(imm < 0));
+ tcg_gen_add2_tl(retl, reth, srcl, srch, imml, immh);
+}
+
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
return gen_arith_imm_fn(ctx, a, EXT_NONE,
- tcg_gen_addi_tl, tcg_gen_addi_tl, NULL);
+ tcg_gen_addi_tl, tcg_gen_addi_tl, gen_addi2_i128);
}
static void gen_slt_tl(TCGv ret, TCGv s1, TCGv s2)
@@ -246,21 +377,33 @@ static void gen_slt_tl(TCGv ret, TCGv s1, TCGv s2)
tcg_gen_setcond_tl(TCG_COND_LT, ret, s1, s2);
}
+static void gen_slt_i128(TCGv retl, TCGv reth,
+ TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h)
+{
+ gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LT);
+}
+
static void gen_sltu_tl(TCGv ret, TCGv s1, TCGv s2)
{
tcg_gen_setcond_tl(TCG_COND_LTU, ret, s1, s2);
}
+static void gen_sltu_i128(TCGv retl, TCGv reth,
+ TCGv s1l, TCGv s1h, TCGv s2l, TCGv s2h)
+{
+ gen_setcond_i128(retl, reth, s1l, s1h, s2l, s2h, TCG_COND_LTU);
+}
+
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
return gen_arith_imm_tl(ctx, a, EXT_SIGN,
- gen_slt_lt, gen_slt_lt, NULL);
+ gen_slt_tl, gen_slt_tl, gen_slt_i128);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
return gen_arith_imm_tl(ctx, a, EXT_SIGN,
- gen_sltu_lt, gen_sltu_lt, NULL);
+ gen_sltu_tl, gen_sltu_tl, gen_sltu_i128);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
@@ -299,13 +442,13 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
return gen_arith(ctx, a, EXT_NONE,
- tcg_gen_add_tl, tcg_gen_add_tl, NULL);
+ tcg_gen_add_tl, tcg_gen_add_tl, tcg_gen_add2_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
return gen_arith(ctx, a, EXT_NONE,
- tcg_gen_sub_tl, tcg_gen_sub_tl, NULL);
+ tcg_gen_sub_tl, tcg_gen_sub_tl, tcg_gen_sub2_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -316,22 +459,26 @@ static bool trans_sll(DisasContext *ctx, arg_sll *a)
static bool trans_slt(DisasContext *ctx, arg_slt *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_slt_lt, gen_slt_lt, NULL);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_slt_tl, gen_slt_tl, gen_slt_i128);
}
static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
{
- return gen_arith(ctx, a, EXT_SIGN, gen_sltu_lt, gen_sltu_lt, NULL);
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_sltu_tl, gen_sltu_tl, gen_sltu_i128);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
- return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl, tcg_gen_shr_tl, NULL);
+ return gen_shift(ctx, a, EXT_ZERO,
+ tcg_gen_shr_tl, tcg_gen_shr_tl, NULL);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
- return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl, tcg_gen_sar_tl, NULL);
+ return gen_shift(ctx, a, EXT_SIGN,
+ tcg_gen_sar_tl, tcg_gen_sar_tl, NULL);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
@@ -349,18 +496,26 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
return gen_logic(ctx, a, EXT_NONE, tcg_gen_and_tl);
}
+static void gen_addiw_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long imm)
+{
+ tcg_gen_addi_tl(retl, srcl, imm);
+}
+
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_arith_imm_fn(ctx, a, EXT_NONE, NULL, tcg_gen_addi_tl, NULL);
+ return gen_arith_imm_fn(ctx, a, EXT_NONE,
+ NULL, tcg_gen_addi_tl, gen_addiw_i128);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, tcg_gen_shli_tl, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE,
+ NULL, tcg_gen_shli_tl, NULL);
}
static void gen_srliw_tl(TCGv dst, TCGv src, target_long shamt)
@@ -370,9 +525,10 @@ static void gen_srliw_tl(TCGv dst, TCGv src, target_long shamt)
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_srliw_tl, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE,
+ NULL, gen_srliw_tl, NULL);
}
static void gen_sraiw_tl(TCGv dst, TCGv src, target_long shamt)
@@ -382,23 +538,40 @@ static void gen_sraiw_tl(TCGv dst, TCGv src, target_long shamt)
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, gen_sraiw_tl, NULL);
+ return gen_shift_imm_fn(ctx, a, EXT_NONE,
+ NULL, gen_sraiw_tl, NULL);
+}
+
+static void gen_addw_i128(TCGv retl, TCGv reth,
+ TCGv src1l, TCGv src1h,
+ TCGv src2l, TCGv src2h)
+{
+ tcg_gen_add_tl(retl, src1l, src2l);
}
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_arith(ctx, a, EXT_NONE, NULL, tcg_gen_add_tl, NULL);
+ return gen_arith(ctx, a, EXT_NONE,
+ NULL, tcg_gen_add_tl, gen_addw_i128);
+}
+
+static void gen_subw_i128(TCGv retl, TCGv reth,
+ TCGv src1l, TCGv src1h,
+ TCGv src2l, TCGv src2h)
+{
+ tcg_gen_sub_tl(retl, src1l, src2l);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
- return gen_arith(ctx, a, EXT_NONE, NULL, tcg_gen_sub_tl, NULL);
+ return gen_arith(ctx, a, EXT_NONE,
+ NULL, tcg_gen_sub_tl, gen_subw_i128);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
@@ -406,7 +579,7 @@ static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
REQUIRE_64BIT(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_NONE,
- tcg_gen_shl_tl, tcg_gen_shl_tl, NULL);
+ NULL, tcg_gen_shl_tl, NULL);
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 15/27] target/riscv: 128-bit support for instructions using gen_shift
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Support for the base shift instructions working on 128-bit registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 224 ++++++++++++++++++++++--
1 file changed, 209 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 814aa5f1b7..eca9a76ad5 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -421,22 +421,61 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
}
+static void gen_slli_i128(TCGv retl, TCGv reth,
+ TCGv src1l, TCGv src1h,
+ target_long shamt)
+{
+ if (shamt >= 64) {
+ tcg_gen_shli_tl(reth, src1l, shamt - 64);
+ tcg_gen_movi_tl(retl, 0);
+ } else {
+ tcg_gen_extract2_tl(reth, src1l, src1h, 64 - shamt);
+ tcg_gen_shli_tl(retl, src1l, shamt);
+ }
+}
+
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
return gen_shift_imm_fn(ctx, a, EXT_NONE,
- tcg_gen_shli_tl, tcg_gen_shli_tl, NULL);
+ tcg_gen_shli_tl, tcg_gen_shli_tl, gen_slli_i128);
+}
+
+static void gen_srli_i128(TCGv retl, TCGv reth,
+ TCGv src1l, TCGv src1h,
+ target_long shamt)
+{
+ if (shamt >= 64) {
+ tcg_gen_shri_tl(retl, src1h, shamt - 64);
+ tcg_gen_movi_tl(reth, 0);
+ } else {
+ tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
+ tcg_gen_shri_tl(reth, src1h, shamt);
+ }
}
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
return gen_shift_imm_fn(ctx, a, EXT_ZERO,
- tcg_gen_shri_tl, tcg_gen_shri_tl, NULL);
+ tcg_gen_shri_tl, tcg_gen_shri_tl, gen_srli_i128);
+}
+
+static void gen_srai_i128(TCGv retl, TCGv reth,
+ TCGv src1l, TCGv src1h,
+ target_long shamt)
+{
+ if (shamt >= 64) {
+ tcg_gen_sari_tl(retl, src1h, shamt - 64);
+ tcg_gen_sari_tl(reth, src1h, 63);
+ } else {
+ tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
+ tcg_gen_sari_tl(reth, src1h, shamt);
+ }
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
return gen_shift_imm_fn(ctx, a, EXT_SIGN,
- tcg_gen_sari_tl, tcg_gen_sari_tl, NULL);
+ tcg_gen_sari_tl, tcg_gen_sari_tl, gen_srai_i128);
}
static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -451,10 +490,76 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
tcg_gen_sub_tl, tcg_gen_sub_tl, tcg_gen_sub2_tl);
}
+enum M128_DIR {
+ M128_LEFT,
+ M128_RIGHT,
+ M128_RIGHT_ARITH
+};
+/* 127 <= arg2 <= 0 */
+static void gen_shift_mod128(TCGv ret, TCGv arg1, TCGv arg2, enum M128_DIR dir)
+{
+ TCGv tmp1 = tcg_temp_new(),
+ tmp2 = tcg_temp_new(),
+ sgn = tcg_temp_new(),
+ cnst_zero = tcg_constant_tl(0);
+
+ tcg_gen_setcondi_tl(TCG_COND_GEU, tmp1, arg2, 64);
+
+ tcg_gen_andi_tl(tmp2, arg2, 0x3f);
+ switch (dir) {
+ case M128_LEFT:
+ tcg_gen_shl_tl(tmp2, arg1, tmp2);
+ break;
+ case M128_RIGHT:
+ tcg_gen_shr_tl(tmp2, arg1, tmp2);
+ break;
+ case M128_RIGHT_ARITH:
+ tcg_gen_sar_tl(tmp2, arg1, tmp2);
+ break;
+ }
+
+ if (dir == M128_RIGHT_ARITH) {
+ tcg_gen_sari_tl(sgn, arg1, 63);
+ tcg_gen_movcond_tl(TCG_COND_NE, ret, tmp1, cnst_zero, sgn, tmp2);
+ } else {
+ tcg_gen_movcond_tl(TCG_COND_NE, ret, tmp1, cnst_zero, cnst_zero, tmp2);
+ }
+
+ tcg_temp_free(tmp1);
+ tcg_temp_free(tmp2);
+ tcg_temp_free(sgn);
+ return;
+}
+
+static void gen_sll_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ TCGv tmp = tcg_temp_new();
+ /*
+ * From Hacker's Delight 2.17:
+ * y1 = x1 << n | x0 u>> (64 - n) | x0 << (n - 64)
+ */
+ gen_shift_mod128(desth, src1h, shamt, M128_LEFT);
+
+ tcg_gen_movi_tl(tmp, 64);
+ tcg_gen_sub_tl(tmp, tmp, shamt);
+ gen_shift_mod128(tmp, src1l, tmp, M128_RIGHT);
+ tcg_gen_or_tl(desth, desth, tmp);
+
+ tcg_gen_subi_tl(tmp, shamt, 64);
+ gen_shift_mod128(tmp, src1l, tmp, M128_LEFT);
+ tcg_gen_or_tl(desth, desth, tmp);
+
+ /* From Hacker's Delight 2.17: y0 = x0 << n */
+ gen_shift_mod128(destl, src1l, shamt, M128_LEFT);
+
+ tcg_temp_free(tmp);
+}
+
static bool trans_sll(DisasContext *ctx, arg_sll *a)
{
return gen_shift(ctx, a, EXT_NONE,
- tcg_gen_shl_tl, tcg_gen_shl_tl, NULL);
+ tcg_gen_shl_tl, tcg_gen_shl_tl, gen_sll_i128);
}
static bool trans_slt(DisasContext *ctx, arg_slt *a)
@@ -469,16 +574,69 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
gen_sltu_tl, gen_sltu_tl, gen_sltu_i128);
}
+static void gen_srl_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ TCGv tmp = tcg_temp_new();
+ /*
+ * From Hacker's Delight 2.17:
+ * y0 = x0 u>> n | x1 << (64 - n) | x1 u>> (n - 64)
+ */
+ gen_shift_mod128(destl, src1l, shamt, M128_RIGHT);
+
+ tcg_gen_movi_tl(tmp, 64);
+ tcg_gen_sub_tl(tmp, tmp, shamt);
+ gen_shift_mod128(tmp, src1h, tmp, M128_LEFT);
+ tcg_gen_or_tl(destl, destl, tmp);
+
+ tcg_gen_subi_tl(tmp, shamt, 64);
+ gen_shift_mod128(tmp, src1h, tmp, M128_RIGHT);
+ tcg_gen_or_tl(destl, destl, tmp);
+
+ /* From Hacker's Delight 2.17 : y1 = x1 u>> n */
+ gen_shift_mod128(desth, src1h, shamt, M128_RIGHT);
+
+ tcg_temp_free(tmp);
+}
+
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
return gen_shift(ctx, a, EXT_ZERO,
- tcg_gen_shr_tl, tcg_gen_shr_tl, NULL);
+ tcg_gen_shr_tl, tcg_gen_shr_tl, gen_srl_i128);
+}
+
+static void gen_sra_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ TCGv tmp1 = tcg_temp_new(),
+ tmp2 = tcg_temp_new(),
+ const64 = tcg_constant_tl(64);
+
+ /* Compute y0 value if n < 64: x0 u>> n | x1 << (64 - n) */
+ gen_shift_mod128(tmp1, src1l, shamt, M128_RIGHT);
+ tcg_gen_movi_tl(tmp2, 64);
+ tcg_gen_sub_tl(tmp2, tmp2, shamt);
+ gen_shift_mod128(tmp2, src1h, tmp2, M128_LEFT);
+ tcg_gen_or_tl(tmp1, tmp1, tmp2);
+
+ /* Compute y0 value if n >= 64: x1 s>> (n - 64) */
+ tcg_gen_subi_tl(tmp2, shamt, 64);
+ gen_shift_mod128(tmp2, src1h, tmp2, M128_RIGHT_ARITH);
+
+ /* Conditionally move one value or the other */
+ tcg_gen_movcond_tl(TCG_COND_LT, destl, shamt, const64, tmp1, tmp2);
+
+ /* y1 = x1 s>> n */
+ gen_shift_mod128(desth, src1h, shamt, M128_RIGHT_ARITH);
+
+ tcg_temp_free(tmp1);
+ tcg_temp_free(tmp2);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
return gen_shift(ctx, a, EXT_SIGN,
- tcg_gen_sar_tl, tcg_gen_sar_tl, NULL);
+ tcg_gen_sar_tl, tcg_gen_sar_tl, gen_sra_i128);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
@@ -510,12 +668,18 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
NULL, tcg_gen_addi_tl, gen_addiw_i128);
}
+static void gen_slliwd_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long shamt)
+{
+ tcg_gen_shli_tl(retl, srcl, shamt);
+}
+
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift_imm_fn(ctx, a, EXT_NONE,
- NULL, tcg_gen_shli_tl, NULL);
+ NULL, tcg_gen_shli_tl, gen_slliwd_i128);
}
static void gen_srliw_tl(TCGv dst, TCGv src, target_long shamt)
@@ -523,12 +687,18 @@ static void gen_srliw_tl(TCGv dst, TCGv src, target_long shamt)
tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
}
+static void gen_srliw_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long shamt)
+{
+ gen_srliw_tl(retl, srcl, shamt);
+}
+
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift_imm_fn(ctx, a, EXT_NONE,
- NULL, gen_srliw_tl, NULL);
+ NULL, gen_srliw_tl, gen_srliw_i128);
}
static void gen_sraiw_tl(TCGv dst, TCGv src, target_long shamt)
@@ -536,12 +706,18 @@ static void gen_sraiw_tl(TCGv dst, TCGv src, target_long shamt)
tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
}
+static void gen_sraiw_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long shamt)
+{
+ gen_sraiw_tl(retl, srcl, shamt);
+}
+
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift_imm_fn(ctx, a, EXT_NONE,
- NULL, gen_sraiw_tl, NULL);
+ NULL, gen_sraiw_tl, gen_sraiw_i128);
}
static void gen_addw_i128(TCGv retl, TCGv reth,
@@ -574,28 +750,46 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a)
NULL, tcg_gen_sub_tl, gen_subw_i128);
}
+static void gen_sllwd_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ tcg_gen_shl_tl(destl, src1l, shamt);
+}
+
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_NONE,
- NULL, tcg_gen_shl_tl, NULL);
+ NULL, tcg_gen_shl_tl, gen_sllwd_i128);
+}
+
+static void gen_srlwd_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ tcg_gen_shr_tl(destl, src1l, shamt);
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_ZERO,
- NULL, tcg_gen_shr_tl, NULL);
+ NULL, tcg_gen_shr_tl, gen_srlwd_i128);
+}
+
+static void gen_srawd_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ tcg_gen_sar_tl(destl, src1l, shamt);
}
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_SIGN,
- NULL, tcg_gen_sar_tl, NULL);
+ NULL, tcg_gen_sar_tl, gen_srawd_i128);
}
static bool trans_fence(DisasContext *ctx, arg_fence *a)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 15/27] target/riscv: 128-bit support for instructions using gen_shift
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Support for the base shift instructions working on 128-bit registers.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 224 ++++++++++++++++++++++--
1 file changed, 209 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 814aa5f1b7..eca9a76ad5 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -421,22 +421,61 @@ static bool trans_andi(DisasContext *ctx, arg_andi *a)
return gen_logic_imm_fn(ctx, a, EXT_NONE, tcg_gen_andi_tl);
}
+static void gen_slli_i128(TCGv retl, TCGv reth,
+ TCGv src1l, TCGv src1h,
+ target_long shamt)
+{
+ if (shamt >= 64) {
+ tcg_gen_shli_tl(reth, src1l, shamt - 64);
+ tcg_gen_movi_tl(retl, 0);
+ } else {
+ tcg_gen_extract2_tl(reth, src1l, src1h, 64 - shamt);
+ tcg_gen_shli_tl(retl, src1l, shamt);
+ }
+}
+
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
return gen_shift_imm_fn(ctx, a, EXT_NONE,
- tcg_gen_shli_tl, tcg_gen_shli_tl, NULL);
+ tcg_gen_shli_tl, tcg_gen_shli_tl, gen_slli_i128);
+}
+
+static void gen_srli_i128(TCGv retl, TCGv reth,
+ TCGv src1l, TCGv src1h,
+ target_long shamt)
+{
+ if (shamt >= 64) {
+ tcg_gen_shri_tl(retl, src1h, shamt - 64);
+ tcg_gen_movi_tl(reth, 0);
+ } else {
+ tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
+ tcg_gen_shri_tl(reth, src1h, shamt);
+ }
}
static bool trans_srli(DisasContext *ctx, arg_srli *a)
{
return gen_shift_imm_fn(ctx, a, EXT_ZERO,
- tcg_gen_shri_tl, tcg_gen_shri_tl, NULL);
+ tcg_gen_shri_tl, tcg_gen_shri_tl, gen_srli_i128);
+}
+
+static void gen_srai_i128(TCGv retl, TCGv reth,
+ TCGv src1l, TCGv src1h,
+ target_long shamt)
+{
+ if (shamt >= 64) {
+ tcg_gen_sari_tl(retl, src1h, shamt - 64);
+ tcg_gen_sari_tl(reth, src1h, 63);
+ } else {
+ tcg_gen_extract2_tl(retl, src1l, src1h, shamt);
+ tcg_gen_sari_tl(reth, src1h, shamt);
+ }
}
static bool trans_srai(DisasContext *ctx, arg_srai *a)
{
return gen_shift_imm_fn(ctx, a, EXT_SIGN,
- tcg_gen_sari_tl, tcg_gen_sari_tl, NULL);
+ tcg_gen_sari_tl, tcg_gen_sari_tl, gen_srai_i128);
}
static bool trans_add(DisasContext *ctx, arg_add *a)
@@ -451,10 +490,76 @@ static bool trans_sub(DisasContext *ctx, arg_sub *a)
tcg_gen_sub_tl, tcg_gen_sub_tl, tcg_gen_sub2_tl);
}
+enum M128_DIR {
+ M128_LEFT,
+ M128_RIGHT,
+ M128_RIGHT_ARITH
+};
+/* 127 <= arg2 <= 0 */
+static void gen_shift_mod128(TCGv ret, TCGv arg1, TCGv arg2, enum M128_DIR dir)
+{
+ TCGv tmp1 = tcg_temp_new(),
+ tmp2 = tcg_temp_new(),
+ sgn = tcg_temp_new(),
+ cnst_zero = tcg_constant_tl(0);
+
+ tcg_gen_setcondi_tl(TCG_COND_GEU, tmp1, arg2, 64);
+
+ tcg_gen_andi_tl(tmp2, arg2, 0x3f);
+ switch (dir) {
+ case M128_LEFT:
+ tcg_gen_shl_tl(tmp2, arg1, tmp2);
+ break;
+ case M128_RIGHT:
+ tcg_gen_shr_tl(tmp2, arg1, tmp2);
+ break;
+ case M128_RIGHT_ARITH:
+ tcg_gen_sar_tl(tmp2, arg1, tmp2);
+ break;
+ }
+
+ if (dir == M128_RIGHT_ARITH) {
+ tcg_gen_sari_tl(sgn, arg1, 63);
+ tcg_gen_movcond_tl(TCG_COND_NE, ret, tmp1, cnst_zero, sgn, tmp2);
+ } else {
+ tcg_gen_movcond_tl(TCG_COND_NE, ret, tmp1, cnst_zero, cnst_zero, tmp2);
+ }
+
+ tcg_temp_free(tmp1);
+ tcg_temp_free(tmp2);
+ tcg_temp_free(sgn);
+ return;
+}
+
+static void gen_sll_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ TCGv tmp = tcg_temp_new();
+ /*
+ * From Hacker's Delight 2.17:
+ * y1 = x1 << n | x0 u>> (64 - n) | x0 << (n - 64)
+ */
+ gen_shift_mod128(desth, src1h, shamt, M128_LEFT);
+
+ tcg_gen_movi_tl(tmp, 64);
+ tcg_gen_sub_tl(tmp, tmp, shamt);
+ gen_shift_mod128(tmp, src1l, tmp, M128_RIGHT);
+ tcg_gen_or_tl(desth, desth, tmp);
+
+ tcg_gen_subi_tl(tmp, shamt, 64);
+ gen_shift_mod128(tmp, src1l, tmp, M128_LEFT);
+ tcg_gen_or_tl(desth, desth, tmp);
+
+ /* From Hacker's Delight 2.17: y0 = x0 << n */
+ gen_shift_mod128(destl, src1l, shamt, M128_LEFT);
+
+ tcg_temp_free(tmp);
+}
+
static bool trans_sll(DisasContext *ctx, arg_sll *a)
{
return gen_shift(ctx, a, EXT_NONE,
- tcg_gen_shl_tl, tcg_gen_shl_tl, NULL);
+ tcg_gen_shl_tl, tcg_gen_shl_tl, gen_sll_i128);
}
static bool trans_slt(DisasContext *ctx, arg_slt *a)
@@ -469,16 +574,69 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
gen_sltu_tl, gen_sltu_tl, gen_sltu_i128);
}
+static void gen_srl_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ TCGv tmp = tcg_temp_new();
+ /*
+ * From Hacker's Delight 2.17:
+ * y0 = x0 u>> n | x1 << (64 - n) | x1 u>> (n - 64)
+ */
+ gen_shift_mod128(destl, src1l, shamt, M128_RIGHT);
+
+ tcg_gen_movi_tl(tmp, 64);
+ tcg_gen_sub_tl(tmp, tmp, shamt);
+ gen_shift_mod128(tmp, src1h, tmp, M128_LEFT);
+ tcg_gen_or_tl(destl, destl, tmp);
+
+ tcg_gen_subi_tl(tmp, shamt, 64);
+ gen_shift_mod128(tmp, src1h, tmp, M128_RIGHT);
+ tcg_gen_or_tl(destl, destl, tmp);
+
+ /* From Hacker's Delight 2.17 : y1 = x1 u>> n */
+ gen_shift_mod128(desth, src1h, shamt, M128_RIGHT);
+
+ tcg_temp_free(tmp);
+}
+
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
return gen_shift(ctx, a, EXT_ZERO,
- tcg_gen_shr_tl, tcg_gen_shr_tl, NULL);
+ tcg_gen_shr_tl, tcg_gen_shr_tl, gen_srl_i128);
+}
+
+static void gen_sra_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ TCGv tmp1 = tcg_temp_new(),
+ tmp2 = tcg_temp_new(),
+ const64 = tcg_constant_tl(64);
+
+ /* Compute y0 value if n < 64: x0 u>> n | x1 << (64 - n) */
+ gen_shift_mod128(tmp1, src1l, shamt, M128_RIGHT);
+ tcg_gen_movi_tl(tmp2, 64);
+ tcg_gen_sub_tl(tmp2, tmp2, shamt);
+ gen_shift_mod128(tmp2, src1h, tmp2, M128_LEFT);
+ tcg_gen_or_tl(tmp1, tmp1, tmp2);
+
+ /* Compute y0 value if n >= 64: x1 s>> (n - 64) */
+ tcg_gen_subi_tl(tmp2, shamt, 64);
+ gen_shift_mod128(tmp2, src1h, tmp2, M128_RIGHT_ARITH);
+
+ /* Conditionally move one value or the other */
+ tcg_gen_movcond_tl(TCG_COND_LT, destl, shamt, const64, tmp1, tmp2);
+
+ /* y1 = x1 s>> n */
+ gen_shift_mod128(desth, src1h, shamt, M128_RIGHT_ARITH);
+
+ tcg_temp_free(tmp1);
+ tcg_temp_free(tmp2);
}
static bool trans_sra(DisasContext *ctx, arg_sra *a)
{
return gen_shift(ctx, a, EXT_SIGN,
- tcg_gen_sar_tl, tcg_gen_sar_tl, NULL);
+ tcg_gen_sar_tl, tcg_gen_sar_tl, gen_sra_i128);
}
static bool trans_xor(DisasContext *ctx, arg_xor *a)
@@ -510,12 +668,18 @@ static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
NULL, tcg_gen_addi_tl, gen_addiw_i128);
}
+static void gen_slliwd_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long shamt)
+{
+ tcg_gen_shli_tl(retl, srcl, shamt);
+}
+
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)
{
REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift_imm_fn(ctx, a, EXT_NONE,
- NULL, tcg_gen_shli_tl, NULL);
+ NULL, tcg_gen_shli_tl, gen_slliwd_i128);
}
static void gen_srliw_tl(TCGv dst, TCGv src, target_long shamt)
@@ -523,12 +687,18 @@ static void gen_srliw_tl(TCGv dst, TCGv src, target_long shamt)
tcg_gen_extract_tl(dst, src, shamt, 32 - shamt);
}
+static void gen_srliw_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long shamt)
+{
+ gen_srliw_tl(retl, srcl, shamt);
+}
+
static bool trans_srliw(DisasContext *ctx, arg_srliw *a)
{
REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift_imm_fn(ctx, a, EXT_NONE,
- NULL, gen_srliw_tl, NULL);
+ NULL, gen_srliw_tl, gen_srliw_i128);
}
static void gen_sraiw_tl(TCGv dst, TCGv src, target_long shamt)
@@ -536,12 +706,18 @@ static void gen_sraiw_tl(TCGv dst, TCGv src, target_long shamt)
tcg_gen_sextract_tl(dst, src, shamt, 32 - shamt);
}
+static void gen_sraiw_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long shamt)
+{
+ gen_sraiw_tl(retl, srcl, shamt);
+}
+
static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
{
REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift_imm_fn(ctx, a, EXT_NONE,
- NULL, gen_sraiw_tl, NULL);
+ NULL, gen_sraiw_tl, gen_sraiw_i128);
}
static void gen_addw_i128(TCGv retl, TCGv reth,
@@ -574,28 +750,46 @@ static bool trans_subw(DisasContext *ctx, arg_subw *a)
NULL, tcg_gen_sub_tl, gen_subw_i128);
}
+static void gen_sllwd_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ tcg_gen_shl_tl(destl, src1l, shamt);
+}
+
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_NONE,
- NULL, tcg_gen_shl_tl, NULL);
+ NULL, tcg_gen_shl_tl, gen_sllwd_i128);
+}
+
+static void gen_srlwd_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ tcg_gen_shr_tl(destl, src1l, shamt);
}
static bool trans_srlw(DisasContext *ctx, arg_srlw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_ZERO,
- NULL, tcg_gen_shr_tl, NULL);
+ NULL, tcg_gen_shr_tl, gen_srlwd_i128);
+}
+
+static void gen_srawd_i128(TCGv destl, TCGv desth,
+ TCGv src1l, TCGv src1h, TCGv shamt)
+{
+ tcg_gen_sar_tl(destl, src1l, shamt);
}
static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
ctx->w = true;
return gen_shift(ctx, a, EXT_SIGN,
- NULL, tcg_gen_sar_tl, NULL);
+ NULL, tcg_gen_sar_tl, gen_srawd_i128);
}
static bool trans_fence(DisasContext *ctx, arg_fence *a)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 16/27] target/riscv: support for 128-bit loads and store
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
The 128-bit ISA adds ldu, lq and sq. We provide here support for these
instructions. Note that although we compute a 128-bit address, we only use
the lower 64-bit to actually address memory, cowardly utilizing the
existing address translation mechanism of QEMU.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn16.decode | 32 +++++-
target/riscv/insn32.decode | 4 +
target/riscv/insn_trans/trans_rvi.c.inc | 132 ++++++++++++++++++++++--
3 files changed, 157 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 2e9212663c..151fc6e567 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -39,6 +39,10 @@
%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
%imm_lui 12:s1 2:5 !function=ex_shift_12
+# Added for 128 bit support
+%uimm_cl_q 5:2 10:3 !function=ex_shift_3
+%uimm_6bit_lq 2:3 12:1 5:2 !function=ex_shift_3
+%uimm_6bit_sq 7:3 10:3 !function=ex_shift_3
# Argument sets imported from insn32.decode:
&empty !extern
@@ -54,16 +58,20 @@
# Formats 16:
@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
+@cl_q ... . ..... ..... .. &i imm=%uimm_6bit_lq rs1=2 %rd
@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3
+@cs_q ... ... ... .. ... .. &s imm=%uimm_cl_q rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@cj ... ........... .. &j imm=%imm_cj
@cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0
+@c_lqsp ... . ..... ..... .. &i imm=%uimm_6bit_lq rs1=2 %rd
@c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd
@c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
+@c_sqsp ... . ..... ..... .. &s imm=%uimm_6bit_sq rs1=2 rs2=%rs2_5
@c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
@c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
@c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd
@@ -87,9 +95,17 @@
illegal 000 000 000 00 --- 00
addi 000 ... ... .. ... 00 @c_addi4spn
}
-fld 001 ... ... .. ... 00 @cl_d
+{
+ fld 001 ... ... .. ... 00 @cl_d
+ # *** RV128C specific Standard Extension (Quadrant 0) ***
+ lq 001 ... ... .. ... 00 @cl_q
+}
lw 010 ... ... .. ... 00 @cl_w
-fsd 101 ... ... .. ... 00 @cs_d
+{
+ fsd 101 ... ... .. ... 00 @cs_d
+ # *** RV128C specific Standard Extension (Quadrant 0) ***
+ sq 101 ... ... .. ... 00 @cs_q
+}
sw 110 ... ... .. ... 00 @cs_w
# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
@@ -132,7 +148,11 @@ addw 100 1 11 ... 01 ... 01 @cs_2
# *** RV32/64C Standard Extension (Quadrant 2) ***
slli 000 . ..... ..... 10 @c_shift2
-fld 001 . ..... ..... 10 @c_ldsp
+{
+ fld 001 . ..... ..... 10 @c_ldsp
+ # *** RV128C specific Standard Extension (Quadrant 2) ***
+ lq 001 ... ... .. ... 10 @c_lqsp
+}
{
illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
lw 010 . ..... ..... 10 @c_lwsp
@@ -147,7 +167,11 @@ fld 001 . ..... ..... 10 @c_ldsp
jalr 100 1 ..... 00000 10 @c_jalr rd=1 # C.JALR
add 100 1 ..... ..... 10 @cr
}
-fsd 101 ...... ..... 10 @c_sdsp
+{
+ fsd 101 ...... ..... 10 @c_sdsp
+ # *** RV128C specific Standard Extension (Quadrant 2) ***
+ sq 101 ... ... .. ... 10 @c_sqsp
+}
sw 110 . ..... ..... 10 @c_swsp
# *** RV32C and RV64C specific Standard Extension (Quadrant 2) ***
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2cd921d51c..79611cb65d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -163,6 +163,10 @@ sllw 0000000 ..... ..... 001 ..... 0111011 @r
srlw 0000000 ..... ..... 101 ..... 0111011 @r
sraw 0100000 ..... ..... 101 ..... 0111011 @r
+# *** RV128I Base Instruction Set (in addition to RV64I) ***
+ldu ............ ..... 111 ..... 0000011 @i
+lq ............ ..... 010 ..... 0001111 @i
+sq ............ ..... 100 ..... 0100011 @s
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
mulh 0000001 ..... ..... 001 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index eca9a76ad5..1373fe94b9 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -275,9 +275,63 @@ static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
return true;
}
+/*
+ * TODO: we should assert that src1h == 0, as we do not change the
+ * address translation mechanism
+ */
+static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
+{
+ TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src1h = get_gprh(ctx, a->rs1);
+ TCGv destl = dest_gpr(ctx, a->rd);
+ TCGv desth = dest_gprh(ctx, a->rd);
+ TCGv addrl = tcg_temp_new();
+ TCGv addrh = tcg_temp_new();
+ TCGv imml = tcg_temp_new();
+ TCGv immh = tcg_constant_tl(-(a->imm < 0));
+
+ /* Build a 128-bit address */
+ if (a->imm != 0) {
+ tcg_gen_movi_tl(imml, a->imm);
+ tcg_gen_add2_tl(addrl, addrh, src1l, src1h, imml, immh);
+ } else {
+ tcg_gen_mov_tl(addrl, src1l);
+ tcg_gen_mov_tl(addrh, src1h);
+ }
+
+ if (memop != (MemOp)MO_TEO) {
+ tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, memop);
+ if (memop & MO_SIGN) {
+ tcg_gen_sari_tl(desth, destl, 63);
+ } else {
+ tcg_gen_movi_tl(desth, 0);
+ }
+ } else {
+ tcg_gen_qemu_ld_tl(memop & MO_BSWAP ? desth : destl, addrl,
+ ctx->mem_idx, MO_TEQ);
+ tcg_gen_movi_tl(imml, 8);
+ tcg_gen_movi_tl(immh, 0);
+ tcg_gen_add2_tl(addrl, addrh, addrl, addrh, imml, immh);
+ tcg_gen_qemu_ld_tl(memop & MO_BSWAP ? destl : desth, addrl,
+ ctx->mem_idx, MO_TEQ);
+ }
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ tcg_temp_free(addrl);
+ tcg_temp_free(addrh);
+ tcg_temp_free(imml);
+ return true;
+}
+
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
- return gen_load_tl(ctx, a, memop);
+ if (is_128bit(ctx)) {
+ return gen_load_i128(ctx, a, memop);
+ } else {
+ return gen_load_tl(ctx, a, memop);
+ }
}
static bool trans_lb(DisasContext *ctx, arg_lb *a)
@@ -295,6 +349,18 @@ static bool trans_lw(DisasContext *ctx, arg_lw *a)
return gen_load(ctx, a, MO_TESL);
}
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+ REQUIRE_64_OR_128BIT(ctx);
+ return gen_load(ctx, a, MO_TESQ);
+}
+
+static bool trans_lq(DisasContext *ctx, arg_lq *a)
+{
+ REQUIRE_128BIT(ctx);
+ return gen_load(ctx, a, MO_TEO);
+}
+
static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
{
return gen_load(ctx, a, MO_UB);
@@ -307,14 +373,14 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
return gen_load(ctx, a, MO_TEUL);
}
-static bool trans_ld(DisasContext *ctx, arg_ld *a)
+static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEQ);
+ REQUIRE_128BIT(ctx);
+ return gen_load(ctx, a, MO_TEUQ);
}
static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
@@ -332,9 +398,55 @@ static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
return true;
}
+/*
+ * TODO: we should assert that src1h == 0, as we do not change the
+ * address translation mechanism
+ */
+static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
+{
+ TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src1h = get_gprh(ctx, a->rs1);
+ TCGv src2l = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv src2h = get_gprh(ctx, a->rs2);
+ TCGv addrl = tcg_temp_new();
+ TCGv addrh = tcg_temp_new();
+ TCGv imml = tcg_temp_new();
+ TCGv immh = tcg_constant_tl(-(a->imm < 0));
+
+ /* Build a 128-bit address */
+ if (a->imm != 0) {
+ tcg_gen_movi_tl(imml, a->imm);
+ tcg_gen_add2_tl(addrl, addrh, src1l, src1h, imml, immh);
+ } else {
+ tcg_gen_mov_tl(addrl, src1l);
+ tcg_gen_mov_tl(addrh, src1h);
+ }
+
+ if (memop != (MemOp)MO_TEO) {
+ tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop);
+ } else {
+ tcg_gen_qemu_st_tl(memop & MO_BSWAP ? src2h : src2l, addrl,
+ ctx->mem_idx, MO_TEQ);
+ tcg_gen_movi_tl(imml, 8);
+ tcg_gen_movi_tl(immh, 0);
+ tcg_gen_add2_tl(addrl, addrh, addrl, addrh, imml, immh);
+ tcg_gen_qemu_st_tl(memop & MO_BSWAP ? src2l : src2h, addrl,
+ ctx->mem_idx, MO_TEQ);
+ }
+
+ tcg_temp_free(addrl);
+ tcg_temp_free(addrh);
+ tcg_temp_free(imml);
+ return true;
+}
+
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
- return gen_store_tl(ctx, a, memop);
+ if (is_128bit(ctx)) {
+ return gen_store_i128(ctx, a, memop);
+ } else {
+ return gen_store_tl(ctx, a, memop);
+ }
}
static bool trans_sb(DisasContext *ctx, arg_sb *a)
@@ -354,10 +466,16 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
return gen_store(ctx, a, MO_TEQ);
}
+static bool trans_sq(DisasContext *ctx, arg_sq *a)
+{
+ REQUIRE_128BIT(ctx);
+ return gen_store(ctx, a, MO_TEO);
+}
+
static void gen_addi2_i128(TCGv retl, TCGv reth,
TCGv srcl, TCGv srch, target_long imm)
{
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 16/27] target/riscv: support for 128-bit loads and store
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
The 128-bit ISA adds ldu, lq and sq. We provide here support for these
instructions. Note that although we compute a 128-bit address, we only use
the lower 64-bit to actually address memory, cowardly utilizing the
existing address translation mechanism of QEMU.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn16.decode | 32 +++++-
target/riscv/insn32.decode | 4 +
target/riscv/insn_trans/trans_rvi.c.inc | 132 ++++++++++++++++++++++--
3 files changed, 157 insertions(+), 11 deletions(-)
diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 2e9212663c..151fc6e567 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -39,6 +39,10 @@
%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
%imm_lui 12:s1 2:5 !function=ex_shift_12
+# Added for 128 bit support
+%uimm_cl_q 5:2 10:3 !function=ex_shift_3
+%uimm_6bit_lq 2:3 12:1 5:2 !function=ex_shift_3
+%uimm_6bit_sq 7:3 10:3 !function=ex_shift_3
# Argument sets imported from insn32.decode:
&empty !extern
@@ -54,16 +58,20 @@
# Formats 16:
@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
+@cl_q ... . ..... ..... .. &i imm=%uimm_6bit_lq rs1=2 %rd
@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
@cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3
+@cs_q ... ... ... .. ... .. &s imm=%uimm_cl_q rs1=%rs1_3 rs2=%rs2_3
@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
@cj ... ........... .. &j imm=%imm_cj
@cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0
+@c_lqsp ... . ..... ..... .. &i imm=%uimm_6bit_lq rs1=2 %rd
@c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd
@c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
+@c_sqsp ... . ..... ..... .. &s imm=%uimm_6bit_sq rs1=2 rs2=%rs2_5
@c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
@c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
@c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd
@@ -87,9 +95,17 @@
illegal 000 000 000 00 --- 00
addi 000 ... ... .. ... 00 @c_addi4spn
}
-fld 001 ... ... .. ... 00 @cl_d
+{
+ fld 001 ... ... .. ... 00 @cl_d
+ # *** RV128C specific Standard Extension (Quadrant 0) ***
+ lq 001 ... ... .. ... 00 @cl_q
+}
lw 010 ... ... .. ... 00 @cl_w
-fsd 101 ... ... .. ... 00 @cs_d
+{
+ fsd 101 ... ... .. ... 00 @cs_d
+ # *** RV128C specific Standard Extension (Quadrant 0) ***
+ sq 101 ... ... .. ... 00 @cs_q
+}
sw 110 ... ... .. ... 00 @cs_w
# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
@@ -132,7 +148,11 @@ addw 100 1 11 ... 01 ... 01 @cs_2
# *** RV32/64C Standard Extension (Quadrant 2) ***
slli 000 . ..... ..... 10 @c_shift2
-fld 001 . ..... ..... 10 @c_ldsp
+{
+ fld 001 . ..... ..... 10 @c_ldsp
+ # *** RV128C specific Standard Extension (Quadrant 2) ***
+ lq 001 ... ... .. ... 10 @c_lqsp
+}
{
illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
lw 010 . ..... ..... 10 @c_lwsp
@@ -147,7 +167,11 @@ fld 001 . ..... ..... 10 @c_ldsp
jalr 100 1 ..... 00000 10 @c_jalr rd=1 # C.JALR
add 100 1 ..... ..... 10 @cr
}
-fsd 101 ...... ..... 10 @c_sdsp
+{
+ fsd 101 ...... ..... 10 @c_sdsp
+ # *** RV128C specific Standard Extension (Quadrant 2) ***
+ sq 101 ... ... .. ... 10 @c_sqsp
+}
sw 110 . ..... ..... 10 @c_swsp
# *** RV32C and RV64C specific Standard Extension (Quadrant 2) ***
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 2cd921d51c..79611cb65d 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -163,6 +163,10 @@ sllw 0000000 ..... ..... 001 ..... 0111011 @r
srlw 0000000 ..... ..... 101 ..... 0111011 @r
sraw 0100000 ..... ..... 101 ..... 0111011 @r
+# *** RV128I Base Instruction Set (in addition to RV64I) ***
+ldu ............ ..... 111 ..... 0000011 @i
+lq ............ ..... 010 ..... 0001111 @i
+sq ............ ..... 100 ..... 0100011 @s
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
mulh 0000001 ..... ..... 001 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index eca9a76ad5..1373fe94b9 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -275,9 +275,63 @@ static bool gen_load_tl(DisasContext *ctx, arg_lb *a, MemOp memop)
return true;
}
+/*
+ * TODO: we should assert that src1h == 0, as we do not change the
+ * address translation mechanism
+ */
+static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop)
+{
+ TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src1h = get_gprh(ctx, a->rs1);
+ TCGv destl = dest_gpr(ctx, a->rd);
+ TCGv desth = dest_gprh(ctx, a->rd);
+ TCGv addrl = tcg_temp_new();
+ TCGv addrh = tcg_temp_new();
+ TCGv imml = tcg_temp_new();
+ TCGv immh = tcg_constant_tl(-(a->imm < 0));
+
+ /* Build a 128-bit address */
+ if (a->imm != 0) {
+ tcg_gen_movi_tl(imml, a->imm);
+ tcg_gen_add2_tl(addrl, addrh, src1l, src1h, imml, immh);
+ } else {
+ tcg_gen_mov_tl(addrl, src1l);
+ tcg_gen_mov_tl(addrh, src1h);
+ }
+
+ if (memop != (MemOp)MO_TEO) {
+ tcg_gen_qemu_ld_tl(destl, addrl, ctx->mem_idx, memop);
+ if (memop & MO_SIGN) {
+ tcg_gen_sari_tl(desth, destl, 63);
+ } else {
+ tcg_gen_movi_tl(desth, 0);
+ }
+ } else {
+ tcg_gen_qemu_ld_tl(memop & MO_BSWAP ? desth : destl, addrl,
+ ctx->mem_idx, MO_TEQ);
+ tcg_gen_movi_tl(imml, 8);
+ tcg_gen_movi_tl(immh, 0);
+ tcg_gen_add2_tl(addrl, addrh, addrl, addrh, imml, immh);
+ tcg_gen_qemu_ld_tl(memop & MO_BSWAP ? destl : desth, addrl,
+ ctx->mem_idx, MO_TEQ);
+ }
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ tcg_temp_free(addrl);
+ tcg_temp_free(addrh);
+ tcg_temp_free(imml);
+ return true;
+}
+
static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
- return gen_load_tl(ctx, a, memop);
+ if (is_128bit(ctx)) {
+ return gen_load_i128(ctx, a, memop);
+ } else {
+ return gen_load_tl(ctx, a, memop);
+ }
}
static bool trans_lb(DisasContext *ctx, arg_lb *a)
@@ -295,6 +349,18 @@ static bool trans_lw(DisasContext *ctx, arg_lw *a)
return gen_load(ctx, a, MO_TESL);
}
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+ REQUIRE_64_OR_128BIT(ctx);
+ return gen_load(ctx, a, MO_TESQ);
+}
+
+static bool trans_lq(DisasContext *ctx, arg_lq *a)
+{
+ REQUIRE_128BIT(ctx);
+ return gen_load(ctx, a, MO_TEO);
+}
+
static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
{
return gen_load(ctx, a, MO_UB);
@@ -307,14 +373,14 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
return gen_load(ctx, a, MO_TEUL);
}
-static bool trans_ld(DisasContext *ctx, arg_ld *a)
+static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEQ);
+ REQUIRE_128BIT(ctx);
+ return gen_load(ctx, a, MO_TEUQ);
}
static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
@@ -332,9 +398,55 @@ static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
return true;
}
+/*
+ * TODO: we should assert that src1h == 0, as we do not change the
+ * address translation mechanism
+ */
+static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
+{
+ TCGv src1l = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src1h = get_gprh(ctx, a->rs1);
+ TCGv src2l = get_gpr(ctx, a->rs2, EXT_NONE);
+ TCGv src2h = get_gprh(ctx, a->rs2);
+ TCGv addrl = tcg_temp_new();
+ TCGv addrh = tcg_temp_new();
+ TCGv imml = tcg_temp_new();
+ TCGv immh = tcg_constant_tl(-(a->imm < 0));
+
+ /* Build a 128-bit address */
+ if (a->imm != 0) {
+ tcg_gen_movi_tl(imml, a->imm);
+ tcg_gen_add2_tl(addrl, addrh, src1l, src1h, imml, immh);
+ } else {
+ tcg_gen_mov_tl(addrl, src1l);
+ tcg_gen_mov_tl(addrh, src1h);
+ }
+
+ if (memop != (MemOp)MO_TEO) {
+ tcg_gen_qemu_st_tl(src2l, addrl, ctx->mem_idx, memop);
+ } else {
+ tcg_gen_qemu_st_tl(memop & MO_BSWAP ? src2h : src2l, addrl,
+ ctx->mem_idx, MO_TEQ);
+ tcg_gen_movi_tl(imml, 8);
+ tcg_gen_movi_tl(immh, 0);
+ tcg_gen_add2_tl(addrl, addrh, addrl, addrh, imml, immh);
+ tcg_gen_qemu_st_tl(memop & MO_BSWAP ? src2l : src2h, addrl,
+ ctx->mem_idx, MO_TEQ);
+ }
+
+ tcg_temp_free(addrl);
+ tcg_temp_free(addrh);
+ tcg_temp_free(imml);
+ return true;
+}
+
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
- return gen_store_tl(ctx, a, memop);
+ if (is_128bit(ctx)) {
+ return gen_store_i128(ctx, a, memop);
+ } else {
+ return gen_store_tl(ctx, a, memop);
+ }
}
static bool trans_sb(DisasContext *ctx, arg_sb *a)
@@ -354,10 +466,16 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
return gen_store(ctx, a, MO_TEQ);
}
+static bool trans_sq(DisasContext *ctx, arg_sq *a)
+{
+ REQUIRE_128BIT(ctx);
+ return gen_store(ctx, a, MO_TEO);
+}
+
static void gen_addi2_i128(TCGv retl, TCGv reth,
TCGv srcl, TCGv srch, target_long imm)
{
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 17/27] target/riscv: 128-bit double word integer arithmetic instructions
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
The ISA adds the addid, addd and subd instructions that work on 64-bit
while in 128-bit mode. Similarly to what is done for insns working on
32-bit (w suffix), we set a 'd' flag so that masking and sign extension
occurs as it should when using the registers' accessors.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn32.decode | 4 ++
target/riscv/translate.c | 12 ++++--
target/riscv/insn_trans/trans_rvi.c.inc | 50 +++++++++++++++++++++++++
3 files changed, 63 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 79611cb65d..eea540cea9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -167,6 +167,10 @@ sraw 0100000 ..... ..... 101 ..... 0111011 @r
ldu ............ ..... 111 ..... 0000011 @i
lq ............ ..... 010 ..... 0001111 @i
sq ............ ..... 100 ..... 0100011 @s
+addid ............ ..... 000 ..... 1011011 @i
+addd 0000000 ..... ..... 000 ..... 1111011 @r
+subd 0100000 ..... ..... 000 ..... 1111011 @r
+
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
mulh 0000001 ..... ..... 001 ..... 0110011 @r
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b3f70bcde0..120841de48 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -68,6 +68,7 @@ typedef struct DisasContext {
to reset this known value. */
int frm;
bool w;
+ bool d;
bool virt_enabled;
bool ext_ifencei;
bool hlsx;
@@ -264,7 +265,7 @@ static inline TCGv cpu_gprh_check(DisasContext *ctx, int reg_num)
static TCGv get_gprh(DisasContext *ctx, int reg_num)
{
- if (reg_num == 0 || ctx->w) {
+ if (reg_num == 0 || ctx->w || ctx->d) {
return ctx->zero;
}
return cpu_gprh_check(ctx, reg_num);
@@ -300,7 +301,7 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
static void gen_set_gprh(DisasContext *ctx, int reg_num, TCGv t)
{
if (reg_num != 0) {
- if (ctx->w) {
+ if (ctx->w || ctx->d) {
tcg_gen_sari_tl(cpu_gprh_check(ctx, reg_num), cpu_gpr[reg_num], 63);
} else {
tcg_gen_mov_tl(cpu_gprh_check(ctx, reg_num), t);
@@ -699,7 +700,10 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
desth = tcg_temp_new(),
shamt = tcg_temp_new();
- tcg_gen_andi_tl(shamt, src2l, !ctx->w << 5 | 0x1f);
+ tcg_gen_andi_tl(shamt, src2l,
+ (!(ctx->d ^ ctx->w) << 6)
+ | ((ctx->d | !ctx->w) << 5)
+ | 0x1f);
fn128(destl, desth, src1l, src1h, shamt);
gen_set_gpr(ctx, a->rd, destl);
@@ -804,6 +808,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
ctx->cs = cs;
ctx->w = false;
+ ctx->d = false;
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
@@ -830,6 +835,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
decode_opc(env, ctx, opcode16);
ctx->base.pc_next = ctx->pc_succ_insn;
ctx->w = false;
+ ctx->d = false;
for (int i = ctx->ntemp - 1; i >= 0; --i) {
tcg_temp_free(ctx->temp[i]);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 1373fe94b9..05e13bbc1d 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -476,6 +476,56 @@ static bool trans_sq(DisasContext *ctx, arg_sq *a)
return gen_store(ctx, a, MO_TEO);
}
+static bool trans_addd(DisasContext *ctx, arg_addd *a)
+{
+ REQUIRE_128BIT(ctx);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE),
+ src2 = get_gpr(ctx, a->rs2, EXT_NONE),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd);
+
+ ctx->d = true;
+ tcg_gen_add_tl(destl, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ return true;
+}
+
+static bool trans_addid(DisasContext *ctx, arg_addid *a)
+{
+ REQUIRE_128BIT(ctx);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd);
+
+ ctx->d = true;
+ tcg_gen_addi_tl(destl, src1, a->imm);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ return true;
+}
+
+static bool trans_subd(DisasContext *ctx, arg_subd *a)
+{
+ REQUIRE_128BIT(ctx);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE),
+ src2 = get_gpr(ctx, a->rs2, EXT_NONE),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd);
+
+ ctx->d = true;
+ tcg_gen_sub_tl(destl, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ return true;
+}
+
static void gen_addi2_i128(TCGv retl, TCGv reth,
TCGv srcl, TCGv srch, target_long imm)
{
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 17/27] target/riscv: 128-bit double word integer arithmetic instructions
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
The ISA adds the addid, addd and subd instructions that work on 64-bit
while in 128-bit mode. Similarly to what is done for insns working on
32-bit (w suffix), we set a 'd' flag so that masking and sign extension
occurs as it should when using the registers' accessors.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn32.decode | 4 ++
target/riscv/translate.c | 12 ++++--
target/riscv/insn_trans/trans_rvi.c.inc | 50 +++++++++++++++++++++++++
3 files changed, 63 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 79611cb65d..eea540cea9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -167,6 +167,10 @@ sraw 0100000 ..... ..... 101 ..... 0111011 @r
ldu ............ ..... 111 ..... 0000011 @i
lq ............ ..... 010 ..... 0001111 @i
sq ............ ..... 100 ..... 0100011 @s
+addid ............ ..... 000 ..... 1011011 @i
+addd 0000000 ..... ..... 000 ..... 1111011 @r
+subd 0100000 ..... ..... 000 ..... 1111011 @r
+
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
mulh 0000001 ..... ..... 001 ..... 0110011 @r
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b3f70bcde0..120841de48 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -68,6 +68,7 @@ typedef struct DisasContext {
to reset this known value. */
int frm;
bool w;
+ bool d;
bool virt_enabled;
bool ext_ifencei;
bool hlsx;
@@ -264,7 +265,7 @@ static inline TCGv cpu_gprh_check(DisasContext *ctx, int reg_num)
static TCGv get_gprh(DisasContext *ctx, int reg_num)
{
- if (reg_num == 0 || ctx->w) {
+ if (reg_num == 0 || ctx->w || ctx->d) {
return ctx->zero;
}
return cpu_gprh_check(ctx, reg_num);
@@ -300,7 +301,7 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
static void gen_set_gprh(DisasContext *ctx, int reg_num, TCGv t)
{
if (reg_num != 0) {
- if (ctx->w) {
+ if (ctx->w || ctx->d) {
tcg_gen_sari_tl(cpu_gprh_check(ctx, reg_num), cpu_gpr[reg_num], 63);
} else {
tcg_gen_mov_tl(cpu_gprh_check(ctx, reg_num), t);
@@ -699,7 +700,10 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
desth = tcg_temp_new(),
shamt = tcg_temp_new();
- tcg_gen_andi_tl(shamt, src2l, !ctx->w << 5 | 0x1f);
+ tcg_gen_andi_tl(shamt, src2l,
+ (!(ctx->d ^ ctx->w) << 6)
+ | ((ctx->d | !ctx->w) << 5)
+ | 0x1f);
fn128(destl, desth, src1l, src1h, shamt);
gen_set_gpr(ctx, a->rd, destl);
@@ -804,6 +808,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
ctx->cs = cs;
ctx->w = false;
+ ctx->d = false;
ctx->ntemp = 0;
memset(ctx->temp, 0, sizeof(ctx->temp));
@@ -830,6 +835,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
decode_opc(env, ctx, opcode16);
ctx->base.pc_next = ctx->pc_succ_insn;
ctx->w = false;
+ ctx->d = false;
for (int i = ctx->ntemp - 1; i >= 0; --i) {
tcg_temp_free(ctx->temp[i]);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 1373fe94b9..05e13bbc1d 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -476,6 +476,56 @@ static bool trans_sq(DisasContext *ctx, arg_sq *a)
return gen_store(ctx, a, MO_TEO);
}
+static bool trans_addd(DisasContext *ctx, arg_addd *a)
+{
+ REQUIRE_128BIT(ctx);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE),
+ src2 = get_gpr(ctx, a->rs2, EXT_NONE),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd);
+
+ ctx->d = true;
+ tcg_gen_add_tl(destl, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ return true;
+}
+
+static bool trans_addid(DisasContext *ctx, arg_addid *a)
+{
+ REQUIRE_128BIT(ctx);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd);
+
+ ctx->d = true;
+ tcg_gen_addi_tl(destl, src1, a->imm);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ return true;
+}
+
+static bool trans_subd(DisasContext *ctx, arg_subd *a)
+{
+ REQUIRE_128BIT(ctx);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE),
+ src2 = get_gpr(ctx, a->rs2, EXT_NONE),
+ destl = dest_gpr(ctx, a->rd),
+ desth = dest_gprh(ctx, a->rd);
+
+ ctx->d = true;
+ tcg_gen_sub_tl(destl, src1, src2);
+
+ gen_set_gpr(ctx, a->rd, destl);
+ gen_set_gprh(ctx, a->rd, desth);
+
+ return true;
+}
+
static void gen_addi2_i128(TCGv retl, TCGv reth,
TCGv srcl, TCGv srch, target_long imm)
{
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 18/27] target/riscv: 128-bit double word integer shift instructions
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
All variations of shifts on 64-bit values are available in the
128-bit ISA, so we add them now.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn32.decode | 10 +++++
target/riscv/translate.c | 4 +-
target/riscv/insn_trans/trans_rvi.c.inc | 58 +++++++++++++++++++++++++
3 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index eea540cea9..be8d6aa85f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -22,6 +22,7 @@
%rs1 15:5
%rd 7:5
%sh5 20:5
+%sh6 20:6
%sh7 20:7
%csr 20:12
@@ -92,6 +93,9 @@
# Formats 64:
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
+# Formats 128:
+@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
+
# *** Privileged Instructions ***
ecall 000000000000 00000 000 00000 1110011
ebreak 000000000001 00000 000 00000 1110011
@@ -168,8 +172,14 @@ ldu ............ ..... 111 ..... 0000011 @i
lq ............ ..... 010 ..... 0001111 @i
sq ............ ..... 100 ..... 0100011 @s
addid ............ ..... 000 ..... 1011011 @i
+sllid 000000 ...... ..... 001 ..... 1011011 @sh6
+srlid 000000 ...... ..... 101 ..... 1011011 @sh6
+sraid 010000 ...... ..... 101 ..... 1011011 @sh6
addd 0000000 ..... ..... 000 ..... 1111011 @r
subd 0100000 ..... ..... 000 ..... 1111011 @r
+slld 0000000 ..... ..... 001 ..... 1111011 @r
+srld 0000000 ..... ..... 101 ..... 1111011 @r
+srad 0100000 ..... ..... 101 ..... 1111011 @r
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 120841de48..195dc3f461 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -624,8 +624,8 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
} else if (is_128bit(ctx)) {
- if ((ctx->w && a->shamt >= 32)
- || (!ctx->w && a->shamt >= 128)) {
+ if ((ctx->w && a->shamt >= 32) || (ctx->d && a->shamt >= 64)
+ || (!ctx->w && !ctx->d && a->shamt >= 128)) {
return false;
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 05e13bbc1d..1a1defb102 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -888,6 +888,39 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
NULL, gen_sraiw_tl, gen_sraiw_i128);
}
+static bool trans_sllid(DisasContext *ctx, arg_sllid *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, NULL, gen_slliwd_i128);
+}
+
+static void gen_srlid_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long shamt)
+{
+ tcg_gen_shri_tl(retl, srcl, shamt);
+}
+
+static bool trans_srlid(DisasContext *ctx, arg_srlid *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, NULL, gen_srlid_i128);
+}
+
+static void gen_sraid_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long shamt)
+{
+ tcg_gen_sari_tl(retl, srcl, shamt);
+}
+
+static bool trans_sraid(DisasContext *ctx, arg_sraid *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, NULL, gen_sraid_i128);
+}
+
static void gen_addw_i128(TCGv retl, TCGv reth,
TCGv src1l, TCGv src1h,
TCGv src2l, TCGv src2h)
@@ -960,6 +993,31 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
NULL, tcg_gen_sar_tl, gen_srawd_i128);
}
+/* Translation functions for 64-bit operations specific to RV128 */
+static bool trans_slld(DisasContext *ctx, arg_slld *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift(ctx, a, EXT_NONE,
+ tcg_gen_shl_tl, tcg_gen_shl_tl, gen_sllwd_i128);
+}
+
+static bool trans_srld(DisasContext *ctx, arg_srld *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift(ctx, a, EXT_ZERO,
+ tcg_gen_shr_tl, tcg_gen_shr_tl, gen_srlwd_i128);
+}
+
+static bool trans_srad(DisasContext *ctx, arg_srad *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift(ctx, a, EXT_SIGN,
+ tcg_gen_sar_tl, tcg_gen_sar_tl, gen_srawd_i128);
+}
+
static bool trans_fence(DisasContext *ctx, arg_fence *a)
{
/* FENCE is a full memory barrier. */
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 18/27] target/riscv: 128-bit double word integer shift instructions
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
All variations of shifts on 64-bit values are available in the
128-bit ISA, so we add them now.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn32.decode | 10 +++++
target/riscv/translate.c | 4 +-
target/riscv/insn_trans/trans_rvi.c.inc | 58 +++++++++++++++++++++++++
3 files changed, 70 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index eea540cea9..be8d6aa85f 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -22,6 +22,7 @@
%rs1 15:5
%rd 7:5
%sh5 20:5
+%sh6 20:6
%sh7 20:7
%csr 20:12
@@ -92,6 +93,9 @@
# Formats 64:
@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
+# Formats 128:
+@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
+
# *** Privileged Instructions ***
ecall 000000000000 00000 000 00000 1110011
ebreak 000000000001 00000 000 00000 1110011
@@ -168,8 +172,14 @@ ldu ............ ..... 111 ..... 0000011 @i
lq ............ ..... 010 ..... 0001111 @i
sq ............ ..... 100 ..... 0100011 @s
addid ............ ..... 000 ..... 1011011 @i
+sllid 000000 ...... ..... 001 ..... 1011011 @sh6
+srlid 000000 ...... ..... 101 ..... 1011011 @sh6
+sraid 010000 ...... ..... 101 ..... 1011011 @sh6
addd 0000000 ..... ..... 000 ..... 1111011 @r
subd 0100000 ..... ..... 000 ..... 1111011 @r
+slld 0000000 ..... ..... 001 ..... 1111011 @r
+srld 0000000 ..... ..... 101 ..... 1111011 @r
+srad 0100000 ..... ..... 101 ..... 1111011 @r
# *** RV32M Standard Extension ***
mul 0000001 ..... ..... 000 ..... 0110011 @r
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 120841de48..195dc3f461 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -624,8 +624,8 @@ static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
} else if (is_128bit(ctx)) {
- if ((ctx->w && a->shamt >= 32)
- || (!ctx->w && a->shamt >= 128)) {
+ if ((ctx->w && a->shamt >= 32) || (ctx->d && a->shamt >= 64)
+ || (!ctx->w && !ctx->d && a->shamt >= 128)) {
return false;
}
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 05e13bbc1d..1a1defb102 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -888,6 +888,39 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
NULL, gen_sraiw_tl, gen_sraiw_i128);
}
+static bool trans_sllid(DisasContext *ctx, arg_sllid *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, NULL, gen_slliwd_i128);
+}
+
+static void gen_srlid_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long shamt)
+{
+ tcg_gen_shri_tl(retl, srcl, shamt);
+}
+
+static bool trans_srlid(DisasContext *ctx, arg_srlid *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, NULL, gen_srlid_i128);
+}
+
+static void gen_sraid_i128(TCGv retl, TCGv reth,
+ TCGv srcl, TCGv srch, target_long shamt)
+{
+ tcg_gen_sari_tl(retl, srcl, shamt);
+}
+
+static bool trans_sraid(DisasContext *ctx, arg_sraid *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift_imm_fn(ctx, a, EXT_NONE, NULL, NULL, gen_sraid_i128);
+}
+
static void gen_addw_i128(TCGv retl, TCGv reth,
TCGv src1l, TCGv src1h,
TCGv src2l, TCGv src2h)
@@ -960,6 +993,31 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
NULL, tcg_gen_sar_tl, gen_srawd_i128);
}
+/* Translation functions for 64-bit operations specific to RV128 */
+static bool trans_slld(DisasContext *ctx, arg_slld *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift(ctx, a, EXT_NONE,
+ tcg_gen_shl_tl, tcg_gen_shl_tl, gen_sllwd_i128);
+}
+
+static bool trans_srld(DisasContext *ctx, arg_srld *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift(ctx, a, EXT_ZERO,
+ tcg_gen_shr_tl, tcg_gen_shr_tl, gen_srlwd_i128);
+}
+
+static bool trans_srad(DisasContext *ctx, arg_srad *a)
+{
+ REQUIRE_128BIT(ctx);
+ ctx->d = true;
+ return gen_shift(ctx, a, EXT_SIGN,
+ tcg_gen_sar_tl, tcg_gen_sar_tl, gen_srawd_i128);
+}
+
static bool trans_fence(DisasContext *ctx, arg_fence *a)
{
/* FENCE is a full memory barrier. */
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 19/27] target/riscv: support for 128-bit base multiplications insns
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
We deal here with the multiplication part of the M extension as, although a
bit complex, the code is generated inline, as opposed to division and
remainder that resort to helpers (to come soon).
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvm.c.inc | 183 ++++++++++++++++++++++--
1 file changed, 173 insertions(+), 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index 0c5f1ba548..d61c79450c 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -18,12 +18,106 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+static void gen_mulu2_i128(TCGv rll, TCGv rlh, TCGv rhl, TCGv rhh,
+ TCGv al, TCGv ah, TCGv bl, TCGv bh)
+{
+ TCGv tmpl = tcg_temp_new(),
+ tmph = tcg_temp_new(),
+ cnst_zero = tcg_constant_tl(0);
+
+ tcg_gen_mulu2_tl(rll, rlh, al, bl);
+
+ tcg_gen_mulu2_tl(tmpl, tmph, al, bh);
+ tcg_gen_add2_tl(rlh, rhl, rlh, cnst_zero, tmpl, tmph);
+ tcg_gen_mulu2_tl(tmpl, tmph, ah, bl);
+ tcg_gen_add2_tl(rlh, tmph, rlh, rhl, tmpl, tmph);
+ /* Overflow detection into rhh */
+ tcg_gen_setcond_tl(TCG_COND_LTU, rhh, tmph, rhl);
+
+ tcg_gen_mov_tl(rhl, tmph);
+
+ tcg_gen_mulu2_tl(tmpl, tmph, ah, bh);
+ tcg_gen_add2_tl(rhl, rhh, rhl, rhh, tmpl, tmph);
+
+ tcg_temp_free(tmpl);
+ tcg_temp_free(tmph);
+}
+
+static void gen_mul_i128(TCGv rll, TCGv rlh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ TCGv rhl = tcg_temp_new(),
+ rhh = tcg_temp_new();
+
+ gen_mulu2_i128(rll, rlh, rhl, rhh, rs1l, rs1h, rs2l, rs2h);
+
+ tcg_temp_free(rhl);
+ tcg_temp_free(rhh);
+}
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_NONE,
- tcg_gen_mul_tl, tcg_gen_mul_tl, NULL);
+ tcg_gen_mul_tl, tcg_gen_mul_tl, gen_mul_i128);
+}
+
+static void gen_mulh_i128(TCGv rhl, TCGv rhh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ TCGv rll = tcg_temp_new(),
+ rlh = tcg_temp_new(),
+ rlln = tcg_temp_new(),
+ rlhn = tcg_temp_new(),
+ rhln = tcg_temp_new(),
+ rhhn = tcg_temp_new(),
+ sgnres = tcg_temp_new(),
+ tmp = tcg_temp_new(),
+ cnst_one = tcg_constant_tl(1),
+ cnst_zero = tcg_constant_tl(0);
+
+ /* Extract sign of result (=> sgn(a) xor sgn(b)) */
+ tcg_gen_setcondi_tl(TCG_COND_LT, sgnres, rs1h, 0);
+ tcg_gen_setcondi_tl(TCG_COND_LT, tmp, rs2h, 0);
+ tcg_gen_xor_tl(sgnres, sgnres, tmp);
+
+ /* Take absolute value of operands */
+ tcg_gen_sari_tl(rhl, rs1h, 63);
+ tcg_gen_add2_tl(rlln, rlhn, rs1l, rs1h, rhl, rhl);
+ tcg_gen_xor_tl(rlln, rlln, rhl);
+ tcg_gen_xor_tl(rlhn, rlhn, rhl);
+
+ tcg_gen_sari_tl(rhl, rs2h, 63);
+ tcg_gen_add2_tl(rhln, rhhn, rs2l, rs2h, rhl, rhl);
+ tcg_gen_xor_tl(rhln, rhln, rhl);
+ tcg_gen_xor_tl(rhhn, rhhn, rhl);
+
+ /* Unsigned multiplication */
+ gen_mulu2_i128(rll, rlh, rhl, rhh, rlln, rlhn, rhln, rhhn);
+
+ /* Negation of result (two's complement : ~res + 1) */
+ tcg_gen_not_tl(rlln, rll);
+ tcg_gen_not_tl(rlhn, rlh);
+ tcg_gen_not_tl(rhln, rhl);
+ tcg_gen_not_tl(rhhn, rhh);
+
+ tcg_gen_add2_tl(rlln, tmp, rlln, cnst_zero, cnst_one, cnst_zero);
+ tcg_gen_add2_tl(rlhn, tmp, rlhn, cnst_zero, tmp, cnst_zero);
+ tcg_gen_add2_tl(rhln, tmp, rhln, cnst_zero, tmp, cnst_zero);
+ tcg_gen_add2_tl(rhhn, tmp, rhhn, cnst_zero, tmp, cnst_zero);
+
+ /* Move conditionally result or -result depending on result sign */
+ tcg_gen_movcond_tl(TCG_COND_NE, rhl, sgnres, cnst_zero, rhln, rhl);
+ tcg_gen_movcond_tl(TCG_COND_NE, rhh, sgnres, cnst_zero, rhhn, rhh);
+
+ tcg_temp_free(rll);
+ tcg_temp_free(rlh);
+ tcg_temp_free(rlln);
+ tcg_temp_free(rlhn);
+ tcg_temp_free(rhln);
+ tcg_temp_free(rhhn);
+ tcg_temp_free(sgnres);
+ tcg_temp_free(tmp);
}
static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
@@ -38,7 +132,58 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_NONE,
- gen_mulh, gen_mulh, NULL);
+ gen_mulh, gen_mulh, gen_mulh_i128);
+}
+
+static void gen_mulhsu_i128(TCGv rhl, TCGv rhh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ TCGv rll = tcg_temp_new(),
+ rlh = tcg_temp_new(),
+ rlln = tcg_temp_new(),
+ rlhn = tcg_temp_new(),
+ rhln = tcg_temp_new(),
+ rhhn = tcg_temp_new(),
+ sgnres = tcg_temp_new(),
+ tmp = tcg_temp_new(),
+ cnst_one = tcg_constant_tl(1),
+ cnst_zero = tcg_constant_tl(0);
+
+ /* Extract sign of result (=> sgn(a)) */
+ tcg_gen_setcondi_tl(TCG_COND_LT, sgnres, rs1h, 0);
+
+ /* Take absolute value of rs1 */
+ tcg_gen_sari_tl(rhl, rs1h, 63);
+ tcg_gen_add2_tl(rlln, rlhn, rs1l, rs1h, rhl, rhl);
+ tcg_gen_xor_tl(rlln, rlln, rhl);
+ tcg_gen_xor_tl(rlhn, rlhn, rhl);
+
+ /* Unsigned multiplication */
+ gen_mulu2_i128(rll, rlh, rhl, rhh, rlln, rlhn, rs2l, rs2h);
+
+ /* Negation of result (two's complement : ~res + 1) */
+ tcg_gen_not_tl(rlln, rll);
+ tcg_gen_not_tl(rlhn, rlh);
+ tcg_gen_not_tl(rhln, rhl);
+ tcg_gen_not_tl(rhhn, rhh);
+
+ tcg_gen_add2_tl(rlln, tmp, rlln, cnst_zero, cnst_one, cnst_zero);
+ tcg_gen_add2_tl(rlhn, tmp, rlhn, cnst_zero, tmp, cnst_zero);
+ tcg_gen_add2_tl(rhln, tmp, rhln, cnst_zero, tmp, cnst_zero);
+ tcg_gen_add2_tl(rhhn, tmp, rhhn, cnst_zero, tmp, cnst_zero);
+
+ /* Move conditionally result or -result depending on result sign */
+ tcg_gen_movcond_tl(TCG_COND_NE, rhl, sgnres, cnst_zero, rhln, rhl);
+ tcg_gen_movcond_tl(TCG_COND_NE, rhh, sgnres, cnst_zero, rhhn, rhh);
+
+ tcg_temp_free(rll);
+ tcg_temp_free(rlh);
+ tcg_temp_free(rlln);
+ tcg_temp_free(rlhn);
+ tcg_temp_free(rhln);
+ tcg_temp_free(rhhn);
+ tcg_temp_free(sgnres);
+ tcg_temp_free(tmp);
}
static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
@@ -60,7 +205,19 @@ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_NONE,
- gen_mulhsu, gen_mulhsu, NULL);
+ gen_mulhsu, gen_mulhsu, gen_mulhsu_i128);
+}
+
+static void gen_mulhu_i128(TCGv rhl, TCGv rhh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ TCGv rll = tcg_temp_new(),
+ rlh = tcg_temp_new();
+
+ gen_mulu2_i128(rll, rlh, rhl, rhh, rs1l, rs1h, rs2l, rs2h);
+
+ tcg_temp_free(rll);
+ tcg_temp_free(rlh);
}
static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
@@ -75,7 +232,7 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_NONE,
- gen_mulhu, gen_mulhu, NULL);
+ gen_mulhu, gen_mulhu, gen_mulhu_i128);
}
static void gen_div(TCGv ret, TCGv source1, TCGv source2)
@@ -218,18 +375,24 @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
gen_remu, gen_remu, NULL);
}
+static void gen_mulw_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ tcg_gen_mul_tl(rdl, rs1l, rs2l);
+}
+
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_NONE,
- tcg_gen_mul_tl, tcg_gen_mul_tl, NULL);
+ tcg_gen_mul_tl, tcg_gen_mul_tl, gen_mulw_i128);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_SIGN,
@@ -238,7 +401,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_ZERO,
@@ -247,7 +410,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
static bool trans_remw(DisasContext *ctx, arg_remw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_SIGN,
@@ -256,7 +419,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_ZERO,
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 19/27] target/riscv: support for 128-bit base multiplications insns
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
We deal here with the multiplication part of the M extension as, although a
bit complex, the code is generated inline, as opposed to division and
remainder that resort to helpers (to come soon).
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvm.c.inc | 183 ++++++++++++++++++++++--
1 file changed, 173 insertions(+), 10 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index 0c5f1ba548..d61c79450c 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -18,12 +18,106 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+static void gen_mulu2_i128(TCGv rll, TCGv rlh, TCGv rhl, TCGv rhh,
+ TCGv al, TCGv ah, TCGv bl, TCGv bh)
+{
+ TCGv tmpl = tcg_temp_new(),
+ tmph = tcg_temp_new(),
+ cnst_zero = tcg_constant_tl(0);
+
+ tcg_gen_mulu2_tl(rll, rlh, al, bl);
+
+ tcg_gen_mulu2_tl(tmpl, tmph, al, bh);
+ tcg_gen_add2_tl(rlh, rhl, rlh, cnst_zero, tmpl, tmph);
+ tcg_gen_mulu2_tl(tmpl, tmph, ah, bl);
+ tcg_gen_add2_tl(rlh, tmph, rlh, rhl, tmpl, tmph);
+ /* Overflow detection into rhh */
+ tcg_gen_setcond_tl(TCG_COND_LTU, rhh, tmph, rhl);
+
+ tcg_gen_mov_tl(rhl, tmph);
+
+ tcg_gen_mulu2_tl(tmpl, tmph, ah, bh);
+ tcg_gen_add2_tl(rhl, rhh, rhl, rhh, tmpl, tmph);
+
+ tcg_temp_free(tmpl);
+ tcg_temp_free(tmph);
+}
+
+static void gen_mul_i128(TCGv rll, TCGv rlh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ TCGv rhl = tcg_temp_new(),
+ rhh = tcg_temp_new();
+
+ gen_mulu2_i128(rll, rlh, rhl, rhh, rs1l, rs1h, rs2l, rs2h);
+
+ tcg_temp_free(rhl);
+ tcg_temp_free(rhh);
+}
static bool trans_mul(DisasContext *ctx, arg_mul *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_NONE,
- tcg_gen_mul_tl, tcg_gen_mul_tl, NULL);
+ tcg_gen_mul_tl, tcg_gen_mul_tl, gen_mul_i128);
+}
+
+static void gen_mulh_i128(TCGv rhl, TCGv rhh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ TCGv rll = tcg_temp_new(),
+ rlh = tcg_temp_new(),
+ rlln = tcg_temp_new(),
+ rlhn = tcg_temp_new(),
+ rhln = tcg_temp_new(),
+ rhhn = tcg_temp_new(),
+ sgnres = tcg_temp_new(),
+ tmp = tcg_temp_new(),
+ cnst_one = tcg_constant_tl(1),
+ cnst_zero = tcg_constant_tl(0);
+
+ /* Extract sign of result (=> sgn(a) xor sgn(b)) */
+ tcg_gen_setcondi_tl(TCG_COND_LT, sgnres, rs1h, 0);
+ tcg_gen_setcondi_tl(TCG_COND_LT, tmp, rs2h, 0);
+ tcg_gen_xor_tl(sgnres, sgnres, tmp);
+
+ /* Take absolute value of operands */
+ tcg_gen_sari_tl(rhl, rs1h, 63);
+ tcg_gen_add2_tl(rlln, rlhn, rs1l, rs1h, rhl, rhl);
+ tcg_gen_xor_tl(rlln, rlln, rhl);
+ tcg_gen_xor_tl(rlhn, rlhn, rhl);
+
+ tcg_gen_sari_tl(rhl, rs2h, 63);
+ tcg_gen_add2_tl(rhln, rhhn, rs2l, rs2h, rhl, rhl);
+ tcg_gen_xor_tl(rhln, rhln, rhl);
+ tcg_gen_xor_tl(rhhn, rhhn, rhl);
+
+ /* Unsigned multiplication */
+ gen_mulu2_i128(rll, rlh, rhl, rhh, rlln, rlhn, rhln, rhhn);
+
+ /* Negation of result (two's complement : ~res + 1) */
+ tcg_gen_not_tl(rlln, rll);
+ tcg_gen_not_tl(rlhn, rlh);
+ tcg_gen_not_tl(rhln, rhl);
+ tcg_gen_not_tl(rhhn, rhh);
+
+ tcg_gen_add2_tl(rlln, tmp, rlln, cnst_zero, cnst_one, cnst_zero);
+ tcg_gen_add2_tl(rlhn, tmp, rlhn, cnst_zero, tmp, cnst_zero);
+ tcg_gen_add2_tl(rhln, tmp, rhln, cnst_zero, tmp, cnst_zero);
+ tcg_gen_add2_tl(rhhn, tmp, rhhn, cnst_zero, tmp, cnst_zero);
+
+ /* Move conditionally result or -result depending on result sign */
+ tcg_gen_movcond_tl(TCG_COND_NE, rhl, sgnres, cnst_zero, rhln, rhl);
+ tcg_gen_movcond_tl(TCG_COND_NE, rhh, sgnres, cnst_zero, rhhn, rhh);
+
+ tcg_temp_free(rll);
+ tcg_temp_free(rlh);
+ tcg_temp_free(rlln);
+ tcg_temp_free(rlhn);
+ tcg_temp_free(rhln);
+ tcg_temp_free(rhhn);
+ tcg_temp_free(sgnres);
+ tcg_temp_free(tmp);
}
static void gen_mulh(TCGv ret, TCGv s1, TCGv s2)
@@ -38,7 +132,58 @@ static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_NONE,
- gen_mulh, gen_mulh, NULL);
+ gen_mulh, gen_mulh, gen_mulh_i128);
+}
+
+static void gen_mulhsu_i128(TCGv rhl, TCGv rhh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ TCGv rll = tcg_temp_new(),
+ rlh = tcg_temp_new(),
+ rlln = tcg_temp_new(),
+ rlhn = tcg_temp_new(),
+ rhln = tcg_temp_new(),
+ rhhn = tcg_temp_new(),
+ sgnres = tcg_temp_new(),
+ tmp = tcg_temp_new(),
+ cnst_one = tcg_constant_tl(1),
+ cnst_zero = tcg_constant_tl(0);
+
+ /* Extract sign of result (=> sgn(a)) */
+ tcg_gen_setcondi_tl(TCG_COND_LT, sgnres, rs1h, 0);
+
+ /* Take absolute value of rs1 */
+ tcg_gen_sari_tl(rhl, rs1h, 63);
+ tcg_gen_add2_tl(rlln, rlhn, rs1l, rs1h, rhl, rhl);
+ tcg_gen_xor_tl(rlln, rlln, rhl);
+ tcg_gen_xor_tl(rlhn, rlhn, rhl);
+
+ /* Unsigned multiplication */
+ gen_mulu2_i128(rll, rlh, rhl, rhh, rlln, rlhn, rs2l, rs2h);
+
+ /* Negation of result (two's complement : ~res + 1) */
+ tcg_gen_not_tl(rlln, rll);
+ tcg_gen_not_tl(rlhn, rlh);
+ tcg_gen_not_tl(rhln, rhl);
+ tcg_gen_not_tl(rhhn, rhh);
+
+ tcg_gen_add2_tl(rlln, tmp, rlln, cnst_zero, cnst_one, cnst_zero);
+ tcg_gen_add2_tl(rlhn, tmp, rlhn, cnst_zero, tmp, cnst_zero);
+ tcg_gen_add2_tl(rhln, tmp, rhln, cnst_zero, tmp, cnst_zero);
+ tcg_gen_add2_tl(rhhn, tmp, rhhn, cnst_zero, tmp, cnst_zero);
+
+ /* Move conditionally result or -result depending on result sign */
+ tcg_gen_movcond_tl(TCG_COND_NE, rhl, sgnres, cnst_zero, rhln, rhl);
+ tcg_gen_movcond_tl(TCG_COND_NE, rhh, sgnres, cnst_zero, rhhn, rhh);
+
+ tcg_temp_free(rll);
+ tcg_temp_free(rlh);
+ tcg_temp_free(rlln);
+ tcg_temp_free(rlhn);
+ tcg_temp_free(rhln);
+ tcg_temp_free(rhhn);
+ tcg_temp_free(sgnres);
+ tcg_temp_free(tmp);
}
static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2)
@@ -60,7 +205,19 @@ static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_NONE,
- gen_mulhsu, gen_mulhsu, NULL);
+ gen_mulhsu, gen_mulhsu, gen_mulhsu_i128);
+}
+
+static void gen_mulhu_i128(TCGv rhl, TCGv rhh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ TCGv rll = tcg_temp_new(),
+ rlh = tcg_temp_new();
+
+ gen_mulu2_i128(rll, rlh, rhl, rhh, rs1l, rs1h, rs2l, rs2h);
+
+ tcg_temp_free(rll);
+ tcg_temp_free(rlh);
}
static void gen_mulhu(TCGv ret, TCGv s1, TCGv s2)
@@ -75,7 +232,7 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_NONE,
- gen_mulhu, gen_mulhu, NULL);
+ gen_mulhu, gen_mulhu, gen_mulhu_i128);
}
static void gen_div(TCGv ret, TCGv source1, TCGv source2)
@@ -218,18 +375,24 @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
gen_remu, gen_remu, NULL);
}
+static void gen_mulw_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ tcg_gen_mul_tl(rdl, rs1l, rs2l);
+}
+
static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_NONE,
- tcg_gen_mul_tl, tcg_gen_mul_tl, NULL);
+ tcg_gen_mul_tl, tcg_gen_mul_tl, gen_mulw_i128);
}
static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_SIGN,
@@ -238,7 +401,7 @@ static bool trans_divw(DisasContext *ctx, arg_divw *a)
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_ZERO,
@@ -247,7 +410,7 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
static bool trans_remw(DisasContext *ctx, arg_remw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_SIGN,
@@ -256,7 +419,7 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
{
- REQUIRE_64BIT(ctx);
+ REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_ZERO,
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 20/27] target/riscv: addition of the 'd' insns for 128-bit mult/div/rem
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
All mult/div/rem instructions that work on double integers (suffixed
'd') can be tcg-generated in a few micro-ops, they are added here.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvm.c.inc | 112 +++++++++++++++++++++++-
2 files changed, 115 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index be8d6aa85f..380604acee 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -198,6 +198,13 @@ divuw 0000001 ..... ..... 101 ..... 0111011 @r
remw 0000001 ..... ..... 110 ..... 0111011 @r
remuw 0000001 ..... ..... 111 ..... 0111011 @r
+# *** RV128M Standard Extension (in addition to RV64M) ***
+muld 0000001 ..... ..... 000 ..... 1111011 @r
+divd 0000001 ..... ..... 100 ..... 1111011 @r
+divud 0000001 ..... ..... 101 ..... 1111011 @r
+remd 0000001 ..... ..... 110 ..... 1111011 @r
+remud 0000001 ..... ..... 111 ..... 1111011 @r
+
# *** RV32A Standard Extension ***
lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index d61c79450c..9ed9ba0f0f 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -390,13 +390,25 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
tcg_gen_mul_tl, tcg_gen_mul_tl, gen_mulw_i128);
}
+static void gen_divw_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_div(rdl, rs1l, rs2l);
+}
+
static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_SIGN,
- gen_div, gen_div, NULL);
+ gen_div, gen_div, gen_divw_i128);
+}
+
+static void gen_divuw_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_divu(rdl, rs1l, rs2l);
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
@@ -405,7 +417,13 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_ZERO,
- gen_divu, gen_divu, NULL);
+ gen_divu, gen_divu, gen_divuw_i128);
+}
+
+static void gen_remw_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_rem(rdl, rs1l, rs2l);
}
static bool trans_remw(DisasContext *ctx, arg_remw *a)
@@ -414,7 +432,13 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_SIGN,
- gen_rem, gen_rem, NULL);
+ gen_rem, gen_rem, gen_remw_i128);
+}
+
+static void gen_remuw_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_remu(rdl, rs1l, rs2l);
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
@@ -423,5 +447,85 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_ZERO,
- gen_remu, gen_remu, NULL);
+ gen_remu, gen_remu, gen_remuw_i128);
+}
+
+static void gen_muld_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ tcg_gen_mul_tl(rdl, rs1l, rs2l);
+}
+
+static bool trans_muld(DisasContext *ctx, arg_muld *a)
+{
+ REQUIRE_128BIT(ctx);
+ REQUIRE_EXT(ctx, RVM);
+ ctx->d = true;
+
+ return gen_arith(ctx, a, EXT_SIGN,
+ tcg_gen_mul_tl, tcg_gen_mul_tl, gen_muld_i128);
+}
+
+static void gen_divd_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_div(rdl, rs1l, rs2l);
+}
+
+static bool trans_divd(DisasContext *ctx, arg_divd *a)
+{
+ REQUIRE_128BIT(ctx);
+ REQUIRE_EXT(ctx, RVM);
+ ctx->d = true;
+
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_div, gen_div, gen_divd_i128);
+}
+
+static void gen_divud_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_divu(rdl, rs1l, rs2l);
+}
+
+static bool trans_divud(DisasContext *ctx, arg_divud *a)
+{
+ REQUIRE_128BIT(ctx);
+ REQUIRE_EXT(ctx, RVM);
+ ctx->d = true;
+
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_divu, gen_divu, gen_divud_i128);
+}
+
+static void gen_remd_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_rem(rdl, rs1l, rs2l);
+}
+
+static bool trans_remd(DisasContext *ctx, arg_remd *a)
+{
+ REQUIRE_128BIT(ctx);
+ REQUIRE_EXT(ctx, RVM);
+ ctx->d = true;
+
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_rem, gen_rem, gen_remd_i128);
+}
+
+static void gen_remud_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_remu(rdl, rs1l, rs2l);
+}
+
+static bool trans_remud(DisasContext *ctx, arg_remud *a)
+{
+ REQUIRE_128BIT(ctx);
+ REQUIRE_EXT(ctx, RVM);
+ ctx->d = true;
+
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_remu, gen_remu, gen_remud_i128);
}
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 20/27] target/riscv: addition of the 'd' insns for 128-bit mult/div/rem
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
All mult/div/rem instructions that work on double integers (suffixed
'd') can be tcg-generated in a few micro-ops, they are added here.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn32.decode | 7 ++
target/riscv/insn_trans/trans_rvm.c.inc | 112 +++++++++++++++++++++++-
2 files changed, 115 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index be8d6aa85f..380604acee 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -198,6 +198,13 @@ divuw 0000001 ..... ..... 101 ..... 0111011 @r
remw 0000001 ..... ..... 110 ..... 0111011 @r
remuw 0000001 ..... ..... 111 ..... 0111011 @r
+# *** RV128M Standard Extension (in addition to RV64M) ***
+muld 0000001 ..... ..... 000 ..... 1111011 @r
+divd 0000001 ..... ..... 100 ..... 1111011 @r
+divud 0000001 ..... ..... 101 ..... 1111011 @r
+remd 0000001 ..... ..... 110 ..... 1111011 @r
+remud 0000001 ..... ..... 111 ..... 1111011 @r
+
# *** RV32A Standard Extension ***
lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index d61c79450c..9ed9ba0f0f 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -390,13 +390,25 @@ static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
tcg_gen_mul_tl, tcg_gen_mul_tl, gen_mulw_i128);
}
+static void gen_divw_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_div(rdl, rs1l, rs2l);
+}
+
static bool trans_divw(DisasContext *ctx, arg_divw *a)
{
REQUIRE_64_OR_128BIT(ctx);
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_SIGN,
- gen_div, gen_div, NULL);
+ gen_div, gen_div, gen_divw_i128);
+}
+
+static void gen_divuw_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_divu(rdl, rs1l, rs2l);
}
static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
@@ -405,7 +417,13 @@ static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_ZERO,
- gen_divu, gen_divu, NULL);
+ gen_divu, gen_divu, gen_divuw_i128);
+}
+
+static void gen_remw_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_rem(rdl, rs1l, rs2l);
}
static bool trans_remw(DisasContext *ctx, arg_remw *a)
@@ -414,7 +432,13 @@ static bool trans_remw(DisasContext *ctx, arg_remw *a)
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_SIGN,
- gen_rem, gen_rem, NULL);
+ gen_rem, gen_rem, gen_remw_i128);
+}
+
+static void gen_remuw_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_remu(rdl, rs1l, rs2l);
}
static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
@@ -423,5 +447,85 @@ static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
REQUIRE_EXT(ctx, RVM);
ctx->w = true;
return gen_arith(ctx, a, EXT_ZERO,
- gen_remu, gen_remu, NULL);
+ gen_remu, gen_remu, gen_remuw_i128);
+}
+
+static void gen_muld_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ tcg_gen_mul_tl(rdl, rs1l, rs2l);
+}
+
+static bool trans_muld(DisasContext *ctx, arg_muld *a)
+{
+ REQUIRE_128BIT(ctx);
+ REQUIRE_EXT(ctx, RVM);
+ ctx->d = true;
+
+ return gen_arith(ctx, a, EXT_SIGN,
+ tcg_gen_mul_tl, tcg_gen_mul_tl, gen_muld_i128);
+}
+
+static void gen_divd_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_div(rdl, rs1l, rs2l);
+}
+
+static bool trans_divd(DisasContext *ctx, arg_divd *a)
+{
+ REQUIRE_128BIT(ctx);
+ REQUIRE_EXT(ctx, RVM);
+ ctx->d = true;
+
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_div, gen_div, gen_divd_i128);
+}
+
+static void gen_divud_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_divu(rdl, rs1l, rs2l);
+}
+
+static bool trans_divud(DisasContext *ctx, arg_divud *a)
+{
+ REQUIRE_128BIT(ctx);
+ REQUIRE_EXT(ctx, RVM);
+ ctx->d = true;
+
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_divu, gen_divu, gen_divud_i128);
+}
+
+static void gen_remd_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_rem(rdl, rs1l, rs2l);
+}
+
+static bool trans_remd(DisasContext *ctx, arg_remd *a)
+{
+ REQUIRE_128BIT(ctx);
+ REQUIRE_EXT(ctx, RVM);
+ ctx->d = true;
+
+ return gen_arith(ctx, a, EXT_SIGN,
+ gen_rem, gen_rem, gen_remd_i128);
+}
+
+static void gen_remud_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_remu(rdl, rs1l, rs2l);
+}
+
+static bool trans_remud(DisasContext *ctx, arg_remud *a)
+{
+ REQUIRE_128BIT(ctx);
+ REQUIRE_EXT(ctx, RVM);
+ ctx->d = true;
+
+ return gen_arith(ctx, a, EXT_ZERO,
+ gen_remu, gen_remu, gen_remud_i128);
}
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 21/27] target/riscv: div and rem insns on 128-bit
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Given the complexity of the implementation of these instructions, we call
helpers to produce their behavior. From an implementation standpoint, we
ended up by adding two more tcg globals to return the 128-bit result in a
wrapper that itself is called by gen_arith.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 1 +
target/riscv/helper.h | 6 ++
target/riscv/m128_helper.c | 109 ++++++++++++++++++++++++
target/riscv/translate.c | 7 +-
target/riscv/insn_trans/trans_rvm.c.inc | 44 +++++++++-
target/riscv/meson.build | 1 +
6 files changed, 163 insertions(+), 5 deletions(-)
create mode 100644 target/riscv/m128_helper.c
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1de9a1286b..81cbd77d09 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -121,6 +121,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
+ target_ulong hlpr[2]; /* scratch registers for 128-bit div/rem helpers */
uint64_t fpr[32]; /* assume both F and D extensions */
/* vector coprocessor state. */
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 460eee9988..01d885d566 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1149,3 +1149,9 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+/* 128-bit integer multiplication and division */
+DEF_HELPER_5(divu_i128, void, env, i64, i64, i64, i64)
+DEF_HELPER_5(divs_i128, void, env, i64, i64, i64, i64)
+DEF_HELPER_5(remu_i128, void, env, i64, i64, i64, i64)
+DEF_HELPER_5(rems_i128, void, env, i64, i64, i64, i64)
diff --git a/target/riscv/m128_helper.c b/target/riscv/m128_helper.c
new file mode 100644
index 0000000000..694ca5da9b
--- /dev/null
+++ b/target/riscv/m128_helper.c
@@ -0,0 +1,109 @@
+/*
+ * RISC-V Emulation Helpers for QEMU.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2017-2018 SiFive, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/main-loop.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+
+void HELPER(divu_i128)(CPURISCVState *env,
+ uint64_t ul, uint64_t uh,
+ uint64_t vl, uint64_t vh)
+{
+ uint64_t ql, qh;
+ Int128 q;
+
+ if (vl == 0 && vh == 0) { /* Handle special behavior on div by zero */
+ ql = ~0x0;
+ qh = ~0x0;
+ } else {
+ q = int128_divu(int128_make128(ul, uh), int128_make128(vl, vh));
+ ql = int128_getlo(q);
+ qh = int128_gethi(q);
+ }
+
+ env->hlpr[0] = ql;
+ env->hlpr[1] = qh;
+}
+
+void HELPER(remu_i128)(CPURISCVState *env,
+ uint64_t ul, uint64_t uh,
+ uint64_t vl, uint64_t vh)
+{
+ uint64_t rl, rh;
+ Int128 r;
+
+ if (vl == 0 && vh == 0) {
+ rl = ul;
+ rh = uh;
+ } else {
+ r = int128_remu(int128_make128(ul, uh), int128_make128(vl, vh));
+ rl = int128_getlo(r);
+ rh = int128_gethi(r);
+ }
+
+ env->hlpr[0] = rl;
+ env->hlpr[1] = rh;
+}
+
+void HELPER(divs_i128)(CPURISCVState *env,
+ uint64_t ul, uint64_t uh,
+ uint64_t vl, uint64_t vh)
+{
+ uint64_t qh, ql;
+ Int128 q;
+
+ if (vl == 0 && vh == 0) { /* Div by zero check */
+ ql = ~0x0;
+ qh = ~0x0;
+ } else if (uh == 0x8000000000000000 && ul == 0 &&
+ vh == ~0x0 && vl == ~0x0) {
+ /* Signed div overflow check (-2**127 / -1) */
+ ql = ul;
+ qh = uh;
+ } else {
+ q = int128_divs(int128_make128(ul, uh), int128_make128(vl, vh));
+ ql = int128_getlo(q);
+ qh = int128_gethi(q);
+ }
+
+ env->hlpr[0] = ql;
+ env->hlpr[1] = qh;
+}
+
+void HELPER(rems_i128)(CPURISCVState *env,
+ uint64_t ul, uint64_t uh,
+ uint64_t vl, uint64_t vh)
+{
+ uint64_t rh, rl;
+ Int128 r;
+
+ if (vl == 0 && vh == 0) {
+ rl = ul;
+ rh = uh;
+ } else {
+ r = int128_rems(int128_make128(ul, uh), int128_make128(vl, vh));
+ rl = int128_getlo(r);
+ rh = int128_gethi(r);
+ }
+
+ env->hlpr[0] = rl;
+ env->hlpr[1] = rh;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 195dc3f461..cb697bd0e4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -32,7 +32,7 @@
#include "instmap.h"
/* global register indices */
-static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl;
+static TCGv cpu_gpr[32], cpu_gprh[32], cpu_hlpr[2], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
@@ -917,6 +917,11 @@ void riscv_translate_init(void)
offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]);
}
+ cpu_hlpr[0] = tcg_global_mem_new(cpu_env,
+ offsetof(CPURISCVState, hlpr[0]), "helper_reg0");
+ cpu_hlpr[1] = tcg_global_mem_new(cpu_env,
+ offsetof(CPURISCVState, hlpr[1]), "helper_reg1");
+
for (i = 0; i < 32; i++) {
cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index 9ed9ba0f0f..f46e746bed 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -235,6 +235,15 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
gen_mulhu, gen_mulhu, gen_mulhu_i128);
}
+static void gen_div_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_helper_divs_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h,
+ (TCGv_i64)rs2l, (TCGv_i64)rs2h);
+ tcg_gen_mov_tl(rdl, cpu_hlpr[0]);
+ tcg_gen_mov_tl(rdh, cpu_hlpr[1]);
+}
+
static void gen_div(TCGv ret, TCGv source1, TCGv source2)
{
TCGv temp1, temp2, zero, one, mone, min;
@@ -272,7 +281,16 @@ static bool trans_div(DisasContext *ctx, arg_div *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_SIGN,
- gen_div, gen_div, NULL);
+ gen_div, gen_div, gen_div_i128);
+}
+
+static void gen_divu_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_helper_divu_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h,
+ (TCGv_i64)rs2l, (TCGv_i64)rs2h);
+ tcg_gen_mov_tl(rdl, cpu_hlpr[0]);
+ tcg_gen_mov_tl(rdh, cpu_hlpr[1]);
}
static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
@@ -301,7 +319,16 @@ static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_ZERO,
- gen_divu, gen_divu, NULL);
+ gen_divu, gen_divu, gen_divu_i128);
+}
+
+static void gen_rem_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_helper_rems_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h,
+ (TCGv_i64)rs2l, (TCGv_i64)rs2h);
+ tcg_gen_mov_tl(rdl, cpu_hlpr[0]);
+ tcg_gen_mov_tl(rdh, cpu_hlpr[1]);
}
static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
@@ -343,7 +370,16 @@ static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_SIGN,
- gen_rem, gen_rem, NULL);
+ gen_rem, gen_rem, gen_rem_i128);
+}
+
+static void gen_remu_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_helper_remu_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h,
+ (TCGv_i64)rs2l, (TCGv_i64)rs2h);
+ tcg_gen_mov_tl(rdl, cpu_hlpr[0]);
+ tcg_gen_mov_tl(rdh, cpu_hlpr[1]);
}
static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
@@ -372,7 +408,7 @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_ZERO,
- gen_remu, gen_remu, NULL);
+ gen_remu, gen_remu, gen_remu_i128);
}
static void gen_mulw_i128(TCGv rdl, TCGv rdh,
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index d5e0bc93ea..a32158da93 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -18,6 +18,7 @@ riscv_ss.add(files(
'vector_helper.c',
'bitmanip_helper.c',
'translate.c',
+ 'm128_helper.c'
))
riscv_softmmu_ss = ss.source_set()
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 21/27] target/riscv: div and rem insns on 128-bit
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Given the complexity of the implementation of these instructions, we call
helpers to produce their behavior. From an implementation standpoint, we
ended up by adding two more tcg globals to return the 128-bit result in a
wrapper that itself is called by gen_arith.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 1 +
target/riscv/helper.h | 6 ++
target/riscv/m128_helper.c | 109 ++++++++++++++++++++++++
target/riscv/translate.c | 7 +-
target/riscv/insn_trans/trans_rvm.c.inc | 44 +++++++++-
target/riscv/meson.build | 1 +
6 files changed, 163 insertions(+), 5 deletions(-)
create mode 100644 target/riscv/m128_helper.c
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 1de9a1286b..81cbd77d09 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -121,6 +121,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
target_ulong gpr[32];
target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
+ target_ulong hlpr[2]; /* scratch registers for 128-bit div/rem helpers */
uint64_t fpr[32]; /* assume both F and D extensions */
/* vector coprocessor state. */
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 460eee9988..01d885d566 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1149,3 +1149,9 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+/* 128-bit integer multiplication and division */
+DEF_HELPER_5(divu_i128, void, env, i64, i64, i64, i64)
+DEF_HELPER_5(divs_i128, void, env, i64, i64, i64, i64)
+DEF_HELPER_5(remu_i128, void, env, i64, i64, i64, i64)
+DEF_HELPER_5(rems_i128, void, env, i64, i64, i64, i64)
diff --git a/target/riscv/m128_helper.c b/target/riscv/m128_helper.c
new file mode 100644
index 0000000000..694ca5da9b
--- /dev/null
+++ b/target/riscv/m128_helper.c
@@ -0,0 +1,109 @@
+/*
+ * RISC-V Emulation Helpers for QEMU.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
+ * Copyright (c) 2017-2018 SiFive, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/main-loop.h"
+#include "exec/exec-all.h"
+#include "exec/helper-proto.h"
+
+void HELPER(divu_i128)(CPURISCVState *env,
+ uint64_t ul, uint64_t uh,
+ uint64_t vl, uint64_t vh)
+{
+ uint64_t ql, qh;
+ Int128 q;
+
+ if (vl == 0 && vh == 0) { /* Handle special behavior on div by zero */
+ ql = ~0x0;
+ qh = ~0x0;
+ } else {
+ q = int128_divu(int128_make128(ul, uh), int128_make128(vl, vh));
+ ql = int128_getlo(q);
+ qh = int128_gethi(q);
+ }
+
+ env->hlpr[0] = ql;
+ env->hlpr[1] = qh;
+}
+
+void HELPER(remu_i128)(CPURISCVState *env,
+ uint64_t ul, uint64_t uh,
+ uint64_t vl, uint64_t vh)
+{
+ uint64_t rl, rh;
+ Int128 r;
+
+ if (vl == 0 && vh == 0) {
+ rl = ul;
+ rh = uh;
+ } else {
+ r = int128_remu(int128_make128(ul, uh), int128_make128(vl, vh));
+ rl = int128_getlo(r);
+ rh = int128_gethi(r);
+ }
+
+ env->hlpr[0] = rl;
+ env->hlpr[1] = rh;
+}
+
+void HELPER(divs_i128)(CPURISCVState *env,
+ uint64_t ul, uint64_t uh,
+ uint64_t vl, uint64_t vh)
+{
+ uint64_t qh, ql;
+ Int128 q;
+
+ if (vl == 0 && vh == 0) { /* Div by zero check */
+ ql = ~0x0;
+ qh = ~0x0;
+ } else if (uh == 0x8000000000000000 && ul == 0 &&
+ vh == ~0x0 && vl == ~0x0) {
+ /* Signed div overflow check (-2**127 / -1) */
+ ql = ul;
+ qh = uh;
+ } else {
+ q = int128_divs(int128_make128(ul, uh), int128_make128(vl, vh));
+ ql = int128_getlo(q);
+ qh = int128_gethi(q);
+ }
+
+ env->hlpr[0] = ql;
+ env->hlpr[1] = qh;
+}
+
+void HELPER(rems_i128)(CPURISCVState *env,
+ uint64_t ul, uint64_t uh,
+ uint64_t vl, uint64_t vh)
+{
+ uint64_t rh, rl;
+ Int128 r;
+
+ if (vl == 0 && vh == 0) {
+ rl = ul;
+ rh = uh;
+ } else {
+ r = int128_rems(int128_make128(ul, uh), int128_make128(vl, vh));
+ rl = int128_getlo(r);
+ rh = int128_gethi(r);
+ }
+
+ env->hlpr[0] = rl;
+ env->hlpr[1] = rh;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 195dc3f461..cb697bd0e4 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -32,7 +32,7 @@
#include "instmap.h"
/* global register indices */
-static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl;
+static TCGv cpu_gpr[32], cpu_gprh[32], cpu_hlpr[2], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
@@ -917,6 +917,11 @@ void riscv_translate_init(void)
offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]);
}
+ cpu_hlpr[0] = tcg_global_mem_new(cpu_env,
+ offsetof(CPURISCVState, hlpr[0]), "helper_reg0");
+ cpu_hlpr[1] = tcg_global_mem_new(cpu_env,
+ offsetof(CPURISCVState, hlpr[1]), "helper_reg1");
+
for (i = 0; i < 32; i++) {
cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
diff --git a/target/riscv/insn_trans/trans_rvm.c.inc b/target/riscv/insn_trans/trans_rvm.c.inc
index 9ed9ba0f0f..f46e746bed 100644
--- a/target/riscv/insn_trans/trans_rvm.c.inc
+++ b/target/riscv/insn_trans/trans_rvm.c.inc
@@ -235,6 +235,15 @@ static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
gen_mulhu, gen_mulhu, gen_mulhu_i128);
}
+static void gen_div_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_helper_divs_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h,
+ (TCGv_i64)rs2l, (TCGv_i64)rs2h);
+ tcg_gen_mov_tl(rdl, cpu_hlpr[0]);
+ tcg_gen_mov_tl(rdh, cpu_hlpr[1]);
+}
+
static void gen_div(TCGv ret, TCGv source1, TCGv source2)
{
TCGv temp1, temp2, zero, one, mone, min;
@@ -272,7 +281,16 @@ static bool trans_div(DisasContext *ctx, arg_div *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_SIGN,
- gen_div, gen_div, NULL);
+ gen_div, gen_div, gen_div_i128);
+}
+
+static void gen_divu_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_helper_divu_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h,
+ (TCGv_i64)rs2l, (TCGv_i64)rs2h);
+ tcg_gen_mov_tl(rdl, cpu_hlpr[0]);
+ tcg_gen_mov_tl(rdh, cpu_hlpr[1]);
}
static void gen_divu(TCGv ret, TCGv source1, TCGv source2)
@@ -301,7 +319,16 @@ static bool trans_divu(DisasContext *ctx, arg_divu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_ZERO,
- gen_divu, gen_divu, NULL);
+ gen_divu, gen_divu, gen_divu_i128);
+}
+
+static void gen_rem_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_helper_rems_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h,
+ (TCGv_i64)rs2l, (TCGv_i64)rs2h);
+ tcg_gen_mov_tl(rdl, cpu_hlpr[0]);
+ tcg_gen_mov_tl(rdh, cpu_hlpr[1]);
}
static void gen_rem(TCGv ret, TCGv source1, TCGv source2)
@@ -343,7 +370,16 @@ static bool trans_rem(DisasContext *ctx, arg_rem *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_SIGN,
- gen_rem, gen_rem, NULL);
+ gen_rem, gen_rem, gen_rem_i128);
+}
+
+static void gen_remu_i128(TCGv rdl, TCGv rdh,
+ TCGv rs1l, TCGv rs1h, TCGv rs2l, TCGv rs2h)
+{
+ gen_helper_remu_i128(cpu_env, (TCGv_i64)rs1l, (TCGv_i64)rs1h,
+ (TCGv_i64)rs2l, (TCGv_i64)rs2h);
+ tcg_gen_mov_tl(rdl, cpu_hlpr[0]);
+ tcg_gen_mov_tl(rdh, cpu_hlpr[1]);
}
static void gen_remu(TCGv ret, TCGv source1, TCGv source2)
@@ -372,7 +408,7 @@ static bool trans_remu(DisasContext *ctx, arg_remu *a)
{
REQUIRE_EXT(ctx, RVM);
return gen_arith(ctx, a, EXT_ZERO,
- gen_remu, gen_remu, NULL);
+ gen_remu, gen_remu, gen_remu_i128);
}
static void gen_mulw_i128(TCGv rdl, TCGv rdh,
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index d5e0bc93ea..a32158da93 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -18,6 +18,7 @@ riscv_ss.add(files(
'vector_helper.c',
'bitmanip_helper.c',
'translate.c',
+ 'm128_helper.c'
))
riscv_softmmu_ss = ss.source_set()
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 22/27] target/riscv: adding high part of some csrs
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Adding the high part of a minimal set of csr.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 81cbd77d09..a2d7d65efb 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -196,9 +196,14 @@ struct CPURISCVState {
target_ulong hgatp;
uint64_t htimedelta;
- /* Upper 64-bits of 128-bit misa CSR */
+ /* Upper 64-bits of 128-bit CSRs */
uint64_t misah;
uint64_t misah_mask;
+ uint64_t mtvech;
+ uint64_t mscratchh;
+ uint64_t mepch;
+ uint64_t satph;
+ uint64_t mstatush;
/* Virtual CSRs */
/*
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 22/27] target/riscv: adding high part of some csrs
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Adding the high part of a minimal set of csr.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 81cbd77d09..a2d7d65efb 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -196,9 +196,14 @@ struct CPURISCVState {
target_ulong hgatp;
uint64_t htimedelta;
- /* Upper 64-bits of 128-bit misa CSR */
+ /* Upper 64-bits of 128-bit CSRs */
uint64_t misah;
uint64_t misah_mask;
+ uint64_t mtvech;
+ uint64_t mscratchh;
+ uint64_t mepch;
+ uint64_t satph;
+ uint64_t mstatush;
/* Virtual CSRs */
/*
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 23/27] target/riscv: helper functions to wrap calls to 128-bit csr insns
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We have a slight issue with returning 128-bit values: we use the globals
we added to support div/rem insns to that end.
Theses helpers all call a unique function that is currently a stub.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 4 ++++
target/riscv/helper.h | 3 +++
target/riscv/csr.c | 7 +++++++
target/riscv/op_helper.c | 44 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 58 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a2d7d65efb..911fdc4ecf 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -506,6 +506,10 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
target_ulong new_value,
target_ulong write_mask);
+RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
+ Int128 *ret_value,
+ Int128 new_value, Int128 write_mask);
+
typedef struct {
const char *name;
riscv_csr_predicate_fn predicate;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 01d885d566..d1176649f1 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -68,6 +68,9 @@ DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_2(csrr, tl, env, int)
DEF_HELPER_3(csrw, void, env, int, tl)
DEF_HELPER_4(csrrw, tl, env, int, tl, tl)
+DEF_HELPER_2(csrr_i128, void, env, int)
+DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
+DEF_HELPER_6(csrrw_i128, void, env, int, tl, tl, tl, tl)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_2(sret, tl, env, tl)
DEF_HELPER_2(mret, tl, env, tl)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 23fbbd3216..9529119238 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1492,6 +1492,13 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
+ Int128 *ret_value,
+ Int128 new_value, Int128 write_mask)
+{
+ return RISCV_EXCP_ILLEGAL_INST;
+}
+
/*
* Debugger support. If not in user mode, set env->debugger before the
* riscv_csrrw call and clear it after the call.
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index ee7c24efe7..753eb35000 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -69,6 +69,50 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
return val;
}
+void helper_csrr_i128(CPURISCVState *env, int csr)
+{
+ Int128 rv = int128_zero();
+ RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
+ int128_zero(),
+ int128_zero());
+
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
+ }
+
+ env->hlpr[0] = int128_getlo(rv);
+ env->hlpr[1] = int128_gethi(rv);
+}
+
+void helper_csrw_i128(CPURISCVState *env, int csr,
+ target_ulong srcl, target_ulong srch)
+{
+ RISCVException ret = riscv_csrrw_i128(env, csr, NULL,
+ int128_make128(srcl, srch),
+ UINT128_MAX);
+
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
+ }
+}
+
+void helper_csrrw_i128(CPURISCVState *env, int csr,
+ target_ulong srcl, target_ulong srch,
+ target_ulong maskl, target_ulong maskh)
+{
+ Int128 rv = int128_zero();
+ RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
+ int128_make128(srcl, srch),
+ int128_make128(maskl, maskh));
+
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
+ }
+
+ env->hlpr[0] = int128_getlo(rv);
+ env->hlpr[1] = int128_gethi(rv);
+}
+
#ifndef CONFIG_USER_ONLY
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 23/27] target/riscv: helper functions to wrap calls to 128-bit csr insns
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Given the side effects they have, the csr instructions are realized as
helpers. We extend this existing infrastructure for 128-bit sized csr.
We have a slight issue with returning 128-bit values: we use the globals
we added to support div/rem insns to that end.
Theses helpers all call a unique function that is currently a stub.
The trans_csrxx functions supporting 128-bit are yet to be implemented.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 4 ++++
target/riscv/helper.h | 3 +++
target/riscv/csr.c | 7 +++++++
target/riscv/op_helper.c | 44 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 58 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a2d7d65efb..911fdc4ecf 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -506,6 +506,10 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
target_ulong new_value,
target_ulong write_mask);
+RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
+ Int128 *ret_value,
+ Int128 new_value, Int128 write_mask);
+
typedef struct {
const char *name;
riscv_csr_predicate_fn predicate;
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 01d885d566..d1176649f1 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -68,6 +68,9 @@ DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_2(csrr, tl, env, int)
DEF_HELPER_3(csrw, void, env, int, tl)
DEF_HELPER_4(csrrw, tl, env, int, tl, tl)
+DEF_HELPER_2(csrr_i128, void, env, int)
+DEF_HELPER_4(csrw_i128, void, env, int, tl, tl)
+DEF_HELPER_6(csrrw_i128, void, env, int, tl, tl, tl, tl)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_2(sret, tl, env, tl)
DEF_HELPER_2(mret, tl, env, tl)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 23fbbd3216..9529119238 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1492,6 +1492,13 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
+ Int128 *ret_value,
+ Int128 new_value, Int128 write_mask)
+{
+ return RISCV_EXCP_ILLEGAL_INST;
+}
+
/*
* Debugger support. If not in user mode, set env->debugger before the
* riscv_csrrw call and clear it after the call.
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index ee7c24efe7..753eb35000 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -69,6 +69,50 @@ target_ulong helper_csrrw(CPURISCVState *env, int csr,
return val;
}
+void helper_csrr_i128(CPURISCVState *env, int csr)
+{
+ Int128 rv = int128_zero();
+ RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
+ int128_zero(),
+ int128_zero());
+
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
+ }
+
+ env->hlpr[0] = int128_getlo(rv);
+ env->hlpr[1] = int128_gethi(rv);
+}
+
+void helper_csrw_i128(CPURISCVState *env, int csr,
+ target_ulong srcl, target_ulong srch)
+{
+ RISCVException ret = riscv_csrrw_i128(env, csr, NULL,
+ int128_make128(srcl, srch),
+ UINT128_MAX);
+
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
+ }
+}
+
+void helper_csrrw_i128(CPURISCVState *env, int csr,
+ target_ulong srcl, target_ulong srch,
+ target_ulong maskl, target_ulong maskh)
+{
+ Int128 rv = int128_zero();
+ RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
+ int128_make128(srcl, srch),
+ int128_make128(maskl, maskh));
+
+ if (ret != RISCV_EXCP_NONE) {
+ riscv_raise_exception(env, ret, GETPC());
+ }
+
+ env->hlpr[0] = int128_getlo(rv);
+ env->hlpr[1] = int128_gethi(rv);
+}
+
#ifndef CONFIG_USER_ONLY
target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 24/27] target/riscv: modification of the trans_csrxx for 128-bit support
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 201 ++++++++++++++++++------
1 file changed, 156 insertions(+), 45 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 1a1defb102..7d09cdd89c 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -1087,20 +1087,74 @@ static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mask)
return do_csr_post(ctx);
}
+static bool do_csrr_i128(DisasContext *ctx, int rd, int rc)
+{
+ TCGv_i32 csr = tcg_constant_i32(rc);
+
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_csrr_i128(cpu_env, csr);
+ gen_set_gpr(ctx, rd, cpu_hlpr[0]);
+ gen_set_gprh(ctx, rd, cpu_hlpr[1]);
+ return do_csr_post(ctx);
+}
+
+static bool do_csrw_i128(DisasContext *ctx, int rc, TCGv srcl, TCGv srch)
+{
+ TCGv_i32 csr = tcg_constant_i32(rc);
+
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_csrw_i128(cpu_env, csr, srcl, srch);
+ return do_csr_post(ctx);
+}
+
+static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
+ TCGv srcl, TCGv srch, TCGv maskl, TCGv maskh)
+{
+ TCGv_i32 csr = tcg_constant_i32(rc);
+
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_csrrw_i128(cpu_env, csr, srcl, srch, maskl, maskh);
+ gen_set_gpr(ctx, rd, cpu_hlpr[0]);
+ gen_set_gprh(ctx, rd, cpu_hlpr[1]);
+ return do_csr_post(ctx);
+}
+
static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
{
- TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
-
- /*
- * If rd == 0, the insn shall not read the csr, nor cause any of the
- * side effects that might occur on a csr read.
- */
- if (a->rd == 0) {
- return do_csrw(ctx, a->csr, src);
+ if (!is_128bit(ctx)) {
+ TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ /*
+ * If rd == 0, the insn shall not read the csr, nor cause any of the
+ * side effects that might occur on a csr read.
+ */
+ if (a->rd == 0) {
+ return do_csrw(ctx, a->csr, src);
+ }
+
+ TCGv mask = tcg_constant_tl(-1);
+ return do_csrrw(ctx, a->rd, a->csr, src, mask);
+ } else {
+ TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv srch = get_gprh(ctx, a->rs1);
+
+ /*
+ * If rd == 0, the insn shall not read the csr, nor cause any of the
+ * side effects that might occur on a csr read.
+ */
+ if (a->rd == 0) {
+ return do_csrw_i128(ctx, a->csr, srcl, srch);
+ }
+
+ TCGv mask = tcg_constant_tl(-1);
+ return do_csrrw_i128(ctx, a->rd, a->csr, srcl, srch, mask, mask);
}
-
- TCGv mask = tcg_constant_tl(-1);
- return do_csrrw(ctx, a->rd, a->csr, src, mask);
}
static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
@@ -1112,13 +1166,24 @@ static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
* a zero value, the instruction will still attempt to write the
* unmodified value back to the csr and will cause side effects.
*/
- if (a->rs1 == 0) {
- return do_csrr(ctx, a->rd, a->csr);
+ if (!is_128bit(ctx)) {
+ if (a->rs1 == 0) {
+ return do_csrr(ctx, a->rd, a->csr);
+ }
+
+ TCGv ones = tcg_constant_tl(-1);
+ TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
+ return do_csrrw(ctx, a->rd, a->csr, ones, mask);
+ } else {
+ if (a->rs1 == 0) {
+ return do_csrr_i128(ctx, a->rd, a->csr);
+ }
+
+ TCGv ones = tcg_constant_tl(-1);
+ TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
+ TCGv maskh = get_gprh(ctx, a->rs1);
+ return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, maskl, maskh);
}
-
- TCGv ones = tcg_constant_tl(-1);
- TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
- return do_csrrw(ctx, a->rd, a->csr, ones, mask);
}
static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
@@ -1130,28 +1195,54 @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
* a zero value, the instruction will still attempt to write the
* unmodified value back to the csr and will cause side effects.
*/
- if (a->rs1 == 0) {
- return do_csrr(ctx, a->rd, a->csr);
+ if (!is_128bit(ctx)) {
+ if (a->rs1 == 0) {
+ return do_csrr(ctx, a->rd, a->csr);
+ }
+
+ TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
+ return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
+ } else {
+ if (a->rs1 == 0) {
+ return do_csrr_i128(ctx, a->rd, a->csr);
+ }
+
+ TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
+ TCGv maskh = get_gprh(ctx, a->rs1);
+ return do_csrrw_i128(ctx, a->rd, a->csr,
+ ctx->zero, ctx->zero, maskl, maskh);
}
-
- TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
- return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
}
static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
{
- TCGv src = tcg_constant_tl(a->rs1);
-
- /*
- * If rd == 0, the insn shall not read the csr, nor cause any of the
- * side effects that might occur on a csr read.
- */
- if (a->rd == 0) {
- return do_csrw(ctx, a->csr, src);
+ if (!is_128bit(ctx)) {
+ TCGv src = tcg_constant_tl(a->rs1);
+
+ /*
+ * If rd == 0, the insn shall not read the csr, nor cause any of the
+ * side effects that might occur on a csr read.
+ */
+ if (a->rd == 0) {
+ return do_csrw(ctx, a->csr, src);
+ }
+
+ TCGv mask = tcg_constant_tl(-1);
+ return do_csrrw(ctx, a->rd, a->csr, src, mask);
+ } else {
+ TCGv src = tcg_constant_tl(a->rs1);
+
+ /*
+ * If rd == 0, the insn shall not read the csr, nor cause any of the
+ * side effects that might occur on a csr read.
+ */
+ if (a->rd == 0) {
+ return do_csrw_i128(ctx, a->csr, src, ctx->zero);
+ }
+
+ TCGv mask = tcg_constant_tl(-1);
+ return do_csrrw_i128(ctx, a->rd, a->csr, src, ctx->zero, mask, mask);
}
-
- TCGv mask = tcg_constant_tl(-1);
- return do_csrrw(ctx, a->rd, a->csr, src, mask);
}
static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
@@ -1163,16 +1254,26 @@ static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
* a zero value, the instruction will still attempt to write the
* unmodified value back to the csr and will cause side effects.
*/
- if (a->rs1 == 0) {
- return do_csrr(ctx, a->rd, a->csr);
+ if (!is_128bit(ctx)) {
+ if (a->rs1 == 0) {
+ return do_csrr(ctx, a->rd, a->csr);
+ }
+
+ TCGv ones = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(a->rs1);
+ return do_csrrw(ctx, a->rd, a->csr, ones, mask);
+ } else {
+ if (a->rs1 == 0) {
+ return do_csrr_i128(ctx, a->rd, a->csr);
+ }
+
+ TCGv ones = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(a->rs1);
+ return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, mask, ctx->zero);
}
-
- TCGv ones = tcg_constant_tl(-1);
- TCGv mask = tcg_constant_tl(a->rs1);
- return do_csrrw(ctx, a->rd, a->csr, ones, mask);
}
-static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
+static bool trans_csrrci(DisasContext *ctx, arg_csrrci * a)
{
/*
* If rs1 == 0, the insn shall not write to the csr at all, nor
@@ -1181,10 +1282,20 @@ static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
* a zero value, the instruction will still attempt to write the
* unmodified value back to the csr and will cause side effects.
*/
- if (a->rs1 == 0) {
- return do_csrr(ctx, a->rd, a->csr);
+ if (!is_128bit(ctx)) {
+ if (a->rs1 == 0) {
+ return do_csrr(ctx, a->rd, a->csr);
+ }
+
+ TCGv mask = tcg_constant_tl(a->rs1);
+ return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
+ } else {
+ if (a->rs1 == 0) {
+ return do_csrr_i128(ctx, a->rd, a->csr);
+ }
+
+ TCGv mask = tcg_constant_tl(a->rs1);
+ return do_csrrw_i128(ctx, a->rd, a->csr,
+ ctx->zero, ctx->zero, mask, ctx->zero);
}
-
- TCGv mask = tcg_constant_tl(a->rs1);
- return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
}
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 24/27] target/riscv: modification of the trans_csrxx for 128-bit support
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
As opposed to the gen_arith and gen_shift generation helpers, the csr insns
do not have a common prototype, so the choice to generate 32/64 or 128-bit
helper calls is done in the trans_csrxx functions.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 201 ++++++++++++++++++------
1 file changed, 156 insertions(+), 45 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
index 1a1defb102..7d09cdd89c 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -1087,20 +1087,74 @@ static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mask)
return do_csr_post(ctx);
}
+static bool do_csrr_i128(DisasContext *ctx, int rd, int rc)
+{
+ TCGv_i32 csr = tcg_constant_i32(rc);
+
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_csrr_i128(cpu_env, csr);
+ gen_set_gpr(ctx, rd, cpu_hlpr[0]);
+ gen_set_gprh(ctx, rd, cpu_hlpr[1]);
+ return do_csr_post(ctx);
+}
+
+static bool do_csrw_i128(DisasContext *ctx, int rc, TCGv srcl, TCGv srch)
+{
+ TCGv_i32 csr = tcg_constant_i32(rc);
+
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_csrw_i128(cpu_env, csr, srcl, srch);
+ return do_csr_post(ctx);
+}
+
+static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc,
+ TCGv srcl, TCGv srch, TCGv maskl, TCGv maskh)
+{
+ TCGv_i32 csr = tcg_constant_i32(rc);
+
+ if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
+ gen_io_start();
+ }
+ gen_helper_csrrw_i128(cpu_env, csr, srcl, srch, maskl, maskh);
+ gen_set_gpr(ctx, rd, cpu_hlpr[0]);
+ gen_set_gprh(ctx, rd, cpu_hlpr[1]);
+ return do_csr_post(ctx);
+}
+
static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a)
{
- TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
-
- /*
- * If rd == 0, the insn shall not read the csr, nor cause any of the
- * side effects that might occur on a csr read.
- */
- if (a->rd == 0) {
- return do_csrw(ctx, a->csr, src);
+ if (!is_128bit(ctx)) {
+ TCGv src = get_gpr(ctx, a->rs1, EXT_NONE);
+
+ /*
+ * If rd == 0, the insn shall not read the csr, nor cause any of the
+ * side effects that might occur on a csr read.
+ */
+ if (a->rd == 0) {
+ return do_csrw(ctx, a->csr, src);
+ }
+
+ TCGv mask = tcg_constant_tl(-1);
+ return do_csrrw(ctx, a->rd, a->csr, src, mask);
+ } else {
+ TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv srch = get_gprh(ctx, a->rs1);
+
+ /*
+ * If rd == 0, the insn shall not read the csr, nor cause any of the
+ * side effects that might occur on a csr read.
+ */
+ if (a->rd == 0) {
+ return do_csrw_i128(ctx, a->csr, srcl, srch);
+ }
+
+ TCGv mask = tcg_constant_tl(-1);
+ return do_csrrw_i128(ctx, a->rd, a->csr, srcl, srch, mask, mask);
}
-
- TCGv mask = tcg_constant_tl(-1);
- return do_csrrw(ctx, a->rd, a->csr, src, mask);
}
static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
@@ -1112,13 +1166,24 @@ static bool trans_csrrs(DisasContext *ctx, arg_csrrs *a)
* a zero value, the instruction will still attempt to write the
* unmodified value back to the csr and will cause side effects.
*/
- if (a->rs1 == 0) {
- return do_csrr(ctx, a->rd, a->csr);
+ if (!is_128bit(ctx)) {
+ if (a->rs1 == 0) {
+ return do_csrr(ctx, a->rd, a->csr);
+ }
+
+ TCGv ones = tcg_constant_tl(-1);
+ TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
+ return do_csrrw(ctx, a->rd, a->csr, ones, mask);
+ } else {
+ if (a->rs1 == 0) {
+ return do_csrr_i128(ctx, a->rd, a->csr);
+ }
+
+ TCGv ones = tcg_constant_tl(-1);
+ TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
+ TCGv maskh = get_gprh(ctx, a->rs1);
+ return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, maskl, maskh);
}
-
- TCGv ones = tcg_constant_tl(-1);
- TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
- return do_csrrw(ctx, a->rd, a->csr, ones, mask);
}
static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
@@ -1130,28 +1195,54 @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a)
* a zero value, the instruction will still attempt to write the
* unmodified value back to the csr and will cause side effects.
*/
- if (a->rs1 == 0) {
- return do_csrr(ctx, a->rd, a->csr);
+ if (!is_128bit(ctx)) {
+ if (a->rs1 == 0) {
+ return do_csrr(ctx, a->rd, a->csr);
+ }
+
+ TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
+ return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
+ } else {
+ if (a->rs1 == 0) {
+ return do_csrr_i128(ctx, a->rd, a->csr);
+ }
+
+ TCGv maskl = get_gpr(ctx, a->rs1, EXT_ZERO);
+ TCGv maskh = get_gprh(ctx, a->rs1);
+ return do_csrrw_i128(ctx, a->rd, a->csr,
+ ctx->zero, ctx->zero, maskl, maskh);
}
-
- TCGv mask = get_gpr(ctx, a->rs1, EXT_ZERO);
- return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
}
static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a)
{
- TCGv src = tcg_constant_tl(a->rs1);
-
- /*
- * If rd == 0, the insn shall not read the csr, nor cause any of the
- * side effects that might occur on a csr read.
- */
- if (a->rd == 0) {
- return do_csrw(ctx, a->csr, src);
+ if (!is_128bit(ctx)) {
+ TCGv src = tcg_constant_tl(a->rs1);
+
+ /*
+ * If rd == 0, the insn shall not read the csr, nor cause any of the
+ * side effects that might occur on a csr read.
+ */
+ if (a->rd == 0) {
+ return do_csrw(ctx, a->csr, src);
+ }
+
+ TCGv mask = tcg_constant_tl(-1);
+ return do_csrrw(ctx, a->rd, a->csr, src, mask);
+ } else {
+ TCGv src = tcg_constant_tl(a->rs1);
+
+ /*
+ * If rd == 0, the insn shall not read the csr, nor cause any of the
+ * side effects that might occur on a csr read.
+ */
+ if (a->rd == 0) {
+ return do_csrw_i128(ctx, a->csr, src, ctx->zero);
+ }
+
+ TCGv mask = tcg_constant_tl(-1);
+ return do_csrrw_i128(ctx, a->rd, a->csr, src, ctx->zero, mask, mask);
}
-
- TCGv mask = tcg_constant_tl(-1);
- return do_csrrw(ctx, a->rd, a->csr, src, mask);
}
static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
@@ -1163,16 +1254,26 @@ static bool trans_csrrsi(DisasContext *ctx, arg_csrrsi *a)
* a zero value, the instruction will still attempt to write the
* unmodified value back to the csr and will cause side effects.
*/
- if (a->rs1 == 0) {
- return do_csrr(ctx, a->rd, a->csr);
+ if (!is_128bit(ctx)) {
+ if (a->rs1 == 0) {
+ return do_csrr(ctx, a->rd, a->csr);
+ }
+
+ TCGv ones = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(a->rs1);
+ return do_csrrw(ctx, a->rd, a->csr, ones, mask);
+ } else {
+ if (a->rs1 == 0) {
+ return do_csrr_i128(ctx, a->rd, a->csr);
+ }
+
+ TCGv ones = tcg_constant_tl(-1);
+ TCGv mask = tcg_constant_tl(a->rs1);
+ return do_csrrw_i128(ctx, a->rd, a->csr, ones, ones, mask, ctx->zero);
}
-
- TCGv ones = tcg_constant_tl(-1);
- TCGv mask = tcg_constant_tl(a->rs1);
- return do_csrrw(ctx, a->rd, a->csr, ones, mask);
}
-static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
+static bool trans_csrrci(DisasContext *ctx, arg_csrrci * a)
{
/*
* If rs1 == 0, the insn shall not write to the csr at all, nor
@@ -1181,10 +1282,20 @@ static bool trans_csrrci(DisasContext *ctx, arg_csrrci *a)
* a zero value, the instruction will still attempt to write the
* unmodified value back to the csr and will cause side effects.
*/
- if (a->rs1 == 0) {
- return do_csrr(ctx, a->rd, a->csr);
+ if (!is_128bit(ctx)) {
+ if (a->rs1 == 0) {
+ return do_csrr(ctx, a->rd, a->csr);
+ }
+
+ TCGv mask = tcg_constant_tl(a->rs1);
+ return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
+ } else {
+ if (a->rs1 == 0) {
+ return do_csrr_i128(ctx, a->rd, a->csr);
+ }
+
+ TCGv mask = tcg_constant_tl(a->rs1);
+ return do_csrrw_i128(ctx, a->rd, a->csr,
+ ctx->zero, ctx->zero, mask, ctx->zero);
}
-
- TCGv mask = tcg_constant_tl(a->rs1);
- return do_csrrw(ctx, a->rd, a->csr, ctx->zero, mask);
}
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 25/27] target/riscv: actual functions to realize crs 128-bit insns
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
The csrs are accessed through function pointers: we set-up the table
for the 128-bit accesses, make the stub a function that does what it
should, and implement basic accesses on read-only csrs.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 16 +++++
target/riscv/csr.c | 152 ++++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 165 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 911fdc4ecf..8a28b69a1b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -510,6 +510,15 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
Int128 *ret_value,
Int128 new_value, Int128 write_mask);
+typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
+ Int128 *ret_value);
+typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
+ Int128 new_value);
+typedef RISCVException (*riscv_csr_op128_fn)(CPURISCVState *env, int csrno,
+ Int128 *ret_value,
+ Int128 new_value,
+ Int128 write_mask);
+
typedef struct {
const char *name;
riscv_csr_predicate_fn predicate;
@@ -518,6 +527,12 @@ typedef struct {
riscv_csr_op_fn op;
} riscv_csr_operations;
+typedef struct {
+ riscv_csr_read128_fn read128;
+ riscv_csr_write128_fn write128;
+ riscv_csr_op128_fn op128;
+} riscv_csr_operations128;
+
/* CSR function table constants */
enum {
CSR_TABLE_SIZE = 0x1000
@@ -525,6 +540,7 @@ enum {
/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
+extern riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE];
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9529119238..6ebc03f89b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -462,6 +462,13 @@ static const char valid_vm_1_10_64[16] = {
};
/* Machine Information Registers */
+static RISCVException read_zero_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_zero();
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_zero(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -469,6 +476,13 @@ static RISCVException read_zero(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mhartid_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_make64(env->mhartid);
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -554,6 +568,13 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_make128(env->misa, env->misah);
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_misa(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1492,11 +1513,118 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static inline RISCVException riscv_csrrw_check_i128(CPURISCVState *env,
+ int csrno,
+ Int128 write_mask,
+ RISCVCPU *cpu)
+{
+ /* check privileges and return -1 if check fails */
+#if !defined(CONFIG_USER_ONLY)
+ int effective_priv = env->priv;
+ int read_only = get_field(csrno, 0xc00) == 3;
+
+ if (riscv_has_ext(env, RVH) &&
+ env->priv == PRV_S &&
+ !riscv_cpu_virt_enabled(env)) {
+ /*
+ * We are in S mode without virtualisation, therefore we are in HS Mode.
+ * Add 1 to the effective privledge level to allow us to access the
+ * Hypervisor CSRs.
+ */
+ effective_priv++;
+ }
+
+ if ((int128_nz(write_mask) && read_only) ||
+ (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#endif
+
+ /* ensure the CSR extension is enabled. */
+ if (!cpu->cfg.ext_icsr) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ /* check predicate */
+ if (!csr_ops[csrno].predicate) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ RISCVException ret = csr_ops[csrno].predicate(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
- Int128 *ret_value,
- Int128 new_value, Int128 write_mask)
+ Int128 *ret_value,
+ Int128 new_value, Int128 write_mask)
{
- return RISCV_EXCP_ILLEGAL_INST;
+ RISCVException ret;
+ Int128 old_value;
+
+ RISCVCPU *cpu = env_archcpu(env);
+
+ if (!csr_ops_128[csrno].read128 && !csr_ops_128[csrno].op128) {
+ /*
+ * FIXME: Fall back to 64-bit version for now, if the 128-bit
+ * alternative isn't defined.
+ * Note, some CSRs don't extend to MXLEN, for those,
+ * this fallback is correctly handling the read/write.
+ */
+ target_ulong ret_64;
+ ret = riscv_csrrw(env, csrno, &ret_64,
+ int128_getlo(new_value),
+ int128_getlo(write_mask));
+
+ if (ret_value) {
+ *ret_value = int128_make64(ret_64);
+ }
+
+ return ret;
+ }
+
+ RISCVException check_status =
+ riscv_csrrw_check_i128(env, csrno, write_mask, cpu);
+ if (check_status != RISCV_EXCP_NONE) {
+ return check_status;
+ }
+
+ /* execute combined read/write operation if it exists */
+ if (csr_ops_128[csrno].op128) {
+ return csr_ops_128[csrno].op128(env, csrno, ret_value,
+ new_value, write_mask);
+ }
+
+ /* if no accessor exists then return failure */
+ if (!csr_ops_128[csrno].read128) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ /* read old value */
+ ret = csr_ops_128[csrno].read128(env, csrno, &old_value);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ /* write value if writable and write mask set, otherwise drop writes */
+ if (int128_nz(write_mask)) {
+ new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
+ int128_and(new_value, write_mask));
+ if (csr_ops_128[csrno].write128) {
+ ret = csr_ops_128[csrno].write128(env, csrno, new_value);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+ }
+ }
+
+ /* return old value */
+ if (ret_value) {
+ *ret_value = old_value;
+ }
+
+ return RISCV_EXCP_NONE;
}
/*
@@ -1520,6 +1648,24 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
}
/* Control and Status Register function table */
+riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE] = {
+#if !defined(CONFIG_USER_ONLY)
+ [CSR_MVENDORID] = { read_zero_i128 },
+ [CSR_MARCHID] = { read_zero_i128 },
+ [CSR_MIMPID] = { read_zero_i128 },
+ [CSR_MHARTID] = { read_mhartid_i128 },
+
+ [CSR_MSTATUS] = { read_zero_i128 },
+ [CSR_MISA] = { read_misa_i128 },
+ [CSR_MTVEC] = { read_zero_i128 },
+
+ [CSR_MSCRATCH] = { read_zero_i128 },
+ [CSR_MEPC] = { read_zero_i128 },
+
+ [CSR_SATP] = { read_zero_i128 },
+#endif
+};
+
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Floating-Point CSRs */
[CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 25/27] target/riscv: actual functions to realize crs 128-bit insns
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
The csrs are accessed through function pointers: we set-up the table
for the 128-bit accesses, make the stub a function that does what it
should, and implement basic accesses on read-only csrs.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu.h | 16 +++++
target/riscv/csr.c | 152 ++++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 165 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 911fdc4ecf..8a28b69a1b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -510,6 +510,15 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
Int128 *ret_value,
Int128 new_value, Int128 write_mask);
+typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
+ Int128 *ret_value);
+typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno,
+ Int128 new_value);
+typedef RISCVException (*riscv_csr_op128_fn)(CPURISCVState *env, int csrno,
+ Int128 *ret_value,
+ Int128 new_value,
+ Int128 write_mask);
+
typedef struct {
const char *name;
riscv_csr_predicate_fn predicate;
@@ -518,6 +527,12 @@ typedef struct {
riscv_csr_op_fn op;
} riscv_csr_operations;
+typedef struct {
+ riscv_csr_read128_fn read128;
+ riscv_csr_write128_fn write128;
+ riscv_csr_op128_fn op128;
+} riscv_csr_operations128;
+
/* CSR function table constants */
enum {
CSR_TABLE_SIZE = 0x1000
@@ -525,6 +540,7 @@ enum {
/* CSR function table */
extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE];
+extern riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE];
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9529119238..6ebc03f89b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -462,6 +462,13 @@ static const char valid_vm_1_10_64[16] = {
};
/* Machine Information Registers */
+static RISCVException read_zero_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_zero();
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_zero(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -469,6 +476,13 @@ static RISCVException read_zero(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mhartid_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_make64(env->mhartid);
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -554,6 +568,13 @@ static RISCVException write_mstatush(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_make128(env->misa, env->misah);
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_misa(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1492,11 +1513,118 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static inline RISCVException riscv_csrrw_check_i128(CPURISCVState *env,
+ int csrno,
+ Int128 write_mask,
+ RISCVCPU *cpu)
+{
+ /* check privileges and return -1 if check fails */
+#if !defined(CONFIG_USER_ONLY)
+ int effective_priv = env->priv;
+ int read_only = get_field(csrno, 0xc00) == 3;
+
+ if (riscv_has_ext(env, RVH) &&
+ env->priv == PRV_S &&
+ !riscv_cpu_virt_enabled(env)) {
+ /*
+ * We are in S mode without virtualisation, therefore we are in HS Mode.
+ * Add 1 to the effective privledge level to allow us to access the
+ * Hypervisor CSRs.
+ */
+ effective_priv++;
+ }
+
+ if ((int128_nz(write_mask) && read_only) ||
+ (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+#endif
+
+ /* ensure the CSR extension is enabled. */
+ if (!cpu->cfg.ext_icsr) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ /* check predicate */
+ if (!csr_ops[csrno].predicate) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ RISCVException ret = csr_ops[csrno].predicate(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
- Int128 *ret_value,
- Int128 new_value, Int128 write_mask)
+ Int128 *ret_value,
+ Int128 new_value, Int128 write_mask)
{
- return RISCV_EXCP_ILLEGAL_INST;
+ RISCVException ret;
+ Int128 old_value;
+
+ RISCVCPU *cpu = env_archcpu(env);
+
+ if (!csr_ops_128[csrno].read128 && !csr_ops_128[csrno].op128) {
+ /*
+ * FIXME: Fall back to 64-bit version for now, if the 128-bit
+ * alternative isn't defined.
+ * Note, some CSRs don't extend to MXLEN, for those,
+ * this fallback is correctly handling the read/write.
+ */
+ target_ulong ret_64;
+ ret = riscv_csrrw(env, csrno, &ret_64,
+ int128_getlo(new_value),
+ int128_getlo(write_mask));
+
+ if (ret_value) {
+ *ret_value = int128_make64(ret_64);
+ }
+
+ return ret;
+ }
+
+ RISCVException check_status =
+ riscv_csrrw_check_i128(env, csrno, write_mask, cpu);
+ if (check_status != RISCV_EXCP_NONE) {
+ return check_status;
+ }
+
+ /* execute combined read/write operation if it exists */
+ if (csr_ops_128[csrno].op128) {
+ return csr_ops_128[csrno].op128(env, csrno, ret_value,
+ new_value, write_mask);
+ }
+
+ /* if no accessor exists then return failure */
+ if (!csr_ops_128[csrno].read128) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+ /* read old value */
+ ret = csr_ops_128[csrno].read128(env, csrno, &old_value);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ /* write value if writable and write mask set, otherwise drop writes */
+ if (int128_nz(write_mask)) {
+ new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
+ int128_and(new_value, write_mask));
+ if (csr_ops_128[csrno].write128) {
+ ret = csr_ops_128[csrno].write128(env, csrno, new_value);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+ }
+ }
+
+ /* return old value */
+ if (ret_value) {
+ *ret_value = old_value;
+ }
+
+ return RISCV_EXCP_NONE;
}
/*
@@ -1520,6 +1648,24 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
}
/* Control and Status Register function table */
+riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE] = {
+#if !defined(CONFIG_USER_ONLY)
+ [CSR_MVENDORID] = { read_zero_i128 },
+ [CSR_MARCHID] = { read_zero_i128 },
+ [CSR_MIMPID] = { read_zero_i128 },
+ [CSR_MHARTID] = { read_mhartid_i128 },
+
+ [CSR_MSTATUS] = { read_zero_i128 },
+ [CSR_MISA] = { read_misa_i128 },
+ [CSR_MTVEC] = { read_zero_i128 },
+
+ [CSR_MSCRATCH] = { read_zero_i128 },
+ [CSR_MEPC] = { read_zero_i128 },
+
+ [CSR_SATP] = { read_zero_i128 },
+#endif
+};
+
riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Floating-Point CSRs */
[CSR_FFLAGS] = { "fflags", fs, read_fflags, write_fflags },
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 26/27] target/riscv: adding 128-bit access functions for some csrs
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Access to mstatus, mtvec, mscratch and mepc is implemented.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 111 ++++++++++++++++++++++++++++++++++++++--
2 files changed, 108 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..553b0a3d71 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -360,6 +360,7 @@
#define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000ULL
+#define MSTATUSH128_SD 0x8000000000000000ULL
#define MISA32_MXL 0xC0000000
#define MISA64_MXL 0xC000000000000000ULL
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6ebc03f89b..a9146a4496 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -491,6 +491,61 @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno,
}
/* Machine Trap Setup */
+static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_make128(env->mstatus, env->mstatush);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mstatus_i128(CPURISCVState *env, int csrno,
+ Int128 val)
+{
+ Int128 mstatus = int128_make128(env->mstatus, env->mstatush);
+ Int128 mask = int128_zero();
+ int dirty;
+
+ /* flush tlb on mstatus fields that affect VM */
+ if (int128_getlo(int128_xor(mstatus, val))
+ & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
+ MSTATUS_MPRV | MSTATUS_SUM)) {
+ tlb_flush(env_cpu(env));
+ }
+ mask = int128_make64(MSTATUS_SIE | MSTATUS_SPIE |
+ MSTATUS_MIE | MSTATUS_MPIE |
+ MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
+ MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
+ MSTATUS_TW);
+
+ if (!riscv_cpu_is_32bit(env)) {
+ /*
+ * RV32: MPV and GVA are not in mstatus. The current plan is to
+ * add them to mstatush. For now, we just don't support it.
+ */
+ mask = int128_or(mask, int128_make64(MSTATUS_MPV | MSTATUS_GVA));
+ }
+
+ mstatus = int128_or(int128_and(mstatus, int128_not(mask)),
+ int128_and(val, mask));
+
+ dirty = ((int128_getlo(mstatus) & MSTATUS_FS) == MSTATUS_FS) |
+ ((int128_getlo(mstatus) & MSTATUS_XS) == MSTATUS_XS);
+ if (dirty) {
+ if (riscv_cpu_is_32bit(env)) {
+ mstatus = int128_make64(int128_getlo(mstatus) | MSTATUS32_SD);
+ } else if (riscv_cpu_is_64bit(env)) {
+ mstatus = int128_make64(int128_getlo(mstatus) | MSTATUS64_SD);
+ } else {
+ mstatus = int128_or(mstatus, int128_make128(0, MSTATUSH128_SD));
+ }
+ }
+
+ env->mstatus = int128_getlo(mstatus);
+ env->mstatush = int128_gethi(mstatus);
+
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mstatus(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -684,6 +739,26 @@ static RISCVException write_mie(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mtvec_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_make128(env->mtvec, env->mtvech);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mtvec_i128(CPURISCVState *env, int csrno,
+ Int128 val)
+{
+ /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+ if ((int128_getlo(val) & 3) < 2) {
+ env->mtvec = int128_getlo(val);
+ env->mtvech = int128_gethi(val);
+ } else {
+ qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
+ }
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mtvec(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -718,6 +793,19 @@ static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
}
/* Machine Trap Handling */
+static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
+ Int128 *val) {
+ *val = int128_make128(env->mscratch, env->mscratchh);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
+ Int128 val) {
+ env->mscratch = int128_getlo(val);
+ env->mscratchh = int128_gethi(val);
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mscratch(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -732,6 +820,21 @@ static RISCVException write_mscratch(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mepc_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_make128(env->mepc, env->mepch);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mepc_i128(CPURISCVState *env, int csrno,
+ Int128 val)
+{
+ env->mepc = int128_getlo(val);
+ env->mepch = int128_gethi(val);
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mepc(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1655,12 +1758,12 @@ riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE] = {
[CSR_MIMPID] = { read_zero_i128 },
[CSR_MHARTID] = { read_mhartid_i128 },
- [CSR_MSTATUS] = { read_zero_i128 },
+ [CSR_MSTATUS] = { read_mstatus_i128, write_mstatus_i128 },
[CSR_MISA] = { read_misa_i128 },
- [CSR_MTVEC] = { read_zero_i128 },
+ [CSR_MTVEC] = { read_mtvec_i128, write_mtvec_i128 },
- [CSR_MSCRATCH] = { read_zero_i128 },
- [CSR_MEPC] = { read_zero_i128 },
+ [CSR_MSCRATCH] = { read_mscratch_i128, write_mscratch_i128 },
+ [CSR_MEPC] = { read_mepc_i128, write_mepc_i128 },
[CSR_SATP] = { read_zero_i128 },
#endif
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 26/27] target/riscv: adding 128-bit access functions for some csrs
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Access to mstatus, mtvec, mscratch and mepc is implemented.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 111 ++++++++++++++++++++++++++++++++++++++--
2 files changed, 108 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..553b0a3d71 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -360,6 +360,7 @@
#define MSTATUS32_SD 0x80000000
#define MSTATUS64_SD 0x8000000000000000ULL
+#define MSTATUSH128_SD 0x8000000000000000ULL
#define MISA32_MXL 0xC0000000
#define MISA64_MXL 0xC000000000000000ULL
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6ebc03f89b..a9146a4496 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -491,6 +491,61 @@ static RISCVException read_mhartid(CPURISCVState *env, int csrno,
}
/* Machine Trap Setup */
+static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_make128(env->mstatus, env->mstatush);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mstatus_i128(CPURISCVState *env, int csrno,
+ Int128 val)
+{
+ Int128 mstatus = int128_make128(env->mstatus, env->mstatush);
+ Int128 mask = int128_zero();
+ int dirty;
+
+ /* flush tlb on mstatus fields that affect VM */
+ if (int128_getlo(int128_xor(mstatus, val))
+ & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
+ MSTATUS_MPRV | MSTATUS_SUM)) {
+ tlb_flush(env_cpu(env));
+ }
+ mask = int128_make64(MSTATUS_SIE | MSTATUS_SPIE |
+ MSTATUS_MIE | MSTATUS_MPIE |
+ MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
+ MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
+ MSTATUS_TW);
+
+ if (!riscv_cpu_is_32bit(env)) {
+ /*
+ * RV32: MPV and GVA are not in mstatus. The current plan is to
+ * add them to mstatush. For now, we just don't support it.
+ */
+ mask = int128_or(mask, int128_make64(MSTATUS_MPV | MSTATUS_GVA));
+ }
+
+ mstatus = int128_or(int128_and(mstatus, int128_not(mask)),
+ int128_and(val, mask));
+
+ dirty = ((int128_getlo(mstatus) & MSTATUS_FS) == MSTATUS_FS) |
+ ((int128_getlo(mstatus) & MSTATUS_XS) == MSTATUS_XS);
+ if (dirty) {
+ if (riscv_cpu_is_32bit(env)) {
+ mstatus = int128_make64(int128_getlo(mstatus) | MSTATUS32_SD);
+ } else if (riscv_cpu_is_64bit(env)) {
+ mstatus = int128_make64(int128_getlo(mstatus) | MSTATUS64_SD);
+ } else {
+ mstatus = int128_or(mstatus, int128_make128(0, MSTATUSH128_SD));
+ }
+ }
+
+ env->mstatus = int128_getlo(mstatus);
+ env->mstatush = int128_gethi(mstatus);
+
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mstatus(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -684,6 +739,26 @@ static RISCVException write_mie(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mtvec_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_make128(env->mtvec, env->mtvech);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mtvec_i128(CPURISCVState *env, int csrno,
+ Int128 val)
+{
+ /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+ if ((int128_getlo(val) & 3) < 2) {
+ env->mtvec = int128_getlo(val);
+ env->mtvech = int128_gethi(val);
+ } else {
+ qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
+ }
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mtvec(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -718,6 +793,19 @@ static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
}
/* Machine Trap Handling */
+static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
+ Int128 *val) {
+ *val = int128_make128(env->mscratch, env->mscratchh);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
+ Int128 val) {
+ env->mscratch = int128_getlo(val);
+ env->mscratchh = int128_gethi(val);
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mscratch(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -732,6 +820,21 @@ static RISCVException write_mscratch(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_mepc_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ *val = int128_make128(env->mepc, env->mepch);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mepc_i128(CPURISCVState *env, int csrno,
+ Int128 val)
+{
+ env->mepc = int128_getlo(val);
+ env->mepch = int128_gethi(val);
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mepc(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1655,12 +1758,12 @@ riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE] = {
[CSR_MIMPID] = { read_zero_i128 },
[CSR_MHARTID] = { read_mhartid_i128 },
- [CSR_MSTATUS] = { read_zero_i128 },
+ [CSR_MSTATUS] = { read_mstatus_i128, write_mstatus_i128 },
[CSR_MISA] = { read_misa_i128 },
- [CSR_MTVEC] = { read_zero_i128 },
+ [CSR_MTVEC] = { read_mtvec_i128, write_mtvec_i128 },
- [CSR_MSCRATCH] = { read_zero_i128 },
- [CSR_MEPC] = { read_zero_i128 },
+ [CSR_MSCRATCH] = { read_mscratch_i128, write_mscratch_i128 },
+ [CSR_MEPC] = { read_mepc_i128, write_mepc_i128 },
[CSR_SATP] = { read_zero_i128 },
#endif
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 27/27] target/riscv: support for 128-bit satp
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-06 21:28 ` Frédéric Pétrot
-1 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas,
palmer, Frédéric Pétrot, philmd
Support for a 128-bit satp. This is a bit more involved than necessary
because we took the opportunity to increase the page size to 16kB, and
change the page table geometry, which makes the page walk a bit more
parametrizable (variables instead of defines).
Note that is anyway a necessary step for the merging of the 32-bit and
64-bit riscv versions in a single executable.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu-param.h | 9 ++++-
target/riscv/cpu_bits.h | 10 +++++
target/riscv/cpu_helper.c | 54 +++++++++++++++++++--------
target/riscv/csr.c | 77 +++++++++++++++++++++++++++++++++++++--
4 files changed, 130 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index c10459b56f..78f0916403 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -19,10 +19,15 @@
#else
/* 64-bit target, since QEMU isn't built to have TARGET_LONG_BITS over 64 */
# define TARGET_LONG_BITS 64
-# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
-# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
+# define TARGET_PHYS_ADDR_SPACE_BITS 64 /* 54-bit PPN */
+# define TARGET_VIRT_ADDR_SPACE_BITS 44 /* sv44 */
#endif
+
+#if defined(TARGET_RISCV32) || defined(TARGET_RISCV64)
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
+#else
+#define TARGET_PAGE_BITS 14 /* 16 KiB pages for RV128 */
+#endif
/*
* The current MMU Modes are:
* - U mode 0b000
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 553b0a3d71..a4f6ba927f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -428,6 +428,11 @@
#define SATP64_ASID 0x0FFFF00000000000ULL
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
+/* RV128 satp CSR field masks (H/L for high/low dword) */
+#define SATP128_HMODE 0xFF00000000000000ULL
+#define SATP128_HASID 0x00FFFFFFFF000000ULL
+#define SATP128_LPPN 0x0003FFFFFFFFFFFFULL
+
/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
#define VM_1_09_MBARE 0
#define VM_1_09_MBB 1
@@ -443,6 +448,9 @@
#define VM_1_10_SV48 9
#define VM_1_10_SV57 10
#define VM_1_10_SV64 11
+#define VM_1_10_SV44 12
+#define VM_1_10_SV54 13
+
/* Page table entry (PTE) fields */
#define PTE_V 0x001 /* Valid */
@@ -460,6 +468,8 @@
/* Leaf page shift amount */
#define PGSHIFT 12
+/* For now, pages in RV128 are 16 KiB. */
+#define PGSHIFT128 14
/* Default Reset Vector adress */
#define DEFAULT_RSTVEC 0x1000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d41d5cd27c..55dea1f58b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -391,7 +391,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
*prot = 0;
hwaddr base;
- int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
+ int levels, ptidxbits, ptesize, vm, sum, mxr, widened, pgshift;
if (first_stage == true) {
mxr = get_field(env->mstatus, MSTATUS_MXR);
@@ -404,17 +404,25 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
if (riscv_cpu_is_32bit(env)) {
base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->vsatp, SATP32_MODE);
- } else {
+ } else if (riscv_cpu_is_64bit(env)) {
base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
vm = get_field(env->vsatp, SATP64_MODE);
+ } else {
+ /* TODO : Hypervisor extension not supported yet in RV128. */
+ g_assert_not_reached();
}
} else {
if (riscv_cpu_is_32bit(env)) {
base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->satp, SATP32_MODE);
- } else {
+ } else if (riscv_cpu_is_64bit(env)) {
base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
vm = get_field(env->satp, SATP64_MODE);
+ } else if (riscv_cpu_is_128bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP128_LPPN) << PGSHIFT128;
+ vm = get_field(env->satph, SATP128_HMODE);
+ } else {
+ g_assert_not_reached();
}
}
widened = 0;
@@ -422,9 +430,15 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
if (riscv_cpu_is_32bit(env)) {
base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->hgatp, SATP32_MODE);
- } else {
+ } else if (riscv_cpu_is_64bit(env)) {
base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
vm = get_field(env->hgatp, SATP64_MODE);
+ } else {
+ /*
+ * TODO : Hypervisor extension not supported yet in RV128,
+ * so there shouldn't be any two-stage address lookups.
+ */
+ g_assert_not_reached();
}
widened = 2;
}
@@ -432,13 +446,17 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
switch (vm) {
case VM_1_10_SV32:
- levels = 2; ptidxbits = 10; ptesize = 4; break;
+ levels = 2; ptidxbits = 10; ptesize = 4; pgshift = 12; break;
case VM_1_10_SV39:
- levels = 3; ptidxbits = 9; ptesize = 8; break;
+ levels = 3; ptidxbits = 9; ptesize = 8; pgshift = 12; break;
case VM_1_10_SV48:
- levels = 4; ptidxbits = 9; ptesize = 8; break;
+ levels = 4; ptidxbits = 9; ptesize = 8; pgshift = 12; break;
case VM_1_10_SV57:
- levels = 5; ptidxbits = 9; ptesize = 8; break;
+ levels = 5; ptidxbits = 9; ptesize = 8; pgshift = 12; break;
+ case VM_1_10_SV44:
+ levels = 3; ptidxbits = 10; ptesize = 16; pgshift = 14; break;
+ case VM_1_10_SV54:
+ levels = 4; ptidxbits = 10; ptesize = 16; pgshift = 14; break;
case VM_1_10_MBARE:
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -448,7 +466,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
CPUState *cs = env_cpu(env);
- int va_bits = PGSHIFT + levels * ptidxbits + widened;
+ int va_bits = pgshift + levels * ptidxbits + widened;
target_ulong mask, masked_msbs;
if (TARGET_LONG_BITS > (va_bits - 1)) {
@@ -463,6 +481,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
int ptshift = (levels - 1) * ptidxbits;
+ uint64_t pgoff_mask = (1ULL << pgshift) - 1;
int i;
#if !TCG_OVERSIZED_GUEST
@@ -471,10 +490,10 @@ restart:
for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
target_ulong idx;
if (i == 0) {
- idx = (addr >> (PGSHIFT + ptshift)) &
+ idx = (addr >> (pgshift + ptshift)) &
((1 << (ptidxbits + widened)) - 1);
} else {
- idx = (addr >> (PGSHIFT + ptshift)) &
+ idx = (addr >> (pgshift + ptshift)) &
((1 << ptidxbits) - 1);
}
@@ -482,6 +501,7 @@ restart:
hwaddr pte_addr;
if (two_stage && first_stage) {
+ /* TODO : Two-stage translation for RV128 */
int vbase_prot;
hwaddr vbase;
@@ -515,6 +535,10 @@ restart:
if (riscv_cpu_is_32bit(env)) {
pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
} else {
+ /*
+ * For RV128, load only lower 64 bits as only those
+ * are used for now
+ */
pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
}
@@ -529,7 +553,7 @@ restart:
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
- base = ppn << PGSHIFT;
+ base = ppn << pgshift;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
return TRANSLATE_FAIL;
@@ -601,9 +625,9 @@ restart:
/* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
- target_ulong vpn = addr >> PGSHIFT;
- *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
- (addr & ~TARGET_PAGE_MASK);
+ target_ulong vpn = addr >> pgshift;
+ *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << pgshift) |
+ (addr & pgoff_mask);
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a9146a4496..3a6bc02571 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -461,6 +461,12 @@ static const char valid_vm_1_10_64[16] = {
[VM_1_10_SV57] = 1
};
+static const bool valid_vm_1_10_128[16] = {
+ [VM_1_10_MBARE] = 1,
+ [VM_1_10_SV44] = 1,
+ [VM_1_10_SV54] = 1
+};
+
/* Machine Information Registers */
static RISCVException read_zero_i128(CPURISCVState *env, int csrno,
Int128 *val)
@@ -557,8 +563,12 @@ static int validate_vm(CPURISCVState *env, target_ulong vm)
{
if (riscv_cpu_is_32bit(env)) {
return valid_vm_1_10_32[vm & 0xf];
- } else {
+ } else if (riscv_cpu_is_64bit(env)) {
return valid_vm_1_10_64[vm & 0xf];
+ } else if (riscv_cpu_is_128bit(env)) {
+ return valid_vm_1_10_128[vm & 0xf];
+ } else {
+ return 0;
}
}
@@ -1090,6 +1100,67 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
}
/* Supervisor Protection and Translation */
+static RISCVException read_satp_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+ *val = int128_zero();
+ return RISCV_EXCP_NONE;
+ }
+
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ } else {
+ *val = int128_make128(env->satp, env->satph);
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_satp_i128(CPURISCVState *env, int csrno,
+ Int128 val)
+{
+ uint32_t asid;
+ bool vm_ok;
+ Int128 mask;
+
+ if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+ return RISCV_EXCP_NONE;
+ }
+
+ if (riscv_cpu_is_32bit(env)) {
+ vm_ok = validate_vm(env, get_field(int128_getlo(val), SATP32_MODE));
+ mask = int128_make64((int128_getlo(val) ^ env->satp)
+ & (SATP32_MODE | SATP32_ASID | SATP32_PPN));
+ asid = (int128_getlo(val) ^ env->satp) & SATP32_ASID;
+ } else if (riscv_cpu_is_64bit(env)) {
+ vm_ok = validate_vm(env, get_field(int128_getlo(val), SATP64_MODE));
+ mask = int128_make64((int128_getlo(val) ^ env->satp)
+ & (SATP64_MODE | SATP64_ASID | SATP64_PPN));
+ asid = (int128_getlo(val) ^ env->satp) & SATP64_ASID;
+ } else {
+ vm_ok = validate_vm(env, get_field(int128_gethi(val), SATP128_HMODE));
+ mask = int128_and(
+ int128_xor(val, int128_make128(env->satp, env->satph)),
+ int128_make128(SATP128_LPPN, SATP128_HMODE | SATP128_HASID));
+ asid = (int128_gethi(val) ^ env->satph) & SATP128_HASID;
+ }
+
+
+ if (vm_ok && int128_nz(mask)) {
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ } else {
+ if (asid) {
+ tlb_flush(env_cpu(env));
+ }
+ env->satp = int128_getlo(val);
+ env->satph = int128_gethi(val);
+ }
+ }
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_satp(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1624,7 +1695,7 @@ static inline RISCVException riscv_csrrw_check_i128(CPURISCVState *env,
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
int effective_priv = env->priv;
- int read_only = get_field(csrno, 0xc00) == 3;
+ int read_only = get_field(csrno, 0xC00) == 3;
if (riscv_has_ext(env, RVH) &&
env->priv == PRV_S &&
@@ -1765,7 +1836,7 @@ riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE] = {
[CSR_MSCRATCH] = { read_mscratch_i128, write_mscratch_i128 },
[CSR_MEPC] = { read_mepc_i128, write_mepc_i128 },
- [CSR_SATP] = { read_zero_i128 },
+ [CSR_SATP] = { read_satp_i128, write_satp_i128 },
#endif
};
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [PATCH v2 27/27] target/riscv: support for 128-bit satp
@ 2021-10-06 21:28 ` Frédéric Pétrot
0 siblings, 0 replies; 60+ messages in thread
From: Frédéric Pétrot @ 2021-10-06 21:28 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: alistair.francis, richard.henderson, bin.meng, philmd, palmer,
fabien.portas, Frédéric Pétrot
Support for a 128-bit satp. This is a bit more involved than necessary
because we took the opportunity to increase the page size to 16kB, and
change the page table geometry, which makes the page walk a bit more
parametrizable (variables instead of defines).
Note that is anyway a necessary step for the merging of the 32-bit and
64-bit riscv versions in a single executable.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/cpu-param.h | 9 ++++-
target/riscv/cpu_bits.h | 10 +++++
target/riscv/cpu_helper.c | 54 +++++++++++++++++++--------
target/riscv/csr.c | 77 +++++++++++++++++++++++++++++++++++++--
4 files changed, 130 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index c10459b56f..78f0916403 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -19,10 +19,15 @@
#else
/* 64-bit target, since QEMU isn't built to have TARGET_LONG_BITS over 64 */
# define TARGET_LONG_BITS 64
-# define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */
-# define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */
+# define TARGET_PHYS_ADDR_SPACE_BITS 64 /* 54-bit PPN */
+# define TARGET_VIRT_ADDR_SPACE_BITS 44 /* sv44 */
#endif
+
+#if defined(TARGET_RISCV32) || defined(TARGET_RISCV64)
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
+#else
+#define TARGET_PAGE_BITS 14 /* 16 KiB pages for RV128 */
+#endif
/*
* The current MMU Modes are:
* - U mode 0b000
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 553b0a3d71..a4f6ba927f 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -428,6 +428,11 @@
#define SATP64_ASID 0x0FFFF00000000000ULL
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
+/* RV128 satp CSR field masks (H/L for high/low dword) */
+#define SATP128_HMODE 0xFF00000000000000ULL
+#define SATP128_HASID 0x00FFFFFFFF000000ULL
+#define SATP128_LPPN 0x0003FFFFFFFFFFFFULL
+
/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
#define VM_1_09_MBARE 0
#define VM_1_09_MBB 1
@@ -443,6 +448,9 @@
#define VM_1_10_SV48 9
#define VM_1_10_SV57 10
#define VM_1_10_SV64 11
+#define VM_1_10_SV44 12
+#define VM_1_10_SV54 13
+
/* Page table entry (PTE) fields */
#define PTE_V 0x001 /* Valid */
@@ -460,6 +468,8 @@
/* Leaf page shift amount */
#define PGSHIFT 12
+/* For now, pages in RV128 are 16 KiB. */
+#define PGSHIFT128 14
/* Default Reset Vector adress */
#define DEFAULT_RSTVEC 0x1000
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d41d5cd27c..55dea1f58b 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -391,7 +391,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
*prot = 0;
hwaddr base;
- int levels, ptidxbits, ptesize, vm, sum, mxr, widened;
+ int levels, ptidxbits, ptesize, vm, sum, mxr, widened, pgshift;
if (first_stage == true) {
mxr = get_field(env->mstatus, MSTATUS_MXR);
@@ -404,17 +404,25 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
if (riscv_cpu_is_32bit(env)) {
base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->vsatp, SATP32_MODE);
- } else {
+ } else if (riscv_cpu_is_64bit(env)) {
base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
vm = get_field(env->vsatp, SATP64_MODE);
+ } else {
+ /* TODO : Hypervisor extension not supported yet in RV128. */
+ g_assert_not_reached();
}
} else {
if (riscv_cpu_is_32bit(env)) {
base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->satp, SATP32_MODE);
- } else {
+ } else if (riscv_cpu_is_64bit(env)) {
base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
vm = get_field(env->satp, SATP64_MODE);
+ } else if (riscv_cpu_is_128bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP128_LPPN) << PGSHIFT128;
+ vm = get_field(env->satph, SATP128_HMODE);
+ } else {
+ g_assert_not_reached();
}
}
widened = 0;
@@ -422,9 +430,15 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
if (riscv_cpu_is_32bit(env)) {
base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
vm = get_field(env->hgatp, SATP32_MODE);
- } else {
+ } else if (riscv_cpu_is_64bit(env)) {
base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
vm = get_field(env->hgatp, SATP64_MODE);
+ } else {
+ /*
+ * TODO : Hypervisor extension not supported yet in RV128,
+ * so there shouldn't be any two-stage address lookups.
+ */
+ g_assert_not_reached();
}
widened = 2;
}
@@ -432,13 +446,17 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
switch (vm) {
case VM_1_10_SV32:
- levels = 2; ptidxbits = 10; ptesize = 4; break;
+ levels = 2; ptidxbits = 10; ptesize = 4; pgshift = 12; break;
case VM_1_10_SV39:
- levels = 3; ptidxbits = 9; ptesize = 8; break;
+ levels = 3; ptidxbits = 9; ptesize = 8; pgshift = 12; break;
case VM_1_10_SV48:
- levels = 4; ptidxbits = 9; ptesize = 8; break;
+ levels = 4; ptidxbits = 9; ptesize = 8; pgshift = 12; break;
case VM_1_10_SV57:
- levels = 5; ptidxbits = 9; ptesize = 8; break;
+ levels = 5; ptidxbits = 9; ptesize = 8; pgshift = 12; break;
+ case VM_1_10_SV44:
+ levels = 3; ptidxbits = 10; ptesize = 16; pgshift = 14; break;
+ case VM_1_10_SV54:
+ levels = 4; ptidxbits = 10; ptesize = 16; pgshift = 14; break;
case VM_1_10_MBARE:
*physical = addr;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -448,7 +466,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
CPUState *cs = env_cpu(env);
- int va_bits = PGSHIFT + levels * ptidxbits + widened;
+ int va_bits = pgshift + levels * ptidxbits + widened;
target_ulong mask, masked_msbs;
if (TARGET_LONG_BITS > (va_bits - 1)) {
@@ -463,6 +481,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
}
int ptshift = (levels - 1) * ptidxbits;
+ uint64_t pgoff_mask = (1ULL << pgshift) - 1;
int i;
#if !TCG_OVERSIZED_GUEST
@@ -471,10 +490,10 @@ restart:
for (i = 0; i < levels; i++, ptshift -= ptidxbits) {
target_ulong idx;
if (i == 0) {
- idx = (addr >> (PGSHIFT + ptshift)) &
+ idx = (addr >> (pgshift + ptshift)) &
((1 << (ptidxbits + widened)) - 1);
} else {
- idx = (addr >> (PGSHIFT + ptshift)) &
+ idx = (addr >> (pgshift + ptshift)) &
((1 << ptidxbits) - 1);
}
@@ -482,6 +501,7 @@ restart:
hwaddr pte_addr;
if (two_stage && first_stage) {
+ /* TODO : Two-stage translation for RV128 */
int vbase_prot;
hwaddr vbase;
@@ -515,6 +535,10 @@ restart:
if (riscv_cpu_is_32bit(env)) {
pte = address_space_ldl(cs->as, pte_addr, attrs, &res);
} else {
+ /*
+ * For RV128, load only lower 64 bits as only those
+ * are used for now
+ */
pte = address_space_ldq(cs->as, pte_addr, attrs, &res);
}
@@ -529,7 +553,7 @@ restart:
return TRANSLATE_FAIL;
} else if (!(pte & (PTE_R | PTE_W | PTE_X))) {
/* Inner PTE, continue walking */
- base = ppn << PGSHIFT;
+ base = ppn << pgshift;
} else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) {
/* Reserved leaf PTE flags: PTE_W */
return TRANSLATE_FAIL;
@@ -601,9 +625,9 @@ restart:
/* for superpage mappings, make a fake leaf PTE for the TLB's
benefit. */
- target_ulong vpn = addr >> PGSHIFT;
- *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) |
- (addr & ~TARGET_PAGE_MASK);
+ target_ulong vpn = addr >> pgshift;
+ *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << pgshift) |
+ (addr & pgoff_mask);
/* set permissions on the TLB entry */
if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a9146a4496..3a6bc02571 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -461,6 +461,12 @@ static const char valid_vm_1_10_64[16] = {
[VM_1_10_SV57] = 1
};
+static const bool valid_vm_1_10_128[16] = {
+ [VM_1_10_MBARE] = 1,
+ [VM_1_10_SV44] = 1,
+ [VM_1_10_SV54] = 1
+};
+
/* Machine Information Registers */
static RISCVException read_zero_i128(CPURISCVState *env, int csrno,
Int128 *val)
@@ -557,8 +563,12 @@ static int validate_vm(CPURISCVState *env, target_ulong vm)
{
if (riscv_cpu_is_32bit(env)) {
return valid_vm_1_10_32[vm & 0xf];
- } else {
+ } else if (riscv_cpu_is_64bit(env)) {
return valid_vm_1_10_64[vm & 0xf];
+ } else if (riscv_cpu_is_128bit(env)) {
+ return valid_vm_1_10_128[vm & 0xf];
+ } else {
+ return 0;
}
}
@@ -1090,6 +1100,67 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno,
}
/* Supervisor Protection and Translation */
+static RISCVException read_satp_i128(CPURISCVState *env, int csrno,
+ Int128 *val)
+{
+ if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+ *val = int128_zero();
+ return RISCV_EXCP_NONE;
+ }
+
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ } else {
+ *val = int128_make128(env->satp, env->satph);
+ }
+
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_satp_i128(CPURISCVState *env, int csrno,
+ Int128 val)
+{
+ uint32_t asid;
+ bool vm_ok;
+ Int128 mask;
+
+ if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+ return RISCV_EXCP_NONE;
+ }
+
+ if (riscv_cpu_is_32bit(env)) {
+ vm_ok = validate_vm(env, get_field(int128_getlo(val), SATP32_MODE));
+ mask = int128_make64((int128_getlo(val) ^ env->satp)
+ & (SATP32_MODE | SATP32_ASID | SATP32_PPN));
+ asid = (int128_getlo(val) ^ env->satp) & SATP32_ASID;
+ } else if (riscv_cpu_is_64bit(env)) {
+ vm_ok = validate_vm(env, get_field(int128_getlo(val), SATP64_MODE));
+ mask = int128_make64((int128_getlo(val) ^ env->satp)
+ & (SATP64_MODE | SATP64_ASID | SATP64_PPN));
+ asid = (int128_getlo(val) ^ env->satp) & SATP64_ASID;
+ } else {
+ vm_ok = validate_vm(env, get_field(int128_gethi(val), SATP128_HMODE));
+ mask = int128_and(
+ int128_xor(val, int128_make128(env->satp, env->satph)),
+ int128_make128(SATP128_LPPN, SATP128_HMODE | SATP128_HASID));
+ asid = (int128_gethi(val) ^ env->satph) & SATP128_HASID;
+ }
+
+
+ if (vm_ok && int128_nz(mask)) {
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ } else {
+ if (asid) {
+ tlb_flush(env_cpu(env));
+ }
+ env->satp = int128_getlo(val);
+ env->satph = int128_gethi(val);
+ }
+ }
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_satp(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1624,7 +1695,7 @@ static inline RISCVException riscv_csrrw_check_i128(CPURISCVState *env,
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
int effective_priv = env->priv;
- int read_only = get_field(csrno, 0xc00) == 3;
+ int read_only = get_field(csrno, 0xC00) == 3;
if (riscv_has_ext(env, RVH) &&
env->priv == PRV_S &&
@@ -1765,7 +1836,7 @@ riscv_csr_operations128 csr_ops_128[CSR_TABLE_SIZE] = {
[CSR_MSCRATCH] = { read_mscratch_i128, write_mscratch_i128 },
[CSR_MEPC] = { read_mepc_i128, write_mepc_i128 },
- [CSR_SATP] = { read_zero_i128 },
+ [CSR_SATP] = { read_satp_i128, write_satp_i128 },
#endif
};
--
2.33.0
^ permalink raw reply related [flat|nested] 60+ messages in thread
* Re: [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-07 8:06 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 60+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-07 8:06 UTC (permalink / raw)
To: Frédéric Pétrot, qemu-devel, qemu-riscv
Cc: alistair.francis, bin.meng, richard.henderson, palmer, fabien.portas
On 10/6/21 23:28, Frédéric Pétrot wrote:
> Introducing unsigned quad, signed quad, and octo accesses types
> to handle load and store by 128-bit processors.
> This is just a small addition to Richard's patch not yet upstreamed
> https://lore.kernel.org/qemu-devel/20210818191920.390759-24-richard.henderson@linaro.org/
> Note that the patch must be applied first for the rest to compile
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> ---
> include/exec/memop.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/exec/memop.h b/include/exec/memop.h
> index 04264ffd6b..9297f58a39 100644
> --- a/include/exec/memop.h
> +++ b/include/exec/memop.h
> @@ -85,10 +85,13 @@ typedef enum MemOp {
> MO_UB = MO_8,
> MO_UW = MO_16,
> MO_UL = MO_32,
> + MO_UQ = MO_64,
> MO_SB = MO_SIGN | MO_8,
> MO_SW = MO_SIGN | MO_16,
> MO_SL = MO_SIGN | MO_32,
> + MO_SQ = MO_SIGN | MO_64,
> MO_Q = MO_64,
To avoid confusion, I'd rename MO_Q -> MO_UQ in a
previous patch, updating the repository with a simple
sed command from the shell:
$ sed -i '/MO_Q/MO_UQ' $(git grep -lw MO_Q)
> + MO_O = MO_128,
>
> MO_LEUW = MO_LE | MO_UW,
> MO_LEUL = MO_LE | MO_UL,
> @@ -105,9 +108,12 @@ typedef enum MemOp {
> #ifdef NEED_CPU_H
> MO_TEUW = MO_TE | MO_UW,
> MO_TEUL = MO_TE | MO_UL,
> + MO_TEUQ = MO_TE | MO_UQ,
> MO_TESW = MO_TE | MO_SW,
> MO_TESL = MO_TE | MO_SL,
> + MO_TESQ = MO_TE | MO_SQ,
> MO_TEQ = MO_TE | MO_Q,
> + MO_TEO = MO_TE | MO_O,
> #endif
>
> MO_SSIZE = MO_SIZE | MO_SIGN,
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values
@ 2021-10-07 8:06 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 60+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-07 8:06 UTC (permalink / raw)
To: Frédéric Pétrot, qemu-devel, qemu-riscv
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas, palmer
On 10/6/21 23:28, Frédéric Pétrot wrote:
> Introducing unsigned quad, signed quad, and octo accesses types
> to handle load and store by 128-bit processors.
> This is just a small addition to Richard's patch not yet upstreamed
> https://lore.kernel.org/qemu-devel/20210818191920.390759-24-richard.henderson@linaro.org/
> Note that the patch must be applied first for the rest to compile
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> ---
> include/exec/memop.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/exec/memop.h b/include/exec/memop.h
> index 04264ffd6b..9297f58a39 100644
> --- a/include/exec/memop.h
> +++ b/include/exec/memop.h
> @@ -85,10 +85,13 @@ typedef enum MemOp {
> MO_UB = MO_8,
> MO_UW = MO_16,
> MO_UL = MO_32,
> + MO_UQ = MO_64,
> MO_SB = MO_SIGN | MO_8,
> MO_SW = MO_SIGN | MO_16,
> MO_SL = MO_SIGN | MO_32,
> + MO_SQ = MO_SIGN | MO_64,
> MO_Q = MO_64,
To avoid confusion, I'd rename MO_Q -> MO_UQ in a
previous patch, updating the repository with a simple
sed command from the shell:
$ sed -i '/MO_Q/MO_UQ' $(git grep -lw MO_Q)
> + MO_O = MO_128,
>
> MO_LEUW = MO_LE | MO_UW,
> MO_LEUL = MO_LE | MO_UL,
> @@ -105,9 +108,12 @@ typedef enum MemOp {
> #ifdef NEED_CPU_H
> MO_TEUW = MO_TE | MO_UW,
> MO_TEUL = MO_TE | MO_UL,
> + MO_TEUQ = MO_TE | MO_UQ,
> MO_TESW = MO_TE | MO_SW,
> MO_TESL = MO_TE | MO_SL,
> + MO_TESQ = MO_TE | MO_SQ,
> MO_TEQ = MO_TE | MO_Q,
> + MO_TEO = MO_TE | MO_O,
> #endif
>
> MO_SSIZE = MO_SIZE | MO_SIGN,
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v2 00/27] Adding partial support for 128-bit riscv target
2021-10-06 21:28 ` Frédéric Pétrot
@ 2021-10-07 8:11 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 60+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-07 8:11 UTC (permalink / raw)
To: Frédéric Pétrot, qemu-devel, qemu-riscv, Alex Bennée
Cc: alistair.francis, bin.meng, richard.henderson, palmer, fabien.portas
On 10/6/21 23:28, Frédéric Pétrot wrote:
> This series of patches provides partial 128-bit support for the riscv
> target architecture.
> For the 128-bit, the tests are there: https://github.com/fpetrot/128-test
> * from hash 925e1af2c7, run the tests in unit_test_i
> * from hash 6d4a39f2c4, run in addition the tests in unit_test_m
> * from hash 864e563916, run in addition the tests unit_test_csr
It would be very helpful to integrate those tests in our suite,
to catch future regressions.
The usual process is:
- Add a submodule
- Add buildsys machinery to call your tests manually
- Add a GitLab job automatically running the tests
Note however we already have too many submodules, so there
might be a simpler alternative.
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [PATCH v2 00/27] Adding partial support for 128-bit riscv target
@ 2021-10-07 8:11 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 60+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-07 8:11 UTC (permalink / raw)
To: Frédéric Pétrot, qemu-devel, qemu-riscv, Alex Bennée
Cc: bin.meng, richard.henderson, alistair.francis, fabien.portas, palmer
On 10/6/21 23:28, Frédéric Pétrot wrote:
> This series of patches provides partial 128-bit support for the riscv
> target architecture.
> For the 128-bit, the tests are there: https://github.com/fpetrot/128-test
> * from hash 925e1af2c7, run the tests in unit_test_i
> * from hash 6d4a39f2c4, run in addition the tests in unit_test_m
> * from hash 864e563916, run in addition the tests unit_test_csr
It would be very helpful to integrate those tests in our suite,
to catch future regressions.
The usual process is:
- Add a submodule
- Add buildsys machinery to call your tests manually
- Add a GitLab job automatically running the tests
Note however we already have too many submodules, so there
might be a simpler alternative.
^ permalink raw reply [flat|nested] 60+ messages in thread
end of thread, other threads:[~2021-10-07 8:12 UTC | newest]
Thread overview: 60+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-06 21:28 [PATCH v2 00/27] Adding partial support for 128-bit riscv target Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-07 8:06 ` Philippe Mathieu-Daudé
2021-10-07 8:06 ` Philippe Mathieu-Daudé
2021-10-06 21:28 ` [PATCH v2 02/27] Int128.h: addition of a few 128-bit operations Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 03/27] target/riscv: adding upper 64 bits for misa Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 04/27] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 05/27] target/riscv: additional macros to check instruction support Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 07/27] target/riscv: refactoring calls to gen_arith Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 08/27] target/riscv: refactoring calls to gen_shift Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 10/27] target/riscv: adding accessors to the registers upper part Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 12/27] target/riscv: moving some insns close to similar insns Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 13/27] target/riscv: rename a few gen function helpers Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 14/27] target/riscv: 128-bit support for instructions using gen_arith/gen_logic Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 15/27] target/riscv: 128-bit support for instructions using gen_shift Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 16/27] target/riscv: support for 128-bit loads and store Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 17/27] target/riscv: 128-bit double word integer arithmetic instructions Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 18/27] target/riscv: 128-bit double word integer shift instructions Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 19/27] target/riscv: support for 128-bit base multiplications insns Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 20/27] target/riscv: addition of the 'd' insns for 128-bit mult/div/rem Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 21/27] target/riscv: div and rem insns on 128-bit Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 22/27] target/riscv: adding high part of some csrs Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 23/27] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 24/27] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 25/27] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 26/27] target/riscv: adding 128-bit access functions for some csrs Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-06 21:28 ` [PATCH v2 27/27] target/riscv: support for 128-bit satp Frédéric Pétrot
2021-10-06 21:28 ` Frédéric Pétrot
2021-10-07 8:11 ` [PATCH v2 00/27] Adding partial support for 128-bit riscv target Philippe Mathieu-Daudé
2021-10-07 8:11 ` Philippe Mathieu-Daudé
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