[PATCH v5 0/3] CXL XOR Interleave Arithmetic

[PATCH v5 0/3] CXL XOR Interleave Arithmetic

[alison.schofield]

From: Alison Schofield <alison.schofield@intel.com>

Changes in v5:
- Add to 'n' for 6 & 12 way. (v3->v4 broke it)
- Clean up x3 index init. (Dan)
- Remove unneeded HB's from cxl_test topology.
- Remove dependency on stale patch in cxl_test.

Changes in v4:
- Use GENMASK_ULL to fix i386 arch build (0-day)
- Use do_div to fix ARM arch build (0-day)
- Update comments in ACPICA patch to reflect new state of the
  ACPICA patch - pending again in github.

Changes in v3:
- Fix the 3, 6, 12 way interleave (again).
- Do not look for a CXIMS when not needed for x1 & x3 interleaves
- New cxl_test patch: Add cxl_test module support for this feature
- In a separate ndctl patch, cxl test: cxl_xor_region is added

Changes in v2:
- Use ilog2() of the decoded interleave ways to determine number
  of xormaps, instead of using encoded ways directly. This fixes
  3, 6, and 12 way interleaves. (Dan)

Add support for the new 'XOR' Interleave Arithmetic as defined
in the CXL 3.0 Specification:
https://www.computeexpresslink.org/download-the-specification


Alison Schofield (2):
  For ACPICA: Add the CXIMS structure definition to the CEDT table
  cxl/acpi: Support CXL XOR Interleave Math (CXIMS)
  tools/testing/cxl: Add XOR Math support to cxl_test

 drivers/cxl/acpi.c           | 129 +++++++++++++++++++++++++++++++++--
 drivers/cxl/cxl.h            |   2 +
 include/acpi/actbl1.h        |  14 +++-
 tools/testing/cxl/test/cxl.c | 118 +++++++++++++++++++++++++++++++-
 4 files changed, 254 insertions(+), 9 deletions(-)

-- 
2.37.3

[PATCH v5 1/3] For ACPICA: Add the CXIMS structure definition to the CEDT table

[alison.schofield]

From: Alison Schofield <alison.schofield@intel.com>

A linux-ized ACPI patch is included here for reference. The ACPI
pull request has been merged and we expect the upstream version
shortly. https://github.com/acpica/acpica/pull/795

The CXL XOR Interleave Math Structure (CXIMS) is added to the
CXL Early Discovery Table (CEDT). This new structure is defined
in the CXL 3.0 specification Section 9.17.1.4

https://www.computeexpresslink.org/spec-landing

Signed-off-by: Alison Schofield <alison.schofield@intel.com>
---
 include/acpi/actbl1.h | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 15c78678c5d3..f96f4fe5328d 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -329,7 +329,8 @@ struct acpi_cedt_header {
 enum acpi_cedt_type {
 	ACPI_CEDT_TYPE_CHBS = 0,
 	ACPI_CEDT_TYPE_CFMWS = 1,
-	ACPI_CEDT_TYPE_RESERVED = 2,
+	ACPI_CEDT_TYPE_CXIMS = 2,
+	ACPI_CEDT_TYPE_RESERVED = 3,
 };
 
 /* Values for version field above */
@@ -380,6 +381,7 @@ struct acpi_cedt_cfmws_target_element {
 /* Values for Interleave Arithmetic field above */
 
 #define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO   (0)
+#define ACPI_CEDT_CFMWS_ARITHMETIC_XOR	    (1)
 
 /* Values for Restrictions field above */
 
@@ -389,6 +391,16 @@ struct acpi_cedt_cfmws_target_element {
 #define ACPI_CEDT_CFMWS_RESTRICT_PMEM       (1<<3)
 #define ACPI_CEDT_CFMWS_RESTRICT_FIXED      (1<<4)
 
+/* 2: CXL XOR Interleave Math Structure */
+
+struct acpi_cedt_cxims {
+	struct acpi_cedt_header header;
+	u16 reserved1;
+	u8 hbig;
+	u8 nr_xormaps;
+	u64 xormap_list[];
+};
+
 /*******************************************************************************
  *
  * CPEP - Corrected Platform Error Polling table (ACPI 4.0)
-- 
2.37.3

[PATCH v5 2/3] cxl/acpi: Support CXL XOR Interleave Math (CXIMS)

[alison.schofield]

From: Alison Schofield <alison.schofield@intel.com>

When the CFMWS is using XOR math, parse the corresponding
CXIMS structure and store the xormaps in the root decoder
structure. Use the xormaps in a new lookup, cxl_hb_xor(),
to find a targets entry in the host bridge interleave
target list.

Defined in CXL Specfication 3.0 Section: 9.17.1

Signed-off-by: Alison Schofield <alison.schofield@intel.com>
---
 drivers/cxl/acpi.c | 129 +++++++++++++++++++++++++++++++++++++++++++--
 drivers/cxl/cxl.h  |   2 +
 2 files changed, 126 insertions(+), 5 deletions(-)

diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c
index fb649683dd3a..1211c31c29d2 100644
--- a/drivers/cxl/acpi.c
+++ b/drivers/cxl/acpi.c
@@ -6,9 +6,106 @@
 #include <linux/kernel.h>
 #include <linux/acpi.h>
 #include <linux/pci.h>
+#include <asm/div64.h>
 #include "cxlpci.h"
 #include "cxl.h"
 
+struct cxims_data {
+	int nr_maps;
+	u64 xormaps[];
+};
+
+/*
+ * Find a targets entry (n) in the host bridge interleave list.
+ * CXL Specfication 3.0 Table 9-22
+ */
+static struct cxl_dport *cxl_hb_xor(struct cxl_root_decoder *cxlrd, int pos)
+{
+	struct cxl_switch_decoder *cxlsd = &cxlrd->cxlsd;
+	struct cxims_data *cximsd = cxlrd->platform_data;
+	struct cxl_decoder *cxld = &cxlsd->cxld;
+	int ig = cxld->interleave_granularity;
+	int iw = cxld->interleave_ways;
+	int eiw, i = 0, n = 0;
+	u64 hpa;
+
+	if (dev_WARN_ONCE(&cxld->dev,
+			  cxld->interleave_ways != cxlsd->nr_targets,
+			  "misconfigured root decoder\n"))
+		return NULL;
+
+	if (iw == 1)
+		/* Entry is always 0 for no interleave */
+		return cxlrd->cxlsd.target[0];
+
+	hpa = cxlrd->res->start + pos * ig;
+
+	if (iw == 3)
+		goto no_map;
+
+	/* IW: 2,4,6,8,12,16 begin building 'n' using xormaps */
+	for (i = 0; i < cximsd->nr_maps; i++)
+		n |= (hweight64(hpa & cximsd->xormaps[i]) & 1) << i;
+
+no_map:
+	/* IW: 3,6,12 add a modulo calculation to 'n' */
+	if (!is_power_of_2(iw)) {
+		eiw = ilog2(iw / 3) + 8;
+		hpa &= GENMASK_ULL(51, eiw + ig);
+		n |= do_div(hpa, 3) << i;
+	}
+	return cxlrd->cxlsd.target[n];
+}
+
+struct cxl_cxims_context {
+	struct device *dev;
+	struct cxl_root_decoder *cxlrd;
+};
+
+static int cxl_parse_cxims(union acpi_subtable_headers *header, void *arg,
+			   const unsigned long end)
+{
+	struct acpi_cedt_cxims *cxims = (struct acpi_cedt_cxims *)header;
+	struct cxl_cxims_context *ctx = arg;
+	struct cxl_root_decoder *cxlrd = ctx->cxlrd;
+	struct cxl_decoder *cxld = &cxlrd->cxlsd.cxld;
+	struct device *dev = ctx->dev;
+	struct cxims_data *cximsd;
+	unsigned int hbig, nr_maps;
+	int rc;
+
+	rc = cxl_to_granularity(cxims->hbig, &hbig);
+	if (rc)
+		return rc;
+
+	if (hbig == cxld->interleave_granularity) {
+		/* IW 1,3 do not use xormaps and skip this parsing entirely */
+
+		if (is_power_of_2(cxld->interleave_ways))
+			/* 2, 4, 8, 16 way */
+			nr_maps = ilog2(cxld->interleave_ways);
+		else
+			/* 6, 12 way */
+			nr_maps = ilog2(cxld->interleave_ways / 3);
+
+		if (cxims->nr_xormaps < nr_maps) {
+			dev_dbg(dev, "CXIMS nr_xormaps[%d] expected[%d]\n",
+				cxims->nr_xormaps, nr_maps);
+			return -ENXIO;
+		}
+
+		cximsd = devm_kzalloc(dev,
+				      struct_size(cximsd, xormaps, nr_maps),
+				      GFP_KERNEL);
+		memcpy(cximsd->xormaps, cxims->xormap_list,
+		       nr_maps * sizeof(*cximsd->xormaps));
+		cximsd->nr_maps = nr_maps;
+		cxlrd->platform_data = cximsd;
+		cxlrd->calc_hb = cxl_hb_xor;
+	}
+	return 0;
+}
+
 static unsigned long cfmws_to_decoder_flags(int restrictions)
 {
 	unsigned long flags = CXL_DECODER_F_ENABLE;
@@ -33,11 +130,6 @@ static int cxl_acpi_cfmws_verify(struct device *dev,
 	int rc, expected_len;
 	unsigned int ways;
 
-	if (cfmws->interleave_arithmetic != ACPI_CEDT_CFMWS_ARITHMETIC_MODULO) {
-		dev_err(dev, "CFMWS Unsupported Interleave Arithmetic\n");
-		return -EINVAL;
-	}
-
 	if (!IS_ALIGNED(cfmws->base_hpa, SZ_256M)) {
 		dev_err(dev, "CFMWS Base HPA not 256MB aligned\n");
 		return -EINVAL;
@@ -84,6 +176,7 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
 	struct cxl_cfmws_context *ctx = arg;
 	struct cxl_port *root_port = ctx->root_port;
 	struct resource *cxl_res = ctx->cxl_res;
+	struct cxl_cxims_context cxims_ctx;
 	struct cxl_root_decoder *cxlrd;
 	struct device *dev = ctx->dev;
 	struct acpi_cedt_cfmws *cfmws;
@@ -148,7 +241,33 @@ static int cxl_parse_cfmws(union acpi_subtable_headers *header, void *arg,
 		ig = CXL_DECODER_MIN_GRANULARITY;
 	cxld->interleave_granularity = ig;
 
+	if (cfmws->interleave_arithmetic == ACPI_CEDT_CFMWS_ARITHMETIC_XOR) {
+		if (ways == 1 || ways == 3)	{
+			/* Skip CXIMS parsing for IW 1 or 3. No xormaps used */
+			cxlrd->calc_hb = cxl_hb_xor;
+			goto decoder_add;
+		}
+
+		cxims_ctx = (struct cxl_cxims_context) {
+			.dev = dev,
+			.cxlrd = cxlrd,
+		};
+
+		rc = acpi_table_parse_cedt(ACPI_CEDT_TYPE_CXIMS,
+					   cxl_parse_cxims, &cxims_ctx);
+		if (rc < 0)
+			goto err_xormap;
+
+		if (cxlrd->calc_hb != cxl_hb_xor) {
+			rc = -ENXIO;
+			goto err_xormap;
+		}
+	}
+
+decoder_add:
 	rc = cxl_decoder_add(cxld, target_map);
+
+err_xormap:
 	if (rc)
 		put_device(&cxld->dev);
 	else
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index f680450f0b16..0a17a7007bff 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -330,12 +330,14 @@ struct cxl_switch_decoder {
  * @res: host / parent resource for region allocations
  * @region_id: region id for next region provisioning event
  * @calc_hb: which host bridge covers the n'th position by granularity
+ * @platform_data: platform specific configuration data
  * @cxlsd: base cxl switch decoder
  */
 struct cxl_root_decoder {
 	struct resource *res;
 	atomic_t region_id;
 	struct cxl_dport *(*calc_hb)(struct cxl_root_decoder *cxlrd, int pos);
+	void *platform_data;
 	struct cxl_switch_decoder cxlsd;
 };
 
-- 
2.37.3

[PATCH v5 3/3] tools/testing/cxl: Add XOR Math support to cxl_test

[alison.schofield]

From: Alison Schofield <alison.schofield@intel.com>

Expand the cxl_test topology to include CFMWS's that use XOR math
for interleave arithmetic, as defined in the CXL Specification 3.0.

With this expanded topology, cxl_test is useful for testing
x1,x2,x4 ways with XOR interleave arithmetic.

Define the additional XOR CFMWS entries to appear only with the
module parameter interleave_arithmetic=1. The cxl_test default
continues to be modulo math.

modprobe cxl_test interleave_arithmetic=1

Signed-off-by: Alison Schofield <alison.schofield@intel.com>
---
 tools/testing/cxl/test/cxl.c | 118 ++++++++++++++++++++++++++++++++++-
 1 file changed, 115 insertions(+), 3 deletions(-)

diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c
index a072b2d3e726..82f349cf84f5 100644
--- a/tools/testing/cxl/test/cxl.c
+++ b/tools/testing/cxl/test/cxl.c
@@ -11,6 +11,8 @@
 #include <cxlmem.h>
 #include "mock.h"
 
+static int interleave_arithmetic;
+
 #define NR_CXL_HOST_BRIDGES 2
 #define NR_CXL_ROOT_PORTS 2
 #define NR_CXL_SWITCH_PORTS 2
@@ -83,6 +85,22 @@ static struct {
 		struct acpi_cedt_cfmws cfmws;
 		u32 target[2];
 	} cfmws3;
+	struct {
+		struct acpi_cedt_cfmws cfmws;
+		u32 target[1];
+	} cfmws4;
+	struct {
+		struct acpi_cedt_cfmws cfmws;
+		u32 target[2];
+	} cfmws5;
+	struct {
+		struct acpi_cedt_cfmws cfmws;
+		u32 target[4];
+	} cfmws6;
+	struct {
+		struct acpi_cedt_cxims cxims;
+		u64 xormap_list[2];
+	} cxims0;
 } __packed mock_cedt = {
 	.cedt = {
 		.header = {
@@ -167,13 +185,88 @@ static struct {
 		},
 		.target = { 0, 1, },
 	},
+	/* .cfmws4,5,6 use XOR Math (interleave_arithmetic == 1) */
+	.cfmws4 = {
+		.cfmws = {
+			.header = {
+				.type = ACPI_CEDT_TYPE_CFMWS,
+				.length = sizeof(mock_cedt.cfmws4),
+			},
+			.interleave_arithmetic = 1,
+			.interleave_ways = 0,
+			.granularity = 4,
+			.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
+					ACPI_CEDT_CFMWS_RESTRICT_PMEM,
+			.qtg_id = 0,
+			.window_size = SZ_256M * 4UL,
+		},
+		.target = { 0 },
+	},
+	.cfmws5 = {
+		.cfmws = {
+			.header = {
+				.type = ACPI_CEDT_TYPE_CFMWS,
+				.length = sizeof(mock_cedt.cfmws5),
+			},
+			.interleave_arithmetic = 1,
+			.interleave_ways = 1,
+			.granularity = 0,
+			.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
+					ACPI_CEDT_CFMWS_RESTRICT_PMEM,
+			.qtg_id = 1,
+			.window_size = SZ_256M * 8UL,
+		},
+		.target = { 0, 1, },
+	},
+	.cfmws6 = {
+		.cfmws = {
+			.header = {
+				.type = ACPI_CEDT_TYPE_CFMWS,
+				.length = sizeof(mock_cedt.cfmws6),
+			},
+			.interleave_arithmetic = 1,
+			.interleave_ways = 2,
+			.granularity = 0,
+			.restrictions = ACPI_CEDT_CFMWS_RESTRICT_TYPE3 |
+					ACPI_CEDT_CFMWS_RESTRICT_PMEM,
+			.qtg_id = 0,
+			.window_size = SZ_256M * 16UL,
+		},
+		.target = { 0, 1, 0, 1, },
+	},
+	.cxims0 = {
+		.cxims = {
+			.header = {
+				.type = ACPI_CEDT_TYPE_CXIMS,
+				.length = sizeof(mock_cedt.cxims0),
+			},
+			.hbig = 0,
+			.nr_xormaps = 2,
+		},
+		.xormap_list = { 0x404100, 0x808200 },
+	},
 };
 
-struct acpi_cedt_cfmws *mock_cfmws[4] = {
+struct acpi_cedt_cfmws *mock_cfmws[7] = {
 	[0] = &mock_cedt.cfmws0.cfmws,
 	[1] = &mock_cedt.cfmws1.cfmws,
 	[2] = &mock_cedt.cfmws2.cfmws,
 	[3] = &mock_cedt.cfmws3.cfmws,
+	/* Modulo Math above, XOR Math below */
+	[4] = &mock_cedt.cfmws4.cfmws,
+	[5] = &mock_cedt.cfmws5.cfmws,
+	[6] = &mock_cedt.cfmws6.cfmws,
+};
+
+static int cfmws_start;
+static int cfmws_end;
+#define CFMWS_MOD_ARRAY_START 0
+#define CFMWS_MOD_ARRAY_END   3
+#define CFMWS_XOR_ARRAY_START 4
+#define CFMWS_XOR_ARRAY_END   6
+
+struct acpi_cedt_cxims *mock_cxims[1] = {
+	[0] = &mock_cedt.cxims0.cxims,
 };
 
 struct cxl_mock_res {
@@ -245,7 +338,7 @@ static int populate_cedt(void)
 		chbs->length = size;
 	}
 
-	for (i = 0; i < ARRAY_SIZE(mock_cfmws); i++) {
+	for (i = cfmws_start; i <= cfmws_end; i++) {
 		struct acpi_cedt_cfmws *window = mock_cfmws[i];
 
 		res = alloc_mock_res(window->window_size);
@@ -288,12 +381,19 @@ static int mock_acpi_table_parse_cedt(enum acpi_cedt_type id,
 		}
 
 	if (id == ACPI_CEDT_TYPE_CFMWS)
-		for (i = 0; i < ARRAY_SIZE(mock_cfmws); i++) {
+		for (i = cfmws_start; i <= cfmws_end; i++) {
 			h = (union acpi_subtable_headers *) mock_cfmws[i];
 			end = (unsigned long) h + mock_cfmws[i]->header.length;
 			handler_arg(h, arg, end);
 		}
 
+	if (id == ACPI_CEDT_TYPE_CXIMS)
+		for (i = 0; i < ARRAY_SIZE(mock_cxims); i++) {
+			h = (union acpi_subtable_headers *)mock_cxims[i];
+			end = (unsigned long)h + mock_cxims[i]->header.length;
+			handler_arg(h, arg, end);
+		}
+
 	return 0;
 }
 
@@ -644,6 +744,16 @@ static __init int cxl_test_init(void)
 	if (rc)
 		goto err_gen_pool_add;
 
+	if (interleave_arithmetic == 1) {
+		cfmws_start = CFMWS_XOR_ARRAY_START;
+		cfmws_end = CFMWS_XOR_ARRAY_END;
+		dev_dbg(NULL, "cxl_test loading xor math option\n");
+	} else {
+		cfmws_start = CFMWS_MOD_ARRAY_START;
+		cfmws_end = CFMWS_MOD_ARRAY_END;
+		dev_dbg(NULL, "cxl_test loading modulo math option\n");
+	}
+
 	rc = populate_cedt();
 	if (rc)
 		goto err_populate;
@@ -814,6 +924,8 @@ static __exit void cxl_test_exit(void)
 	unregister_cxl_mock_ops(&cxl_mock_ops);
 }
 
+module_param(interleave_arithmetic, int, 0000);
+MODULE_PARM_DESC(interleave_arithmetic, "Modulo:0, XOR:1");
 module_init(cxl_test_init);
 module_exit(cxl_test_exit);
 MODULE_LICENSE("GPL v2");
-- 
2.37.3

Re: [PATCH v5 0/3] CXL XOR Interleave Arithmetic

[Alison Schofield]

On Wed, Oct 26, 2022 at 09:07:40PM -0700, alison.schofield@intel.com wrote:
> From: Alison Schofield <alison.schofield@intel.com>
> 
> Changes in v5:

  - Rebase to 6.1-rc2

> - Add to 'n' for 6 & 12 way. (v3->v4 broke it)
> - Clean up x3 index init. (Dan)
> - Remove unneeded HB's from cxl_test topology.
> - Remove dependency on stale patch in cxl_test.
> 
> Changes in v4:
> - Use GENMASK_ULL to fix i386 arch build (0-day)
> - Use do_div to fix ARM arch build (0-day)
> - Update comments in ACPICA patch to reflect new state of the
>   ACPICA patch - pending again in github.
> 
> Changes in v3:
> - Fix the 3, 6, 12 way interleave (again).
> - Do not look for a CXIMS when not needed for x1 & x3 interleaves
> - New cxl_test patch: Add cxl_test module support for this feature
> - In a separate ndctl patch, cxl test: cxl_xor_region is added
> 
> Changes in v2:
> - Use ilog2() of the decoded interleave ways to determine number
>   of xormaps, instead of using encoded ways directly. This fixes
>   3, 6, and 12 way interleaves. (Dan)
> 
> Add support for the new 'XOR' Interleave Arithmetic as defined
> in the CXL 3.0 Specification:
> https://www.computeexpresslink.org/download-the-specification
> 
> 
> Alison Schofield (2):
>   For ACPICA: Add the CXIMS structure definition to the CEDT table
>   cxl/acpi: Support CXL XOR Interleave Math (CXIMS)
>   tools/testing/cxl: Add XOR Math support to cxl_test
> 
>  drivers/cxl/acpi.c           | 129 +++++++++++++++++++++++++++++++++--
>  drivers/cxl/cxl.h            |   2 +
>  include/acpi/actbl1.h        |  14 +++-
>  tools/testing/cxl/test/cxl.c | 118 +++++++++++++++++++++++++++++++-
>  4 files changed, 254 insertions(+), 9 deletions(-)
> 
> -- 
> 2.37.3
> 

Re: [PATCH v5 1/3] For ACPICA: Add the CXIMS structure definition to the CEDT table

[Jonathan Cameron]

On Wed, 26 Oct 2022 21:07:41 -0700
alison.schofield@intel.com wrote:

> From: Alison Schofield <alison.schofield@intel.com>
> 
> A linux-ized ACPI patch is included here for reference. The ACPI
> pull request has been merged and we expect the upstream version
> shortly. https://github.com/acpica/acpica/pull/795
> 
> The CXL XOR Interleave Math Structure (CXIMS) is added to the
> CXL Early Discovery Table (CEDT). This new structure is defined
> in the CXL 3.0 specification Section 9.17.1.4
> 
> https://www.computeexpresslink.org/spec-landing
> 
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
One trivial comment.

Checked against spec and lgtm

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

> ---
>  include/acpi/actbl1.h | 14 +++++++++++++-
>  1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
> index 15c78678c5d3..f96f4fe5328d 100644
> --- a/include/acpi/actbl1.h
> +++ b/include/acpi/actbl1.h
> @@ -329,7 +329,8 @@ struct acpi_cedt_header {
>  enum acpi_cedt_type {
>  	ACPI_CEDT_TYPE_CHBS = 0,
>  	ACPI_CEDT_TYPE_CFMWS = 1,
> -	ACPI_CEDT_TYPE_RESERVED = 2,
> +	ACPI_CEDT_TYPE_CXIMS = 2,
> +	ACPI_CEDT_TYPE_RESERVED = 3,

Whilst I struggle to see the point of this RESERVED DEFINE it's almost in keeping
with other similar definitions.  However they do have comments to say
that /* 3 and greater are reserved */ and the comma isn't present
as these are guaranteed to be last element.  Probably want to do the same.

>  };
>  
>  /* Values for version field above */
> @@ -380,6 +381,7 @@ struct acpi_cedt_cfmws_target_element {
>  /* Values for Interleave Arithmetic field above */
>  
>  #define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO   (0)
> +#define ACPI_CEDT_CFMWS_ARITHMETIC_XOR	    (1)
>  
>  /* Values for Restrictions field above */
>  
> @@ -389,6 +391,16 @@ struct acpi_cedt_cfmws_target_element {
>  #define ACPI_CEDT_CFMWS_RESTRICT_PMEM       (1<<3)
>  #define ACPI_CEDT_CFMWS_RESTRICT_FIXED      (1<<4)
>  
> +/* 2: CXL XOR Interleave Math Structure */
> +
> +struct acpi_cedt_cxims {
> +	struct acpi_cedt_header header;
> +	u16 reserved1;
> +	u8 hbig;
> +	u8 nr_xormaps;
> +	u64 xormap_list[];
> +};
> +
>  /*******************************************************************************
>   *
>   * CPEP - Corrected Platform Error Polling table (ACPI 4.0)

Re: [PATCH v5 1/3] For ACPICA: Add the CXIMS structure definition to the CEDT table

[Alison Schofield]

On Thu, Nov 03, 2022 at 06:02:48PM +0000, Jonathan Cameron wrote:
> On Wed, 26 Oct 2022 21:07:41 -0700
> alison.schofield@intel.com wrote:
> 
> > From: Alison Schofield <alison.schofield@intel.com>
> > 
> > A linux-ized ACPI patch is included here for reference. The ACPI
> > pull request has been merged and we expect the upstream version
> > shortly. https://github.com/acpica/acpica/pull/795
> > 
> > The CXL XOR Interleave Math Structure (CXIMS) is added to the
> > CXL Early Discovery Table (CEDT). This new structure is defined
> > in the CXL 3.0 specification Section 9.17.1.4
> > 
> > https://www.computeexpresslink.org/spec-landing
> > 
> > Signed-off-by: Alison Schofield <alison.schofield@intel.com>
> One trivial comment.
> 
> Checked against spec and lgtm
> 
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> > ---
> >  include/acpi/actbl1.h | 14 +++++++++++++-
> >  1 file changed, 13 insertions(+), 1 deletion(-)
> > 
> > diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
> > index 15c78678c5d3..f96f4fe5328d 100644
> > --- a/include/acpi/actbl1.h
> > +++ b/include/acpi/actbl1.h
> > @@ -329,7 +329,8 @@ struct acpi_cedt_header {
> >  enum acpi_cedt_type {
> >  	ACPI_CEDT_TYPE_CHBS = 0,
> >  	ACPI_CEDT_TYPE_CFMWS = 1,
> > -	ACPI_CEDT_TYPE_RESERVED = 2,
> > +	ACPI_CEDT_TYPE_CXIMS = 2,
> > +	ACPI_CEDT_TYPE_RESERVED = 3,
> 
> Whilst I struggle to see the point of this RESERVED DEFINE it's almost in keeping
> with other similar definitions.  However they do have comments to say
> that /* 3 and greater are reserved */ and the comma isn't present
> as these are guaranteed to be last element.  Probably want to do the same.

Thanks Jonathan,

I see what you mean (now).
I think my best option here is to submit a separate (new) pull request to
ACPICA for the cleanup: remove comma and add comment.

FYI - The actual linuxized version of this patch, which grew to include
RDPAS is now available here:

https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git/commit/?h=bleeding-edge&id=f350c68e3cd5ce605e44c7830029cd936a223f66

and was previously posted to linux-cxl as:
https://lore.kernel.org/linux-cxl/20220916232102.673102-1-alison.schofield@intel.com/

Alison

> 
> >  };
> >  
> >  /* Values for version field above */
> > @@ -380,6 +381,7 @@ struct acpi_cedt_cfmws_target_element {
> >  /* Values for Interleave Arithmetic field above */
> >  
> >  #define ACPI_CEDT_CFMWS_ARITHMETIC_MODULO   (0)
> > +#define ACPI_CEDT_CFMWS_ARITHMETIC_XOR	    (1)
> >  
> >  /* Values for Restrictions field above */
> >  
> > @@ -389,6 +391,16 @@ struct acpi_cedt_cfmws_target_element {
> >  #define ACPI_CEDT_CFMWS_RESTRICT_PMEM       (1<<3)
> >  #define ACPI_CEDT_CFMWS_RESTRICT_FIXED      (1<<4)
> >  
> > +/* 2: CXL XOR Interleave Math Structure */
> > +
> > +struct acpi_cedt_cxims {
> > +	struct acpi_cedt_header header;
> > +	u16 reserved1;
> > +	u8 hbig;
> > +	u8 nr_xormaps;
> > +	u64 xormap_list[];
> > +};
> > +
> >  /*******************************************************************************
> >   *
> >   * CPEP - Corrected Platform Error Polling table (ACPI 4.0)
>