* [PATCH] target/riscv/pmp: Raise exception if no PMP entry is configured
@ 2020-12-23 1:21 ` Atish Patra
0 siblings, 0 replies; 6+ messages in thread
From: Atish Patra @ 2020-12-23 1:21 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Anup Patel, Atish Patra,
Alistair Francis, Palmer Dabbelt
As per the privilege specification, any access from S/U mode should fail
if no pmp region is configured.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/op_helper.c | 5 +++++
target/riscv/pmp.c | 4 ++--
target/riscv/pmp.h | 1 +
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index d55def76cffd..1eddcb94de7e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -150,6 +150,11 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
uint64_t mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
+
+ if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
+
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
mstatus = set_field(mstatus, MSTATUS_MIE,
get_field(mstatus, MSTATUS_MPIE));
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 2eda8e1e2f07..fbc4073fb359 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -74,7 +74,7 @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
/*
* Count the number of active rules.
*/
-static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
+inline uint32_t pmp_get_num_rules(CPURISCVState *env)
{
return env->pmp_state.num_rules;
}
@@ -237,7 +237,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
- return true;
+ return (env->priv == PRV_M) ? true : false;
}
if (size == 0) {
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 6c6b4c9befe8..c8d5ef4a694e 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -64,5 +64,6 @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
target_ulong *tlb_size);
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
void pmp_update_rule_nums(CPURISCVState *env);
+uint32_t pmp_get_num_rules(CPURISCVState *env);
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] target/riscv/pmp: Raise exception if no PMP entry is configured
@ 2020-12-23 1:21 ` Atish Patra
0 siblings, 0 replies; 6+ messages in thread
From: Atish Patra @ 2020-12-23 1:21 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Atish Patra, Alistair Francis, Bastian Koppelmann,
Palmer Dabbelt, Sagar Karandikar, Anup Patel
As per the privilege specification, any access from S/U mode should fail
if no pmp region is configured.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/op_helper.c | 5 +++++
target/riscv/pmp.c | 4 ++--
target/riscv/pmp.h | 1 +
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index d55def76cffd..1eddcb94de7e 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -150,6 +150,11 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
uint64_t mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
+
+ if (!pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
+ riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
+
target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV);
mstatus = set_field(mstatus, MSTATUS_MIE,
get_field(mstatus, MSTATUS_MPIE));
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 2eda8e1e2f07..fbc4073fb359 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -74,7 +74,7 @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
/*
* Count the number of active rules.
*/
-static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
+inline uint32_t pmp_get_num_rules(CPURISCVState *env)
{
return env->pmp_state.num_rules;
}
@@ -237,7 +237,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
/* Short cut if no rules */
if (0 == pmp_get_num_rules(env)) {
- return true;
+ return (env->priv == PRV_M) ? true : false;
}
if (size == 0) {
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 6c6b4c9befe8..c8d5ef4a694e 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -64,5 +64,6 @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
target_ulong *tlb_size);
void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
void pmp_update_rule_nums(CPURISCVState *env);
+uint32_t pmp_get_num_rules(CPURISCVState *env);
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv/pmp: Raise exception if no PMP entry is configured
2020-12-23 1:21 ` Atish Patra
@ 2020-12-23 2:49 ` Richard Henderson
-1 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2020-12-23 2:49 UTC (permalink / raw)
To: Atish Patra, qemu-devel, qemu-riscv
Cc: Bastian Koppelmann, Anup Patel, Alistair Francis, Palmer Dabbelt,
Sagar Karandikar
On 12/22/20 5:21 PM, Atish Patra wrote:
> +++ b/target/riscv/pmp.c
> @@ -74,7 +74,7 @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
> /*
> * Count the number of active rules.
> */
> -static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
> +inline uint32_t pmp_get_num_rules(CPURISCVState *env)
> {
> return env->pmp_state.num_rules;
> }
...
> --- a/target/riscv/pmp.h
> +++ b/target/riscv/pmp.h
> @@ -64,5 +64,6 @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
> target_ulong *tlb_size);
> void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
> void pmp_update_rule_nums(CPURISCVState *env);
> +uint32_t pmp_get_num_rules(CPURISCVState *env);
You need to remove the inline as well.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv/pmp: Raise exception if no PMP entry is configured
@ 2020-12-23 2:49 ` Richard Henderson
0 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2020-12-23 2:49 UTC (permalink / raw)
To: Atish Patra, qemu-devel, qemu-riscv
Cc: Sagar Karandikar, Bastian Koppelmann, Anup Patel,
Alistair Francis, Palmer Dabbelt
On 12/22/20 5:21 PM, Atish Patra wrote:
> +++ b/target/riscv/pmp.c
> @@ -74,7 +74,7 @@ static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index)
> /*
> * Count the number of active rules.
> */
> -static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
> +inline uint32_t pmp_get_num_rules(CPURISCVState *env)
> {
> return env->pmp_state.num_rules;
> }
...
> --- a/target/riscv/pmp.h
> +++ b/target/riscv/pmp.h
> @@ -64,5 +64,6 @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa,
> target_ulong *tlb_size);
> void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
> void pmp_update_rule_nums(CPURISCVState *env);
> +uint32_t pmp_get_num_rules(CPURISCVState *env);
You need to remove the inline as well.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv/pmp: Raise exception if no PMP entry is configured
2020-12-23 2:49 ` Richard Henderson
@ 2020-12-23 19:26 ` Atish Patra
-1 siblings, 0 replies; 6+ messages in thread
From: Atish Patra @ 2020-12-23 19:26 UTC (permalink / raw)
To: qemu-riscv, richard.henderson, qemu-devel
Cc: kbastian, Alistair Francis, Anup Patel, palmer, sagark
On Tue, 2020-12-22 at 18:49 -0800, Richard Henderson wrote:
> On 12/22/20 5:21 PM, Atish Patra wrote:
> > +++ b/target/riscv/pmp.c
> > @@ -74,7 +74,7 @@ static inline int pmp_is_locked(CPURISCVState
> > *env, uint32_t pmp_index)
> > /*
> > * Count the number of active rules.
> > */
> > -static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
> > +inline uint32_t pmp_get_num_rules(CPURISCVState *env)
> > {
> > return env->pmp_state.num_rules;
> > }
> ...
> > --- a/target/riscv/pmp.h
> > +++ b/target/riscv/pmp.h
> > @@ -64,5 +64,6 @@ bool pmp_is_range_in_tlb(CPURISCVState *env,
> > hwaddr tlb_sa,
> > target_ulong *tlb_size);
> > void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
> > void pmp_update_rule_nums(CPURISCVState *env);
> > +uint32_t pmp_get_num_rules(CPURISCVState *env);
>
> You need to remove the inline as well.
>
Of course. Fixed in v2. Thanks.
>
> r~
--
Regards,
Atish
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv/pmp: Raise exception if no PMP entry is configured
@ 2020-12-23 19:26 ` Atish Patra
0 siblings, 0 replies; 6+ messages in thread
From: Atish Patra @ 2020-12-23 19:26 UTC (permalink / raw)
To: qemu-riscv, richard.henderson, qemu-devel
Cc: palmer, kbastian, sagark, Alistair Francis, Anup Patel
On Tue, 2020-12-22 at 18:49 -0800, Richard Henderson wrote:
> On 12/22/20 5:21 PM, Atish Patra wrote:
> > +++ b/target/riscv/pmp.c
> > @@ -74,7 +74,7 @@ static inline int pmp_is_locked(CPURISCVState
> > *env, uint32_t pmp_index)
> > /*
> > * Count the number of active rules.
> > */
> > -static inline uint32_t pmp_get_num_rules(CPURISCVState *env)
> > +inline uint32_t pmp_get_num_rules(CPURISCVState *env)
> > {
> > return env->pmp_state.num_rules;
> > }
> ...
> > --- a/target/riscv/pmp.h
> > +++ b/target/riscv/pmp.h
> > @@ -64,5 +64,6 @@ bool pmp_is_range_in_tlb(CPURISCVState *env,
> > hwaddr tlb_sa,
> > target_ulong *tlb_size);
> > void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
> > void pmp_update_rule_nums(CPURISCVState *env);
> > +uint32_t pmp_get_num_rules(CPURISCVState *env);
>
> You need to remove the inline as well.
>
Of course. Fixed in v2. Thanks.
>
> r~
--
Regards,
Atish
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-12-23 19:29 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-23 1:21 [PATCH] target/riscv/pmp: Raise exception if no PMP entry is configured Atish Patra
2020-12-23 1:21 ` Atish Patra
2020-12-23 2:49 ` Richard Henderson
2020-12-23 2:49 ` Richard Henderson
2020-12-23 19:26 ` Atish Patra
2020-12-23 19:26 ` Atish Patra
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.