* [linux-next:master 6564/9127] drivers/clk/qcom/gcc-ipq8074.c:4610:30: warning: initialized field overwritten
@ 2020-07-17 19:21 kernel test robot
2020-07-18 4:30 ` Sivaprakash Murugesan
0 siblings, 1 reply; 2+ messages in thread
From: kernel test robot @ 2020-07-17 19:21 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 16128 bytes --]
Hi Sivaprakash,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
head: aab7ee9f8ff0110bfcd594b33dc33748dc1baf46
commit: f0cfcf1ade201dcfd3365f231efc90e846fa46df [6564/9127] clk: qcom: ipq8074: Add missing clocks for pcie
config: arm-randconfig-r026-20200717 (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout f0cfcf1ade201dcfd3365f231efc90e846fa46df
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/clk/qcom/gcc-ipq8074.c:4610:30: warning: initialized field overwritten [-Woverride-init]
4610 | [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
| ^
drivers/clk/qcom/gcc-ipq8074.c:4610:30: note: (near initialization for 'gcc_ipq8074_clks[133]')
drivers/clk/qcom/gcc-ipq8074.c:4611:26: warning: initialized field overwritten [-Woverride-init]
4611 | [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
| ^
drivers/clk/qcom/gcc-ipq8074.c:4611:26: note: (near initialization for 'gcc_ipq8074_clks[134]')
drivers/clk/qcom/gcc-ipq8074.c:4612:33: warning: initialized field overwritten [-Woverride-init]
4612 | [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
| ^
drivers/clk/qcom/gcc-ipq8074.c:4612:33: note: (near initialization for 'gcc_ipq8074_clks[132]')
vim +4610 drivers/clk/qcom/gcc-ipq8074.c
4384
4385 static struct clk_regmap *gcc_ipq8074_clks[] = {
4386 [GPLL0_MAIN] = &gpll0_main.clkr,
4387 [GPLL0] = &gpll0.clkr,
4388 [GPLL2_MAIN] = &gpll2_main.clkr,
4389 [GPLL2] = &gpll2.clkr,
4390 [GPLL4_MAIN] = &gpll4_main.clkr,
4391 [GPLL4] = &gpll4.clkr,
4392 [GPLL6_MAIN] = &gpll6_main.clkr,
4393 [GPLL6] = &gpll6.clkr,
4394 [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
4395 [UBI32_PLL] = &ubi32_pll.clkr,
4396 [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
4397 [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
4398 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
4399 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
4400 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
4401 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
4402 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
4403 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
4404 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
4405 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
4406 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
4407 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
4408 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
4409 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
4410 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
4411 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
4412 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
4413 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
4414 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
4415 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
4416 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
4417 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
4418 [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
4419 [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
4420 [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
4421 [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
4422 [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
4423 [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
4424 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
4425 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
4426 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
4427 [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
4428 [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
4429 [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
4430 [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
4431 [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
4432 [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
4433 [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
4434 [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
4435 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
4436 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
4437 [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
4438 [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
4439 [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
4440 [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
4441 [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
4442 [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
4443 [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
4444 [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
4445 [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
4446 [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
4447 [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
4448 [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
4449 [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
4450 [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
4451 [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
4452 [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
4453 [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
4454 [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
4455 [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
4456 [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
4457 [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
4458 [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
4459 [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
4460 [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
4461 [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
4462 [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
4463 [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
4464 [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
4465 [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
4466 [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
4467 [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
4468 [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
4469 [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
4470 [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
4471 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
4472 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
4473 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
4474 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
4475 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
4476 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
4477 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
4478 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
4479 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
4480 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
4481 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
4482 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
4483 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
4484 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
4485 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
4486 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
4487 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
4488 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
4489 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
4490 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
4491 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
4492 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
4493 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
4494 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
4495 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
4496 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
4497 [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
4498 [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
4499 [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
4500 [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
4501 [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
4502 [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
4503 [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
4504 [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
4505 [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
4506 [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
4507 [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
4508 [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
4509 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
4510 [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
4511 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
4512 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
4513 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
4514 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
4515 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
4516 [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
4517 [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
4518 [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
4519 [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
4520 [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
4521 [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
4522 [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
4523 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
4524 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
4525 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
4526 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
4527 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
4528 [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
4529 [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
4530 [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
4531 [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
4532 [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
4533 [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
4534 [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
4535 [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
4536 [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
4537 [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
4538 [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
4539 [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
4540 [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
4541 [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
4542 [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
4543 [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
4544 [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
4545 [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
4546 [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
4547 [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
4548 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
4549 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
4550 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
4551 [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
4552 [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
4553 [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
4554 [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
4555 [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
4556 [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
4557 [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
4558 [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
4559 [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
4560 [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
4561 [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
4562 [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
4563 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
4564 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
4565 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
4566 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
4567 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
4568 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
4569 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
4570 [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
4571 [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
4572 [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
4573 [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
4574 [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
4575 [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
4576 [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
4577 [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
4578 [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
4579 [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
4580 [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
4581 [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
4582 [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
4583 [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
4584 [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
4585 [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
4586 [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
4587 [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
4588 [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
4589 [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
4590 [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
4591 [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
4592 [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
4593 [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
4594 [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
4595 [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
4596 [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
4597 [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
4598 [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
4599 [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
4600 [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
4601 [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
4602 [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
4603 [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
4604 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
4605 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
4606 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
4607 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
4608 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
4609 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
> 4610 [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4611 [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4612 [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4613 };
4614
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 35765 bytes --]
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [linux-next:master 6564/9127] drivers/clk/qcom/gcc-ipq8074.c:4610:30: warning: initialized field overwritten
2020-07-17 19:21 [linux-next:master 6564/9127] drivers/clk/qcom/gcc-ipq8074.c:4610:30: warning: initialized field overwritten kernel test robot
@ 2020-07-18 4:30 ` Sivaprakash Murugesan
0 siblings, 0 replies; 2+ messages in thread
From: Sivaprakash Murugesan @ 2020-07-18 4:30 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 17145 bytes --]
Hi Stephen,
I have sent the fix for this warning.
https://lore.kernel.org/lkml/1594877570-9280-1-git-send-email-sivaprak(a)codeaurora.org/
can you please review?
Thanks,
Siva
On 7/18/2020 12:51 AM, kernel test robot wrote:
> Hi Sivaprakash,
>
> FYI, the error/warning still remains.
>
> tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
> head: aab7ee9f8ff0110bfcd594b33dc33748dc1baf46
> commit: f0cfcf1ade201dcfd3365f231efc90e846fa46df [6564/9127] clk: qcom: ipq8074: Add missing clocks for pcie
> config: arm-randconfig-r026-20200717 (attached as .config)
> compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> git checkout f0cfcf1ade201dcfd3365f231efc90e846fa46df
> # save the attached .config to linux build tree
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All warnings (new ones prefixed by >>):
>
>>> drivers/clk/qcom/gcc-ipq8074.c:4610:30: warning: initialized field overwritten [-Woverride-init]
> 4610 | [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
> | ^
> drivers/clk/qcom/gcc-ipq8074.c:4610:30: note: (near initialization for 'gcc_ipq8074_clks[133]')
> drivers/clk/qcom/gcc-ipq8074.c:4611:26: warning: initialized field overwritten [-Woverride-init]
> 4611 | [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
> | ^
> drivers/clk/qcom/gcc-ipq8074.c:4611:26: note: (near initialization for 'gcc_ipq8074_clks[134]')
> drivers/clk/qcom/gcc-ipq8074.c:4612:33: warning: initialized field overwritten [-Woverride-init]
> 4612 | [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
> | ^
> drivers/clk/qcom/gcc-ipq8074.c:4612:33: note: (near initialization for 'gcc_ipq8074_clks[132]')
>
> vim +4610 drivers/clk/qcom/gcc-ipq8074.c
>
> 4384
> 4385 static struct clk_regmap *gcc_ipq8074_clks[] = {
> 4386 [GPLL0_MAIN] = &gpll0_main.clkr,
> 4387 [GPLL0] = &gpll0.clkr,
> 4388 [GPLL2_MAIN] = &gpll2_main.clkr,
> 4389 [GPLL2] = &gpll2.clkr,
> 4390 [GPLL4_MAIN] = &gpll4_main.clkr,
> 4391 [GPLL4] = &gpll4.clkr,
> 4392 [GPLL6_MAIN] = &gpll6_main.clkr,
> 4393 [GPLL6] = &gpll6.clkr,
> 4394 [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
> 4395 [UBI32_PLL] = &ubi32_pll.clkr,
> 4396 [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
> 4397 [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
> 4398 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
> 4399 [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
> 4400 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
> 4401 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
> 4402 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
> 4403 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
> 4404 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
> 4405 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
> 4406 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
> 4407 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
> 4408 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
> 4409 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
> 4410 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
> 4411 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
> 4412 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
> 4413 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
> 4414 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
> 4415 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
> 4416 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
> 4417 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
> 4418 [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
> 4419 [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
> 4420 [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
> 4421 [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
> 4422 [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
> 4423 [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
> 4424 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
> 4425 [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
> 4426 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
> 4427 [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
> 4428 [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
> 4429 [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
> 4430 [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
> 4431 [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
> 4432 [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
> 4433 [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
> 4434 [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
> 4435 [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
> 4436 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
> 4437 [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
> 4438 [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
> 4439 [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
> 4440 [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
> 4441 [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
> 4442 [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
> 4443 [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
> 4444 [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
> 4445 [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
> 4446 [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
> 4447 [NSS_PORT1_RX_CLK_SRC] = &nss_port1_rx_clk_src.clkr,
> 4448 [NSS_PORT1_RX_DIV_CLK_SRC] = &nss_port1_rx_div_clk_src.clkr,
> 4449 [NSS_PORT1_TX_CLK_SRC] = &nss_port1_tx_clk_src.clkr,
> 4450 [NSS_PORT1_TX_DIV_CLK_SRC] = &nss_port1_tx_div_clk_src.clkr,
> 4451 [NSS_PORT2_RX_CLK_SRC] = &nss_port2_rx_clk_src.clkr,
> 4452 [NSS_PORT2_RX_DIV_CLK_SRC] = &nss_port2_rx_div_clk_src.clkr,
> 4453 [NSS_PORT2_TX_CLK_SRC] = &nss_port2_tx_clk_src.clkr,
> 4454 [NSS_PORT2_TX_DIV_CLK_SRC] = &nss_port2_tx_div_clk_src.clkr,
> 4455 [NSS_PORT3_RX_CLK_SRC] = &nss_port3_rx_clk_src.clkr,
> 4456 [NSS_PORT3_RX_DIV_CLK_SRC] = &nss_port3_rx_div_clk_src.clkr,
> 4457 [NSS_PORT3_TX_CLK_SRC] = &nss_port3_tx_clk_src.clkr,
> 4458 [NSS_PORT3_TX_DIV_CLK_SRC] = &nss_port3_tx_div_clk_src.clkr,
> 4459 [NSS_PORT4_RX_CLK_SRC] = &nss_port4_rx_clk_src.clkr,
> 4460 [NSS_PORT4_RX_DIV_CLK_SRC] = &nss_port4_rx_div_clk_src.clkr,
> 4461 [NSS_PORT4_TX_CLK_SRC] = &nss_port4_tx_clk_src.clkr,
> 4462 [NSS_PORT4_TX_DIV_CLK_SRC] = &nss_port4_tx_div_clk_src.clkr,
> 4463 [NSS_PORT5_RX_CLK_SRC] = &nss_port5_rx_clk_src.clkr,
> 4464 [NSS_PORT5_RX_DIV_CLK_SRC] = &nss_port5_rx_div_clk_src.clkr,
> 4465 [NSS_PORT5_TX_CLK_SRC] = &nss_port5_tx_clk_src.clkr,
> 4466 [NSS_PORT5_TX_DIV_CLK_SRC] = &nss_port5_tx_div_clk_src.clkr,
> 4467 [NSS_PORT6_RX_CLK_SRC] = &nss_port6_rx_clk_src.clkr,
> 4468 [NSS_PORT6_RX_DIV_CLK_SRC] = &nss_port6_rx_div_clk_src.clkr,
> 4469 [NSS_PORT6_TX_CLK_SRC] = &nss_port6_tx_clk_src.clkr,
> 4470 [NSS_PORT6_TX_DIV_CLK_SRC] = &nss_port6_tx_div_clk_src.clkr,
> 4471 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
> 4472 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
> 4473 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
> 4474 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
> 4475 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
> 4476 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
> 4477 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
> 4478 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
> 4479 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
> 4480 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
> 4481 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
> 4482 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
> 4483 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
> 4484 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
> 4485 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
> 4486 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
> 4487 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
> 4488 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
> 4489 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
> 4490 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
> 4491 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
> 4492 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
> 4493 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
> 4494 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
> 4495 [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
> 4496 [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
> 4497 [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
> 4498 [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
> 4499 [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
> 4500 [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
> 4501 [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
> 4502 [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
> 4503 [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
> 4504 [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
> 4505 [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
> 4506 [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
> 4507 [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
> 4508 [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
> 4509 [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
> 4510 [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
> 4511 [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
> 4512 [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
> 4513 [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
> 4514 [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
> 4515 [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
> 4516 [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
> 4517 [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
> 4518 [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
> 4519 [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
> 4520 [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
> 4521 [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
> 4522 [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
> 4523 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
> 4524 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
> 4525 [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
> 4526 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
> 4527 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
> 4528 [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
> 4529 [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
> 4530 [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
> 4531 [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
> 4532 [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
> 4533 [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
> 4534 [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
> 4535 [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
> 4536 [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
> 4537 [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
> 4538 [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
> 4539 [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
> 4540 [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
> 4541 [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
> 4542 [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
> 4543 [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
> 4544 [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
> 4545 [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
> 4546 [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
> 4547 [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
> 4548 [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
> 4549 [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
> 4550 [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
> 4551 [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
> 4552 [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
> 4553 [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
> 4554 [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
> 4555 [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
> 4556 [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
> 4557 [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
> 4558 [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
> 4559 [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
> 4560 [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
> 4561 [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
> 4562 [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
> 4563 [GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
> 4564 [GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
> 4565 [GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
> 4566 [GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
> 4567 [GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
> 4568 [GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
> 4569 [GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
> 4570 [GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
> 4571 [GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
> 4572 [GCC_NSS_PORT1_RX_CLK] = &gcc_nss_port1_rx_clk.clkr,
> 4573 [GCC_NSS_PORT1_TX_CLK] = &gcc_nss_port1_tx_clk.clkr,
> 4574 [GCC_NSS_PORT2_RX_CLK] = &gcc_nss_port2_rx_clk.clkr,
> 4575 [GCC_NSS_PORT2_TX_CLK] = &gcc_nss_port2_tx_clk.clkr,
> 4576 [GCC_NSS_PORT3_RX_CLK] = &gcc_nss_port3_rx_clk.clkr,
> 4577 [GCC_NSS_PORT3_TX_CLK] = &gcc_nss_port3_tx_clk.clkr,
> 4578 [GCC_NSS_PORT4_RX_CLK] = &gcc_nss_port4_rx_clk.clkr,
> 4579 [GCC_NSS_PORT4_TX_CLK] = &gcc_nss_port4_tx_clk.clkr,
> 4580 [GCC_NSS_PORT5_RX_CLK] = &gcc_nss_port5_rx_clk.clkr,
> 4581 [GCC_NSS_PORT5_TX_CLK] = &gcc_nss_port5_tx_clk.clkr,
> 4582 [GCC_NSS_PORT6_RX_CLK] = &gcc_nss_port6_rx_clk.clkr,
> 4583 [GCC_NSS_PORT6_TX_CLK] = &gcc_nss_port6_tx_clk.clkr,
> 4584 [GCC_PORT1_MAC_CLK] = &gcc_port1_mac_clk.clkr,
> 4585 [GCC_PORT2_MAC_CLK] = &gcc_port2_mac_clk.clkr,
> 4586 [GCC_PORT3_MAC_CLK] = &gcc_port3_mac_clk.clkr,
> 4587 [GCC_PORT4_MAC_CLK] = &gcc_port4_mac_clk.clkr,
> 4588 [GCC_PORT5_MAC_CLK] = &gcc_port5_mac_clk.clkr,
> 4589 [GCC_PORT6_MAC_CLK] = &gcc_port6_mac_clk.clkr,
> 4590 [GCC_UNIPHY0_PORT1_RX_CLK] = &gcc_uniphy0_port1_rx_clk.clkr,
> 4591 [GCC_UNIPHY0_PORT1_TX_CLK] = &gcc_uniphy0_port1_tx_clk.clkr,
> 4592 [GCC_UNIPHY0_PORT2_RX_CLK] = &gcc_uniphy0_port2_rx_clk.clkr,
> 4593 [GCC_UNIPHY0_PORT2_TX_CLK] = &gcc_uniphy0_port2_tx_clk.clkr,
> 4594 [GCC_UNIPHY0_PORT3_RX_CLK] = &gcc_uniphy0_port3_rx_clk.clkr,
> 4595 [GCC_UNIPHY0_PORT3_TX_CLK] = &gcc_uniphy0_port3_tx_clk.clkr,
> 4596 [GCC_UNIPHY0_PORT4_RX_CLK] = &gcc_uniphy0_port4_rx_clk.clkr,
> 4597 [GCC_UNIPHY0_PORT4_TX_CLK] = &gcc_uniphy0_port4_tx_clk.clkr,
> 4598 [GCC_UNIPHY0_PORT5_RX_CLK] = &gcc_uniphy0_port5_rx_clk.clkr,
> 4599 [GCC_UNIPHY0_PORT5_TX_CLK] = &gcc_uniphy0_port5_tx_clk.clkr,
> 4600 [GCC_UNIPHY1_PORT5_RX_CLK] = &gcc_uniphy1_port5_rx_clk.clkr,
> 4601 [GCC_UNIPHY1_PORT5_TX_CLK] = &gcc_uniphy1_port5_tx_clk.clkr,
> 4602 [GCC_UNIPHY2_PORT6_RX_CLK] = &gcc_uniphy2_port6_rx_clk.clkr,
> 4603 [GCC_UNIPHY2_PORT6_TX_CLK] = &gcc_uniphy2_port6_tx_clk.clkr,
> 4604 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
> 4605 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
> 4606 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
> 4607 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
> 4608 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
> 4609 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
>> 4610 [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
> 4611 [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
> 4612 [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
> 4613 };
> 4614
>
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
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2020-07-17 19:21 [linux-next:master 6564/9127] drivers/clk/qcom/gcc-ipq8074.c:4610:30: warning: initialized field overwritten kernel test robot
2020-07-18 4:30 ` Sivaprakash Murugesan
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