* [PATCH v2] arm64: dts: mt8183: Add gce client reg for display subcomponents
@ 2021-03-24 7:08 ` Hsin-Yi Wang
0 siblings, 0 replies; 6+ messages in thread
From: Hsin-Yi Wang @ 2021-03-24 7:08 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Rob Herring, Matthias Brugger, Enric Balletbo i Serra,
devicetree, linux-mediatek, linux-kernel
Add mediatek,gce-client-reg for mmsys, ccorr, aal, gamma, dither.
Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
v1->v2:
Add for mmsys.
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 80519a145f13..16f4b1fc0fb9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -983,6 +983,9 @@ mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
ovl0: ovl@14008000 {
@@ -1058,6 +1061,7 @@ ccorr0: ccorr@1400f000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
};
aal0: aal@14010000 {
@@ -1067,6 +1071,7 @@ aal0: aal@14010000 {
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
};
gamma0: gamma@14011000 {
@@ -1075,6 +1080,7 @@ gamma0: gamma@14011000 {
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
};
dither0: dither@14012000 {
@@ -1083,6 +1089,7 @@ dither0: dither@14012000 {
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
};
dsi0: dsi@14014000 {
--
2.31.0.291.g576ba9dcdaf-goog
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2] arm64: dts: mt8183: Add gce client reg for display subcomponents
@ 2021-03-24 7:08 ` Hsin-Yi Wang
0 siblings, 0 replies; 6+ messages in thread
From: Hsin-Yi Wang @ 2021-03-24 7:08 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Rob Herring, Matthias Brugger, Enric Balletbo i Serra,
devicetree, linux-mediatek, linux-kernel
Add mediatek,gce-client-reg for mmsys, ccorr, aal, gamma, dither.
Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
v1->v2:
Add for mmsys.
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 80519a145f13..16f4b1fc0fb9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -983,6 +983,9 @@ mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
ovl0: ovl@14008000 {
@@ -1058,6 +1061,7 @@ ccorr0: ccorr@1400f000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
};
aal0: aal@14010000 {
@@ -1067,6 +1071,7 @@ aal0: aal@14010000 {
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
};
gamma0: gamma@14011000 {
@@ -1075,6 +1080,7 @@ gamma0: gamma@14011000 {
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
};
dither0: dither@14012000 {
@@ -1083,6 +1089,7 @@ dither0: dither@14012000 {
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
};
dsi0: dsi@14014000 {
--
2.31.0.291.g576ba9dcdaf-goog
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2] arm64: dts: mt8183: Add gce client reg for display subcomponents
@ 2021-03-24 7:08 ` Hsin-Yi Wang
0 siblings, 0 replies; 6+ messages in thread
From: Hsin-Yi Wang @ 2021-03-24 7:08 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Rob Herring, Matthias Brugger, Enric Balletbo i Serra,
devicetree, linux-mediatek, linux-kernel
Add mediatek,gce-client-reg for mmsys, ccorr, aal, gamma, dither.
Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
v1->v2:
Add for mmsys.
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 80519a145f13..16f4b1fc0fb9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -983,6 +983,9 @@ mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
+ mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+ <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
ovl0: ovl@14008000 {
@@ -1058,6 +1061,7 @@ ccorr0: ccorr@1400f000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
};
aal0: aal@14010000 {
@@ -1067,6 +1071,7 @@ aal0: aal@14010000 {
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
};
gamma0: gamma@14011000 {
@@ -1075,6 +1080,7 @@ gamma0: gamma@14011000 {
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
};
dither0: dither@14012000 {
@@ -1083,6 +1089,7 @@ dither0: dither@14012000 {
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
};
dsi0: dsi@14014000 {
--
2.31.0.291.g576ba9dcdaf-goog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: dts: mt8183: Add gce client reg for display subcomponents
2021-03-24 7:08 ` Hsin-Yi Wang
(?)
@ 2021-03-29 15:26 ` Matthias Brugger
-1 siblings, 0 replies; 6+ messages in thread
From: Matthias Brugger @ 2021-03-29 15:26 UTC (permalink / raw)
To: Hsin-Yi Wang, linux-arm-kernel
Cc: Rob Herring, Enric Balletbo i Serra, devicetree, linux-mediatek,
linux-kernel
On 24/03/2021 08:08, Hsin-Yi Wang wrote:
> Add mediatek,gce-client-reg for mmsys, ccorr, aal, gamma, dither.
>
> Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Applied to v5.12-next/dts64
Thanks!
> ---
> v1->v2:
> Add for mmsys.
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 80519a145f13..16f4b1fc0fb9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -983,6 +983,9 @@ mmsys: syscon@14000000 {
> compatible = "mediatek,mt8183-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> #clock-cells = <1>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> };
>
> ovl0: ovl@14008000 {
> @@ -1058,6 +1061,7 @@ ccorr0: ccorr@1400f000 {
> interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> };
>
> aal0: aal@14010000 {
> @@ -1067,6 +1071,7 @@ aal0: aal@14010000 {
> interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> };
>
> gamma0: gamma@14011000 {
> @@ -1075,6 +1080,7 @@ gamma0: gamma@14011000 {
> interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> };
>
> dither0: dither@14012000 {
> @@ -1083,6 +1089,7 @@ dither0: dither@14012000 {
> interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> };
>
> dsi0: dsi@14014000 {
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: dts: mt8183: Add gce client reg for display subcomponents
@ 2021-03-29 15:26 ` Matthias Brugger
0 siblings, 0 replies; 6+ messages in thread
From: Matthias Brugger @ 2021-03-29 15:26 UTC (permalink / raw)
To: Hsin-Yi Wang, linux-arm-kernel
Cc: Rob Herring, Enric Balletbo i Serra, devicetree, linux-mediatek,
linux-kernel
On 24/03/2021 08:08, Hsin-Yi Wang wrote:
> Add mediatek,gce-client-reg for mmsys, ccorr, aal, gamma, dither.
>
> Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Applied to v5.12-next/dts64
Thanks!
> ---
> v1->v2:
> Add for mmsys.
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 80519a145f13..16f4b1fc0fb9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -983,6 +983,9 @@ mmsys: syscon@14000000 {
> compatible = "mediatek,mt8183-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> #clock-cells = <1>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> };
>
> ovl0: ovl@14008000 {
> @@ -1058,6 +1061,7 @@ ccorr0: ccorr@1400f000 {
> interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> };
>
> aal0: aal@14010000 {
> @@ -1067,6 +1071,7 @@ aal0: aal@14010000 {
> interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> };
>
> gamma0: gamma@14011000 {
> @@ -1075,6 +1080,7 @@ gamma0: gamma@14011000 {
> interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> };
>
> dither0: dither@14012000 {
> @@ -1083,6 +1089,7 @@ dither0: dither@14012000 {
> interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> };
>
> dsi0: dsi@14014000 {
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] arm64: dts: mt8183: Add gce client reg for display subcomponents
@ 2021-03-29 15:26 ` Matthias Brugger
0 siblings, 0 replies; 6+ messages in thread
From: Matthias Brugger @ 2021-03-29 15:26 UTC (permalink / raw)
To: Hsin-Yi Wang, linux-arm-kernel
Cc: Rob Herring, Enric Balletbo i Serra, devicetree, linux-mediatek,
linux-kernel
On 24/03/2021 08:08, Hsin-Yi Wang wrote:
> Add mediatek,gce-client-reg for mmsys, ccorr, aal, gamma, dither.
>
> Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Applied to v5.12-next/dts64
Thanks!
> ---
> v1->v2:
> Add for mmsys.
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 80519a145f13..16f4b1fc0fb9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -983,6 +983,9 @@ mmsys: syscon@14000000 {
> compatible = "mediatek,mt8183-mmsys", "syscon";
> reg = <0 0x14000000 0 0x1000>;
> #clock-cells = <1>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> };
>
> ovl0: ovl@14008000 {
> @@ -1058,6 +1061,7 @@ ccorr0: ccorr@1400f000 {
> interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> };
>
> aal0: aal@14010000 {
> @@ -1067,6 +1071,7 @@ aal0: aal@14010000 {
> interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> };
>
> gamma0: gamma@14011000 {
> @@ -1075,6 +1080,7 @@ gamma0: gamma@14011000 {
> interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> };
>
> dither0: dither@14012000 {
> @@ -1083,6 +1089,7 @@ dither0: dither@14012000 {
> interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> clocks = <&mmsys CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> };
>
> dsi0: dsi@14014000 {
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-03-29 23:06 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-03-24 7:08 [PATCH v2] arm64: dts: mt8183: Add gce client reg for display subcomponents Hsin-Yi Wang
2021-03-24 7:08 ` Hsin-Yi Wang
2021-03-24 7:08 ` Hsin-Yi Wang
2021-03-29 15:26 ` Matthias Brugger
2021-03-29 15:26 ` Matthias Brugger
2021-03-29 15:26 ` Matthias Brugger
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