From: Richard Henderson <richard.henderson@linaro.org>
To: "Wu, Fei" <fei2.wu@intel.com>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Christoph Muellner <christoph.muellner@vrull.eu>
Subject: Re: [PATCH v4 1/2] target/riscv: separate priv from mmu_idx
Date: Thu, 23 Mar 2023 09:07:10 -0700 [thread overview]
Message-ID: <ab0db790-b577-6ffb-a424-7b243b7019f2@linaro.org> (raw)
In-Reply-To: <7db6d615-5ddc-5e1b-1d3c-a85c22e6af74@intel.com>
On 3/22/23 23:00, Wu, Fei wrote:
>>> + ctx->priv = env->priv;
>>
>> This is not right. You should put env->priv into tb flags before you use
>> it in translation.
>>
> I see some other env usages in this function, when will env->priv and
> tb_flags.priv mismatch (assume we have recorded priv in tb_flags)?
You are correct that they should match, because of tb_flags, but it is bad form to read
from env, as that leads to errors. Since you *can* read the same data from tb_flags, you
should.
The read of misa_ext and misa_mxl_max are correct, because they are constant set at cpu
init/realize.
The read of vstart is incorrect. The TB_FLAGS field is VL_EQ_VLMAX, which includes a test
for vstart == 0, but the smaller vstart == 0 test is not extractable from that. Thus the
usage in e.g. vext_check_reduction is incorrect. One would require a new TB_FLAGS bit to
encode vstart ==/!= 0 alone.
r~
next prev parent reply other threads:[~2023-03-23 16:08 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-23 2:44 [PATCH v4 0/2] target/riscv: reduce MSTATUS_SUM overhead Fei Wu
2023-03-23 2:44 ` [PATCH v4 1/2] target/riscv: separate priv from mmu_idx Fei Wu
2023-03-23 5:37 ` LIU Zhiwei
2023-03-23 6:00 ` Wu, Fei
2023-03-23 6:25 ` Wu, Fei
2023-03-23 6:59 ` LIU Zhiwei
2023-03-23 13:18 ` Wu, Fei
2023-03-23 16:07 ` Richard Henderson [this message]
2023-03-24 1:20 ` Wu, Fei
2023-03-24 2:37 ` Richard Henderson
2023-03-24 3:01 ` Wu, Fei
2023-03-23 15:53 ` Richard Henderson
2023-03-24 1:02 ` Wu, Fei
2023-03-24 1:22 ` Wu, Fei
2023-03-24 12:31 ` Wu, Fei
2023-03-23 2:44 ` [PATCH v4 2/2] target/riscv: reduce overhead of MSTATUS_SUM change Fei Wu
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