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* [PATCH 01/21] drm/i915: Restrict the aliasing-ppgtt to the size of the ggtt
@ 2019-09-02  4:02 Chris Wilson
  2019-09-02  4:02 ` [PATCH 02/21] drm/i915: Report aliasing ppgtt size as ggtt size Chris Wilson
                   ` (23 more replies)
  0 siblings, 24 replies; 53+ messages in thread
From: Chris Wilson @ 2019-09-02  4:02 UTC (permalink / raw)
  To: intel-gfx; +Cc: Matthew Auld

The aliasing-ppgtt is not allowed to be smaller than the ggtt, nor
should we advertise it as being any bigger, or else we may get sued for
false advertisement.

Testcase: igt/gem_exec_big
Fixes: 0b718ba1e884 ("drm/i915/gtt: Downgrade Cherryview back to aliasing-ppgtt")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index ee51fd1a6207..906dc6fff383 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2597,6 +2597,8 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
 	GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma);
 	ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma;
 
+	ppgtt->vm.total = ggtt->vm.total;
+
 	return 0;
 
 err_ppgtt:
-- 
2.23.0

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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 53+ messages in thread
* [PATCH 01/21] drm/i915/gtt: Downgrade Baytrail back to aliasing-ppgtt
@ 2019-08-30  6:11 Chris Wilson
  2019-08-30  6:11 ` [PATCH 12/21] drm/i915: Mark up address spaces that may need to allocate Chris Wilson
  0 siblings, 1 reply; 53+ messages in thread
From: Chris Wilson @ 2019-08-30  6:11 UTC (permalink / raw)
  To: intel-gfx

With the upcoming change in timing (dramatically reducing the latency
between manipulating the ppGTT and execution), no amount of tweaking
could save Baytrail, it would always fail to invalidate its TLB. Ville
was right, Baytrail is beyond hope.

v2: Rollback on all gen7; same timing instability on TLB invalidation.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 63 +++++++---------------
 drivers/gpu/drm/i915/i915_pci.c            |  4 +-
 2 files changed, 20 insertions(+), 47 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index 601c16239fdf..ac55a0d054bd 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -1741,46 +1741,22 @@ static int remap_l3(struct i915_request *rq)
 
 static int switch_context(struct i915_request *rq)
 {
-	struct intel_engine_cs *engine = rq->engine;
-	struct i915_address_space *vm = vm_alias(rq->hw_context);
-	unsigned int unwind_mm = 0;
-	u32 hw_flags = 0;
+	struct intel_context *ce = rq->hw_context;
+	struct i915_address_space *vm = vm_alias(ce);
 	int ret;
 
 	GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
 
 	if (vm) {
-		struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
-		int loops;
-
-		/*
-		 * Baytail takes a little more convincing that it really needs
-		 * to reload the PD between contexts. It is not just a little
-		 * longer, as adding more stalls after the load_pd_dir (i.e.
-		 * adding a long loop around flush_pd_dir) is not as effective
-		 * as reloading the PD umpteen times. 32 is derived from
-		 * experimentation (gem_exec_parallel/fds) and has no good
-		 * explanation.
-		 */
-		loops = 1;
-		if (engine->id == BCS0 && IS_VALLEYVIEW(engine->i915))
-			loops = 32;
-
-		do {
-			ret = load_pd_dir(rq, ppgtt);
-			if (ret)
-				goto err;
-		} while (--loops);
-
-		if (ppgtt->pd_dirty_engines & engine->mask) {
-			unwind_mm = engine->mask;
-			ppgtt->pd_dirty_engines &= ~unwind_mm;
-			hw_flags = MI_FORCE_RESTORE;
-		}
+		ret = load_pd_dir(rq, i915_vm_to_ppgtt(vm));
+		if (ret)
+			return ret;
 	}
 
-	if (rq->hw_context->state) {
-		GEM_BUG_ON(engine->id != RCS0);
+	if (ce->state) {
+		u32 hw_flags;
+
+		GEM_BUG_ON(rq->engine->id != RCS0);
 
 		/*
 		 * The kernel context(s) is treated as pure scratch and is not
@@ -1789,22 +1765,25 @@ static int switch_context(struct i915_request *rq)
 		 * as nothing actually executes using the kernel context; it
 		 * is purely used for flushing user contexts.
 		 */
+		hw_flags = 0;
 		if (i915_gem_context_is_kernel(rq->gem_context))
 			hw_flags = MI_RESTORE_INHIBIT;
 
 		ret = mi_set_context(rq, hw_flags);
 		if (ret)
-			goto err_mm;
+			return ret;
 	}
 
 	if (vm) {
+		struct intel_engine_cs *engine = rq->engine;
+
 		ret = engine->emit_flush(rq, EMIT_INVALIDATE);
 		if (ret)
-			goto err_mm;
+			return ret;
 
 		ret = flush_pd_dir(rq);
 		if (ret)
-			goto err_mm;
+			return ret;
 
 		/*
 		 * Not only do we need a full barrier (post-sync write) after
@@ -1816,24 +1795,18 @@ static int switch_context(struct i915_request *rq)
 		 */
 		ret = engine->emit_flush(rq, EMIT_INVALIDATE);
 		if (ret)
-			goto err_mm;
+			return ret;
 
 		ret = engine->emit_flush(rq, EMIT_FLUSH);
 		if (ret)
-			goto err_mm;
+			return ret;
 	}
 
 	ret = remap_l3(rq);
 	if (ret)
-		goto err_mm;
+		return ret;
 
 	return 0;
-
-err_mm:
-	if (unwind_mm)
-		i915_vm_to_ppgtt(vm)->pd_dirty_engines |= unwind_mm;
-err:
-	return ret;
 }
 
 static int ring_request_alloc(struct i915_request *request)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1974e4c78a43..18212c39a9ba 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -420,7 +420,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = {
 	.has_rc6 = 1, \
 	.has_rc6p = 1, \
 	.has_rps = true, \
-	.ppgtt_type = INTEL_PPGTT_FULL, \
+	.ppgtt_type = INTEL_PPGTT_ALIASING, \
 	.ppgtt_size = 31, \
 	IVB_PIPE_OFFSETS, \
 	IVB_CURSOR_OFFSETS, \
@@ -476,7 +476,7 @@ static const struct intel_device_info intel_valleyview_info = {
 	.has_rps = true,
 	.display.has_gmch = 1,
 	.display.has_hotplug = 1,
-	.ppgtt_type = INTEL_PPGTT_FULL,
+	.ppgtt_type = INTEL_PPGTT_ALIASING,
 	.ppgtt_size = 31,
 	.has_snoop = true,
 	.has_coherent_ggtt = false,
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 53+ messages in thread
end of thread, other threads:[~2019-09-27 17:03 UTC | newest]

Thread overview: 53+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-02  4:02 [PATCH 01/21] drm/i915: Restrict the aliasing-ppgtt to the size of the ggtt Chris Wilson
2019-09-02  4:02 ` [PATCH 02/21] drm/i915: Report aliasing ppgtt size as ggtt size Chris Wilson
2019-09-02  8:55   ` Matthew Auld
2019-09-02  4:02 ` [PATCH 03/21] drm/i915/execlists: Ignore lost completion events Chris Wilson
2019-09-02  4:02 ` [PATCH 04/21] drm/i915: Refresh the errno to vmf_fault translations Chris Wilson
2019-09-03 15:34   ` Abdiel Janulgue
2019-09-02  4:02 ` [PATCH 05/21] drm/i915: Replace obj->pin_global with obj->frontbuffer Chris Wilson
2019-09-02  4:02 ` [PATCH 06/21] dma-fence: Serialise signal enabling (dma_fence_enable_sw_signaling) Chris Wilson
2019-09-02  4:02 ` [PATCH 07/21] drm/mm: Pack allocated/scanned boolean into a bitfield Chris Wilson
2019-09-02  4:02 ` [PATCH 08/21] drm/i915: Make shrink/unshrink be atomic Chris Wilson
2019-09-10 19:54   ` Matthew Auld
2019-09-02  4:02 ` [PATCH 09/21] drm/i915: Only track bound elements of the GTT Chris Wilson
2019-09-02  4:02 ` [PATCH 10/21] drm/i915: Make i915_vma.flags atomic_t for mutex reduction Chris Wilson
2019-09-10 20:06   ` Matthew Auld
2019-09-02  4:02 ` [PATCH 11/21] drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use Chris Wilson
2019-09-10 20:17   ` Matthew Auld
2019-09-02  4:02 ` [PATCH 12/21] drm/i915: Mark up address spaces that may need to allocate Chris Wilson
2019-09-20 16:22   ` Tvrtko Ursulin
2019-09-20 16:35     ` Chris Wilson
2019-09-23  8:10       ` Tvrtko Ursulin
2019-09-25  8:23         ` Chris Wilson
2019-09-25 15:59           ` Tvrtko Ursulin
2019-09-27 17:03             ` Chris Wilson
2019-09-02  4:02 ` [PATCH 13/21] drm/i915: Pull i915_vma_pin under the vm->mutex Chris Wilson
2019-09-16 10:13   ` Tvrtko Ursulin
2019-09-16 11:10     ` Chris Wilson
2019-09-17 12:37   ` Tvrtko Ursulin
2019-09-17 18:56     ` Chris Wilson
2019-09-19 13:37       ` Tvrtko Ursulin
2019-09-19 14:05         ` Chris Wilson
2019-09-02  4:02 ` [PATCH 14/21] drm/i915: Push the i915_active.retire into a worker Chris Wilson
2019-09-02  4:02 ` [PATCH 15/21] drm/i915: Coordinate i915_active with its own mutex Chris Wilson
2019-09-20 16:14   ` Tvrtko Ursulin
2019-09-20 16:32     ` Chris Wilson
2019-09-02  4:02 ` [PATCH 16/21] drm/i915: Move idle barrier cleanup into engine-pm Chris Wilson
2019-09-20 16:18   ` Tvrtko Ursulin
2019-09-02  4:02 ` [PATCH 17/21] drm/i915: Drop struct_mutex from around i915_retire_requests() Chris Wilson
2019-09-24 15:25   ` Tvrtko Ursulin
2019-09-25  8:43     ` Chris Wilson
2019-09-25  8:49       ` Tvrtko Ursulin
2019-09-02  4:03 ` [PATCH 18/21] drm/i915: Remove the GEM idle worker Chris Wilson
2019-09-24 15:26   ` Tvrtko Ursulin
2019-09-02  4:03 ` [PATCH 19/21] drm/i915: Merge wait_for_timelines with retire_request Chris Wilson
2019-09-24 15:57   ` Tvrtko Ursulin
2019-09-25  8:54     ` Chris Wilson
2019-09-02  4:03 ` [PATCH 20/21] drm/i915: Move request runtime management onto gt Chris Wilson
2019-09-02  4:03 ` [PATCH 21/21] drm/i915: Move global activity tracking from GEM to GT Chris Wilson
2019-09-25  9:55   ` Tvrtko Ursulin
2019-09-02  4:54 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/21] drm/i915: Restrict the aliasing-ppgtt to the size of the ggtt Patchwork
2019-09-02  5:20 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-02  8:00 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-09-02  8:52 ` [PATCH 01/21] " Matthew Auld
  -- strict thread matches above, loose matches on Subject: below --
2019-08-30  6:11 [PATCH 01/21] drm/i915/gtt: Downgrade Baytrail back to aliasing-ppgtt Chris Wilson
2019-08-30  6:11 ` [PATCH 12/21] drm/i915: Mark up address spaces that may need to allocate Chris Wilson

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