* [Qemu-devel] [PATCH v4 0/2] 680x0 mul and div instructions
@ 2016-11-01 20:03 Laurent Vivier
2016-11-01 20:03 ` [Qemu-devel] [PATCH v4 1/2] target-m68k: add 64bit mull Laurent Vivier
2016-11-01 20:03 ` [Qemu-devel] [PATCH v4 2/2] target-m68k: add 680x0 divu/divs variants Laurent Vivier
0 siblings, 2 replies; 7+ messages in thread
From: Laurent Vivier @ 2016-11-01 20:03 UTC (permalink / raw)
To: qemu-devel; +Cc: schwab, agraf, Richard Henderson, gerg, Laurent Vivier
This series is another subset of the series I sent in May:
https://lists.gnu.org/archive/html/qemu-devel/2016-05/msg00501.html
It must be applied on top of series:
"target-m68k: 680x0 instruction set, part 2"
This subset contains reworked patches of mul and div instructions:
- "add 64bit mull": correctly set QREG_CC_V,
- "inline divu/divs": don't inline divu/divs, but update
existing functions to manage 680x0 div instructions
I've checked it doesn't break coldfire support:
http://wiki.qemu.org/download/coldfire-test-0.1.tar.bz2
but it can't boot a 680x0 processor kernel.
v4:
- divull/divsll: build correctly the 64bit num value
check overflow as it is done in divsw
v3:
- mull: manage the case where Dl == Dh
- divu/divs: move all the mechanic to helpers,
and pass the register number to directly set
the result
v2:
- Free "rem" and "quot" in "divl".
Laurent Vivier (2):
target-m68k: add 64bit mull
target-m68k: add 680x0 divu/divs variants
linux-user/main.c | 7 ++
target-m68k/cpu.h | 4 --
target-m68k/helper.h | 8 ++-
target-m68k/op_helper.c | 182 +++++++++++++++++++++++++++++++++++++++++-------
target-m68k/qregs.def | 2 -
target-m68k/translate.c | 146 +++++++++++++++++++++++++-------------
6 files changed, 267 insertions(+), 82 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH v4 1/2] target-m68k: add 64bit mull
2016-11-01 20:03 [Qemu-devel] [PATCH v4 0/2] 680x0 mul and div instructions Laurent Vivier
@ 2016-11-01 20:03 ` Laurent Vivier
2016-11-01 20:03 ` [Qemu-devel] [PATCH v4 2/2] target-m68k: add 680x0 divu/divs variants Laurent Vivier
1 sibling, 0 replies; 7+ messages in thread
From: Laurent Vivier @ 2016-11-01 20:03 UTC (permalink / raw)
To: qemu-devel; +Cc: schwab, agraf, Richard Henderson, gerg, Laurent Vivier
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twidle.net>
---
target-m68k/translate.c | 62 +++++++++++++++++++++++++++++++++++++++----------
1 file changed, 50 insertions(+), 12 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 8433fa0..61986cc 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1812,24 +1812,62 @@ DISAS_INSN(tas)
DISAS_INSN(mull)
{
uint16_t ext;
- TCGv reg;
TCGv src1;
- TCGv dest;
+ int sign;
- /* The upper 32 bits of the product are discarded, so
- muls.l and mulu.l are functionally equivalent. */
ext = read_im16(env, s);
- if (ext & 0x87ff) {
- gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
+
+ sign = ext & 0x800;
+
+ if (ext & 0x400) {
+ if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
+ gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
+ return;
+ }
+
+ SRC_EA(env, src1, OS_LONG, 0, NULL);
+
+ if (sign) {
+ tcg_gen_muls2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
+ } else {
+ tcg_gen_mulu2_i32(QREG_CC_Z, QREG_CC_N, src1, DREG(ext, 12));
+ }
+ /* if Dl == Dh, 68040 returns low word */
+ tcg_gen_mov_i32(DREG(ext, 0), QREG_CC_N);
+ tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_Z);
+ tcg_gen_or_i32(QREG_CC_Z, QREG_CC_Z, QREG_CC_N);
+
+ tcg_gen_movi_i32(QREG_CC_V, 0);
+ tcg_gen_movi_i32(QREG_CC_C, 0);
+
+ set_cc_op(s, CC_OP_FLAGS);
return;
}
- reg = DREG(ext, 12);
SRC_EA(env, src1, OS_LONG, 0, NULL);
- dest = tcg_temp_new();
- tcg_gen_mul_i32(dest, src1, reg);
- tcg_gen_mov_i32(reg, dest);
- /* Unlike m68k, coldfire always clears the overflow bit. */
- gen_logic_cc(s, dest, OS_LONG);
+ if (m68k_feature(s->env, M68K_FEATURE_M68000)) {
+ tcg_gen_movi_i32(QREG_CC_C, 0);
+ if (sign) {
+ tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
+ /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */
+ tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31);
+ tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z);
+ } else {
+ tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12));
+ /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */
+ tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C);
+ }
+ tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
+ tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N);
+
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+
+ set_cc_op(s, CC_OP_FLAGS);
+ } else {
+ /* The upper 32 bits of the product are discarded, so
+ muls.l and mulu.l are functionally equivalent. */
+ tcg_gen_mul_i32(DREG(ext, 12), src1, DREG(ext, 12));
+ gen_logic_cc(s, DREG(ext, 12), OS_LONG);
+ }
}
static void gen_link(DisasContext *s, uint16_t insn, int32_t offset)
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Qemu-devel] [PATCH v4 2/2] target-m68k: add 680x0 divu/divs variants
2016-11-01 20:03 [Qemu-devel] [PATCH v4 0/2] 680x0 mul and div instructions Laurent Vivier
2016-11-01 20:03 ` [Qemu-devel] [PATCH v4 1/2] target-m68k: add 64bit mull Laurent Vivier
@ 2016-11-01 20:03 ` Laurent Vivier
2016-11-01 20:49 ` Richard Henderson
` (2 more replies)
1 sibling, 3 replies; 7+ messages in thread
From: Laurent Vivier @ 2016-11-01 20:03 UTC (permalink / raw)
To: qemu-devel; +Cc: schwab, agraf, Richard Henderson, gerg, Laurent Vivier
Update helper to set the throwing location in case of div-by-0.
Cleanup divX.w and add quad word variants of divX.l.
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
---
linux-user/main.c | 7 ++
target-m68k/cpu.h | 4 --
target-m68k/helper.h | 8 ++-
target-m68k/op_helper.c | 182 +++++++++++++++++++++++++++++++++++++++++-------
target-m68k/qregs.def | 2 -
target-m68k/translate.c | 84 ++++++++++++----------
6 files changed, 217 insertions(+), 70 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 75b199f..c1d5eb4 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -2864,6 +2864,13 @@ void cpu_loop(CPUM68KState *env)
info._sifields._sigfault._addr = env->pc;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
break;
+ case EXCP_DIV0:
+ info.si_signo = TARGET_SIGFPE;
+ info.si_errno = 0;
+ info.si_code = TARGET_FPE_INTDIV;
+ info._sifields._sigfault._addr = env->pc;
+ queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+ break;
case EXCP_TRAP0:
{
abi_long ret;
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 6dfb54e..0b4ed7b 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -95,10 +95,6 @@ typedef struct CPUM68KState {
uint32_t macsr;
uint32_t mac_mask;
- /* Temporary storage for DIV helpers. */
- uint32_t div1;
- uint32_t div2;
-
/* MMU status. */
struct {
uint32_t ar;
diff --git a/target-m68k/helper.h b/target-m68k/helper.h
index aae01f9..d863e55 100644
--- a/target-m68k/helper.h
+++ b/target-m68k/helper.h
@@ -1,8 +1,12 @@
DEF_HELPER_1(bitrev, i32, i32)
DEF_HELPER_1(ff1, i32, i32)
DEF_HELPER_FLAGS_2(sats, TCG_CALL_NO_RWG_SE, i32, i32, i32)
-DEF_HELPER_2(divu, void, env, i32)
-DEF_HELPER_2(divs, void, env, i32)
+DEF_HELPER_3(divuw, void, env, int, i32)
+DEF_HELPER_3(divsw, void, env, int, s32)
+DEF_HELPER_4(divul, void, env, int, int, i32)
+DEF_HELPER_4(divsl, void, env, int, int, s32)
+DEF_HELPER_4(divull, void, env, int, int, i32)
+DEF_HELPER_4(divsll, void, env, int, int, s32)
DEF_HELPER_2(set_sr, void, env, i32)
DEF_HELPER_3(movec, void, env, i32, i32)
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 48e02e4..a4bfa4e 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -166,12 +166,17 @@ bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
return false;
}
-static void raise_exception(CPUM68KState *env, int tt)
+static void raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
{
CPUState *cs = CPU(m68k_env_get_cpu(env));
cs->exception_index = tt;
- cpu_loop_exit(cs);
+ cpu_loop_exit_restore(cs, raddr);
+}
+
+static void raise_exception(CPUM68KState *env, int tt)
+{
+ raise_exception_ra(env, tt, 0);
}
void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt)
@@ -179,51 +184,178 @@ void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt)
raise_exception(env, tt);
}
-void HELPER(divu)(CPUM68KState *env, uint32_t word)
+void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den)
{
- uint32_t num;
- uint32_t den;
- uint32_t quot;
- uint32_t rem;
+ uint32_t num = env->dregs[destr];
+ uint32_t quot, rem;
- num = env->div1;
- den = env->div2;
- /* ??? This needs to make sure the throwing location is accurate. */
if (den == 0) {
- raise_exception(env, EXCP_DIV0);
+ raise_exception_ra(env, EXCP_DIV0, GETPC());
}
quot = num / den;
rem = num % den;
- env->cc_v = (word && quot > 0xffff ? -1 : 0);
+ env->cc_c = 0; /* always cleared, even if overflow */
+ if (quot > 0xffff) {
+ env->cc_v = -1;
+ /* nothing else is modified */
+ /* real 68040 keeps Z and N on overflow,
+ * whereas documentation says "undefined"
+ */
+ return;
+ }
+ env->dregs[destr] = deposit32(quot, 16, 16, rem);
env->cc_z = quot;
env->cc_n = quot;
+ env->cc_v = 0;
+}
+
+void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den)
+{
+ int32_t num = env->dregs[destr];
+ uint32_t quot, rem;
+
+ if (den == 0) {
+ raise_exception_ra(env, EXCP_DIV0, GETPC());
+ }
+ quot = num / den;
+ rem = num % den;
+
+ env->cc_c = 0; /* always cleared, even if overflow */
+ if (quot != (int16_t)quot) {
+ env->cc_v = -1;
+ /* nothing else is modified */
+ /* real 68040 keeps Z and N on overflow,
+ * whereas documentation says "undefined"
+ */
+ return;
+ }
+ env->dregs[destr] = deposit32(quot, 16, 16, rem);
+ env->cc_z = quot;
+ env->cc_n = quot;
+ env->cc_v = 0;
+}
+
+void HELPER(divul)(CPUM68KState *env, int numr, int regr, uint32_t den)
+{
+ uint32_t num = env->dregs[numr];
+ uint32_t quot, rem;
+
+ if (den == 0) {
+ raise_exception_ra(env, EXCP_DIV0, GETPC());
+ }
+ quot = num / den;
+ rem = num % den;
+
env->cc_c = 0;
+ env->cc_z = quot;
+ env->cc_n = quot;
+ env->cc_v = 0;
- env->div1 = quot;
- env->div2 = rem;
+ if (m68k_feature(env, M68K_FEATURE_CF_ISA_A)) {
+ if (numr == regr) {
+ env->dregs[numr] = quot;
+ } else {
+ env->dregs[regr] = rem;
+ }
+ } else {
+ env->dregs[regr] = rem;
+ env->dregs[numr] = quot;
+ }
}
-void HELPER(divs)(CPUM68KState *env, uint32_t word)
+void HELPER(divsl)(CPUM68KState *env, int numr, int regr, int32_t den)
{
- int32_t num;
- int32_t den;
- int32_t quot;
+ int32_t num = env->dregs[numr];
+ int32_t quot, rem;
+
+ if (den == 0) {
+ raise_exception_ra(env, EXCP_DIV0, GETPC());
+ }
+ quot = num / den;
+ rem = num % den;
+
+ env->cc_c = 0;
+ env->cc_z = quot;
+ env->cc_n = quot;
+ env->cc_v = 0;
+
+ if (m68k_feature(env, M68K_FEATURE_CF_ISA_A)) {
+ if (numr == regr) {
+ env->dregs[numr] = quot;
+ } else {
+ env->dregs[regr] = rem;
+ }
+ } else {
+ env->dregs[regr] = rem;
+ env->dregs[numr] = quot;
+ }
+}
+
+void HELPER(divull)(CPUM68KState *env, int numr, int regr, uint32_t den)
+{
+ uint64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]);
+ uint64_t quot;
+ uint32_t rem;
+
+ if (den == 0) {
+ raise_exception_ra(env, EXCP_DIV0, GETPC());
+ }
+ quot = num / den;
+ rem = num % den;
+
+ env->cc_c = 0; /* always cleared, even if overflow */
+ if (quot > 0xffffffffULL) {
+ env->cc_v = -1;
+ /* nothing else is modified */
+ /* real 68040 keeps Z and N on overflow,
+ * whereas documentation says "undefined"
+ */
+ return;
+ }
+ env->cc_z = quot;
+ env->cc_n = quot;
+ env->cc_v = 0;
+
+ /*
+ * If Dq and Dr are the same, the quotient is returned.
+ * therefore we set Dq last.
+ */
+
+ env->dregs[regr] = rem;
+ env->dregs[numr] = quot;
+}
+
+void HELPER(divsll)(CPUM68KState *env, int numr, int regr, int32_t den)
+{
+ int64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]);
+ int64_t quot;
int32_t rem;
- num = env->div1;
- den = env->div2;
if (den == 0) {
- raise_exception(env, EXCP_DIV0);
+ raise_exception_ra(env, EXCP_DIV0, GETPC());
}
quot = num / den;
rem = num % den;
- env->cc_v = (word && quot != (int16_t)quot ? -1 : 0);
+ env->cc_c = 0; /* always cleared, even if overflow */
+ if (quot != (int32_t)quot) {
+ env->cc_v = -1;
+ /* nothing else is modified */
+ /* real 68040 keeps Z and N on overflow,
+ * whereas documentation says "undefined"
+ */
+ return;
+ }
env->cc_z = quot;
env->cc_n = quot;
- env->cc_c = 0;
+ env->cc_v = 0;
+
+ /*
+ * If Dq and Dr are the same, the quotient is returned.
+ * therefore we set Dq last.
+ */
- env->div1 = quot;
- env->div2 = rem;
+ env->dregs[regr] = rem;
+ env->dregs[numr] = quot;
}
diff --git a/target-m68k/qregs.def b/target-m68k/qregs.def
index 156c0f5..51ff43b 100644
--- a/target-m68k/qregs.def
+++ b/target-m68k/qregs.def
@@ -7,7 +7,5 @@ DEFO32(CC_C, cc_c)
DEFO32(CC_N, cc_n)
DEFO32(CC_V, cc_v)
DEFO32(CC_Z, cc_z)
-DEFO32(DIV1, div1)
-DEFO32(DIV2, div2)
DEFO32(MACSR, macsr)
DEFO32(MAC_MASK, mac_mask)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 61986cc..4f71b7d 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1191,64 +1191,74 @@ DISAS_INSN(mulw)
DISAS_INSN(divw)
{
- TCGv reg;
- TCGv tmp;
- TCGv src;
int sign;
+ TCGv src;
+ TCGv destr;
+
+ /* divX.w <EA>,Dn 32/16 -> 16r:16q */
sign = (insn & 0x100) != 0;
- reg = DREG(insn, 9);
- if (sign) {
- tcg_gen_ext16s_i32(QREG_DIV1, reg);
- } else {
- tcg_gen_ext16u_i32(QREG_DIV1, reg);
- }
+
+ /* dest.l / src.w */
+
SRC_EA(env, src, OS_WORD, sign, NULL);
- tcg_gen_mov_i32(QREG_DIV2, src);
+ destr = tcg_const_i32(REG(insn, 9));
if (sign) {
- gen_helper_divs(cpu_env, tcg_const_i32(1));
+ gen_helper_divsw(cpu_env, destr, src);
} else {
- gen_helper_divu(cpu_env, tcg_const_i32(1));
+ gen_helper_divuw(cpu_env, destr, src);
}
-
- tmp = tcg_temp_new();
- src = tcg_temp_new();
- tcg_gen_ext16u_i32(tmp, QREG_DIV1);
- tcg_gen_shli_i32(src, QREG_DIV2, 16);
- tcg_gen_or_i32(reg, tmp, src);
+ tcg_temp_free(destr);
set_cc_op(s, CC_OP_FLAGS);
}
DISAS_INSN(divl)
{
- TCGv num;
- TCGv den;
- TCGv reg;
+ TCGv num, reg, den;
+ int sign;
uint16_t ext;
ext = read_im16(env, s);
- if (ext & 0x87f8) {
- gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
+
+ sign = (ext & 0x0800) != 0;
+
+ if (ext & 0x400) {
+ if (!m68k_feature(s->env, M68K_FEATURE_QUAD_MULDIV)) {
+ gen_exception(s, s->insn_pc, EXCP_ILLEGAL);
+ return;
+ }
+
+ /* divX.l <EA>, Dr:Dq 64/32 -> 32r:32q */
+
+ SRC_EA(env, den, OS_LONG, 0, NULL);
+ num = tcg_const_i32(REG(ext, 12));
+ reg = tcg_const_i32(REG(ext, 0));
+ if (sign) {
+ gen_helper_divsll(cpu_env, num, reg, den);
+ } else {
+ gen_helper_divull(cpu_env, num, reg, den);
+ }
+ tcg_temp_free(reg);
+ tcg_temp_free(num);
+ set_cc_op(s, CC_OP_FLAGS);
return;
}
- num = DREG(ext, 12);
- reg = DREG(ext, 0);
- tcg_gen_mov_i32(QREG_DIV1, num);
+
+ /* divX.l <EA>, Dq 32/32 -> 32q */
+ /* divXl.l <EA>, Dr:Dq 32/32 -> 32r:32q */
+
SRC_EA(env, den, OS_LONG, 0, NULL);
- tcg_gen_mov_i32(QREG_DIV2, den);
- if (ext & 0x0800) {
- gen_helper_divs(cpu_env, tcg_const_i32(0));
- } else {
- gen_helper_divu(cpu_env, tcg_const_i32(0));
- }
- if ((ext & 7) == ((ext >> 12) & 7)) {
- /* div */
- tcg_gen_mov_i32 (reg, QREG_DIV1);
+ num = tcg_const_i32(REG(ext, 12));
+ reg = tcg_const_i32(REG(ext, 0));
+ if (sign) {
+ gen_helper_divsl(cpu_env, num, reg, den);
} else {
- /* rem */
- tcg_gen_mov_i32 (reg, QREG_DIV2);
+ gen_helper_divul(cpu_env, num, reg, den);
}
+ tcg_temp_free(reg);
+ tcg_temp_free(num);
+
set_cc_op(s, CC_OP_FLAGS);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/2] target-m68k: add 680x0 divu/divs variants
2016-11-01 20:03 ` [Qemu-devel] [PATCH v4 2/2] target-m68k: add 680x0 divu/divs variants Laurent Vivier
@ 2016-11-01 20:49 ` Richard Henderson
2016-11-27 17:42 ` Laurent Vivier
2016-11-27 19:41 ` Laurent Vivier
2 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2016-11-01 20:49 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel; +Cc: schwab, agraf, gerg
On 11/01/2016 02:03 PM, Laurent Vivier wrote:
> Update helper to set the throwing location in case of div-by-0.
> Cleanup divX.w and add quad word variants of divX.l.
>
> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
> ---
> linux-user/main.c | 7 ++
> target-m68k/cpu.h | 4 --
> target-m68k/helper.h | 8 ++-
> target-m68k/op_helper.c | 182 +++++++++++++++++++++++++++++++++++++++++-------
> target-m68k/qregs.def | 2 -
> target-m68k/translate.c | 84 ++++++++++++----------
> 6 files changed, 217 insertions(+), 70 deletions(-)
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/2] target-m68k: add 680x0 divu/divs variants
2016-11-01 20:03 ` [Qemu-devel] [PATCH v4 2/2] target-m68k: add 680x0 divu/divs variants Laurent Vivier
2016-11-01 20:49 ` Richard Henderson
@ 2016-11-27 17:42 ` Laurent Vivier
2016-11-27 17:59 ` Richard Henderson
2016-11-27 19:41 ` Laurent Vivier
2 siblings, 1 reply; 7+ messages in thread
From: Laurent Vivier @ 2016-11-27 17:42 UTC (permalink / raw)
To: qemu-devel; +Cc: Richard Henderson
Hi,
I come back on some patches as I've been able to test some instructions
using RISU.
Le 01/11/2016 à 21:03, Laurent Vivier a écrit :
...
> --- a/target-m68k/op_helper.c
> +++ b/target-m68k/op_helper.c
> @@ -179,51 +184,178 @@ void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt)
> raise_exception(env, tt);
> }
>
> -void HELPER(divu)(CPUM68KState *env, uint32_t word)
> +void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den)
> {
> - uint32_t num;
> - uint32_t den;
> - uint32_t quot;
> - uint32_t rem;
> + uint32_t num = env->dregs[destr];
> + uint32_t quot, rem;
>
> - num = env->div1;
> - den = env->div2;
> - /* ??? This needs to make sure the throwing location is accurate. */
> if (den == 0) {
> - raise_exception(env, EXCP_DIV0);
> + raise_exception_ra(env, EXCP_DIV0, GETPC());
> }
> quot = num / den;
> rem = num % den;
>
> - env->cc_v = (word && quot > 0xffff ? -1 : 0);
> + env->cc_c = 0; /* always cleared, even if overflow */
> + if (quot > 0xffff) {
> + env->cc_v = -1;
> + /* nothing else is modified */
> + /* real 68040 keeps Z and N on overflow,
> + * whereas documentation says "undefined"
> + */
> + return;
> + }
> + env->dregs[destr] = deposit32(quot, 16, 16, rem);
> env->cc_z = quot;
> env->cc_n = quot;
quot is here a 32bit, but the result is only the 16 lower bits, so I
think we should have
env->cc_z = (int16_t)quot;
env->cc_n = (int16_t)quot;
> + env->cc_v = 0;
> +}
> +
> +void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den)
> +{
> + int32_t num = env->dregs[destr];
> + uint32_t quot, rem;
> +
> + if (den == 0) {
> + raise_exception_ra(env, EXCP_DIV0, GETPC());
> + }
> + quot = num / den;
> + rem = num % den;
> +
> + env->cc_c = 0; /* always cleared, even if overflow */
> + if (quot != (int16_t)quot) {
> + env->cc_v = -1;
> + /* nothing else is modified */
> + /* real 68040 keeps Z and N on overflow,
> + * whereas documentation says "undefined"
> + */
> + return;
> + }
> + env->dregs[destr] = deposit32(quot, 16, 16, rem);
> + env->cc_z = quot;
> + env->cc_n = quot;
Same here:
env->cc_z = (int16_t)quot;
env->cc_n = (int16_t)quot;
Thanks,
Laurent
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/2] target-m68k: add 680x0 divu/divs variants
2016-11-27 17:42 ` Laurent Vivier
@ 2016-11-27 17:59 ` Richard Henderson
0 siblings, 0 replies; 7+ messages in thread
From: Richard Henderson @ 2016-11-27 17:59 UTC (permalink / raw)
To: Laurent Vivier, qemu-devel
On 11/27/2016 09:42 AM, Laurent Vivier wrote:
>> > + env->dregs[destr] = deposit32(quot, 16, 16, rem);
>> > env->cc_z = quot;
>> > env->cc_n = quot;
> quot is here a 32bit, but the result is only the 16 lower bits, so I
> think we should have
>
> env->cc_z = (int16_t)quot;
> env->cc_n = (int16_t)quot;
>
Yep, you're right.
r~
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/2] target-m68k: add 680x0 divu/divs variants
2016-11-01 20:03 ` [Qemu-devel] [PATCH v4 2/2] target-m68k: add 680x0 divu/divs variants Laurent Vivier
2016-11-01 20:49 ` Richard Henderson
2016-11-27 17:42 ` Laurent Vivier
@ 2016-11-27 19:41 ` Laurent Vivier
2 siblings, 0 replies; 7+ messages in thread
From: Laurent Vivier @ 2016-11-27 19:41 UTC (permalink / raw)
To: qemu-devel; +Cc: gerg, schwab, agraf, Richard Henderson
Le 01/11/2016 à 21:03, Laurent Vivier a écrit :
> diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
> index 48e02e4..a4bfa4e 100644
> +void HELPER(divull)(CPUM68KState *env, int numr, int regr, uint32_t den)
> +{
> + uint64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]);
> + uint64_t quot;
> + uint32_t rem;
> +
> + if (den == 0) {
> + raise_exception_ra(env, EXCP_DIV0, GETPC());
> + }
> + quot = num / den;
> + rem = num % den;
> +
> + env->cc_c = 0; /* always cleared, even if overflow */
> + if (quot > 0xffffffffULL) {
> + env->cc_v = -1;
> + /* nothing else is modified */
> + /* real 68040 keeps Z and N on overflow,
> + * whereas documentation says "undefined"
> + */
> + return;
> + }
...
> +
> +void HELPER(divsll)(CPUM68KState *env, int numr, int regr, int32_t den)
> +{
> + int64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]);
> + int64_t quot;
> int32_t rem;
>
> - num = env->div1;
> - den = env->div2;
> if (den == 0) {
> - raise_exception(env, EXCP_DIV0);
> + raise_exception_ra(env, EXCP_DIV0, GETPC());
> }
> quot = num / den;
> rem = num % den;
>
> - env->cc_v = (word && quot != (int16_t)quot ? -1 : 0);
> + env->cc_c = 0; /* always cleared, even if overflow */
> + if (quot != (int32_t)quot) {
> + env->cc_v = -1;
> + /* nothing else is modified */
> + /* real 68040 keeps Z and N on overflow,
> + * whereas documentation says "undefined"
> + */
> + return;
> + }
On a real 68040, for divsll and divull, Z is unset.
(while divsw/divuw don't modify it as we do).
So I will update the patch with this behavior.
Laurent
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-11-27 19:41 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-11-01 20:03 [Qemu-devel] [PATCH v4 0/2] 680x0 mul and div instructions Laurent Vivier
2016-11-01 20:03 ` [Qemu-devel] [PATCH v4 1/2] target-m68k: add 64bit mull Laurent Vivier
2016-11-01 20:03 ` [Qemu-devel] [PATCH v4 2/2] target-m68k: add 680x0 divu/divs variants Laurent Vivier
2016-11-01 20:49 ` Richard Henderson
2016-11-27 17:42 ` Laurent Vivier
2016-11-27 17:59 ` Richard Henderson
2016-11-27 19:41 ` Laurent Vivier
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